Creating and Instantiating a Verilog HDL Function for Use with the Synplify Software

You can create or modify design files that contain custom IP core variations of provided functions. You can then instantiate the custom IP variations in a design file for use with the Synopsys® Synplify and Quartus® Prime software. This procedure shows only how to instantiate a PLL function using Verilog HDL; however, you can use similar procedures to instantiate other provided functions.

  1. If you have not already done so, set up the Synplify Working environment.
  2. If you have not already done so, create a design for use with the Synplify software.
  3. Open the IP Catalog and specify appropriate options for the IP core you want to instantiate.
  4. To prepare the Verilog HDL design for synthesis with the Synplify software, you must specify that the Synplify software should treat the design file created in the paremeter editor as a "black box." The Synplify software then makes the correct connections to the ports in the Verilog HDL output netlist file (.vqm). The Quartus® Prime software reads in the Verilog HDL netlist file as a Verilog Quartus Mapping File (.vqm) Definition and processes the instantiated Intel® FPGA IP. The paramter editor also generates a file with the extension _bb.v that can be used as an empty module declaration for use as a black box. To specify that the Synplify software should treat the design file for the Intel® FPGA IP as a "black box," refer to the following example:
  5. If necessary, perform a functional simulation of the design using an EDA simulation tool.
  6. Generate Verilog Quartus mapping files with the Synplify software.
  7. If you have not already done so, create a new project or open an existing project.
  8. Compile the design in the Quartus® Prime software.