Compiling Intel FPGA simulation model files

Before simulating an Intel FPGA design, you must compile Intel FPGA simulation model files.

To compile Intel FPGA simulation models, use any of the following methods

• Compile simulation models manually with your simulator, according to the simulator vendor documentation.
• Compile all required libraries at once with the EDA Simulation Library Compiler. You can perform this task interactively, or using a command line argument.
  Note: Once the simulation model compilation starts, the compilation may require from 15 minutes to a full hour, depending on your system. Although the compilation messages may appear paused or incomplete, the compilation is still running correctly.
• Enable Tools > Launch Simulation Library Compiler > Settings > Compatible Mode for Quartus Simulation Flow to use precompiled simulation libraries after one-time compilation. This technique reduces the compilation time and use of computing resources by using precompiled simulation libraries, rather than compiling the same device libraries every time you compile simulation sources of the project or IP. Precompiled simulation libraries allow you to compile the device library once, and then reuse the precompiled library across multiple projects or with the same target device family.
  Note: When you enable this option, the Simulation Library Compiler generates separate tile-specific variants of libraries, rather than merging all libraries into one. This method is specifically useful when working with Quartus Prime- or Platform Designer-generated simulation scripts.