TMC-20208: RAM Blocks with Unregistered Outputs that are the Source of Paths Failing Setup Analysis
Description
Violations of this rule identify RAM blocks with unregistered outputs that are source nodes of paths that fail setup analysis. Registering RAM outputs can significantly improve RAM's μtco.
Parameters
| Name | Description | Type | Default Value | Min Value | Max Value |
|---|---|---|---|---|---|
| maximum_setup_slack | Reports a violation for timing paths that have a setup slack below the value of this parameter. | double | 0.0 | ||
| to_clock_filter | Reports a violation for timing paths that end at a register in a clock domain that matches the value of this parameter. | string | * | ||
| minimum_number_of_adders | Reports a violation for timing endpoints that are preceded by a number of independent adder chains greater than or equal to this value. | integer | 3 | ||
| minimum_number_of_soft_mult_chains | Reports a violation for timing endpoints that are preceded by a number of independent adder chains that are implementing multiplier logic greater than or equal to this value. | integer | 2 |
Recommendation
Review the Fitter report 'RAM Summary'. Next, register RAM output to improve μtco by adding 1 additional pipeline to the design's RAM output path.
Severity
Medium
Tags
| Tag | Description |
|---|---|
| ram | Design rule checks related to M20k blocks inside the FPGA fabric. |
Device Family
- Intel®Stratix® 10
- Intel Agilex®
- Intel Agilex®
- Intel Agilex®
- Intel®Arria® 10
- Intel®Cyclone® 10 GX