CLK-30030: PLL Setting Violation

Description

Violations of this rule identify PLL nodes that have inconsistent settings between the clock assigned and the PLL settings.

Recommendation

Modify the clock assignment to match PLL settings.

Severity

High

Tags

Tag Description
sdc Design rule checks related to SDC validity checking.

Device Family

  • Intel®Cyclone® 10 GX
  • Intel®Arria® 10
  • Intel®Stratix® 10
  • Intel Agilex®
  • Intel Agilex®