Early Place Stage Reports

During Early Place the Fitter begins assigning core design logic to device resources. For Intel® Stratix® 10 designs, the Early Place stage reports include the Global & Other Fast Signals Summary and Global & Other Fast Signals Details reports. Use these reports to verify which clocks the Compiler promotes to global clocks. Clock planning occurs after the Plan stage for Intel® Arria® 10 and Intel® Cyclone® 10 designs.
Figure 1. Early Place Stage Reports (Intel® Stratix® 10 Design)