The HDMI Intel® FPGA intellectual property (IP) core provides support for the next generation of video display interface technology. Due to its ability to send high-definition audio and video, High-Definition Multimedia Interface (HDMI) has become the most common digital connection in consumer electronics.
The HDMI cable and connectors carry four differential pairs that are composed of three Transition-minimized Differential Signaling (TMDS) data channels and one clock channel in HDMI 2.0 or four Fixed Rate Link (FRL) data channels in HDMI 2.1. You can use these channels to carry video, audio, and auxiliary data at a raw bit rate of up to 3.4/6/8/10/12 Gbps per channel. HDCP-encrypted transmission can also be integrated into our IP through the newly released Intel® FPGA HDCP core.
HDMI 2.0 Demonstration
This video demonstrates 4Kp60 resolution display using our HDMI IP core on the Stratix® V GX FPGA Development Kit.
In this demonstration we will be showing the new 8K UDX10 reference design for Intel® Arria® 10 FPGAs, featuring new HDMI 2.1 IP as well as the 8K ready Intel® FPGA Video and Image Processing Suite IP, which contains more than 20 video processing functions that allow you to build a customized video pipeline.
In this demo, we will show you a new solution for High-Bandwidth Digital Content Protection using Intel® FPGAs that are compatible with HDMI and DisplayPort solutions and can be used to receive, transmit or repeat HDCP content.