MAX® 10 Nios® II Embedded Evaluation Kit

The MAX® 10 Nios® II Embedded Evaluation Kit (NEEK) from Terasic is a full featured embedded evaluation kit based upon the Intel® MAX 10 family of FPGAs. It is a comprehensive design environment with everything embedded developers need to create a processing-based system. The MAX 10 NEEK delivers an integrated platform that includes hardware, design tools, intellectual property (IP), and reference designs for developing a wide range of applications.

The fully integrated kit allows developers to rapidly customize their processor and IP to suit their specific needs, rather than constraining their software around the fixed feature set of the processor.

The kit features a capacitive LCD multimedia color touch panel, which natively supports multi-touch gestures. An eight megapixel digital image sensor, ambient light sensor, and three-axis accelerometer make up this rich feature set, along with a variety of interfaces connecting the MAX 10 NEEK to the outside for Internet of Things (IoT) applications across markets.

The MAX 10 NEEK has been designed to meet the performance and power requirements for applications such as:

  • Embedded processing applications
  • Multimedia applications
  • Human machine interface development
  • Video display applications

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Demonstration Designs Include

  • Robotic control via Bluetooth (Terasic Pmod* Compatible module not included)
  • MIPI camera
  • G sensor
  • Humidity and temperature sensor
  • ADC and MIC
  • Painter
  • HDMI Rx
  • and many more 

Design examples include the source code and design files. This is a great way to see examples of software drivers for various hardware peripheral on your board. These may be downloaded from either the Design Store  or Terasic website.

With this kit, you can:

  • Evaluate various processor options and configurations using a soft Nios II processor
  • Begin development of your hardware and software design early, testing out proof of concept easily
  • Use as a platform for target reference designs, OS/BSP, and tools
  • Nios II processor supports various operating systems, full details may be found on the Nios II Ecosystem web page
Figure 1. MAX 10 NEEK Touch Screen
Figure 3. MAX 10 NEEK Board

Ordering Information

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This development kit features a 10M50DAF484-6 device, order via the e-store or contact your local Terasic distributor to place your order.

Intellectual Property

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This IP suite includes all the IP you need to ship a standard Nios II processor design. Upgrade your kit with this perpetual-use, royalty-free license bundle for embedded design.

  • Nios II processor
  • Triple-Speed Ethernet MegaCore® function
  • DDR2 and DDR3 high-performance memory controllers
  • 16650 UART

IP licenses are sold separately. You may still install and start designing with any Intel FPGA IP core via the OpenCore Plus (PDF) simulation and hardware evaluation feature

Development Kit Contents

Hardware Software2
  • MAX 10 10M50DAF484C6GES
    • 50 K logic elements (LEs)
    • Integrated dual 12 bit analog-to-digital converter (ADC)
    • Four analogue phase-locked loops (PLLs)
  • Programming and configuration
    • Embedded Intel FPGA DownIoad Cable II (JTAG)
    • Optional JTAG direct via 10-pin header
  • Memory devices
    • 64 M x 16 1 Gb DDR3 SDRAM via soft memory controller
    • 128 M x 8 1 Gb DDR3 SDRAM via soft memory controller
    • 512 Mb quad serial peripheral interface (SPI) flash memory
  • Communications interfaces
    • USB 2.0 PHY interface
    • Gigabit Ethernet (GbE) RJ-45 port
    • Micro SD flash memory card
    • Digilent Pmod* Compatible connector
  • Analogue interface
    • 2X SMA analogue inputs, 0-2.5 V
    • 1X SMA DAC output, 0-2.5 V
    • 2X ten ways ADC input header
    • Potentiometer input to ADC
  • Buttons, switches, LEDs, and so on
    • FPGA reset button - default logic reset to FPGA core
    • Configuration image select switch
    • 5X user pushbuttons
    • 10X user slide switches
    • 10X user LEDs
    • Two seven- segment displays
  • Miscellaneous interfaces
    • PS2
  • Capacitive LCD touch screen
    • 800x480 colour LCD, equipped with a 7 inch amorphous TFT-LCD module
    • Five-point  multitouch screen
  • Video in
    • Eight megapixel, MIPI CSI-2 colour camera input
    • High-deifinition multimedia interface (HDMI) video input
  • Audio
    • 24 bit CD quality audio coded with mic-in, line-in, line out jacks
  • Sensors
    • Humidity and temperature sensor
    • Ambient light sensor
    • Accelerometer
    • Power monitor
  • Clocking for users
    • 1X 10 MHz single ended, external oscillator clock source
    • 1X 25 MHz single ended, external oscillator clock source
    • 3X 50 MHz single ended,external oscillator clock source
  • Mini USB cable for on board Intel FPGA Download Cable II
  • 5 V/3 A power supply and cord
  • Golden System Reference Design
  • MAX 10 NEEK Development Kit User Manual
  • Development Kit design files (BOM, schematics, layout)
  • Nios II  (IDE)  Integrated Design Environment
  • Intel Quartus® Prime web software (supported)
  • Nios II processor (optional)
  • MegaCore IP library (optional)