ECC Handling Issues on Intel ® XScale I/O Processors

ECC Handling Issues on Intel XScale® I/O Processors: Note

Overview
This document presents ECC-protected memory information specific to the Intel XScale® I/O processors and focuses on:
• Interactions of 80200 Bus Control Unit (BCU) and Memory Control Unit (MCU) as it relates to ECC on Intel XScale® I/O processors, including:
— recommended setup
— ECC transaction management and reporting
— transaction timing/completion considerations
— ECC, performance impact and error handling.
• 80310-specific issues regarding Intel XScale® technology core memory writes to ECC enabled memory regions.

Note: The 80303 is an i960-based IOP processor, so it operates slightly differently than the Intel XScale® processor.

ECC Functionality in the IOP
The I/O processor is a single functional device that integrates the Intel XScale® processor with an MCU and intelligent peripherals.

Discrete ECC values are calculated and stored in memory by the MCU on each 64-bit bus width memory write. ECC stored values are recomputed and compared with stored ECC values for accuracy by the MCU and/or BCU (80310 only) on each bus 64-bit bus read.

Read the full ECC Handling Issues on Intel XScale® I/O Processors Application Note.