// Copyright (C) 2007 - Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // disable it for now as tx_pma model has problem with it `ifdef MODEL_TECH `mti_v2k_int_delays_on `endif /////////////////////////////////////////////////////////////////////////////// // // // Containing Verilog Model for the Atoms: // // // // stratixiv_hssi_pll // // stratixiv_hssi_clock_divider // // stratixiv_hssi_rx_pma // // stratixiv_hssi_tx_pma // // stratixiv_hssi_tx_pcs // // stratixiv_hssi_rx_pcs // // stratixiv_hssi_cmu // // stratixiv_hssi_calibration_block // // stratixiv_hssi_refclk_divider // // // /////////////////////////////////////////////////////////////////////////////// `timescale 1 ps / 1 ps module stratixiv_hssi_aux_clock_div ( clk, // input clock reset, // reset enable_d, // enable DPRIO d, // division factor for DPRIO support clkout // divided clock ); input clk,reset; input enable_d; input [7:0] d; output clkout; parameter clk_divide_by = 1; parameter extra_latency = 0; integer clk_edges,m; reg [2*extra_latency:0] div_n_register; reg [7:0] d_factor_dly; reg [31:0] clk_divide_value; wire [7:0] d_factor; wire int_reset; initial begin div_n_register = 'b0; clk_edges = -1; m = 0; d_factor_dly = 'b0; clk_divide_value = clk_divide_by; end assign d_factor = (enable_d === 1'b1) ? d : clk_divide_value[7:0]; always @(d_factor) begin d_factor_dly <= d_factor; end // create a reset pulse when there is a change in the d_factor value assign int_reset = (d_factor !== d_factor_dly) ? 1'b1 : 1'b0; always @(posedge clk or negedge clk or posedge reset or posedge int_reset) begin div_n_register <= {div_n_register, div_n_register[0]}; if ((reset === 1'b1) || (int_reset === 1'b1)) begin clk_edges = -1; div_n_register <= 'b0; end else begin if (clk_edges == -1) begin div_n_register[0] <= clk; if (clk == 1'b1) clk_edges = 0; end else if (clk_edges % d_factor == 0) div_n_register[0] <= ~div_n_register[0]; if (clk_edges >= 0 || clk == 1'b1) clk_edges = (clk_edges + 1) % (2*d_factor) ; end end assign clkout = div_n_register[2*extra_latency]; endmodule `timescale 1 ps / 1 ps module stratixiv_hssi_aux_clock_mult ( clk, // input clock fbclk, // feedback clock adjust, // adjust frequency adjust_without_lol, reset, // reset enable_m, // enable DPRIO m, // multiplication factor for DPRIO support clkout, // multiplied clock busy // state ); input clk,fbclk,adjust,reset; input adjust_without_lol; input enable_m; input [7:0] m; output[3:0] clkout; output [1:0] busy; parameter clk_multiply_by = 1; parameter pfd_fb_select = "internal"; `define HSSI_CLOCK_MULT_INITIAL 2'b01 `define HSSI_CLOCK_MULT_ACTIVE 2'b11 `define HSSI_CLOCK_MULT_INACTIVE 2'b00 integer clk_adjust; integer clk_adjust_interval; integer clk_adjust_running; integer clk_fast_period; integer clk_sync_period; integer n; integer phasedelay; integer phase_adjust; integer sched_time; real last_rising_edge,clk_period; real last_fb_rising_edge; reg [1:0] busy; reg clk_adjust_settled; reg mult_n; reg [3:0] clkout_reg; reg [31:0] clk_multiply_value; reg fb_select; reg current_mult_val; wire [7:0] m_factor; initial begin clk_multiply_value = clk_multiply_by; end assign m_factor = (enable_m === 1'b1) ? m : clk_multiply_value[7:0]; // At start of reconfiguration, set multiplier to reset state always @(m_factor) begin busy = `HSSI_CLOCK_MULT_INITIAL; last_rising_edge = 0; last_fb_rising_edge = 0; mult_n = 'b0; n = 0; end initial begin busy = `HSSI_CLOCK_MULT_INITIAL; last_rising_edge = 0; last_fb_rising_edge = 0; mult_n = 'b0; n = 0; fb_select = alpha_tolower(pfd_fb_select) == "iqtxrxclk" ? 1'b1 : 1'b0; end always @(posedge fbclk) last_fb_rising_edge <= $realtime; always @(posedge adjust) busy = `HSSI_CLOCK_MULT_INITIAL; always @(posedge clk or posedge reset) begin if (reset === 1'b1) begin mult_n = 1'b0; busy = `HSSI_CLOCK_MULT_INITIAL; end else begin if (fb_select == 1'b0) begin if (busy == `HSSI_CLOCK_MULT_INITIAL && adjust_without_lol == 1'b0) // first rising edge begin mult_n = 1'b0; last_rising_edge = $realtime; busy = `HSSI_CLOCK_MULT_ACTIVE; end else begin last_rising_edge <= $realtime; if (busy == `HSSI_CLOCK_MULT_INITIAL && adjust_without_lol == 1'b1) begin mult_n = 1'b0; busy = `HSSI_CLOCK_MULT_ACTIVE; end if (busy == `HSSI_CLOCK_MULT_ACTIVE) // second rising edge begin clk_period = $realtime - last_rising_edge; clk_fast_period = clk_period/m_factor - 0.5; clk_adjust = clk_period - clk_fast_period * m_factor; busy = `HSSI_CLOCK_MULT_INACTIVE; end current_mult_val = mult_n; mult_n <= ~mult_n; if (clk_adjust > 0) clk_adjust_running = clk_adjust + 1; clk_adjust_settled = (clk_adjust == 0); // if no adjustment necessary sched_time = 0; for (n = m_factor; n >= 1 ; n=n-1) begin if (clk_adjust_settled == 1'b0) begin clk_adjust_running = clk_adjust_running - 1; clk_adjust_interval = n/clk_adjust_running; if (n % clk_adjust_running == 0) clk_adjust_settled = 1'b1; clk_sync_period = clk_fast_period + 1; end else begin if (clk_adjust == 0) clk_sync_period = clk_fast_period; else begin if (n % clk_adjust_interval == 0) clk_sync_period = clk_fast_period + 1; else clk_sync_period = clk_fast_period; end end if (reset == 1'b1) mult_n <= 1'b0; else begin sched_time = sched_time + clk_sync_period/2; mult_n <= #sched_time current_mult_val; sched_time = sched_time + clk_sync_period - clk_sync_period/2; if (n > 1) mult_n <= #sched_time ~current_mult_val; end end end end else begin if (busy == `HSSI_CLOCK_MULT_INITIAL && adjust_without_lol == 1'b0) // first rising edge begin mult_n = 1'b0; last_rising_edge = $realtime; busy = `HSSI_CLOCK_MULT_ACTIVE; end else begin last_rising_edge <= $realtime; if (busy == `HSSI_CLOCK_MULT_INITIAL && adjust_without_lol == 1'b1) begin mult_n = 1'b0; busy = `HSSI_CLOCK_MULT_ACTIVE; end if (busy == `HSSI_CLOCK_MULT_ACTIVE) // second rising edge begin clk_period = $realtime - last_rising_edge; phase_adjust = $realtime - last_fb_rising_edge; if (phase_adjust >= clk_period) phase_adjust = 0; clk_fast_period = clk_period/m_factor - 0.5; clk_adjust = clk_period - clk_fast_period * m_factor; if ((phase_adjust == 0) && (last_fb_rising_edge == last_rising_edge)) busy = `HSSI_CLOCK_MULT_INACTIVE; end current_mult_val = mult_n; mult_n <= ~mult_n; if (clk_adjust > 0) clk_adjust_running = clk_adjust + 1; // if no adjustment necessary clk_adjust_settled = (clk_adjust == 0); sched_time = 0; for (n = m_factor; n >= 1 ; n=n-1) begin if (clk_adjust_settled == 1'b0) begin clk_adjust_running = clk_adjust_running - 1; clk_adjust_interval = n/clk_adjust_running; if (n % clk_adjust_running == 0) clk_adjust_settled = 1'b1; clk_sync_period = clk_fast_period + 1; end else begin if (clk_adjust == 0) clk_sync_period = clk_fast_period; else begin if (n % clk_adjust_interval == 0) clk_sync_period = clk_fast_period + 1; else clk_sync_period = clk_fast_period; end end if (reset == 1'b1) mult_n <= 1'b0; else begin sched_time = sched_time + clk_sync_period/2; mult_n <= #sched_time current_mult_val; sched_time = sched_time + clk_sync_period - clk_sync_period/2; if (n > 1) mult_n <= #sched_time ~current_mult_val; end end end end end end //Generate four clkout with equally distributed phase always @(mult_n) begin if (fb_select == 1'b1) clkout_reg[0] <= #(phase_adjust) mult_n; else clkout_reg[0] <= mult_n; end always @(posedge clkout[0]) begin phasedelay = clk_fast_period/4; end always @(clkout[0]) begin clkout_reg[1] <= #(phasedelay) clkout[0]; clkout_reg[2] <= ~clkout[0]; clkout_reg[3] <= #(phasedelay) ~clkout[0]; end assign clkout[0] = clkout_reg[0]; assign clkout[1] = clkout_reg[1]; assign clkout[2] = clkout_reg[2]; assign clkout[3] = clkout_reg[3]; endmodule `timescale 1 ps / 1 ps //------------------------------------------------------------------------------ // COPYRIGHT (c) 2007 ALTERA CORPORATION // ALL RIGHTS RESERVED //------------------------------------------------------------------------------ //====Revision Log================ //Rev: 1.9 Mon Mar 24 17:38:35 PDT 2008 cgaillar //Needed to enhance implementation for correct behavior if first clock edge after reset is a falling edge //====End Log====================== module stratixiv_hssi_pma_c_divby2q ( clk, clk0, clk90, clk180, clk270, clkb, rst_n, vcce_la, vssexqyx ); input clk; input clkb; input rst_n; input vcce_la; input vssexqyx; output clk0; output clk90; output clk180; output clk270; reg clk0, clk90, clk180, clk270, clk0_init; initial begin clk0_init = 1'b0; clk0 = 1'b1; clk90 = 1'b1; clk180 = 1'b1; clk270 = 1'b1; end always @ ( posedge clk or negedge rst_n ) if ( rst_n == 1'b0 ) begin clk0_init <= 1'b0; clk0 <= 1'b1; clk180 <= 1'b1; end else begin clk0_init <= 1'b1; clk0 <= ~clk0; clk180 <= clk0; end always @ ( posedge clkb or negedge rst_n ) if ( rst_n == 1'b0 ) begin clk90 <= 1'b1; clk270 <= 1'b1; end else begin if ( clk0_init == 1'b1 ) begin clk90 <= ~clk90; clk270 <= clk90; end end endmodule // stratixiv_hssi_pma_c_divby2q //====Revision Log================ //Rev: 1.1 Tue Sep 2 10:24:11 PDT 2008 cgaillar //Initial C5 version // //Rev: 1.3 Fri Oct 26 14:16:46 PDT 2007 cgaillar //Commented-out/removed timescale //====End Log====================== module stratixiv_hssi_pma_c_controller_4t16 ( atben, ct0, ct1, ct2, ct3, tmsb1, tmsb2, tmsb3, tmsb4, tmsb5, tmsb6, tmsb7, tmsb8, tmsb9, tmsb10, tmsb11, tmsb12, tmsb13, tmsb14, tmsb15, vcce_la, vssex ); input ct0; input ct1; input ct2; input ct3; input vcce_la; input vssex; output atben; output tmsb1; output tmsb2; output tmsb3; output tmsb4; output tmsb5; output tmsb6; output tmsb7; output tmsb8; output tmsb9; output tmsb10; output tmsb11; output tmsb12; output tmsb13; output tmsb14; output tmsb15; wire tmsb0; reg [15:0] tmsb_bus; assign tmsb0 = tmsb_bus[0]; assign tmsb1 = tmsb_bus[1]; assign tmsb2 = tmsb_bus[2]; assign tmsb3 = tmsb_bus[3]; assign tmsb4 = tmsb_bus[4]; assign tmsb5 = tmsb_bus[5]; assign tmsb6 = tmsb_bus[6]; assign tmsb7 = tmsb_bus[7]; assign tmsb8 = tmsb_bus[8]; assign tmsb9 = tmsb_bus[9]; assign tmsb10 = tmsb_bus[10]; assign tmsb11 = tmsb_bus[11]; assign tmsb12 = tmsb_bus[12]; assign tmsb13 = tmsb_bus[13]; assign tmsb14 = tmsb_bus[14]; assign tmsb15 = tmsb_bus[15]; assign atben = |{ct3,ct2,ct1,ct0}; always @ ( ct3, ct2, ct1, ct0 ) case ( {ct3,ct2,ct1,ct0} ) 4'b0000 : tmsb_bus = 16'b0000000000000001; 4'b0001 : tmsb_bus = 16'b0000000000000010; 4'b0010 : tmsb_bus = 16'b0000000000000100; 4'b0011 : tmsb_bus = 16'b0000000000001000; 4'b0100 : tmsb_bus = 16'b0000000000010000; 4'b0101 : tmsb_bus = 16'b0000000000100000; 4'b0110 : tmsb_bus = 16'b0000000001000000; 4'b0111 : tmsb_bus = 16'b0000000010000000; 4'b1000 : tmsb_bus = 16'b0000000100000000; 4'b1001 : tmsb_bus = 16'b0000001000000000; 4'b1010 : tmsb_bus = 16'b0000010000000000; 4'b1011 : tmsb_bus = 16'b0000100000000000; 4'b1100 : tmsb_bus = 16'b0001000000000000; 4'b1101 : tmsb_bus = 16'b0010000000000000; 4'b1110 : tmsb_bus = 16'b0100000000000000; 4'b1111 : tmsb_bus = 16'b1000000000000000; default : tmsb_bus = 16'b0000000000000000; endcase endmodule // stratixiv_hssi_pma_c_controller_4t16 //====Revision Log================ //Rev: 1.1 Tue Sep 2 10:24:10 PDT 2008 cgaillar //Initial C5 version // //Rev: 1.7 Fri Jun 6 11:55:49 PDT 2008 cgaillar //Refined reset & powerdown conditions for behavior closer to schematics //====End Log====================== module stratixiv_hssi_pma_c_clkgendrv ( clk0, clk90, clk180, clk270, cpulse, cpulseb, cpulseo, div5, hfclk_n, hfclk_p, lfclk_n, lfclk_p, rst_n, vccelxqyx, vssexqyx ); input clk0; input clk90; input clk180; input clk270; input div5; input rst_n; input vccelxqyx; input vssexqyx; output cpulse; output cpulseb; output cpulseo; output hfclk_n; output hfclk_p; output lfclk_n; output lfclk_p; integer lfclkp_counter; reg lfclkp_div5, lfclkp_div4, lfclkn_div5, lfclkn_div4, cpulse_div4, cpulse_div5; reg init_done; reg hfclk_p_prev; wire hfclk_p_wire; assign hfclk_p = hfclk_p_wire; assign hfclk_p_wire = ~rst_n ? 1'b0 : ~clk180; assign hfclk_n = ~rst_n ? 1'b1 : ~clk0; assign lfclk_p = ~rst_n ? 1'b0 : div5 ? lfclkp_div5 : lfclkp_div4; assign lfclk_n = ~rst_n ? 1'b1 : div5 ? lfclkn_div5 : lfclkn_div4; assign cpulse = ~rst_n ? 1'b0 : div5 ? cpulse_div5 : cpulse_div4; assign cpulseo = cpulse; assign cpulseb = ~cpulse; initial begin lfclkp_counter = 0; // change to blocking : manju lfclkp_div4 = 1'b0; lfclkp_div5 = 1'b0; lfclkn_div4 = 1'b1; lfclkn_div5 = 1'b1; cpulse_div4 = 1'b0; cpulse_div5 = 1'b0; init_done = 1'b0; // added : manju end // Edge counter used for lfclkp/n_div4/div5 and cpulse_div4/5 generation always @ ( hfclk_p_wire or negedge rst_n ) begin if ( rst_n == 1'b0 ) begin lfclkp_counter <= 0; lfclkp_div4 <= 1'b0; lfclkp_div5 <= 1'b0; lfclkn_div4 <= 1'b1; lfclkn_div5 <= 1'b1; cpulse_div4 <= 1'b0; cpulse_div5 <= 1'b0; init_done <= 1'b0; end else if (hfclk_p_wire != hfclk_p_prev) begin // after one cycle of hfclkp, if set, reset cpulse_div4/5 if ( hfclk_p_wire == 1'b1 & cpulse_div5 == 1'b1 ) cpulse_div5 <= 1'b0; if ( hfclk_p_wire == 1'b1 & cpulse_div4 == 1'b1 ) cpulse_div4 <= 1'b0; // generation of lfclkp/n_div5 & pulse_div5 ** posedge of lfclkp_div5 occurs at posedge of hfclkp ** if ( ( lfclkp_counter % 5 == 1 ) & ( hfclk_p_wire == 1'b1 ) ) begin lfclkp_div5 <= 1'b1; lfclkn_div5 <= 1'b0; if ( lfclkp_div5 == 1'b0 ) cpulse_div5 <= 1'b1; end else if ( ( lfclkp_counter % 5 == 1 ) & ( hfclk_p_wire == 1'b0 ) ) begin lfclkp_div5 <= 1'b0; lfclkn_div5 <= 1'b1; end // generation of lfclkp/n_div4 & pulse_div4 ** posedge of lfclkp_div5 occurs at posedge of hfclkp ** if ( ( hfclk_p_wire == 1'b1 ) & ( ( lfclkp_counter % 4 == 0 ) | ( lfclkp_counter % 4 == 1 ) ) ) begin if ( init_done == 1'b0 ) begin lfclkp_div4 <= 1'b1; lfclkn_div4 <= 1'b0; init_done <= 1'b1; end else begin lfclkp_div4 <= ~lfclkp_div4; lfclkn_div4 <= ~lfclkn_div4; end if ( lfclkp_div4 == 1'b0 ) cpulse_div4 <= 1'b1; end lfclkp_counter <= lfclkp_counter + 1; end hfclk_p_prev = hfclk_p_wire; end endmodule // stratixiv_hssi_pma_c_clkgendrv //====Revision Log================ //Rev: 1.1 Tue Sep 2 10:24:10 PDT 2008 cgaillar //Initial C5 version // //Rev: 1.23 Wed Jun 18 11:42:18 PDT 2008 cgaillar //Removed all 1'b1 & 1'b0 from instances. Added ifdef COSIM flag to change delay parameter from 1 to 0.05 and 2 to 0.1 //====End Log====================== module stratixiv_hssi_pma_c_clkgenbuf ( cgb_x_en, clk0_0, clk0_1, clk0_out, clk90_0, clk90_1, clk90_out, clk180_0, clk180_1, clk180_out, clk270_0, clk270_1, clk270_out, cmu_sel, cpulse, div5, dynamic_sw, gen2ngen1, hclk, hfclk_n, hfclk_p, lfclk_n, lfclk_p, m_sel, pcie_sw, pcie_sw_cdr, pclk, pdb, rst_n, rst_n1, vccelxqyx, vssexqyx ); input [1:0] cgb_x_en; input clk0_0; input clk0_1; input clk90_0; input clk90_1; input clk180_0; input clk180_1; input clk270_0; input clk270_1; input cmu_sel; input div5; input dynamic_sw; input [1:0] m_sel; input pcie_sw; input pdb; input rst_n; input vccelxqyx; input vssexqyx; output clk0_out; output clk90_out; output clk180_out; output clk270_out; output cpulse; output gen2ngen1; output hclk; output hfclk_n; output hfclk_p; output lfclk_n; output lfclk_p; output pcie_sw_cdr; output pclk; output rst_n1; parameter PARAM_DELAY = 0; wire pdb_buf, rst_n1; wire [3:0] clk_in; wire [3:0] clk_div2, clk_div4; reg [3:0] clk_out; wire clk270_out, clk180_out, clk90_out, clk0_out; wire rst_n1_clkgenbuf_div, rst_n2_clkgenbuf_div; wire cpulse_i, cpulseb_i, cpulseo; wire gen2ngen1; wire hfclkn_i, hfclkp_i, lfclkn_i, lfclkp_i; assign pdb_buf = pdb & ~(|cgb_x_en); assign rst_n1 = rst_n & pdb_buf; // * * b_mux4_2t1 - xcmux instance * * assign clk_in = (~rst_n1|~pdb_buf) ? 4'b0000 : ( cmu_sel ? {clk270_1,clk180_1,clk90_1,clk0_1} : {clk270_0,clk180_0,clk90_0,clk0_0} ); // * * stratixiv_hssi_pma_c_clkgenbuf_div - xdiv instance * * assign rst_n1_clkgenbuf_div = rst_n1 & ( m_sel[1] | m_sel[0]); assign rst_n2_clkgenbuf_div = rst_n1 & m_sel[1]; assign clk270_out = clk_out[3]; assign clk180_out = clk_out[2]; assign clk90_out = clk_out[1]; assign clk0_out = clk_out[0]; stratixiv_hssi_pma_c_divby2q xdiv2_2 ( .clk(~clk_in[2]), .clk0(clk_div2[0]), .clk90(clk_div2[1]), .clk180(clk_div2[2]), .clk270(clk_div2[3]), .vcce_la(vccelxqyx), .vssexqyx(vssexqyx), .clkb(~clk_in[0]), .rst_n(rst_n1_clkgenbuf_div) ); stratixiv_hssi_pma_c_divby2q xdiv2_4 ( .clk(~clk_div2[2]), .clk0(clk_div4[0]), .clk90(clk_div4[1]), .clk180(clk_div4[2]), .clk270(clk_div4[3]), .vcce_la(vccelxqyx), .vssexqyx(vssexqyx), .clkb(~clk_div2[0]), .rst_n(rst_n2_clkgenbuf_div) ); always @ ( m_sel or clk_in or clk_div2 or clk_div4 ) case ( m_sel ) 2'b00 : clk_out = clk_in; 2'b01 : clk_out = clk_div2; 2'b10 : clk_out = clk_div4; 2'b11 : clk_out = 4'b0000; default : clk_out = 4'bxxxx; endcase // * * stratixiv_hssi_pma_c_clkgendrv - xdrv instance - div by 4 or 5 * * stratixiv_hssi_pma_c_clkgendrv xdrv ( .clk0(clk0_out), .clk90(clk90_out), .clk180(clk180_out), .clk270(clk270_out), .cpulse(cpulse_i), .cpulseb(cpulseb_i), .cpulseo(cpulseo), .div5(div5), .hfclk_n(hfclkn_i), .hfclk_p(hfclkp_i), .lfclk_n(lfclkn_i), .lfclk_p(lfclkp_i), .rst_n(rst_n1), .vccelxqyx(vccelxqyx), .vssexqyx(vssexqyx) ); // * * c_pcie_sw - xpcie_sw instance * * stratixiv_hssi_pma_c_pcie_sw #(.PARAM_DELAY (PARAM_DELAY)) xpcie_sw ( .cpulse(cpulse_i), .cpulse_out(cpulse), .cpulseb(cpulseb_i), .cpulsei(cpulse_i), .dynamic_sw(dynamic_sw), .gen2ngen1(gen2ngen1), .hclk(hclk), .hfclkn(hfclkn_i), .hfclkn_out(hfclk_n), .hfclkp(hfclkp_i), .hfclkp_out(hfclk_p), .lfclkn(lfclkn_i), .lfclkn_out(lfclk_n), .lfclkp(lfclkp_i), .lfclkp_out(lfclk_p), .pcie_sw(pcie_sw), .pcie_sw_cdr(pcie_sw_cdr), .pclk(pclk), .pdb(pdb_buf), .rst_n(rst_n1), .vccelxqyx(vccelxqyx), .vssexqyx(vssexqyx), .div5(div5) ); endmodule // stratixiv_hssi_pma_c_clkgenbuf //====Revision Log================ //Rev: 1.1 Tue Sep 2 10:24:14 PDT 2008 cgaillar //Initial C5 version // //Rev: 1.8 Thu Feb 21 11:30:42 PST 2008 cgaillar //Updates to match g_gx_ww7_clean tag //====End Log====================== module stratixiv_hssi_pma_c_clkgenbuf_cmu ( cgb_vccelxqyx, cgb_vssexqyx, cgb_x_en, clk0_0, clk0_1, clk90_0, clk90_1, clk180_0, clk180_1, clk270_0, clk270_1, cmu_sel, cpulse_ht, cpulse_x1, div5, dynamic_sw, gen2ngen1, hclk, hfclkn_ht, hfclkn_x1, hfclkp_ht, hfclkp_x1, ht_sel, lfclkn_ht, lfclkn_x1, lfclkp_ht, lfclkp_x1, m_sel, pcie_sw, pcie_sw_cdr, pclk, pdb, rst_n, vccelxqyx, vssexqyx ); input [1:0] cgb_x_en; input clk0_0; input clk0_1; input clk90_0; input clk90_1; input clk180_0; input clk180_1; input clk270_0; input clk270_1; input cmu_sel; input div5; input dynamic_sw; input ht_sel; input [1:0] m_sel; input pcie_sw; input pdb; input rst_n; input vccelxqyx; input vssexqyx; output cgb_vccelxqyx; output cgb_vssexqyx; output cpulse_ht; output cpulse_x1; output gen2ngen1; output hclk; output hfclkn_ht; output hfclkn_x1; output hfclkp_ht; output hfclkp_x1; output lfclkn_ht; output lfclkn_x1; output lfclkp_ht; output lfclkp_x1; output pcie_sw_cdr; output pclk; supply1 vccelxqyx; supply0 vssexqyx; wire rst_n1; wire rst_n1b; wire ht_en; wire clk0_out, clk90_out, clk180_out, clk270_out; wire cpulseo; wire cpulseb_ht; nand x5b ( rst_n1b, rst_n1, ht_sel ); not x6b ( ht_en, rst_n1b ); stratixiv_hssi_pma_c_clkgenbuf xclkgen ( .cgb_x_en(cgb_x_en), .clk0_0(clk0_0), .clk0_1(clk0_1), .clk0_out(clk0_out), .clk90_0(clk90_0), .clk90_1(clk90_1), .clk90_out(clk90_out), .clk180_0(clk180_0), .clk180_1(clk180_1), .clk180_out(clk180_out), .clk270_0(clk270_0), .clk270_1(clk270_1), .clk270_out(clk270_out), .cmu_sel(cmu_sel), .cpulse(cpulse_x1), .div5(div5), .dynamic_sw(dynamic_sw), .gen2ngen1(gen2ngen1), .hclk(hclk), .hfclk_n(hfclkn_x1), .hfclk_p(hfclkp_x1), .lfclk_n(lfclkn_x1), .lfclk_p(lfclkp_x1), .m_sel(m_sel), .pcie_sw(pcie_sw), .pcie_sw_cdr(pcie_sw_cdr), .pclk(pclk), .pdb(pdb), .rst_n(rst_n), .rst_n1(rst_n1), .vccelxqyx(vccelxqyx), .vssexqyx(vssexqyx) ); stratixiv_hssi_pma_c_clkgendrv xdrv ( .clk0(clk270_out), .clk90(clk0_out), .clk180(clk90_out), .clk270(clk180_out), .cpulse(cpulse_ht), .cpulseb(cpulseb_ht), .cpulseo(cpulseo), .div5(div5), .hfclk_n(hfclkn_ht), .hfclk_p(hfclkp_ht), .lfclk_n(lfclkn_ht), .lfclk_p(lfclkp_ht), .rst_n(ht_en), .vccelxqyx(vccelxqyx), .vssexqyx(vssexqyx) ); pmos xmatb1 ( cgb_vccelxqyx, vccelxqyx, vssexqyx ); nmos xmatb3 ( cgb_vssexqyx, vssexqyx, vccelxqyx ); endmodule // stratixiv_hssi_pma_c_clkgenbuf_cmu module stratixiv_hssi_pma_c_d2a_mbpass ( bypass, d2a_in, d2a_out, radce_adapt, radce_pdb, vccehx, vssex ); input [7:5] bypass; input d2a_in; input radce_adapt; input radce_pdb; input vccehx; input vssex; output d2a_out; wire [7:1] level; wire [7:5] nbypass; wire [7:0] sel; assign d2a_out = (radce_adapt || (~radce_adapt && ~radce_pdb)) ? d2a_in : 1'bz; assign d2a_out = ((~radce_adapt && radce_pdb) && (bypass[7] || bypass[6] || bypass[5])) ? vccehx : 1'bz; endmodule // stratixiv_hssi_pma_c_d2a_mbpass //====Revision Log================ //Rev: 1.4 Wed Dec 5 13:59:34 PST 2007 cgaillar //Updates to match g_gx_ww45_clean schematic tag //====End Log====================== module stratixiv_hssi_pma_c_tx_clkmux_cmu ( cpulse, cpulse_ht, cpulse_x1, cpulse_x4, cpulse_xn_b, cpulse_xn_t, delay_sel, hfclk_n, hfclk_p, hfclkn_ht, hfclkn_x1, hfclkn_x4, hfclkn_xn_b, hfclkn_xn_t, hfclkp_ht, hfclkp_x1, hfclkp_x4, hfclkp_xn_b, hfclkp_xn_t, ht_sel, lfclk_n, lfclk_p, lfclkn_ht, lfclkn_x1, lfclkn_x4, lfclkn_xn_b, lfclkn_xn_t, lfclkp_ht, lfclkp_x1, lfclkp_x4, lfclkp_xn_b, lfclkp_xn_t, pdb, sel, vccelxqyx, vssexqyx ); input cpulse_ht; input cpulse_x1; input cpulse_x4; input cpulse_xn_b; input cpulse_xn_t; input delay_sel; input hfclkn_ht; input hfclkn_x1; input hfclkn_x4; input hfclkn_xn_b; input hfclkn_xn_t; input hfclkp_ht; input hfclkp_x1; input hfclkp_x4; input hfclkp_xn_b; input hfclkp_xn_t; input ht_sel; input lfclkn_ht; input lfclkn_x1; input lfclkn_x4; input lfclkn_xn_b; input lfclkn_xn_t; input lfclkp_ht; input lfclkp_x1; input lfclkp_x4; input lfclkp_xn_b; input lfclkp_xn_t; input pdb; input [1:0] sel; input vccelxqyx; input vssexqyx; output cpulse; output hfclk_n; output hfclk_p; output lfclk_n; output lfclk_p; parameter DELAY = 1; wire n10_sel_0, n11_sel_1; wire nx1_sel_xn,n01_sel_x4,n00_sel_x1; wire hfclkp_x1_0, hfclkn_x1_0, cpulse_x1_0, lfclkp_x1_0, lfclkn_x1_0, sel_x4_d; reg hfclkp_x4_0,hfclkn_x4_0,cpulse_x4_0,lfclkp_x4_0,lfclkn_x4_0; reg hfclkp_xn,hfclkn_xn,cpulse_xn,lfclkp_xn,lfclkn_xn; reg hfclk_p,hfclk_n,cpulse,lfclk_p,lfclk_n; reg hfclkp_ht_d,hfclkn_ht_d,cpulse_ht_d,lfclkp_ht_d,lfclkn_ht_d; reg hfclkp_x4_d,hfclkn_x4_d,cpulse_x4_d,lfclkp_x4_d,lfclkn_x4_d; // * * c_tx_clkmux_2t1 x0 * * // xhtdelay always @ ( hfclkp_ht,hfclkn_ht,cpulse_ht,lfclkp_ht,lfclkn_ht ) begin {hfclkp_ht_d,hfclkn_ht_d,cpulse_ht_d,lfclkp_ht_d,lfclkn_ht_d} <= #DELAY {hfclkp_ht,hfclkn_ht,cpulse_ht,lfclkp_ht,lfclkn_ht}; end assign hfclkp_x1_0 = ( pdb == 1'b0 ) ? 1'b0 :( (ht_sel == 1'b1) & (sel == 2'b00) ) ? hfclkp_ht_d : hfclkp_x1; assign hfclkn_x1_0 = ( pdb == 1'b0 ) ? 1'b0 :( (ht_sel == 1'b1) & (sel == 2'b00) ) ? hfclkn_ht_d : hfclkn_x1; assign cpulse_x1_0 = ( pdb == 1'b0 ) ? 1'b0 :( (ht_sel == 1'b1) & (sel == 2'b00) ) ? cpulse_ht_d : cpulse_x1; assign lfclkp_x1_0 = ( pdb == 1'b0 ) ? 1'b0 :( (ht_sel == 1'b1) & (sel == 2'b00) ) ? lfclkp_ht_d : lfclkp_x1; assign lfclkn_x1_0 = ( pdb == 1'b0 ) ? 1'b0 :( (ht_sel == 1'b1) & (sel == 2'b00) ) ? lfclkn_ht_d : lfclkn_x1; // * * c_tx_clkmux_2t1 x2 * * // xdelay always @ ( hfclkp_x4,hfclkn_x4,cpulse_x4,lfclkp_x4,lfclkn_x4 ) begin {hfclkp_x4_d,hfclkn_x4_d,cpulse_x4_d,lfclkp_x4_d,lfclkn_x4_d} <= #DELAY {hfclkp_x4,hfclkn_x4,cpulse_x4,lfclkp_x4,lfclkn_x4}; end assign sel_x4_d = delay_sel & ~sel[1] & sel[0]; always @ ( sel_x4_d or hfclkp_x4_d or hfclkn_x4_d or cpulse_x4_d or lfclkp_x4_d or lfclkn_x4_d or hfclkp_x4 or hfclkn_x4 or cpulse_x4 or lfclkp_x4 or lfclkn_x4 or pdb ) begin if ( pdb == 1'b1 ) case ( sel_x4_d ) 1'b0 : begin {hfclkp_x4_0,hfclkn_x4_0,cpulse_x4_0,lfclkp_x4_0,lfclkn_x4_0} = {hfclkp_x4,hfclkn_x4,cpulse_x4,lfclkp_x4,lfclkn_x4}; end 1'b1 : begin {hfclkp_x4_0,hfclkn_x4_0,cpulse_x4_0,lfclkp_x4_0,lfclkn_x4_0} = {hfclkp_x4_d,hfclkn_x4_d,cpulse_x4_d,lfclkp_x4_d,lfclkn_x4_d}; end default : begin {hfclkp_x4_0,hfclkn_x4_0,cpulse_x4_0,lfclkp_x4_0,lfclkn_x4_0} = 5'bxxxxx; end endcase else begin {hfclkp_x4_0,hfclkn_x4_0,cpulse_x4_0,lfclkp_x4_0,lfclkn_x4_0} = 5'b00000; end end // * * c_tx_clkmux_2t1 x0 * * assign n10_sel_0 = sel[1] & ~sel[0] & pdb; assign n11_sel_1 = sel[1] & sel[0] & pdb; always @ ( n11_sel_1 or n10_sel_0 or hfclkp_xn_t or hfclkn_xn_t or cpulse_xn_t or lfclkp_xn_t or lfclkn_xn_t or hfclkp_xn_b or hfclkn_xn_b or cpulse_xn_b or lfclkp_xn_b or lfclkn_xn_b or pdb ) begin if ( pdb == 1'b1 ) case ( {n11_sel_1,n10_sel_0} ) 2'b00 :begin {hfclkp_xn,hfclkn_xn,cpulse_xn,lfclkp_xn,lfclkn_xn} = 5'bzzzzz; end 2'b01 :begin {hfclkp_xn,hfclkn_xn,cpulse_xn,lfclkp_xn,lfclkn_xn} = {hfclkp_xn_t,hfclkn_xn_t,cpulse_xn_t,lfclkp_xn_t,lfclkn_xn_t}; end 2'b10 :begin {hfclkp_xn,hfclkn_xn,cpulse_xn,lfclkp_xn,lfclkn_xn} = {hfclkp_xn_b,hfclkn_xn_b,cpulse_xn_b,lfclkp_xn_b,lfclkn_xn_b}; end default :begin {hfclkp_xn,hfclkn_xn,cpulse_xn,lfclkp_xn,lfclkn_xn} = 5'bxxxxx; end endcase else begin {hfclkp_xn,hfclkn_xn,cpulse_xn,lfclkp_xn,lfclkn_xn} = 5'b00000; end end // * * c_tx_clkmux x1 * * assign nx1_sel_xn = sel[1]; assign n01_sel_x4 = ~sel[1] & sel[0] & pdb; assign n00_sel_x1 = ~sel[1] & ~sel[0] & pdb; always @ ( nx1_sel_xn or n01_sel_x4 or n00_sel_x1 or hfclkp_x1_0 or hfclkn_x1_0 or cpulse_x1_0 or lfclkp_x1_0 or lfclkn_x1_0 or hfclkp_x4_0 or hfclkn_x4_0 or cpulse_x4_0 or lfclkp_x4_0 or lfclkn_x4_0 or hfclkp_xn or hfclkn_xn or cpulse_xn or lfclkp_xn or lfclkn_xn or pdb ) begin if ( pdb == 1'b1 ) case ( {nx1_sel_xn,n01_sel_x4,n00_sel_x1} ) 3'b000 : begin {hfclk_p,hfclk_n,cpulse,lfclk_p,lfclk_n} = 5'bzzzzz; end 3'b001 : begin {hfclk_p,hfclk_n,cpulse,lfclk_p,lfclk_n} = {hfclkp_x1_0,hfclkn_x1_0,cpulse_x1_0,lfclkp_x1_0,lfclkn_x1_0}; end 3'b010 : begin {hfclk_p,hfclk_n,cpulse,lfclk_p,lfclk_n} = {hfclkp_x4_0,hfclkn_x4_0,cpulse_x4_0,lfclkp_x4_0,lfclkn_x4_0}; end 3'b100 : begin {hfclk_p,hfclk_n,cpulse,lfclk_p,lfclk_n} = {hfclkp_xn,hfclkn_xn,cpulse_xn,lfclkp_xn,lfclkn_xn}; end default : begin {hfclk_p,hfclk_n,cpulse,lfclk_p,lfclk_n} = 5'bxxxxx; end endcase else begin {hfclk_p,hfclk_n,cpulse,lfclk_p,lfclk_n} = 5'b00000; end end endmodule // stratixiv_hssi_pma_c_tx_clkmux_cmu //====Revision Log================ //Rev: 1.1 Tue Sep 2 10:24:15 PDT 2008 cgaillar //Initial C5 version // //Rev: 1.1 Wed May 14 13:18:59 PDT 2008 cgaillar //Updates to match g_gx_ww19_clean schematic tag // //====End Log====================== module stratixiv_hssi_pma_c_deser_pcie ( ck_div, en, pcie, pcieo, rpcie, rst_n, vcce_la, vssexqyx ); input ck_div; input pcie; input rpcie; input rst_n; input vcce_la; input vssexqyx; output en; output pcieo; parameter PARAM_DELAY = 0; reg n1, n0, pcie2, n4, n3, n2, n6; wire exor, pcie_clk_div; initial begin n0 = 0; n1 = 0; n2 = 0; n3 = 0; n4 = 0; n6 = 0; pcie2 = 0; end assign pcie_clk_div = ck_div & rpcie; assign exor = (~n1 & n0 ) | (n1 & ~n0); assign en = ~(n2 | n3 | n4 ); assign pcieo = ~rpcie | n6; always @ ( posedge pcie_clk_div or negedge rst_n ) if ( rst_n == 1'b0 ) begin {n1,n0,pcie2} <= #(PARAM_DELAY) 3'b000; {n4,n3,n2} <= #(PARAM_DELAY) 3'b000; n6 <= #(PARAM_DELAY) 1'b0; end else begin {n1,n0,pcie2} <= #(PARAM_DELAY) {n0,pcie2,pcie}; {n4,n3,n2} <= #(PARAM_DELAY) {n3,n2,exor}; n6 <= #(PARAM_DELAY) n1; end endmodule // stratixiv_hssi_pma_c_deser_pcie //====Revision Log================ //Rev: 1.1 Tue Sep 2 10:24:14 PDT 2008 cgaillar //Initial C5 version // //Rev: 1.2 Wed Jun 18 11:42:17 PDT 2008 cgaillar //Removed all 1'b1 & 1'b0 from instances. Added ifdef COSIM flag to change delay parameter from 1 to 0.05 and 2 to 0.1 // //Rev: 1.1 Wed May 14 13:18:58 PDT 2008 cgaillar //Updates to match g_gx_ww19_clean schematic tag // //====End Log====================== module stratixiv_hssi_pma_c_deser_10to20 ( ck_div, ckb_2div, clk_div, div2, douta, doutb, doutn, doutp, en, nck_div, nclk_div, rst_n, vcce_la, vssexqyx ); input ck_div; input div2; input [9:0] doutn; input [9:0] doutp; input en; input nck_div; input rst_n; input vcce_la; input vssexqyx; output ckb_2div; output clk_div; output [9:0] douta; output [9:0] doutb; output nclk_div; wire nc0, nc1, nc2, ck_2div, ckb_2div, ck_div2; wire rst_n_div2; reg [9:0] d10a, douta, doutb; parameter PARAM_DELAY = 0; assign rst_n_div2 = rst_n & div2; assign clk_div = en & (~ck_2div); stratixiv_hssi_pma_c_divby2q xdiv2_2 ( .clk(~ck_div), .clkb(ck_div), .clk0(nc0), .clk90(nc1), .vcce_la(vcce_la), .vssexqyx(vssexqyx), .clk180(ck_div2), .clk270(nc2), .rst_n(rst_n) ); assign ck_2div = div2 ? ~ck_div2 : ~ck_div; assign ckb_2div = div2 ? ck_div2 : ck_div; always @ ( negedge rst_n or posedge ck_2div ) if ( ~rst_n ) d10a[9:0] <= #(PARAM_DELAY) 10'b0000000000; else d10a[9:0] <= #(PARAM_DELAY) doutp[9:0]; always @ ( negedge rst_n or posedge ckb_2div ) if ( ~rst_n ) douta[9:0] <= #(PARAM_DELAY) 10'b0000000000; else douta[9:0] <= #(PARAM_DELAY) d10a[9:0]; always @ ( negedge rst_n_div2 or posedge ckb_2div ) if ( ~rst_n_div2 ) doutb[9:0] <= #(PARAM_DELAY) 10'b0000000000; else doutb[9:0] <= #(PARAM_DELAY) doutp[9:0]; endmodule // stratixiv_hssi_pma_c_deser_10to20 //====Revision Log================ //Rev: 1.1 Tue Sep 2 10:24:14 PDT 2008 cgaillar //Initial C5 version // //Rev: 1.2 Fri Jul 25 10:36:38 PDT 2008 cgaillar //Fixed iTrack 49370 // //Rev: 1.1 Wed May 14 13:18:59 PDT 2008 cgaillar //Updates to match g_gx_ww19_clean schematic tag // //====End Log====================== module stratixiv_hssi_pma_c_deser_ff_chain ( clka, clkb, dout, rsd, rst_n, rtest_fsd, rxinn, rxinp, vcce_la, vssexqyx ); input clka; input clkb; input [2:0] rsd; input rst_n; input rtest_fsd; input rxinn; input rxinp; input vcce_la; input vssexqyx; output dout; reg [3:0] drp, dfp; reg dout_1, dout; wire rxp_clk, rxn_clk, muxout_ff_chain; parameter PARAM_DELAY = 0; assign rxp_clk = rxinp & ~(rsd[2] & rtest_fsd); assign rxn_clk = rxinn & ~(rsd[2] & rtest_fsd); assign muxout_ff_chain = ( rsd[1] == 1'b0 & rsd[0] == 1'b0 ) ? |{drp[0],dfp[0]} : ( rsd[1] == 1'b0 & rsd[0] == 1'b1 ) ? |{drp[1],dfp[1]} : ( rsd[1] == 1'b1 & rsd[0] == 1'b0 ) ? |{drp[2],dfp[2]} : ( rsd[1] == 1'b1 & rsd[0] == 1'b1 ) ? |{drp[3],dfp[3]} : 1'bx; always @ ( posedge rxp_clk or negedge rst_n ) if ( rst_n == 1'b0 ) drp[3:0] <= #(PARAM_DELAY) 4'b0000; else drp[3:0] <= #(PARAM_DELAY) {drp[2:0],vcce_la}; always @ ( posedge rxn_clk or negedge rst_n ) if ( rst_n == 1'b0 ) dfp[3:0] <= #(PARAM_DELAY) 4'b0000; else dfp[3:0] <= #(PARAM_DELAY) {dfp[2:0],vcce_la}; always @ ( posedge clka ) // posedge ph[3] ) dout_1 <= #(PARAM_DELAY) muxout_ff_chain; always @ ( posedge clkb ) // negedge ph[3] ) dout <= #(PARAM_DELAY) dout_1; endmodule // stratixiv_hssi_pma_c_deser_ff_chain //====Revision Log================ //Rev: 1.1 Tue Sep 2 10:24:14 PDT 2008 cgaillar //Initial C5 version // //Rev: 1.2 Mon Aug 4 11:26:00 PDT 2008 cgaillar //Updated shiftout polarity in noswitch logic, and clk edge from posedge to negedge for fsd edge detection logic - iTrack 49743 // //Rev: 1.1 Wed May 14 13:18:59 PDT 2008 cgaillar //Updates to match g_gx_ww19_clean schematic tag // //====End Log====================== module stratixiv_hssi_pma_c_deser_fsd_rst ( in, rst, vcce_la, vssexqyx ); input in; input vcce_la; input vssexqyx; output rst; reg rst; parameter RST_SD_PULSE_WIDTH = 1; initial rst <= 1'b1; // rst pulse generator always @ ( negedge in ) begin rst <= 1'b0; rst <= # (RST_SD_PULSE_WIDTH) 1'b1; end endmodule // stratixiv_hssi_pma_c_deser_fsd_rst //====Revision Log================ //Rev: 1.17 Fri Apr 25 17:28:55 PDT 2008 cgaillar //Replaced 1'b1 & 1'b0 with vcc* & vss* in instances derived from schematics // //Rev: 1.16 Wed Mar 5 14:25:52 PST 2008 cgaillar //Initialized register in Fast Signal Detect logic //====End Log====================== module stratixiv_hssi_pma_c_deser ( clk90b, clk_divrx, deser_div2, deser_div5, deser_pdb, deven, devenb, dodd, doddb, dout, fsd, pcie_sw, pcieo, rdynamic_sw, rfast_sd, rst_n, rtest_fastsd, rxinn, rxinp, vcce_la, vssexqyx ); input clk90b; input deser_div2; input deser_div5; input deser_pdb; input deven; input devenb; input dodd; input doddb; input pcie_sw; input rdynamic_sw; input [3:0] rfast_sd; input rst_n; input rtest_fastsd; input rxinn; input rxinp; input vcce_la; input vssexqyx; output clk_divrx; output [19:0] dout; output fsd; output pcieo; reg [9:0] dp; reg [3:0] dsync; reg [3:0] drp, dfp; reg [9:0] outp, outn; reg [4:0] ph; reg deven_ok, devenb_ok, data_even; reg dodd_ok, doddb_ok, data_odd; reg ck_div; reg clk90_div5, clk90_div4, clk270_div5, clk270_div4, clk90_div_init_done, clk270_div_init_done; reg even_all0q, even_all1q, odd_all0q, odd_all1q; reg sd, sd1, shiftout_1, shiftoutq; reg n1, n0, pcie2, n4, n3, n2, n6; reg got_first_clk270_rising_edge; wire clk90, clk270; wire b1, cout, muxout_ff_chain; wire rst_ni, rst_n_div2; wire ck_div2, ck_2div; wire even_all0, even_all1, odd_all0, odd_all1; wire ckb_2div, rxp_clk, rxn_clk, noswitch; wire nc0; wire pcie_clk_div, activity; wire exor; wire shiftout; wire rst_sd; wire en; parameter PARAM_DELAY = 0; integer clk90_counter, clk270_counter; initial begin clk90_div_init_done <= 1'b0; clk270_div_init_done <= 1'b0; clk90_counter <= 0; clk270_counter <= 0; clk90_div4 <= 1'b0; clk90_div5 <= 1'b0; clk270_div4 <= 1'b0; clk270_div5 <= 1'b0; pcie2 = 0; drp <= 4'b0000; dfp <= 4'b0000; even_all1q <= 1'b0; even_all0q <= 1'b0; odd_all1q <= 1'b0; odd_all0q <= 1'b0; shiftoutq <= 1'b0; shiftout_1 <= 1'b0; n0 = 0; n1 = 0; n2 = 0; n3 = 0; n4 = 0; n6 = 0; got_first_clk270_rising_edge = 0; end assign rst_ni = deser_pdb & rst_n; assign rst_n_div2 = rst_ni & deser_div2; assign clk90 = ~clk90b; assign clk270 = clk90b; // * * c_deser_ph_clk * * // b1 synch w/ clk90 ; 60-40 duty-cycle in div5 mode ; 50-50 in div4 mode // cout synch w/ clk270 ; 50-50 duty-cycle in div5 and div4 modes assign b1 = deser_div5 ? clk90_div5 : clk90_div4; assign cout = deser_div5 ? clk270_div5 : clk270_div4; always @ ( posedge clk90 or negedge rst_ni ) begin if ( rst_ni == 1'b0 ) begin clk90_counter <= 0; clk90_div_init_done <= 1'b0; clk90_div5 <= 1'b0; clk90_div4 <= 1'b0; end else begin // generation of clk90_div5 if ( clk90_div_init_done == 1'b0 ) begin clk90_div5 <= 1'b1; clk90_div4 <= 1'b1; clk90_div_init_done <= 1'b1; end else begin if ( clk90_counter % 5 == 0 ) clk90_div5 <= 1'b1; else if ( clk90_counter % 5 == 3 ) clk90_div5 <= 1'b0; // generation of clk90_div4 if ( clk90_counter % 2 == 0 ) clk90_div4 <= ~clk90_div4; end clk90_counter <= clk90_counter + 1; end end // clk270_div4/5 should not start toggling before clk90_div4/5 always @ ( clk270 or negedge rst_ni ) begin if ( rst_ni == 1'b0 ) begin clk270_counter <= 0; clk270_div_init_done <= 1'b0; clk270_div5 <= 1'b0; clk270_div4 <= 1'b0; got_first_clk270_rising_edge = 1'b0; end else if ( clk90_div_init_done == 1'b1 ) begin // generation of clk270_div5 if ( ( clk270_counter % 5 == 0 ) & ( clk270 == 1'b1 ) ) begin got_first_clk270_rising_edge = 1'b1; clk270_div5 <= 1'b1; end else if ( ( clk270_counter % 5 == 0 ) & ( clk270 == 1'b0 ) ) clk270_div5 <= 1'b0; // generation of clk270_div4 if ( ( clk270 == 1'b1 ) & ( clk270_counter % 4 == 0 ) ) begin if ( clk270_div_init_done == 1'b0 ) begin clk270_div4 <= 1'b1; clk270_div_init_done <= 1'b1; end else clk270_div4 <= ~clk270_div4; end if (got_first_clk270_rising_edge == 1'b1) clk270_counter <= clk270_counter + 1; end end // like b1, ph duty-cycle is 60-40 in dvi5 mode, and 50-50 in div4 mode always @ ( negedge rst_ni or posedge clk270 ) if ( ~rst_ni ) ph[3:0] <= #(PARAM_DELAY) 4'b0000; else ph[3:0] <= #(PARAM_DELAY) {ph[2:0],b1}; always @ ( negedge deser_div5 or posedge clk270 ) if ( ~deser_div5 ) ph[4] <= #(PARAM_DELAY) 1'b0; else ph[4] <= #(PARAM_DELAY) ph[3]; // Shift register always @ ( negedge rst_ni or posedge ph[0] ) if ( ~rst_ni ) dp[1:0] <= #(PARAM_DELAY) 2'b00; else dp[1:0] <= #(PARAM_DELAY) {dodd,deven}; // used to be {data_odd,data_even} always @ ( negedge rst_ni or posedge ph[1] ) if ( ~rst_ni ) dp[3:2] <= #(PARAM_DELAY) 2'b00; else dp[3:2] <= #(PARAM_DELAY) {dodd,deven}; always @ ( negedge rst_ni or posedge ph[2] ) if ( ~rst_ni ) dp[5:4] <= #(PARAM_DELAY) 2'b00; else dp[5:4] <= #(PARAM_DELAY) {dodd,deven}; always @ ( negedge rst_ni or posedge ph[3] ) if ( ~rst_ni ) dp[7:6] <= #(PARAM_DELAY) 2'b00; else dp[7:6] <= #(PARAM_DELAY) {dodd,deven}; always @ ( negedge rst_ni or posedge ph[4] ) if ( ~rst_ni ) dp[9:8] <= #(PARAM_DELAY) 2'b00; else dp[9:8] <= #(PARAM_DELAY) {dodd,deven}; // dp[0,1,2,3] synchronization always @ ( negedge rst_ni or posedge ph[3] ) if ( ~rst_ni ) dsync[3:0] <= #(PARAM_DELAY) 4'b0000; else dsync[3:0] <= #(PARAM_DELAY) dp[3:0]; always @ ( negedge rst_ni or posedge ph[0] ) if ( ~rst_ni ) begin outp[9:0] <= #(PARAM_DELAY) 10'b0000000000; outn[9:0] <= #(PARAM_DELAY) 10'b0000000000; end else begin outp[9:0] <= #(PARAM_DELAY) {dp[9:4],dsync[3:0]}; outn[9:0] <= #(PARAM_DELAY) ~{dp[9:4],dsync[3:0]}; end // * * c_deser_10to20 * * stratixiv_hssi_pma_c_deser_10to20 x10to20 ( .ck_div(cout), .ckb_2div(ckb_2div), .clk_div(clk_divrx), .div2(deser_div2), .douta(dout[9:0]), .doutb(dout[19:10]), .doutn(outn), .doutp(outp), .en(en), .nck_div(~cout), .nclk_div(nc0), .rst_n(rst_ni), .vcce_la(vcce_la), .vssexqyx(vssexqyx) ); // * * c_deser_fsd_rst * * stratixiv_hssi_pma_c_deser_fsd_rst xrst ( .in(~ph[3]), .rst(rst_sd), .vcce_la(vcce_la), .vssexqyx(vssexqyx) ); // c_deser_ff_chain stratixiv_hssi_pma_c_deser_ff_chain xff_chain ( .clka(ph[3]/*clk_ff*/), .clkb(ph[0]/*ck_divbuf*/), .dout(shiftout), .rsd(rfast_sd[2:0]), .rst_n(rst_sd), .rtest_fsd(rtest_fastsd), .rxinn(rxinn), .rxinp(rxinp), .vcce_la(vcce_la), .vssexqyx(vssexqyx) ); // c_deser_pcie stratixiv_hssi_pma_c_deser_pcie xpcie ( .ck_div(ckb_2div), .en(en), .pcie(pcie_sw), .pcieo(pcieo), .rpcie(rdynamic_sw), .rst_n(rst_ni), .vcce_la(vcce_la), .vssexqyx(vssexqyx) ); // ** c_deser_data_comp blocks * * assign even_all1 = &{outp[6],outp[4],outp[2],outp[0]} & ( ~deser_div5 | outp[8] ); assign even_all0 = &{outn[6],outn[4],outn[2],outn[0]} & ( ~deser_div5 | outn[8] ); assign odd_all1 = &{outp[7],outp[5],outp[3],outp[1]} & ( ~deser_div5 | outp[9] ); assign odd_all0 = &{outn[7],outn[5],outn[3],outn[1]} & ( ~deser_div5 | outn[9] ); assign noswitch = (~((shiftout & rfast_sd[3]) | shiftoutq ) | ( ~rfast_sd[2] & rtest_fastsd ) ) & ( ~activity | ( ~rfast_sd[2] & ~rtest_fastsd ) ); assign activity = ~(((( even_all0 | ~rfast_sd[3] ) & even_all0q ) | (( even_all1 | ~rfast_sd[3] ) & even_all1q )) & ((( odd_all0 | ~rfast_sd[3] ) & odd_all0q ) | (( odd_all1 | ~rfast_sd[3] ) & odd_all1q ))); always @ ( negedge rst_ni or negedge clk_divrx ) if ( rst_ni == 1'b0 ) begin even_all1q <= #(PARAM_DELAY) 1'b0; even_all0q <= #(PARAM_DELAY) 1'b0; odd_all1q <= #(PARAM_DELAY) 1'b0; odd_all0q <= #(PARAM_DELAY) 1'b0; shiftoutq <= #(PARAM_DELAY) 1'b0; end else begin even_all1q <= #(PARAM_DELAY) even_all1; even_all0q <= #(PARAM_DELAY) even_all0; odd_all1q <= #(PARAM_DELAY) odd_all1; odd_all0q <= #(PARAM_DELAY) odd_all0; shiftoutq <= #(PARAM_DELAY) shiftout; end always @ ( negedge rst_ni or posedge clk_divrx ) if ( rst_ni == 1'b0 ) {sd1,sd} <= #(PARAM_DELAY) 1'b0; else {sd1,sd} <= #(PARAM_DELAY) {sd,~noswitch}; assign fsd = sd1 | sd; endmodule // stratixiv_hssi_pma_c_deser module stratixiv_hssi_pma_c_div4or5_mcnt (clk, clkb, d5, fout, foutn, rst_n, vccerx, vssex); output fout, foutn; input vccerx, vssex; input clk, clkb, d5, rst_n; reg clk_by2, clk_by4; reg a, b, c; wire clk_by5; assign foutn = ~fout; assign fout = (d5) ? clk_by5 : clk_by4; // Divide-by-4 clock always @ (rst_n or posedge clk) if (!rst_n) clk_by2 <= 1'b0; else clk_by2 <= ~clk_by2; always @ (negedge rst_n or posedge clk_by2) if (!rst_n) clk_by4 <= 1'b0; else clk_by4 <= ~clk_by4; // Divide-by-5 clock assign clk_by5 = (clk | ~b) & (a | clk_by5); always @ (negedge rst_n or posedge clk) if (!rst_n) begin a <= 1'b0; b <= 1'b0; c <= 1'b0; end else begin a <= (~a & ~b & c); b <= (~a & ~c); c <= (b); end endmodule // stratixiv_hssi_pma_c_div4or5_mcnt module stratixiv_hssi_pma_c_lockdet_tx18 ( disableb, dn, dnb, ib50, lock, lockb, pd, up, upb, vccerx, vssex ); input disableb; input dn; input dnb; input pd; input up; input upb; input vccerx; input vssex; inout ib50; output lock; output lockb; reg [4:0] cnt; assign lock = (cnt === 5'd3); assign lockb = ~lock; always @ (pd or posedge up) if (pd) cnt <= 5'd0; else if (cnt !== 5'd3) cnt <= cnt + 1; endmodule // stratixiv_hssi_pma_c_lockdet_tx18 module stratixiv_hssi_pma_c_pfd (dn, dnb, fbclk, refclk, up, upb, vccerx, vssex); output dn, dnb, up, upb; input vccerx, vssex; input fbclk, refclk; assign up = refclk; assign upb = ~refclk; assign dn = fbclk; assign dnb = ~fbclk; endmodule // stratixiv_hssi_pma_c_pfd module stratixiv_hssi_pma_c_rlpbk_ctrl ( cru_rlbk, rrevlb_sw, rrx_s_rdlpbk, tx_rlpbk, vccerx, vssex ); input cru_rlbk; input rrevlb_sw; input rrx_s_rdlpbk; input vccerx; input vssex; output tx_rlpbk; assign tx_rlpbk = (rrevlb_sw) ? cru_rlbk : rrx_s_rdlpbk; endmodule // stratixiv_hssi_pma_c_rlpbk_ctrl //====Revision Log================ //Rev: 1.1 Fri Oct 5 16:32:34 PDT 2007 cgaillar //Added timescale //====End Log====================== `ifdef POF `timescale 1ps/1fs `endif module stratixiv_hssi_pma_c_rlpbk_mux ( doddn, doddp, dodn, dodp, don, don_pre, dop, dop_pre, drxn, drxp, sel, vcce_la, voddn, voddp, vodn, vodp, von, von_pre, vop, vop_pre, vssex ); input doddn; input doddp; input dodn; input dodp; input don; input don_pre; input dop; input dop_pre; input drxn; input drxp; input sel; input vcce_la; input vssex; output voddn; output voddp; output vodn; output vodp; output von; output von_pre; output vop; output vop_pre; assign von = sel ? don : drxn; assign vop = sel ? dop : drxp; assign voddn = doddn; assign voddp = doddp; assign vodn = dodn; assign vodp = dodp; assign von_pre = don_pre; assign vop_pre = dop_pre; endmodule // stratixiv_hssi_pma_c_rlpbk_mux //====Revision Log================ //Rev: 1.19 Wed Jun 18 11:42:15 PDT 2008 cgaillar //Removed all 1'b1 & 1'b0 from instances. Added ifdef COSIM flag to change delay parameter from 1 to 0.05 and 2 to 0.1 //====End Log====================== module stratixiv_hssi_pma_c_rx ( ac_mode, analog_sd, atb0_rx, atb1_rx, atbsel, bsmode, bsrxn_in, bsrxn_out, bsrxp_in, bsrxp_out, ck0_sigdet, eqa_ctrl, eqb_ctrl, eqc_ctrl, eqd_ctrl, eqv_ctrl, ibc50u, ibp50u, ibp150u, inn, inn3, inp, inp3, lpbkn, lpbkp, mem_init, oc_calpd, oc_en, pd2, pd2_term, pd_rxclk_term, pdb, pdb_clk, pdbh_rx, pdbh_rxclk_term, pdbh_term, pdshft_clk, rbit_dc, rdlpbkn, rdlpbkn_far, rdlpbkp, rdlpbkp_far, refclk, rstn, rx_b50, rx_oc, rx_test, rx_testclk, rxbuf_ibias, rxn, rxp, s_lpbk, s_rdlpbk, sd_cdr, sd_cpon, sd_cpop, sd_force, sd_off, sd_on, sdlv, slew, term, vcce_la, vcce_oa, vccehtxqyx, vssexqyx, vtt ); input ac_mode; input [5:0] atbsel; input bsmode; input bsrxn_in; input bsrxp_in; input ck0_sigdet; input eqa_ctrl; input eqb_ctrl; input eqc_ctrl; input eqd_ctrl; input lpbkn; input lpbkp; input mem_init; input oc_calpd; input oc_en; input pd2_term; input pdb; input pdb_clk; input pdbh_term; input pdshft_clk; input [3:0] rbit_dc; input refclk; input rstn; input [3:0] rx_b50; input [7:0] rx_oc; input rx_test; input rx_testclk; input s_lpbk; input s_rdlpbk; input sd_force; input [4:0] sd_off; input [3:0] sd_on; input [3:0] sdlv; input [1:0] slew; input [2:0] term; input vcce_la; input vcce_oa; input vccehtxqyx; input vssexqyx; input [2:0] vtt; inout atb0_rx; inout atb1_rx; inout eqv_ctrl; inout [1:0] ibc50u; inout [3:0] ibp50u; inout [1:0] ibp150u; inout inn; inout inp; output analog_sd; output bsrxn_out; output bsrxp_out; output inn3; output inp3; output pd2; output pd_rxclk_term; output pdbh_rx; output pdbh_rxclk_term; output rdlpbkn; output rdlpbkn_far; output rdlpbkp; output rdlpbkp_far; output rxbuf_ibias; output rxn; output rxp; output sd_cdr; output sd_cpon; output sd_cpop; parameter PARAM_DELAY = 0; parameter SD_PULSE_DELAY = 1; parameter INVALID_SD_ON_OFF = 500; wire [2:0] ib50uc2; wire vccbn1g, d_vm, vbn_lb, vbn_dlb, vbn2_dlb, rxbuf_vcc, rxbuf_vsg; wire dlbpd, lbpd, lpmuxp, lpmuxn, rx_testclkpd, rx_testpd, slbpd; wire linepd, pdh_rx; reg rst_sdn, rst_sdp, sdp, sdn, sd_on_chg, sd_off_chg; integer sd_1_compout_pulse, sd_0_ck0_pulse, sdp_count, sdn_count; integer ck0_sigdet_count_cpop, ck0_sigdet_count_cpon; // pd2_term, pdb_clk, pdbh_term and pdsht_clk - added in ww1 assign pd2 = ~pdb; assign pd_rxclk_term = ~(pdb_clk | pdb); assign pdbh_rx = pdb; assign pdh_rx = pd2; assign pdbh_rxclk_term = ~(pdshft_clk & pdh_rx); // txgate instances assign atb0_rx = atbsel[0] ? vccbn1g : 1'bz; // rxbuf_vcc, rxbuf_vsg, vbn2_dlb, assign atb1_rx = atbsel[0] ? d_vm : 1'bz; // vbn_dlb, vbn_lb, d_vm, vccbn1g are 'z' assign atb0_rx = atbsel[1] ? rxbuf_ibias : 1'bz; assign atb1_rx = atbsel[1] ? vbn_lb : 1'bz; // assign atb0_rx = atbsel[2] ? vbn_dlb : 1'bz; // assign atb1_rx = atbsel[2] ? vbn2_dlb : 1'bz; // assign atb0_rx = atbsel[3] ? rxbuf_vcc : 1'bz; // assign atb1_rx = atbsel[3] ? rxbuf_vsg : 1'bz; // assign atb0_rx = atbsel[4] ? vssexqyx : 1'bz; assign atb1_rx = atbsel[4] ? vssexqyx : 1'bz; // c_rx_dlb - buffer w/ power-down (loopback to TX) assign dlbpd = ~(s_rdlpbk & pdb); assign rdlpbkp = (dlbpd) ? 1'b1 : rxp; assign rdlpbkn = (dlbpd) ? 1'b0 : rxn; assign rdlpbkp_far = rdlpbkp; assign rdlpbkn_far = rdlpbkn; // rx test mux assign rx_testclkpd = ~(rx_testclk & pdb); assign rx_testpd = ~( rx_test & pdb); assign slbpd = ~( s_lpbk & pdb); assign {lpmuxp,lpmuxn} = ( {~rx_testclkpd,~rx_testpd,~slbpd} == 3'b001 ) ? { lpbkp, lpbkn} : ( {~rx_testclkpd,~rx_testpd,~slbpd} == 3'b010 ) ? { lpbkp, lpbkn} : ( {~rx_testclkpd,~rx_testpd,~slbpd} == 3'b100 ) ? {refclk,~refclk} : ( {~rx_testclkpd,~rx_testpd,~slbpd} == 3'b000 ) ? 2'bzz : 2'bxx; // c_rx_lb - buffer w/ power-down (loopback from serializer) assign lbpd = ~( (s_lpbk | rx_testclk | rx_test ) & pdb ); assign inp3 = pdb ? ((lbpd) ? inp : lpmuxp) : 1'b1; assign inn3 = pdb ? ((lbpd) ? inn : lpmuxn) : 1'b1; // c_rx_term_vtt black-box // c_rx_buffer instance assign linepd = ~lbpd; assign rxp = pdb ? inp3 : 1'b1; assign rxn = pdb ? inn3 : 1'b1; // c_sd - signal detect assign analog_sd = sdp | sdn; assign sd_cdr = sd_force | s_lpbk | analog_sd; assign sd_cpop = (inp !== 1'bz) ? (inp & pdb) : 1'b0; // for digital simulation, assuming inp and inn are comparator's outputs assign sd_cpon = (inn !== 1'bz) ? (inn & pdb) : 1'b0; initial begin rst_sdn <= 1'b0; rst_sdp <= 1'b0; sdp_count <= 0; sdn_count <= 0; ck0_sigdet_count_cpop <= 0; ck0_sigdet_count_cpon <= 0; sdp <= 1'b0; sdn <= 1'b0; end always @ ( sd_on ) begin if ( (sd_on == 4'b0000) | (sd_on == 4'b1111) ) begin sd_1_compout_pulse <= INVALID_SD_ON_OFF; // $display ("Instance %m, Time %t: ERROR [Illegal usage]: The SD_ON value is illegal - sd_on=%b", $time, sd_on); end else case ( sd_on ) 4'b0001 : sd_1_compout_pulse <= 4; 4'b0010 : sd_1_compout_pulse <= 6; 4'b0011 : sd_1_compout_pulse <= 8; 4'b0100 : sd_1_compout_pulse <= 10; 4'b0101 : sd_1_compout_pulse <= 12; 4'b0110 : sd_1_compout_pulse <= 14; 4'b0111 : sd_1_compout_pulse <= 16; 4'b1000 : sd_1_compout_pulse <= 18; 4'b1001 : sd_1_compout_pulse <= 20; 4'b1010 : sd_1_compout_pulse <= 22; 4'b1011 : sd_1_compout_pulse <= 24; 4'b1100 : sd_1_compout_pulse <= 26; 4'b1101 : sd_1_compout_pulse <= 28; 4'b1110 : sd_1_compout_pulse <= 30; default : sd_1_compout_pulse <= 4; endcase sd_1_compout_pulse = sd_on; sd_on_chg <= 1'b1; sd_on_chg <= #(SD_PULSE_DELAY) 1'b0; end always @ ( sd_off ) begin if (sd_off == 4'b1111) begin sd_0_ck0_pulse <= INVALID_SD_ON_OFF; // $display ("Instance %m, Time %t: ERROR [Illegal usage]: The SD_OFF value is illegal - sd_off=%b", $time, sd_off); end else case ( sd_off[3:0] ) 4'b0001 : sd_0_ck0_pulse <= 4; 4'b0010 : sd_0_ck0_pulse <= 6; 4'b0011 : sd_0_ck0_pulse <= 8; 4'b0100 : sd_0_ck0_pulse <= 10; 4'b0101 : sd_0_ck0_pulse <= 12; 4'b0110 : sd_0_ck0_pulse <= 14; 4'b0111 : sd_0_ck0_pulse <= 16; 4'b1000 : sd_0_ck0_pulse <= 18; 4'b1001 : sd_0_ck0_pulse <= 20; 4'b1010 : sd_0_ck0_pulse <= 22; 4'b1011 : sd_0_ck0_pulse <= 24; 4'b1100 : sd_0_ck0_pulse <= 26; 4'b1101 : sd_0_ck0_pulse <= 28; 4'b1110 : sd_0_ck0_pulse <= 30; default : sd_0_ck0_pulse <= 4; endcase sd_off_chg <= 1'b1; sd_off_chg <= #(SD_PULSE_DELAY) 1'b0; end // Set sdp always @ ( negedge sd_cpop or posedge rst_sdp or negedge rstn or posedge sd_on_chg ) if ( (rst_sdp == 1'b1) | (sd_on_chg == 1'b1) | (rstn == 1'b0) ) begin sdp <= #(PARAM_DELAY) 1'b0; sdp_count <= 0; end else begin sdp_count = sdp_count + 1; if ( sdp_count >= sd_1_compout_pulse ) sdp <= #(PARAM_DELAY) 1'b1; end // Set sdn always @ ( negedge sd_cpon or negedge rstn or posedge rst_sdn or posedge sd_on_chg ) if ( (rst_sdn == 1'b1) | (sd_on_chg == 1'b1) | (rstn == 1'b0) ) begin sdn <= #(PARAM_DELAY) 1'b0; sdn_count <= 0; end else begin sdn_count = sdn_count + 1; if ( sdn_count >= sd_1_compout_pulse ) sdn <= #(PARAM_DELAY) 1'b1; end // Clear sdp -- generate rst_sdp always @ ( ck0_sigdet or posedge sd_cpop ) begin if ( (ck0_sigdet == 1'b0) & (sd_cpop == 1'b0) ) begin ck0_sigdet_count_cpop = ck0_sigdet_count_cpop + 1; if ( ck0_sigdet_count_cpop == sd_0_ck0_pulse ) rst_sdp <= 1'b1; end else if ( ck0_sigdet == 1'b1 ) rst_sdp <= 1'b0; if ( sd_cpop == 1'b1 ) ck0_sigdet_count_cpop = 0; end // Clear sdn -- generate rst_sdn always @ ( ck0_sigdet or posedge sd_cpon ) begin if ( (ck0_sigdet == 1'b0) & (sd_cpon == 1'b0) ) begin ck0_sigdet_count_cpon = ck0_sigdet_count_cpon + 1; if ( ck0_sigdet_count_cpon == sd_0_ck0_pulse ) rst_sdn <= 1'b1; end else if ( ck0_sigdet == 1'b1 ) rst_sdn <= 1'b0; if ( sd_cpon == 1'b1 ) ck0_sigdet_count_cpon = 0; end endmodule // c_rx //====Revision Log================ //Rev: 1.8 Wed Jun 18 11:42:15 PDT 2008 cgaillar //Removed all 1'b1 & 1'b0 from instances. Added ifdef COSIM flag to change delay parameter from 1 to 0.05 and 2 to 0.1 //====End Log====================== module stratixiv_hssi_pma_c_ser_20to10 ( clk_divtx, data, data_a, data_b, div2, lfclk_n, lfclk_p, pclk_in, pclksel, rst_n, vccetxqyx, vssexqyx ); input [9:0] data_a; input [9:0] data_b; input div2; input lfclk_n; input lfclk_p; input pclk_in; input pclksel; input rst_n; input vccetxqyx; input vssexqyx; output clk_divtx; output [9:0] data; parameter PARAM_DELAY = 0; `ifdef COSIM parameter PARAM_DELAY_1 = 0.05; `else parameter PARAM_DELAY_1 = 1; `endif wire rst_pdb, sel, nc0, nc1, nc2; wire lfclk_div2; reg [9:0] d10m; reg [9:0] data, d10a, d10b;//, lfclk_p_del; assign sel = ~clk_divtx & div2; assign rst_pdb = rst_n & div2; initial begin data <= 10'b0000000000; // To avoid propagation of 'X' first clock cycles d10a <= 10'b0000000000; d10b <= 10'b0000000000; end // xdivby2 stratixiv_hssi_pma_c_divby2q xdiv2_2 ( .clk(lfclk_p), .clkb(lfclk_n), .clk0(nc0), .clk90(nc1), .vcce_la(vccetxqyx), .vssexqyx(vssexqyx), .clk180(lfclk_div2), .clk270(nc2), .rst_n(rst_n) ); // c_mux2to1_4xd - xi37 // clk_divtx is same as halfclk_p assign clk_divtx = ( {pclksel,div2} == 2'b00 ) ? lfclk_p : ( {pclksel,div2} == 2'b01 ) ? lfclk_div2 : ( {pclksel,div2} == 2'b10 ) ? pclk_in : ( {pclksel,div2} == 2'b11 ) ? pclk_in : 1'bx ; // Pipe A always @ ( posedge clk_divtx or negedge rst_n ) if ( rst_n == 1'b0 ) d10a <= #(PARAM_DELAY) 10'b0000000000; else d10a <= #(PARAM_DELAY) data_a; // Pipe B always @ ( posedge clk_divtx or negedge rst_pdb ) if ( rst_pdb == 1'b0 ) d10b <= #(PARAM_DELAY) 10'b0000000000; else d10b <= #(PARAM_DELAY) data_b; always @ ( sel, d10b, d10a ) if ( sel ) d10m <= #(PARAM_DELAY_1) d10b; else d10m <= #(PARAM_DELAY_1) d10a; // Pipe #2 always @ ( posedge lfclk_p or negedge rst_n ) if ( rst_n == 1'b0 ) data <= #(PARAM_DELAY) 10'b0000000000; else data <= #(PARAM_DELAY) d10m; endmodule // stratixiv_hssi_pma_c_ser_20to10 //====Revision Log================ //Rev: 1.23 Wed Jun 18 11:42:15 PDT 2008 cgaillar //Removed all 1'b1 & 1'b0 from instances. Added ifdef COSIM flag to change delay parameter from 1 to 0.05 and 2 to 0.1 //====End Log====================== module stratixiv_hssi_pma_c_ser ( clk_divtx, cpulse, data, div2, div5, hfclkn, hfclkp, lbvon, lbvop, lfclkn, lfclkp, pclk_in, pclksel, pdb, pre_em, pre_em_2t, pre_em_pretap, pre_en_out, rst_n, s_lpbk, vccelxqyx, vccetxqyx, von, von_op1, von_op2, von_pre, vop, vop_op1, vop_op2, vop_pre, vssexqyx ); input cpulse; input [19:0] data; input div2; input div5; input hfclkn; input hfclkp; input lfclkn; input lfclkp; input pclk_in; input pclksel; input pdb; input [4:0] pre_em; input [3:0] pre_em_2t; input [3:0] pre_em_pretap; input rst_n; input s_lpbk; input vccelxqyx; input vccetxqyx; input vssexqyx; output clk_divtx; output lbvon; output lbvop; output pre_en_out; output von; output von_op1; output von_op2; output von_pre; output vop; output vop_op1; output vop_op2; output vop_pre; parameter PARAM_DELAY = 0; wire pre_en, pre_en_pretap, pre_en_2t, s_lpbkbuf, div5buf, rst_nbuf, rst_pdb; wire pe_pre, pe, pe_2t, lben, lben_rst; wire [9:0] d10, d10m; wire lfclk_div2; wire nc0, nc1, nc3; reg [9:0] data_mux5t1_sync1; reg [4:0] do_mux5t1_sync2, de_mux5t1_sync2; reg cp_even, c0_even, c1_even, c2_even, c3_even, c4_even; reg cp_odd, c0_odd, c1_odd, c2_odd, c3_odd, c4_odd; reg out_o, out_e, vop_pre_reg, von_pre_reg, vop_reg, von_reg, vop_op1_reg, von_op1_reg; reg oo1, oo2, oo3, oe1, oe2, oe3, vop_op2_reg, von_op2_reg, out_lb_reg, outb_lb_reg; wire clk_divtx_wire; assign pre_en_out = |pre_em; assign pre_en_pretap = |pre_em_pretap; assign pre_en_2t = |pre_em_2t; assign s_lpbkbuf = pdb & s_lpbk; assign div5buf = pdb & div5; assign rst_nbuf = pdb & rst_n; assign clk_divtx = clk_divtx_wire; // * * c_ser_20to10 -- x20to10 instance * * assign rst_pdb = rst_n & div2; initial begin data_mux5t1_sync1 <= 10'b0000000000; de_mux5t1_sync2[4:0] <= 5'b00000; do_mux5t1_sync2[4:0] <= 5'b00000; vop_op1_reg <= 1'b0; von_op1_reg <= 1'b1; vop_op2_reg <= 1'b0; von_op2_reg <= 1'b1; vop_reg <= 1'b0; von_reg <= 1'b1; vop_pre_reg <= 1'b0; von_pre_reg <= 1'b1; out_lb_reg <= 1'b0; outb_lb_reg <= 1'b1; {out_o, out_e} <= 2'b00; {oo1, oe1} <= 2'b00; {oo2, oe2} <= 2'b00; {oo3, oe3} <= 2'b00; {cp_even,c0_even,c1_even,c2_even,c3_even,c4_even} <= 6'b000000; {cp_odd,c0_odd,c1_odd,c2_odd,c3_odd,c4_odd} <= 6'b000000; end // * * c_ser_20to10 * * stratixiv_hssi_pma_c_ser_20to10 x20to10 ( .clk_divtx(clk_divtx), .data(d10), .data_a(data[9:0]), .data_b(data[19:10]), .div2(div2), .lfclk_n(lfclkn), .lfclk_p(lfclkp), .pclk_in(pclk_in), .pclksel(pclksel), .rst_n(rst_nbuf), .vccetxqyx(vccetxqyx), .vssexqyx(vssexqyx) ); // * * c_ser_mux5to1 -- xmux5to1_even & odd instances * * // Pipe #1 - synchronize data to lfclkp negedge always @ ( posedge lfclkn or negedge rst_nbuf ) if ( ~rst_nbuf ) data_mux5t1_sync1 <= #(PARAM_DELAY) 10'b0000000000; else data_mux5t1_sync1 <= #(PARAM_DELAY) d10; // Pipe #2 - Synchronize 0,2,4 and 1,3 to CLK and CLKB ; 6,8 and 5,7,9 to CLK and CLKB always @ ( posedge lfclkp or negedge rst_nbuf ) if ( ~rst_nbuf ) begin de_mux5t1_sync2[2:0] <= #(PARAM_DELAY) 3'b000; do_mux5t1_sync2[1:0] <= #(PARAM_DELAY) 2'b00; end else begin de_mux5t1_sync2[2:0] <= #(PARAM_DELAY) {data_mux5t1_sync1[4],data_mux5t1_sync1[2],data_mux5t1_sync1[0]}; do_mux5t1_sync2[1:0] <= #(PARAM_DELAY) {data_mux5t1_sync1[3],data_mux5t1_sync1[1]}; end always @ ( posedge lfclkn or negedge rst_nbuf ) if ( ~rst_nbuf ) begin de_mux5t1_sync2[4:3] <= #(PARAM_DELAY) 2'b00; do_mux5t1_sync2[4:2] <= #(PARAM_DELAY) 3'b000; end else begin de_mux5t1_sync2[4:3] <= #(PARAM_DELAY) {data_mux5t1_sync1[8],data_mux5t1_sync1[6]}; do_mux5t1_sync2[4:2] <= #(PARAM_DELAY) {data_mux5t1_sync1[9],data_mux5t1_sync1[7],data_mux5t1_sync1[5]}; end // Pulse generation for odd and even - CPULSE, CP, C0, ..., C4 always @ ( posedge hfclkn or negedge rst_nbuf ) if ( ~rst_nbuf ) {c4_even,c3_even,c2_even,c1_even,c0_even} <= #(PARAM_DELAY) 5'b00000; else begin c0_even <= #(PARAM_DELAY) cpulse; c1_even <= #(PARAM_DELAY) c0_even; c2_even <= #(PARAM_DELAY) c1_even; c3_even <= #(PARAM_DELAY) c2_even; if ( div5buf == 1'b1 ) c4_even <= #(PARAM_DELAY) c3_even; end always @ ( posedge hfclkn or negedge rst_nbuf ) // Mux Odd if ( ~rst_nbuf) cp_odd <= #(PARAM_DELAY) 1'b0; else cp_odd <= #(PARAM_DELAY) cpulse; always @ ( posedge hfclkp or negedge rst_nbuf ) if ( ~rst_nbuf) {c4_odd,c3_odd,c2_odd,c1_odd,c0_odd} <= #(PARAM_DELAY) 5'b00000; else begin c0_odd <= #(PARAM_DELAY) cp_odd; c1_odd <= #(PARAM_DELAY) c0_odd; c2_odd <= #(PARAM_DELAY) c1_odd; c3_odd <= #(PARAM_DELAY) c2_odd; if ( div5buf == 1'b1 ) c4_odd <= #(PARAM_DELAY) c3_odd; end // Mux2to1 Even outputs always @ ( posedge c0_even ) if ( c0_even == 1'b1 ) begin out_e <= #(PARAM_DELAY) de_mux5t1_sync2[0]; end always @ ( posedge c1_even ) if ( c1_even == 1'b1 ) begin out_e <= #(PARAM_DELAY) de_mux5t1_sync2[1]; end always @ ( posedge c2_even ) if ( c2_even == 1'b1 ) begin out_e <= #(PARAM_DELAY) de_mux5t1_sync2[2]; end always @ ( posedge c3_even ) if ( c3_even == 1'b1 ) begin out_e <= #(PARAM_DELAY) de_mux5t1_sync2[3]; end always @ ( posedge c4_even ) if ( c4_even == 1'b1 ) begin out_e <= #(PARAM_DELAY) de_mux5t1_sync2[4]; end // Mux2to1 Odd outputs always @ ( posedge c0_odd ) if ( c0_odd == 1'b1 ) begin out_o <= #(PARAM_DELAY) do_mux5t1_sync2[0]; end always @ ( posedge c1_odd ) if ( c1_odd == 1'b1 ) begin out_o <= #(PARAM_DELAY) do_mux5t1_sync2[1]; end always @ ( posedge c2_odd ) if ( c2_odd == 1'b1 ) begin out_o <= #(PARAM_DELAY) do_mux5t1_sync2[2]; end always @ ( posedge c3_odd ) if ( c3_odd == 1'b1 ) begin out_o <= #(PARAM_DELAY) do_mux5t1_sync2[3]; end always @ ( posedge c4_odd ) if ( c4_odd == 1'b1 ) begin out_o <= #(PARAM_DELAY) do_mux5t1_sync2[4]; end // * * c_ser_mux2to1 -- xmux2to1 instance * * assign pe_pre = pre_en_pretap & rst_nbuf & pdb; assign pe = pre_en_out & rst_nbuf & pdb; assign pe_2t = pre_en_2t & rst_nbuf & pdb; assign vop_pre = pe_pre ? vop_pre_reg : 1'b1; assign von_pre = pe_pre ? von_pre_reg : 1'b1; assign vop = pdb ? vop_reg : 1'b1; assign von = pdb ? von_reg : 1'b1; assign vop_op1 = pe ? vop_op1_reg : 1'b1; assign von_op1 = pe ? von_op1_reg : 1'b1; assign vop_op2 = pe_2t ? vop_op2_reg : 1'b1; assign von_op2 = pe_2t ? von_op2_reg : 1'b1; // FFs for OO & OE 1, 2 and 3 Generation always @ ( posedge hfclkn or negedge rst_nbuf ) if ( ~rst_nbuf) {oe3,oo2,oe1} <= #(PARAM_DELAY) 3'b000; else begin oe1 <= #(PARAM_DELAY) out_e; oo2 <= #(PARAM_DELAY) oo1; oe3 <= #(PARAM_DELAY) oe2; end always @ ( posedge hfclkp or negedge rst_nbuf ) if ( ~rst_nbuf) {oo3,oe2,oo1} <= #(PARAM_DELAY) 3'b000; else begin oo1 <= #(PARAM_DELAY) out_o; oe2 <= #(PARAM_DELAY) oe1; oo3 <= #(PARAM_DELAY) oo2; end // FFs for VOP/N_PRE, VOP/N, VOP/N_OP1 and VOP/N_OP2 Outputs Generation always @ ( posedge hfclkp or negedge pe_pre ) if ( ~pe_pre ) begin vop_pre_reg <= #(PARAM_DELAY) 1'b0; von_pre_reg <= #(PARAM_DELAY) 1'b1; end else begin vop_pre_reg <= #(PARAM_DELAY) out_o; von_pre_reg <= #(PARAM_DELAY) ~out_o; end always @ ( posedge hfclkn or negedge pe_pre ) if ( ~pe_pre ) begin vop_pre_reg <= #(PARAM_DELAY) 1'b0; von_pre_reg <= #(PARAM_DELAY) 1'b1; end else begin vop_pre_reg <= #(PARAM_DELAY) out_e; von_pre_reg <= #(PARAM_DELAY) ~out_e; end always @ ( posedge hfclkp or negedge pdb ) if ( ~pdb ) begin vop_reg <= #(PARAM_DELAY) 1'b0; von_reg <= #(PARAM_DELAY) 1'b1; end else begin vop_reg <= #(PARAM_DELAY) oe1; von_reg <= #(PARAM_DELAY) ~oe1; end always @ ( posedge hfclkn or negedge pdb ) if ( ~pdb ) begin vop_reg <= #(PARAM_DELAY) 1'b0; von_reg <= #(PARAM_DELAY) 1'b1; end else begin vop_reg <= #(PARAM_DELAY) oo1; von_reg <= #(PARAM_DELAY) ~oo1; end always @ ( posedge hfclkp or negedge pe ) if ( ~pe ) begin vop_op1_reg <= #(PARAM_DELAY) 1'b0; von_op1_reg <= #(PARAM_DELAY) 1'b1; end else begin vop_op1_reg <= #(PARAM_DELAY) oo2; von_op1_reg <= #(PARAM_DELAY) ~oo2; end always @ ( posedge hfclkn or negedge pe ) if ( ~pe ) begin vop_op1_reg <= #(PARAM_DELAY) 1'b0; von_op1_reg <= #(PARAM_DELAY) 1'b1; end else begin vop_op1_reg <= #(PARAM_DELAY) oe2; von_op1_reg <= #(PARAM_DELAY) ~oe2; end always @ ( posedge hfclkp or negedge pe_2t ) if ( ~pe_2t ) begin vop_op2_reg <= #(PARAM_DELAY) 1'b0; von_op2_reg <= #(PARAM_DELAY) 1'b1; end else begin vop_op2_reg <= #(PARAM_DELAY) oe3; von_op2_reg <= #(PARAM_DELAY) ~oe3; end always @ ( posedge hfclkn or negedge pe_2t ) if ( ~pe_2t ) begin vop_op2_reg <= #(PARAM_DELAY) 1'b0; von_op2_reg <= #(PARAM_DELAY) 1'b1; end else begin vop_op2_reg <= #(PARAM_DELAY) oo3; von_op2_reg <= #(PARAM_DELAY) ~oo3; end // * * c_ser_mux2to1_lb -- xmux2to1_lb instance * * assign lben = pdb & s_lpbkbuf; assign lben_rst = pdb & s_lpbkbuf & rst_n; assign lbvop = lben ? out_lb_reg : 1'b1; assign lbvon = lben ? outb_lb_reg : 1'b1; always @ ( posedge hfclkn or negedge lben_rst ) if ( ~lben_rst ) begin out_lb_reg <= #(PARAM_DELAY) 1'b0; outb_lb_reg <= #(PARAM_DELAY) 1'b1; end else begin out_lb_reg <= #(PARAM_DELAY) out_e; outb_lb_reg <= #(PARAM_DELAY) ~out_e; end always @ ( posedge hfclkp or negedge lben_rst ) if ( ~lben_rst ) begin out_lb_reg <= #(PARAM_DELAY) 1'b0; outb_lb_reg <= #(PARAM_DELAY) 1'b1; end else begin out_lb_reg <= #(PARAM_DELAY) out_o; outb_lb_reg <= #(PARAM_DELAY) ~out_o; end endmodule // stratixiv_hssi_pma_c_ser // Modified from c_sdffrr_1x.v module stratixiv_hssi_pma_c_sdl_en_2x ( clk, d, db, en, out, outb, vcce_la, vssex ); input clk; input d; input db; input en; input vcce_la; input vssex; output out, outb; reg out, outb; always @ (en or posedge clk) begin if (~en) begin out <= 1'b0; outb <= 1'b1; end else begin out <= d; outb <= db; end end endmodule // stratixiv_hssi_pma_c_sdl_en_2x //====Revision Log================ //Rev: 1.5 Tue Jul 1 15:25:03 PDT 2008 cgaillar //Updated c_tx port and rcv_detect logic to be on for differential data, in addition to '0,0' or '1,1' //====End Log====================== module stratixiv_hssi_pma_c_rcv_detect_div_by_2 (CLK, RESET_N, CLKOUT); // synthesis syn_black_box input CLK, RESET_N; output CLKOUT; reg CLKOUT; wire NEXT_VAL; initial CLKOUT = 1'b0; // state definition always @ (posedge CLK or negedge RESET_N) if (!RESET_N) CLKOUT <= 1'b0; else CLKOUT <= NEXT_VAL; assign NEXT_VAL = ~CLKOUT; endmodule // div_by_2 // synchronizer to synchronize the receiver module stratixiv_hssi_pma_c_rcv_detect_clk_gen (CLK, RESET_N, CLKOUT); input CLK, RESET_N; output CLKOUT; wire CLKOUT; wire CLK8M, CLK4M, CLK2M; stratixiv_hssi_pma_c_rcv_detect_div_by_2 DIV_1(.CLK(CLK), .RESET_N(RESET_N), .CLKOUT(CLK8M)); stratixiv_hssi_pma_c_rcv_detect_div_by_2 DIV_2(.CLK(CLK8M), .RESET_N(RESET_N), .CLKOUT(CLK4M)); stratixiv_hssi_pma_c_rcv_detect_div_by_2 DIV_3(.CLK(CLK4M), .RESET_N(RESET_N), .CLKOUT(CLK2M)); stratixiv_hssi_pma_c_rcv_detect_div_by_2 DIV_4(.CLK(CLK2M), .RESET_N(RESET_N), .CLKOUT(CLKOUT)); endmodule // clk_gen module stratixiv_hssi_pma_c_rcv_detect_sync (CLK, RESET_N, RCV_DET, RCV_DET_OUT); // synthesis syn_black_box input CLK, RESET_N, RCV_DET; output RCV_DET_OUT; reg RCV_DET_OUT; reg RCV_DET_MID; always @ (posedge CLK or negedge RESET_N) if (!RESET_N) begin RCV_DET_OUT <= 1'b0; RCV_DET_MID <= 1'b0; end else begin RCV_DET_OUT <= RCV_DET_MID; RCV_DET_MID <= RCV_DET; end endmodule // rcv_det_sync // receiver detect finite state machine module stratixiv_hssi_pma_c_rcv_detect_fsm (CLK, RESET_N, COM_PASS, PROBE_PASS, DET_ON, DETECT_VALID, RCV_FOUND, TX_DET_RX, RX_P, RX_N ); // synthesis syn_black_box input CLK, RESET_N, COM_PASS, PROBE_PASS, TX_DET_RX, RX_P, RX_N; output RCV_FOUND, DET_ON, DETECT_VALID; reg [2:0] STATE; reg [2:0] NEXTSTATE; reg RCV_FOUND, DET_ON, NEXT_RCV_FOUND, DETECT_VALID; reg FAKE_RCV_PRESENT; wire RXPN_NOT_Z; // state definition parameter RESET = 3'b000; parameter WAKE = 3'b001; parameter STATE_1 = 3'b011; parameter STATE_2 = 3'b101; parameter HOLD = 3'b100; // manju : FAKE_RCV_PRESENT will always be '1' as no Denali models. // assign RXPN_NOT_Z = ( (RX_P == 1'b1) && (RX_N == 1'b1) || (RX_P == 1'b0) && (RX_N == 1'b0) || // (RX_P == 1'b0) && (RX_N == 1'b1) || (RX_P == 1'b1) && (RX_N == 1'b0) ) ? 1'b1 : 1'b0; initial begin FAKE_RCV_PRESENT = 1'b1; NEXTSTATE = 3'b001; end // State logic and FSM always @ (posedge CLK or negedge RESET_N) if(!RESET_N) STATE <= RESET; else STATE <= NEXTSTATE; always @ (STATE or COM_PASS) begin case (STATE) RESET: NEXTSTATE = WAKE; WAKE: begin if (COM_PASS) NEXTSTATE = STATE_1; else NEXTSTATE = WAKE; end STATE_1: NEXTSTATE = STATE_2; STATE_2: NEXTSTATE = HOLD; HOLD: NEXTSTATE = HOLD; default: NEXTSTATE = RESET; endcase // case(state) end // always @ (state or com_pass) // Output logic always @ (posedge CLK or negedge RESET_N) if(!RESET_N) RCV_FOUND <= 1'b0; else RCV_FOUND <= NEXT_RCV_FOUND; always @ (NEXTSTATE or PROBE_PASS or FAKE_RCV_PRESENT) begin if ((NEXTSTATE == STATE_2) && (!PROBE_PASS) && FAKE_RCV_PRESENT) // probe pass goes up slow -> there is rx NEXT_RCV_FOUND = 1'b1; else if ((NEXTSTATE == HOLD) && FAKE_RCV_PRESENT) NEXT_RCV_FOUND = RCV_FOUND; else // probe pass goes up fast -> no rx NEXT_RCV_FOUND = 1'b0; end // there is no rcv_det_syn always @ (STATE) if (STATE == RESET) DET_ON = 1'b0; else DET_ON = 1'b1; always @ (STATE) if (STATE == HOLD) DETECT_VALID = 1'b1; else DETECT_VALID = 1'b0; endmodule // rcv_det_fsm module stratixiv_hssi_pma_c_rcv_detect_control (CLK, RCV_DET_EN, RCV_DET_PDB, COM_PASS, PROBE_PASS, DET_ON, DETECT_VALID, RCV_FOUND, RX_P, RX_N); input CLK, RCV_DET_EN, RCV_DET_PDB, COM_PASS, PROBE_PASS, RX_P, RX_N; output DET_ON, DETECT_VALID, RCV_FOUND; wire RCV_DET_SYN; stratixiv_hssi_pma_c_rcv_detect_sync XRCV_DET_SYNC (CLK, RCV_DET_PDB, RCV_DET_EN, RCV_DET_SYN); stratixiv_hssi_pma_c_rcv_detect_fsm XRCV_DET_FSM (CLK, RCV_DET_SYN, COM_PASS, PROBE_PASS, DET_ON, DETECT_VALID, RCV_FOUND, RCV_DET_EN, RX_P, RX_N); endmodule // rcv_det_control // Digital part of the receiver detection module stratixiv_hssi_pma_c_rcv_det_digital (OSCCLK, RCV_DET_PDB, RCV_DET_EN, COM_PASS, PROBE_PASS, DET_ON, DETECT_VALID, RCV_FOUND, RX_P, RX_N); input OSCCLK, RCV_DET_PDB, RCV_DET_EN, COM_PASS, PROBE_PASS, RX_P, RX_N; output DET_ON, RCV_FOUND, DETECT_VALID; wire CLK; stratixiv_hssi_pma_c_rcv_detect_clk_gen XCLK_GEN (OSCCLK, RCV_DET_PDB, CLK); stratixiv_hssi_pma_c_rcv_detect_control XRCV_DET_CTRL(CLK, RCV_DET_EN, RCV_DET_PDB, COM_PASS, PROBE_PASS, DET_ON, DETECT_VALID, RCV_FOUND, RX_P, RX_N); endmodule // rcv_det_digital //====Revision Log================ //Rev: 1.5 Wed Apr 23 10:44:50 PDT 2008 cgaillar //Reverted to probe_pass 1.3 version logic //====End Log====================== `timescale 1ps / 1ps module stratixiv_hssi_pma_c_rcv_detect ( com_pass, detect_on, fixed_clk_out, probe_pass, rcv_det_pdb, rdet, rx_det_clk, rx_det_valid, rx_found, sel_150r, tx_det_rx, rx_n, rx_p ); input rcv_det_pdb; input [1:0] rdet; input rx_det_clk; input tx_det_rx; input rx_p; input rx_n; output com_pass; output detect_on; output fixed_clk_out; output probe_pass; output rx_det_valid; output rx_found; output sel_150r; wire com_pass, probe_pass; assign fixed_clk_out = rx_det_clk; assign sel_150r = 1'b0; assign #100000 com_pass = detect_on; assign #100000 probe_pass = 1'b0; // * * Analog portion not modeled * * stratixiv_hssi_pma_c_rcv_det_digital XRCV_DET_DIGITAL ( .OSCCLK (rx_det_clk), .RCV_DET_PDB (rcv_det_pdb), .RCV_DET_EN (tx_det_rx), .COM_PASS (com_pass), .PROBE_PASS (probe_pass), .DET_ON (detect_on), .DETECT_VALID (rx_det_valid), .RCV_FOUND (rx_found), .RX_N(rx_n), .RX_P(rx_p) ); endmodule // stratixiv_hssi_pma_c_rcv_detect //====Revision Log================ //Rev: 1.2 Tue Sep 23 17:46:02 PDT 2008 cgaillar //Updated tx_det_rx and tx_elec_idl priority //====End Log====================== module stratixiv_hssi_pma_c_tx ( atb0, atb1, bsmode, bsoeb, bstxn_in, bstxp_in, cgb_vccelxqyx, cgb_vssexqyx, com_pass, detect_on, fixed_clk_out, ib50uc_rcvdt, ib50uc_vcm, ib50ut_vcm, ib100uc, lst, pdb, probe_pass, r_dft_sel, r_dis_idlegate, r_highv, r_lowv, r_rx_det, r_slew, rlpbkn, rlpbkn_em, rlpbkp, rlpbkp_em, rpre_em_1t, rpre_em_2t, rpre_em_pt, rsig_inv_2t, rsig_inv_ptap, rterm_sel, rtx_rlpbk, rtx_vtt, rvod_sel, rx_det_clk, rx_det_pdb, rx_detect_valid, rx_found, sel_150r, tx50, tx_det_rx, tx_dftout, tx_elec_idl, vccehtxqyx, vccehxqyx, vccesdh_la, vccesdp_la, vccetxqyx, vin, vin_po1, vin_po2, vin_pre, vip, vip_po1, vip_po2, vip_pre, von, vop, vssexqyx, rx_p, rx_n ); input bsmode; input bsoeb; input bstxn_in; input bstxp_in; input cgb_vccelxqyx; input cgb_vssexqyx; input [3:0] lst; input pdb; input [2:0] r_dft_sel; input r_dis_idlegate; input r_highv; input r_lowv; input [1:0] r_rx_det; input [1:0] r_slew; input rlpbkn; input rlpbkn_em; input rlpbkp; input rlpbkp_em; input [4:0] rpre_em_1t; input [3:0] rpre_em_2t; input [3:0] rpre_em_pt; input rsig_inv_2t; input rsig_inv_ptap; input [2:0] rterm_sel; input rtx_rlpbk; input [1:0] rtx_vtt; input [2:0] rvod_sel; input rx_det_clk; input rx_det_pdb; input [3:0] tx50; input tx_det_rx; input tx_elec_idl; input vccehtxqyx; input vccehxqyx; input vccesdh_la; input vccesdp_la; input vccetxqyx; input vin; input vin_po1; input vin_po2; input vin_pre; input vip; input vip_po1; input vip_po2; input vip_pre; input vssexqyx; input rx_p; input rx_n; inout atb0; inout atb1; inout ib50uc_rcvdt; inout ib50uc_vcm; inout ib50ut_vcm; inout ib100uc; output com_pass; output detect_on; output fixed_clk_out; output probe_pass; output rx_detect_valid; output rx_found; output sel_150r; output [6:1] tx_dftout; output von; output vop; wire [14:0] atbsel; wire atbi_0, atbi_1; wire vtp_1po, vtn_1po, vbiasp_cs, vbiasn_cs, vbiasp, vbiasn, vtp, vtn; // not driven for now wire [6:1] vodselb, vodsel_pdrv; wire atben; reg [5:1] pre_em_2po, pre_em_pre; reg [6:1] pre_em_1po; wire po1_en_pdrvb, pre_en_pos, pre_en_neg, po2_en_pos, po2_en_neg; wire outpos_p, outpos_n, outneg_p, outneg_n; wire [5:0] vopos_pd, vopos_nd, voneg_pd, voneg_nd; wire txden, rlpbk_en, po1_rlpbk_en, po1_en, po2_en, pre_en; wire prepb_em_pre, pd_idl, vccbn1g, threshold; reg prep, pren, po1p, po1n, po2p, po2n, mainp, mainn; reg [3:0] dec2t4_en; reg [6:1] vodsel; // ibias_ref & c_tx_vcm not modeled // txgate_por assign atb0 = atben ? atbi_0 : 1'bz; assign atb1 = atben ? atbi_1 : 1'bz; stratixiv_hssi_pma_c_controller_4t16 xatb ( .atben(atben), .ct0(lst[0]), .ct1(lst[1]), .ct2(lst[2]), .ct3(lst[3]), .tmsb1(atbsel[0]), .tmsb2(atbsel[1]), .tmsb3(atbsel[2]), .tmsb4(atbsel[3]), .tmsb5(atbsel[4]), .tmsb6(atbsel[5]), .tmsb7(atbsel[6]), .tmsb8(atbsel[7]), .tmsb9(atbsel[8]), .tmsb10(atbsel[9]), .tmsb11(atbsel[10]), .tmsb12(atbsel[11]), .tmsb13(atbsel[12]), .tmsb14(atbsel[13]), .tmsb15(atbsel[14]), .vcce_la(vccesdp_la), .vssex(vssexqyx) ); // * * C_TX_DRIVER * * // txgate_por assign atbi_0 = atbsel[1] ? vtp_1po : 1'bz; assign atbi_0 = atbsel[0] ? vbiasp : 1'bz; assign atbi_0 = atbsel[2] ? vbiasp_cs : 1'bz; assign atbi_0 = atbsel[3] ? vtp : 1'bz; assign atbi_1 = atbsel[1] ? vtn_1po : 1'bz; assign atbi_1 = atbsel[0] ? vbiasn : 1'bz; assign atbi_1 = atbsel[2] ? vbiasn_cs : 1'bz; assign atbi_1 = atbsel[3] ? vtn : 1'bz; // -- c_tx_dec xtxdec -- assign txden = pdb & ~tx_elec_idl & ~rtx_rlpbk; assign rlpbk_en = pdb & ~tx_elec_idl & rtx_rlpbk; assign po1_rlpbk_en = rlpbk_en ? |rpre_em_1t : 1'b0; // c_dec3t7 - xmp_decode assign vodselb = ~vodsel; always @ ( rvod_sel or pdb ) begin if ( pdb == 1'b1 ) case ( rvod_sel ) 3'b000 : vodsel <= 6'b000000; 3'b001 : vodsel <= 6'b000001; 3'b010 : vodsel <= 6'b000011; 3'b011 : vodsel <= 6'b000111; 3'b100 : vodsel <= 6'b001111; 3'b101 : vodsel <= 6'b011111; 3'b110 : vodsel <= 6'b100011; 3'b111 : vodsel <= 6'b100111; default : vodsel <= 6'b000000; endcase else vodsel = 6'b000000; end // c_dec5t5 - x1t_decode always @ ( rpre_em_1t or pdb ) begin if ( pdb == 1'b1 ) begin case ( rpre_em_1t ) 5'b00000 : pre_em_1po <= 6'b000000; 5'b00001 : pre_em_1po <= 6'b000100; 5'b00010 : pre_em_1po <= 6'b000101; 5'b00011 : pre_em_1po <= 6'b000110; 5'b00100 : pre_em_1po <= 6'b000111; 5'b00101 : pre_em_1po <= 6'b001000; 5'b00110 : pre_em_1po <= 6'b001001; 5'b00111 : pre_em_1po <= 6'b001010; 5'b01000 : pre_em_1po <= 6'b001011; 5'b01001 : pre_em_1po <= 6'b001100; 5'b01010 : pre_em_1po <= 6'b001101; 5'b01011 : pre_em_1po <= 6'b001110; 5'b01100 : pre_em_1po <= 6'b001111; 5'b01101 : pre_em_1po <= 6'b010000; 5'b01110 : pre_em_1po <= 6'b010001; 5'b01111 : pre_em_1po <= 6'b010010; 5'b10000 : pre_em_1po <= 6'b010011; 5'b10001 : pre_em_1po <= 6'b010100; 5'b10010 : pre_em_1po <= 6'b010101; 5'b10011 : pre_em_1po <= 6'b010110; 5'b10100 : pre_em_1po <= 6'b010111; 5'b10101 : pre_em_1po <= 6'b011000; 5'b10110 : pre_em_1po <= 6'b011010; 5'b10111 : pre_em_1po <= 6'b011100; 5'b11000 : pre_em_1po <= 6'b011110; 5'b11001 : pre_em_1po <= 6'b110000; 5'b11010 : pre_em_1po <= 6'b110010; 5'b11011 : pre_em_1po <= 6'b110100; 5'b11100 : pre_em_1po <= 6'b110110; 5'b11101 : pre_em_1po <= 6'b111000; 5'b11110 : pre_em_1po <= 6'b111100; 5'b11111 : pre_em_1po <= 6'b111111; default : pre_em_1po <= 6'b000000; endcase end else pre_em_1po <= 6'b000000; end // x2t_decode always @ ( rpre_em_2t or pdb ) begin if ( pdb == 1'b1 ) begin if ( rpre_em_2t == 4'b0000 ) pre_em_2po[5:1] <= 5'b00000; else pre_em_2po[5:1] <= {1'b1,rpre_em_2t}; end else pre_em_2po <= 5'b00000; end // xpr_decode always @ ( rpre_em_pt or pdb ) begin if ( pdb == 1'b1 ) begin if ( rpre_em_pt == 4'b0000 ) pre_em_pre[5:1] <= 5'b00000; else pre_em_pre[5:1] <= {1'b1,rpre_em_pt}; end else pre_em_pre <= 5'b00000; end // -- c_tx_testmux_dec -- always @ ( r_dft_sel ) case ( r_dft_sel ) 3'b0?? : dec2t4_en <= 4'b0000; 3'b100 : dec2t4_en <= 4'b0001; 3'b101 : dec2t4_en <= 4'b0010; 3'b110 : dec2t4_en <= 4'b0100; 3'b111 : dec2t4_en <= 4'b1000; default : dec2t4_en <= 4'b0000; endcase assign tx_dftout[6:1] = ( dec2t4_en[3] == 1'b1 ) ? {1'b0,pre_em_pre[5:1]} : ( dec2t4_en[2] == 1'b1 ) ? {1'b0,pre_em_2po[5:1]} : ( dec2t4_en[1] == 1'b1 ) ? pre_em_1po[6:1] : ( dec2t4_en[0] == 1'b1 ) ? vodsel[6:1] : 6'b000000; // used to be 6'bxxxxxx -- too pessimistic // -- c_tx_drv_buf xdrvbuf -- assign vodsel_pdrv = vodsel & {6{~tx_elec_idl}}; // -- c_tx_predrv xpredrv -- assign pd_idl = ~pdb | tx_elec_idl; // xmain_tap_mux always @ ( txden, rlpbk_en, vip, vin, rlpbkp, rlpbkn ) case ( {rlpbk_en,txden} ) 2'b00 : begin {mainp,mainn} <= 2'b01; end 2'b01 : begin {mainp,mainn} <= {vip,vin}; end 2'b10 : begin {mainp,mainn} <= {rlpbkp,rlpbkn}; end 2'b11 : begin {mainp,mainn} <= 2'bxx; end default : begin {mainp,mainn} <= 2'bxx; end endcase // xdrv0 assign vopos_pd[0] = (pd_idl === 1'b0) ? mainp : 1'b1; // slew fct is not implemented assign vopos_nd[0] = (pd_idl === 1'b0) ? mainp : 1'b0; assign voneg_pd[0] = (pd_idl === 1'b0) ? mainn : 1'b1; assign voneg_nd[0] = (pd_idl === 1'b0) ? mainn : 1'b0; // xdv_x6 - for driving strength assign vopos_pd[1] = vodsel_pdrv[1] ? mainp : 1'b1; // slew fct is not implemelted assign vopos_nd[1] = vodsel_pdrv[1] ? mainp : 1'b0; assign voneg_pd[1] = vodsel_pdrv[1] ? mainn : 1'b1; assign voneg_nd[1] = vodsel_pdrv[1] ? mainn : 1'b0; assign vopos_pd[2] = vodsel_pdrv[2] ? mainp : 1'b1; assign vopos_nd[2] = vodsel_pdrv[2] ? mainp : 1'b0; assign voneg_pd[2] = vodsel_pdrv[2] ? mainn : 1'b1; assign voneg_nd[2] = vodsel_pdrv[2] ? mainn : 1'b0; assign vopos_pd[3] = vodsel_pdrv[3] ? mainp : 1'b1; assign vopos_nd[3] = vodsel_pdrv[3] ? mainp : 1'b0; assign voneg_pd[3] = vodsel_pdrv[3] ? mainn : 1'b1; assign voneg_nd[3] = vodsel_pdrv[3] ? mainn : 1'b0; assign vopos_pd[4] = vodsel_pdrv[4] ? mainp : 1'b1; assign vopos_nd[4] = vodsel_pdrv[4] ? mainp : 1'b0; assign voneg_pd[4] = vodsel_pdrv[4] ? mainn : 1'b1; assign voneg_nd[4] = vodsel_pdrv[4] ? mainn : 1'b0; assign vopos_pd[5] = vodsel_pdrv[5] ? mainp : 1'b1; assign vopos_nd[5] = vodsel_pdrv[5] ? mainp : 1'b0; assign voneg_pd[5] = vodsel_pdrv[5] ? mainn : 1'b1; assign voneg_nd[5] = vodsel_pdrv[5] ? mainn : 1'b0; // * * x1post_drv, x2post_drv and xpre_drv not implemented * * // -- c_tx_drv xctxdrv -- assign vop = ( ~(&voneg_pd) & ~(&voneg_nd) ) ? 1'b1 : ( (|voneg_pd) & (|voneg_nd) ) ? 1'b0 : ( (|voneg_pd) & ~(&voneg_nd) ) ? 1'bz : ( tx_det_rx === 1'b1 ) ? 1'b0 : 1'bx; // 7 bits for driving strength - fct not implemented assign von = ( ~(&vopos_pd) & ~(&vopos_nd) ) ? 1'b1 : ( (|vopos_pd) & (|vopos_nd) ) ? 1'b0 : ( (|vopos_pd) & ~(&vopos_nd) ) ? 1'bz : ( tx_det_rx === 1'b1 ) ? 1'b0 : 1'bx; // * * C_RCV_DETECT * * stratixiv_hssi_pma_c_rcv_detect xi_rcv_det ( .com_pass(com_pass), .detect_on(detect_on), .fixed_clk_out(fixed_clk_out), .probe_pass(probe_pass), .rcv_det_pdb(rx_det_pdb), .rdet(r_rx_det), .rx_det_clk(rx_det_clk), .rx_det_valid(rx_detect_valid), .rx_found(rx_found), .sel_150r(sel_150r), .tx_det_rx(tx_det_rx), .rx_n(rx_n), .rx_p(rx_p) ); endmodule // stratixiv_hssi_pma_c_tx `timescale 1 ns / 1 ps module stratixiv_hssi_pma_ppmdetect (scan_mode, ppmsel, fref, fvcobyn, pd, hard_reset, rforcehigh, rforcelow, freq_lock, ppm_cnt_latch, ppm_cnt_reset); // MZ input scan_mode; // MZ input [5:0] ppmsel; // ppmsel setting ppmsel=6'b100000 <=> +/- 1000 PPM // ppmsel=6'b010000 <=> +/- 500 PPM // ppmsel=6'b001000 <=> +/- 300 PPM // ppmsel=6'b000100 <=> +/- 200 PPM // ppmsel=6'b000010 <=> +/- 125 PPM // ppmsel=6'b000001 <=> +/- 100 PPM input fref; // Reference clock input fvcobyn; // VCO divided clock input pd; // Power down input rforcehigh; // CRAM: force freq_lock high input rforcelow; // CRAM: force freq_lock low input hard_reset; // initialize all registers to one input ppm_cnt_reset; // reset ppm_cnt_latch register output freq_lock; // fref and fvcobyn are in range, set by ppmsel output [6:0] ppm_cnt_latch; // PPM difference, can be sent off-chip via testmux reg [15:0] ref_cnt; // 16-bit counter using fref clock reg [15:0] vco_cnt; // 16-bit counter using fvcobyn clock reg [3:0] eight_cnt; // counter used to delay the 16-bit counters reset by 8-cycles reg [6:0] ppm_cnt; // 6-bit counter used to count number of fref in open windows reg stable2, stable1, stable0; reg overflow_vco, overflow_vco1, overflow_vco2; reg freq_lock_pre; reg v65536v, v65536r; reg window0, window1; reg rst_div2, rst_div1, rst_div0; reg stay; reg rst_div_fref;//exists to delay the release of ref_cnt by one cycle. This will reduce the // the time difference between the start of ref_cnt and vco_cnt after the // release of rst_div. The time difference is due to rst_div being synchronized // to fvcobyn from fref domain. ref_cnt start up immediately and vco_cnt starts // 2 fvcobyn clock edges later. rst_div_fref will help reduce that 2 edge gap to // 1 edge. wire eight_cnt_0; wire eight_cnt_4; wire eight_cnt_8; wire window; wire freq_lock; wire ppm_cnt_reset; wire pd_sync_fref, pd_sync_fvcobyn; wire hard_reset_inv; reg [6:0] ppm_cnt_latch; assign eight_cnt_0 = ~|eight_cnt; assign eight_cnt_4 = ~eight_cnt[3] & eight_cnt[2] & ~eight_cnt[1] & ~eight_cnt[0]; assign eight_cnt_8 = eight_cnt[3] & ~eight_cnt[2] & ~eight_cnt[1] & ~eight_cnt[0]; assign window = v65536r ^ v65536v; // Inverting hard_reset because rxpma_rstb is active low assign hard_reset_inv = ~hard_reset; reg pd_sync_fref_pre, pd_sync_fref_b4scanmux, pd_sync_fvcobyn_pre, pd_sync_fvcobyn_b4scanmux; // MZ //Synchronize pd to fref always @(posedge hard_reset_inv or posedge fref) if (hard_reset_inv) begin pd_sync_fref_pre <= 1'b1; pd_sync_fref_b4scanmux <= 1'b1; // MZ end else begin pd_sync_fref_pre <= pd; pd_sync_fref_b4scanmux <= pd_sync_fref_pre; // MZ end assign pd_sync_fref = scan_mode ? 1'b0 : pd_sync_fref_b4scanmux; // MZ //Synchronize pd to fvcobyn always @(posedge hard_reset_inv or posedge fvcobyn) if (hard_reset_inv) begin pd_sync_fvcobyn_pre <= 1'b1; pd_sync_fvcobyn_b4scanmux <= 1'b1; // MZ end else begin pd_sync_fvcobyn_pre <= pd; pd_sync_fvcobyn_b4scanmux <= pd_sync_fvcobyn_pre; // MZ end assign pd_sync_fvcobyn = scan_mode ? 1'b0 : pd_sync_fvcobyn_b4scanmux; // MZ // This piece of code creates flags that reset the 16-bit counters, when they BOTH go // beyond 32768 (plus about 20 cycles) cycles. Before that they have to synchronized to // relevant clock domains. This resetting has to happen because when the PPM difference // is so low that the window signal is less than a fref clock period, it will be missed // and the counters will continue counting until it reaches all ONES. This is not desirable. reg overflow_ref; always @(posedge pd_sync_fref or posedge fref) if (pd_sync_fref) overflow_ref <= 1'b0; else overflow_ref <= (ref_cnt > 16'h8010) ? 1'b1 : 1'b0; always @(posedge pd_sync_fvcobyn or posedge fvcobyn) if (pd_sync_fvcobyn) overflow_vco <= 1'b0; else overflow_vco <= (vco_cnt > 16'h8010) ? 1'b1 : 1'b0; // After power down is released, the counters start counting. One counter may start several // thousand cycles after the other. So, after 128 cycles of fvcobyn, a signal called "stable" // is released. This will guarantee that fvcobyn was stable, before module operation started. always @(posedge pd_sync_fvcobyn or posedge fvcobyn) if (pd_sync_fvcobyn) stable0 <= 1'b0; else if (vco_cnt[15:0] == 16'b0000000011111111) stable0 <= 1'b1; //synchronize stable and overflow_vco to fref domain. "overflow_vco" will be used as one of the //cases when rst_div = 1 always @(posedge pd_sync_fref or posedge fref) if (pd_sync_fref) begin stable1 <= 1'b0; stable2 <= 1'b0; overflow_vco1 <= 1'b0; overflow_vco2 <= 1'b0; end else begin stable1 <= stable0; stable2 <= stable1; overflow_vco1 <= overflow_vco; overflow_vco2 <= overflow_vco1; end //synchronize rst_div to fvcobyn domain always @(posedge pd_sync_fvcobyn or posedge fvcobyn) if (pd_sync_fvcobyn) begin rst_div1 <= 1'b0; rst_div2 <= 1'b0; end else begin rst_div1 <= rst_div0; rst_div2 <= rst_div1; end //window1 is set to HIGH if clocks are stable ("stable2" = 1) and //window1 can be HIGH only when the 8 counter is not counting down. always @(posedge pd_sync_fref or posedge fref) begin if (pd_sync_fref) begin window0 <= 1'b0; window1 <= 1'b0; end else if (~stable2) begin window0 <= 1'b0; window1 <= 1'b0; end else begin window1 <= window0; if (eight_cnt_8 == 1) window0 <= window; else window0 <= 1'b0; end end // fref and fvcobyn counter reset always @(posedge pd_sync_fref or posedge fref) if (pd_sync_fref) begin rst_div0 <= 1'b0; rst_div_fref <= 1'b0; end else if (((eight_cnt > 0) && (eight_cnt < 8)) | (overflow_ref & overflow_vco2)) begin rst_div0 <= 1'b1; rst_div_fref <= rst_div0; end else begin rst_div0 <= 1'b0; rst_div_fref <= rst_div0; end //reset counters during PD_SYNC and during the clocking down of the 8 counter // fref counter always @(posedge pd_sync_fref or posedge fref) if (pd_sync_fref) begin ref_cnt <= 16'h0000; v65536r <= 1'b1; end else if (rst_div_fref) begin ref_cnt <= 16'h0000; v65536r <= 1'b1; end else begin ref_cnt <= ref_cnt + 1; v65536r <= ~(ref_cnt[15]); //ref_cnt[15] = 1 means 32,768 cycles have passed end // fvcobyn counter always @(posedge pd_sync_fvcobyn or posedge fvcobyn) if (pd_sync_fvcobyn) begin vco_cnt <= 16'h0000; v65536v <= 1'b1; end else if (rst_div2) begin vco_cnt <= 16'h0000; v65536v <= 1'b1; end else begin vco_cnt <= vco_cnt + 1; v65536v <= ~(vco_cnt[15]); //vco_cnt[15] = 1 means 32,768 cycles have passed end // count only after window ends. Then stop at 0 and reset to 8. // "stay" there until window goes high and low again. STAY is HIGH from // when WINDOW1 is HIGH to when EIGHT_CNT is 0. always @(posedge pd_sync_fref or posedge fref) if (pd_sync_fref) begin eight_cnt <= 4'h8; stay <= 1'b0; end else if(eight_cnt_0 == 1) begin eight_cnt <= 4'h8; stay <= 1'b0; end else if((window1 == 1) || (overflow_ref & overflow_vco2)) stay <= 1'b1; else if((window1 == 0) && (stay == 1)) begin eight_cnt <= eight_cnt - 1; end // PPM counter // using 6-bit counter to acount for setting of more than 1000PPM // starts counting when window starts, which is "upd_synctctr" // stops counting when window ends, which is when always @(posedge pd_sync_fref or posedge fref) begin if (pd_sync_fref) ppm_cnt <= 7'b0000000; // Avoiding the comparison after pd_sync else if (eight_cnt_0) ppm_cnt <= 7'b0000000; // If else if (ppm_cnt == 7'b1111111) ppm_cnt <= 7'b1111111; //Hold all Ones until eight_count_0 else if (window1 == 1'b1) //If window has been opened by FREF or FVCOBYN ppm_cnt <= ppm_cnt + 1; end // freq_lock_pre detection // Perfom the comparison 4 clock cycles before reseting the 16-bit counters always @(posedge pd_sync_fref or posedge fref) begin if (pd_sync_fref) begin freq_lock_pre <= 1'b0; end else if (eight_cnt_4) begin // ppmsel setting ppmsel=6'b100000 <=> +/- 1000 PPM // ppmsel=6'b010000 <=> +/- 500 PPM // ppmsel=6'b001000 <=> +/- 300 PPM // ppmsel=6'b001001 <=> +/- 250 PPM // ppmsel=6'b000100 <=> +/- 200 PPM // ppmsel=6'b000010 <=> +/- 125 PPM // ppmsel=6'b000001 <=> +/- 100 PPM // ppmsel=6'b000011 <=> +/- 62.5 PPM freq_lock_pre <=(((eight_cnt_4 == 1) && (ppmsel == 6'b100000) && (ppm_cnt <= 7'd67)) || // +/- 1000 PPM ((eight_cnt_4 == 1) && (ppmsel == 6'b010000) && (ppm_cnt <= 7'd34)) || // +/- 500 PPM ((eight_cnt_4 == 1) && (ppmsel == 6'b001000) && (ppm_cnt <= 7'd21)) || // +/- 300 PPM ((eight_cnt_4 == 1) && (ppmsel == 6'b001001) && (ppm_cnt <= 7'd18)) || // +/- 250 PPM ((eight_cnt_4 == 1) && (ppmsel == 6'b000100) && (ppm_cnt <= 7'd15)) || // +/- 200 PPM ((eight_cnt_4 == 1) && (ppmsel == 6'b000010) && (ppm_cnt <= 7'd10)) || // +/- 125 PPM ((eight_cnt_4 == 1) && (ppmsel == 6'b000001) && (ppm_cnt <= 7'd8)) || // +/- 100 PPM ((eight_cnt_4 == 1) && (ppmsel == 6'b000011) && (ppm_cnt <= 7'd6)) || // +/- 62.5 PPM ((eight_cnt_4 == 1) && (ppmsel == 6'b111111) )) ? 1'b1 : 1'b0; end end always @(posedge pd_sync_fref or posedge fref) begin if (pd_sync_fref) ppm_cnt_latch <= 7'b0000000; else if (ppm_cnt_reset) ppm_cnt_latch <= 7'b0000000; else if (eight_cnt_4) ppm_cnt_latch <= ppm_cnt; end //CRAM bits force HIGH or LOW on to freq_lock. This serves as module bypass. assign freq_lock = rforcehigh ? 1'b1 : (rforcelow ? 1'b0 : freq_lock_pre); endmodule //====Revision Log================ //Rev: 1.2 Thu May 22 18:17:56 PDT 2008 cgaillar //Updated after Allen's cosim feeback //====End Log====================== module stratixiv_hssi_pma_c_ser_10g ( clk_divtx, clk_skew, cpulse, cpulseb, data_in, hfclkn, hfclkp, lbvon, lbvop, lfclkn, lfclkp, pdb, pre_em, rst_n, s_lpbk, vccelxqyx, vccetxqyx, von, von_op1, vop, vop_op1, vssexqyx ); input [2:0] clk_skew; input cpulse; input cpulseb; input [63:0] data_in; input hfclkn; input hfclkp; input lfclkn; input lfclkp; input pdb; input [4:0] pre_em; input rst_n; input s_lpbk; input vccelxqyx; input vccetxqyx; input vssexqyx; output clk_divtx; output lbvon; output lbvop; output von; output von_op1; output vop; output vop_op1; parameter PARAM_DELAY = 0; reg [7:0] do8; reg core_clk, lfclkp_div_init_done, out_lb_reg, outb_lb_reg, out_e, out_o; reg [7:0] data_mux4t1_sync1, cpulse_x8_bus; reg [3:0] do_mux4t1_sync2, de_mux4t1_sync2; reg c0_even, c1_even, c2_even, c3_even, cp; reg cp_odd, c0_odd, c1_odd, c2_odd, c3_odd, cpulse_x8; reg oo1, oe1, vop_reg, von_reg, vop_op1_reg, von_op1_reg; reg [63:0] data_sync, do64; wire lben; wire pre_en, s_lpbkbuf; wire rst_nbuf; wire pe; integer lfclkp_counter; assign pre_en = |pre_em; assign s_lpbkbuf = pdb & s_lpbk; assign rst_nbuf = pdb & rst_n; assign clk_divtx = core_clk; initial begin data_mux4t1_sync1 <= 8'b0000_0000; de_mux4t1_sync2[3:0] <= 4'b0000; do_mux4t1_sync2[3:0] <= 4'b0000; vop_op1_reg <= 1'b0; von_op1_reg <= 1'b1; vop_reg <= 1'b0; von_reg <= 1'b1; out_lb_reg <= 1'b0; outb_lb_reg <= 1'b1; {out_o, out_e} <= 2'b00; {oo1, oe1} <= 2'b00; {c0_even,c1_even,c2_even,c3_even} <= 4'b0000; {c0_odd,c1_odd,c2_odd,c3_odd} <= 4'b0000; do8 <= 8'b0000_0000; {cpulse_x8_bus[6:0],cp,cpulse_x8} <= 9'b0_0000_0000; data_sync <= 64'b0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000; do64 <= 64'b0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000; do8 <= 8'b0000_0000; lfclkp_counter = 0; lfclkp_div_init_done = 1'b0; end // * * c_div8_10g * * always @ ( posedge lfclkp or negedge rst_nbuf ) begin if ( rst_nbuf == 1'b0 ) begin lfclkp_counter <= 0; lfclkp_div_init_done <= 1'b0; core_clk <= 1'b0; end else begin // after one cycle of lfclkp, if set, reset cpulse_x8 if ( lfclkp == 1'b1 & cpulse_x8 == 1'b1 ) cpulse_x8 <= 1'b0; if ( lfclkp_div_init_done == 1'b0 ) begin core_clk <= 1'b1; lfclkp_div_init_done <= 1'b1; end else begin // generation of core_clk if ( lfclkp_counter % 4 == 0 ) begin core_clk <= ~core_clk; if ( core_clk == 1'b0 ) cpulse_x8 <= 1'b1; end end lfclkp_counter <= lfclkp_counter + 1; end end // * * c_mux64to8_10g * * // - cpulse_8x8_gen - always @ ( posedge lfclkp or negedge rst_nbuf ) begin if ( rst_nbuf == 1'b0 ) {cpulse_x8_bus[7:0],cp} <= #(PARAM_DELAY) 9'b0_0000_0000; else {cpulse_x8_bus[7:0],cp} <= #(PARAM_DELAY) {cpulse_x8_bus[6:0],cp,cpulse_x8}; end // - c_64bit_reg_10g - always @ ( posedge core_clk ) data_sync <= #(PARAM_DELAY) data_in; // - c_32bit_reg_10g bits[63:32] - always @ ( posedge core_clk ) do64[63:32] <= #(PARAM_DELAY) data_sync[63:32]; // - c_32bit_reg_10g bits[31:0] - always @ ( negedge core_clk ) do64[31:0] <= #(PARAM_DELAY) data_sync[31:0]; // - a_8bit_tri_reg - always @ ( posedge cpulse_x8_bus[4] or negedge rst_nbuf ) if ( ~rst_nbuf ) do8 <= #(PARAM_DELAY) 8'b0000_0000; else do8 <= #(PARAM_DELAY) do64[7:0]; always @ ( posedge cpulse_x8_bus[5] or negedge rst_nbuf ) if ( ~rst_nbuf ) do8 <= #(PARAM_DELAY) 8'b0000_0000; else do8 <= #(PARAM_DELAY) do64[15:8]; always @ ( posedge cpulse_x8_bus[6] or negedge rst_nbuf ) if ( ~rst_nbuf ) do8 <= #(PARAM_DELAY) 8'b0000_0000; else do8 <= #(PARAM_DELAY) do64[23:16]; always @ ( posedge cpulse_x8_bus[7] or negedge rst_nbuf ) if ( ~rst_nbuf ) do8 <= #(PARAM_DELAY) 8'b0000_0000; else do8 <= #(PARAM_DELAY) do64[31:24]; always @ ( posedge cpulse_x8_bus[0] or negedge rst_nbuf ) if ( ~rst_nbuf ) do8 <= #(PARAM_DELAY) 8'b0000_0000; else do8 <= #(PARAM_DELAY) do64[39:32]; always @ ( posedge cpulse_x8_bus[1] or negedge rst_nbuf ) if ( ~rst_nbuf ) do8 <= #(PARAM_DELAY) 8'b0000_0000; else do8 <= #(PARAM_DELAY) do64[47:40]; always @ ( posedge cpulse_x8_bus[2] or negedge rst_nbuf ) if ( ~rst_nbuf ) do8 <= #(PARAM_DELAY) 8'b0000_0000; else do8 <= #(PARAM_DELAY) do64[55:48]; always @ ( posedge cpulse_x8_bus[3] or negedge rst_nbuf ) if ( ~rst_nbuf ) do8 <= #(PARAM_DELAY) 8'b0000_0000; else do8 <= #(PARAM_DELAY) do64[63:56]; // * * stratixiv_hssi_pma_c_ser_mux4to1 -- xmux4to1_even & odd instances * * // Pipe #1 - synchronize data to lfclkp negedge always @ ( posedge lfclkn or negedge rst_nbuf ) if ( lfclkn == 1'b1 ) data_mux4t1_sync1 <= #(PARAM_DELAY) do8; else data_mux4t1_sync1 <= #(PARAM_DELAY) 8'b0000_0000; // Pipe #2 - Synchronize 0,2 and 1,3 to CLK and CLKB ; 6,8 and 5,7 to CLK and CLKB always @ ( posedge lfclkp or negedge rst_nbuf ) if ( lfclkp == 1'b1 ) begin de_mux4t1_sync2[1:0] <= #(PARAM_DELAY) {data_mux4t1_sync1[2],data_mux4t1_sync1[0]}; do_mux4t1_sync2[1:0] <= #(PARAM_DELAY) {data_mux4t1_sync1[3],data_mux4t1_sync1[1]}; end else begin de_mux4t1_sync2[1:0] <= #(PARAM_DELAY) 2'b00; do_mux4t1_sync2[1:0] <= #(PARAM_DELAY) 2'b00; end always @ ( posedge lfclkn or negedge rst_nbuf ) if ( lfclkn == 1'b1 ) begin de_mux4t1_sync2[3:2] <= #(PARAM_DELAY) {data_mux4t1_sync1[6],data_mux4t1_sync1[4]}; do_mux4t1_sync2[3:2] <= #(PARAM_DELAY) {data_mux4t1_sync1[7],data_mux4t1_sync1[5]}; end else begin de_mux4t1_sync2[3:2] <= #(PARAM_DELAY) 2'b00; do_mux4t1_sync2[3:2] <= #(PARAM_DELAY) 2'b00; end // Pulse generation for odd and even - CPULSE, CP, C0, ..., C3 always @ ( posedge hfclkn or negedge rst_nbuf ) if ( hfclkn == 1'b1 ) begin c0_even <= #(PARAM_DELAY) cpulse; c1_even <= #(PARAM_DELAY) c0_even; c2_even <= #(PARAM_DELAY) c1_even; c3_even <= #(PARAM_DELAY) c2_even; end else {c3_even,c2_even,c1_even,c0_even} <= #(PARAM_DELAY) 4'b0000; always @ ( posedge hfclkn or negedge rst_nbuf ) // Mux Odd if ( ~rst_nbuf ) cp_odd <= #(PARAM_DELAY) 1'b0; else cp_odd <= #(PARAM_DELAY) cpulse; always @ ( posedge hfclkp or negedge rst_nbuf ) if ( hfclkp == 1'b1 ) begin c0_odd <= #(PARAM_DELAY) cp_odd; c1_odd <= #(PARAM_DELAY) c0_odd; c2_odd <= #(PARAM_DELAY) c1_odd; c3_odd <= #(PARAM_DELAY) c2_odd; end else {c3_odd,c2_odd,c1_odd,c0_odd} <= #(PARAM_DELAY) 4'b0000; // Mux2to1 Even outputs always @ ( posedge c0_even ) if ( c0_even == 1'b1 ) begin out_e <= #(PARAM_DELAY) de_mux4t1_sync2[0]; end always @ ( posedge c1_even ) if ( c1_even == 1'b1 ) begin out_e <= #(PARAM_DELAY) de_mux4t1_sync2[1]; end always @ ( posedge c2_even ) if ( c2_even == 1'b1 ) begin out_e <= #(PARAM_DELAY) de_mux4t1_sync2[2]; end always @ ( posedge c3_even ) if ( c3_even == 1'b1 ) begin out_e <= #(PARAM_DELAY) de_mux4t1_sync2[3]; end // Mux2to1 Odd outputs always @ ( posedge c0_odd ) if ( c0_odd == 1'b1 ) begin out_o <= #(PARAM_DELAY) do_mux4t1_sync2[0]; end always @ ( posedge c1_odd ) if ( c1_odd == 1'b1 ) begin out_o <= #(PARAM_DELAY) do_mux4t1_sync2[1]; end always @ ( posedge c2_odd ) if ( c2_odd == 1'b1 ) begin out_o <= #(PARAM_DELAY) do_mux4t1_sync2[2]; end always @ ( posedge c3_odd ) if ( c3_odd == 1'b1 ) begin out_o <= #(PARAM_DELAY) do_mux4t1_sync2[3]; end // * * stratixiv_hssi_pma_c_ser_mux2to1 -- xmux2to1 instance * * assign pe = pre_en & rst_nbuf & pdb; assign vop = pdb ? vop_reg : 1'b1; assign von = pdb ? von_reg : 1'b1; assign vop_op1 = pe ? vop_op1_reg : 1'b1; assign von_op1 = pe ? von_op1_reg : 1'b1; always @ ( posedge hfclkn or negedge rst_nbuf ) if ( rst_nbuf == 1'b0 ) oe1 <= #(PARAM_DELAY) 1'b0; else oe1 <= #(PARAM_DELAY) out_e; always @ ( posedge hfclkp or negedge rst_nbuf ) if ( rst_nbuf == 1'b0 ) oo1 <= #(PARAM_DELAY) 1'b0; else oo1 <= #(PARAM_DELAY) out_o; always @ ( posedge hfclkp ) if ( hfclkp == 1'b1 & pdb == 1'b1) begin vop_reg <= #(PARAM_DELAY) out_o; von_reg <= #(PARAM_DELAY) ~out_o; end always @ ( posedge hfclkn ) if ( hfclkn == 1'b1 & pdb == 1'b1 ) begin vop_reg <= #(PARAM_DELAY) out_e; von_reg <= #(PARAM_DELAY) ~out_e; end always @ ( posedge hfclkp ) if ( hfclkp == 1'b1 & pe == 1'b1) begin vop_op1_reg <= #(PARAM_DELAY) oe1; von_op1_reg <= #(PARAM_DELAY) ~oe1; end always @ ( posedge hfclkn ) if ( hfclkn == 1'b1 & pe == 1'b1 ) begin vop_op1_reg <= #(PARAM_DELAY) oo1; von_op1_reg <= #(PARAM_DELAY) ~oo1; end // * * stratixiv_hssi_pma_c_ser_mux2to1_lb -- xmux2to1_lb instance * * assign lben = pdb & s_lpbkbuf; assign lbvop = lben ? out_lb_reg : 1'b1; assign lbvon = lben ? outb_lb_reg : 1'b1; always @ ( posedge hfclkn ) if ( hfclkn == 1'b1 & lben == 1'b1 ) begin out_lb_reg <= #(PARAM_DELAY) out_e; outb_lb_reg <= #(PARAM_DELAY) ~out_e; end always @ ( posedge hfclkp ) if ( hfclkp == 1'b1 & lben == 1'b1 ) begin out_lb_reg <= #(PARAM_DELAY) out_o; outb_lb_reg <= #(PARAM_DELAY) ~out_o; end endmodule // stratixiv_hssi_pma_c_ser_10g //====Revision Log================ //Rev: 1.3 Fri Apr 25 17:08:38 PDT 2008 cgaillar //Removed clk270 input port // //Rev: 1.2 Fri Feb 29 09:57:15 PST 2008 cgaillar //Updated mapping on 64 to 8 mux //====End Log====================== module stratixiv_hssi_pma_c_deser_10g ( clk90b, clk_divrx, deser_pdb, deven, devenb, dodd, doddb, dout, rst_n, vcce_la, vssexqyx ); input clk90b; input deser_pdb; input deven; input devenb; input dodd; input doddb; input rst_n; input vcce_la; input vssexqyx; output clk_divrx; output [63:0] dout; parameter PARAM_DELAY = 0; integer clk90_counter, clk270_counter, ph2_counter; reg clk90_div_init_done, clk90_div4, clk270_div_init_done, clk270_div4, ph2_div_init_done, ph2_div8; reg [3:0] ph, dsync; reg [7:0] dp, doutp, doutn, ph8; reg [63:0] dout, dout_int, dsync8; wire clk90, clk270; assign clk90 = ~clk90b; assign clk270 = clk90b; initial begin clk90_div_init_done <= 1'b0; clk270_div_init_done <= 1'b0; ph2_div_init_done <= 1'b0; clk90_counter <= 0; clk270_counter <= 0; ph2_counter <= 0; clk90_div4 <= 1'b0; clk270_div4 <= 1'b0; ph2_div8 <= 1'b0; end // * * c_deser_2to8_10g * * // - c_deser_divby4_10g - always @ ( posedge clk90 or negedge rst_n ) begin if ( rst_n == 1'b0 ) begin clk90_counter <= 0; clk90_div_init_done <= 1'b0; clk90_div4 <= 1'b0; end else begin if ( clk90_div_init_done == 1'b0 ) begin clk90_div4 <= 1'b1; clk90_div_init_done <= 1'b1; end else begin // generation of clk90_div4 if ( clk90_counter % 2 == 0 ) clk90_div4 <= ~clk90_div4; end clk90_counter <= clk90_counter + 1; end end // clk270_div4 should not start toggling before clk90_div4 always @ ( clk270 or negedge rst_n ) begin if ( rst_n == 1'b0 ) begin clk270_counter <= 0; clk270_div_init_done <= 1'b0; clk270_div4 <= 1'b0; end else if ( clk90_div_init_done == 1'b1 ) begin // generation of clk270_div4 if ( ( clk270 == 1'b1 ) & ( clk270_counter % 4 == 0 ) ) begin if ( clk270_div_init_done == 1'b0 ) begin clk270_div4 <= 1'b1; clk270_div_init_done <= 1'b1; end else clk270_div4 <= ~clk270_div4; end clk270_counter <= clk270_counter + 1; end end always @ ( negedge rst_n or posedge clk270 ) if ( ~rst_n ) ph[3:0] <= #(PARAM_DELAY) 4'b0000; else ph[3:0] <= #(PARAM_DELAY) {ph[2:0],clk270_div4}; // - 1 to 4 demux - // Shift register always @ ( negedge rst_n or posedge ph[0] ) if ( ~rst_n ) dp[1:0] <= #(PARAM_DELAY) 2'b00; else dp[1:0] <= #(PARAM_DELAY) {dodd,deven}; always @ ( negedge rst_n or posedge ph[1] ) if ( ~rst_n ) dp[3:2] <= #(PARAM_DELAY) 2'b00; else dp[3:2] <= #(PARAM_DELAY) {dodd,deven}; always @ ( negedge rst_n or posedge ph[2] ) if ( ~rst_n ) dp[5:4] <= #(PARAM_DELAY) 2'b00; else dp[5:4] <= #(PARAM_DELAY) {dodd,deven}; always @ ( negedge rst_n or posedge ph[3] ) if ( ~rst_n ) dp[7:6] <= #(PARAM_DELAY) 2'b00; else dp[7:6] <= #(PARAM_DELAY) {dodd,deven}; // dp[0,1,2,3] synchronization always @ ( negedge rst_n or negedge ph[0] ) if ( ~rst_n ) dsync[3:0] <= #(PARAM_DELAY) 4'b0000; else dsync[3:0] <= #(PARAM_DELAY) dp[3:0]; always @ ( negedge rst_n or posedge ph[0] ) if ( ~rst_n ) begin doutp[7:0] <= #(PARAM_DELAY) 8'b0000_0000; doutn[7:0] <= #(PARAM_DELAY) 8'b0000_0000; end else begin doutp[7:0] <= #(PARAM_DELAY) {dp[7:4],dsync[3:0]}; doutn[7:0] <= #(PARAM_DELAY) ~{dp[7:4],dsync[3:0]}; end // * * c_deser_8to64_10g * * // - c_deser_divby8_10g - always @ ( posedge ph[2] or negedge rst_n ) begin if ( rst_n == 1'b0 ) begin ph2_counter <= 0; ph2_div_init_done <= 1'b0; ph2_div8 <= 1'b0; end else begin if ( ph2_div_init_done == 1'b0 ) begin ph2_div8 <= 1'b1; ph2_div_init_done <= 1'b1; end else begin // generation of ph2_div8 if ( ph2_counter % 4 == 0 ) ph2_div8 <= ~ph2_div8; end ph2_counter <= ph2_counter + 1; end end always @ ( negedge rst_n or posedge ph[2] ) if ( ~rst_n ) ph8[7:0] <= #(PARAM_DELAY) 8'b0000_0000; else ph8[7:0] <= #(PARAM_DELAY) {ph8[6:0],ph2_div8}; // - c_deser_by8_8_10g - assign clk_divrx = ph8[0]; always @ ( negedge rst_n or posedge ph8[0] ) if ( ~rst_n ) dout_int[7:0] <= #(PARAM_DELAY) 8'b0000_0000; else dout_int[7:0] <= #(PARAM_DELAY) doutp[7:0]; always @ ( negedge rst_n or posedge ph8[1] ) if ( ~rst_n ) dout_int[15:8] <= #(PARAM_DELAY) 8'b0000_0000; else dout_int[15:8] <= #(PARAM_DELAY) doutp[7:0]; always @ ( negedge rst_n or posedge ph8[2] ) if ( ~rst_n ) dout_int[23:16] <= #(PARAM_DELAY) 8'b0000_0000; else dout_int[23:16] <= #(PARAM_DELAY) doutp[7:0]; always @ ( negedge rst_n or posedge ph8[3] ) if ( ~rst_n ) dout_int[31:24] <= #(PARAM_DELAY) 8'b0000_0000; else dout_int[31:24] <= #(PARAM_DELAY) doutp[7:0]; always @ ( negedge rst_n or posedge ph8[4] ) if ( ~rst_n ) dout_int[39:32] <= #(PARAM_DELAY) 8'b0000_0000; else dout_int[39:32] <= #(PARAM_DELAY) doutp[7:0]; always @ ( negedge rst_n or posedge ph8[5] ) if ( ~rst_n ) dout_int[47:40] <= #(PARAM_DELAY) 8'b0000_0000; else dout_int[47:40] <= #(PARAM_DELAY) doutp[7:0]; always @ ( negedge rst_n or posedge ph8[6] ) if ( ~rst_n ) dout_int[55:48] <= #(PARAM_DELAY) 8'b0000_0000; else dout_int[55:48] <= #(PARAM_DELAY) doutp[7:0]; always @ ( negedge rst_n or posedge ph8[7] ) if ( ~rst_n ) dout_int[63:56] <= #(PARAM_DELAY) 8'b0000_0000; else dout_int[63:56] <= #(PARAM_DELAY) doutp[7:0]; always @ ( negedge rst_n or posedge ph8[7] ) if ( ~rst_n ) begin dsync8[ 7: 0] <= #(PARAM_DELAY) 8'b0000_0000; dsync8[15: 8] <= #(PARAM_DELAY) 8'b0000_0000; dsync8[23:16] <= #(PARAM_DELAY) 8'b0000_0000; dsync8[31:24] <= #(PARAM_DELAY) 8'b0000_0000; end else begin dsync8[ 7: 0] <= #(PARAM_DELAY) dout_int[ 7: 0]; dsync8[15: 8] <= #(PARAM_DELAY) dout_int[15: 8]; dsync8[23:16] <= #(PARAM_DELAY) dout_int[23:16]; dsync8[31:24] <= #(PARAM_DELAY) dout_int[31:24]; end always @ ( negedge rst_n or posedge clk_divrx ) if ( ~rst_n ) dout[63:0] <= #(PARAM_DELAY) 64'b0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000; else dout[63:0] <= #(PARAM_DELAY) {dout_int[63:32],dsync8[31:0]}; endmodule // stratixiv_hssi_pma_c_deser_10g //====Revision Log================ //Rev: 1.13 Wed Jun 18 11:42:18 PDT 2008 cgaillar //Removed all 1'b1 & 1'b0 from instances. Added ifdef COSIM flag to change delay parameter from 1 to 0.05 and 2 to 0.1 //====End Log====================== module stratixiv_hssi_pma_c_pcie_sw ( cpulse, cpulse_out, cpulseb, cpulsei, dynamic_sw, gen2ngen1, hclk, hfclkn, hfclkn_out, hfclkp, hfclkp_out, lfclkn, lfclkn_out, lfclkp, lfclkp_out, pcie_sw, pcie_sw_cdr, pclk, pdb, rst_n, vccelxqyx, vssexqyx, div5 ); input cpulse; input cpulseb; input cpulsei; input dynamic_sw; input hfclkn; input hfclkp; input lfclkn; input lfclkp; input pcie_sw; input pdb; input rst_n; input vccelxqyx; input vssexqyx; input div5; output cpulse_out; output gen2ngen1; output hclk; output hfclkn_out; output hfclkp_out; output lfclkn_out; output lfclkp_out; output pcie_sw_cdr; output pclk; parameter PARAM_DELAY = 0; wire nclri, clk_selectb, div2_enlf; wire lfclk0_div2, lfclk90_div2, lfclk180_div2, lfclk270_div2; wire lfclk0_div2_int, lfclk90_div2_int, lfclk180_div2_int, lfclk270_div2_int; wire hfclk0_div2, hfclk90_div2, hfclk180_div2, hfclk270_div2; wire cpulse_div2, cpulse_div2_int; reg div2_enhf, div2_enhf_reg; integer counter_hfclk0_div2; // integer cpulse_div2_counter; initial begin div2_enhf = 1'b0; div2_enhf_reg = 1'b0; // cpulse_div2_counter = 0; counter_hfclk0_div2 = 0; end always @ ( negedge hfclkp or negedge rst_n ) if ( rst_n == 1'b0) div2_enhf_reg <= 1'b0; else div2_enhf_reg <= div2_enhf; stratixiv_hssi_pma_c_divby2q xhf ( .clk(hfclkp), .clk0(hfclk0_div2), .clk90(hfclk90_div2), .clk180(hfclk180_div2), .vcce_la(vccelxqyx), .vssexqyx(vssexqyx), .clk270(hfclk270_div2), .clkb(hfclkn), .rst_n(div2_enhf_reg) ); stratixiv_hssi_pma_c_divby2q xlf ( .clk(lfclkp), .clk0(lfclk0_div2_int), .clk90(lfclk90_div2_int), .clk180(lfclk180_div2_int), .vcce_la(vccelxqyx), .vssexqyx(vssexqyx), .clk270(lfclk270_div2_int), .clkb(lfclkn), .rst_n(vccelxqyx) ); assign hclk = ~(~lfclkp & rst_n); assign pclk = lfclkp_out; assign clk_selectb = div2_enhf_reg; assign gen2ngen1 = nclri ? ~div2_enhf_reg : 1'b0; assign nclri = dynamic_sw & rst_n; assign pcie_sw_cdr = ~pcie_sw & dynamic_sw & rst_n; assign {lfclk0_div2,lfclk90_div2,lfclk180_div2,lfclk270_div2} = div2_enhf_reg ? {lfclk0_div2_int,lfclk90_div2_int,lfclk180_div2_int,lfclk270_div2_int} : 4'b0000; assign {hfclkp_out,hfclkn_out,cpulse_out,lfclkp_out,lfclkn_out} = ~pdb ? 5'b01_0_01 : ~clk_selectb ? {hfclkp,hfclkn,cpulse,lfclkp,lfclkn} : {hfclk0_div2,hfclk180_div2,cpulse_div2&lfclk0_div2,lfclk0_div2,lfclk180_div2}; // cpulse_div2 generation assign cpulse_div2_int = ( ~div5 && (counter_hfclk0_div2 % 4 == 1) || div5 && (counter_hfclk0_div2 % 5 == 1) ) ? 1'b1 : 1'b0; assign cpulse_div2 = cpulse_div2_int & lfclk0_div2; always @ ( posedge hfclk0_div2 or negedge div2_enhf_reg ) if (div2_enhf_reg == 1'b0) counter_hfclk0_div2 <= 0; else if (div2_enhf_reg == 1'b1) counter_hfclk0_div2 <= counter_hfclk0_div2 + 1; // - stratixiv_hssi_pma_c_deglitch - // Synchronization with lclk270 _div2 always @ ( posedge lfclk270_div2_int or negedge rst_n ) if ( rst_n == 1'b0) div2_enhf <= 1'b0; else if($time > 0) div2_enhf <= pcie_sw_cdr; endmodule // stratixiv_hssi_pma_c_pcie_sw //====Revision Log================ //Rev: 1.1 Tue Sep 2 10:28:39 PDT 2008 cgaillar //Initial C5 version // //Rev: 1.2 Fri Apr 25 17:28:54 PDT 2008 cgaillar //Replaced 1'b1 & 1'b0 with vcc* & vss* in instances derived from schematics //====End Log====================== module stratixiv_hssi_pma_c_clkgendrv_tx10g ( clk0, clk180, cpulse, cpulseb, hfclk_n, hfclk_p, lfclk_n, lfclk_p, rst_n, vccelxqyx, vssexqyx ); input clk0; input clk180; input rst_n; input vccelxqyx; input vssexqyx; output cpulse; output cpulseb; output hfclk_n; output hfclk_p; output lfclk_n; output lfclk_p; wire nc2; stratixiv_hssi_pma_c_clkgendrv xdrv ( .clk0(clk0), .clk90(1'b0), .clk180(clk180), .clk270(1'b1), .cpulse(cpulse), .cpulseb(cpulseb), .cpulseo(nc2), .div5(1'b0), .hfclk_n(hfclk_n), .hfclk_p(hfclk_p), .lfclk_n(lfclk_n), .lfclk_p(lfclk_p), .rst_n(rst_n), .vccelxqyx(vccelxqyx), .vssexqyx(vssexqyx) ); endmodule // stratixiv_hssi_pma_c_clkgendrv_tx10g //====Revision Log================ //Rev: 1.1 Tue Sep 2 10:28:40 PDT 2008 cgaillar //Initial C5 version // //Rev: 1.1 Fri Apr 25 12:04:06 PDT 2008 cgaillar //Updates to match g_gx_clean_ww16 PMA / g_hssi_ww17 HSSI tags // //====End Log====================== module stratixiv_hssi_pma_c_clkgenbuf_tx10g ( clk0_in, clk180_in, cpulse, cpulseb, hfclk_n, hfclk_p, lfclk_n, lfclk_p, rst_n, vccelxqyx, vssexqyx ); input clk0_in; input clk180_in; input rst_n; input vccelxqyx; input vssexqyx; output cpulse; output cpulseb; output hfclk_n; output hfclk_p; output lfclk_n; output lfclk_p; wire clk0_out, clk180_out; assign clk0_out = clk0_in; assign clk180_out = clk180_in; stratixiv_hssi_pma_c_clkgendrv_tx10g xdrv ( .clk0(clk0_out), .clk180(clk180_out), .cpulse(cpulse), .cpulseb(cpulseb), .hfclk_n(hfclk_n), .hfclk_p(hfclk_p), .lfclk_n(lfclk_n), .lfclk_p(lfclk_p), .rst_n(rst_n), .vccelxqyx(vccelxqyx), .vssexqyx(vssexqyx) ); endmodule // stratixiv_hssi_pma_c_clkgenbuf_tx10g // *********************************************************** // This WYSIWYG atom header was automatically generated by the // Atmgen build tool. To change it, alter data stored in the // corresponding WYS file(s) in the tools/atmgen subdirectory. // *********************************************************** // *** Section 1 -- Header *** // ----------------------------------------------------------- // // Module Name : stratixiv_hssi_clock_divider // // Description : DEV_FAMILY_STRATIXIV stratixiv_hssi_clock_divider Verilog simulation model // // ----------------------------------------------------------- `timescale 1 ps/1 ps // *** End of Section 1 *** // *** Section 3 -- Module declaration *** module stratixiv_hssi_clock_divider( clk0in, clk1in, dpriodisable, dprioin, powerdn, quadreset, rateswitch, rateswitchbaseclkin, rateswitchdonein, refclkdig, refclkin, vcobypassin, analogfastrefclkout, analogfastrefclkoutshifted, analogrefclkout, analogrefclkoutshifted, analogrefclkpulse, analogrefclkpulseshifted, coreclkout, dprioout, rateswitchbaseclock, rateswitchdone, rateswitchout, refclkout ); // *** End of Section 3 *** // *** Section 4 -- Port size declarations *** // Note: Variable port sizes dictated by parameters are not currently defined in // the WYS file data. Busses are marked with the VARIABLE notation as a reminder. `define ANALOGFASTREFCLKOUT_PORTSIZE_CONST_stratixiv_hssi_clock_divider 2 // * VARIABLE `define ANALOGFASTREFCLKOUTSHIFTED_PORTSIZE_CONST_stratixiv_hssi_clock_divider 2 // * VARIABLE `define ANALOGREFCLKOUT_PORTSIZE_CONST_stratixiv_hssi_clock_divider 2 // * VARIABLE `define ANALOGREFCLKOUTSHIFTED_PORTSIZE_CONST_stratixiv_hssi_clock_divider 2 // * VARIABLE `define ANALOGREFCLKPULSE_PORTSIZE_CONST_stratixiv_hssi_clock_divider 1 `define ANALOGREFCLKPULSESHIFTED_PORTSIZE_CONST_stratixiv_hssi_clock_divider 1 `define CLK0IN_PORTSIZE_CONST_stratixiv_hssi_clock_divider 4 // * VARIABLE `define CLK1IN_PORTSIZE_CONST_stratixiv_hssi_clock_divider 4 // * VARIABLE `define CORECLKOUT_PORTSIZE_CONST_stratixiv_hssi_clock_divider 1 `define DPRIODISABLE_PORTSIZE_CONST_stratixiv_hssi_clock_divider 1 `define DPRIOIN_PORTSIZE_CONST_stratixiv_hssi_clock_divider 100 `define DPRIOOUT_PORTSIZE_CONST_stratixiv_hssi_clock_divider 100 `define POWERDN_PORTSIZE_CONST_stratixiv_hssi_clock_divider 1 `define QUADRESET_PORTSIZE_CONST_stratixiv_hssi_clock_divider 1 `define RATESWITCH_PORTSIZE_CONST_stratixiv_hssi_clock_divider 1 `define RATESWITCHBASECLKIN_PORTSIZE_CONST_stratixiv_hssi_clock_divider 2 // * VARIABLE `define RATESWITCHBASECLOCK_PORTSIZE_CONST_stratixiv_hssi_clock_divider 1 `define RATESWITCHDONE_PORTSIZE_CONST_stratixiv_hssi_clock_divider 1 `define RATESWITCHDONEIN_PORTSIZE_CONST_stratixiv_hssi_clock_divider 2 // * VARIABLE `define RATESWITCHOUT_PORTSIZE_CONST_stratixiv_hssi_clock_divider 1 `define REFCLKDIG_PORTSIZE_CONST_stratixiv_hssi_clock_divider 1 `define REFCLKIN_PORTSIZE_CONST_stratixiv_hssi_clock_divider 2 // * VARIABLE `define REFCLKOUT_PORTSIZE_CONST_stratixiv_hssi_clock_divider 1 `define VCOBYPASSIN_PORTSIZE_CONST_stratixiv_hssi_clock_divider 1 // *** End of Section 4 *** // *** Section 5 -- Port declarations *** input [`CLK0IN_PORTSIZE_CONST_stratixiv_hssi_clock_divider - 1 : 0] clk0in; input [`CLK1IN_PORTSIZE_CONST_stratixiv_hssi_clock_divider - 1 : 0] clk1in; input dpriodisable; input [`DPRIOIN_PORTSIZE_CONST_stratixiv_hssi_clock_divider - 1 : 0] dprioin; input powerdn; input quadreset; input rateswitch; input [`RATESWITCHBASECLKIN_PORTSIZE_CONST_stratixiv_hssi_clock_divider - 1 : 0] rateswitchbaseclkin; input [`RATESWITCHDONEIN_PORTSIZE_CONST_stratixiv_hssi_clock_divider - 1 : 0] rateswitchdonein; input refclkdig; input [`REFCLKIN_PORTSIZE_CONST_stratixiv_hssi_clock_divider - 1 : 0] refclkin; input vcobypassin; output [`ANALOGFASTREFCLKOUT_PORTSIZE_CONST_stratixiv_hssi_clock_divider - 1 : 0] analogfastrefclkout; output [`ANALOGFASTREFCLKOUTSHIFTED_PORTSIZE_CONST_stratixiv_hssi_clock_divider - 1 : 0] analogfastrefclkoutshifted; output [`ANALOGREFCLKOUT_PORTSIZE_CONST_stratixiv_hssi_clock_divider - 1 : 0] analogrefclkout; output [`ANALOGREFCLKOUTSHIFTED_PORTSIZE_CONST_stratixiv_hssi_clock_divider - 1 : 0] analogrefclkoutshifted; output analogrefclkpulse; output analogrefclkpulseshifted; output coreclkout; output [`DPRIOOUT_PORTSIZE_CONST_stratixiv_hssi_clock_divider - 1 : 0] dprioout; output rateswitchbaseclock; output rateswitchdone; output rateswitchout; output refclkout; // *** End of Section 5 *** // *** Section 6 -- Parameter declarations and default values *** parameter lpm_type = "stratixiv_hssi_clock_divider"; parameter channel_num = 0 ; parameter coreclk_out_gated_by_quad_reset = "false"; parameter data_rate = 0 ; parameter divide_by = 4 ; parameter divider_type = "CHANNEL_REGULAR"; parameter dprio_config_mode = 6'h00; parameter effective_data_rate = "unused"; parameter enable_dynamic_divider = "false"; parameter enable_refclk_out = "false"; parameter inclk_select = 0 ; parameter logical_channel_address = 0 ; parameter pre_divide_by = 1 ; parameter rate_switch_base_clk_in_select = 0 ; parameter rate_switch_done_in_select = 0 ; parameter refclk_divide_by = 0 ; parameter refclk_multiply_by = 0 ; parameter refclkin_select = 0 ; parameter select_local_rate_switch_base_clock = "false"; parameter select_local_rate_switch_done = "true"; // shawn parameter select_local_refclk = "false"; parameter select_refclk_dig = "false"; parameter sim_analogfastrefclkout_phase_shift = 0 ; parameter sim_analogrefclkout_phase_shift = 0 ; parameter sim_coreclkout_phase_shift = 0 ; parameter sim_refclkout_phase_shift = 0 ; parameter use_coreclk_out_post_divider = "false"; parameter use_refclk_post_divider = "false"; parameter use_vco_bypass = "false"; // *** End of Section 6 *** // *** Section 7 -- Port declarations with defaults, if any *** // This section will always be empty for WYSIWYG atoms // tri1 devclrn; //sample // *** End of Section 7 *** // -------------------------------------------------------------------------- // Model Implementation Begin // -------------------------------------------------------------------------- `define STRATIXIV_HSSI_CD_WORD_LENGTH 18 // --------------------------------------------------------------------------- // New DPRIO Begin // --------------------------------------------------------------------------- `define INCLK_SELECT_CLOCK_DIV_IDX 0 // logic index `define ht_sel_CLOCK_DIV_IDX 1 // existing - only in cmu `define rdynamic_sw_CLOCK_DIV_IDX_0 86 // matching tx_pma index `define rpmadwidth_tx_CLOCK_DIV_IDX_0 89 // rcgb_div5 `define rpma_doublewidth_tx_CLOCK_DIV_IDX_0 90 // rcgb_div2 `define rcgb_m_sel_CLOCK_DIV_IDX_0 91 `define rcgb_m_sel_CLOCK_DIV_IDX_1 92 `define rcgb_cmu_sel_CLOCK_DIV_IDX_0 93 // central clock divider section `define rfreerun_centrl_CLOCK_DIV_IDX 10 `define rcentrl_clk_sel_CLOCK_DIV_IDX 11 `define rrefclk_out_div2_CLOCK_DIV_IDX 12 // --------------------------------------------------------------------------- // DPRIO input CRAM // --------------------------------------------------------------------------- // CRAM value from DPRIO wire dprioin_ht_sel; wire dprioin_rcgb_cmu_sel; wire [1:0] dprioin_rcgb_m_sel; wire dprioin_rpmadwidth_tx; // rcgb_div5 wire dprioin_rcgb_rpma_doublewidth_tx; // rcgb_div2 wire dprioin_rcgb_dynamic_sw; // SW logical index wire dprioin_inclk_select; // central clock divider section wire dprioin_rfreerun_centrl; wire dprioin_rcentrl_clk_sel; wire dprioin_rrefclk_out_div2; // --------------------------------------------------------------------------- // Initial CRAM // --------------------------------------------------------------------------- reg init_ht_sel; reg init_rcgb_cmu_sel; reg [1:0] init_rcgb_m_sel; reg init_rpmadwidth_tx; // rcgb_div5 reg init_rcgb_rpma_doublewidth_tx; // rcgb_div2 reg init_rcgb_dynamic_sw; // SW logical index reg init_inclk_select; // central clock divider section reg init_rfreerun_centrl; reg init_rcentrl_clk_sel; reg init_rrefclk_out_div2; reg is_high_speed_regular; reg is_enable_refclk_out; reg is_select_local_refclk; reg is_select_local_rate_switch_done; reg is_select_local_rate_switch_base_clock; reg is_use_vco_bypass; wire is_using_refclk_post_divider; wire is_using_coreclk_out_post_divider; wire is_select_refclk_dig; // --------------------------------------------------------------------------- // CRAM // --------------------------------------------------------------------------- wire cram_ht_sel; wire cram_rcgb_cmu_sel; wire [1:0] cram_rcgb_m_sel; wire cram_rpmadwidth_tx; // rcgb_div5 wire cram_rcgb_rpma_doublewidth_tx; // rcgb_div2 wire cram_rcgb_dynamic_sw; // SW logical index wire cram_inclk_select; // central clock divider section wire cram_rfreerun_centrl; wire cram_rcentrl_clk_sel; wire cram_rrefclk_out_div2; // --------------------------------------------------------------------------- // Set DPRIO CRAM input from dprioin // --------------------------------------------------------------------------- assign dprioin_ht_sel = dprioin[`ht_sel_CLOCK_DIV_IDX]; assign dprioin_rcgb_cmu_sel = dprioin[`rcgb_cmu_sel_CLOCK_DIV_IDX_0]; assign dprioin_rcgb_m_sel = dprioin[`rcgb_m_sel_CLOCK_DIV_IDX_1 : `rcgb_m_sel_CLOCK_DIV_IDX_0]; assign dprioin_rpmadwidth_tx = dprioin[`rpmadwidth_tx_CLOCK_DIV_IDX_0]; assign dprioin_rcgb_rpma_doublewidth_tx = dprioin[`rpma_doublewidth_tx_CLOCK_DIV_IDX_0]; assign dprioin_rcgb_dynamic_sw = dprioin[`rdynamic_sw_CLOCK_DIV_IDX_0]; // SW logical index assign dprioin_inclk_select = dprioin[`INCLK_SELECT_CLOCK_DIV_IDX]; // central clock divider section assign dprioin_rfreerun_centrl = dprioin[`rfreerun_centrl_CLOCK_DIV_IDX]; assign dprioin_rcentrl_clk_sel = dprioin[`rcentrl_clk_sel_CLOCK_DIV_IDX]; assign dprioin_rrefclk_out_div2 = dprioin[`rrefclk_out_div2_CLOCK_DIV_IDX]; // --------------------------------------------------------------------------- // Set DPRIO output from initial CRAM // --------------------------------------------------------------------------- //assign dprioout[`rcru_pdbwctrl_PLL_IDX_1 : `rcru_pdbwctrl_PLL_IDX_0] = init_rcru_pdbwctrl; assign dprioout[`ht_sel_CLOCK_DIV_IDX] = init_ht_sel; assign dprioout[`rcgb_cmu_sel_CLOCK_DIV_IDX_0] = init_rcgb_cmu_sel; assign dprioout[`rcgb_m_sel_CLOCK_DIV_IDX_1 : `rcgb_m_sel_CLOCK_DIV_IDX_0] = init_rcgb_m_sel; assign dprioout[`rpmadwidth_tx_CLOCK_DIV_IDX_0] = init_rpmadwidth_tx; assign dprioout[`rpma_doublewidth_tx_CLOCK_DIV_IDX_0] = init_rcgb_rpma_doublewidth_tx; assign dprioout[`rdynamic_sw_CLOCK_DIV_IDX_0] = init_rcgb_dynamic_sw; // SW logical index assign dprioout[`INCLK_SELECT_CLOCK_DIV_IDX] = init_inclk_select; // central clock divider section assign dprioout[`rfreerun_centrl_CLOCK_DIV_IDX] = init_rfreerun_centrl; assign dprioout[`rcentrl_clk_sel_CLOCK_DIV_IDX] = init_rcentrl_clk_sel ; assign dprioout[`rrefclk_out_div2_CLOCK_DIV_IDX] = init_rrefclk_out_div2; // --------------------------------------------------------------------------- // Set DPRIO CRAM // --------------------------------------------------------------------------- //assign cram_ht_sel = (dpriodisable_in !== 1'b0) ? init_ht_sel : dprioin_ht_sel; assign cram_ht_sel = init_ht_sel; assign cram_rcgb_cmu_sel = (dpriodisable !== 1'b0) ? init_rcgb_cmu_sel : dprioin_rcgb_cmu_sel; assign cram_rcgb_m_sel = (dpriodisable !== 1'b0) ? init_rcgb_m_sel : dprioin_rcgb_m_sel; assign cram_rpmadwidth_tx = (dpriodisable !== 1'b0) ? init_rpmadwidth_tx : dprioin_rpmadwidth_tx; assign cram_rcgb_rpma_doublewidth_tx = (dpriodisable !== 1'b0) ? init_rcgb_rpma_doublewidth_tx : dprioin_rcgb_rpma_doublewidth_tx; assign cram_rcgb_dynamic_sw = (dpriodisable !== 1'b0) ? init_rcgb_dynamic_sw : dprioin_rcgb_dynamic_sw; // SW logical index assign cram_inclk_select = (dpriodisable !== 1'b0) ? init_inclk_select : dprioin_inclk_select; // central clock divider section assign cram_rfreerun_centrl = (dpriodisable !== 1'b0) ? init_rfreerun_centrl : dprioin_rfreerun_centrl; assign cram_rcentrl_clk_sel = (dpriodisable !== 1'b0) ? init_rcentrl_clk_sel : dprioin_rcentrl_clk_sel; assign cram_rrefclk_out_div2 = (dpriodisable !== 1'b0) ? init_rrefclk_out_div2 : dprioin_rrefclk_out_div2; // wires for other inputs and outputs // inputs wire [1:0] clkgen_cgb_x_en; wire clkgen_clk0_0; wire clkgen_clk90_0; wire clkgen_clk180_0; wire clkgen_clk270_0; wire clkgen_clk0_1; wire clkgen_clk90_1; wire clkgen_clk180_1; wire clkgen_clk270_1; wire clkgen_pcie_sw; wire clkgen_pdb; wire clkgen_rst_n; // outputs wire clkgen_cgb_vccelxqyx; wire clkgen_cgb_vssexqyx; wire clkgen_cpulse_ht; wire clkgen_cpulse_x1; wire clkgen_hclk; wire clkgen_hfclkn_ht; wire clkgen_hfclkn_x1; wire clkgen_hfclkp_ht; wire clkgen_hfclkp_x1; wire clkgen_lfclkn_ht; wire clkgen_lfclkn_x1; wire clkgen_lfclkp_ht; wire clkgen_lfclkp_x1; wire clkgen_pclk; wire clkgen_pcie_sw_cdr; wire clkgen_gen2ngen1; wire vccelx; wire vssex; wire wire_reset; // 10g outputs wire clkgen_10g_cpulse; wire clkgen_10g_cpulseb; wire clkgen_10g_hfclk_n; wire clkgen_10g_hfclk_p; wire clkgen_10g_lfclk_n; wire clkgen_10g_lfclk_p; // intermediate wires wire coreclkout_mux; wire coreclk_divide_out; wire vcobypassmux_out; wire refclk_divide_out; wire refclkdividemux_out; // function declarations // convert uppercase parameter values to lowercase // assumes that the maximum character length of a parameter is 18 function [8*`STRATIXIV_HSSI_CD_WORD_LENGTH:1] alpha_tolower; input [8*`STRATIXIV_HSSI_CD_WORD_LENGTH:1] given_string; reg [8*`STRATIXIV_HSSI_CD_WORD_LENGTH:1] return_string; reg [8*`STRATIXIV_HSSI_CD_WORD_LENGTH:1] reg_string; reg [8:1] tmp; reg [8:1] conv_char; integer byte_count; begin return_string = " "; // initialise strings to spaces conv_char = " "; reg_string = given_string; for (byte_count = `STRATIXIV_HSSI_CD_WORD_LENGTH; byte_count >= 1; byte_count = byte_count - 1) begin tmp = reg_string[8*`STRATIXIV_HSSI_CD_WORD_LENGTH:(8*(`STRATIXIV_HSSI_CD_WORD_LENGTH-1)+1)]; reg_string = reg_string << 8; if ((tmp >= 65) && (tmp <= 90)) // ASCII number of 'A' is 65, 'Z' is 90 begin conv_char = tmp + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set return_string = {return_string, conv_char}; end else return_string = {return_string, tmp}; end alpha_tolower = return_string; end endfunction initial begin // Convert Parameters to initial CRAMs init_ht_sel = (alpha_tolower(divider_type) == "central_enhanced" || alpha_tolower(divider_type) == "central_regular") ? 1'b1 : 1'b0; init_rcgb_cmu_sel = (inclk_select == 0) ? 1'b0 : 1'b1; init_rcgb_m_sel = (pre_divide_by == 2) ? 2'b01 : (pre_divide_by == 4) ? 2'b10 : 2'b00; init_rpmadwidth_tx = (divide_by == 4) ? 1'b0 : 1'b1; init_rcgb_rpma_doublewidth_tx = (use_refclk_post_divider == "true") ? 1'b1 : 1'b0; init_rcgb_dynamic_sw = (enable_dynamic_divider == "true") ? 1'b1 : 1'b0; // sw logic index init_inclk_select = (inclk_select == 0) ? 1'b0 : 1'b1; // central clock divider section init_rfreerun_centrl = 1'b1; // missing parameter init_rcentrl_clk_sel = (select_refclk_dig == "true") ? 1'b1 : 1'b0; init_rrefclk_out_div2 = (use_coreclk_out_post_divider == "true") ? 1'b1 : 1'b0; is_high_speed_regular = (alpha_tolower(divider_type) == "high_speed_regular") ? 1'b1 : 1'b0; is_enable_refclk_out = (enable_refclk_out == "true") ? 1'b1 : 1'b0; is_select_local_refclk = (select_local_refclk == "true") ? 1'b1 : 1'b0; is_select_local_rate_switch_done = (select_local_rate_switch_done == "true") ? 1'b1 : 1'b0; is_select_local_rate_switch_base_clock = (select_local_rate_switch_base_clock == "true") ? 1'b1 : 1'b0; is_use_vco_bypass = (use_vco_bypass == "true") ? 1'b1 : 1'b0; end assign is_using_refclk_post_divider = (cram_rcgb_rpma_doublewidth_tx === 1'b1) ? 1'b1 : 1'b0; assign is_using_coreclk_out_post_divider = (cram_rrefclk_out_div2 === 1'b1) ? 1'b1 : 1'b0; assign is_select_refclk_dig = (cram_rcentrl_clk_sel === 1'b1) ? 1'b1 : 1'b0; // connect inputs from top-level //assign cgb_pclksel = (refclkin_select; assign clkgen_cgb_x_en = 2'b00; // enable for pdb assign clkgen_clk0_0 = (is_high_speed_regular == 1'b1) ? 1'b0 : clk0in[0]; // Phase 0 assign clkgen_clk0_1 = (is_high_speed_regular == 1'b1) ? 1'b0 : clk1in[0]; // Phase 0 assign clkgen_clk90_0 = (is_high_speed_regular == 1'b1) ? 1'b0 : clk0in[1]; assign clkgen_clk90_1 = (is_high_speed_regular == 1'b1) ? 1'b0 : clk1in[1]; assign clkgen_clk180_0 = (is_high_speed_regular == 1'b1) ? 1'b0 : clk0in[2]; assign clkgen_clk180_1 = (is_high_speed_regular == 1'b1) ? 1'b0 : clk1in[2]; assign clkgen_clk270_0 = (is_high_speed_regular == 1'b1) ? 1'b0 : clk0in[3]; assign clkgen_clk270_1 = (is_high_speed_regular == 1'b1) ? 1'b0 : clk1in[3]; assign clkgen_pdb = (powerdn === 1'b1) ? 1'b0 : 1'b1; // pdb is active low assign clkgen_pcie_sw = (rateswitch === 1'b1) ? 1'b1 : 1'b0; assign clkgen_rst_n = (quadreset === 1'b1) ? 1'b0 : 1'b1; // ICD's clkgenbuf_cmu instantiation stratixiv_hssi_pma_c_clkgenbuf_cmu clkgen ( .cgb_x_en(clkgen_cgb_x_en), .clk0_0(clkgen_clk0_0), .clk0_1(clkgen_clk0_1), .clk90_0(clkgen_clk90_0), .clk90_1(clkgen_clk90_1), .clk180_0(clkgen_clk180_0), .clk180_1(clkgen_clk180_1), .clk270_0(clkgen_clk270_0), .clk270_1(clkgen_clk270_1), .cmu_sel(cram_inclk_select), .div5(cram_rpmadwidth_tx), .dynamic_sw(cram_rcgb_dynamic_sw), .ht_sel(cram_ht_sel), .m_sel(cram_rcgb_m_sel), .pcie_sw(clkgen_pcie_sw), .pdb(clkgen_pdb), .rst_n(clkgen_rst_n), .vccelxqyx(vccelx), .vssexqyx(vssex), .cgb_vccelxqyx(clkgen_cgb_vccelxqyx), .cgb_vssexqyx(clkgen_cgb_vssexqyx), .cpulse_ht(clkgen_cpulse_ht), .cpulse_x1(clkgen_cpulse_x1), .gen2ngen1(clkgen_gen2ngen1), .hclk(clkgen_hclk), .hfclkn_ht(clkgen_hfclkn_ht), .hfclkn_x1(clkgen_hfclkn_x1), .hfclkp_ht(clkgen_hfclkp_ht), .hfclkp_x1(clkgen_hfclkp_x1), .lfclkn_ht(clkgen_lfclkn_ht), .lfclkn_x1(clkgen_lfclkn_x1), .lfclkp_ht(clkgen_lfclkp_ht), .lfclkp_x1(clkgen_lfclkp_x1), .pcie_sw_cdr(clkgen_pcie_sw_cdr), .pclk(clkgen_pclk) ); stratixiv_hssi_pma_c_clkgenbuf_tx10g clkgen_10g ( .clk0_in(clk0in[0]), .clk180_in(clk0in[2]), .rst_n(clkgen_rst_n), .vccelxqyx(vccelx), .vssexqyx(vssex), .cpulse(clkgen_10g_cpulse), .cpulseb(clkgen_10g_cpulseb), .hfclk_n(clkgen_10g_hfclk_n), .hfclk_p(clkgen_10g_hfclk_p), .lfclk_n(clkgen_10g_lfclk_n), .lfclk_p(clkgen_10g_lfclk_p) ); assign analogrefclkout = (is_high_speed_regular == 1'b1) ? ({clkgen_10g_lfclk_n, clkgen_10g_lfclk_p}) : ({clkgen_lfclkn_x1, clkgen_lfclkp_x1}); assign analogfastrefclkout = (is_high_speed_regular == 1'b1) ? ({clkgen_10g_hfclk_n, clkgen_10g_hfclk_p}) : ({clkgen_hfclkn_x1, clkgen_hfclkp_x1}); assign analogrefclkpulse = (is_high_speed_regular == 1'b1) ? clkgen_10g_cpulse : clkgen_cpulse_x1; assign rateswitchdone = (is_select_local_rate_switch_done == 1'b1) ? clkgen_gen2ngen1 : rateswitchdonein[rate_switch_done_in_select]; assign rateswitchbaseclock = (is_select_local_rate_switch_base_clock == 1'b1) ? clkgen_hclk : rateswitchbaseclkin[rate_switch_base_clk_in_select]; assign rateswitchout = rateswitch; assign analogrefclkoutshifted = ({clkgen_lfclkn_ht, clkgen_lfclkp_ht}); assign analogfastrefclkoutshifted = ({clkgen_hfclkn_ht, clkgen_hfclkp_ht}); assign analogrefclkpulseshifted = clkgen_cpulse_ht; assign vcobypassmux_out = (is_use_vco_bypass == 1'b1 ? ~vcobypassin : clkgen_pclk); stratixiv_hssi_aux_clock_div refclk_divider ( .clk(vcobypassmux_out), .enable_d(1'b0), .d(8'b0), .reset(wire_reset), .clkout(refclk_divide_out) ); defparam refclk_divider.clk_divide_by = 2; defparam refclk_divider.extra_latency = 0; assign refclkdividemux_out = (is_using_refclk_post_divider == 1'b1 ? refclk_divide_out : vcobypassmux_out); assign refclkout = (is_enable_refclk_out == 1'b1 ? (is_select_refclk_dig == 1'b1) ? refclkdig : (is_select_local_refclk == 1'b1 ? refclkdividemux_out : refclkin[refclkin_select]) : 1'bz); stratixiv_hssi_aux_clock_div coreclk_divider ( .clk(refclkout), .enable_d(1'b0), .d(8'b0), .reset(wire_reset), .clkout(coreclk_divide_out) ); defparam coreclk_divider.clk_divide_by = 2; defparam coreclk_divider.extra_latency = 0; assign coreclkout = (is_using_coreclk_out_post_divider == 1'b1) ? coreclk_divide_out : refclkout; endmodule // *********************************************************** // This WYSIWYG atom header was automatically generated by the // Atmgen build tool. To change it, alter data stored in the // corresponding WYS file(s) in the tools/atmgen subdirectory. // *********************************************************** // *** Section 1 -- Header *** // ----------------------------------------------------------- // // Module Name : stratixiv_hssi_pll // // Description : DEV_FAMILY_STRATIXIV stratixiv_hssi_pll Verilog simulation model // // ----------------------------------------------------------- `timescale 1 ps/1 ps // *** End of Section 1 *** // *** Section 3 -- Module declaration *** module stratixiv_hssi_pll( areset, datain, dpriodisable, dprioin, earlyeios, extra10gin, inclk, locktorefclk, pfdfbclk, powerdown, rateswitch, clk, dataout, dprioout, freqlocked, locked, pfdfbclkout, pfdrefclkout, vcobypassout ); // *** End of Section 3 *** // *** Section 4 -- Port size declarations *** // Note: Variable port sizes dictated by parameters are not currently defined in // the WYS file data. Busses are marked with the VARIABLE notation as a reminder. `define ARESET_PORTSIZE_CONST_stratixiv_hssi_pll 1 `define CLK_PORTSIZE_CONST_stratixiv_hssi_pll 4 // * VARIABLE `define DATAIN_PORTSIZE_CONST_stratixiv_hssi_pll 1 `define DATAOUT_PORTSIZE_CONST_stratixiv_hssi_pll 2 // * VARIABLE `define DPRIODISABLE_PORTSIZE_CONST_stratixiv_hssi_pll 1 `define DPRIOIN_PORTSIZE_CONST_stratixiv_hssi_pll 300 // * VARIABLE `define DPRIOOUT_PORTSIZE_CONST_stratixiv_hssi_pll 300 // * VARIABLE `define EARLYEIOS_PORTSIZE_CONST_stratixiv_hssi_pll 1 `define EXTRA10GIN_PORTSIZE_CONST_stratixiv_hssi_pll 6 // * VARIABLE `define FREQLOCKED_PORTSIZE_CONST_stratixiv_hssi_pll 1 `define INCLK_PORTSIZE_CONST_stratixiv_hssi_pll 10 // * VARIABLE `define LOCKED_PORTSIZE_CONST_stratixiv_hssi_pll 1 `define LOCKTOREFCLK_PORTSIZE_CONST_stratixiv_hssi_pll 1 `define PFDFBCLK_PORTSIZE_CONST_stratixiv_hssi_pll 1 `define PFDFBCLKOUT_PORTSIZE_CONST_stratixiv_hssi_pll 1 `define PFDREFCLKOUT_PORTSIZE_CONST_stratixiv_hssi_pll 1 `define POWERDOWN_PORTSIZE_CONST_stratixiv_hssi_pll 1 `define RATESWITCH_PORTSIZE_CONST_stratixiv_hssi_pll 1 `define VCOBYPASSOUT_PORTSIZE_CONST_stratixiv_hssi_pll 1 // *** End of Section 4 *** `ifdef ALPHA_TOLOWER_WORD_LENGTH `else `define ALPHA_TOLOWER_WORD_LENGTH 25 `endif // for alpha_tolower function // *** Section 5 -- Port declarations *** input areset; input datain; input dpriodisable; input [`DPRIOIN_PORTSIZE_CONST_stratixiv_hssi_pll - 1 : 0] dprioin; input earlyeios; input [`EXTRA10GIN_PORTSIZE_CONST_stratixiv_hssi_pll - 1 : 0] extra10gin; input [`INCLK_PORTSIZE_CONST_stratixiv_hssi_pll - 1 : 0] inclk; input locktorefclk; input pfdfbclk; input powerdown; input rateswitch; output [`CLK_PORTSIZE_CONST_stratixiv_hssi_pll - 1 : 0] clk; output [`DATAOUT_PORTSIZE_CONST_stratixiv_hssi_pll - 1 : 0] dataout; output [`DPRIOOUT_PORTSIZE_CONST_stratixiv_hssi_pll - 1 : 0] dprioout; output freqlocked; output locked; output pfdfbclkout; output pfdrefclkout; output vcobypassout; // *** End of Section 5 *** // *** Section 6 -- Parameter declarations and default values *** parameter lpm_type = "stratixiv_hssi_pll"; parameter auto_settings = "true"; parameter bandwidth_type = "Auto"; parameter base_data_rate = "unused"; parameter channel_num = 0 ; parameter charge_pump_current_bits = 0 ; parameter charge_pump_mode_bits = 0 ; parameter charge_pump_test_enable = "false"; parameter dprio_config_mode = "000000"; parameter effective_data_rate = "unused"; parameter enable_dynamic_divider = "false"; parameter fast_lock_control = "false"; parameter inclk0_input_period = 0 ; parameter inclk1_input_period = 0 ; parameter inclk2_input_period = 0 ; parameter inclk3_input_period = 0 ; parameter inclk4_input_period = 0 ; parameter inclk5_input_period = 0 ; parameter inclk6_input_period = 0 ; parameter inclk7_input_period = 0 ; parameter inclk8_input_period = 0 ; parameter inclk9_input_period = 0 ; parameter input_clock_frequency = "unused"; parameter logical_channel_address = 0 ; parameter logical_tx_pll_number = 0 ; parameter loop_filter_c_bits = 0 ; parameter loop_filter_r_bits = 0 ; parameter m = 0 ; parameter n = 0 ; parameter pd_charge_pump_current_bits = 0 ; parameter pd_loop_filter_r_bits = 0 ; parameter pfd_clk_select = 0 ; parameter pfd_fb_select = "internal"; parameter pll_type = "Auto"; parameter protocol_hint = "basic"; parameter refclk_divide_by = 0 ; parameter refclk_multiply_by = 0 ; parameter sim_is_negative_ppm_drift = "false"; parameter sim_net_ppm_variation = 0 ; parameter test_charge_pump_current_down = "false"; parameter test_charge_pump_current_up = "false"; parameter use_refclk_pin = "false"; parameter vco_data_rate = 0 ; parameter vco_divide_by = 0 ; parameter vco_multiply_by = 0 ; parameter vco_post_scale = 0 ; parameter vco_range = "low"; parameter vco_tuning_bits = 0 ; parameter volt_reg_control_bits = 0 ; parameter volt_reg_output_bits = 0 ; // *** End of Section 6 *** // SIMULATION_ONLY_PARAMETERS_BEGIN parameter sim_clkout_phase_shift = 0; parameter sim_clkout_latency = 0; parameter PARAM_DELAY = 0; // SIMULATION_ONLY_PARAMETERS_END // *** Section 7 -- Port declarations with defaults, if any *** // This section will always be empty for WYSIWYG atoms // tri1 devclrn; //sample // *** End of Section 7 *** // --------------------------------------------------------------------------- // Model Implementation Begin - // --------------------------------------------------------------------------- tri1 dpriodisable; // --------------------------------------------------------------------------- // New DPRIO Begin // --------------------------------------------------------------------------- // Table39: PMA Per Channel RX Control Register 4 for Channel 0 `define rcru_pdbwctrl_PLL_IDX_0 0 `define rcru_pdbwctrl_PLL_IDX_1 1 `define rcru_pfdbwctrl_PLL_IDX_0 2 `define rcru_pfdbwctrl_PLL_IDX_1 3 `define rcru_crplctrl_PLL_IDX_0 4 `define rcru_crplctrl_PLL_IDX_1 5 `define rcru_ctl0_PLL_IDX_0 6 `define rcru_l_PLL_IDX_0 7 `define rcru_l_PLL_IDX_1 8 `define rcru_m_PLL_IDX_0 9 `define rcru_m_PLL_IDX_1 10 `define rcru_m_PLL_IDX_2 11 `define rcru_m_PLL_IDX_3 12 `define rcru_m_sel_PLL_IDX_0 13 `define rcru_m_sel_PLL_IDX_1 14 `define rcru_div2_PLL_IDX_0 15 // Table40: PMA Per Channel RX Control Register 5 for Channel 0 `define reserved_0_TB40_PLL_IDX_0 16 `define reserved_0_TB40_PLL_IDX_1 17 `define rcru_iselpd_PLL_IDX_0 18 `define rcru_iselpd_PLL_IDX_1 19 `define rcru_iselpd_PLL_IDX_2 20 `define rcru_isel_PLL_IDX_0 21 `define rcru_isel_PLL_IDX_1 22 `define rcru_isel_PLL_IDX_2 23 `define rcru_testdnen_PLL_IDX_0 24 `define rcru_testupen_PLL_IDX_0 25 `define rcru_testen_PLL_IDX_0 26 `define rcru_lst_PLL_IDX_0 27 `define rcru_lst_PLL_IDX_1 28 `define rcru_lst_PLL_IDX_2 29 `define rcru_lst_PLL_IDX_3 30 `define rcru_rlbk_PLL_IDX_0 31 // Table41: PMA Per Channel RX Control Register 6 for Channel 0 `define rcru_rgla_isel_PLL_IDX_0 32 `define rcru_rgla_isel_PLL_IDX_1 33 `define rcru_rgla_isel_PLL_IDX_2 34 `define rcru_pdof_test_PLL_IDX_0 35 `define rcru_pdof_test_PLL_IDX_1 36 `define rcru_pdof_test_PLL_IDX_2 37 `define rcru_pdfl_PLL_IDX_0 38 `define rcru_sd_sel_PLL_IDX_0 39 `define reserved_0_TB41_PLL_IDX_0 40 `define rcru_ignore_phslck_PLL_IDX_0 41 `define rcru_cmu_mode_PLL_IDX_0 42 `define rrx_cru_rst_PLL_IDX_0 43 `define rrx_cru_pdb_PLL_IDX_0 44 `define rltr_PLL_IDX_0 45 `define rltd_PLL_IDX_0 46 `define rcp_mode_PLL_IDX_0 47 // Table42: PMA Per Channel RX Control Register 7 for Channel 0 `define rcru_pdof_270i_PLL_IDX_0 48 `define rcru_pdof_270i_PLL_IDX_1 49 `define rcru_pdof_270i_PLL_IDX_2 50 `define rcru_pdof_270i_PLL_IDX_3 51 `define rcru_pdof_180i_PLL_IDX_0 52 `define rcru_pdof_180i_PLL_IDX_1 53 `define rcru_pdof_180i_PLL_IDX_2 54 `define rcru_pdof_180i_PLL_IDX_3 55 `define rcru_pdof_90i_PLL_IDX_0 56 `define rcru_pdof_90i_PLL_IDX_1 57 `define rcru_pdof_90i_PLL_IDX_2 58 `define rcru_pdof_90i_PLL_IDX_3 59 `define rcru_pdof_0i_PLL_IDX_0 60 `define rcru_pdof_0i_PLL_IDX_1 61 `define rcru_pdof_0i_PLL_IDX_2 62 `define rcru_pdof_0i_PLL_IDX_3 63 // Manual: PLL (only rx_cdr_pll uses it: table 33 & 59) -------------- `define rdynamic_sw_PLL_IDX_0 70 // SW logical index ---------------------------------------------------------- `define PFD_CLK_SEL_PLL_IDX_0 100 `define PFD_CLK_SEL_PLL_IDX_1 101 `define PFD_CLK_SEL_PLL_IDX_2 102 `define PFD_CLK_SEL_PLL_IDX_3 103 // --------------------------------------------------------------------------- // DPRIO input CRAM // --------------------------------------------------------------------------- // PMA Per Channel RX Control Register 4 for Channel 0 wire [1:0] dprioin_rcru_pdbwctrl; wire [1:0] dprioin_rcru_pfdbwctrl; wire [1:0] dprioin_rcru_crplctrl; wire dprioin_rcru_ctl0; wire [1:0] dprioin_rcru_l; wire [3:0] dprioin_rcru_m; wire [1:0] dprioin_rcru_m_sel; wire dprioin_rcru_div2; // PMA Per Channel RX Control Register 5 for Channel 0 wire [1:0] dprioin_reserved_0_TB40; wire [2:0] dprioin_rcru_iselpd; wire [2:0] dprioin_rcru_isel; wire dprioin_rcru_testdnen; wire dprioin_rcru_testupen; wire dprioin_rcru_testen; wire [3:0] dprioin_rcru_lst; wire dprioin_rcru_rlbk; // PMA Per Channel RX Control Register 6 for Channel 0 wire [2:0] dprioin_rcru_rgla_isel; wire [2:0] dprioin_rcru_pdof_test; wire dprioin_rcru_pdfl; wire dprioin_rcru_sd_sel; wire dprioin_reserved_0_TB41; wire dprioin_rcru_ignore_phslck; wire dprioin_rcru_cmu_mode; wire dprioin_rrx_cru_rst; wire dprioin_rrx_cru_pdb; wire dprioin_rltr; wire dprioin_rltd; wire dprioin_rcp_mode; // PMA Per Channel RX Control Register 7 for Channel 0 wire [3:0] dprioin_rcru_pdof_270i; wire [3:0] dprioin_rcru_pdof_180i; wire [3:0] dprioin_rcru_pdof_90i; wire [3:0] dprioin_rcru_pdof_0i; // Manual section wire [3:0] dprioin_pfd_clk_sel; wire [7:0] dprioin_vco_post_scale; wire [1:0] dprioin_pfd_fb_select; wire [7:0] m_dprioin_modulus; wire [7:0] n_dprioin_modulus; wire dprioin_rdynamic_sw; // --------------------------------------------------------------------------- // Initial CRAM // --------------------------------------------------------------------------- // PMA Per Channel RX Control Register 4 for Channel 0 reg [1:0] init_rcru_pdbwctrl; reg [1:0] init_rcru_pfdbwctrl; reg [1:0] init_rcru_crplctrl; reg init_rcru_ctl0; reg [1:0] init_rcru_l; reg [3:0] init_rcru_m; reg [1:0] init_rcru_m_sel; reg init_rcru_div2; // PMA Per Channel RX Control Register 5 for Channel 0 reg [1:0] init_reserved_0_TB40; reg [2:0] init_rcru_iselpd; reg [2:0] init_rcru_isel; reg init_rcru_testdnen; reg init_rcru_testupen; reg init_rcru_testen; reg [3:0] init_rcru_lst; reg init_rcru_rlbk; // PMA Per Channel RX Control Register 6 for Channel 0 reg [2:0] init_rcru_rgla_isel; reg [2:0] init_rcru_pdof_test; reg init_rcru_pdfl; reg init_rcru_sd_sel; reg init_reserved_0_TB41; reg init_rcru_ignore_phslck; reg init_rcru_cmu_mode; reg init_rrx_cru_rst; reg init_rrx_cru_pdb; reg init_rltr; reg init_rltd; reg init_rcp_mode; // PMA Per Channel RX Control Register 7 for Channel 0 reg [3:0] init_rcru_pdof_270i; reg [3:0] init_rcru_pdof_180i; reg [3:0] init_rcru_pdof_90i; reg [3:0] init_rcru_pdof_0i; // Manual section reg [3:0] init_pfd_clk_sel; reg [1:0] init_vco_post_scale; reg [1:0] init_pfd_fb_select; // --------------------------------------------------------------------------- // CRAM // --------------------------------------------------------------------------- // PMA Per Channel RX Control Register 4 for Channel 0 wire [1:0] cram_rcru_pdbwctrl; wire [1:0] cram_rcru_pfdbwctrl; wire [1:0] cram_rcru_crplctrl; wire cram_rcru_ctl0; wire [1:0] cram_rcru_l; wire [3:0] cram_rcru_m; wire [1:0] cram_rcru_m_sel; wire cram_rcru_div2; // PMA Per Channel RX Control Register 5 for Channel 0 wire [1:0] cram_reserved_0_TB40; wire [2:0] cram_rcru_iselpd; wire [2:0] cram_rcru_isel; wire cram_rcru_testdnen; wire cram_rcru_testupen; wire cram_rcru_testen; wire [3:0] cram_rcru_lst; wire cram_rcru_rlbk; // PMA Per Channel RX Control Register 6 for Channel 0 wire [2:0] cram_rcru_rgla_isel; wire [2:0] cram_rcru_pdof_test; wire cram_rcru_pdfl; wire cram_rcru_sd_sel; wire cram_reserved_0_TB41; wire cram_rcru_ignore_phslck; wire cram_rcru_cmu_mode; wire cram_rrx_cru_rst; wire cram_rrx_cru_pdb; wire cram_rltr; wire cram_rltd; wire cram_rcp_mode; // PMA Per Channel RX Control Register 7 for Channel 0 wire [3:0] cram_rcru_pdof_270i; wire [3:0] cram_rcru_pdof_180i; wire [3:0] cram_rcru_pdof_90i; wire [3:0] cram_rcru_pdof_0i; // Manual section wire [3:0] cram_pfd_clk_sel; wire [1:0] cram_vco_post_scale; wire [1:0] cram_pfd_fb_select; wire cram_rdynamic_sw; // end of DPRIO declaration --------------------------------- reg pll_type_is_cdr_or_cmu; reg use_pcie_clk; reg pll_type_is_rx_cdr; initial begin pll_type_is_cdr_or_cmu = (alpha_tolower(pll_type) == "rx cdr" || alpha_tolower(pll_type) == "high speed rx cdr" || alpha_tolower(pll_type) == "cmu" || alpha_tolower(pll_type) == "high speed cmu"); pll_type_is_rx_cdr = (alpha_tolower(pll_type) == "rx cdr"); use_pcie_clk =(alpha_tolower(pll_type) == "rx cdr") && (alpha_tolower(protocol_hint) == "pcie2" || enable_dynamic_divider == "true"); end // --------------------------------------------------------------------------- // Set DPRIO CRAM input from dprioin // --------------------------------------------------------------------------- // PMA Per Channel RX Control Register 4 for Channel 0 assign dprioin_rcru_pdbwctrl = dprioin[`rcru_pdbwctrl_PLL_IDX_1 : `rcru_pdbwctrl_PLL_IDX_0]; assign dprioin_rcru_pfdbwctrl = dprioin[`rcru_pfdbwctrl_PLL_IDX_1 : `rcru_pfdbwctrl_PLL_IDX_0]; assign dprioin_rcru_crplctrl = dprioin[`rcru_crplctrl_PLL_IDX_1 : `rcru_crplctrl_PLL_IDX_0]; assign dprioin_rcru_ctl0 = dprioin[`rcru_ctl0_PLL_IDX_0]; assign dprioin_rcru_l = dprioin[`rcru_l_PLL_IDX_1 : `rcru_l_PLL_IDX_0]; assign dprioin_rcru_m = dprioin[`rcru_m_PLL_IDX_3 : `rcru_m_PLL_IDX_0]; assign dprioin_rcru_m_sel = dprioin[`rcru_m_sel_PLL_IDX_1 : `rcru_m_sel_PLL_IDX_0]; assign dprioin_rcru_div2 = dprioin[`rcru_div2_PLL_IDX_0]; // PMA Per Channel RX Control Register 5 for Channel 0 assign dprioin_reserved_0_TB40 = dprioin[`reserved_0_TB40_PLL_IDX_1 : `reserved_0_TB40_PLL_IDX_0]; assign dprioin_rcru_iselpd = dprioin[`rcru_iselpd_PLL_IDX_2 : `rcru_iselpd_PLL_IDX_0]; assign dprioin_rcru_isel = dprioin[`rcru_isel_PLL_IDX_2 : `rcru_isel_PLL_IDX_0]; assign dprioin_rcru_testdnen = dprioin[`rcru_testdnen_PLL_IDX_0]; assign dprioin_rcru_testupen = dprioin[`rcru_testupen_PLL_IDX_0]; assign dprioin_rcru_testen = dprioin[`rcru_testen_PLL_IDX_0]; assign dprioin_rcru_lst = dprioin[`rcru_lst_PLL_IDX_3 : `rcru_lst_PLL_IDX_0]; assign dprioin_rcru_rlbk = dprioin[`rcru_rlbk_PLL_IDX_0]; // PMA Per Channel RX Control Register 6 for Channel 0 assign dprioin_rcru_rgla_isel = dprioin[`rcru_rgla_isel_PLL_IDX_2 : `rcru_rgla_isel_PLL_IDX_0]; assign dprioin_rcru_pdof_test = dprioin[`rcru_pdof_test_PLL_IDX_2 : `rcru_pdof_test_PLL_IDX_0]; assign dprioin_rcru_pdfl = dprioin[`rcru_pdfl_PLL_IDX_0]; assign dprioin_rcru_sd_sel = dprioin[`rcru_sd_sel_PLL_IDX_0]; assign dprioin_reserved_0_TB41 = dprioin[`reserved_0_TB41_PLL_IDX_0]; assign dprioin_rcru_ignore_phslck = dprioin[`rcru_ignore_phslck_PLL_IDX_0]; assign dprioin_rcru_cmu_mode = dprioin[`rcru_cmu_mode_PLL_IDX_0]; assign dprioin_rrx_cru_rst = dprioin[`rrx_cru_rst_PLL_IDX_0]; assign dprioin_rrx_cru_pdb = dprioin[`rrx_cru_pdb_PLL_IDX_0]; assign dprioin_rltr = dprioin[`rltr_PLL_IDX_0]; assign dprioin_rltd = dprioin[`rltd_PLL_IDX_0]; assign dprioin_rcp_mode = dprioin[`rcp_mode_PLL_IDX_0]; // PMA Per Channel RX Control Register 7 for Channel 0 assign dprioin_rcru_pdof_270i = dprioin[`rcru_pdof_270i_PLL_IDX_3 : `rcru_pdof_270i_PLL_IDX_0]; assign dprioin_rcru_pdof_180i = dprioin[`rcru_pdof_180i_PLL_IDX_3 : `rcru_pdof_180i_PLL_IDX_0]; assign dprioin_rcru_pdof_90i = dprioin[`rcru_pdof_90i_PLL_IDX_3 : `rcru_pdof_90i_PLL_IDX_0]; assign dprioin_rcru_pdof_0i = dprioin[`rcru_pdof_0i_PLL_IDX_3 : `rcru_pdof_0i_PLL_IDX_0]; // Manual section assign dprioin_pfd_clk_sel = dprioin[`PFD_CLK_SEL_PLL_IDX_3 : `PFD_CLK_SEL_PLL_IDX_0]; assign dprioin_rdynamic_sw = dprioin[`rdynamic_sw_PLL_IDX_0]; // --------------------------------------------------------------------------- // Set DPRIO output from initial CRAM // --------------------------------------------------------------------------- // PMA Per Channel RX Control Register 4 for Channel 0 assign dprioout[`rcru_pdbwctrl_PLL_IDX_1 : `rcru_pdbwctrl_PLL_IDX_0] = init_rcru_pdbwctrl; assign dprioout[`rcru_pfdbwctrl_PLL_IDX_1 : `rcru_pfdbwctrl_PLL_IDX_0] = init_rcru_pfdbwctrl; assign dprioout[`rcru_crplctrl_PLL_IDX_1 : `rcru_crplctrl_PLL_IDX_0] = init_rcru_crplctrl; assign dprioout[`rcru_ctl0_PLL_IDX_0] = init_rcru_ctl0; assign dprioout[`rcru_l_PLL_IDX_1 : `rcru_l_PLL_IDX_0] = init_rcru_l; assign dprioout[`rcru_m_PLL_IDX_3 : `rcru_m_PLL_IDX_0] = init_rcru_m; assign dprioout[`rcru_m_sel_PLL_IDX_1 : `rcru_m_sel_PLL_IDX_0] = init_rcru_m_sel; assign dprioout[`rcru_div2_PLL_IDX_0] = init_rcru_div2; // PMA Per Channel RX Control Register 5 for Channel 0 assign dprioout[`reserved_0_TB40_PLL_IDX_1 : `reserved_0_TB40_PLL_IDX_0] = init_reserved_0_TB40; assign dprioout[`rcru_iselpd_PLL_IDX_2 : `rcru_iselpd_PLL_IDX_0] = init_rcru_iselpd; assign dprioout[`rcru_isel_PLL_IDX_2 : `rcru_isel_PLL_IDX_0] = init_rcru_isel; assign dprioout[`rcru_testdnen_PLL_IDX_0] = init_rcru_testdnen; assign dprioout[`rcru_testupen_PLL_IDX_0] = init_rcru_testupen; assign dprioout[`rcru_testen_PLL_IDX_0] = init_rcru_testen; assign dprioout[`rcru_lst_PLL_IDX_3 : `rcru_lst_PLL_IDX_0] = init_rcru_lst; assign dprioout[`rcru_rlbk_PLL_IDX_0] = init_rcru_rlbk; // PMA Per Channel RX Control Register 6 for Channel 0 assign dprioout[`rcru_rgla_isel_PLL_IDX_2 : `rcru_rgla_isel_PLL_IDX_0] = init_rcru_rgla_isel; assign dprioout[`rcru_pdof_test_PLL_IDX_2 : `rcru_pdof_test_PLL_IDX_0] = init_rcru_pdof_test; assign dprioout[`rcru_pdfl_PLL_IDX_0] = init_rcru_pdfl; assign dprioout[`rcru_sd_sel_PLL_IDX_0] = init_rcru_sd_sel; assign dprioout[`reserved_0_TB41_PLL_IDX_0] = init_reserved_0_TB41; assign dprioout[`rcru_ignore_phslck_PLL_IDX_0] = init_rcru_ignore_phslck; assign dprioout[`rcru_cmu_mode_PLL_IDX_0] = init_rcru_cmu_mode; assign dprioout[`rrx_cru_rst_PLL_IDX_0] = init_rrx_cru_rst; assign dprioout[`rrx_cru_pdb_PLL_IDX_0] = init_rrx_cru_pdb; assign dprioout[`rltr_PLL_IDX_0] = init_rltr; assign dprioout[`rltd_PLL_IDX_0] = init_rltd; assign dprioout[`rcp_mode_PLL_IDX_0] = init_rcp_mode; // PMA Per Channel RX Control Register 7 for Channel 0 assign dprioout[`rcru_pdof_270i_PLL_IDX_3 : `rcru_pdof_270i_PLL_IDX_0] = init_rcru_pdof_270i; assign dprioout[`rcru_pdof_180i_PLL_IDX_3 : `rcru_pdof_180i_PLL_IDX_0] = init_rcru_pdof_180i; assign dprioout[`rcru_pdof_90i_PLL_IDX_3 : `rcru_pdof_90i_PLL_IDX_0] = init_rcru_pdof_90i; assign dprioout[`rcru_pdof_0i_PLL_IDX_3 : `rcru_pdof_0i_PLL_IDX_0] = init_rcru_pdof_0i; // Manual section assign dprioout[`PFD_CLK_SEL_PLL_IDX_3 : `PFD_CLK_SEL_PLL_IDX_0] = init_pfd_clk_sel; // --------------------------------------------------------------------------- // Set DPRIO CRAM // --------------------------------------------------------------------------- // PMA Per Channel RX Control Register 4 for Channel 0 assign cram_rcru_pdbwctrl = (dpriodisable !== 1'b0) ? init_rcru_pdbwctrl : dprioin_rcru_pdbwctrl; assign cram_rcru_pfdbwctrl = (dpriodisable !== 1'b0) ? init_rcru_pfdbwctrl : dprioin_rcru_pfdbwctrl; assign cram_rcru_crplctrl = (dpriodisable !== 1'b0) ? init_rcru_crplctrl : dprioin_rcru_crplctrl; assign cram_rcru_ctl0 = (dpriodisable !== 1'b0) ? init_rcru_ctl0 : dprioin_rcru_ctl0; assign cram_rcru_l = (dpriodisable !== 1'b0) ? init_rcru_l : dprioin_rcru_l; assign cram_rcru_m = (dpriodisable === 1'b0 && (pll_type_is_cdr_or_cmu)) ? dprioin_rcru_m : init_rcru_m; assign cram_rcru_m_sel = (dpriodisable === 1'b0 && (pll_type_is_cdr_or_cmu)) ? dprioin_rcru_m_sel : init_rcru_m_sel; assign cram_rcru_div2 = (dpriodisable !== 1'b0) ? init_rcru_div2 : dprioin_rcru_div2; // PMA Per Channel RX Control Register 5 for Channel 0 assign cram_reserved_0_TB40 = (dpriodisable !== 1'b0) ? init_reserved_0_TB40 : dprioin_reserved_0_TB40; assign cram_rcru_iselpd = (dpriodisable !== 1'b0) ? init_rcru_iselpd : dprioin_rcru_iselpd; assign cram_rcru_isel = (dpriodisable !== 1'b0) ? init_rcru_isel : dprioin_rcru_isel; assign cram_rcru_testdnen = (dpriodisable !== 1'b0) ? init_rcru_testdnen : dprioin_rcru_testdnen; assign cram_rcru_testupen = (dpriodisable !== 1'b0) ? init_rcru_testupen : dprioin_rcru_testupen; assign cram_rcru_testen = (dpriodisable !== 1'b0) ? init_rcru_testen : dprioin_rcru_testen; assign cram_rcru_lst = (dpriodisable !== 1'b0) ? init_rcru_lst : dprioin_rcru_lst; assign cram_rcru_rlbk = (dpriodisable !== 1'b0) ? init_rcru_rlbk : dprioin_rcru_rlbk; // PMA Per Channel RX Control Register 6 for Channel 0 assign cram_rcru_rgla_isel = (dpriodisable !== 1'b0) ? init_rcru_rgla_isel : dprioin_rcru_rgla_isel; assign cram_rcru_pdof_test = (dpriodisable !== 1'b0) ? init_rcru_pdof_test : dprioin_rcru_pdof_test; assign cram_rcru_pdfl = (dpriodisable !== 1'b0) ? init_rcru_pdfl : dprioin_rcru_pdfl; assign cram_rcru_sd_sel = (dpriodisable !== 1'b0) ? init_rcru_sd_sel : dprioin_rcru_sd_sel; assign cram_reserved_0_TB41 = (dpriodisable !== 1'b0) ? init_reserved_0_TB41 : dprioin_reserved_0_TB41; assign cram_rcru_ignore_phslck = (dpriodisable !== 1'b0) ? init_rcru_ignore_phslck : dprioin_rcru_ignore_phslck; assign cram_rcru_cmu_mode = (dpriodisable !== 1'b0) ? init_rcru_cmu_mode : dprioin_rcru_cmu_mode; assign cram_rrx_cru_rst = (dpriodisable !== 1'b0) ? init_rrx_cru_rst : dprioin_rrx_cru_rst; assign cram_rrx_cru_pdb = (dpriodisable !== 1'b0) ? init_rrx_cru_pdb : dprioin_rrx_cru_pdb; assign cram_rltr = (dpriodisable !== 1'b0) ? init_rltr : dprioin_rltr; assign cram_rltd = (dpriodisable !== 1'b0) ? init_rltd : dprioin_rltd; assign cram_rcp_mode = (dpriodisable !== 1'b0) ? init_rcp_mode : dprioin_rcp_mode; // PMA Per Channel RX Control Register 7 for Channel 0 assign cram_rcru_pdof_270i = (dpriodisable !== 1'b0) ? init_rcru_pdof_270i : dprioin_rcru_pdof_270i; assign cram_rcru_pdof_180i = (dpriodisable !== 1'b0) ? init_rcru_pdof_180i : dprioin_rcru_pdof_180i; assign cram_rcru_pdof_90i = (dpriodisable !== 1'b0) ? init_rcru_pdof_90i : dprioin_rcru_pdof_90i; assign cram_rcru_pdof_0i = (dpriodisable !== 1'b0) ? init_rcru_pdof_0i : dprioin_rcru_pdof_0i; // manual section assign cram_pfd_clk_sel = (dpriodisable === 1'b0 && (pll_type_is_cdr_or_cmu)) ? dprioin_pfd_clk_sel : init_pfd_clk_sel; assign cram_vco_post_scale = init_vco_post_scale; // to prevent centrl_clk_div.rdymaic_sw propagated into tx_pll assign cram_rdynamic_sw = (dpriodisable !== 1'b0) ? use_pcie_clk : (pll_type_is_rx_cdr & dprioin_rdynamic_sw); // convert from Paramters into initial CRAMs from parameter ------------------ initial begin // RX PMA control register 7 init_rcru_pdof_270i = 4'b0000; init_rcru_pdof_180i = 4'b0000; init_rcru_pdof_90i = 4'b0000; init_rcru_pdof_0i = 4'b0000; init_rcru_m = (m == 1 ? 4'b0000 : m == 2 ? 4'b0001 : m == 4 ? 4'b0010 : m == 5 ? 4'b0011 : m == 8 ? 4'b0100 : m == 10 ? 4'b0101 : m == 16 ? 4'b0110 : m == 20 ? 4'b0111 : m == 25 ? 4'b1000 : m == 32 ? 4'b1001 : m == 40 ? 4'b1010 : m == 50 ? 4'b1011 : 4'bx); //init_rcru_m = m_init init_rcru_m_sel = (n == 1 ? 2'b00 : n == 2 ? 2'b01 : n == 4 ? 2'b10 : n == 8 ? 2'b11 : 2'b00); //init_rcru_m_sel = n_init init_pfd_clk_sel = (pfd_clk_select >= 0) && (pfd_clk_select <= 9) ? pfd_clk_select : 4'b0000; //init_pfd_clk_sel = pfd_clk_sel_init init_vco_post_scale = (vco_post_scale == 0 ? 1 : vco_post_scale); init_pfd_fb_select = (alpha_tolower(pfd_fb_select) == "pldclk" ? 2'b10 : alpha_tolower(pfd_fb_select) == "iqtxrxclk" ? 2'b11 : 2'b00); end // --------------------------------------------------------------------------- // New DPRIO End // --------------------------------------------------------------------------- // Read in Dynamic CRAMs ----------------------------------------------------- assign m_dprioin_modulus = (cram_rcru_m === 4'b0000) ? 8'b00000001 : (cram_rcru_m === 4'b0001) ? 8'b00000010 : (cram_rcru_m === 4'b0010) ? 8'b00000100 : (cram_rcru_m === 4'b0011) ? 8'b00000101 : (cram_rcru_m === 4'b0100) ? 8'b00001000 : (cram_rcru_m === 4'b0101) ? 8'b00001010 : (cram_rcru_m === 4'b0110) ? 8'b00010000 : (cram_rcru_m === 4'b0111) ? 8'b00010100 : (cram_rcru_m === 4'b1000) ? 8'b00011001 : (cram_rcru_m === 4'b1001) ? 8'b00100000 : (cram_rcru_m === 4'b1010) ? 8'b00101000 : (cram_rcru_m === 4'b1011) ? 8'b00110010 : 8'b00000001; assign n_dprioin_modulus = (cram_rcru_m_sel === 2'b00) ? 8'b00000001 : (cram_rcru_m_sel === 2'b01) ? 8'b00000010 : (cram_rcru_m_sel === 2'b10) ? 8'b00000100 : 8'b00000001; // --------------------------------------------------------------------------- // Model / Submodule Instantiations - // --------------------------------------------------------------------------- `define S4_HSSI_PLL_INITIAL 2'b01 `define S4_HSSI_PLL_ACTIVE 2'b11 `define S4_HSSI_PLL_INACTIVE 2'b00 wire areset_ipd; wire ck0_pd; wire ck90_pd; wire ck180_pd; wire ck270_pd; wire datain_ipd; wire dpriodisable_ipd; wire [299:0] dprioin_ipd; wire [9:0] inclk_ipd; wire locktorefclk_ipd; wire pfdfbclk_ipd; wire powerdown_ipd; wire rateswitch_ipd; // DPRIO wire dprioenable; reg dprioen_reg; wire [7:0] cru_l_chn; assign areset_ipd = (areset === 1'b1) ? 1'b1 : 1'b0; assign datain_ipd = (datain === 1'b1) ? 1'b1 : 1'b0; assign dpriodisable_ipd = (dpriodisable === 1'b0) ? 1'b0 : 1'b1; // making 1’b1 default value when port has x or z value. assign locktorefclk_ipd = (locktorefclk === 1'b1) ? 1'b1 : 1'b0; assign powerdown_ipd = (powerdown === 1'b1) ? 1'b1 : 1'b0; assign pfdfbclk_ipd = (pfdfbclk === 1'b1) ? 1'b1 : 1'b0; assign rateswitch_ipd = (rateswitch === 1'b1) ? 1'b1 : 1'b0; assign dprioin_ipd = dprioin; assign inclk_ipd = inclk; specify (inclk *> clk) = (0,0); endspecify // intermediate wires wire [1:0] busy; // VCO state wire charge_pump_delayed; wire check_phase; wire clk_div; wire clk_div_delayed; wire [3:0] clk_post_scale; wire [3:0] clk_vco; wire datain_dly; wire divide_by_M_clkout; wire fbclk; wire [3:0] pcie_clk; wire pcie_div2_clk0; wire pcie_div2_clk1; wire pfd_refclk; wire pll_clkin; wire pll_clkin_pre_latency; wire reset; reg deven, devenb; reg dodd, doddb; reg deven_int1; reg deven_int2; reg dodd_int1; reg dodd_int2; reg d90_int1; reg d90_int2; reg d270_int1; reg d270_int2; reg pcie_div2_clk2; reg pcie_div2_clk3; wire pdb; reg charge_pump; // re-adjust VCO frequency reg adjust_without_lol; real last_fb_clk_edge; real expected_clk_period; real clk_tolerance; real real_clk_period; real last_pfd_refclk_edge; real last_pll_clkin_edge; real last_real_clk_period; reg first_pll_clkin_edge_detect; reg display_msgs; reg freq_viol_msg_sem; reg locked_real; wire dprio_reset; // reset through DPRIO CRAM in 7.1 wire [7:0] d_wire; genvar j; function real select_clock_period; input clk_select; integer clk_select; real period; begin case (clk_select) 0 : period = inclk0_input_period; 1 : period = inclk1_input_period; 2 : period = inclk2_input_period; 3 : period = inclk3_input_period; 4 : period = inclk4_input_period; 5 : period = inclk5_input_period; 6 : period = inclk6_input_period; 7 : period = inclk7_input_period; 8 : period = inclk8_input_period; 9 : period = inclk9_input_period; default : begin $display("Invalid logical clock select"); $display("Time: %0t Instance: %m", $time); end endcase select_clock_period = period; end endfunction // get the absolute value function integer abs; input value; integer value; begin if (value < 0) abs = value * -1; else abs = value; end endfunction // alpha_tolower function function [8*`ALPHA_TOLOWER_WORD_LENGTH:1] alpha_tolower; input [8*`ALPHA_TOLOWER_WORD_LENGTH:1] input_string; reg [8*`ALPHA_TOLOWER_WORD_LENGTH:1] return_string; reg [8*`ALPHA_TOLOWER_WORD_LENGTH:1] reg_string; reg [8:1] tmp; reg [8:1] conv_char; integer byte_count; begin reg_string = input_string; for (byte_count = `ALPHA_TOLOWER_WORD_LENGTH; byte_count >= 1; byte_count = byte_count - 1) begin tmp = reg_string[8*`ALPHA_TOLOWER_WORD_LENGTH:(8*(`ALPHA_TOLOWER_WORD_LENGTH-1)+1)]; reg_string = reg_string << 8; if ((tmp >= 65) && (tmp <= 90)) // ASCII number of 'A' is 65, 'Z' is 90 begin conv_char = tmp + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set return_string = {return_string, conv_char}; end else return_string = {return_string, tmp}; end alpha_tolower = return_string; end endfunction initial begin charge_pump = 1'b1; first_pll_clkin_edge_detect = 1'b0; expected_clk_period = (select_clock_period(pfd_clk_select)); clk_tolerance = 0.1 * expected_clk_period; // same as Stratix display_msgs = 1'b1; freq_viol_msg_sem = 1'b1; locked_real = 1'b0; adjust_without_lol = 1'b0; end assign pll_clkin_pre_latency = (cram_pfd_clk_sel == 0) ? inclk_ipd[0] : (cram_pfd_clk_sel == 1) ? inclk_ipd[1] : (cram_pfd_clk_sel == 2) ? inclk_ipd[2] : (cram_pfd_clk_sel == 3) ? inclk_ipd[3] : (cram_pfd_clk_sel == 4) ? inclk_ipd[4] : (cram_pfd_clk_sel == 5) ? inclk_ipd[5] : (cram_pfd_clk_sel == 6) ? inclk_ipd[6] : (cram_pfd_clk_sel == 7) ? inclk_ipd[7] : (cram_pfd_clk_sel == 8) ? inclk_ipd[8] : (cram_pfd_clk_sel == 9) ? inclk_ipd[9] : inclk_ipd[0]; assign reset = areset_ipd | powerdown_ipd | dprio_reset; assign pdb = !powerdown_ipd; // DPRIO assign dprioenable = ~dpriodisable_ipd; assign cru_l_chn = dprioin_ipd[15:8]; assign dprio_reset = ((dprioenable === 1'b1) && (dprioin_ipd[16] === 1'b1 || dprioin_ipd[17] === 1'b1)) ? 1'b1 : 1'b0; // Clock latency reg [sim_clkout_latency:0] clkin_pre_latency; initial begin clkin_pre_latency = 'b0; end always@(posedge pll_clkin_pre_latency or negedge pll_clkin_pre_latency or posedge reset) begin if (reset) begin clkin_pre_latency = 'b0; end else begin clkin_pre_latency <= {clkin_pre_latency, clkin_pre_latency[0]}; clkin_pre_latency[0] <= pll_clkin_pre_latency; end end assign pll_clkin = clkin_pre_latency[sim_clkout_latency]; // DPRIO : Register the dprioenable signal to avoid asynchronous reconfiguration always @(posedge pll_clkin) begin dprioen_reg <= dprioenable; end // N counter stratixiv_hssi_aux_clock_div n_cntr (.clk(pll_clkin), .enable_d(dprioenable), .d(n_dprioin_modulus), .reset(reset), .clkout(pfd_refclk) ); defparam n_cntr.clk_divide_by = n; defparam n_cntr.extra_latency = 0; // Input frequency checks always @(posedge pll_clkin or posedge reset) begin if (reset) begin first_pll_clkin_edge_detect = 1'b0; end else begin if (first_pll_clkin_edge_detect == 1'b0) first_pll_clkin_edge_detect = 1'b1; else begin real_clk_period = $realtime - last_pll_clkin_edge; if ((real_clk_period < expected_clk_period - clk_tolerance) || (real_clk_period > expected_clk_period + clk_tolerance)) begin if (freq_viol_msg_sem == 1'b1) begin $display("Warning : CMU PLL input frequency mismatch between parameter-specified period and real clock period"); $display("Time: %0t Instance: %m", $time); $display("Clock period specified in parameter is %0t but real clock period is %0t",expected_clk_period,real_clk_period); freq_viol_msg_sem = 1'b0; end end if ((real_clk_period != last_real_clk_period) && (last_real_clk_period > 0)) begin charge_pump = 1'b1; if (abs(real_clk_period - last_real_clk_period) <= 2) adjust_without_lol = 1'b1; end last_real_clk_period = real_clk_period; end last_pll_clkin_edge = $realtime; end end // PFD always @(posedge pfd_refclk) last_pfd_refclk_edge = $realtime; always @(posedge fbclk) last_fb_clk_edge = $realtime; always @(negedge pfd_refclk) begin if (($realtime > 0) && (busy != `S4_HSSI_PLL_ACTIVE) && (busy != `S4_HSSI_PLL_INITIAL)) begin // charge_pump = (last_pfd_refclk_edge != last_fb_clk_edge); if (last_pfd_refclk_edge != last_fb_clk_edge) begin charge_pump = 1'b1; if (locked == 1'b1) adjust_without_lol = 1'b1; end else charge_pump = 1'b0; end end always @(negedge reset) begin charge_pump = 1'b1; adjust_without_lol = 1'b0; display_msgs = 1'b1; end always @(posedge reset) begin if (reset == 1'b1) begin $display ("Note : CMU PLL is reset"); $display ("Time: %0t Instance: %m", $time); end end always @(charge_pump) begin if (charge_pump == 1'b1 && adjust_without_lol == 1'b0) begin if (display_msgs == 1'b0) begin $display ("Note : CMU PLL lost lock due to reset or change in frequency of input clock"); $display ("Time: %0t Instance: %m", $time); display_msgs = 1'b1; end end else begin if (display_msgs == 1'b1) begin $display ("Note : CMU PLL locked to incoming clock"); $display ("Time: %0t Instance: %m", $time); display_msgs = 1'b0; end end end always @(busy) begin if (busy == `S4_HSSI_PLL_INACTIVE) begin charge_pump = 1'b0; adjust_without_lol = 1'b0; end end // VCO stratixiv_hssi_aux_clock_mult vco ( .clk(pfd_refclk), .fbclk(fbclk), .adjust(charge_pump), .adjust_without_lol(adjust_without_lol), .reset(reset), .enable_m(dprioenable), .m(m_dprioin_modulus), .clkout(clk_vco), // VCO output .busy(busy) ); defparam vco.clk_multiply_by = m; defparam vco.pfd_fb_select = pfd_fb_select; reg [3:0] clk_post_scale_tmp; initial begin clk_post_scale_tmp = 'b0; end generate for (j = 0; j < 4; j = j + 1) begin : post_scale always@(posedge clk_vco[j] or negedge clk_vco[j] or posedge reset) begin if (reset) begin clk_post_scale_tmp[j] = 1'b0; end else begin clk_post_scale_tmp[j] = clk_vco[j]; end end end endgenerate assign clk_post_scale = clk_post_scale_tmp; // Feedback stratixiv_hssi_aux_clock_div divide_by_M ( .clk(clk_post_scale[0]), .reset(reset), .enable_d(dprioen_reg), .d(m_dprioin_modulus), // .clkout(fbclk) .clkout(divide_by_M_clkout) ); defparam divide_by_M.clk_divide_by = m; defparam divide_by_M.extra_latency = 0; assign fbclk = (init_pfd_fb_select == 2'b00) ? divide_by_M_clkout : pfdfbclk_ipd; // PCIE divide-by-2 stratixiv_hssi_aux_clock_div pcie_sw_0 (.clk(clk_post_scale[0]), .enable_d(1'b0), .d(d_wire), .reset(reset), .clkout(pcie_div2_clk0) ); defparam pcie_sw_0.clk_divide_by = 2; defparam pcie_sw_0.extra_latency = 0; always @(posedge reset or pcie_div2_clk0) begin if (reset == 1'b1) pcie_div2_clk2 <= 1'b0; else pcie_div2_clk2 <= ~pcie_div2_clk0; end stratixiv_hssi_aux_clock_div pcie_sw_1 (.clk(!clk_post_scale[0]), .enable_d(1'b0), .d(d_wire), .reset(reset), .clkout(pcie_div2_clk1) ); defparam pcie_sw_1.clk_divide_by = 2; defparam pcie_sw_1.extra_latency = 0; always @(posedge reset or pcie_div2_clk1) begin if (reset == 1'b1) pcie_div2_clk3 <= 1'b0; else pcie_div2_clk3 <= ~pcie_div2_clk1; end always @(busy or reset) begin if (reset === 1'b1) locked_real <= 1'b0; else if (busy == `S4_HSSI_PLL_INACTIVE || adjust_without_lol == 1'b1) locked_real <= 1'b1; else locked_real <= 1'b0; end assign pcie_clk[0] = (rateswitch_ipd === 1'b0) ? pcie_div2_clk0 : clk_post_scale[0]; assign pcie_clk[1] = (rateswitch_ipd === 1'b0) ? pcie_div2_clk1 : clk_post_scale[1]; assign pcie_clk[2] = (rateswitch_ipd === 1'b0) ? pcie_div2_clk2 : clk_post_scale[2]; assign pcie_clk[3] = (rateswitch_ipd === 1'b0) ? pcie_div2_clk3 : clk_post_scale[3]; initial begin deven_int2 <= 1'b0; dodd_int2 <= 1'b0; end assign ck0_pd = (cram_rdynamic_sw === 1'b1) ? pcie_clk[0] : clk_post_scale[0]; assign ck90_pd = (cram_rdynamic_sw === 1'b1) ? pcie_clk[1] : clk_post_scale[1]; assign ck180_pd = (cram_rdynamic_sw === 1'b1) ? pcie_clk[2] : clk_post_scale[2]; assign ck270_pd = (cram_rdynamic_sw === 1'b1) ? pcie_clk[3] : clk_post_scale[3]; assign #5 datain_dly = datain_ipd; // PD : from ICD RTL c_cdr.v WW5 always @ ( ck0_pd or negedge pdb ) if ( pdb == 1'b0 ) deven_int1 <= #(PARAM_DELAY) 1'b0; else begin if ( ( ck0_pd == 1'b1 ) ) deven_int1 <= #(PARAM_DELAY) datain_dly; else if ( ck0_pd == 1'b0 ) deven_int2 <= #(PARAM_DELAY) deven_int1; end always @ ( ck180_pd or negedge pdb ) if ( pdb == 1'b0 ) dodd_int1 <= #(PARAM_DELAY) 1'b0; else begin if ( ( ck180_pd == 1'b1 ) ) dodd_int1 <= #(PARAM_DELAY) datain_dly; else if ( ck180_pd == 1'b0 ) dodd_int2 <= #(PARAM_DELAY) dodd_int1; end always @ ( posedge ck90_pd or negedge pdb ) if ( pdb == 1'b0 ) begin {deven ,dodd } <= #(PARAM_DELAY) 2'b00; end else begin {deven ,dodd } <= #(PARAM_DELAY) {deven_int2,dodd_int2}; end assign clk[0] = ck0_pd && (locked || (init_pfd_fb_select == 2'b11)); assign clk[1] = ck90_pd && (locked || (init_pfd_fb_select == 2'b11)); assign clk[2] = ck180_pd && (locked || (init_pfd_fb_select == 2'b11)); assign clk[3] = ck270_pd && (locked || (init_pfd_fb_select == 2'b11)); assign dataout[0] = deven; assign dataout[1] = dodd; assign locked = locked_real; assign pfdfbclkout = fbclk; assign pfdrefclkout = pfd_refclk; assign vcobypassout = pll_clkin; assign freqlocked = ~locktorefclk_ipd; endmodule // *********************************************************** // This WYSIWYG atom header was automatically generated by the // Atmgen build tool. To change it, alter data stored in the // corresponding WYS file(s) in the tools/atmgen subdirectory. // *********************************************************** // *** Section 1 -- Header *** // ----------------------------------------------------------- // // Module Name : stratixiv_hssi_tx_pma // // Description : DEV_FAMILY_STRATIXIV stratixiv_hssi_tx_pma Verilog simulation model // // ----------------------------------------------------------- `timescale 1 ps/1 ps // *** End of Section 1 *** // *** Section 3 -- Module declaration *** module stratixiv_hssi_tx_pma( datain, datainfull, detectrxpowerdown, dpriodisable, dprioin, extra10gin, fastrefclk0in, fastrefclk1in, fastrefclk2in, fastrefclk3in, fastrefclk4in, forceelecidle, pclk, powerdn, refclk0in, refclk0inpulse, refclk1in, refclk1inpulse, refclk2in, refclk2inpulse, refclk3in, refclk3inpulse, refclk4in, refclk4inpulse, revserialfdbk, rxdetectclk, rxdetecten, txpmareset, clockout, dataout, dftout, dprioout, rxdetectvalidout, rxfoundout, seriallpbkout ); // *** End of Section 3 *** // *** Section 4 -- Port size declarations *** // Note: Variable port sizes dictated by parameters are not currently defined in // the WYS file data. Busses are marked with the VARIABLE notation as a reminder. `define CLOCKOUT_PORTSIZE_CONST_stratixiv_hssi_tx_pma 1 `define DATAIN_PORTSIZE_CONST_stratixiv_hssi_tx_pma 64 // * VARIABLE `define DATAINFULL_PORTSIZE_CONST_stratixiv_hssi_tx_pma 20 // * VARIABLE `define DATAOUT_PORTSIZE_CONST_stratixiv_hssi_tx_pma 1 `define DETECTRXPOWERDOWN_PORTSIZE_CONST_stratixiv_hssi_tx_pma 1 `define DFTOUT_PORTSIZE_CONST_stratixiv_hssi_tx_pma 6 // * VARIABLE `define DPRIODISABLE_PORTSIZE_CONST_stratixiv_hssi_tx_pma 1 `define DPRIOIN_PORTSIZE_CONST_stratixiv_hssi_tx_pma 300 // * VARIABLE `define DPRIOOUT_PORTSIZE_CONST_stratixiv_hssi_tx_pma 300 // * VARIABLE `define EXTRA10GIN_PORTSIZE_CONST_stratixiv_hssi_tx_pma 11 // * VARIABLE `define FASTREFCLK0IN_PORTSIZE_CONST_stratixiv_hssi_tx_pma 2 // * VARIABLE `define FASTREFCLK1IN_PORTSIZE_CONST_stratixiv_hssi_tx_pma 2 // * VARIABLE `define FASTREFCLK2IN_PORTSIZE_CONST_stratixiv_hssi_tx_pma 2 // * VARIABLE `define FASTREFCLK3IN_PORTSIZE_CONST_stratixiv_hssi_tx_pma 2 // * VARIABLE `define FASTREFCLK4IN_PORTSIZE_CONST_stratixiv_hssi_tx_pma 2 `define FORCEELECIDLE_PORTSIZE_CONST_stratixiv_hssi_tx_pma 1 `define PCLK_PORTSIZE_CONST_stratixiv_hssi_tx_pma 5 `define POWERDN_PORTSIZE_CONST_stratixiv_hssi_tx_pma 1 `define REFCLK0IN_PORTSIZE_CONST_stratixiv_hssi_tx_pma 2 // * VARIABLE `define REFCLK0INPULSE_PORTSIZE_CONST_stratixiv_hssi_tx_pma 1 `define REFCLK1IN_PORTSIZE_CONST_stratixiv_hssi_tx_pma 2 // * VARIABLE `define REFCLK1INPULSE_PORTSIZE_CONST_stratixiv_hssi_tx_pma 1 `define REFCLK2IN_PORTSIZE_CONST_stratixiv_hssi_tx_pma 2 // * VARIABLE `define REFCLK2INPULSE_PORTSIZE_CONST_stratixiv_hssi_tx_pma 1 `define REFCLK3IN_PORTSIZE_CONST_stratixiv_hssi_tx_pma 2 // * VARIABLE `define REFCLK3INPULSE_PORTSIZE_CONST_stratixiv_hssi_tx_pma 1 `define REFCLK4IN_PORTSIZE_CONST_stratixiv_hssi_tx_pma 2 `define REFCLK4INPULSE_PORTSIZE_CONST_stratixiv_hssi_tx_pma 1 `define REVSERIALFDBK_PORTSIZE_CONST_stratixiv_hssi_tx_pma 1 `define RXDETECTCLK_PORTSIZE_CONST_stratixiv_hssi_tx_pma 1 `define RXDETECTEN_PORTSIZE_CONST_stratixiv_hssi_tx_pma 1 `define RXDETECTVALIDOUT_PORTSIZE_CONST_stratixiv_hssi_tx_pma 1 `define RXFOUNDOUT_PORTSIZE_CONST_stratixiv_hssi_tx_pma 1 `define SERIALLPBKOUT_PORTSIZE_CONST_stratixiv_hssi_tx_pma 1 `define TXPMARESET_PORTSIZE_CONST_stratixiv_hssi_tx_pma 1 // *** End of Section 4 *** // *** Section 5 -- Port declarations *** input [`DATAIN_PORTSIZE_CONST_stratixiv_hssi_tx_pma - 1 : 0] datain; input [`DATAINFULL_PORTSIZE_CONST_stratixiv_hssi_tx_pma - 1 : 0] datainfull; input detectrxpowerdown; input dpriodisable; input [`DPRIOIN_PORTSIZE_CONST_stratixiv_hssi_tx_pma - 1 : 0] dprioin; input [`EXTRA10GIN_PORTSIZE_CONST_stratixiv_hssi_tx_pma - 1 : 0] extra10gin; input [`FASTREFCLK0IN_PORTSIZE_CONST_stratixiv_hssi_tx_pma - 1 : 0] fastrefclk0in; input [`FASTREFCLK1IN_PORTSIZE_CONST_stratixiv_hssi_tx_pma - 1 : 0] fastrefclk1in; input [`FASTREFCLK2IN_PORTSIZE_CONST_stratixiv_hssi_tx_pma - 1 : 0] fastrefclk2in; input [`FASTREFCLK3IN_PORTSIZE_CONST_stratixiv_hssi_tx_pma - 1 : 0] fastrefclk3in; input [`FASTREFCLK4IN_PORTSIZE_CONST_stratixiv_hssi_tx_pma - 1 : 0] fastrefclk4in; input forceelecidle; input [`PCLK_PORTSIZE_CONST_stratixiv_hssi_tx_pma - 1 : 0] pclk; input powerdn; input [`REFCLK0IN_PORTSIZE_CONST_stratixiv_hssi_tx_pma - 1 : 0] refclk0in; input refclk0inpulse; input [`REFCLK1IN_PORTSIZE_CONST_stratixiv_hssi_tx_pma - 1 : 0] refclk1in; input refclk1inpulse; input [`REFCLK2IN_PORTSIZE_CONST_stratixiv_hssi_tx_pma - 1 : 0] refclk2in; input refclk2inpulse; input [`REFCLK3IN_PORTSIZE_CONST_stratixiv_hssi_tx_pma - 1 : 0] refclk3in; input refclk3inpulse; input [`REFCLK4IN_PORTSIZE_CONST_stratixiv_hssi_tx_pma - 1 : 0] refclk4in; input refclk4inpulse; input revserialfdbk; input rxdetectclk; input rxdetecten; input txpmareset; output clockout; output dataout; output [`DFTOUT_PORTSIZE_CONST_stratixiv_hssi_tx_pma - 1 : 0] dftout; output [`DPRIOOUT_PORTSIZE_CONST_stratixiv_hssi_tx_pma - 1 : 0] dprioout; output rxdetectvalidout; output rxfoundout; output seriallpbkout; // *** End of Section 5 *** // *** Section 6 -- Parameter declarations and default values *** parameter lpm_type = "stratixiv_hssi_tx_pma"; parameter analog_power = "1.5V"; parameter channel_number = 0 ; parameter channel_type = "auto"; parameter clkin_select = 0 ; parameter clkmux_delay = "false"; parameter common_mode = "0.6v"; parameter dprio_config_mode = 6'h00; parameter enable_reverse_serial_loopback = "false"; parameter logical_channel_address = 0 ; parameter logical_protocol_hint_0 = "basic"; parameter logical_protocol_hint_1 = "basic"; parameter logical_protocol_hint_2 = "basic"; parameter logical_protocol_hint_3 = "basic"; parameter low_speed_test_select = 0 ; parameter physical_clkin0_mapping = "x1"; parameter physical_clkin1_mapping = "x4"; parameter physical_clkin2_mapping = "xn_top"; parameter physical_clkin3_mapping = "xn_bottom"; parameter physical_clkin4_mapping = "hypertransport"; parameter preemp_pretap = 0 ; parameter preemp_pretap_inv = "false"; parameter preemp_tap_1 = 0 ; parameter preemp_tap_1_a = 0 ; parameter preemp_tap_1_b = 0 ; parameter preemp_tap_1_c = 0 ; parameter preemp_tap_2 = 0 ; parameter preemp_tap_2_inv = "false"; parameter protocol_hint = "basic"; parameter rx_detect = 0 ; parameter serialization_factor = 8 ; parameter slew_rate = "low"; parameter termination = "oct 100 ohms"; parameter use_external_termination = "false"; parameter use_pclk = "false"; parameter use_pma_direct = "false"; parameter use_rx_detect = "false"; parameter use_ser_double_data_mode = "false"; parameter vod_selection = 0 ; parameter vod_selection_a = 0 ; parameter vod_selection_b = 0 ; parameter vod_selection_c = 0 ; parameter vod_selection_d = 0 ; // *** End of Section 6 *** // *** Section 7 -- Port declarations with defaults, if any *** // This section will always be empty for WYSIWYG atoms // tri1 devclrn; //sample // *** End of Section 7 *** // LOCAL_PARAMETERS_BEGIN parameter DPRIO_CHANNEL_INTERFACE_BIT = 4; // LOCAL_PARAMETERS_END `define STRATIXIV_HSSI_TX_PMA_ALPHA_TOLOWER_WORD_LENGTH 25 // --------------------------------------------------------------------------- // New DPRIO Begin // --------------------------------------------------------------------------- // Table28: PMA Per Channel TX Control Register 1 for Channel 0 `define rpowdnt_TXPMA_IDX_0 0 `define rvod_seld_TXPMA_IDX_0 1 `define rvod_seld_TXPMA_IDX_1 2 `define rvod_seld_TXPMA_IDX_2 3 `define rvod_selc_TXPMA_IDX_0 4 `define rvod_selc_TXPMA_IDX_1 5 `define rvod_selc_TXPMA_IDX_2 6 `define rvod_selb_TXPMA_IDX_0 7 `define rvod_selb_TXPMA_IDX_1 8 `define rvod_selb_TXPMA_IDX_2 9 `define rvod_sela_TXPMA_IDX_0 10 `define rvod_sela_TXPMA_IDX_1 11 `define rvod_sela_TXPMA_IDX_2 12 `define rvod_sel_non_pcie_TXPMA_IDX_0 13 `define rvod_sel_non_pcie_TXPMA_IDX_1 14 `define rvod_sel_non_pcie_TXPMA_IDX_2 15 // Table29: PMA Per Channel TX Control Register 2 for Channel 0 `define reserved_0_TB29_TXPMA_IDX_0 16 `define rpre_em_1t_b_TXPMA_IDX_0 17 `define rpre_em_1t_b_TXPMA_IDX_1 18 `define rpre_em_1t_b_TXPMA_IDX_2 19 `define rpre_em_1t_b_TXPMA_IDX_3 20 `define rpre_em_1t_b_TXPMA_IDX_4 21 `define rpre_em_1t_a_TXPMA_IDX_0 22 `define rpre_em_1t_a_TXPMA_IDX_1 23 `define rpre_em_1t_a_TXPMA_IDX_2 24 `define rpre_em_1t_a_TXPMA_IDX_3 25 `define rpre_em_1t_a_TXPMA_IDX_4 26 `define rpre_em_1t_no_pcie_TXPMA_IDX_0 27 `define rpre_em_1t_no_pcie_TXPMA_IDX_1 28 `define rpre_em_1t_no_pcie_TXPMA_IDX_2 29 `define rpre_em_1t_no_pcie_TXPMA_IDX_3 30 `define rpre_em_1t_no_pcie_TXPMA_IDX_4 31 // Table30: PMA Per Channel TX Control Register 3 for Channel 0 `define rpre_em_pt_TXPMA_IDX_0 32 `define rpre_em_pt_TXPMA_IDX_1 33 `define rpre_em_pt_TXPMA_IDX_2 34 `define rpre_em_pt_TXPMA_IDX_3 35 `define rpre_em_2t_TXPMA_IDX_0 36 `define rpre_em_2t_TXPMA_IDX_1 37 `define rpre_em_2t_TXPMA_IDX_2 38 `define rpre_em_2t_TXPMA_IDX_3 39 `define rpre_em_1t_c_TXPMA_IDX_0 40 `define rpre_em_1t_c_TXPMA_IDX_1 41 `define rpre_em_1t_c_TXPMA_IDX_2 42 `define rpre_em_1t_c_TXPMA_IDX_3 43 `define rpre_em_1t_c_TXPMA_IDX_4 44 `define reserved_0_TB30_TXPMA_IDX_0 45 `define reserved_0_TB30_TXPMA_IDX_1 46 `define reserved_0_TB30_TXPMA_IDX_2 47 // Table31: PMA Per Channel TX Control Register 4 for Channel 0 `define rlowv_TXPMA_IDX_0 48 `define rrx_det_TXPMA_IDX_0 49 `define rrx_det_TXPMA_IDX_1 50 `define rsig_inv_2t_TXPMA_IDX_0 51 `define rsig_inv_ptap_TXPMA_IDX_0 52 `define rslew_TXPMA_IDX_0 53 `define rslew_TXPMA_IDX_1 54 `define rtx_lst_TXPMA_IDX_0 55 `define rtx_lst_TXPMA_IDX_1 56 `define rtx_lst_TXPMA_IDX_2 57 `define rtx_lst_TXPMA_IDX_3 58 `define rtx_vtt_TXPMA_IDX_0 59 `define rtx_vtt_TXPMA_IDX_1 60 `define rtx_term_sel_TXPMA_IDX_0 61 `define rtx_term_sel_TXPMA_IDX_1 62 `define rtx_term_sel_TXPMA_IDX_2 63 // Table32: PMA Per Channel TX Control Register 5 for Channel 0 `define reserved_1_TB32_TXPMA_IDX_0 64 `define reserved_1_TB32_TXPMA_IDX_1 65 `define reserved_1_TB32_TXPMA_IDX_2 66 `define reserved_1_TB32_TXPMA_IDX_3 67 `define reserved_1_TB32_TXPMA_IDX_4 68 `define reserved_1_TB32_TXPMA_IDX_5 69 `define reserved_1_TB32_TXPMA_IDX_6 70 `define reserved_1_TB32_TXPMA_IDX_7 71 `define reserved_1_TB32_TXPMA_IDX_8 72 `define reserved_1_TB32_TXPMA_IDX_9 73 `define reserved_1_TB32_TXPMA_IDX_10 74 `define rtx_ob_pdb_TXPMA_IDX_0 75 `define reserved_0_TB32_TXPMA_IDX_0 76 `define r_dft_sel_TXPMA_IDX_0 77 `define r_dft_sel_TXPMA_IDX_1 78 `define r_dft_sel_TXPMA_IDX_2 79 // Table33: PMA Per Channel TX Control Register 6 for Channel 0 `define reserved_0_TB33_TXPMA_IDX_0 80 `define reserved_0_TB33_TXPMA_IDX_1 81 `define reserved_0_TB33_TXPMA_IDX_2 82 `define reserved_0_TB33_TXPMA_IDX_3 83 `define rtx_cgb_pdb_TXPMA_IDX_0 84 `define rpclksel_TXPMA_IDX_0 85 `define rdynamic_sw_TXPMA_IDX_0 86 `define rs_lpbk_TXPMA_IDX_0 87 `define rcgb_delay_sel_TXPMA_IDX_0 88 `define rpmadwidth_tx_TXPMA_IDX_0 89 `define rpma_doublewidth_tx_TXPMA_IDX_0 90 `define rcgb_m_sel_TXPMA_IDX_0 91 `define rcgb_m_sel_TXPMA_IDX_1 92 `define rcgb_cmu_sel_TXPMA_IDX_0 93 `define rcgb_x_en_TXPMA_IDX_0 94 `define rcgb_x_en_TXPMA_IDX_1 95 // Table34: PMA Per Channel TX Control Register 7 for Channel 0 `define reserved_1_TB34_TXPMA_IDX_0 96 `define reserved_1_TB34_TXPMA_IDX_1 97 `define reserved_1_TB34_TXPMA_IDX_2 98 `define rpcs_sd_sel_TXPMA_IDX_0 99 `define rrx_refclk_TXPMA_IDX_0 100 `define rimpctrl_TXPMA_IDX_0 101 `define reserved_0_TB34_TXPMA_IDX_0 102 `define reserved_0_TB34_TXPMA_IDX_1 103 `define reserved_0_TB34_TXPMA_IDX_2 104 `define reserved_0_TB34_TXPMA_IDX_3 105 `define rrevlb_sw_TXPMA_IDX_0 106 `define rvcobypass_TXPMA_IDX_0 107 `define rrefclk_sel_TXPMA_IDX_0 108 `define rrefclk_sel_TXPMA_IDX_1 109 `define riqclk_sel_TXPMA_IDX_0 110 `define riqclk_sel_TXPMA_IDX_1 111 // Table35: PMA Per Channel TX Control Register 8 for Channel 0 `define rpma_reserved_0_TB35_TXPMA_IDX_0 112 `define rpma_reserved_0_TB35_TXPMA_IDX_1 113 `define rpma_reserved_0_TB35_TXPMA_IDX_2 114 `define rpma_reserved_0_TB35_TXPMA_IDX_3 115 `define rpma_reserved_0_TB35_TXPMA_IDX_4 116 `define rpma_reserved_0_TB35_TXPMA_IDX_5 117 `define rpma_reserved_0_TB35_TXPMA_IDX_6 118 `define rpma_reserved_0_TB35_TXPMA_IDX_7 119 `define rpma_reserved_0_TB35_TXPMA_IDX_8 120 `define rpma_reserved_0_TB35_TXPMA_IDX_9 121 `define rpma_reserved_0_TB35_TXPMA_IDX_10 122 `define rpma_reserved_0_TB35_TXPMA_IDX_11 123 `define rpma_reserved_0_TB35_TXPMA_IDX_12 124 `define rpma_reserved_0_TB35_TXPMA_IDX_13 125 `define rpma_reserved_0_TB35_TXPMA_IDX_14 126 `define rpma_reserved_0_TB35_TXPMA_IDX_15 127 // Extra `define ht_sel_TX_PMA_IDX 128 // SW logical index ---------------------------------------------------------- `define CLKIN_SELECT_TXPMA_IDX_0 200 `define CLKIN_SELECT_TXPMA_IDX_1 201 `define CLKIN_SELECT_TXPMA_IDX_2 202 // --------------------------------------------------------------------------- // DPRIO input CRAM // --------------------------------------------------------------------------- // PMA Per Channel TX Control Register 1 for Channel 0 wire dprioin_rpowdnt; wire [2:0] dprioin_rvod_seld; wire [2:0] dprioin_rvod_selc; wire [2:0] dprioin_rvod_selb; wire [2:0] dprioin_rvod_sela; wire [2:0] dprioin_rvod_sel_non_pcie; // PMA Per Channel TX Control Register 2 for Channel 0 wire dprioin_reserved_0_TB29; wire [4:0] dprioin_rpre_em_1t_b; wire [4:0] dprioin_rpre_em_1t_a; wire [4:0] dprioin_rpre_em_1t_no_pcie; // PMA Per Channel TX Control Register 3 for Channel 0 wire [3:0] dprioin_rpre_em_pt; wire [3:0] dprioin_rpre_em_2t; wire [4:0] dprioin_rpre_em_1t_c; wire [2:0] dprioin_reserved_0_TB30; // PMA Per Channel TX Control Register 4 for Channel 0 wire dprioin_rlowv; wire [1:0] dprioin_rrx_det; wire dprioin_rsig_inv_2t; wire dprioin_rsig_inv_ptap; wire [1:0] dprioin_rslew; wire [3:0] dprioin_rtx_lst; wire [1:0] dprioin_rtx_vtt; wire [2:0] dprioin_rtx_term_sel; // PMA Per Channel TX Control Register 5 for Channel 0 wire [10:0] dprioin_reserved_1_TB32; wire dprioin_rtx_ob_pdb; wire dprioin_reserved_0_TB32; wire [2:0] dprioin_r_dft_sel; // PMA Per Channel TX Control Register 6 for Channel 0 wire [3:0] dprioin_reserved_0_TB33; wire dprioin_rtx_cgb_pdb; wire dprioin_rpclksel; wire dprioin_rdynamic_sw; wire dprioin_rs_lpbk; wire dprioin_rcgb_delay_sel; wire dprioin_rpmadwidth_tx; wire dprioin_rpma_doublewidth_tx; wire [1:0] dprioin_rcgb_m_sel; wire dprioin_rcgb_cmu_sel; wire [1:0] dprioin_rcgb_x_en; // PMA Per Channel TX Control Register 7 for Channel 0 wire [2:0] dprioin_reserved_1_TB34; wire dprioin_rpcs_sd_sel; wire dprioin_rrx_refclk; wire dprioin_rimpctrl; wire [3:0] dprioin_reserved_0_TB34; wire dprioin_rrevlb_sw; wire dprioin_rvcobypass; wire [1:0] dprioin_rrefclk_sel; wire [1:0] dprioin_riqclk_sel; // PMA Per Channel TX Control Register 8 for Channel 0 wire [15:0] dprioin_rpma_reserved_0_TB35; // Extra wire dprioin_ht_sel; wire [2:0] dprioin_clkin_sel; // --------------------------------------------------------------------------- // Initial CRAM // --------------------------------------------------------------------------- // PMA Per Channel TX Control Register 1 for Channel 0 reg init_rpowdnt; reg [2:0] init_rvod_seld; reg [2:0] init_rvod_selc; reg [2:0] init_rvod_selb; reg [2:0] init_rvod_sela; reg [2:0] init_rvod_sel_non_pcie; // PMA Per Channel TX Control Register 2 for Channel 0 reg init_reserved_0_TB29; reg [4:0] init_rpre_em_1t_b; reg [4:0] init_rpre_em_1t_a; reg [4:0] init_rpre_em_1t_no_pcie; // PMA Per Channel TX Control Register 3 for Channel 0 reg [3:0] init_rpre_em_pt; reg [3:0] init_rpre_em_2t; reg [4:0] init_rpre_em_1t_c; reg [2:0] init_reserved_0_TB30; // PMA Per Channel TX Control Register 4 for Channel 0 reg init_rlowv; reg [1:0] init_rrx_det; reg init_rsig_inv_2t; reg init_rsig_inv_ptap; reg [1:0] init_rslew; reg [3:0] init_rtx_lst; reg [1:0] init_rtx_vtt; reg [2:0] init_rtx_term_sel; // PMA Per Channel TX Control Register 5 for Channel 0 reg [10:0] init_reserved_1_TB32; reg init_rtx_ob_pdb; reg init_reserved_0_TB32; reg [2:0] init_r_dft_sel; // PMA Per Channel TX Control Register 6 for Channel 0 reg [3:0] init_reserved_0_TB33; reg init_rtx_cgb_pdb; reg init_rpclksel; reg init_rdynamic_sw; reg init_rs_lpbk; reg init_rcgb_delay_sel; reg init_rpmadwidth_tx; reg init_rpma_doublewidth_tx; reg [1:0] init_rcgb_m_sel; reg init_rcgb_cmu_sel; reg [1:0] init_rcgb_x_en; // PMA Per Channel TX Control Register 7 for Channel 0 reg [2:0] init_reserved_1_TB34; reg init_rpcs_sd_sel; reg init_rrx_refclk; reg init_rimpctrl; reg [3:0] init_reserved_0_TB34; reg init_rrevlb_sw; reg init_rvcobypass; reg [1:0] init_rrefclk_sel; reg [1:0] init_riqclk_sel; // PMA Per Channel TX Control Register 8 for Channel 0 reg [15:0] init_rpma_reserved_0_TB35; // Extra reg init_ht_sel; reg [2:0] init_clkin_sel; // --------------------------------------------------------------------------- // CRAM // --------------------------------------------------------------------------- // PMA Per Channel TX Control Register 1 for Channel 0 wire cram_rpowdnt; wire [2:0] cram_rvod_seld; wire [2:0] cram_rvod_selc; wire [2:0] cram_rvod_selb; wire [2:0] cram_rvod_sela; wire [2:0] cram_rvod_sel_non_pcie; // PMA Per Channel TX Control Register 2 for Channel 0 wire cram_reserved_0_TB29; wire [4:0] cram_rpre_em_1t_b; wire [4:0] cram_rpre_em_1t_a; wire [4:0] cram_rpre_em_1t_no_pcie; // PMA Per Channel TX Control Register 3 for Channel 0 wire [3:0] cram_rpre_em_pt; wire [3:0] cram_rpre_em_2t; wire [4:0] cram_rpre_em_1t_c; wire [2:0] cram_reserved_0_TB30; // PMA Per Channel TX Control Register 4 for Channel 0 wire cram_rlowv; wire [1:0] cram_rrx_det; wire cram_rsig_inv_2t; wire cram_rsig_inv_ptap; wire [1:0] cram_rslew; wire [3:0] cram_rtx_lst; wire [1:0] cram_rtx_vtt; wire [2:0] cram_rtx_term_sel; // PMA Per Channel TX Control Register 5 for Channel 0 wire [10:0] cram_reserved_1_TB32; wire cram_rtx_ob_pdb; wire cram_reserved_0_TB32; wire [2:0] cram_r_dft_sel; // PMA Per Channel TX Control Register 6 for Channel 0 wire [3:0] cram_reserved_0_TB33; wire cram_rtx_cgb_pdb; wire cram_rpclksel; wire cram_rdynamic_sw; wire cram_rs_lpbk; wire cram_rcgb_delay_sel; wire cram_rpmadwidth_tx; wire cram_rpma_doublewidth_tx; wire [1:0] cram_rcgb_m_sel; wire cram_rcgb_cmu_sel; wire [1:0] cram_rcgb_x_en; // PMA Per Channel TX Control Register 7 for Channel 0 wire [2:0] cram_reserved_1_TB34; wire cram_rpcs_sd_sel; wire cram_rrx_refclk; wire cram_rimpctrl; wire [3:0] cram_reserved_0_TB34; wire cram_rrevlb_sw; wire cram_rvcobypass; wire [1:0] cram_rrefclk_sel; wire [1:0] cram_riqclk_sel; // PMA Per Channel TX Control Register 8 for Channel 0 wire [15:0] cram_rpma_reserved_0_TB35; // Extra wire cram_ht_sel; wire [2:0] cram_clkin_sel; // --------------------------------------------------------------------------- // INPUT FILTERING ---------------------------------------------------------- // --------------------------------------------------------------------------- wire detectrxpowerdown_in; wire forceelecidle_in; wire powerdn_in; wire txpmareset_in; wire xtx_rx_found; assign detectrxpowerdown_in = (detectrxpowerdown === 1'b1) ? 1'b0 : 1'b1; // assign dpriodisable = (dpriodisable === 1'b0) ? 1'b0 : 1'b1; assign forceelecidle_in = (forceelecidle === 1'b1) ? 1'b1 : 1'b0; assign powerdn_in = (powerdn === 1'b1) ? 1'b0 : 1'b1; assign txpmareset_in = (txpmareset === 1'b1) ? 1'b0 : 1'b1; // active low // --------------------------------------------------------------------------- // TIMING -- Tco/Tsu/Thold // --------------------------------------------------------------------------- specify // setup/hold check on datain done at tx_pcs level (posedge rxdetecten => (rxfoundout +: xtx_rx_found)) = (0, 0); endspecify // --------------------------------------------------------------------------- // Set DPRIO CRAM input from dprioin // --------------------------------------------------------------------------- // PMA Per Channel TX Control Register 1 for Channel 0 assign dprioin_rpowdnt = dprioin[`rpowdnt_TXPMA_IDX_0]; assign dprioin_rvod_seld = dprioin[`rvod_seld_TXPMA_IDX_2 : `rvod_seld_TXPMA_IDX_0]; assign dprioin_rvod_selc = dprioin[`rvod_selc_TXPMA_IDX_2 : `rvod_selc_TXPMA_IDX_0]; assign dprioin_rvod_selb = dprioin[`rvod_selb_TXPMA_IDX_2 : `rvod_selb_TXPMA_IDX_0]; assign dprioin_rvod_sela = dprioin[`rvod_sela_TXPMA_IDX_2 : `rvod_sela_TXPMA_IDX_0]; assign dprioin_rvod_sel_non_pcie = dprioin[`rvod_sel_non_pcie_TXPMA_IDX_2 : `rvod_sel_non_pcie_TXPMA_IDX_0]; // PMA Per Channel TX Control Register 2 for Channel 0 assign dprioin_reserved_0_TB29 = dprioin[`reserved_0_TB29_TXPMA_IDX_0]; assign dprioin_rpre_em_1t_b = dprioin[`rpre_em_1t_b_TXPMA_IDX_4 : `rpre_em_1t_b_TXPMA_IDX_0]; assign dprioin_rpre_em_1t_a = dprioin[`rpre_em_1t_a_TXPMA_IDX_4 : `rpre_em_1t_a_TXPMA_IDX_0]; assign dprioin_rpre_em_1t_no_pcie = dprioin[`rpre_em_1t_no_pcie_TXPMA_IDX_4 : `rpre_em_1t_no_pcie_TXPMA_IDX_0]; // PMA Per Channel TX Control Register 3 for Channel 0 assign dprioin_rpre_em_pt = dprioin[`rpre_em_pt_TXPMA_IDX_3 : `rpre_em_pt_TXPMA_IDX_0]; assign dprioin_rpre_em_2t = dprioin[`rpre_em_2t_TXPMA_IDX_3 : `rpre_em_2t_TXPMA_IDX_0]; assign dprioin_rpre_em_1t_c = dprioin[`rpre_em_1t_c_TXPMA_IDX_4 : `rpre_em_1t_c_TXPMA_IDX_0]; assign dprioin_reserved_0_TB30 = dprioin[`reserved_0_TB30_TXPMA_IDX_2 : `reserved_0_TB30_TXPMA_IDX_0]; // PMA Per Channel TX Control Register 4 for Channel 0 assign dprioin_rlowv = dprioin[`rlowv_TXPMA_IDX_0]; assign dprioin_rrx_det = dprioin[`rrx_det_TXPMA_IDX_1 : `rrx_det_TXPMA_IDX_0]; assign dprioin_rsig_inv_2t = dprioin[`rsig_inv_2t_TXPMA_IDX_0]; assign dprioin_rsig_inv_ptap = dprioin[`rsig_inv_ptap_TXPMA_IDX_0]; assign dprioin_rslew = dprioin[`rslew_TXPMA_IDX_1 : `rslew_TXPMA_IDX_0]; assign dprioin_rtx_lst = dprioin[`rtx_lst_TXPMA_IDX_3 : `rtx_lst_TXPMA_IDX_0]; assign dprioin_rtx_vtt = dprioin[`rtx_vtt_TXPMA_IDX_1 : `rtx_vtt_TXPMA_IDX_0]; assign dprioin_rtx_term_sel = dprioin[`rtx_term_sel_TXPMA_IDX_2 : `rtx_term_sel_TXPMA_IDX_0]; // PMA Per Channel TX Control Register 5 for Channel 0 assign dprioin_reserved_1_TB32 = dprioin[`reserved_1_TB32_TXPMA_IDX_10 : `reserved_1_TB32_TXPMA_IDX_0]; assign dprioin_rtx_ob_pdb = dprioin[`rtx_ob_pdb_TXPMA_IDX_0]; assign dprioin_reserved_0_TB32 = dprioin[`reserved_0_TB32_TXPMA_IDX_0]; assign dprioin_r_dft_sel = dprioin[`r_dft_sel_TXPMA_IDX_2 : `r_dft_sel_TXPMA_IDX_0]; // PMA Per Channel TX Control Register 6 for Channel 0 assign dprioin_reserved_0_TB33 = dprioin[`reserved_0_TB33_TXPMA_IDX_3 : `reserved_0_TB33_TXPMA_IDX_0]; assign dprioin_rtx_cgb_pdb = dprioin[`rtx_cgb_pdb_TXPMA_IDX_0]; assign dprioin_rpclksel = dprioin[`rpclksel_TXPMA_IDX_0]; assign dprioin_rdynamic_sw = dprioin[`rdynamic_sw_TXPMA_IDX_0]; assign dprioin_rs_lpbk = dprioin[`rs_lpbk_TXPMA_IDX_0]; assign dprioin_rcgb_delay_sel = dprioin[`rcgb_delay_sel_TXPMA_IDX_0]; assign dprioin_rpmadwidth_tx = dprioin[`rpmadwidth_tx_TXPMA_IDX_0]; assign dprioin_rpma_doublewidth_tx = dprioin[`rpma_doublewidth_tx_TXPMA_IDX_0]; assign dprioin_rcgb_m_sel = dprioin[`rcgb_m_sel_TXPMA_IDX_1 : `rcgb_m_sel_TXPMA_IDX_0]; assign dprioin_rcgb_cmu_sel = dprioin[`rcgb_cmu_sel_TXPMA_IDX_0]; assign dprioin_rcgb_x_en = dprioin[`rcgb_x_en_TXPMA_IDX_1 : `rcgb_x_en_TXPMA_IDX_0]; // PMA Per Channel TX Control Register 7 for Channel 0 assign dprioin_reserved_1_TB34 = dprioin[`reserved_1_TB34_TXPMA_IDX_2 : `reserved_1_TB34_TXPMA_IDX_0]; assign dprioin_rpcs_sd_sel = dprioin[`rpcs_sd_sel_TXPMA_IDX_0]; assign dprioin_rrx_refclk = dprioin[`rrx_refclk_TXPMA_IDX_0]; assign dprioin_rimpctrl = dprioin[`rimpctrl_TXPMA_IDX_0]; assign dprioin_reserved_0_TB34 = dprioin[`reserved_0_TB34_TXPMA_IDX_3 : `reserved_0_TB34_TXPMA_IDX_0]; assign dprioin_rrevlb_sw = dprioin[`rrevlb_sw_TXPMA_IDX_0]; assign dprioin_rvcobypass = dprioin[`rvcobypass_TXPMA_IDX_0]; assign dprioin_rrefclk_sel = dprioin[`rrefclk_sel_TXPMA_IDX_1 : `rrefclk_sel_TXPMA_IDX_0]; assign dprioin_riqclk_sel = dprioin[`riqclk_sel_TXPMA_IDX_1 : `riqclk_sel_TXPMA_IDX_0]; // PMA Per Channel TX Control Register 8 for Channel 0 assign dprioin_rpma_reserved_0_TB35 = dprioin[`rpma_reserved_0_TB35_TXPMA_IDX_15 : `rpma_reserved_0_TB35_TXPMA_IDX_0]; // Extra assign dprioin_ht_sel = dprioin[`ht_sel_TX_PMA_IDX]; assign dprioin_clkin_sel = dprioin[`CLKIN_SELECT_TXPMA_IDX_2 : `CLKIN_SELECT_TXPMA_IDX_0]; // --------------------------------------------------------------------------- // Set DPRIO output from initial CRAM // --------------------------------------------------------------------------- // PMA Per Channel TX Control Register 1 for Channel 0 assign dprioout[`rpowdnt_TXPMA_IDX_0] = init_rpowdnt; assign dprioout[`rvod_seld_TXPMA_IDX_2 : `rvod_seld_TXPMA_IDX_0] = init_rvod_seld; assign dprioout[`rvod_selc_TXPMA_IDX_2 : `rvod_selc_TXPMA_IDX_0] = init_rvod_selc; assign dprioout[`rvod_selb_TXPMA_IDX_2 : `rvod_selb_TXPMA_IDX_0] = init_rvod_selb; assign dprioout[`rvod_sela_TXPMA_IDX_2 : `rvod_sela_TXPMA_IDX_0] = init_rvod_sela; assign dprioout[`rvod_sel_non_pcie_TXPMA_IDX_2 : `rvod_sel_non_pcie_TXPMA_IDX_0] = init_rvod_sel_non_pcie; // PMA Per Channel TX Control Register 2 for Channel 0 assign dprioout[`reserved_0_TB29_TXPMA_IDX_0] = init_reserved_0_TB29; assign dprioout[`rpre_em_1t_b_TXPMA_IDX_4 : `rpre_em_1t_b_TXPMA_IDX_0] = init_rpre_em_1t_b; assign dprioout[`rpre_em_1t_a_TXPMA_IDX_4 : `rpre_em_1t_a_TXPMA_IDX_0] = init_rpre_em_1t_a; assign dprioout[`rpre_em_1t_no_pcie_TXPMA_IDX_4 : `rpre_em_1t_no_pcie_TXPMA_IDX_0] = init_rpre_em_1t_no_pcie; // PMA Per Channel TX Control Register 3 for Channel 0 assign dprioout[`rpre_em_pt_TXPMA_IDX_3 : `rpre_em_pt_TXPMA_IDX_0] = init_rpre_em_pt; assign dprioout[`rpre_em_2t_TXPMA_IDX_3 : `rpre_em_2t_TXPMA_IDX_0] = init_rpre_em_2t; assign dprioout[`rpre_em_1t_c_TXPMA_IDX_4 : `rpre_em_1t_c_TXPMA_IDX_0] = init_rpre_em_1t_c; assign dprioout[`reserved_0_TB30_TXPMA_IDX_2 : `reserved_0_TB30_TXPMA_IDX_0] = init_reserved_0_TB30; // PMA Per Channel TX Control Register 4 for Channel 0 assign dprioout[`rlowv_TXPMA_IDX_0] = init_rlowv; assign dprioout[`rrx_det_TXPMA_IDX_1 : `rrx_det_TXPMA_IDX_0] = init_rrx_det; assign dprioout[`rsig_inv_2t_TXPMA_IDX_0] = init_rsig_inv_2t; assign dprioout[`rsig_inv_ptap_TXPMA_IDX_0] = init_rsig_inv_ptap; assign dprioout[`rslew_TXPMA_IDX_1 : `rslew_TXPMA_IDX_0] = init_rslew; assign dprioout[`rtx_lst_TXPMA_IDX_3 : `rtx_lst_TXPMA_IDX_0] = init_rtx_lst; assign dprioout[`rtx_vtt_TXPMA_IDX_1 : `rtx_vtt_TXPMA_IDX_0] = init_rtx_vtt; assign dprioout[`rtx_term_sel_TXPMA_IDX_2 : `rtx_term_sel_TXPMA_IDX_0] = init_rtx_term_sel; // PMA Per Channel TX Control Register 5 for Channel 0 assign dprioout[`reserved_1_TB32_TXPMA_IDX_10 : `reserved_1_TB32_TXPMA_IDX_0] = init_reserved_1_TB32; assign dprioout[`rtx_ob_pdb_TXPMA_IDX_0] = init_rtx_ob_pdb; assign dprioout[`reserved_0_TB32_TXPMA_IDX_0] = init_reserved_0_TB32; assign dprioout[`r_dft_sel_TXPMA_IDX_2 : `r_dft_sel_TXPMA_IDX_0] = init_r_dft_sel; // PMA Per Channel TX Control Register 6 for Channel 0 assign dprioout[`reserved_0_TB33_TXPMA_IDX_3 : `reserved_0_TB33_TXPMA_IDX_0] = init_reserved_0_TB33; assign dprioout[`rtx_cgb_pdb_TXPMA_IDX_0] = init_rtx_cgb_pdb; assign dprioout[`rpclksel_TXPMA_IDX_0] = init_rpclksel; assign dprioout[`rdynamic_sw_TXPMA_IDX_0] = init_rdynamic_sw; assign dprioout[`rs_lpbk_TXPMA_IDX_0] = init_rs_lpbk; assign dprioout[`rcgb_delay_sel_TXPMA_IDX_0] = init_rcgb_delay_sel; assign dprioout[`rpmadwidth_tx_TXPMA_IDX_0] = init_rpmadwidth_tx; assign dprioout[`rpma_doublewidth_tx_TXPMA_IDX_0] = init_rpma_doublewidth_tx; assign dprioout[`rcgb_m_sel_TXPMA_IDX_1 : `rcgb_m_sel_TXPMA_IDX_0] = init_rcgb_m_sel; assign dprioout[`rcgb_cmu_sel_TXPMA_IDX_0] = init_rcgb_cmu_sel; assign dprioout[`rcgb_x_en_TXPMA_IDX_1 : `rcgb_x_en_TXPMA_IDX_0] = init_rcgb_x_en; // PMA Per Channel TX Control Register 7 for Channel 0 assign dprioout[`reserved_1_TB34_TXPMA_IDX_2 : `reserved_1_TB34_TXPMA_IDX_0] = init_reserved_1_TB34; assign dprioout[`rpcs_sd_sel_TXPMA_IDX_0] = init_rpcs_sd_sel; assign dprioout[`rrx_refclk_TXPMA_IDX_0] = init_rrx_refclk; assign dprioout[`rimpctrl_TXPMA_IDX_0] = init_rimpctrl; assign dprioout[`reserved_0_TB34_TXPMA_IDX_3 : `reserved_0_TB34_TXPMA_IDX_0] = init_reserved_0_TB34; assign dprioout[`rrevlb_sw_TXPMA_IDX_0] = init_rrevlb_sw; assign dprioout[`rvcobypass_TXPMA_IDX_0] = init_rvcobypass; assign dprioout[`rrefclk_sel_TXPMA_IDX_1 : `rrefclk_sel_TXPMA_IDX_0] = init_rrefclk_sel; assign dprioout[`riqclk_sel_TXPMA_IDX_1 : `riqclk_sel_TXPMA_IDX_0] = init_riqclk_sel; // PMA Per Channel TX Control Register 8 for Channel 0 assign dprioout[`rpma_reserved_0_TB35_TXPMA_IDX_15 : `rpma_reserved_0_TB35_TXPMA_IDX_0] = init_rpma_reserved_0_TB35; // Extra assign dprioout[`ht_sel_TX_PMA_IDX] = init_ht_sel; assign dprioout[`CLKIN_SELECT_TXPMA_IDX_2 : `CLKIN_SELECT_TXPMA_IDX_0] = init_clkin_sel; // --------------------------------------------------------------------------- // Set DPRIO CRAM // --------------------------------------------------------------------------- // PMA Per Channel TX Control Register 1 for Channel 0 assign cram_rpowdnt = (dpriodisable !== 1'b0) ? init_rpowdnt : dprioin_rpowdnt; assign cram_rvod_seld = (dpriodisable !== 1'b0) ? init_rvod_seld : dprioin_rvod_seld; assign cram_rvod_selc = (dpriodisable !== 1'b0) ? init_rvod_selc : dprioin_rvod_selc; assign cram_rvod_selb = (dpriodisable !== 1'b0) ? init_rvod_selb : dprioin_rvod_selb; assign cram_rvod_sela = (dpriodisable !== 1'b0) ? init_rvod_sela : dprioin_rvod_sela; assign cram_rvod_sel_non_pcie = (dpriodisable !== 1'b0) ? init_rvod_sel_non_pcie : dprioin_rvod_sel_non_pcie; // PMA Per Channel TX Control Register 2 for Channel 0 assign cram_reserved_0_TB29 = (dpriodisable !== 1'b0) ? init_reserved_0_TB29 : dprioin_reserved_0_TB29; assign cram_rpre_em_1t_b = (dpriodisable !== 1'b0) ? init_rpre_em_1t_b : dprioin_rpre_em_1t_b; assign cram_rpre_em_1t_a = (dpriodisable !== 1'b0) ? init_rpre_em_1t_a : dprioin_rpre_em_1t_a; assign cram_rpre_em_1t_no_pcie = (dpriodisable !== 1'b0) ? init_rpre_em_1t_no_pcie : dprioin_rpre_em_1t_no_pcie; // PMA Per Channel TX Control Register 3 for Channel 0 assign cram_rpre_em_pt = (dpriodisable !== 1'b0) ? init_rpre_em_pt : dprioin_rpre_em_pt; assign cram_rpre_em_2t = (dpriodisable !== 1'b0) ? init_rpre_em_2t : dprioin_rpre_em_2t; assign cram_rpre_em_1t_c = (dpriodisable !== 1'b0) ? init_rpre_em_1t_c : dprioin_rpre_em_1t_c; assign cram_reserved_0_TB30 = (dpriodisable !== 1'b0) ? init_reserved_0_TB30 : dprioin_reserved_0_TB30; // PMA Per Channel TX Control Register 4 for Channel 0 assign cram_rlowv = (dpriodisable !== 1'b0) ? init_rlowv : dprioin_rlowv; assign cram_rrx_det = (dpriodisable !== 1'b0) ? init_rrx_det : dprioin_rrx_det; assign cram_rsig_inv_2t = (dpriodisable !== 1'b0) ? init_rsig_inv_2t : dprioin_rsig_inv_2t; assign cram_rsig_inv_ptap = (dpriodisable !== 1'b0) ? init_rsig_inv_ptap : dprioin_rsig_inv_ptap; assign cram_rslew = (dpriodisable !== 1'b0) ? init_rslew : dprioin_rslew; assign cram_rtx_lst = (dpriodisable !== 1'b0) ? init_rtx_lst : dprioin_rtx_lst; assign cram_rtx_vtt = (dpriodisable !== 1'b0) ? init_rtx_vtt : dprioin_rtx_vtt; assign cram_rtx_term_sel = (dpriodisable !== 1'b0) ? init_rtx_term_sel : dprioin_rtx_term_sel; // PMA Per Channel TX Control Register 5 for Channel 0 assign cram_reserved_1_TB32 = (dpriodisable !== 1'b0) ? init_reserved_1_TB32 : dprioin_reserved_1_TB32; assign cram_rtx_ob_pdb = (dpriodisable !== 1'b0) ? init_rtx_ob_pdb : dprioin_rtx_ob_pdb; assign cram_reserved_0_TB32 = (dpriodisable !== 1'b0) ? init_reserved_0_TB32 : dprioin_reserved_0_TB32; assign cram_r_dft_sel = (dpriodisable !== 1'b0) ? init_r_dft_sel : dprioin_r_dft_sel; // PMA Per Channel TX Control Register 6 for Channel 0 assign cram_reserved_0_TB33 = (dpriodisable !== 1'b0) ? init_reserved_0_TB33 : dprioin_reserved_0_TB33; assign cram_rtx_cgb_pdb = (dpriodisable !== 1'b0) ? init_rtx_cgb_pdb : dprioin_rtx_cgb_pdb; assign cram_rpclksel = (dpriodisable !== 1'b0) ? init_rpclksel : dprioin_rpclksel; assign cram_rdynamic_sw = (dpriodisable !== 1'b0) ? init_rdynamic_sw : dprioin_rdynamic_sw; assign cram_rs_lpbk = (dpriodisable !== 1'b0) ? init_rs_lpbk : dprioin_rs_lpbk; assign cram_rcgb_delay_sel = 1'b0; // delay chains not modeled here assign cram_rpmadwidth_tx = (dpriodisable !== 1'b0) ? init_rpmadwidth_tx : dprioin_rpmadwidth_tx; assign cram_rpma_doublewidth_tx = (dpriodisable !== 1'b0) ? init_rpma_doublewidth_tx : dprioin_rpma_doublewidth_tx; assign cram_rcgb_m_sel = (dpriodisable !== 1'b0) ? init_rcgb_m_sel : dprioin_rcgb_m_sel; assign cram_rcgb_cmu_sel = (dpriodisable !== 1'b0) ? init_rcgb_cmu_sel : dprioin_rcgb_cmu_sel; assign cram_rcgb_x_en = (dpriodisable !== 1'b0) ? init_rcgb_x_en : dprioin_rcgb_x_en; // PMA Per Channel TX Control Register 7 for Channel 0 assign cram_reserved_1_TB34 = (dpriodisable !== 1'b0) ? init_reserved_1_TB34 : dprioin_reserved_1_TB34; assign cram_rpcs_sd_sel = (dpriodisable !== 1'b0) ? init_rpcs_sd_sel : dprioin_rpcs_sd_sel; assign cram_rrx_refclk = (dpriodisable !== 1'b0) ? init_rrx_refclk : dprioin_rrx_refclk; assign cram_rimpctrl = (dpriodisable !== 1'b0) ? init_rimpctrl : dprioin_rimpctrl; assign cram_reserved_0_TB34 = (dpriodisable !== 1'b0) ? init_reserved_0_TB34 : dprioin_reserved_0_TB34; assign cram_rrevlb_sw = (dpriodisable !== 1'b0) ? init_rrevlb_sw : dprioin_rrevlb_sw; assign cram_rvcobypass = (dpriodisable !== 1'b0) ? init_rvcobypass : dprioin_rvcobypass; assign cram_rrefclk_sel = (dpriodisable !== 1'b0) ? init_rrefclk_sel : dprioin_rrefclk_sel; assign cram_riqclk_sel = (dpriodisable !== 1'b0) ? init_riqclk_sel : dprioin_riqclk_sel; // PMA Per Channel TX Control Register 8 for Channel 0 assign cram_rpma_reserved_0_TB35 = (dpriodisable !== 1'b0) ? init_rpma_reserved_0_TB35 : dprioin_rpma_reserved_0_TB35; // Extra assign cram_ht_sel = init_ht_sel; // SPR 288513 assign cram_clkin_sel = (dpriodisable !== 1'b0) ? init_clkin_sel : dprioin_clkin_sel; // Function function [8*`STRATIXIV_HSSI_TX_PMA_ALPHA_TOLOWER_WORD_LENGTH:1] alpha_tolower; input [8*`STRATIXIV_HSSI_TX_PMA_ALPHA_TOLOWER_WORD_LENGTH:1] input_string; reg [8*`STRATIXIV_HSSI_TX_PMA_ALPHA_TOLOWER_WORD_LENGTH:1] return_string; reg [8*`STRATIXIV_HSSI_TX_PMA_ALPHA_TOLOWER_WORD_LENGTH:1] reg_string; reg [8:1] tmp; reg [8:1] conv_char; integer byte_count; begin reg_string = input_string; for (byte_count = `STRATIXIV_HSSI_TX_PMA_ALPHA_TOLOWER_WORD_LENGTH; byte_count >= 1; byte_count = byte_count - 1) begin tmp = reg_string[8*`STRATIXIV_HSSI_TX_PMA_ALPHA_TOLOWER_WORD_LENGTH:(8*(`STRATIXIV_HSSI_TX_PMA_ALPHA_TOLOWER_WORD_LENGTH-1)+1)]; reg_string = reg_string << 8; if ((tmp >= 65) && (tmp <= 90)) // ASCII number of 'A' is 65, 'Z' is 90 begin conv_char = tmp + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set return_string = {return_string, conv_char}; end else return_string = {return_string, tmp}; end alpha_tolower = return_string; end endfunction function [31:0] int2bin; input input_value; integer input_value; integer i; begin for (i = 0; i <= 31; i = i + 1) begin if (input_value % 2 == 0) int2bin[i] = 1'b0; else int2bin[i] = 1'b1; input_value = input_value / 2; end end endfunction // end function initial begin // TX PMA control register 1 init_rpowdnt = 1'b0; init_rvod_sel_non_pcie = (vod_selection == 0) ? 3'b000 : (vod_selection == 1) ? 3'b001 : (vod_selection == 2) ? 3'b010 : (vod_selection == 3) ? 3'b110 : (vod_selection == 4) ? 3'b011 : (vod_selection == 5) ? 3'b111 : (vod_selection == 6) ? 3'b100 : (vod_selection == 7) ? 3'b101 : 3'b000; init_rvod_seld = vod_selection_d; init_rvod_selc = vod_selection_c; init_rvod_selb = vod_selection_b; init_rvod_sela = vod_selection_a; // TX PMA control register 2 init_rpre_em_1t_b = preemp_tap_1_b; init_rpre_em_1t_a = preemp_tap_1_a; init_rpre_em_1t_no_pcie = preemp_tap_1; // TX PMA control register 3 init_rpre_em_pt = preemp_pretap; init_rpre_em_2t = preemp_tap_2; init_rpre_em_1t_c = preemp_tap_1_c; // TX PMA control register 4 init_rlowv = 1'b0; init_rrx_det = rx_detect; init_rsig_inv_2t = (preemp_tap_2_inv == "true") ? 1'b1 : 1'b0; init_rsig_inv_ptap = (preemp_pretap_inv == "true") ? 1'b1 : 1'b0; init_rslew = (slew_rate == "low" ? 2'b01 : slew_rate == "medium" ? 2'b10 : slew_rate == "high" ? 2'b11 : 2'b00); init_rtx_lst = low_speed_test_select; init_rtx_vtt = (alpha_tolower(common_mode) == "tristate") ? 2'b00 : (alpha_tolower(common_mode) == "0.6v") ? 2'b01 : (alpha_tolower(common_mode) == "0.7v") ? 2'b10 : 2'b11; init_rtx_term_sel = (alpha_tolower(termination) == "off" ? 3'b000 : (alpha_tolower(termination) == "oct 85 ohms" || alpha_tolower(termination) == "85_ohms") ? 3'b111 : (alpha_tolower(termination) == "oct 100 ohms" || alpha_tolower(termination) == "100_ohms") ? 3'b110 : (alpha_tolower(termination) == "oct 120 ohms" || alpha_tolower(termination) == "120_ohms") ? 3'b101 : 3'b100); // TX PMA Control Register 6 init_rpma_doublewidth_tx = (serialization_factor == 16 || serialization_factor == 20 ? 1'b1 : 1'b0); //init_rpma_doublewidth_tx = rser_div2_init; init_rpmadwidth_tx = (serialization_factor == 10 || serialization_factor == 20 ? 1'b1 : 1'b0); //init_rpmadwidth_tx = rser_div5_init; init_rcgb_delay_sel = (clkmux_delay == "true") ? 1'b1 : 1'b0; init_rcgb_x_en = clkin_select; init_rpclksel = (use_pclk == "true") ? 1'b1 : 1'b0; init_rs_lpbk = (enable_reverse_serial_loopback == "true") ? 1'b1 : 1'b0; // Extra init_ht_sel = (clkin_select > 3) ? 1'b1 : 1'b0; // logic select init_clkin_sel = clkin_select; end // --------------------------------------------------------------------------- // New DPRIO End // --------------------------------------------------------------------------- // --------------------------------------------------------------------------- // Model / Submodule Instantiations - // --------------------------------------------------------------------------- // common supply wires wire vccelxqyx; wire vsse; assign vccelxqyx = 1'b1; assign vsse = 1'b0; // for the tx_clkmux instance // input wires wire xtxclkmux_ht_sel; // output wires wire xtxclkmux_cpulse; wire xtxclkmux_hfclkn; wire xtxclkmux_hfclkp; wire xtxclkmux_lfclkn; wire xtxclkmux_lfclkp; assign xtxclkmux_ht_sel = serialization_factor <= 20 ? cram_ht_sel : 1'b0; // the actual instance stratixiv_hssi_pma_c_tx_clkmux_cmu xtxclkmux ( .cpulse_ht(refclk4inpulse), .cpulse_x1(refclk0inpulse), .cpulse_x4(refclk1inpulse), .cpulse_xn_b(refclk3inpulse), .cpulse_xn_t(refclk2inpulse), .delay_sel(cram_rcgb_delay_sel), .hfclkn_ht(fastrefclk4in[1]), .hfclkn_x1(fastrefclk0in[1]), .hfclkn_x4(fastrefclk1in[1]), .hfclkn_xn_b(fastrefclk3in[1]), .hfclkn_xn_t(fastrefclk2in[1]), .hfclkp_ht(fastrefclk4in[0]), .hfclkp_x1(fastrefclk0in[0]), .hfclkp_x4(fastrefclk1in[0]), .hfclkp_xn_b(fastrefclk3in[0]), .hfclkp_xn_t(fastrefclk2in[0]), .ht_sel(xtxclkmux_ht_sel), .lfclkn_ht(refclk4in[1]), .lfclkn_x1(refclk0in[1]), .lfclkn_x4(refclk1in[1]), .lfclkn_xn_b(refclk3in[1]), .lfclkn_xn_t(refclk2in[1]), .lfclkp_ht(refclk4in[0]), .lfclkp_x1(refclk0in[0]), .lfclkp_x4(refclk1in[0]), .lfclkp_xn_b(refclk3in[0]), .lfclkp_xn_t(refclk2in[0]), .pdb(powerdn_in), .sel(cram_clkin_sel[1:0]), .vccelxqyx(vccelxqyx), .vssexqyx(vsse), .cpulse(xtxclkmux_cpulse), .hfclk_n(xtxclkmux_hfclkn), .hfclk_p(xtxclkmux_hfclkp), .lfclk_n(xtxclkmux_lfclkn), .lfclk_p(xtxclkmux_lfclkp) ); // for the serializer instance // input wires wire xser_cpulse; wire [19:0] xser_data; wire [19:0] xser_data_dprio; wire xser_hfclkn; wire xser_hfclkp; wire xser_lfclkn; wire xser_lfclkp; wire xser_pclk; wire xser_rs_lpbk; wire vccetx; // output wires wire xser_clk_divtx; wire xser_lbvop; wire xser_lbvon; wire xser_pre_en_out; wire xser_von; wire xser_von_op1; wire xser_von_op2; wire xser_von_pre; wire xser_vop; wire xser_vop_op1; wire xser_vop_op2; wire xser_vop_pre; reg use_pma_direct_param; initial begin use_pma_direct_param = (use_pma_direct == "true" ) ? 1'b1 : 1'b0; end // get the inputs assign xser_data = (use_pma_direct_param == 1'b1 && serialization_factor == 16) ? ({{2{1'b0}}, datain[15:8], {2{1'b0}}, datain[7:0]}) : datain[19:0]; assign xser_data_dprio = (use_pma_direct_param == 1'b1 && (dprio_config_mode & DPRIO_CHANNEL_INTERFACE_BIT) != 0) ? datainfull : xser_data; assign xser_pclk = (cram_clkin_sel == 0) ? pclk[0] : (cram_clkin_sel == 1) ? pclk[1] : (cram_clkin_sel == 2) ? pclk[2] : (cram_clkin_sel == 3) ? pclk[3] : (cram_clkin_sel == 4) ? pclk[4] : pclk[0]; // shawn: clkin_select assign xser_rs_lpbk = 1'b1; // always enabled - allow serial_loop_back assign {xser_cpulse, xser_hfclkn, xser_hfclkp, xser_lfclkn, xser_lfclkp} = serialization_factor > 20 ? 5'b00000 : {xtxclkmux_cpulse, xtxclkmux_hfclkn, xtxclkmux_hfclkp, xtxclkmux_lfclkn, xtxclkmux_lfclkp}; // the actual instance stratixiv_hssi_pma_c_ser xser ( .cpulse(xser_cpulse), .data(xser_data_dprio), .div2(cram_rpma_doublewidth_tx), .div5(cram_rpmadwidth_tx), .hfclkn(xser_hfclkn), .hfclkp(xser_hfclkp), .lfclkn(xser_lfclkn), .lfclkp(xser_lfclkp), .pclk_in(xser_pclk), .pclksel(cram_rpclksel), .pdb(powerdn_in), .pre_em(cram_rpre_em_1t_no_pcie), .pre_em_2t(cram_rpre_em_2t), .pre_em_pretap(cram_rpre_em_pt), .rst_n(txpmareset_in), .s_lpbk(xser_rs_lpbk), .vccelxqyx(vccelxqyx), .vccetxqyx(vsse), .vssexqyx(vsse), .clk_divtx(xser_clk_divtx), .lbvon(xser_lbvon), .lbvop(xser_lbvop), .pre_en_out(xser_pre_en_out), .von(xser_von), .von_op1(xser_von_op1), .von_op2(xser_von_op2), .von_pre(xser_von_pre), .vop(xser_vop), .vop_op1(xser_vop_op1), .vop_op2(xser_vop_op2), .vop_pre(xser_vop_pre) ); // 10g output wires wire xser_10g_clk_divtx; wire xser_10g_lbvon; wire xser_10g_von; wire xser_10g_von_op1; wire xser_10g_lbvop; wire xser_10g_vop; wire xser_10g_vop_op1; generate if (serialization_factor > 20) begin stratixiv_hssi_pma_c_ser_10g xser_10g ( .clk_skew(), .cpulse(xtxclkmux_cpulse), .cpulseb(~xtxclkmux_cpulse), .data_in(datain[63:0]), .hfclkn(xtxclkmux_hfclkn), .hfclkp(xtxclkmux_hfclkp), .lfclkn(xtxclkmux_lfclkn), .lfclkp(xtxclkmux_lfclkp), .pdb(powerdn_in), .pre_em(cram_rpre_em_1t_no_pcie), .rst_n(txpmareset_in), .s_lpbk(1'b1), // always enabled, for now .vccelxqyx(vccelxqyx), .vccetxqyx(vsse), .vssexqyx(vsse), .clk_divtx(xser_10g_clk_divtx), .lbvon(xser_10g_lbvon), .lbvop(xser_10g_lbvop), .von(xser_10g_von), .von_op1(xser_10g_von_op1), .vop(xser_10g_vop), .vop_op1(xser_10g_vop_op1) ); end endgenerate // serializer outputs assign clockout = serialization_factor > 20 ? xser_10g_clk_divtx : xser_clk_divtx; assign seriallpbkout = serialization_factor > 20 ? xser_10g_lbvop : xser_lbvop; // for the TX driver instance // input wires wire xtx_bsmode; wire xtx_bsoeb; wire xtx_bstxn_in; wire xtx_bstxp_in; wire xtx_rlpbkn_em; wire xtx_rlpbkp_em; wire [2:0] xtx_r_dft_sel; wire xtx_r_dis_idlegate; wire xtx_r_highv; wire xtx_r_lowv; wire [3:0] xtx_rpre_em_2t; wire [3:0] xtx_rpre_em_pt; wire xtx_rx_det_clk; wire xtx_rx_n; wire xtx_rx_p; wire [3:0] xtx_tx50; wire xtx_vin; wire xtx_vin_op1; wire xtx_vip; wire xtx_vip_op1; // inout wires wire xtx_atb0; wire xtx_atb1; wire xtx_ib50uc_vcm; wire xtx_ib50ut_vcm; wire xtx_ib100uc; wire xtx_ib50uc_rcvdt; wire xtx_von; wire xtx_vop; // output wires wire xtx_com_pass; wire xtx_detect_on; wire xtx_fixed_clk; wire xtx_probe_pass; wire xtx_rx_detect_valid; wire xtx_sel_150r; wire [6:1] xtx_tx_dftout; wire [31:0] vod_selection_bin; //use for int2bin function //temporarily generate rxdetectclk - fixed clock of 125 Mhz reg rx_det_clk_reg; initial begin rx_det_clk_reg = 1'b0; forever begin #4000 rx_det_clk_reg = ~rx_det_clk_reg; end end assign xtx_rx_det_clk = rx_det_clk_reg; // end // get the inputs assign xtx_rpre_em_2t = serialization_factor <= 20 ? cram_rpre_em_2t : 4'b0000; assign xtx_rpre_em_pt = serialization_factor <= 20 ? cram_rpre_em_pt : 4'b0000; assign vod_selection_bin = int2bin(vod_selection); assign xtx_vin = serialization_factor <= 20 ? xser_von : xser_10g_von; assign xtx_vin_op1 = serialization_factor <= 20 ? xser_von_op1 : xser_10g_von_op1; assign xtx_vip = serialization_factor <= 20 ? xser_vop : xser_10g_vop; assign xtx_vip_op1 = serialization_factor <= 20 ? xser_vop_op1 : xser_10g_vop_op1; // the actual instance stratixiv_hssi_pma_c_tx xtx ( .bsmode(xtx_bsmode), .bsoeb(xtx_bsoeb), .bstxn_in(xtx_bstxn_in), .bstxp_in(xtx_bstxp_in), .cgb_vccelxqyx(1'b1), .cgb_vssexqyx(vsse), .lst(cram_rtx_lst), .pdb(powerdn_in), .r_dft_sel(xtx_r_dft_sel), .r_dis_idlegate(xtx_r_dis_idlegate), .r_highv(xtx_r_highv), .r_lowv(xtx_r_lowv), .r_rx_det(cram_rrx_det), .r_slew(cram_rslew), .rlpbkn(~revserialfdbk), .rlpbkn_em(xtx_rlpbkn_em), .rlpbkp(revserialfdbk), .rlpbkp_em(xtx_rlpbkp_em), .rpre_em_1t(cram_rpre_em_1t_no_pcie), .rpre_em_2t(xtx_rpre_em_2t), .rpre_em_pt(xtx_rpre_em_pt), .rsig_inv_2t(cram_rsig_inv_2t), .rsig_inv_ptap(cram_rsig_inv_ptap), .rterm_sel(cram_rtx_term_sel), .rtx_rlpbk(cram_rs_lpbk), .rtx_vtt(cram_rtx_vtt), .rvod_sel(vod_selection_bin[2:0]), .rx_det_clk(xtx_rx_det_clk), .rx_det_pdb(detectrxpowerdown_in), .rx_n(xtx_rx_n), .rx_p(xtx_rx_p), .tx50(xtx_tx50), .tx_det_rx(rxdetecten), .tx_elec_idl(forceelecidle_in), .vccehtxqyx(vsse), .vccehxqyx(vsse), .vccesdh_la(vsse), .vccesdp_la(vsse), .vccetxqyx(vsse), .vin(xtx_vin), .vin_po1(xtx_vin_op1), .vin_po2(xser_von_op2), .vin_pre(xser_von_pre), .vip(xtx_vip), .vip_po1(xtx_vip_op1), .vip_po2(xser_vop_op2), .vip_pre(xser_vop_pre), .vssexqyx(vsse), .atb0(xtx_atb0), .atb1(xtx_atb1), .ib50uc_rcvdt(xtx_ib50uc_rcvdt), .ib50uc_vcm(xtx_ib50uc_vcm), .ib50ut_vcm(xtx_ib50ut_vcm), .ib100uc(xtx_ib100uc), .von(xtx_von), .vop(xtx_vop), .com_pass(xtx_com_pass), .detect_on(xtx_detect_on), .fixed_clk_out(xtx_fixed_clk), .probe_pass(xtx_probe_pass), .rx_detect_valid(xtx_rx_detect_valid), .rx_found(xtx_rx_found), .sel_150r(xtx_sel_150r), .tx_dftout(xtx_tx_dftout) ); // driver outputs assign dataout = xtx_vop; assign dftout = xtx_tx_dftout; assign rxdetectvalidout = xtx_rx_detect_valid; assign rxfoundout = xtx_rx_found; // --------------------------------------------------------------------------- // Model Implementation End - // --------------------------------------------------------------------------- endmodule // *********************************************************** // This WYSIWYG atom header was automatically generated by the // Atmgen build tool. To change it, alter data stored in the // corresponding WYS file(s) in the tools/atmgen subdirectory. // *********************************************************** // *** Section 1 -- Header *** // ----------------------------------------------------------- // // Module Name : stratixiv_hssi_rx_pma // // Description : DEV_FAMILY_STRATIXIV stratixiv_hssi_rx_pma Verilog simulation model // // ----------------------------------------------------------- `timescale 1 ps/1 ps // *** End of Section 1 *** // *** Section 3 -- Module declaration *** module stratixiv_hssi_rx_pma( adaptcapture, adcepowerdn, adcereset, adcestandby, datain, deserclock, dpriodisable, dprioin, extra10gin, freqlock, ignorephslck, locktodata, locktoref, offsetcancellationen, plllocked, powerdn, ppmdetectdividedclk, ppmdetectrefclk, recoverdatain, rxpmareset, seriallpbken, seriallpbkin, testbussel, adaptdone, analogtestbus, clockout, dataout, dataoutfull, dprioout, locktorefout, ppmdetectclkrel, recoverdataout, reverselpbkout, revserialfdbkout, signaldetect ); // *** End of Section 3 *** // *** Section 4 -- Port size declarations *** // Note: Variable port sizes dictated by parameters are not currently defined in // the WYS file data. Busses are marked with the VARIABLE notation as a reminder. `define ADAPTCAPTURE_PORTSIZE_CONST_stratixiv_hssi_rx_pma 1 `define ADAPTDONE_PORTSIZE_CONST_stratixiv_hssi_rx_pma 1 `define ADCEPOWERDN_PORTSIZE_CONST_stratixiv_hssi_rx_pma 1 `define ADCERESET_PORTSIZE_CONST_stratixiv_hssi_rx_pma 1 `define ADCESTANDBY_PORTSIZE_CONST_stratixiv_hssi_rx_pma 1 `define ANALOGTESTBUS_PORTSIZE_CONST_stratixiv_hssi_rx_pma 8 // * VARIABLE `define CLOCKOUT_PORTSIZE_CONST_stratixiv_hssi_rx_pma 1 `define DATAIN_PORTSIZE_CONST_stratixiv_hssi_rx_pma 1 `define DATAOUT_PORTSIZE_CONST_stratixiv_hssi_rx_pma 1 `define DATAOUTFULL_PORTSIZE_CONST_stratixiv_hssi_rx_pma 20 // * VARIABLE `define DESERCLOCK_PORTSIZE_CONST_stratixiv_hssi_rx_pma 4 // * VARIABLE `define DPRIODISABLE_PORTSIZE_CONST_stratixiv_hssi_rx_pma 1 `define DPRIOIN_PORTSIZE_CONST_stratixiv_hssi_rx_pma 300 // * VARIABLE `define DPRIOOUT_PORTSIZE_CONST_stratixiv_hssi_rx_pma 300 // * VARIABLE `define EXTRA10GIN_PORTSIZE_CONST_stratixiv_hssi_rx_pma 38 // * VARIABLE `define FREQLOCK_PORTSIZE_CONST_stratixiv_hssi_rx_pma 1 `define IGNOREPHSLCK_PORTSIZE_CONST_stratixiv_hssi_rx_pma 1 `define LOCKTODATA_PORTSIZE_CONST_stratixiv_hssi_rx_pma 1 `define LOCKTOREF_PORTSIZE_CONST_stratixiv_hssi_rx_pma 1 `define LOCKTOREFOUT_PORTSIZE_CONST_stratixiv_hssi_rx_pma 1 `define OFFSETCANCELLATIONEN_PORTSIZE_CONST_stratixiv_hssi_rx_pma 1 `define PLLLOCKED_PORTSIZE_CONST_stratixiv_hssi_rx_pma 1 `define POWERDN_PORTSIZE_CONST_stratixiv_hssi_rx_pma 1 `define PPMDETECTCLKREL_PORTSIZE_CONST_stratixiv_hssi_rx_pma 1 `define PPMDETECTDIVIDEDCLK_PORTSIZE_CONST_stratixiv_hssi_rx_pma 1 `define PPMDETECTREFCLK_PORTSIZE_CONST_stratixiv_hssi_rx_pma 1 `define RECOVERDATAIN_PORTSIZE_CONST_stratixiv_hssi_rx_pma 2 // * VARIABLE `define RECOVERDATAOUT_PORTSIZE_CONST_stratixiv_hssi_rx_pma 64 // * VARIABLE `define REVERSELPBKOUT_PORTSIZE_CONST_stratixiv_hssi_rx_pma 1 `define REVSERIALFDBKOUT_PORTSIZE_CONST_stratixiv_hssi_rx_pma 1 `define RXPMARESET_PORTSIZE_CONST_stratixiv_hssi_rx_pma 1 `define SERIALLPBKEN_PORTSIZE_CONST_stratixiv_hssi_rx_pma 1 `define SERIALLPBKIN_PORTSIZE_CONST_stratixiv_hssi_rx_pma 1 `define SIGNALDETECT_PORTSIZE_CONST_stratixiv_hssi_rx_pma 1 `define TESTBUSSEL_PORTSIZE_CONST_stratixiv_hssi_rx_pma 4 // * VARIABLE // *** End of Section 4 *** // *** Section 5 -- Port declarations *** input adaptcapture; input adcepowerdn; input adcereset; input adcestandby; input datain; input [`DESERCLOCK_PORTSIZE_CONST_stratixiv_hssi_rx_pma - 1 : 0] deserclock; input dpriodisable; input [`DPRIOIN_PORTSIZE_CONST_stratixiv_hssi_rx_pma - 1 : 0] dprioin; input [`EXTRA10GIN_PORTSIZE_CONST_stratixiv_hssi_rx_pma - 1 : 0] extra10gin; input freqlock; input ignorephslck; input locktodata; input locktoref; input offsetcancellationen; input plllocked; input powerdn; input ppmdetectdividedclk; input ppmdetectrefclk; input [`RECOVERDATAIN_PORTSIZE_CONST_stratixiv_hssi_rx_pma - 1 : 0] recoverdatain; input rxpmareset; input seriallpbken; input seriallpbkin; input [`TESTBUSSEL_PORTSIZE_CONST_stratixiv_hssi_rx_pma - 1 : 0] testbussel; output adaptdone; output [`ANALOGTESTBUS_PORTSIZE_CONST_stratixiv_hssi_rx_pma - 1 : 0] analogtestbus; output clockout; output dataout; output [`DATAOUTFULL_PORTSIZE_CONST_stratixiv_hssi_rx_pma - 1 : 0] dataoutfull; output [`DPRIOOUT_PORTSIZE_CONST_stratixiv_hssi_rx_pma - 1 : 0] dprioout; output locktorefout; output ppmdetectclkrel; output [`RECOVERDATAOUT_PORTSIZE_CONST_stratixiv_hssi_rx_pma - 1 : 0] recoverdataout; output reverselpbkout; output revserialfdbkout; output signaldetect; // *** End of Section 5 *** // *** Section 6 -- Parameter declarations and default values *** parameter lpm_type = "stratixiv_hssi_rx_pma"; parameter adaptive_equalization_mode = "none"; parameter allow_serial_loopback = "false"; parameter allow_vco_bypass = 0 ; parameter analog_power = "1.4V"; parameter channel_number = 0 ; parameter channel_type = "auto"; parameter common_mode = "0.82V"; parameter deserialization_factor = 8 ; parameter dfe_piclk_bandwidth = 0 ; parameter dfe_piclk_phase = 0 ; parameter dfe_piclk_sel = 0 ; parameter dprio_config_mode = 06'b000000 ; parameter enable_ltd = "false"; parameter enable_ltr = "false"; parameter eq_adapt_seq_control = 0 ; parameter eq_dc_gain = 0 ; parameter eq_max_gradient_control = 0 ; parameter eqa_ctrl = 0 ; parameter eqb_ctrl = 0 ; parameter eqc_ctrl = 0 ; parameter eqd_ctrl = 0 ; parameter eqv_ctrl = 0 ; parameter eyemon_bandwidth = 0 ; parameter force_signal_detect = "true"; parameter ignore_lock_detect = "false"; parameter logical_channel_address = 0 ; parameter low_speed_test_select = 0 ; parameter offset_cancellation = 0 ; parameter ppm_gen1_2_xcnt_en = 0 ; parameter ppm_post_eidle = 0 ; parameter ppmselect = 0 ; parameter protocol_hint = "basic"; parameter send_direct_reverse_serial_loopback = "None"; parameter signal_detect_hysteresis = 4 ; parameter signal_detect_hysteresis_valid_threshold = 2 ; parameter signal_detect_loss_threshold = 3 ; parameter termination = "OCT 100 Ohms"; parameter use_deser_double_data_width = "false"; parameter use_external_termination = "false"; parameter use_pma_direct = "false"; // *** End of Section 6 *** // *** Section 7 -- Port declarations with defaults, if any *** // This section will always be empty for WYSIWYG atoms // tri1 devclrn; //sample // *** End of Section 7 *** `define STRATIXIV_HSSI_RX_PMA_ALPHA_TOLOWER_WORD_LENGTH 25 // --------------------------------------------------------------------------- // New DPRIO Begin // --------------------------------------------------------------------------- // Table36: PMA Per Channel RX Control Register 1 for Channel 0 `define rrx_term_sel_RXPMA_IDX_0 0 `define rrx_term_sel_RXPMA_IDX_1 1 `define rrx_term_sel_RXPMA_IDX_2 2 `define rrx_vtt_RXPMA_IDX_0 3 `define rrx_vtt_RXPMA_IDX_1 4 `define rrx_vtt_RXPMA_IDX_2 5 `define rrx_s_rdlpbk_RXPMA_IDX_0 6 `define rrx_bit_dc_RXPMA_IDX_0 7 `define rrx_bit_dc_RXPMA_IDX_1 8 `define rrx_bit_dc_RXPMA_IDX_2 9 `define rrx_bit_dc_RXPMA_IDX_3 10 `define rrx_lst_RXPMA_IDX_0 11 `define rrx_lst_RXPMA_IDX_1 12 `define rrx_lst_RXPMA_IDX_2 13 `define rrx_lst_RXPMA_IDX_3 14 `define rrx_lst_RXPMA_IDX_4 15 // Table37: PMA Per Channel RX Control Register 2 for Channel 0 `define rrxurstpma_RXPMA_IDX_0 16 `define rrx_test_RXPMA_IDX_0 17 `define rrx_sd_force_RXPMA_IDX_0 18 `define rrx_oc_RXPMA_IDX_0 19 `define rrx_oc_RXPMA_IDX_1 20 `define rrx_oc_RXPMA_IDX_2 21 `define rrx_oc_RXPMA_IDX_3 22 `define rrx_oc_RXPMA_IDX_4 23 `define rrx_oc_RXPMA_IDX_5 24 `define rrx_oc_RXPMA_IDX_6 25 `define rrx_oc_RXPMA_IDX_7 26 `define rrx_oc_en_RXPMA_IDX_0 27 `define rrx_sdlv_RXPMA_IDX_0 28 `define rrx_sdlv_RXPMA_IDX_1 29 `define rrx_sdlv_RXPMA_IDX_2 30 `define rrx_sdlv_RXPMA_IDX_3 31 // Table38: PMA Per Channel RX Control Register 3 for Channel 0 `define reserved_0_TB38_RXPMA_IDX_0 32 `define reserved_0_TB38_RXPMA_IDX_1 33 `define reserved_0_TB38_RXPMA_IDX_2 34 `define rpowdnr_RXPMA_IDX_0 35 `define rrx_ib_pdb_RXPMA_IDX_0 36 `define rurx_pdb_RXPMA_IDX_0 37 `define rrx_oc_calpd_RXPMA_IDX_0 38 `define rrx_sd_off_RXPMA_IDX_0 39 `define rrx_sd_off_RXPMA_IDX_1 40 `define rrx_sd_off_RXPMA_IDX_2 41 `define rrx_sd_off_RXPMA_IDX_3 42 `define rrx_sd_off_RXPMA_IDX_4 43 `define rrx_sd_on_RXPMA_IDX_0 44 `define rrx_sd_on_RXPMA_IDX_1 45 `define rrx_sd_on_RXPMA_IDX_2 46 `define rrx_sd_on_RXPMA_IDX_3 47 // Table43: PMA Per Channel RX Control Register 8 for Channel 0 `define reye_monitor_RXPMA_IDX_0 112 `define reye_monitor_RXPMA_IDX_1 113 `define reye_monitor_RXPMA_IDX_2 114 `define reye_monitor_RXPMA_IDX_3 115 `define reye_monitor_RXPMA_IDX_4 116 `define reye_monitor_RXPMA_IDX_5 117 `define reye_monitor_RXPMA_IDX_6 118 `define reye_monitor_RXPMA_IDX_7 119 `define reserved_0_TB43_RXPMA_IDX_0 120 `define reserved_0_TB43_RXPMA_IDX_1 121 `define reserved_0_TB43_RXPMA_IDX_2 122 `define reserved_0_TB43_RXPMA_IDX_3 123 `define reserved_0_TB43_RXPMA_IDX_4 124 `define reserved_0_TB43_RXPMA_IDX_5 125 `define reserved_0_TB43_RXPMA_IDX_6 126 `define reserved_0_TB43_RXPMA_IDX_7 127 // Table44: PMA Per Channel RX Control Register 9 for Channel 0 `define rpma_reserved_0_TB44_RXPMA_IDX_0 128 `define rpma_reserved_0_TB44_RXPMA_IDX_1 129 `define rpma_reserved_0_TB44_RXPMA_IDX_2 130 `define rpma_reserved_0_TB44_RXPMA_IDX_3 131 `define rpma_reserved_0_TB44_RXPMA_IDX_4 132 `define rpma_reserved_0_TB44_RXPMA_IDX_5 133 `define rpma_reserved_0_TB44_RXPMA_IDX_6 134 `define rpma_reserved_0_TB44_RXPMA_IDX_7 135 `define rpma_reserved_0_TB44_RXPMA_IDX_8 136 `define rpma_reserved_0_TB44_RXPMA_IDX_9 137 `define rpma_reserved_0_TB44_RXPMA_IDX_10 138 `define rpma_reserved_0_TB44_RXPMA_IDX_11 139 `define rpma_reserved_0_TB44_RXPMA_IDX_12 140 `define rpma_reserved_0_TB44_RXPMA_IDX_13 141 `define rpma_reserved_0_TB44_RXPMA_IDX_14 142 `define rpma_reserved_0_TB44_RXPMA_IDX_15 143 // Table45: PMA Per Channel RX Control Register 10 for Channel 0 `define rppm_cnt_reset_RXPMA_IDX_0 144 `define rforce1_freqdet_RXPMA_IDX_0 145 `define rforce0_freqdet_RXPMA_IDX_0 146 `define rppmsel_RXPMA_IDX_0 147 `define rppmsel_RXPMA_IDX_1 148 `define rppmsel_RXPMA_IDX_2 149 `define rppmsel_RXPMA_IDX_3 150 `define rppmsel_RXPMA_IDX_4 151 `define rppmsel_RXPMA_IDX_5 152 `define rfastsd_RXPMA_IDX_0 153 `define rfastsd_RXPMA_IDX_1 154 `define rfastsd_RXPMA_IDX_2 155 `define rfastsd_RXPMA_IDX_3 156 `define rtest_fastsd_RXPMA_IDX_0 157 `define rpmadwidth_rx_RXPMA_IDX_0 158 `define rpma_doublewidth_rx_RXPMA_IDX_0 159 // Table46: PMA Per Channel RX Control Register 11 for Channel 0 `define reserved_0_TB46_RXPMA_IDX_0 160 `define reserved_0_TB46_RXPMA_IDX_1 161 `define reserved_0_TB46_RXPMA_IDX_2 162 `define reserved_0_TB46_RXPMA_IDX_3 163 `define reserved_0_TB46_RXPMA_IDX_4 164 `define reserved_0_TB46_RXPMA_IDX_5 165 `define reserved_0_TB46_RXPMA_IDX_6 166 `define reserved_0_TB46_RXPMA_IDX_7 167 `define rppm_gen1_2xcnt_en_RXPMA_IDX_0 168 `define rppm_post_eidle_del_RXPMA_IDX_0 169 `define r_dfe_2t_RXPMA_IDX_0 170 `define r_dfe_2t_RXPMA_IDX_1 171 `define r_dfe_2t_RXPMA_IDX_2 172 `define r_dfe_1t_RXPMA_IDX_0 173 `define r_dfe_1t_RXPMA_IDX_1 174 `define r_dfe_1t_RXPMA_IDX_2 175 // Table47: PMA Per Channel RX Control Register 12 for Channel 0 `define reqv_set_RXPMA_IDX_0 176 `define reqv_set_RXPMA_IDX_1 177 `define reqv_set_RXPMA_IDX_2 178 `define reqd_set_RXPMA_IDX_0 179 `define reqd_set_RXPMA_IDX_1 180 `define reqd_set_RXPMA_IDX_2 181 `define reqc_set_RXPMA_IDX_0 182 `define reqc_set_RXPMA_IDX_1 183 `define reqc_set_RXPMA_IDX_2 184 `define reqb_set_RXPMA_IDX_0 185 `define reqb_set_RXPMA_IDX_1 186 `define reqb_set_RXPMA_IDX_2 187 `define reqa_set_RXPMA_IDX_0 188 `define reqa_set_RXPMA_IDX_1 189 `define reqa_set_RXPMA_IDX_2 190 `define reserved_0_TB47_RXPMA_IDX_0 191 // Table48: PMA Per Channel RX Control Register 13 for Channel 0 `define rdc_freq_RXPMA_IDX_0 192 `define rdc_freq_RXPMA_IDX_1 193 `define rhyst_lf_RXPMA_IDX_0 194 `define rhyst_lf_RXPMA_IDX_1 195 `define rhyst_lf_RXPMA_IDX_2 196 `define rclkdiv_RXPMA_IDX_0 197 `define rclkdiv_RXPMA_IDX_1 198 `define rclkdiv_RXPMA_IDX_2 199 `define rclkdiv_RXPMA_IDX_3 200 `define rrgen_set_RXPMA_IDX_0 201 `define rrgen_set_RXPMA_IDX_1 202 `define rrgen_set_RXPMA_IDX_2 203 `define radce_adapt_RXPMA_IDX_0 204 `define rseq_sel_RXPMA_IDX_0 205 `define rseq_sel_RXPMA_IDX_1 206 `define rlock_lf_ovd_RXPMA_IDX_0 207 // Table49: PMA Per Channel RX Control Register 14 for Channel 0 `define rrgen_vod_RXPMA_IDX_0 208 `define rrgen_vod_RXPMA_IDX_1 209 `define rrgen_vod_RXPMA_IDX_2 210 `define rf_hpf_RXPMA_IDX_0 211 `define rf_hpf_RXPMA_IDX_1 212 `define rf_lpf_RXPMA_IDX_0 213 `define rf_lpf_RXPMA_IDX_1 214 `define reserved_1_TB49_RXPMA_IDX_0 215 `define reserved_1_TB49_RXPMA_IDX_1 216 `define reserved_1_TB49_RXPMA_IDX_2 217 `define reserved_0_TB49_RXPMA_IDX_0 218 `define reserved_0_TB49_RXPMA_IDX_1 219 `define reserved_0_TB49_RXPMA_IDX_2 220 `define rhyst_hf_RXPMA_IDX_0 221 `define rhyst_hf_RXPMA_IDX_1 222 `define rhyst_hf_RXPMA_IDX_2 223 // Table50: PMA Per Channel RX Control Register 15 for Channel 0 `define radce_pdb_RXPMA_IDX_0 224 `define radce_rst_RXPMA_IDX_0 225 `define rhf_os_RXPMA_IDX_0 226 `define rhf_os_RXPMA_IDX_1 227 `define rhf_os_RXPMA_IDX_2 228 `define rhf_os_RXPMA_IDX_3 229 `define rlf_os_RXPMA_IDX_0 230 `define rlf_os_RXPMA_IDX_1 231 `define rlf_os_RXPMA_IDX_2 232 `define rlf_os_RXPMA_IDX_3 233 `define rd2a_res_RXPMA_IDX_0 234 `define rd2a_res_RXPMA_IDX_1 235 `define rrect_adj_RXPMA_IDX_0 236 `define rrect_adj_RXPMA_IDX_1 237 `define rrgen_bw_RXPMA_IDX_0 238 `define rrgen_bw_RXPMA_IDX_1 239 // Table51: PMA Per Channel RX Control Register 16 for Channel 0 `define radce_hflck_RXPMA_IDX_0 240 `define radce_hflck_RXPMA_IDX_1 241 `define radce_hflck_RXPMA_IDX_2 242 `define radce_hflck_RXPMA_IDX_3 243 `define radce_hflck_RXPMA_IDX_4 244 `define radce_hflck_RXPMA_IDX_5 245 `define radce_hflck_RXPMA_IDX_6 246 `define radce_hflck_RXPMA_IDX_7 247 `define radce_hflck_RXPMA_IDX_8 248 `define radce_hflck_RXPMA_IDX_9 249 `define radce_hflck_RXPMA_IDX_10 250 `define radce_hflck_RXPMA_IDX_11 251 `define radce_hflck_RXPMA_IDX_12 252 `define radce_hflck_RXPMA_IDX_13 253 `define radce_hflck_RXPMA_IDX_14 254 `define reserved_0_TB51_RXPMA_IDX_0 255 // Table52: PMA Per Channel RX Control Register 17 for Channel 0 `define radce_lflck_RXPMA_IDX_0 256 `define radce_lflck_RXPMA_IDX_1 257 `define radce_lflck_RXPMA_IDX_2 258 `define radce_lflck_RXPMA_IDX_3 259 `define radce_lflck_RXPMA_IDX_4 260 `define radce_lflck_RXPMA_IDX_5 261 `define radce_lflck_RXPMA_IDX_6 262 `define radce_lflck_RXPMA_IDX_7 263 `define radce_lflck_RXPMA_IDX_8 264 `define radce_lflck_RXPMA_IDX_9 265 `define radce_lflck_RXPMA_IDX_10 266 `define radce_lflck_RXPMA_IDX_11 267 `define radce_lflck_RXPMA_IDX_12 268 `define radce_lflck_RXPMA_IDX_13 269 `define radce_lflck_RXPMA_IDX_14 270 `define reserved_0_TB52_RXPMA_IDX_0 271 // Table53: PMA Per Channel RX Control Register 18 for Channel 0 `define radce_digital_RXPMA_IDX_0 272 `define radce_digital_RXPMA_IDX_1 273 `define radce_digital_RXPMA_IDX_2 274 `define radce_digital_RXPMA_IDX_3 275 `define radce_digital_RXPMA_IDX_4 276 `define radce_digital_RXPMA_IDX_5 277 `define radce_digital_RXPMA_IDX_6 278 `define radce_digital_RXPMA_IDX_7 279 `define radce_digital_RXPMA_IDX_8 280 `define radce_digital_RXPMA_IDX_9 281 `define reserved_0_TB53_RXPMA_IDX_0 282 `define reserved_0_TB53_RXPMA_IDX_1 283 `define reserved_0_TB53_RXPMA_IDX_2 284 `define reserved_0_TB53_RXPMA_IDX_3 285 `define reserved_0_TB53_RXPMA_IDX_4 286 `define reserved_0_TB53_RXPMA_IDX_5 287 // Extra `define RLPBK_RXPMA_IDX 290 `define RREVLB_SW_RXPMA_IDX 291 `define RRX_S_LPBK_RXPMA_IDX 292 // --------------------------------------------------------------------------- // DPRIO input CRAM // --------------------------------------------------------------------------- // PMA Per Channel RX Control Register 1 for Channel 0 wire [2:0] dprioin_rrx_term_sel; wire [2:0] dprioin_rrx_vtt; wire dprioin_rrx_s_rdlpbk; wire [3:0] dprioin_rrx_bit_dc; wire [4:0] dprioin_rrx_lst; // PMA Per Channel RX Control Register 2 for Channel 0 wire dprioin_rrxurstpma; wire dprioin_rrx_test; wire dprioin_rrx_sd_force; wire [7:0] dprioin_rrx_oc; wire dprioin_rrx_oc_en; wire [3:0] dprioin_rrx_sdlv; // PMA Per Channel RX Control Register 3 for Channel 0 wire [2:0] dprioin_reserved_0_TB38; wire dprioin_rpowdnr; wire dprioin_rrx_ib_pdb; wire dprioin_rurx_pdb; wire dprioin_rrx_oc_calpd; wire [4:0] dprioin_rrx_sd_off; wire [3:0] dprioin_rrx_sd_on; // PMA Per Channel RX Control Register 8 for Channel 0 wire [7:0] dprioin_reye_monitor; wire [7:0] dprioin_reserved_0_TB43; // PMA Per Channel RX Control Register 9 for Channel 0 wire [15:0] dprioin_rpma_reserved_0_TB44; // PMA Per Channel RX Control Register 10 for Channel 0 wire dprioin_rppm_cnt_reset; wire dprioin_rforce1_freqdet; wire dprioin_rforce0_freqdet; wire [5:0] dprioin_rppmsel; wire [3:0] dprioin_rfastsd; wire dprioin_rtest_fastsd; wire dprioin_rpmadwidth_rx; wire dprioin_rpma_doublewidth_rx; // PMA Per Channel RX Control Register 11 for Channel 0 wire [7:0] dprioin_reserved_0_TB46; wire dprioin_rppm_gen1_2xcnt_en; wire dprioin_rppm_post_eidle_del; wire [2:0] dprioin_r_dfe_2t; wire [2:0] dprioin_r_dfe_1t; // PMA Per Channel RX Control Register 12 for Channel 0 wire [2:0] dprioin_reqv_set; wire [2:0] dprioin_reqd_set; wire [2:0] dprioin_reqc_set; wire [2:0] dprioin_reqb_set; wire [2:0] dprioin_reqa_set; wire dprioin_reserved_0_TB47; // PMA Per Channel RX Control Register 13 for Channel 0 wire [1:0] dprioin_rdc_freq; wire [2:0] dprioin_rhyst_lf; wire [3:0] dprioin_rclkdiv; wire [2:0] dprioin_rrgen_set; wire dprioin_radce_adapt; wire [1:0] dprioin_rseq_sel; wire dprioin_rlock_lf_ovd; // PMA Per Channel RX Control Register 14 for Channel 0 wire [2:0] dprioin_rrgen_vod; wire [1:0] dprioin_rf_hpf; wire [1:0] dprioin_rf_lpf; wire [2:0] dprioin_reserved_1_TB49; wire [2:0] dprioin_reserved_0_TB49; wire [2:0] dprioin_rhyst_hf; // PMA Per Channel RX Control Register 15 for Channel 0 wire dprioin_radce_pdb; wire dprioin_radce_rst; wire [3:0] dprioin_rhf_os; wire [3:0] dprioin_rlf_os; wire [1:0] dprioin_rd2a_res; wire [1:0] dprioin_rrect_adj; wire [1:0] dprioin_rrgen_bw; // PMA Per Channel RX Control Register 16 for Channel 0 wire [14:0] dprioin_radce_hflck; wire dprioin_reserved_0_TB51; // PMA Per Channel RX Control Register 17 for Channel 0 wire [14:0] dprioin_radce_lflck; wire dprioin_reserved_0_TB52; // PMA Per Channel RX Control Register 18 for Channel 0 wire [9:0] dprioin_radce_digital; wire [5:0] dprioin_reserved_0_TB53; // Extra wire dprioin_rlpbk; wire dprioin_rrevlb_sw; wire dprioin_rrx_s_lpbk; // --------------------------------------------------------------------------- // Initial CRAM // --------------------------------------------------------------------------- // PMA Per Channel RX Control Register 1 for Channel 0 reg [2:0] init_rrx_term_sel; reg [2:0] init_rrx_vtt; reg init_rrx_s_rdlpbk; reg [3:0] init_rrx_bit_dc; reg [4:0] init_rrx_lst; // PMA Per Channel RX Control Register 2 for Channel 0 reg init_rrxurstpma; reg init_rrx_test; reg init_rrx_sd_force; reg [7:0] init_rrx_oc; reg init_rrx_oc_en; reg [3:0] init_rrx_sdlv; // PMA Per Channel RX Control Register 3 for Channel 0 reg [2:0] init_reserved_0_TB38; reg init_rpowdnr; reg init_rrx_ib_pdb; reg init_rurx_pdb; reg init_rrx_oc_calpd; reg [4:0] init_rrx_sd_off; reg [3:0] init_rrx_sd_on; // PMA Per Channel RX Control Register 8 for Channel 0 reg [7:0] init_reye_monitor; reg [7:0] init_reserved_0_TB43; // PMA Per Channel RX Control Register 9 for Channel 0 reg [15:0] init_rpma_reserved_0_TB44; // PMA Per Channel RX Control Register 10 for Channel 0 reg init_rppm_cnt_reset; reg init_rforce1_freqdet; reg init_rforce0_freqdet; reg [5:0] init_rppmsel; reg [3:0] init_rfastsd; reg init_rtest_fastsd; reg init_rpmadwidth_rx; reg init_rpma_doublewidth_rx; // PMA Per Channel RX Control Register 11 for Channel 0 reg [7:0] init_reserved_0_TB46; reg init_rppm_gen1_2xcnt_en; reg init_rppm_post_eidle_del; reg [2:0] init_r_dfe_2t; reg [2:0] init_r_dfe_1t; // PMA Per Channel RX Control Register 12 for Channel 0 reg [2:0] init_reqv_set; reg [2:0] init_reqd_set; reg [2:0] init_reqc_set; reg [2:0] init_reqb_set; reg [2:0] init_reqa_set; reg init_reserved_0_TB47; // PMA Per Channel RX Control Register 13 for Channel 0 reg [1:0] init_rdc_freq; reg [2:0] init_rhyst_lf; reg [3:0] init_rclkdiv; reg [2:0] init_rrgen_set; reg init_radce_adapt; reg [1:0] init_rseq_sel; reg init_rlock_lf_ovd; // PMA Per Channel RX Control Register 14 for Channel 0 reg [2:0] init_rrgen_vod; reg [1:0] init_rf_hpf; reg [1:0] init_rf_lpf; reg [2:0] init_reserved_1_TB49; reg [2:0] init_reserved_0_TB49; reg [2:0] init_rhyst_hf; // PMA Per Channel RX Control Register 15 for Channel 0 reg init_radce_pdb; reg init_radce_rst; reg [3:0] init_rhf_os; reg [3:0] init_rlf_os; reg [1:0] init_rd2a_res; reg [1:0] init_rrect_adj; reg [1:0] init_rrgen_bw; // PMA Per Channel RX Control Register 16 for Channel 0 reg [14:0] init_radce_hflck; reg init_reserved_0_TB51; // PMA Per Channel RX Control Register 17 for Channel 0 reg [14:0] init_radce_lflck; reg init_reserved_0_TB52; // PMA Per Channel RX Control Register 18 for Channel 0 reg [9:0] init_radce_digital; reg [5:0] init_reserved_0_TB53; // Extra reg init_rlpbk; reg init_rrevlb_sw; reg init_rrx_s_lpbk; // --------------------------------------------------------------------------- // CRAM // --------------------------------------------------------------------------- // PMA Per Channel RX Control Register 1 for Channel 0 wire [2:0] cram_rrx_term_sel; wire [2:0] cram_rrx_vtt; wire cram_rrx_s_rdlpbk; wire [3:0] cram_rrx_bit_dc; wire [4:0] cram_rrx_lst; // PMA Per Channel RX Control Register 2 for Channel 0 wire cram_rrxurstpma; wire cram_rrx_test; wire cram_rrx_sd_force; wire [7:0] cram_rrx_oc; wire cram_rrx_oc_en; wire [3:0] cram_rrx_sdlv; // PMA Per Channel RX Control Register 3 for Channel 0 wire [2:0] cram_reserved_0_TB38; wire cram_rpowdnr; wire cram_rrx_ib_pdb; wire cram_rurx_pdb; wire cram_rrx_oc_calpd; wire [4:0] cram_rrx_sd_off; wire [3:0] cram_rrx_sd_on; // PMA Per Channel RX Control Register 8 for Channel 0 wire [7:0] cram_reye_monitor; wire [7:0] cram_reserved_0_TB43; // PMA Per Channel RX Control Register 9 for Channel 0 wire [15:0] cram_rpma_reserved_0_TB44; // PMA Per Channel RX Control Register 10 for Channel 0 wire cram_rppm_cnt_reset; wire cram_rforce1_freqdet; wire cram_rforce0_freqdet; wire [5:0] cram_rppmsel; wire [3:0] cram_rfastsd; wire cram_rtest_fastsd; wire cram_rpmadwidth_rx; wire cram_rpma_doublewidth_rx; // PMA Per Channel RX Control Register 11 for Channel 0 wire [7:0] cram_reserved_0_TB46; wire cram_rppm_gen1_2xcnt_en; wire cram_rppm_post_eidle_del; wire [2:0] cram_r_dfe_2t; wire [2:0] cram_r_dfe_1t; // PMA Per Channel RX Control Register 12 for Channel 0 wire [2:0] cram_reqv_set; wire [2:0] cram_reqd_set; wire [2:0] cram_reqc_set; wire [2:0] cram_reqb_set; wire [2:0] cram_reqa_set; wire cram_reserved_0_TB47; // PMA Per Channel RX Control Register 13 for Channel 0 wire [1:0] cram_rdc_freq; wire [2:0] cram_rhyst_lf; wire [3:0] cram_rclkdiv; wire [2:0] cram_rrgen_set; wire cram_radce_adapt; wire [1:0] cram_rseq_sel; wire cram_rlock_lf_ovd; // PMA Per Channel RX Control Register 14 for Channel 0 wire [2:0] cram_rrgen_vod; wire [1:0] cram_rf_hpf; wire [1:0] cram_rf_lpf; wire [2:0] cram_reserved_1_TB49; wire [2:0] cram_reserved_0_TB49; wire [2:0] cram_rhyst_hf; // PMA Per Channel RX Control Register 15 for Channel 0 wire cram_radce_pdb; wire cram_radce_rst; wire [3:0] cram_rhf_os; wire [3:0] cram_rlf_os; wire [1:0] cram_rd2a_res; wire [1:0] cram_rrect_adj; wire [1:0] cram_rrgen_bw; // PMA Per Channel RX Control Register 16 for Channel 0 wire [14:0] cram_radce_hflck; wire cram_reserved_0_TB51; // PMA Per Channel RX Control Register 17 for Channel 0 wire [14:0] cram_radce_lflck; wire cram_reserved_0_TB52; // PMA Per Channel RX Control Register 18 for Channel 0 wire [9:0] cram_radce_digital; wire [5:0] cram_reserved_0_TB53; // Extra wire cram_rlpbk; wire cram_rrevlb_sw; wire cram_rrx_s_lpbk; // --------------------------------------------------------------------------- // Set DPRIO CRAM input from dprioin // --------------------------------------------------------------------------- // PMA Per Channel RX Control Register 1 for Channel 0 assign dprioin_rrx_term_sel = dprioin[`rrx_term_sel_RXPMA_IDX_2 : `rrx_term_sel_RXPMA_IDX_0]; assign dprioin_rrx_vtt = dprioin[`rrx_vtt_RXPMA_IDX_2 : `rrx_vtt_RXPMA_IDX_0]; assign dprioin_rrx_s_rdlpbk = dprioin[`rrx_s_rdlpbk_RXPMA_IDX_0]; assign dprioin_rrx_bit_dc = dprioin[`rrx_bit_dc_RXPMA_IDX_3 : `rrx_bit_dc_RXPMA_IDX_0]; assign dprioin_rrx_lst = dprioin[`rrx_lst_RXPMA_IDX_4 : `rrx_lst_RXPMA_IDX_0]; // PMA Per Channel RX Control Register 2 for Channel 0 assign dprioin_rrxurstpma = dprioin[`rrxurstpma_RXPMA_IDX_0]; assign dprioin_rrx_test = dprioin[`rrx_test_RXPMA_IDX_0]; assign dprioin_rrx_sd_force = dprioin[`rrx_sd_force_RXPMA_IDX_0]; assign dprioin_rrx_oc = dprioin[`rrx_oc_RXPMA_IDX_7 : `rrx_oc_RXPMA_IDX_0]; assign dprioin_rrx_oc_en = dprioin[`rrx_oc_en_RXPMA_IDX_0]; assign dprioin_rrx_sdlv = dprioin[`rrx_sdlv_RXPMA_IDX_3 : `rrx_sdlv_RXPMA_IDX_0]; // PMA Per Channel RX Control Register 3 for Channel 0 assign dprioin_reserved_0_TB38 = dprioin[`reserved_0_TB38_RXPMA_IDX_2 : `reserved_0_TB38_RXPMA_IDX_0]; assign dprioin_rpowdnr = dprioin[`rpowdnr_RXPMA_IDX_0]; assign dprioin_rrx_ib_pdb = dprioin[`rrx_ib_pdb_RXPMA_IDX_0]; assign dprioin_rurx_pdb = dprioin[`rurx_pdb_RXPMA_IDX_0]; assign dprioin_rrx_oc_calpd = dprioin[`rrx_oc_calpd_RXPMA_IDX_0]; assign dprioin_rrx_sd_off = dprioin[`rrx_sd_off_RXPMA_IDX_4 : `rrx_sd_off_RXPMA_IDX_0]; assign dprioin_rrx_sd_on = dprioin[`rrx_sd_on_RXPMA_IDX_3 : `rrx_sd_on_RXPMA_IDX_0]; // PMA Per Channel RX Control Register 8 for Channel 0 assign dprioin_reye_monitor = dprioin[`reye_monitor_RXPMA_IDX_7 : `reye_monitor_RXPMA_IDX_0]; assign dprioin_reserved_0_TB43 = dprioin[`reserved_0_TB43_RXPMA_IDX_7 : `reserved_0_TB43_RXPMA_IDX_0]; // PMA Per Channel RX Control Register 9 for Channel 0 assign dprioin_rpma_reserved_0_TB44 = dprioin[`rpma_reserved_0_TB44_RXPMA_IDX_15 : `rpma_reserved_0_TB44_RXPMA_IDX_0]; // PMA Per Channel RX Control Register 10 for Channel 0 assign dprioin_rppm_cnt_reset = dprioin[`rppm_cnt_reset_RXPMA_IDX_0]; assign dprioin_rforce1_freqdet = dprioin[`rforce1_freqdet_RXPMA_IDX_0]; assign dprioin_rforce0_freqdet = dprioin[`rforce0_freqdet_RXPMA_IDX_0]; assign dprioin_rppmsel = dprioin[`rppmsel_RXPMA_IDX_5 : `rppmsel_RXPMA_IDX_0]; assign dprioin_rfastsd = dprioin[`rfastsd_RXPMA_IDX_3 : `rfastsd_RXPMA_IDX_0]; assign dprioin_rtest_fastsd = dprioin[`rtest_fastsd_RXPMA_IDX_0]; assign dprioin_rpmadwidth_rx = dprioin[`rpmadwidth_rx_RXPMA_IDX_0]; assign dprioin_rpma_doublewidth_rx = dprioin[`rpma_doublewidth_rx_RXPMA_IDX_0]; // PMA Per Channel RX Control Register 11 for Channel 0 assign dprioin_reserved_0_TB46 = dprioin[`reserved_0_TB46_RXPMA_IDX_7 : `reserved_0_TB46_RXPMA_IDX_0]; assign dprioin_rppm_gen1_2xcnt_en = dprioin[`rppm_gen1_2xcnt_en_RXPMA_IDX_0]; assign dprioin_rppm_post_eidle_del = dprioin[`rppm_post_eidle_del_RXPMA_IDX_0]; assign dprioin_r_dfe_2t = dprioin[`r_dfe_2t_RXPMA_IDX_2 : `r_dfe_2t_RXPMA_IDX_0]; assign dprioin_r_dfe_1t = dprioin[`r_dfe_1t_RXPMA_IDX_2 : `r_dfe_1t_RXPMA_IDX_0]; // PMA Per Channel RX Control Register 12 for Channel 0 assign dprioin_reqv_set = dprioin[`reqv_set_RXPMA_IDX_2 : `reqv_set_RXPMA_IDX_0]; assign dprioin_reqd_set = dprioin[`reqd_set_RXPMA_IDX_2 : `reqd_set_RXPMA_IDX_0]; assign dprioin_reqc_set = dprioin[`reqc_set_RXPMA_IDX_2 : `reqc_set_RXPMA_IDX_0]; assign dprioin_reqb_set = dprioin[`reqb_set_RXPMA_IDX_2 : `reqb_set_RXPMA_IDX_0]; assign dprioin_reqa_set = dprioin[`reqa_set_RXPMA_IDX_2 : `reqa_set_RXPMA_IDX_0]; assign dprioin_reserved_0_TB47 = dprioin[`reserved_0_TB47_RXPMA_IDX_0]; // PMA Per Channel RX Control Register 13 for Channel 0 assign dprioin_rdc_freq = dprioin[`rdc_freq_RXPMA_IDX_1 : `rdc_freq_RXPMA_IDX_0]; assign dprioin_rhyst_lf = dprioin[`rhyst_lf_RXPMA_IDX_2 : `rhyst_lf_RXPMA_IDX_0]; assign dprioin_rclkdiv = dprioin[`rclkdiv_RXPMA_IDX_3 : `rclkdiv_RXPMA_IDX_0]; assign dprioin_rrgen_set = dprioin[`rrgen_set_RXPMA_IDX_2 : `rrgen_set_RXPMA_IDX_0]; assign dprioin_radce_adapt = dprioin[`radce_adapt_RXPMA_IDX_0]; assign dprioin_rseq_sel = dprioin[`rseq_sel_RXPMA_IDX_1 : `rseq_sel_RXPMA_IDX_0]; assign dprioin_rlock_lf_ovd = dprioin[`rlock_lf_ovd_RXPMA_IDX_0]; // PMA Per Channel RX Control Register 14 for Channel 0 assign dprioin_rrgen_vod = dprioin[`rrgen_vod_RXPMA_IDX_2 : `rrgen_vod_RXPMA_IDX_0]; assign dprioin_rf_hpf = dprioin[`rf_hpf_RXPMA_IDX_1 : `rf_hpf_RXPMA_IDX_0]; assign dprioin_rf_lpf = dprioin[`rf_lpf_RXPMA_IDX_1 : `rf_lpf_RXPMA_IDX_0]; assign dprioin_reserved_1_TB49 = dprioin[`reserved_1_TB49_RXPMA_IDX_2 : `reserved_1_TB49_RXPMA_IDX_0]; assign dprioin_reserved_0_TB49 = dprioin[`reserved_0_TB49_RXPMA_IDX_2 : `reserved_0_TB49_RXPMA_IDX_0]; assign dprioin_rhyst_hf = dprioin[`rhyst_hf_RXPMA_IDX_2 : `rhyst_hf_RXPMA_IDX_0]; // PMA Per Channel RX Control Register 15 for Channel 0 assign dprioin_radce_pdb = dprioin[`radce_pdb_RXPMA_IDX_0]; assign dprioin_radce_rst = dprioin[`radce_rst_RXPMA_IDX_0]; assign dprioin_rhf_os = dprioin[`rhf_os_RXPMA_IDX_3 : `rhf_os_RXPMA_IDX_0]; assign dprioin_rlf_os = dprioin[`rlf_os_RXPMA_IDX_3 : `rlf_os_RXPMA_IDX_0]; assign dprioin_rd2a_res = dprioin[`rd2a_res_RXPMA_IDX_1 : `rd2a_res_RXPMA_IDX_0]; assign dprioin_rrect_adj = dprioin[`rrect_adj_RXPMA_IDX_1 : `rrect_adj_RXPMA_IDX_0]; assign dprioin_rrgen_bw = dprioin[`rrgen_bw_RXPMA_IDX_1 : `rrgen_bw_RXPMA_IDX_0]; // PMA Per Channel RX Control Register 16 for Channel 0 assign dprioin_radce_hflck = dprioin[`radce_hflck_RXPMA_IDX_14 : `radce_hflck_RXPMA_IDX_0]; assign dprioin_reserved_0_TB51 = dprioin[`reserved_0_TB51_RXPMA_IDX_0]; // PMA Per Channel RX Control Register 17 for Channel 0 assign dprioin_radce_lflck = dprioin[`radce_lflck_RXPMA_IDX_14 : `radce_lflck_RXPMA_IDX_0]; assign dprioin_reserved_0_TB52 = dprioin[`reserved_0_TB52_RXPMA_IDX_0]; // PMA Per Channel RX Control Register 18 for Channel 0 assign dprioin_radce_digital = dprioin[`radce_digital_RXPMA_IDX_9 : `radce_digital_RXPMA_IDX_0]; assign dprioin_reserved_0_TB53 = dprioin[`reserved_0_TB53_RXPMA_IDX_5 : `reserved_0_TB53_RXPMA_IDX_0]; // Extra assign dprioin_rlpbk = dprioin[`RLPBK_RXPMA_IDX]; assign dprioin_rrevlb_sw = dprioin[`RREVLB_SW_RXPMA_IDX]; assign dprioin_rrx_s_lpbk = dprioin[`RRX_S_LPBK_RXPMA_IDX]; // --------------------------------------------------------------------------- // Set DPRIO output from initial CRAM // --------------------------------------------------------------------------- // PMA Per Channel RX Control Register 1 for Channel 0 assign dprioout[`rrx_term_sel_RXPMA_IDX_2 : `rrx_term_sel_RXPMA_IDX_0] = init_rrx_term_sel; assign dprioout[`rrx_vtt_RXPMA_IDX_2 : `rrx_vtt_RXPMA_IDX_0] = init_rrx_vtt; assign dprioout[`rrx_s_rdlpbk_RXPMA_IDX_0] = init_rrx_s_rdlpbk; assign dprioout[`rrx_bit_dc_RXPMA_IDX_3 : `rrx_bit_dc_RXPMA_IDX_0] = init_rrx_bit_dc; assign dprioout[`rrx_lst_RXPMA_IDX_4 : `rrx_lst_RXPMA_IDX_0] = init_rrx_lst; // PMA Per Channel RX Control Register 2 for Channel 0 assign dprioout[`rrxurstpma_RXPMA_IDX_0] = init_rrxurstpma; assign dprioout[`rrx_test_RXPMA_IDX_0] = init_rrx_test; assign dprioout[`rrx_sd_force_RXPMA_IDX_0] = init_rrx_sd_force; assign dprioout[`rrx_oc_RXPMA_IDX_7 : `rrx_oc_RXPMA_IDX_0] = init_rrx_oc; assign dprioout[`rrx_oc_en_RXPMA_IDX_0] = init_rrx_oc_en; assign dprioout[`rrx_sdlv_RXPMA_IDX_3 : `rrx_sdlv_RXPMA_IDX_0] = init_rrx_sdlv; // PMA Per Channel RX Control Register 3 for Channel 0 assign dprioout[`reserved_0_TB38_RXPMA_IDX_2 : `reserved_0_TB38_RXPMA_IDX_0] = init_reserved_0_TB38; assign dprioout[`rpowdnr_RXPMA_IDX_0] = init_rpowdnr; assign dprioout[`rrx_ib_pdb_RXPMA_IDX_0] = init_rrx_ib_pdb; assign dprioout[`rurx_pdb_RXPMA_IDX_0] = init_rurx_pdb; assign dprioout[`rrx_oc_calpd_RXPMA_IDX_0] = init_rrx_oc_calpd; assign dprioout[`rrx_sd_off_RXPMA_IDX_4 : `rrx_sd_off_RXPMA_IDX_0] = init_rrx_sd_off; assign dprioout[`rrx_sd_on_RXPMA_IDX_3 : `rrx_sd_on_RXPMA_IDX_0] = init_rrx_sd_on; // PMA Per Channel RX Control Register 8 for Channel 0 assign dprioout[`reye_monitor_RXPMA_IDX_7 : `reye_monitor_RXPMA_IDX_0] = init_reye_monitor; assign dprioout[`reserved_0_TB43_RXPMA_IDX_7 : `reserved_0_TB43_RXPMA_IDX_0] = init_reserved_0_TB43; // PMA Per Channel RX Control Register 9 for Channel 0 assign dprioout[`rpma_reserved_0_TB44_RXPMA_IDX_15 : `rpma_reserved_0_TB44_RXPMA_IDX_0] = init_rpma_reserved_0_TB44; // PMA Per Channel RX Control Register 10 for Channel 0 assign dprioout[`rppm_cnt_reset_RXPMA_IDX_0] = init_rppm_cnt_reset; assign dprioout[`rforce1_freqdet_RXPMA_IDX_0] = init_rforce1_freqdet; assign dprioout[`rforce0_freqdet_RXPMA_IDX_0] = init_rforce0_freqdet; assign dprioout[`rppmsel_RXPMA_IDX_5 : `rppmsel_RXPMA_IDX_0] = init_rppmsel; assign dprioout[`rfastsd_RXPMA_IDX_3 : `rfastsd_RXPMA_IDX_0] = init_rfastsd; assign dprioout[`rtest_fastsd_RXPMA_IDX_0] = init_rtest_fastsd; assign dprioout[`rpmadwidth_rx_RXPMA_IDX_0] = init_rpmadwidth_rx; assign dprioout[`rpma_doublewidth_rx_RXPMA_IDX_0] = init_rpma_doublewidth_rx; // PMA Per Channel RX Control Register 11 for Channel 0 assign dprioout[`reserved_0_TB46_RXPMA_IDX_7 : `reserved_0_TB46_RXPMA_IDX_0] = init_reserved_0_TB46; assign dprioout[`rppm_gen1_2xcnt_en_RXPMA_IDX_0] = init_rppm_gen1_2xcnt_en; assign dprioout[`rppm_post_eidle_del_RXPMA_IDX_0] = init_rppm_post_eidle_del; assign dprioout[`r_dfe_2t_RXPMA_IDX_2 : `r_dfe_2t_RXPMA_IDX_0] = init_r_dfe_2t; assign dprioout[`r_dfe_1t_RXPMA_IDX_2 : `r_dfe_1t_RXPMA_IDX_0] = init_r_dfe_1t; // PMA Per Channel RX Control Register 12 for Channel 0 assign dprioout[`reqv_set_RXPMA_IDX_2 : `reqv_set_RXPMA_IDX_0] = init_reqv_set; assign dprioout[`reqd_set_RXPMA_IDX_2 : `reqd_set_RXPMA_IDX_0] = init_reqd_set; assign dprioout[`reqc_set_RXPMA_IDX_2 : `reqc_set_RXPMA_IDX_0] = init_reqc_set; assign dprioout[`reqb_set_RXPMA_IDX_2 : `reqb_set_RXPMA_IDX_0] = init_reqb_set; assign dprioout[`reqa_set_RXPMA_IDX_2 : `reqa_set_RXPMA_IDX_0] = init_reqa_set; assign dprioout[`reserved_0_TB47_RXPMA_IDX_0] = init_reserved_0_TB47; // PMA Per Channel RX Control Register 13 for Channel 0 assign dprioout[`rdc_freq_RXPMA_IDX_1 : `rdc_freq_RXPMA_IDX_0] = init_rdc_freq; assign dprioout[`rhyst_lf_RXPMA_IDX_2 : `rhyst_lf_RXPMA_IDX_0] = init_rhyst_lf; assign dprioout[`rclkdiv_RXPMA_IDX_3 : `rclkdiv_RXPMA_IDX_0] = init_rclkdiv; assign dprioout[`rrgen_set_RXPMA_IDX_2 : `rrgen_set_RXPMA_IDX_0] = init_rrgen_set; assign dprioout[`radce_adapt_RXPMA_IDX_0] = init_radce_adapt; assign dprioout[`rseq_sel_RXPMA_IDX_1 : `rseq_sel_RXPMA_IDX_0] = init_rseq_sel; assign dprioout[`rlock_lf_ovd_RXPMA_IDX_0] = init_rlock_lf_ovd; // PMA Per Channel RX Control Register 14 for Channel 0 assign dprioout[`rrgen_vod_RXPMA_IDX_2 : `rrgen_vod_RXPMA_IDX_0] = init_rrgen_vod; assign dprioout[`rf_hpf_RXPMA_IDX_1 : `rf_hpf_RXPMA_IDX_0] = init_rf_hpf; assign dprioout[`rf_lpf_RXPMA_IDX_1 : `rf_lpf_RXPMA_IDX_0] = init_rf_lpf; assign dprioout[`reserved_1_TB49_RXPMA_IDX_2 : `reserved_1_TB49_RXPMA_IDX_0] = init_reserved_1_TB49; assign dprioout[`reserved_0_TB49_RXPMA_IDX_2 : `reserved_0_TB49_RXPMA_IDX_0] = init_reserved_0_TB49; assign dprioout[`rhyst_hf_RXPMA_IDX_2 : `rhyst_hf_RXPMA_IDX_0] = init_rhyst_hf; // PMA Per Channel RX Control Register 15 for Channel 0 assign dprioout[`radce_pdb_RXPMA_IDX_0] = init_radce_pdb; assign dprioout[`radce_rst_RXPMA_IDX_0] = init_radce_rst; assign dprioout[`rhf_os_RXPMA_IDX_3 : `rhf_os_RXPMA_IDX_0] = init_rhf_os; assign dprioout[`rlf_os_RXPMA_IDX_3 : `rlf_os_RXPMA_IDX_0] = init_rlf_os; assign dprioout[`rd2a_res_RXPMA_IDX_1 : `rd2a_res_RXPMA_IDX_0] = init_rd2a_res; assign dprioout[`rrect_adj_RXPMA_IDX_1 : `rrect_adj_RXPMA_IDX_0] = init_rrect_adj; assign dprioout[`rrgen_bw_RXPMA_IDX_1 : `rrgen_bw_RXPMA_IDX_0] = init_rrgen_bw; // PMA Per Channel RX Control Register 16 for Channel 0 assign dprioout[`radce_hflck_RXPMA_IDX_14 : `radce_hflck_RXPMA_IDX_0] = init_radce_hflck; assign dprioout[`reserved_0_TB51_RXPMA_IDX_0] = init_reserved_0_TB51; // PMA Per Channel RX Control Register 17 for Channel 0 assign dprioout[`radce_lflck_RXPMA_IDX_14 : `radce_lflck_RXPMA_IDX_0] = init_radce_lflck; assign dprioout[`reserved_0_TB52_RXPMA_IDX_0] = init_reserved_0_TB52; // PMA Per Channel RX Control Register 18 for Channel 0 assign dprioout[`radce_digital_RXPMA_IDX_9 : `radce_digital_RXPMA_IDX_0] = init_radce_digital; assign dprioout[`reserved_0_TB53_RXPMA_IDX_5 : `reserved_0_TB53_RXPMA_IDX_0] = init_reserved_0_TB53; // Extra assign dprioout[`RLPBK_RXPMA_IDX] = init_rlpbk; assign dprioout[`RREVLB_SW_RXPMA_IDX] = init_rrevlb_sw; assign dprioout[`RRX_S_LPBK_RXPMA_IDX] = init_rrx_s_lpbk; // --------------------------------------------------------------------------- // Set DPRIO CRAM // --------------------------------------------------------------------------- // PMA Per Channel RX Control Register 1 for Channel 0 assign cram_rrx_term_sel = (dpriodisable !== 1'b0) ? init_rrx_term_sel : dprioin_rrx_term_sel; assign cram_rrx_vtt = (dpriodisable !== 1'b0) ? init_rrx_vtt : dprioin_rrx_vtt; assign cram_rrx_s_rdlpbk = (dpriodisable !== 1'b0) ? init_rrx_s_rdlpbk : dprioin_rrx_s_rdlpbk; assign cram_rrx_bit_dc = (dpriodisable !== 1'b0) ? init_rrx_bit_dc : dprioin_rrx_bit_dc; assign cram_rrx_lst = (dpriodisable !== 1'b0) ? init_rrx_lst : dprioin_rrx_lst; // PMA Per Channel RX Control Register 2 for Channel 0 assign cram_rrxurstpma = (dpriodisable !== 1'b0) ? init_rrxurstpma : dprioin_rrxurstpma; assign cram_rrx_test = (dpriodisable !== 1'b0) ? init_rrx_test : dprioin_rrx_test; assign cram_rrx_sd_force = (dpriodisable !== 1'b0) ? init_rrx_sd_force : dprioin_rrx_sd_force; assign cram_rrx_oc = (dpriodisable !== 1'b0) ? init_rrx_oc : dprioin_rrx_oc; assign cram_rrx_oc_en = (dpriodisable !== 1'b0) ? init_rrx_oc_en : dprioin_rrx_oc_en; assign cram_rrx_sdlv = (dpriodisable !== 1'b0) ? init_rrx_sdlv : dprioin_rrx_sdlv; // PMA Per Channel RX Control Register 3 for Channel 0 assign cram_reserved_0_TB38 = (dpriodisable !== 1'b0) ? init_reserved_0_TB38 : dprioin_reserved_0_TB38; assign cram_rpowdnr = (dpriodisable !== 1'b0) ? init_rpowdnr : dprioin_rpowdnr; assign cram_rrx_ib_pdb = (dpriodisable !== 1'b0) ? init_rrx_ib_pdb : dprioin_rrx_ib_pdb; assign cram_rurx_pdb = (dpriodisable !== 1'b0) ? init_rurx_pdb : dprioin_rurx_pdb; assign cram_rrx_oc_calpd = (dpriodisable !== 1'b0) ? init_rrx_oc_calpd : dprioin_rrx_oc_calpd; assign cram_rrx_sd_off = (dpriodisable !== 1'b0) ? init_rrx_sd_off : dprioin_rrx_sd_off; assign cram_rrx_sd_on = (dpriodisable !== 1'b0) ? init_rrx_sd_on : dprioin_rrx_sd_on; // PMA Per Channel RX Control Register 8 for Channel 0 assign cram_reye_monitor = (dpriodisable !== 1'b0) ? init_reye_monitor : dprioin_reye_monitor; assign cram_reserved_0_TB43 = (dpriodisable !== 1'b0) ? init_reserved_0_TB43 : dprioin_reserved_0_TB43; // PMA Per Channel RX Control Register 9 for Channel 0 assign cram_rpma_reserved_0_TB44 = (dpriodisable !== 1'b0) ? init_rpma_reserved_0_TB44 : dprioin_rpma_reserved_0_TB44; // PMA Per Channel RX Control Register 10 for Channel 0 assign cram_rppm_cnt_reset = (dpriodisable !== 1'b0) ? init_rppm_cnt_reset : dprioin_rppm_cnt_reset; assign cram_rforce1_freqdet = (dpriodisable !== 1'b0) ? init_rforce1_freqdet : dprioin_rforce1_freqdet; assign cram_rforce0_freqdet = (dpriodisable !== 1'b0) ? init_rforce0_freqdet : dprioin_rforce0_freqdet; assign cram_rppmsel = (dpriodisable !== 1'b0) ? init_rppmsel : dprioin_rppmsel; assign cram_rfastsd = (dpriodisable !== 1'b0) ? init_rfastsd : dprioin_rfastsd; assign cram_rtest_fastsd = (dpriodisable !== 1'b0) ? init_rtest_fastsd : dprioin_rtest_fastsd; assign cram_rpmadwidth_rx = (dpriodisable !== 1'b0) ? init_rpmadwidth_rx : dprioin_rpmadwidth_rx; assign cram_rpma_doublewidth_rx = (dpriodisable !== 1'b0) ? init_rpma_doublewidth_rx : dprioin_rpma_doublewidth_rx; // PMA Per Channel RX Control Register 11 for Channel 0 assign cram_reserved_0_TB46 = (dpriodisable !== 1'b0) ? init_reserved_0_TB46 : dprioin_reserved_0_TB46; assign cram_rppm_gen1_2xcnt_en = (dpriodisable !== 1'b0) ? init_rppm_gen1_2xcnt_en : dprioin_rppm_gen1_2xcnt_en; assign cram_rppm_post_eidle_del = (dpriodisable !== 1'b0) ? init_rppm_post_eidle_del : dprioin_rppm_post_eidle_del; assign cram_r_dfe_2t = (dpriodisable !== 1'b0) ? init_r_dfe_2t : dprioin_r_dfe_2t; assign cram_r_dfe_1t = (dpriodisable !== 1'b0) ? init_r_dfe_1t : dprioin_r_dfe_1t; // PMA Per Channel RX Control Register 12 for Channel 0 assign cram_reqv_set = (dpriodisable !== 1'b0) ? init_reqv_set : dprioin_reqv_set; assign cram_reqd_set = (dpriodisable !== 1'b0) ? init_reqd_set : dprioin_reqd_set; assign cram_reqc_set = (dpriodisable !== 1'b0) ? init_reqc_set : dprioin_reqc_set; assign cram_reqb_set = (dpriodisable !== 1'b0) ? init_reqb_set : dprioin_reqb_set; assign cram_reqa_set = (dpriodisable !== 1'b0) ? init_reqa_set : dprioin_reqa_set; assign cram_reserved_0_TB47 = (dpriodisable !== 1'b0) ? init_reserved_0_TB47 : dprioin_reserved_0_TB47; // PMA Per Channel RX Control Register 13 for Channel 0 assign cram_rdc_freq = (dpriodisable !== 1'b0) ? init_rdc_freq : dprioin_rdc_freq; assign cram_rhyst_lf = (dpriodisable !== 1'b0) ? init_rhyst_lf : dprioin_rhyst_lf; assign cram_rclkdiv = (dpriodisable !== 1'b0) ? init_rclkdiv : dprioin_rclkdiv; assign cram_rrgen_set = (dpriodisable !== 1'b0) ? init_rrgen_set : dprioin_rrgen_set; assign cram_radce_adapt = (dpriodisable !== 1'b0) ? init_radce_adapt : dprioin_radce_adapt; assign cram_rseq_sel = (dpriodisable !== 1'b0) ? init_rseq_sel : dprioin_rseq_sel; assign cram_rlock_lf_ovd = (dpriodisable !== 1'b0) ? init_rlock_lf_ovd : dprioin_rlock_lf_ovd; // PMA Per Channel RX Control Register 14 for Channel 0 assign cram_rrgen_vod = (dpriodisable !== 1'b0) ? init_rrgen_vod : dprioin_rrgen_vod; assign cram_rf_hpf = (dpriodisable !== 1'b0) ? init_rf_hpf : dprioin_rf_hpf; assign cram_rf_lpf = (dpriodisable !== 1'b0) ? init_rf_lpf : dprioin_rf_lpf; assign cram_reserved_1_TB49 = (dpriodisable !== 1'b0) ? init_reserved_1_TB49 : dprioin_reserved_1_TB49; assign cram_reserved_0_TB49 = (dpriodisable !== 1'b0) ? init_reserved_0_TB49 : dprioin_reserved_0_TB49; assign cram_rhyst_hf = (dpriodisable !== 1'b0) ? init_rhyst_hf : dprioin_rhyst_hf; // PMA Per Channel RX Control Register 15 for Channel 0 assign cram_radce_pdb = (dpriodisable !== 1'b0) ? init_radce_pdb : dprioin_radce_pdb; assign cram_radce_rst = (dpriodisable !== 1'b0) ? init_radce_rst : dprioin_radce_rst; assign cram_rhf_os = (dpriodisable !== 1'b0) ? init_rhf_os : dprioin_rhf_os; assign cram_rlf_os = (dpriodisable !== 1'b0) ? init_rlf_os : dprioin_rlf_os; assign cram_rd2a_res = (dpriodisable !== 1'b0) ? init_rd2a_res : dprioin_rd2a_res; assign cram_rrect_adj = (dpriodisable !== 1'b0) ? init_rrect_adj : dprioin_rrect_adj; assign cram_rrgen_bw = (dpriodisable !== 1'b0) ? init_rrgen_bw : dprioin_rrgen_bw; // PMA Per Channel RX Control Register 16 for Channel 0 assign cram_radce_hflck = (dpriodisable !== 1'b0) ? init_radce_hflck : dprioin_radce_hflck; assign cram_reserved_0_TB51 = (dpriodisable !== 1'b0) ? init_reserved_0_TB51 : dprioin_reserved_0_TB51; // PMA Per Channel RX Control Register 17 for Channel 0 assign cram_radce_lflck = (dpriodisable !== 1'b0) ? init_radce_lflck : dprioin_radce_lflck; assign cram_reserved_0_TB52 = (dpriodisable !== 1'b0) ? init_reserved_0_TB52 : dprioin_reserved_0_TB52; // PMA Per Channel RX Control Register 18 for Channel 0 assign cram_radce_digital = (dpriodisable !== 1'b0) ? init_radce_digital : dprioin_radce_digital; assign cram_reserved_0_TB53 = (dpriodisable !== 1'b0) ? init_reserved_0_TB53 : dprioin_reserved_0_TB53; // Extra assign cram_rlpbk = (dpriodisable !== 1'b0) ? init_rlpbk : dprioin_rlpbk; assign cram_rrevlb_sw = (dpriodisable !== 1'b0) ? init_rrevlb_sw : dprioin_rrevlb_sw; assign cram_rrx_s_lpbk = (dpriodisable !== 1'b0) ? init_rrx_s_lpbk : dprioin_rrx_s_lpbk; // Function function [8*`STRATIXIV_HSSI_RX_PMA_ALPHA_TOLOWER_WORD_LENGTH:1] alpha_tolower; input [8*`STRATIXIV_HSSI_RX_PMA_ALPHA_TOLOWER_WORD_LENGTH:1] input_string; reg [8*`STRATIXIV_HSSI_RX_PMA_ALPHA_TOLOWER_WORD_LENGTH:1] return_string; reg [8*`STRATIXIV_HSSI_RX_PMA_ALPHA_TOLOWER_WORD_LENGTH:1] reg_string; reg [8:1] tmp; reg [8:1] conv_char; integer byte_count; begin reg_string = input_string; for (byte_count = `STRATIXIV_HSSI_RX_PMA_ALPHA_TOLOWER_WORD_LENGTH; byte_count >= 1; byte_count = byte_count - 1) begin tmp = reg_string[8*`STRATIXIV_HSSI_RX_PMA_ALPHA_TOLOWER_WORD_LENGTH:(8*(`STRATIXIV_HSSI_RX_PMA_ALPHA_TOLOWER_WORD_LENGTH-1)+1)]; reg_string = reg_string << 8; if ((tmp >= 65) && (tmp <= 90)) // ASCII number of 'A' is 65, 'Z' is 90 begin conv_char = tmp + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set return_string = {return_string, conv_char}; end else return_string = {return_string, tmp}; end alpha_tolower = return_string; end endfunction // end function initial begin // RX PMA control register 1 init_rrx_term_sel = 3'b000; init_rrx_vtt = (alpha_tolower(common_mode) == "0.82v" ? 3'b010 : alpha_tolower(common_mode) == "tristate" ? 3'b100 : alpha_tolower(common_mode) == "1.1v" ? 3'b001 : 3'b000); init_rrx_s_rdlpbk = (alpha_tolower(send_direct_reverse_serial_loopback) == "pre-cdr") ? 1'b1 : 1'b0; init_rrx_bit_dc = (eq_dc_gain == 3 ? 4'b0001 : eq_dc_gain == 6 ? 4'b0011 : eq_dc_gain == 9 ? 4'b0111 : eq_dc_gain == 12 ? 4'b1111 : 4'b0000); init_rrx_lst = low_speed_test_select; // RX PMA control register 2 init_rrxurstpma = 1'b0; init_rrx_test = 1'b0; init_rrx_sd_force = (force_signal_detect == "true") ? 1'b1 : 1'b0; init_rrx_oc = offset_cancellation; init_rrx_oc_en = 1'b0; init_rrx_sdlv = 4'b0000; // RX PMA control register 3 init_reserved_0_TB38 = 3'b000; init_rpowdnr = 1'b0; init_rrx_ib_pdb = 1'b0; init_rurx_pdb = 1'b0; init_rrx_oc_calpd = 1'b0; init_rrx_sd_off = signal_detect_loss_threshold; init_rrx_sd_on = signal_detect_hysteresis_valid_threshold; // RX PMA control register 12 init_reqv_set = eqv_ctrl; init_reqd_set = eqd_ctrl; init_reqc_set = eqc_ctrl; init_reqb_set = eqb_ctrl; init_reqa_set = eqa_ctrl; init_reserved_0_TB47 = 1'b0; // RX PMA Control Register 10 init_rppmsel = ppmselect; // extra init_rpma_doublewidth_rx = (deserialization_factor == 16 || deserialization_factor == 20) ? 1'b1 : 1'b0; //rdeser_div2_init init_rpmadwidth_rx = (deserialization_factor == 10 || deserialization_factor == 20) ? 1'b1 : 1'b0; //rdeser_div5_init init_rlpbk = (alpha_tolower(send_direct_reverse_serial_loopback) == "post-cdr") ? 1'b1 : 1'b0; init_rrevlb_sw = init_rlpbk; init_rrx_s_lpbk = (allow_serial_loopback == "true" ? 1'b1 : 1'b0); end // --------------------------------------------------------------------------- // New DPRIO End // --------------------------------------------------------------------------- // --------------------------------------------------------------------------- // Model Implementation Begin - // --------------------------------------------------------------------------- // SIMULATION_ONLY_PARAMETERS_BEGIN parameter PARAM_DELAY = 0; // SIMULATION_ONLY_PARAMETERS_END // --------------------------------------------------------------------------- // Model / Submodule Instantiations - // --------------------------------------------------------------------------- // --------------------------------------------------------------------------- // INPUT FILTERING // --------------------------------------------------------------------------- wire adcepowerdn_in; wire adcereset_in; wire adcestandby_in; wire datain_in; assign adcepowerdn_in = (adcepowerdn === 1'b1) ? 1'b0 : 1'b1; assign adcereset_in = (adcereset === 1'b1) ? 1'b0 : 1'b1; assign adcestandby_in = (adcestandby === 1'b1) ? 1'b0 : 1'b1; assign datain_in = (datain === 1'b1 || datain === 1'b0) ? datain : 1'b0; //prevent x/z propagate to gate netlist // *************************************************************************** // -- uses only *_cram * // -- should NOT use parameters nor *_dprioin * // *************************************************************************** // supply wires common to modules wire vcce; wire vssex; assign vcce = 1'b1; assign vssex = 1'b0; // forward declarations // rx output wires wire rx_eqout_n; wire rx_eqout_p; // input wires for c_adce wire xadce_atb0; wire xadce_atb1; wire xadce_atben; wire xadce_fixed_clk; wire xadce_lock_lf_ovd; wire xadce_rdfe_en; wire xadce_vbn; wire radce_adapt; wire [9:0] radce_digital; wire [14:0] radce_hflck; wire [14:0] radce_lflck; wire [3:0] rclkdiv; wire [1:0] rd2a_res; wire [1:0] rdc_freq; wire [1:0] rf_hpf; wire [1:0] rf_lpf; wire [3:0] rhf_os; wire [2:0] rhyst_hf; wire [2:0] rhyst_lf; wire [3:0] rlf_os; wire [1:0] rrect_adj; wire [1:0] rrgen_bw; wire [2:0] rrgen_set; wire [2:0] rrgen_vod; wire [1:0] rseq_sel; // supply wires for adce supply1 vccehxqyx; supply1 vccerxqyx; supply0 vssexqyx; // output wires wire xadce_adapt_done; wire [23:0] xadce_atbsel; wire [5:0] xadce_eqctrlout; wire xadce_fine_d2aout; wire xadce_hf_adapt_done; wire xadce_hf_clk; wire xadce_hfclk_macro; wire xadce_hfmac_cnt0_nclr; wire xadce_hfmac_cnt2_nclr; wire xadce_ibrgen1; wire xadce_ibrgen2; wire xadce_lf_adapt_done; wire xadce_lf_clk; wire xadce_lfclk_macro; wire xadce_lfmac_cnt0_nclr; wire xadce_lfmac_cnt2_nclr; wire [5:0] xadce_rgenctrlout; wire xadce_tmxselan; wire xadce_tmxselbn; wire xadce_tmxselcn; wire xadce_tmxseldn; wire xadce_tmxselvn; wire xadce_updnn_hf; wire xadce_updnn_lf; wire eqa_ctrl_wire; wire eqb_ctrl_wire; wire eqc_ctrl_wire; wire eqd_ctrl_wire; wire eqv_ctrl_wire; // inout wire atb_0; wire atb_1; wire xadce_ib50u_c; wire xadce_ib50u_t; wire xadce_rxn; wire xadce_rxp; wire xadce_vctl_quiet; stratixiv_hssi_pma_c_adce xadce (.adapt_capture(adaptcapture), .atben(xadce_atben), .atbsel(xadce_atbsel), .eqa_set(cram_reqa_set), .eqb_set(cram_reqb_set), .eqc_set(cram_reqc_set), .eqd_set(cram_reqd_set), .eqin_n(rx_eqout_n), .eqin_p(rx_eqout_p), .eqv_set(cram_reqv_set), .fixed_clk(xadce_fixed_clk), .lock_lf_ovd(xadce_lock_lf_ovd), .lst(cram_rrx_lst), .radce_adapt(radce_adapt), .radce_digital(radce_digital), .radce_hflck(radce_hflck), .radce_lflck(radce_lflck), .radce_pdb(adcepowerdn_in) , .radce_rstb(adcereset_in), .radce_vod_int(), .radce_vod_lsb(), .rbit_dc(vssex), .rclkdiv(rclkdiv), .rd2a_res(rd2a_res), .rdc_freq(rdc_freq), .rdfe_en(xadce_rdfe_en), .rf_hpf(rf_hpf), .rf_lpf(rf_lpf), .rhf_os(rhf_os), .rhyst_hf(rhyst_hf), .rhyst_lf(rhyst_lf), .rlf_os(rlf_os), .rrect_adj(rrect_adj), .rrgen_bw(rrgen_bw), .rrgen_set(rrgen_set), .rrgen_vod(rrgen_vod), .rseq_sel(rseq_sel), .standby(adcestandby_in), .vbn(xadce_vbn), .atb0(xadce_atb0), .atb1(xadce_atb1), .atb_0(atb_0), .atb_1(atb_1), .ib50u_c(xadce_ib50u_c), .ib50u_t(xadce_ib50u_t), .outeqn(xadce_rxn), .outeqp(xadce_rxp), .vccehxqyx(vccehxqyx), .vccerxqyx(vccerxqyx), .vctl_quiet(xadce_vctl_quiet), .vssexqyx(vssexqyx), .adapt_done(xadce_adapt_done), .e_clk(xadce_hf_clk), .eqa_ctrl(eqa_ctrl_wire), .eqb_ctrl(eqb_ctrl_wire), .eqc_ctrl(eqc_ctrl_wire), .eqctrlout(xadce_eqctrlout), .eqd_ctrl(eqd_ctrl_wire), .eqv_ctrl(eqv_ctrl_wire), .fine_d2aout(xadce_fine_d2aout), .hf_adapt_done(xadce_hf_adapt_done), .hfclk_macro(xadce_hfclk_macro), .hfmac_cnt0_nclr(xadce_hfmac_cnt0_nclr), .hfmac_cnt2_nclr(xadce_hfmac_cnt2_nclr), .ibrgen1(xadce_ibrgen1), .ibrgen2(xadce_ibrgen2), .lf_adapt_done(xadce_lf_adapt_done), .lfclk_macro(xadce_lfclk_macro), .lfmac_cnt0_nclr(xadce_lfmac_cnt0_nclr), .lfmac_cnt2_nclr(xadce_lfmac_cnt2_nclr), .r_clk(xadce_lf_clk), .rgenctrlout(xadce_rgenctrlout), .tmxselan(xadce_tmxselan), .tmxselbn(xadce_tmxselbn), .tmxselcn(xadce_tmxselcn), .tmxseldn(xadce_tmxseldn), .tmxselvn(xadce_tmxselvn), .updnn_hf(xadce_updnn_hf), .updnn_lf(xadce_updnn_lf) ); assign adaptdone = xadce_adapt_done; // input wires for c_rx wire [5:0] xrx_atbsel; wire [3:0] ibp50u; wire [1:0] ibc50u; wire [1:0] ibp150u; wire lpbkn; wire lpbkp; wire xrx_refclk; wire rs_lpbk; wire rx_n; wire [3:0] rx_50; wire xrx_pdb; wire [2:0] rrx_term; wire rrx_test; wire xrx_testclk; wire xrx_oc_calpd; wire xrx_ac_mode; wire xrx_bsmode; wire xrx_bsrxn_in; wire xrx_bsrxp_in; wire xrx_mem_init; wire xrx_pd2_term; wire xrx_pdb_clk; wire xrx_pdbh_term; wire xrx_rstn; wire xrx_pdshft_clk; wire [1:0] xrx_slew; // output wires wire analog_sd_icd; wire analog_sd_sw; wire analog_sd; wire bsrxn_out; wire bsrxp_out; wire cdr_rxn; wire cdr_rxp; wire rx_pd2; wire rx_pd_rxclk_term; wire rx_pdbh_rx; wire rx_pdbh_rxclk_term; wire rx_rlpbkp; // to lpbk_mux wire rx_rlpbkn; // to lpbk_mux wire rx_rlpbkp_far; wire rx_rlpbkn_far; wire rx_sd_cpon; wire rx_sd_cpop; wire rx_rxbuf_ibias; wire sd_cdr; // connect inputs assign lpbkp = (seriallpbkin === 1'b0 || seriallpbkin === 1'b1) ? seriallpbkin : 1'b0; //filtering X/Z assign rs_lpbk = (cram_rrx_s_lpbk == 1'b0) ? 1'b0 : seriallpbken; assign rx_n = ~datain_in; assign xrx_refclk = 1'b0; // for now assign xrx_testclk = 1'b0; // for now assign xrx_pdb = (powerdn === 1'b1) ? 1'b0 : 1'b1; assign rrx_test = 1'b0; // for now : need parameter ? // c_rx instance stratixiv_hssi_pma_c_rx xrx ( .ac_mode(xrx_ac_mode), .atbsel(xrx_atbsel), .bsmode(xrx_bsmode), .bsrxn_in(xrx_bsrxn_in), .bsrxp_in(xrx_bsrxp_in), .ck0_sigdet(~deserclock[3]), .eqa_ctrl(eqa_ctrl_wire), .eqb_ctrl(eqb_ctrl_wire), .eqc_ctrl(eqc_ctrl_wire), .eqd_ctrl(eqd_ctrl_wire), .lpbkn(lpbkn), .lpbkp(lpbkp), .mem_init(xrx_mem_init), .oc_calpd(xrx_oc_calpd), .oc_en(offsetcancellationen), .pd2_term(xrx_pd2_term), .pdb(xrx_pdb), .pdb_clk(xrx_pdb_clk), .pdbh_term(xrx_pdbh_term), .pdshft_clk(xrx_pdshft_clk), .rbit_dc(cram_rrx_bit_dc), .refclk(xrx_refclk), .rstn(xrx_rstn), .rx_b50(rx_50), .rx_oc(cram_rrx_oc), .rx_test(rrx_test), .rx_testclk(xrx_testclk), .s_lpbk(rs_lpbk), .s_rdlpbk(cram_rrx_s_rdlpbk), .sd_force(cram_rrx_sd_force), .sd_off(cram_rrx_sd_off), .sd_on(cram_rrx_sd_on), .sdlv(cram_rrx_sdlv), .slew(xrx_slew), .term(rrx_term), .vccehtxqyx(vcce), .vcce_la(vcce), .vcce_oa(vcce), .vssexqyx(vssexqyx), .vtt(cram_rrx_vtt[2:0]), .atb0_rx(atb_0), .atb1_rx(atb_1), .eqv_ctrl(eqv_ctrl_wire), .ibc50u(ibc50u), .ibp50u(ibp50u), .ibp150u(ibp150u), .inn(rx_n), .inp(datain_in), .analog_sd(analog_sd_icd), .bsrxn_out(bsrxn_out), .bsrxp_out(bsrxp_out), .inn3(rx_eqout_n), .inp3(rx_eqout_p), .pd2(rx_pd2), .pd_rxclk_term(rx_pd_rxclk_term), .pdbh_rx(rx_pdbh_rx), .pdbh_rxclk_term(rx_pdbh_rxclk_term), .rdlpbkn(rx_rlpbkn), // loopback to TX thro' mux .rdlpbkn_far(rx_rlpbkn_far), .rdlpbkp(rx_rlpbkp), // loopback to TX thro' mux .rdlpbkp_far(rx_rlpbkp_far), .rxbuf_ibias(rx_rxbuf_ibias), .rxn(cdr_rxn), // to top .rxp(cdr_rxp), // to top .sd_cdr(sd_cdr), // to cdr .sd_cpon(rx_sd_cpon), .sd_cpop(rx_sd_cpop) ); // outputs from the c_rx assign dataout = cdr_rxp; assign signaldetect = analog_sd; `ifdef STRATIXIV_HSSI_USE_ICD_SD assign analog_sd = analog_sd_icd; `else assign analog_sd = analog_sd_sw; `endif // simplified signal detect model like S2GX - SW ---------------- // input wire sd_rx; wire sd_reset; // output reg signaldetect_reg; assign analog_sd_sw = signaldetect_reg; assign sd_rx = (rs_lpbk === 1'b1) ? seriallpbkin : datain; assign sd_reset = (powerdn === 1'b1 || rxpmareset === 1'b1) ? 1'b1 : 1'b0; initial begin signaldetect_reg = 1'b0; end always @ (sd_reset or sd_rx) begin if (sd_reset === 1'b1) signaldetect_reg <= 1'b0; else if (sd_rx === 1'b0 || sd_rx === 1'b1) signaldetect_reg <= 1'b1; else signaldetect_reg <= 1'b0; end // PPMDETECT MODULE // ppmdetect module input wires wire ppmdetect_hardreset_in; wire ppmdetect_pd_in; wire ppmdetect_ppmcntreset_in; wire ppmdetect_scanmode_in; wire ppmdetect_rforcehigh_in; wire ppmdetect_rforcelow_in; // output wires wire ppmdetect_freqlock_out; wire [6:0] ppmdetect_ppmcntlatch_out; // assign inputs assign ppmdetect_hardreset_in = (rxpmareset === 1'b1) ? 1'b0 : 1'b1; assign ppmdetect_pd_in = (powerdn === 1'b1) ? 1'b0 : 1'b1; stratixiv_hssi_pma_ppmdetect xppmdetect ( .fref(ppmdetectrefclk), .fvcobyn(ppmdetectdividedclk), .hard_reset(ppmdetect_hardreset_in), .pd(ppmdetect_pd_in), .ppmsel(cram_rppmsel), .ppm_cnt_reset(ppmdetect_ppmcntreset_in), .scan_mode(ppmdetect_scanmode_in), .rforcehigh(ppmdetect_rforcehigh_in), .rforcelow(ppmdetect_rforcelow_in), .freq_lock(ppmdetect_freqlock_out), .ppm_cnt_latch(ppmdetect_ppmcntlatch_out) ); // simplified freqlock behavior: // (1). Responding to rising edge of rxpll_lock with small counter; // (2). Responding to analogreset // (3). Not responding to loss of rxpll_lock // freqlock wire mrxpll_not_locked; reg mfreqlocked_reg; reg [3:0] mfreqlocked_cnt; wire signal_detect_reg_n; wire lck2refctl_freqlock; assign mrxpll_not_locked = (plllocked === 1'b1) ? 1'b0 : 1'b1; assign signal_detect_reg_n = ~analog_sd; initial begin mfreqlocked_reg = 1'b0; mfreqlocked_cnt = 4'b000; end always @ (posedge ppmdetectrefclk or posedge rxpmareset) begin if (rxpmareset === 1'b1) mfreqlocked_reg <= 1'b0; else if (mfreqlocked_cnt === 4'b1111) mfreqlocked_reg <= 1'b1; else mfreqlocked_reg <= 1'b0; end always @ (posedge ppmdetectrefclk or posedge mrxpll_not_locked or posedge signal_detect_reg_n) begin if (mrxpll_not_locked === 1'b1 || signal_detect_reg_n === 1'b1) mfreqlocked_cnt <= 4'b0000; else if (mfreqlocked_cnt !== 4'b1111) mfreqlocked_cnt <= mfreqlocked_cnt + 4'b0001; end `ifdef STRATIXIV_HSSI_USE_ICD_PPMDETECT assign lck2refctl_freqlock = ppmdetect_freqlock_out; `else assign lck2refctl_freqlock = mfreqlocked_reg; `endif // CDR // input wires for cdr wire ltd; wire ltr; reg devenout, devenbout; reg doddout, oddbout; reg doddx, oddbx; reg oe1, oeb1; reg oo1, oob1; reg oe2, oeb2; reg oo2, oob2; reg rxlpbp_int, rxlpbn_int; reg rxlpbdp_int, rxlpbdn_int; wire deven; wire devenb; wire dodd; wire doddb; wire cdr_pdb; wire ck0_pd; wire ck90_pd; wire ck180_pd; wire ck270_pd; wire clk90_slpbk; wire clk270_slpbk; wire lck2ref; wire pdbx; wire pe; wire rlbk; wire rstb_slpbk; wire rst_n; wire rstn2; wire rxpll_lock; wire rxlpbp, rxlpbn; wire rxlpbdp, rxlpbdn; // connect inputs assign cdr_pdb = (powerdn === 1'b1) ? 1'b0 : 1'b1; assign ck0_pd = deserclock[0]; assign ck90_pd = deserclock[1]; assign ck180_pd = deserclock[2]; assign ck270_pd = deserclock[3]; assign ltd = locktodata; assign ltr = locktoref; assign rlbk = cram_rlpbk; assign rst_n = (rxpmareset === 1'b1) ? 1'b0 : 1'b1; assign deven = recoverdatain[0]; assign dodd = recoverdatain[1]; assign devenb = ~recoverdatain[0]; assign doddb = ~recoverdatain[1]; // * * c_lck2refctl * * assign lck2ref = ~cdr_pdb ? 1'b1 : (~sd_cdr | ~lck2refctl_freqlock) ? 1'b1 : ( sd_cdr & lck2refctl_freqlock & ~plllocked & ~ignorephslck ) ? 1'b1 : ( sd_cdr & lck2refctl_freqlock & plllocked ) ? 1'b0 : 1'b0; assign rxpll_lock = ~lck2ref; // * * c_slpbk * * assign pdbx = cdr_pdb & rlbk; assign rstb_slpbk = pdbx & rst_n; assign clk90_slpbk = ~( ck90_pd & pdbx ); assign clk270_slpbk = ~( ck270_pd & pdbx ); assign rstn2 = pe & vssex ; assign pe = ~pdbx & rst_n & cram_rrx_s_rdlpbk; always @ ( posedge clk90_slpbk or negedge rstb_slpbk ) // xdff0 & xdff1 if ( rstb_slpbk == 1'b0 ) begin {devenout,devenbout} <= #(PARAM_DELAY) 2'b01; {doddx,oddbx} <= #(PARAM_DELAY) 2'b01; end else begin {devenout,devenbout} <= #(PARAM_DELAY) {deven,devenb}; {doddx,oddbx} <= #(PARAM_DELAY) {dodd,doddb}; end always @ ( posedge clk270_slpbk or negedge rstb_slpbk ) // xdff2 if ( rstb_slpbk == 1'b0 ) begin {doddout,oddbout} <= #(PARAM_DELAY) 2'b01; end else begin {doddout,oddbout} <= #(PARAM_DELAY) {doddx,oddbx}; end // xlatch_mux (used to be xpre_emp) always @ ( posedge clk270_slpbk or negedge rst_n ) // x1 if ( rst_n == 1'b0 ) begin {oe1,oeb1} <= #(PARAM_DELAY) 2'b01; end else begin {oe1,oeb1} <= #(PARAM_DELAY) {devenout,devenbout}; end always @ ( posedge clk90_slpbk or negedge rst_n ) // x12 if ( rst_n == 1'b0 ) begin {oo1,oob1} <= #(PARAM_DELAY) 2'b01; end else begin {oo1,oob1} <= #(PARAM_DELAY) {doddout,oddbout}; end always @ ( posedge clk270_slpbk or negedge pdbx ) // x4 if ( pdbx == 1'b0 ) begin {rxlpbp_int,rxlpbn_int} <= #(PARAM_DELAY) 2'b11; end else begin {rxlpbp_int,rxlpbn_int} <= #(PARAM_DELAY) {devenout,devenbout}; end always @ ( posedge clk90_slpbk or negedge pdbx ) // x8 if ( pdbx == 1'b0 ) begin {rxlpbp_int,rxlpbn_int} <= #(PARAM_DELAY) 2'b11; end else begin {rxlpbp_int,rxlpbn_int} <= #(PARAM_DELAY) {doddout,oddbout}; end always @ ( posedge clk90_slpbk or negedge pe ) // x5 if ( pe == 1'b0 ) begin {rxlpbdp_int,rxlpbdn_int} <= #(PARAM_DELAY) 2'b11; end else begin {rxlpbdp_int,rxlpbdn_int} <= #(PARAM_DELAY) {oe1,oeb1}; end always @ ( posedge clk270_slpbk or negedge pe ) // x9 if ( pe == 1'b0 ) begin {rxlpbdp_int,rxlpbdn_int} <= #(PARAM_DELAY) 2'b11; end else begin {rxlpbdp_int,rxlpbdn_int} <= #(PARAM_DELAY) {oo1,oob1}; end assign { rxlpbp, rxlpbn} = { rxlpbp_int, rxlpbn_int}; assign {rxlpbdp,rxlpbdn} = {rxlpbdp_int,rxlpbdn_int}; // outputs from the c_cdr assign locktorefout = lck2ref; assign revserialfdbkout = rxlpbp; ////////////////end cdr // output wires wire ncvondp; wire ncvopdp; wire rlpbkdn; wire rlpbkdp; wire rlpbkn; wire rlpbkp; wire ncvonp; wire ncvopp; stratixiv_hssi_pma_c_rlpbk_mux xrlpbk_mux ( .doddn(vssex), .doddp(vssex), .dodn(rxlpbdn), .dodp(rxlpbdp), .don(rxlpbn), .don_pre(vssex), .dop(rxlpbp), .dop_pre(vssex), .drxn(rx_rlpbkn), .drxp(rx_rlpbkp), .sel(cram_rrevlb_sw), .vcce_la(vcce), .vssex(vssex), .voddn(ncvondp), .voddp(ncvopdp), .vodn(rlpbkdn), .vodp(rlpbkdp), .von(rlpbkn), .von_pre(ncvonp), .vop(rlpbkp), .vop_pre(ncvopp) ); // outputs from the lpbk_mux assign reverselpbkout = cdr_rxp; // input wires for the deserializer wire xdeser_clk90_in; wire xdeser_pdb_in; wire xdeser_rst_n; wire xdeser_pcie_sw; wire rdynamic_sw; wire [3:0] rfast_sd; // output wires wire xdeser_clkdivrx_out; wire [19:0] xdeser_dout_out; wire xdeser_fsd_out; wire xdeser_pcieo_out; wire xdeser_rtest_fastsd; // 10g output wires wire xdeser_10g_clk_divrx; wire [63:0] xdeser_10g_dout; // connect the inputs assign xdeser_clk90_in = (deserialization_factor <= 20) ? ~deserclock[1] : 1'b0; assign xdeser_pdb_in = (powerdn === 1'b1) ? 1'b0 : 1'b1; assign xdeser_rst_n = (rxpmareset === 1'b1) ? 1'b0 : 1'b1; assign xdeser_pcie_sw = 1'b0; // for now assign rdynamic_sw = 1'b0; // for now; // generate blocks (for 10g only) generate if (deserialization_factor > 20) begin // input wires for the 10g deserializer wire xdeser_10g_pdb; wire xdeser_10g_rst_n; assign xdeser_10g_pdb = (powerdn === 1'b1) ? 1'b0 : 1'b1; assign xdeser_10g_rst_n = (rxpmareset === 1'b1) ? 1'b0 : 1'b1; stratixiv_hssi_pma_c_deser_10g xdeser_10g ( .clk90b(~deserclock[1]), .deser_pdb(xdeser_10g_pdb), .deven(recoverdatain[0]), .devenb(~recoverdatain[0]), .dodd(recoverdatain[1]), .doddb(~recoverdatain[1]), .rst_n(xdeser_10g_rst_n), .vcce_la(vcce), .vssexqyx(vssexqyx), .clk_divrx(xdeser_10g_clk_divrx), .dout(xdeser_10g_dout) ); end endgenerate stratixiv_hssi_pma_c_deser xdeser ( .clk90b(xdeser_clk90_in), .deser_div2(cram_rpma_doublewidth_rx), .deser_div5(cram_rpmadwidth_rx), .deser_pdb(xdeser_pdb_in), .deven(deven), // from top .devenb(devenb), // from top .dodd(dodd), // from top .doddb(doddb), // from top .pcie_sw(xdeser_pcie_sw), .rdynamic_sw(rdynamic_sw), .rfast_sd(rfast_sd), .rst_n(xdeser_rst_n), .rtest_fastsd(xdeser_rtest_fastsd), .rxinn(rx_rlpbkn), // from c_rx .rxinp(rx_rlpbkp), // from c_rx .vcce_la(vcce), .vssexqyx(vssexqyx), .clk_divrx(xdeser_clkdivrx_out), .dout(xdeser_dout_out), .fsd(xdeser_fsd_out), .pcieo(xdeser_pcieo_out) ); reg param_use_pma_direct; initial begin param_use_pma_direct = (use_pma_direct == "true") ? 1'b1 : 1'b0; end // outputs from the deserializer assign clockout = (allow_vco_bypass == 0 ? (deserialization_factor <= 20 ? xdeser_clkdivrx_out : xdeser_10g_clk_divrx): allow_vco_bypass == 1 ? (!ppmdetectrefclk) : allow_vco_bypass == 2 ? ppmdetectdividedclk : xdeser_clkdivrx_out); assign recoverdataout[19:0] = (param_use_pma_direct == 1'b1 && deserialization_factor == 16) ? ({{4{1'bz}}, xdeser_dout_out[17:10], xdeser_dout_out[7:0]}) : (deserialization_factor <= 20) ? xdeser_dout_out : xdeser_10g_dout[19:0]; assign recoverdataout[63:20] = (deserialization_factor <= 20) ? ({44{1'bz}}) : xdeser_10g_dout[63:20]; assign dataoutfull = xdeser_dout_out; // drive 0 on analogtestbus assign analogtestbus = 8'b0; // --------------------------------------------------------------------------- // TIMING -- Tco/Tsu/Thold // --------------------------------------------------------------------------- specify (posedge adaptcapture => (adaptdone +: xadce_adapt_done)) = (0, 0); endspecify endmodule `timescale 1 ns / 1 ps module stratixiv_hssi_pcs_reset (hard_reset, clk_2_b, refclk_b_in, scan_mode, rxpcs_rst, txpcs_rst, rxrst_int, txrst_int); input hard_reset; input clk_2_b; input refclk_b_in; input scan_mode; input rxpcs_rst; input txpcs_rst; output rxrst_int; output txrst_int; reg txrst_sync1, txrst_sync2; reg rxrst_sync1, rxrst_sync2; wire txrst_int, rxrst_int; initial begin txrst_sync1 = 1'b0; txrst_sync2 = 1'b0; rxrst_sync1 = 1'b0; rxrst_sync2 = 1'b0; end always @(posedge hard_reset or posedge clk_2_b) begin if (hard_reset) begin rxrst_sync2 <= 1'b1; rxrst_sync1 <= 1'b1; end else begin rxrst_sync2 <= #1 rxrst_sync1; rxrst_sync1 <= rxpcs_rst; end end always @(posedge hard_reset or posedge refclk_b_in) begin if (hard_reset) begin txrst_sync2 <= 1'b1; txrst_sync1 <= 1'b1; end else begin txrst_sync2 <= #1 txrst_sync1; txrst_sync1 <= txpcs_rst; end end // 06-14-02 BT Changed SCAN_SHIFT signal to SCAN_MODE //assign rxrst_int = !SCAN_SHIFT & rxrst_sync2; //assign txrst_int = !SCAN_SHIFT & txrst_sync2; assign rxrst_int = !scan_mode & rxrst_sync2; assign txrst_int = !scan_mode & txrst_sync2; endmodule `timescale 1 ps / 1 ps module stratixiv_hssi_digi_chnl_hip_spt ( rhip_ena, pcs_rxd_ch, pcs_rxvalid, pcs_rxelecidle, pcs_rxstatus_ch, pcs_phystatus, txpma_local_clk, txd_ch, hip_txd_ch, txdetectrxloopback, hip_txdetectrxloopback, rxpolarity, hip_rxpolarity, powerdown_ch, hip_powerdown_ch, txdeemph, hip_txdeemph, txmargin_ch, hip_txmargin_ch, eidleinfersel_ch, hip_eidleinfersel_ch, rate, hip_rate, hip_txelecidle, rxd_ch, hip_rxd_ch, rxvalid, hip_rxvalid, rxelecidle, hip_rxelecidle, rxstatus_ch, hip_rxstatus_ch, phystatus, hip_phystatus, hip_tx_clk, pcs_txd_ch, pcs_txdetectrxloopback, pcs_rxpolarity, pcs_powerdown_ch, pcs_txdeemph, pcs_txmargin_ch, pcs_eidleinfersel_ch, pcs_rate ); input rhip_ena; input [8:0] pcs_rxd_ch; input pcs_rxvalid; input pcs_rxelecidle; input [2:0] pcs_rxstatus_ch; input pcs_phystatus; input txpma_local_clk; input [10:0] txd_ch; input [9:0] hip_txd_ch; input txdetectrxloopback; input hip_txdetectrxloopback; input rxpolarity; input hip_rxpolarity; input [1:0] powerdown_ch; input [1:0] hip_powerdown_ch; input txdeemph; input hip_txdeemph; input [2:0] txmargin_ch; input [2:0] hip_txmargin_ch; input [2:0] eidleinfersel_ch; input [2:0] hip_eidleinfersel_ch; input rate; input hip_rate; input hip_txelecidle; output [8:0] rxd_ch; output [8:0] hip_rxd_ch; output rxvalid; output hip_rxvalid; output rxelecidle; output hip_rxelecidle; output [2:0] rxstatus_ch; output [2:0] hip_rxstatus_ch; output phystatus; output hip_phystatus; output hip_tx_clk; output [10:0] pcs_txd_ch; output pcs_txdetectrxloopback; output pcs_rxpolarity; output [1:0] pcs_powerdown_ch; output pcs_txdeemph; output [2:0] pcs_txmargin_ch; output [2:0] pcs_eidleinfersel_ch; output pcs_rate; wire [8:0] pcs_rxd_ch; wire [2:0] pcs_rxstatus_ch; wire [10:0] txd_ch; wire [9:0] hip_txd_ch; wire [1:0] powerdown_ch; wire [1:0] hip_powerdown_ch; wire [2:0] txmargin_ch; wire [2:0] hip_txmargin_ch; wire [2:0] eidleinfersel_ch; wire [2:0] hip_eidleinfersel_ch; wire [8:0] rxd_ch; wire [8:0] hip_rxd_ch; wire [2:0] rxstatus_ch; wire [2:0] hip_rxstatus_ch; wire [10:0] pcs_txd_ch; wire [1:0] pcs_powerdown_ch; wire [2:0] pcs_txmargin_ch; wire [2:0] pcs_eidleinfersel_ch; //// SECTION for SPLIT signals //// =============================== //// // MUX/SPLIT #5,6,7,8 in Excel spreadsheet assign rxd_ch = pcs_rxd_ch; assign hip_rxd_ch = rhip_ena ? pcs_rxd_ch : 9'b000000000; // MUX/SPLIT #16 in Excel spreadsheet assign rxvalid = pcs_rxvalid; assign hip_rxvalid = rhip_ena ? pcs_rxvalid : 1'b0; // MUX/SPLIT #17 in Excel spreadsheet assign rxelecidle = pcs_rxelecidle; assign hip_rxelecidle = rhip_ena ? pcs_rxelecidle : 1'b1; // MUX/SPLIT #18,19,20,21 in Excel spreadsheet assign rxstatus_ch = pcs_rxstatus_ch; assign hip_rxstatus_ch = rhip_ena ? pcs_rxstatus_ch : 3'b000; // MUX/SPLIT #22 in Excel spreadsheet assign phystatus = pcs_phystatus; assign hip_phystatus = rhip_ena ? pcs_phystatus : 1'b0; assign hip_tx_clk = txpma_local_clk; //// SECTION for MUX signals //// =============================== //// // MUX/SPLIT #1,2,3,4 in Excel spreadsheet assign pcs_txd_ch = rhip_ena ? {hip_txelecidle, hip_txd_ch} : txd_ch; // MUX/SPLIT #10 in Excel spreadsheet assign pcs_txdetectrxloopback = rhip_ena ? hip_txdetectrxloopback : txdetectrxloopback; // MUX/SPLIT #11 in Excel spreadsheet assign pcs_rxpolarity = rhip_ena ? hip_rxpolarity : rxpolarity; // MUX/SPLIT #12,13,14,15 in Excel spreadsheet assign pcs_powerdown_ch = rhip_ena ? hip_powerdown_ch : powerdown_ch; // MUX/SPLIT #23 in Excel spreadsheet assign pcs_txdeemph = rhip_ena ? hip_txdeemph : txdeemph; // MUX/SPLIT #24,25,26,27 in Excel spreadsheet assign pcs_txmargin_ch = rhip_ena ? hip_txmargin_ch : txmargin_ch; // MUX/SPLIT #28,29,30,31 in Excel spreadsheet assign pcs_eidleinfersel_ch = rhip_ena ? hip_eidleinfersel_ch : eidleinfersel_ch; // MUX/SPLIT #32 in Excel spreadsheet assign pcs_rate = rhip_ena ? hip_rate : rate; endmodule `timescale 1 ns / 1 ps module stratixiv_hssi_phystatus_generator_fsm ( // General signals clk, reset_n, //CRAM phystat_ena, // OR of rtx_pipe_enable and rrx_pipe_enable rphystatus_rst_toggle, // no toggle (gen 2) = 0, toggle (option for gen 1) = 1 // PLD Interface powerdown, // power state control phystatus, // communicate completion of power state transitions, receiver // detection, rate change rindv_rx, rmaster_rx, rmaster_up_rx, // Auto Negotiation Module speed_change, // asserted when signaling rate change between Gen 1 and Gen 2 speed_change_centrl, speed_change_quad_up, speed_change_quad_down, // RX PIPE Interface // p1_sync, // PMA interface // TX PMA rx_detect_valid, // rx_detect_bypass = 0 : Validation of rx_found: // synchronized at pipe_interface_top level // rx_detect_bypass = 1 : delayed version of txdetectrx // RX PMA power_state_transition_done, // asserted when successful power state transition occurs power_state_transition_done_ena, // validates power_state_transition_done, currently tied to 0 // Latched Power State Signals p1, // P1 power state from TX PIPE interface // Internal Power State Done Generator internal_done // faked successful power state transition generated by internal // power state transition done module ); //******************************************************************************** // INCLUDE STATEMENTS //******************************************************************************** //******************************************************************************** // I/O SIGNALS //******************************************************************************** // General signals input clk; input reset_n; // CRAM input phystat_ena; input rphystatus_rst_toggle; // PLD Interface input [1:0] powerdown; output phystatus; input rindv_rx; // Select between XAUI mode or indiv channel mode input rmaster_rx; // New bundle mode MDIO, selects master quad input rmaster_up_rx; // New bundle mode MDIO, selects master quad // Auto Negotiation Module input speed_change; input speed_change_centrl; input speed_change_quad_up; input speed_change_quad_down; // RX PIPE Interface //output p1_sync; // PMA interface // TX PMA input rx_detect_valid; // RX PMA input power_state_transition_done; input power_state_transition_done_ena; // Latched Power state signals input p1; // longer recovery time (64 us max) latency // Internal Power State Done Generator input internal_done; //******************************************************************************** // PARAMETERS //******************************************************************************** //******************************************************************************** // DECLARATIONS //******************************************************************************** //reg phystatus; // select between PMA done and internally generated done wire done; reg pre_power_state_transition_done_sync; reg power_state_transition_done_sync; reg power_state_transition_done_sync_reg; // Reset condition reg reset_phystatus; // State transition reg state_transition_phystatus; // Speed Negotiation reg speed_change_reg; reg speed_change_sync; reg speed_change_sync_reg; reg speed_change_phystatus; // Receiver Detection //reg p1_reg; // synchronize from tx clk domain to rx clk domain //reg p1_sync; reg rx_detect_valid_reg; // Edge detection of receiver detection status signal reg rx_detect_valid_phystatus; // P2 exit detection wire decode_p2; reg decode_p2_reg; reg decode_p2_reg1; reg phystatus_high_sel; reg phystatus_high_sel_reg; // Reset reg phystatus_toggle_sel; reg phystatus_toggle_sel_reg; reg pre_phystatus; wire speed_change_local; reg speed_change_centrl_del1; reg speed_change_centrl_del2; //******************************************************************************** // ASSIGN STATEMENTS //******************************************************************************** // Move to PLD interface assign phystatus = (~decode_p2 && decode_p2_reg1)? 1'b1: pre_phystatus; //assign phystatus= pre_phystatus; assign done = power_state_transition_done_ena? (power_state_transition_done_sync && ! power_state_transition_done_sync_reg): internal_done; assign decode_p2 = (powerdown == 2'b11)? phystat_ena: 1'b0; //******************************************************************************** // SUBMODULE INSTANTIATIONS //******************************************************************************** //******************************************************************************** // MAIN CODE //******************************************************************************** // Reset phystatus generation // Phystatus is asserted during reset and then the successful 'transition' into P1 is signal by the assertion // phystatus for 1 cycle. Unlike regular operation, the first entry into P1 is not indicated by a 'done' signal // The assertion of phystatus occurs 4 cycles after reset is released always @ (reset_n) begin if (~reset_n) reset_phystatus = 1'b1; else reset_phystatus = 1'b0; end always @ (reset_n or rphystatus_rst_toggle or done or phystatus_toggle_sel_reg) begin if (~reset_n) phystatus_toggle_sel = 1'b1; else if (rphystatus_rst_toggle | done) phystatus_toggle_sel = 1'b0; else phystatus_toggle_sel = phystatus_toggle_sel_reg; end always @ (posedge clk or negedge reset_n) begin if (~reset_n) begin phystatus_toggle_sel_reg <= #1 1'b1; phystatus_high_sel_reg <= #1 1'b1; end else begin phystatus_toggle_sel_reg <= #1 phystatus_toggle_sel; phystatus_high_sel_reg <= #1 phystatus_high_sel; end end // State transition: sync PMA signal to local clk. Currently not being used // State transition: Internal done generator indicates that there was a successful state transition. // Illegal transitions have been taken into account by the previous module. always @ (posedge clk or negedge reset_n) begin if (!reset_n) begin pre_power_state_transition_done_sync <= #1 1'b0; power_state_transition_done_sync <= #1 1'b0; power_state_transition_done_sync_reg <= #1 1'b0; end else begin pre_power_state_transition_done_sync <= #1 power_state_transition_done; power_state_transition_done_sync <= #1 pre_power_state_transition_done_sync; power_state_transition_done_sync_reg <= #1 power_state_transition_done_sync; end end always @ (reset_n or done) begin if (~reset_n) state_transition_phystatus = 1'b0; else if (done) state_transition_phystatus = 1'b1; else state_transition_phystatus = 1'b0; end always @ (posedge clk or negedge reset_n) begin if (!reset_n) begin speed_change_centrl_del1 <= #1 1'b0; speed_change_centrl_del2 <= #1 1'b0; end else begin speed_change_centrl_del1 <= #1 speed_change_centrl; speed_change_centrl_del2 <= #1 speed_change_centrl_del1; end end // always @ (posedge clk or negedge reset_n) assign speed_change_local = rmaster_rx ? (rindv_rx ? speed_change : speed_change_centrl_del2) : (rmaster_up_rx ? speed_change_quad_up : speed_change_quad_down); // Speed Negotiation always @ (posedge clk or negedge reset_n) begin if (!reset_n) begin speed_change_reg <= #1 1'b0; speed_change_sync <= #1 1'b0; speed_change_sync_reg <= #1 1'b0; end else begin speed_change_reg <= #1 speed_change_local; speed_change_sync <= #1 speed_change_reg; speed_change_sync_reg <= #1 speed_change_sync; end end always @ (reset_n or speed_change_sync or speed_change_sync_reg) begin if (~reset_n) speed_change_phystatus = 1'b0; else if (~speed_change_sync & speed_change_sync_reg) speed_change_phystatus = 1'b1; else speed_change_phystatus = 1'b0; end // Receiver Detection always @ (posedge clk or negedge reset_n) begin if (!reset_n) begin // p1_reg <= 1'b0; // p1_sync <= 1'b0; rx_detect_valid_reg <= #1 1'b0; // rx_detect_valid_phystatus <= 1'b0; end else begin // p1_reg <= p1; // p1_sync <= p1_reg; rx_detect_valid_reg <= #1 rx_detect_valid; // rx_detect_valid_phystatus <= p1_sync && rx_detect_valid && !rx_detect_valid_reg; end end always @ (reset_n or /*p1_sync*/ p1 or rx_detect_valid or rx_detect_valid_reg) begin if (~reset_n) rx_detect_valid_phystatus = 1'b0; // else if (p1_sync && rx_detect_valid && !rx_detect_valid_reg) else if (p1 && rx_detect_valid && !rx_detect_valid_reg) rx_detect_valid_phystatus = 1'b1; else rx_detect_valid_phystatus = 1'b0; end // P2 state exit Detection always @ (posedge clk or negedge reset_n) begin if (!reset_n) begin decode_p2_reg <= #1 1'b0; decode_p2_reg1 <= #1 1'b0; end else begin decode_p2_reg <= #1 decode_p2; decode_p2_reg1 <= #1 decode_p2_reg; end end always @ (reset_n or decode_p2 or decode_p2_reg or phystatus_high_sel_reg or done) begin if (~reset_n) phystatus_high_sel = 1'b0; else if (~decode_p2 && decode_p2_reg) phystatus_high_sel = 1'b1; else if (done) phystatus_high_sel = 1'b0; else phystatus_high_sel = phystatus_high_sel_reg; end always @ (reset_n or phystatus_high_sel or reset_phystatus or state_transition_phystatus or rx_detect_valid_phystatus or phystatus_toggle_sel or speed_change_phystatus) begin if (~reset_n) begin pre_phystatus = 1'b1; end else begin if (phystatus_high_sel || reset_phystatus || state_transition_phystatus || rx_detect_valid_phystatus || phystatus_toggle_sel || speed_change_phystatus) pre_phystatus = 1'b1; else pre_phystatus = 1'b0; end end // always @ (reset_n or phystatus_high_sel or reset_phystatus or state_transition_phystatus or rx_detect_valid_phystatus... endmodule // phystatus_generator_fsm //IP Functional Simulation Model //VERSION_BEGIN 12.0 cbx_mgl 2012:05:31:20:09:47:SJ cbx_simgen 2012:05:31:20:08:35:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 // Copyright (C) 1991-2012 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // You may only use these simulation model output files for simulation // purposes and expressly not for synthesis or any other purposes (in which // event Altera disclaims all warranties of any kind). //synopsys translate_off //synthesis_resources = lut 53 oper_mux 1 stratixiv_hssi_phystatus_generator_fsm 1 `timescale 1 ps / 1 ps module stratixiv_hssi_phystatus_generator ( clk, latched_p0, latched_p0s, latched_p1, latched_p2, phystat_ena, phystatus, power_state_transition_done, power_state_transition_done_ena, powerdown, reset_n, rindv_rx, rmaster_rx, rmaster_up_rx, rphystatus_delay, rphystatus_rst_toggle, rx_detect_valid, speed_change, speed_change_centrl, speed_change_quad_down, speed_change_quad_up) /* synthesis synthesis_clearbox=1 */; input clk; input latched_p0; input latched_p0s; input latched_p1; input latched_p2; input phystat_ena; output phystatus; input power_state_transition_done; input power_state_transition_done_ena; input [1:0] powerdown; input reset_n; input rindv_rx; input rmaster_rx; input rmaster_up_rx; input [2:0] rphystatus_delay; input rphystatus_rst_toggle; input rx_detect_valid; input speed_change; input speed_change_centrl; input speed_change_quad_down; input speed_change_quad_up; reg nllOi21; reg nllOi22; reg nllOl19; reg nllOl20; reg nllOO17; reg nllOO18; reg nlO0l11; reg nlO0l12; reg nlO1i15; reg nlO1i16; reg nlO1O13; reg nlO1O14; reg nlOii10; reg nlOii9; reg nlOil7; reg nlOil8; reg nlOli5; reg nlOli6; reg nlOlO3; reg nlOlO4; reg nlOOl1; reg nlOOl2; reg ni0i; reg ni0l; reg ni1O; reg niii; wire wire_ni0O_CLRN; reg n00i; reg n00l; reg n00O; reg n01i; reg n01l; reg n01O; reg n0ii; reg n0il; reg n0iO; reg n0li; reg n0ll; reg n0lO; reg n0Ol; reg n0OO; reg n1lO; reg n1Ol; reg n1OO; reg ni1i; reg ni1l; reg niil; reg niiO; reg nili; reg nill; reg nilO; reg niOi; reg niOl; reg nl1i; reg niOO_clk_prev; wire wire_niOO_CLRN; wire wire_niOO_PRN; wire wire_n1Oi_o; wire wire_nl0O_phystatus; wire nlO0O; wire nlOiO; initial nllOi21 = 0; always @ ( posedge clk) nllOi21 <= nllOi22; event nllOi21_event; initial #1 ->nllOi21_event; always @(nllOi21_event) nllOi21 <= {1{1'b1}}; initial nllOi22 = 0; always @ ( posedge clk) nllOi22 <= nllOi21; initial nllOl19 = 0; always @ ( posedge clk) nllOl19 <= nllOl20; event nllOl19_event; initial #1 ->nllOl19_event; always @(nllOl19_event) nllOl19 <= {1{1'b1}}; initial nllOl20 = 0; always @ ( posedge clk) nllOl20 <= nllOl19; initial nllOO17 = 0; always @ ( posedge clk) nllOO17 <= nllOO18; event nllOO17_event; initial #1 ->nllOO17_event; always @(nllOO17_event) nllOO17 <= {1{1'b1}}; initial nllOO18 = 0; always @ ( posedge clk) nllOO18 <= nllOO17; initial nlO0l11 = 0; always @ ( posedge clk) nlO0l11 <= nlO0l12; event nlO0l11_event; initial #1 ->nlO0l11_event; always @(nlO0l11_event) nlO0l11 <= {1{1'b1}}; initial nlO0l12 = 0; always @ ( posedge clk) nlO0l12 <= nlO0l11; initial nlO1i15 = 0; always @ ( posedge clk) nlO1i15 <= nlO1i16; event nlO1i15_event; initial #1 ->nlO1i15_event; always @(nlO1i15_event) nlO1i15 <= {1{1'b1}}; initial nlO1i16 = 0; always @ ( posedge clk) nlO1i16 <= nlO1i15; initial nlO1O13 = 0; always @ ( posedge clk) nlO1O13 <= nlO1O14; event nlO1O13_event; initial #1 ->nlO1O13_event; always @(nlO1O13_event) nlO1O13 <= {1{1'b1}}; initial nlO1O14 = 0; always @ ( posedge clk) nlO1O14 <= nlO1O13; initial nlOii10 = 0; always @ ( posedge clk) nlOii10 <= nlOii9; initial nlOii9 = 0; always @ ( posedge clk) nlOii9 <= nlOii10; event nlOii9_event; initial #1 ->nlOii9_event; always @(nlOii9_event) nlOii9 <= {1{1'b1}}; initial nlOil7 = 0; always @ ( posedge clk) nlOil7 <= nlOil8; event nlOil7_event; initial #1 ->nlOil7_event; always @(nlOil7_event) nlOil7 <= {1{1'b1}}; initial nlOil8 = 0; always @ ( posedge clk) nlOil8 <= nlOil7; initial nlOli5 = 0; always @ ( posedge clk) nlOli5 <= nlOli6; event nlOli5_event; initial #1 ->nlOli5_event; always @(nlOli5_event) nlOli5 <= {1{1'b1}}; initial nlOli6 = 0; always @ ( posedge clk) nlOli6 <= nlOli5; initial nlOlO3 = 0; always @ ( posedge clk) nlOlO3 <= nlOlO4; event nlOlO3_event; initial #1 ->nlOlO3_event; always @(nlOlO3_event) nlOlO3 <= {1{1'b1}}; initial nlOlO4 = 0; always @ ( posedge clk) nlOlO4 <= nlOlO3; initial nlOOl1 = 0; always @ ( posedge clk) nlOOl1 <= nlOOl2; event nlOOl1_event; initial #1 ->nlOOl1_event; always @(nlOOl1_event) nlOOl1 <= {1{1'b1}}; initial nlOOl2 = 0; always @ ( posedge clk) nlOOl2 <= nlOOl1; initial begin ni0i = 0; ni0l = 0; ni1O = 0; niii = 0; end always @ ( posedge clk or negedge wire_ni0O_CLRN) begin if (wire_ni0O_CLRN == 1'b0) begin ni0i <= 0; ni0l <= 0; ni1O <= 0; niii <= 0; end else if (nlOiO == 1'b1) begin ni0i <= niiO; ni0l <= nili; ni1O <= niil; niii <= nill; end end assign wire_ni0O_CLRN = ((nlO0l12 ^ nlO0l11) & reset_n); initial begin n00i = 0; n00l = 0; n00O = 0; n01i = 0; n01l = 0; n01O = 0; n0ii = 0; n0il = 0; n0iO = 0; n0li = 0; n0ll = 0; n0lO = 0; n0Ol = 0; n0OO = 0; n1lO = 0; n1Ol = 0; n1OO = 0; ni1i = 0; ni1l = 0; niil = 0; niiO = 0; nili = 0; nill = 0; nilO = 0; niOi = 0; niOl = 0; nl1i = 0; end always @ (clk or wire_niOO_PRN or wire_niOO_CLRN) begin if (wire_niOO_PRN == 1'b0) begin n00i <= 1; n00l <= 1; n00O <= 1; n01i <= 1; n01l <= 1; n01O <= 1; n0ii <= 1; n0il <= 1; n0iO <= 1; n0li <= 1; n0ll <= 1; n0lO <= 1; n0Ol <= 1; n0OO <= 1; n1lO <= 1; n1Ol <= 1; n1OO <= 1; ni1i <= 1; ni1l <= 1; niil <= 1; niiO <= 1; nili <= 1; nill <= 1; nilO <= 1; niOi <= 1; niOl <= 1; nl1i <= 1; end else if (wire_niOO_CLRN == 1'b0) begin n00i <= 0; n00l <= 0; n00O <= 0; n01i <= 0; n01l <= 0; n01O <= 0; n0ii <= 0; n0il <= 0; n0iO <= 0; n0li <= 0; n0ll <= 0; n0lO <= 0; n0Ol <= 0; n0OO <= 0; n1lO <= 0; n1Ol <= 0; n1OO <= 0; ni1i <= 0; ni1l <= 0; niil <= 0; niiO <= 0; nili <= 0; nill <= 0; nilO <= 0; niOi <= 0; niOl <= 0; nl1i <= 0; end else if (clk != niOO_clk_prev && clk == 1'b1) begin n00i <= n00l; n00l <= n0ii; n00O <= wire_n1Oi_o; n01i <= n01l; n01l <= n01O; n01O <= n00i; n0ii <= n0il; n0il <= n0iO; n0iO <= n0li; n0li <= n0ll; n0ll <= ((phystat_ena & (~ power_state_transition_done_ena)) & n0lO); n0lO <= (~ (((((~ ((ni1O ^ n0Ol) ^ (~ (nlO1O14 ^ nlO1O13)))) & (~ (ni0i ^ n0OO))) & (~ (ni0l ^ ni1i))) & (~ (niii ^ ni1l))) & (nlO1i16 ^ nlO1i15))); n0Ol <= ni1O; n0OO <= ni0i; n1lO <= n1Ol; n1Ol <= n1OO; n1OO <= n01i; ni1i <= ni0l; ni1l <= niii; niil <= nilO; niiO <= niOi; nili <= niOl; nill <= nl1i; nilO <= latched_p0; niOi <= latched_p0s; niOl <= latched_p1; nl1i <= latched_p2; end niOO_clk_prev <= clk; end assign wire_niOO_CLRN = ((nlOil8 ^ nlOil7) & reset_n), wire_niOO_PRN = (nlOii10 ^ nlOii9); oper_mux n1Oi ( .data({n1lO, n1Ol, ((nllOi22 ^ nllOi21) & n1OO), ((nllOl20 ^ nllOl19) & n01i), n01l, n01O, n00i, ((nllOO18 ^ nllOO17) & n00l)}), .o(wire_n1Oi_o), .sel({rphystatus_delay[2:0]})); defparam n1Oi.width_data = 8, n1Oi.width_sel = 3; stratixiv_hssi_phystatus_generator_fsm nl0O ( .clk(clk), .internal_done(n00O), .p1(latched_p1), .phystat_ena(phystat_ena), .phystatus(wire_nl0O_phystatus), .power_state_transition_done(power_state_transition_done), .power_state_transition_done_ena(power_state_transition_done_ena), .powerdown({powerdown[1:0]}), .reset_n(reset_n), .rindv_rx(rindv_rx), .rmaster_rx(rmaster_rx), .rmaster_up_rx(rmaster_up_rx), .rphystatus_rst_toggle(rphystatus_rst_toggle), .rx_detect_valid(rx_detect_valid), .speed_change(speed_change), .speed_change_centrl(speed_change_centrl), .speed_change_quad_down(speed_change_quad_down), .speed_change_quad_up(speed_change_quad_up)); assign nlO0O = 1'b1, nlOiO = ((((((((((~ nill) & (~ nili)) & (~ niiO)) & niil) & (nlOOl2 ^ nlOOl1)) | ((((~ nill) & (~ nili)) & niiO) & (~ niil))) | (~ (nlOlO4 ^ nlOlO3))) | ((((~ nill) & nili) & (~ niiO)) & (~ niil))) | (~ (nlOli6 ^ nlOli5))) | (((nill & (~ nili)) & (~ niiO)) & (~ niil))), phystatus = wire_nl0O_phystatus; endmodule //stratixiv_hssi_phystatus_generator //synopsys translate_on //VALID FILE //IP Functional Simulation Model //VERSION_BEGIN 12.0 cbx_mgl 2012:05:31:20:09:47:SJ cbx_simgen 2012:05:31:20:08:35:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 // Copyright (C) 1991-2012 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // You may only use these simulation model output files for simulation // purposes and expressly not for synthesis or any other purposes (in which // event Altera disclaims all warranties of any kind). //synopsys translate_off //synthesis_resources = lut 50 mux21 146 `timescale 1 ps / 1 ps module stratixiv_hssi_rx_pipe_interface ( clk, latched_p1, polinv_rx, polinv_rx_int, rclkcmpinsertpad, reset_n, rind_error_reporting, rrdwidth_rx, rrx_pipe_enable, rx_detect_valid, rx_detect_valid_sync, rx_found, rx_found_sync, rxd, rxd_ch, rxelecidle, rxelectricalidle, rxpolarity, rxstatus, rxvalid, sigdetni, txdetectrx) /* synthesis synthesis_clearbox=1 */; input clk; input latched_p1; input polinv_rx; output polinv_rx_int; input rclkcmpinsertpad; input reset_n; input rind_error_reporting; input rrdwidth_rx; input rrx_pipe_enable; input rx_detect_valid; input rx_detect_valid_sync; input rx_found; input rx_found_sync; input [63:0] rxd; output [63:0] rxd_ch; output rxelecidle; input rxelectricalidle; input rxpolarity; output [2:0] rxstatus; output rxvalid; input sigdetni; input txdetectrx; reg n110l7; reg n110l8; reg n111i11; reg n111i12; reg n111O10; reg n111O9; reg n11ii5; reg n11ii6; reg n11iO3; reg n11iO4; reg n11Ol1; reg n11Ol2; reg nlO0ll41; reg nlO0ll42; reg nlO0Oi39; reg nlO0Oi40; reg nlO0OO37; reg nlO0OO38; reg nlOi0l35; reg nlOi0l36; reg nlOiil33; reg nlOiil34; reg nlOilO31; reg nlOilO32; reg nlOiOl29; reg nlOiOl30; reg nlOl1l27; reg nlOl1l28; reg nlOlii25; reg nlOlii26; reg nlOlli23; reg nlOlli24; reg nlOlOi21; reg nlOlOi22; reg nlOO0i17; reg nlOO0i18; reg nlOO1i19; reg nlOO1i20; reg nlOOiO15; reg nlOOiO16; reg nlOOOl13; reg nlOOOl14; reg n00ii; reg n0ill; reg n0iOi; reg n1l1l; reg n1O0i; reg n1O1O; reg nlOOO; reg nO; reg nl_clk_prev; wire wire_nl_CLRN; wire wire_n000i_dataout; wire wire_n001i_dataout; wire wire_n001l_dataout; wire wire_n001O_dataout; wire wire_n00i_dataout; wire wire_n00l_dataout; wire wire_n00O_dataout; wire wire_n00OO_dataout; wire wire_n010i_dataout; wire wire_n010l_dataout; wire wire_n010O_dataout; wire wire_n011i_dataout; wire wire_n011l_dataout; wire wire_n011O_dataout; wire wire_n01i_dataout; wire wire_n01ii_dataout; wire wire_n01il_dataout; wire wire_n01iO_dataout; wire wire_n01l_dataout; wire wire_n01li_dataout; wire wire_n01ll_dataout; wire wire_n01lO_dataout; wire wire_n01O_dataout; wire wire_n01Oi_dataout; wire wire_n01Ol_dataout; wire wire_n01OO_dataout; wire wire_n0i_dataout; wire wire_n0i1l_dataout; wire wire_n0ii_dataout; wire wire_n0il_dataout; wire wire_n0iO_dataout; wire wire_n0l_dataout; wire wire_n0li_dataout; wire wire_n0ll_dataout; wire wire_n0lO_dataout; wire wire_n0O_dataout; wire wire_n0Oi_dataout; wire wire_n0Ol_dataout; wire wire_n0OO_dataout; wire wire_n100O_dataout; wire wire_n10i_dataout; wire wire_n10ii_dataout; wire wire_n10il_dataout; wire wire_n10iO_dataout; wire wire_n10l_dataout; wire wire_n10li_dataout; wire wire_n10ll_dataout; wire wire_n10lO_dataout; wire wire_n10O_dataout; wire wire_n10Oi_dataout; wire wire_n10Ol_dataout; wire wire_n10OO_dataout; wire wire_n11i_dataout; wire wire_n11l_dataout; wire wire_n1i_dataout; wire wire_n1i0i_dataout; wire wire_n1i0l_dataout; wire wire_n1i0O_dataout; wire wire_n1i1i_dataout; wire wire_n1i1l_dataout; wire wire_n1i1O_dataout; wire wire_n1ii_dataout; wire wire_n1iii_dataout; wire wire_n1iil_dataout; wire wire_n1iiO_dataout; wire wire_n1il_dataout; wire wire_n1ili_dataout; wire wire_n1ill_dataout; wire wire_n1ilO_dataout; wire wire_n1iO_dataout; wire wire_n1iOi_dataout; wire wire_n1iOl_dataout; wire wire_n1l_dataout; wire wire_n1li_dataout; wire wire_n1liO_dataout; wire wire_n1ll_dataout; wire wire_n1lll_dataout; wire wire_n1lO_dataout; wire wire_n1O_dataout; wire wire_n1Oi_dataout; wire wire_n1Ol_dataout; wire wire_n1Oll_dataout; wire wire_n1OlO_dataout; wire wire_n1OO_dataout; wire wire_n1OOi_dataout; wire wire_n1OOl_dataout; wire wire_n1OOO_dataout; wire wire_ni_dataout; wire wire_ni0i_dataout; wire wire_ni0l_dataout; wire wire_ni0O_dataout; wire wire_ni1i_dataout; wire wire_ni1l_dataout; wire wire_ni1O_dataout; wire wire_nii_dataout; wire wire_niii_dataout; wire wire_niil_dataout; wire wire_niiO_dataout; wire wire_nil_dataout; wire wire_nili_dataout; wire wire_nill_dataout; wire wire_nilO_dataout; wire wire_niO_dataout; wire wire_niOi_dataout; wire wire_niOl_dataout; wire wire_niOO_dataout; wire wire_nl0i_dataout; wire wire_nl0l_dataout; wire wire_nl0O_dataout; wire wire_nl1i_dataout; wire wire_nl1l_dataout; wire wire_nl1O_dataout; wire wire_nli_dataout; wire wire_nlii_dataout; wire wire_nlil_dataout; wire wire_nliO_dataout; wire wire_nliOl_dataout; wire wire_nliOO_dataout; wire wire_nll_dataout; wire wire_nll0i_dataout; wire wire_nll0l_dataout; wire wire_nll0O_dataout; wire wire_nll1i_dataout; wire wire_nll1l_dataout; wire wire_nll1O_dataout; wire wire_nlli_dataout; wire wire_nllii_dataout; wire wire_nllil_dataout; wire wire_nlliO_dataout; wire wire_nlll_dataout; wire wire_nllli_dataout; wire wire_nllll_dataout; wire wire_nlllO_dataout; wire wire_nllO_dataout; wire wire_nllOi_dataout; wire wire_nllOl_dataout; wire wire_nllOO_dataout; wire wire_nlO_dataout; wire wire_nlO0i_dataout; wire wire_nlO1i_dataout; wire wire_nlO1l_dataout; wire wire_nlO1O_dataout; wire wire_nlOi_dataout; wire wire_nlOl_dataout; wire wire_nlOO_dataout; wire wire_nlOOl_dataout; wire n11lO; wire nlO00i; wire nlO00l; wire nlO00O; wire nlO01i; wire nlO01l; wire nlO01O; wire nlO0ii; wire nlO0il; wire nlO0iO; wire nlO0li; wire nlOi0i; wire nlOi1l; wire nlOi1O; wire nlOiii; wire nlOili; wire nlOill; wire nlOl0i; wire nlOl0l; wire nlOl0O; wire nlOl1i; wire nlOliO; wire nlOllO; wire nlOlOO; wire nlOO0O; wire nlOO1O; wire nlOOii; wire nlOOil; wire nlOOll; wire nlOOlO; wire nlOOOi; initial n110l7 = 0; always @ ( posedge clk) n110l7 <= n110l8; event n110l7_event; initial #1 ->n110l7_event; always @(n110l7_event) n110l7 <= {1{1'b1}}; initial n110l8 = 0; always @ ( posedge clk) n110l8 <= n110l7; initial n111i11 = 0; always @ ( posedge clk) n111i11 <= n111i12; event n111i11_event; initial #1 ->n111i11_event; always @(n111i11_event) n111i11 <= {1{1'b1}}; initial n111i12 = 0; always @ ( posedge clk) n111i12 <= n111i11; initial n111O10 = 0; always @ ( posedge clk) n111O10 <= n111O9; initial n111O9 = 0; always @ ( posedge clk) n111O9 <= n111O10; event n111O9_event; initial #1 ->n111O9_event; always @(n111O9_event) n111O9 <= {1{1'b1}}; initial n11ii5 = 0; always @ ( posedge clk) n11ii5 <= n11ii6; event n11ii5_event; initial #1 ->n11ii5_event; always @(n11ii5_event) n11ii5 <= {1{1'b1}}; initial n11ii6 = 0; always @ ( posedge clk) n11ii6 <= n11ii5; initial n11iO3 = 0; always @ ( posedge clk) n11iO3 <= n11iO4; event n11iO3_event; initial #1 ->n11iO3_event; always @(n11iO3_event) n11iO3 <= {1{1'b1}}; initial n11iO4 = 0; always @ ( posedge clk) n11iO4 <= n11iO3; initial n11Ol1 = 0; always @ ( posedge clk) n11Ol1 <= n11Ol2; event n11Ol1_event; initial #1 ->n11Ol1_event; always @(n11Ol1_event) n11Ol1 <= {1{1'b1}}; initial n11Ol2 = 0; always @ ( posedge clk) n11Ol2 <= n11Ol1; initial nlO0ll41 = 0; always @ ( posedge clk) nlO0ll41 <= nlO0ll42; event nlO0ll41_event; initial #1 ->nlO0ll41_event; always @(nlO0ll41_event) nlO0ll41 <= {1{1'b1}}; initial nlO0ll42 = 0; always @ ( posedge clk) nlO0ll42 <= nlO0ll41; initial nlO0Oi39 = 0; always @ ( posedge clk) nlO0Oi39 <= nlO0Oi40; event nlO0Oi39_event; initial #1 ->nlO0Oi39_event; always @(nlO0Oi39_event) nlO0Oi39 <= {1{1'b1}}; initial nlO0Oi40 = 0; always @ ( posedge clk) nlO0Oi40 <= nlO0Oi39; initial nlO0OO37 = 0; always @ ( posedge clk) nlO0OO37 <= nlO0OO38; event nlO0OO37_event; initial #1 ->nlO0OO37_event; always @(nlO0OO37_event) nlO0OO37 <= {1{1'b1}}; initial nlO0OO38 = 0; always @ ( posedge clk) nlO0OO38 <= nlO0OO37; initial nlOi0l35 = 0; always @ ( posedge clk) nlOi0l35 <= nlOi0l36; event nlOi0l35_event; initial #1 ->nlOi0l35_event; always @(nlOi0l35_event) nlOi0l35 <= {1{1'b1}}; initial nlOi0l36 = 0; always @ ( posedge clk) nlOi0l36 <= nlOi0l35; initial nlOiil33 = 0; always @ ( posedge clk) nlOiil33 <= nlOiil34; event nlOiil33_event; initial #1 ->nlOiil33_event; always @(nlOiil33_event) nlOiil33 <= {1{1'b1}}; initial nlOiil34 = 0; always @ ( posedge clk) nlOiil34 <= nlOiil33; initial nlOilO31 = 0; always @ ( posedge clk) nlOilO31 <= nlOilO32; event nlOilO31_event; initial #1 ->nlOilO31_event; always @(nlOilO31_event) nlOilO31 <= {1{1'b1}}; initial nlOilO32 = 0; always @ ( posedge clk) nlOilO32 <= nlOilO31; initial nlOiOl29 = 0; always @ ( posedge clk) nlOiOl29 <= nlOiOl30; event nlOiOl29_event; initial #1 ->nlOiOl29_event; always @(nlOiOl29_event) nlOiOl29 <= {1{1'b1}}; initial nlOiOl30 = 0; always @ ( posedge clk) nlOiOl30 <= nlOiOl29; initial nlOl1l27 = 0; always @ ( posedge clk) nlOl1l27 <= nlOl1l28; event nlOl1l27_event; initial #1 ->nlOl1l27_event; always @(nlOl1l27_event) nlOl1l27 <= {1{1'b1}}; initial nlOl1l28 = 0; always @ ( posedge clk) nlOl1l28 <= nlOl1l27; initial nlOlii25 = 0; always @ ( posedge clk) nlOlii25 <= nlOlii26; event nlOlii25_event; initial #1 ->nlOlii25_event; always @(nlOlii25_event) nlOlii25 <= {1{1'b1}}; initial nlOlii26 = 0; always @ ( posedge clk) nlOlii26 <= nlOlii25; initial nlOlli23 = 0; always @ ( posedge clk) nlOlli23 <= nlOlli24; event nlOlli23_event; initial #1 ->nlOlli23_event; always @(nlOlli23_event) nlOlli23 <= {1{1'b1}}; initial nlOlli24 = 0; always @ ( posedge clk) nlOlli24 <= nlOlli23; initial nlOlOi21 = 0; always @ ( posedge clk) nlOlOi21 <= nlOlOi22; event nlOlOi21_event; initial #1 ->nlOlOi21_event; always @(nlOlOi21_event) nlOlOi21 <= {1{1'b1}}; initial nlOlOi22 = 0; always @ ( posedge clk) nlOlOi22 <= nlOlOi21; initial nlOO0i17 = 0; always @ ( posedge clk) nlOO0i17 <= nlOO0i18; event nlOO0i17_event; initial #1 ->nlOO0i17_event; always @(nlOO0i17_event) nlOO0i17 <= {1{1'b1}}; initial nlOO0i18 = 0; always @ ( posedge clk) nlOO0i18 <= nlOO0i17; initial nlOO1i19 = 0; always @ ( posedge clk) nlOO1i19 <= nlOO1i20; event nlOO1i19_event; initial #1 ->nlOO1i19_event; always @(nlOO1i19_event) nlOO1i19 <= {1{1'b1}}; initial nlOO1i20 = 0; always @ ( posedge clk) nlOO1i20 <= nlOO1i19; initial nlOOiO15 = 0; always @ ( posedge clk) nlOOiO15 <= nlOOiO16; event nlOOiO15_event; initial #1 ->nlOOiO15_event; always @(nlOOiO15_event) nlOOiO15 <= {1{1'b1}}; initial nlOOiO16 = 0; always @ ( posedge clk) nlOOiO16 <= nlOOiO15; initial nlOOOl13 = 0; always @ ( posedge clk) nlOOOl13 <= nlOOOl14; event nlOOOl13_event; initial #1 ->nlOOOl13_event; always @(nlOOOl13_event) nlOOOl13 <= {1{1'b1}}; initial nlOOOl14 = 0; always @ ( posedge clk) nlOOOl14 <= nlOOOl13; initial begin n00ii = 0; n0ill = 0; n0iOi = 0; n1l1l = 0; n1O0i = 0; n1O1O = 0; end always @ ( posedge clk or negedge reset_n) begin if (reset_n == 1'b0) begin n00ii <= 0; n0ill <= 0; n0iOi <= 0; n1l1l <= 0; n1O0i <= 0; n1O1O <= 0; end else begin n00ii <= n0ill; n0ill <= txdetectrx; n0iOi <= rx_detect_valid_sync; n1l1l <= n1O1O; n1O0i <= rx_detect_valid_sync; n1O1O <= txdetectrx; end end initial begin nlOOO = 0; nO = 0; end always @ (clk or reset_n or wire_nl_CLRN) begin if (reset_n == 1'b0) begin nlOOO <= 1; nO <= 1; end else if (wire_nl_CLRN == 1'b0) begin nlOOO <= 0; nO <= 0; end else if (clk != nl_clk_prev && clk == 1'b1) begin nlOOO <= rxelectricalidle; nO <= nlOOO; end nl_clk_prev <= clk; end assign wire_nl_CLRN = (n11Ol2 ^ n11Ol1); event nlOOO_event; event nO_event; initial #1 ->nlOOO_event; initial #1 ->nO_event; always @(nlOOO_event) nlOOO <= 1; always @(nO_event) nO <= 1; and(wire_n000i_dataout, (rxd[45] & rxd[46]), ~(nlOi0i)); and(wire_n001i_dataout, wire_n001O_dataout, ~(nlOill)); and(wire_n001l_dataout, nlOi0i, ~(nlOiii)); and(wire_n001O_dataout, wire_n000i_dataout, ~(nlOiii)); and(wire_n00i_dataout, rxd[9], rrx_pipe_enable); and(wire_n00l_dataout, rxd[10], rrx_pipe_enable); and(wire_n00O_dataout, rxd[11], rrx_pipe_enable); and(wire_n00OO_dataout, rxd[43], (nlOllO & (~ nlOliO))); and(wire_n010i_dataout, wire_n01il_dataout, ~(nlOi1l)); and(wire_n010l_dataout, nlOi1O, ~(nlOi1l)); and(wire_n010O_dataout, wire_n01iO_dataout, ~(nlOi1l)); and(wire_n011i_dataout, wire_n010l_dataout, ~(nlOliO)); and(wire_n011l_dataout, wire_n010O_dataout, ~(nlOliO)); and(wire_n011O_dataout, wire_n01ii_dataout, ~(nlOliO)); and(wire_n01i_dataout, rxd[6], rrx_pipe_enable); and(wire_n01ii_dataout, wire_n01li_dataout, ~(nlOi1l)); and(wire_n01il_dataout, wire_n01ll_dataout, ~(nlOi1O)); and(wire_n01iO_dataout, wire_n01lO_dataout, ~(nlOi1O)); and(wire_n01l_dataout, rxd[7], rrx_pipe_enable); and(wire_n01li_dataout, wire_n01Oi_dataout, ~(nlOi1O)); and(wire_n01ll_dataout, wire_n01Ol_dataout, ~(nlOl1i)); or(wire_n01lO_dataout, wire_n01OO_dataout, nlOl1i); and(wire_n01O_dataout, rxd[8], rrx_pipe_enable); and(wire_n01Oi_dataout, wire_n001i_dataout, ~(nlOl1i)); or(wire_n01Ol_dataout, wire_n001l_dataout, nlOill); and(wire_n01OO_dataout, nlOiii, ~(nlOill)); and(wire_n0i_dataout, rxd[54], rrx_pipe_enable); and(wire_n0i1l_dataout, rxd[41], (nlOllO & (~ nlOliO))); and(wire_n0ii_dataout, rxd[12], rrx_pipe_enable); and(wire_n0il_dataout, rxd[13], rrx_pipe_enable); and(wire_n0iO_dataout, rxd[14], rrx_pipe_enable); and(wire_n0l_dataout, rxd[55], rrx_pipe_enable); and(wire_n0li_dataout, rxd[15], rrx_pipe_enable); and(wire_n0ll_dataout, rxd[16], rrx_pipe_enable); and(wire_n0lO_dataout, rxd[17], rrx_pipe_enable); and(wire_n0O_dataout, rxd[56], rrx_pipe_enable); and(wire_n0Oi_dataout, rxd[18], rrx_pipe_enable); and(wire_n0Ol_dataout, rxd[19], rrx_pipe_enable); and(wire_n0OO_dataout, rxd[20], rrx_pipe_enable); and(wire_n100O_dataout, wire_n10li_dataout, ~((~ reset_n))); assign wire_n10i_dataout = (rrx_pipe_enable === 1'b1) ? wire_nliOl_dataout : rx_found; and(wire_n10ii_dataout, wire_n10ll_dataout, ~((~ reset_n))); and(wire_n10il_dataout, wire_n10lO_dataout, ~((~ reset_n))); and(wire_n10iO_dataout, wire_n10Oi_dataout, ~((~ reset_n))); assign wire_n10l_dataout = (rrx_pipe_enable === 1'b1) ? wire_nliOO_dataout : rx_detect_valid; and(wire_n10li_dataout, wire_n10Ol_dataout, ~(nlO0li)); and(wire_n10ll_dataout, wire_n10OO_dataout, ~(nlO0li)); and(wire_n10lO_dataout, wire_n1i1i_dataout, ~(nlO0li)); and(wire_n10O_dataout, wire_nll1i_dataout, rrx_pipe_enable); and(wire_n10Oi_dataout, wire_n1i1l_dataout, ~(nlO0li)); and(wire_n10Ol_dataout, wire_n1i1O_dataout, ~(nlO01i)); and(wire_n10OO_dataout, nlO01l, ~(nlO01i)); and(wire_n11i_dataout, wire_n11l_dataout, ~((~ reset_n))); assign wire_n11l_dataout = (rrdwidth_rx === 1'b1) ? ((rxd[10] | rxd[42]) | (~ (n11iO4 ^ n11iO3))) : rxd[10]; and(wire_n1i_dataout, rxd[51], rrx_pipe_enable); and(wire_n1i0i_dataout, wire_n1iii_dataout, ~(nlO01l)); and(wire_n1i0l_dataout, wire_n1iil_dataout, ~(nlO01l)); and(wire_n1i0O_dataout, wire_n1iiO_dataout, ~(nlO0ii)); and(wire_n1i1i_dataout, wire_n1i0i_dataout, ~(nlO01i)); and(wire_n1i1l_dataout, wire_n1i0l_dataout, ~(nlO01i)); and(wire_n1i1O_dataout, wire_n1i0O_dataout, ~(nlO01l)); assign wire_n1ii_dataout = (rrx_pipe_enable === 1'b1) ? wire_nlOOl_dataout : (~ sigdetni); or(wire_n1iii_dataout, wire_n1ili_dataout, nlO0ii); and(wire_n1iil_dataout, wire_n1ill_dataout, ~(nlO0ii)); or(wire_n1iiO_dataout, wire_n1ilO_dataout, nlO00O); and(wire_n1il_dataout, wire_n11i_dataout, rrx_pipe_enable); and(wire_n1ili_dataout, nlO00i, ~(nlO00O)); and(wire_n1ill_dataout, wire_n1iOi_dataout, ~(nlO00O)); and(wire_n1ilO_dataout, nlO01O, ~(nlO00i)); assign wire_n1iO_dataout = (rrx_pipe_enable === 1'b1) ? rxpolarity : polinv_rx; and(wire_n1iOi_dataout, wire_n1iOl_dataout, ~(nlO00i)); and(wire_n1iOl_dataout, (rxd[13] & rxd[14]), ~(nlO01O)); and(wire_n1l_dataout, rxd[52], rrx_pipe_enable); and(wire_n1li_dataout, rxd[0], rrx_pipe_enable); and(wire_n1liO_dataout, rxd[11], (reset_n & (~ nlO0li))); and(wire_n1ll_dataout, rxd[1], rrx_pipe_enable); and(wire_n1lll_dataout, rxd[9], (reset_n & (~ nlO0li))); and(wire_n1lO_dataout, rxd[2], rrx_pipe_enable); and(wire_n1O_dataout, rxd[53], rrx_pipe_enable); and(wire_n1Oi_dataout, rxd[3], rrx_pipe_enable); and(wire_n1Ol_dataout, rxd[4], rrx_pipe_enable); and(wire_n1Oll_dataout, wire_n1OOO_dataout, ~(nlOl0O)); and(wire_n1OlO_dataout, wire_n011i_dataout, ~(nlOl0O)); and(wire_n1OO_dataout, rxd[5], rrx_pipe_enable); and(wire_n1OOi_dataout, wire_n011l_dataout, ~(nlOl0O)); and(wire_n1OOl_dataout, wire_n011O_dataout, ~(nlOl0O)); and(wire_n1OOO_dataout, wire_n010i_dataout, ~(nlOliO)); and(wire_ni_dataout, rxd[63], rrx_pipe_enable); and(wire_ni0i_dataout, rxd[24], rrx_pipe_enable); and(wire_ni0l_dataout, rxd[25], rrx_pipe_enable); and(wire_ni0O_dataout, rxd[26], rrx_pipe_enable); and(wire_ni1i_dataout, rxd[21], rrx_pipe_enable); and(wire_ni1l_dataout, rxd[22], rrx_pipe_enable); and(wire_ni1O_dataout, rxd[23], rrx_pipe_enable); and(wire_nii_dataout, rxd[57], rrx_pipe_enable); and(wire_niii_dataout, rxd[27], rrx_pipe_enable); and(wire_niil_dataout, rxd[28], rrx_pipe_enable); and(wire_niiO_dataout, rxd[29], rrx_pipe_enable); and(wire_nil_dataout, rxd[58], rrx_pipe_enable); and(wire_nili_dataout, rxd[30], rrx_pipe_enable); and(wire_nill_dataout, rxd[31], rrx_pipe_enable); and(wire_nilO_dataout, rxd[32], rrx_pipe_enable); and(wire_niO_dataout, rxd[59], rrx_pipe_enable); and(wire_niOi_dataout, rxd[33], rrx_pipe_enable); and(wire_niOl_dataout, rxd[34], rrx_pipe_enable); and(wire_niOO_dataout, rxd[35], rrx_pipe_enable); and(wire_nl0i_dataout, rxd[39], rrx_pipe_enable); and(wire_nl0l_dataout, rxd[40], rrx_pipe_enable); and(wire_nl0O_dataout, rxd[41], rrx_pipe_enable); and(wire_nl1i_dataout, rxd[36], rrx_pipe_enable); and(wire_nl1l_dataout, rxd[37], rrx_pipe_enable); and(wire_nl1O_dataout, rxd[38], rrx_pipe_enable); and(wire_nli_dataout, rxd[60], rrx_pipe_enable); and(wire_nlii_dataout, rxd[42], rrx_pipe_enable); and(wire_nlil_dataout, rxd[43], rrx_pipe_enable); and(wire_nliO_dataout, rxd[44], rrx_pipe_enable); and(wire_nliOl_dataout, wire_nll1l_dataout, ~((~ reset_n))); and(wire_nliOO_dataout, wire_nll1O_dataout, ~((~ reset_n))); and(wire_nll_dataout, rxd[61], rrx_pipe_enable); and(wire_nll0i_dataout, wire_nllii_dataout, ~(nlOOOi)); and(wire_nll0l_dataout, wire_nllil_dataout, ~(nlOOlO)); and(wire_nll0O_dataout, wire_nlliO_dataout, ~(nlOOlO)); and(wire_nll1i_dataout, wire_nll0i_dataout, ~((~ reset_n))); or(wire_nll1l_dataout, wire_nll0l_dataout, nlOOOi); or(wire_nll1O_dataout, wire_nll0O_dataout, nlOOOi); and(wire_nlli_dataout, rxd[45], rrx_pipe_enable); or(wire_nllii_dataout, wire_nllli_dataout, nlOOlO); or(wire_nllil_dataout, wire_nllll_dataout, nlOOll); and(wire_nlliO_dataout, wire_nlllO_dataout, ~(nlOOll)); and(wire_nlll_dataout, rxd[46], rrx_pipe_enable); or(wire_nllli_dataout, wire_nllOi_dataout, nlOOll); and(wire_nllll_dataout, wire_nllOl_dataout, ~(nlOOil)); or(wire_nlllO_dataout, wire_nllOO_dataout, nlOOil); and(wire_nllO_dataout, rxd[47], rrx_pipe_enable); or(wire_nllOi_dataout, wire_nlO1i_dataout, nlOOil); or(wire_nllOl_dataout, wire_nlO1l_dataout, nlOO0O); or(wire_nllOO_dataout, wire_nlO1O_dataout, nlOO0O); and(wire_nlO_dataout, rxd[62], rrx_pipe_enable); and(wire_nlO0i_dataout, (wire_n100O_dataout | wire_n1Oll_dataout), ~(nlOlOO)); or(wire_nlO1i_dataout, nlOO1O, nlOO0O); and(wire_nlO1l_dataout, wire_nlO0i_dataout, ~(nlOO1O)); and(wire_nlO1O_dataout, nlOlOO, ~(nlOO1O)); and(wire_nlOi_dataout, rxd[48], rrx_pipe_enable); and(wire_nlOl_dataout, rxd[49], rrx_pipe_enable); and(wire_nlOO_dataout, rxd[50], rrx_pipe_enable); or(wire_nlOOl_dataout, nO, (~ reset_n)); assign n11lO = 1'b1, nlO00i = (rclkcmpinsertpad & (nlO0il & nlO00l)), nlO00l = (((((((rxd[0] & rxd[1]) & rxd[2]) & (~ rxd[3])) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]), nlO00O = ((~ rclkcmpinsertpad) & ((~ nlO0iO) & nlO0il)), nlO01i = ((~ rxd[13]) & (~ rxd[14])), nlO01l = (rxd[13] & (~ rxd[14])), nlO01O = (rclkcmpinsertpad & (nlO0il & (~ nlO00l))), nlO0ii = ((~ rclkcmpinsertpad) & (nlO0iO & nlO0il)), nlO0il = ((~ rxd[13]) & rxd[14]), nlO0iO = ((((((((~ rxd[0]) & rxd[1]) & rxd[2]) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]), nlO0li = ((rx_detect_valid_sync & (~ n1O0i)) & (nlO0ll42 ^ nlO0ll41)), nlOi0i = ((rclkcmpinsertpad & (nlOl0i & (~ nlOili))) & (nlOi0l36 ^ nlOi0l35)), nlOi1l = ((~ rxd[45]) & (~ rxd[46])), nlOi1O = ((rxd[45] & (~ rxd[46])) & (nlO0OO38 ^ nlO0OO37)), nlOiii = ((rclkcmpinsertpad & (nlOl0i & nlOili)) & (nlOiil34 ^ nlOiil33)), nlOili = ((((((((rxd[32] & rxd[33]) & rxd[34]) & (~ rxd[35])) & rxd[36]) & rxd[37]) & rxd[38]) & rxd[39]) & (nlO0Oi40 ^ nlO0Oi39)), nlOill = (((~ rclkcmpinsertpad) & (((~ nlOl0l) & nlOl0i) & (nlOiOl30 ^ nlOiOl29))) & (nlOilO32 ^ nlOilO31)), nlOl0i = ((~ rxd[45]) & rxd[46]), nlOl0l = ((((((((~ rxd[32]) & rxd[33]) & rxd[34]) & rxd[35]) & rxd[36]) & rxd[37]) & rxd[38]) & rxd[39]), nlOl0O = (((~ reset_n) | (~ rrdwidth_rx)) | (~ (nlOlii26 ^ nlOlii25))), nlOl1i = (((~ rclkcmpinsertpad) & (nlOl0l & nlOl0i)) & (nlOl1l28 ^ nlOl1l27)), nlOliO = ((rx_detect_valid_sync & (~ n0iOi)) & (nlOlli24 ^ nlOlli23)), nlOllO = ((reset_n & rrdwidth_rx) & (nlOlOi22 ^ nlOlOi21)), nlOlOO = ((wire_n10ii_dataout | wire_n1OlO_dataout) | (~ (nlOO1i20 ^ nlOO1i19))), nlOO0O = (nlOOii & rind_error_reporting), nlOO1O = ((nlOOii & (~ rind_error_reporting)) & (nlOO0i18 ^ nlOO0i17)), nlOOii = (wire_n1liO_dataout | wire_n00OO_dataout), nlOOil = ((wire_n10il_dataout | wire_n1OOi_dataout) | (~ (nlOOiO16 ^ nlOOiO15))), nlOOll = (wire_n10iO_dataout | wire_n1OOl_dataout), nlOOlO = (wire_n1lll_dataout | wire_n0i1l_dataout), nlOOOi = ((((~ n1O0i) & ((rx_detect_valid_sync & (latched_p1 & rx_found_sync)) & (n11ii6 ^ n11ii5))) & n1l1l) | ((((~ n0iOi) & ((rx_detect_valid_sync & ((rx_found_sync & ((rrdwidth_rx & latched_p1) & (n110l8 ^ n110l7))) & (n111O10 ^ n111O9))) & (n111i12 ^ n111i11))) & n00ii) & (nlOOOl14 ^ nlOOOl13))), polinv_rx_int = wire_n1iO_dataout, rxd_ch = {wire_ni_dataout, wire_nlO_dataout, wire_nll_dataout, wire_nli_dataout, wire_niO_dataout, wire_nil_dataout, wire_nii_dataout, wire_n0O_dataout, wire_n0l_dataout, wire_n0i_dataout, wire_n1O_dataout, wire_n1l_dataout, wire_n1i_dataout, wire_nlOO_dataout, wire_nlOl_dataout, wire_nlOi_dataout, wire_nllO_dataout, wire_nlll_dataout, wire_nlli_dataout, wire_nliO_dataout, wire_nlil_dataout, wire_nlii_dataout, wire_nl0O_dataout, wire_nl0l_dataout, wire_nl0i_dataout, wire_nl1O_dataout, wire_nl1l_dataout, wire_nl1i_dataout, wire_niOO_dataout, wire_niOl_dataout, wire_niOi_dataout, wire_nilO_dataout, wire_nill_dataout, wire_nili_dataout, wire_niiO_dataout, wire_niil_dataout, wire_niii_dataout, wire_ni0O_dataout, wire_ni0l_dataout, wire_ni0i_dataout, wire_ni1O_dataout, wire_ni1l_dataout, wire_ni1i_dataout, wire_n0OO_dataout, wire_n0Ol_dataout, wire_n0Oi_dataout, wire_n0lO_dataout, wire_n0ll_dataout, wire_n0li_dataout, wire_n0iO_dataout, wire_n0il_dataout, wire_n0ii_dataout, wire_n00O_dataout, wire_n00l_dataout, wire_n00i_dataout, wire_n01O_dataout, wire_n01l_dataout, wire_n01i_dataout, wire_n1OO_dataout, wire_n1Ol_dataout, wire_n1Oi_dataout, wire_n1lO_dataout, wire_n1ll_dataout, wire_n1li_dataout}, rxelecidle = wire_n1ii_dataout, rxstatus = {wire_n10O_dataout, wire_n10l_dataout, wire_n10i_dataout}, rxvalid = wire_n1il_dataout; endmodule //stratixiv_hssi_rx_pipe_interface //synopsys translate_on //VALID FILE //IP Functional Simulation Model //VERSION_BEGIN 12.0 cbx_mgl 2012:05:31:20:09:47:SJ cbx_simgen 2012:05:31:20:08:35:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 // Copyright (C) 1991-2012 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // You may only use these simulation model output files for simulation // purposes and expressly not for synthesis or any other purposes (in which // event Altera disclaims all warranties of any kind). //synopsys translate_off //synthesis_resources = lut 36 mux21 13 oper_mux 1 `timescale 1 ps / 1 ps module stratixiv_hssi_tx_pipe_interface ( clk, powerdown, powerstate, refclk_b, refclk_b_reset_n, reset_n, rev_loopbk, revloopback, rtx_elec_idle_delay, rtx_pipe_enable, rtxswing_sel_ena, tx_elec_idle, tx_elec_idle_comp, txd, txd_ch, txdeemph, txdeemph_int, txdetectrx, txdetectrxloopback, txelecidle, txmargin, txmargin_int, txswing, txswing_int) /* synthesis synthesis_clearbox=1 */; input clk; input [1:0] powerdown; output [3:0] powerstate; input refclk_b; input refclk_b_reset_n; input reset_n; output rev_loopbk; input revloopback; input [2:0] rtx_elec_idle_delay; input rtx_pipe_enable; input rtxswing_sel_ena; output tx_elec_idle; input tx_elec_idle_comp; output [43:0] txd; input [43:0] txd_ch; input txdeemph; output txdeemph_int; output txdetectrx; input txdetectrxloopback; input txelecidle; input [2:0] txmargin; output [2:0] txmargin_int; input txswing; output txswing_int; reg niiOl23; reg niiOl24; reg nil0i19; reg nil0i20; reg nil0l17; reg nil0l18; reg nil0O15; reg nil0O16; reg nil1i21; reg nil1i22; reg nilii13; reg nilii14; reg niliO11; reg niliO12; reg nilli10; reg nilli9; reg nilOi7; reg nilOi8; reg nilOl5; reg nilOl6; reg niO1i3; reg niO1i4; reg niO1O1; reg niO1O2; reg nl00i; reg nl10i; reg nl10l; reg nl10O; reg nl11O; reg nl1ii; reg nl1il; reg nl1iO; reg nl1li; reg nl01O_clk_prev; wire wire_nl01O_CLRN; wire wire_nl01O_PRN; reg nl1lO; reg nl1ll_clk_prev; wire wire_nl1ll_CLRN; wire wire_nl1ll_PRN; wire wire_nl1ll_ENA; reg nl1Oi; reg nl1OO; wire wire_niOll_dataout; wire wire_niOlO_dataout; wire wire_niOOi_dataout; wire wire_niOOl_dataout; wire wire_nl00O_dataout; wire wire_nl0il_dataout; wire wire_nl0iO_dataout; wire wire_nl0ll_dataout; wire wire_nl0lO_dataout; wire wire_nl0Oi_dataout; wire wire_nl0Ol_dataout; wire wire_nl0OO_dataout; wire wire_nl11i_dataout; wire wire_nl11l_o; wire nil1O; wire nilll; wire nillO; wire nilOO; initial niiOl23 = 0; always @ ( posedge refclk_b) niiOl23 <= niiOl24; event niiOl23_event; initial #1 ->niiOl23_event; always @(niiOl23_event) niiOl23 <= {1{1'b1}}; initial niiOl24 = 0; always @ ( posedge refclk_b) niiOl24 <= niiOl23; initial nil0i19 = 0; always @ ( posedge refclk_b) nil0i19 <= nil0i20; event nil0i19_event; initial #1 ->nil0i19_event; always @(nil0i19_event) nil0i19 <= {1{1'b1}}; initial nil0i20 = 0; always @ ( posedge refclk_b) nil0i20 <= nil0i19; initial nil0l17 = 0; always @ ( posedge refclk_b) nil0l17 <= nil0l18; event nil0l17_event; initial #1 ->nil0l17_event; always @(nil0l17_event) nil0l17 <= {1{1'b1}}; initial nil0l18 = 0; always @ ( posedge refclk_b) nil0l18 <= nil0l17; initial nil0O15 = 0; always @ ( posedge refclk_b) nil0O15 <= nil0O16; event nil0O15_event; initial #1 ->nil0O15_event; always @(nil0O15_event) nil0O15 <= {1{1'b1}}; initial nil0O16 = 0; always @ ( posedge refclk_b) nil0O16 <= nil0O15; initial nil1i21 = 0; always @ ( posedge refclk_b) nil1i21 <= nil1i22; event nil1i21_event; initial #1 ->nil1i21_event; always @(nil1i21_event) nil1i21 <= {1{1'b1}}; initial nil1i22 = 0; always @ ( posedge refclk_b) nil1i22 <= nil1i21; initial nilii13 = 0; always @ ( posedge refclk_b) nilii13 <= nilii14; event nilii13_event; initial #1 ->nilii13_event; always @(nilii13_event) nilii13 <= {1{1'b1}}; initial nilii14 = 0; always @ ( posedge refclk_b) nilii14 <= nilii13; initial niliO11 = 0; always @ ( posedge refclk_b) niliO11 <= niliO12; event niliO11_event; initial #1 ->niliO11_event; always @(niliO11_event) niliO11 <= {1{1'b1}}; initial niliO12 = 0; always @ ( posedge refclk_b) niliO12 <= niliO11; initial nilli10 = 0; always @ ( posedge refclk_b) nilli10 <= nilli9; initial nilli9 = 0; always @ ( posedge refclk_b) nilli9 <= nilli10; event nilli9_event; initial #1 ->nilli9_event; always @(nilli9_event) nilli9 <= {1{1'b1}}; initial nilOi7 = 0; always @ ( posedge refclk_b) nilOi7 <= nilOi8; event nilOi7_event; initial #1 ->nilOi7_event; always @(nilOi7_event) nilOi7 <= {1{1'b1}}; initial nilOi8 = 0; always @ ( posedge refclk_b) nilOi8 <= nilOi7; initial nilOl5 = 0; always @ ( posedge refclk_b) nilOl5 <= nilOl6; event nilOl5_event; initial #1 ->nilOl5_event; always @(nilOl5_event) nilOl5 <= {1{1'b1}}; initial nilOl6 = 0; always @ ( posedge refclk_b) nilOl6 <= nilOl5; initial niO1i3 = 0; always @ ( posedge refclk_b) niO1i3 <= niO1i4; event niO1i3_event; initial #1 ->niO1i3_event; always @(niO1i3_event) niO1i3 <= {1{1'b1}}; initial niO1i4 = 0; always @ ( posedge refclk_b) niO1i4 <= niO1i3; initial niO1O1 = 0; always @ ( posedge refclk_b) niO1O1 <= niO1O2; event niO1O1_event; initial #1 ->niO1O1_event; always @(niO1O1_event) niO1O1 <= {1{1'b1}}; initial niO1O2 = 0; always @ ( posedge refclk_b) niO1O2 <= niO1O1; initial begin nl00i = 0; nl10i = 0; nl10l = 0; nl10O = 0; nl11O = 0; nl1ii = 0; nl1il = 0; nl1iO = 0; nl1li = 0; end always @ (refclk_b or wire_nl01O_PRN or wire_nl01O_CLRN) begin if (wire_nl01O_PRN == 1'b0) begin nl00i <= 1; nl10i <= 1; nl10l <= 1; nl10O <= 1; nl11O <= 1; nl1ii <= 1; nl1il <= 1; nl1iO <= 1; nl1li <= 1; end else if (wire_nl01O_CLRN == 1'b0) begin nl00i <= 0; nl10i <= 0; nl10l <= 0; nl10O <= 0; nl11O <= 0; nl1ii <= 0; nl1il <= 0; nl1iO <= 0; nl1li <= 0; end else if (refclk_b != nl01O_clk_prev && refclk_b == 1'b1) begin nl00i <= nl11O; nl10i <= nl10l; nl10l <= nl10O; nl10O <= nl1ii; nl11O <= nl10i; nl1ii <= nl1il; nl1il <= nl1iO; nl1iO <= nl1li; nl1li <= nilOO; end nl01O_clk_prev <= refclk_b; end assign wire_nl01O_CLRN = (nilOl6 ^ nilOl5), wire_nl01O_PRN = ((nilOi8 ^ nilOi7) & refclk_b_reset_n); event nl00i_event; event nl10i_event; event nl10l_event; event nl10O_event; event nl11O_event; event nl1ii_event; event nl1il_event; event nl1iO_event; event nl1li_event; initial #1 ->nl00i_event; initial #1 ->nl10i_event; initial #1 ->nl10l_event; initial #1 ->nl10O_event; initial #1 ->nl11O_event; initial #1 ->nl1ii_event; initial #1 ->nl1il_event; initial #1 ->nl1iO_event; initial #1 ->nl1li_event; always @(nl00i_event) nl00i <= 1; always @(nl10i_event) nl10i <= 1; always @(nl10l_event) nl10l <= 1; always @(nl10O_event) nl10O <= 1; always @(nl11O_event) nl11O <= 1; always @(nl1ii_event) nl1ii <= 1; always @(nl1il_event) nl1il <= 1; always @(nl1iO_event) nl1iO <= 1; always @(nl1li_event) nl1li <= 1; initial begin nl1lO = 0; end always @ (refclk_b or wire_nl1ll_PRN or wire_nl1ll_CLRN) begin if (wire_nl1ll_PRN == 1'b0) begin nl1lO <= 1; end else if (wire_nl1ll_CLRN == 1'b0) begin nl1lO <= 0; end else if (wire_nl1ll_ENA == 1'b1) if (refclk_b != nl1ll_clk_prev && refclk_b == 1'b1) begin nl1lO <= nilll; end nl1ll_clk_prev <= refclk_b; end assign wire_nl1ll_ENA = (((nl1OO & nl1lO) & (nilii14 ^ nilii13)) & (~ nl1Oi)), wire_nl1ll_CLRN = (nilli10 ^ nilli9), wire_nl1ll_PRN = ((niliO12 ^ niliO11) & refclk_b_reset_n); event nl1lO_event; initial #1 ->nl1lO_event; always @(nl1lO_event) nl1lO <= 1; initial begin nl1Oi = 0; nl1OO = 0; end always @ ( posedge refclk_b or negedge refclk_b_reset_n) begin if (refclk_b_reset_n == 1'b0) begin nl1Oi <= 0; nl1OO <= 0; end else begin nl1Oi <= nl1OO; nl1OO <= tx_elec_idle_comp; end end and(wire_niOll_dataout, (powerdown[0] & powerdown[1]), ~(nil1O)); and(wire_niOlO_dataout, ((~ powerdown[0]) & powerdown[1]), ~(nil1O)); and(wire_niOOi_dataout, ((powerdown[0] & (~ powerdown[1])) & (niiOl24 ^ niiOl23)), ~(nil1O)); and(wire_niOOl_dataout, (((~ powerdown[0]) & (~ powerdown[1])) & (nil1i22 ^ nil1i21)), ~(nil1O)); assign wire_nl00O_dataout = ((~ rtx_pipe_enable) === 1'b1) ? txdetectrxloopback : (txdetectrxloopback & wire_niOlO_dataout); assign wire_nl0il_dataout = ((~ rtx_pipe_enable) === 1'b1) ? txelecidle : wire_nl11i_dataout; assign wire_nl0iO_dataout = ((~ rtx_pipe_enable) === 1'b1) ? revloopback : ((txdetectrxloopback & wire_niOOl_dataout) & (niO1O2 ^ niO1O1)); and(wire_nl0ll_dataout, txswing, rtxswing_sel_ena); and(wire_nl0lO_dataout, wire_niOOl_dataout, rtx_pipe_enable); and(wire_nl0Oi_dataout, wire_niOOi_dataout, rtx_pipe_enable); and(wire_nl0Ol_dataout, wire_niOlO_dataout, rtx_pipe_enable); and(wire_nl0OO_dataout, wire_niOll_dataout, rtx_pipe_enable); assign wire_nl11i_dataout = ((~ nilOO) === 1'b1) ? nl1li : wire_nl11l_o; oper_mux nl11l ( .data({((nil0i20 ^ nil0i19) & nl00i), nl11O, nl10i, nl10l, ((nil0l18 ^ nil0l17) & nl10O), nl1ii, nl1il, nl1iO}), .o(wire_nl11l_o), .sel({rtx_elec_idle_delay[2:1], ((nil0O16 ^ nil0O15) & rtx_elec_idle_delay[0])})); defparam nl11l.width_data = 8, nl11l.width_sel = 3; assign nil1O = ((~ reset_n) | (~ rtx_pipe_enable)), nilll = 1'b0, nillO = 1'b1, nilOO = ((tx_elec_idle_comp | nl1lO) | (~ (niO1i4 ^ niO1i3))), powerstate = {wire_nl0OO_dataout, wire_nl0Ol_dataout, wire_nl0Oi_dataout, wire_nl0lO_dataout}, rev_loopbk = wire_nl0iO_dataout, tx_elec_idle = wire_nl0il_dataout, txd = {txd_ch[43:0]}, txdeemph_int = txdeemph, txdetectrx = wire_nl00O_dataout, txmargin_int = {txmargin[2:0]}, txswing_int = wire_nl0ll_dataout; endmodule //stratixiv_hssi_tx_pipe_interface //synopsys translate_on //VALID FILE `timescale 1 ns / 1 ps module stratixiv_hssi_q_pipe_interface_top ( // General signals pipe_tx_clk, // TX PIPE interface clock == TX Phase Comp write clock pipe_rx_clk, // RX PIPE interface clock == RX Phase Comp read clock refclk_b, // TX Phase Comp FIFO read clock tx_pipe_reset, // synchronized reset i.e TX Phase Comp write clock rx_pipe_reset, // synchronized reset i.e.RX Phase Comp read clock refclk_b_reset, // synchronized reset i.e.TX Phase Comp read clock // CRAM rtx_pipe_enable, // enable tx pipe interface rrx_pipe_enable, // enable rx pipe interface rrdwidth_rx, // Single width = 0, double width = 1 rtx_elec_idle_delay, // programmable delay for controlling output buffer rtxswing_sel_ena, // Enables control of voltage swing level. Implementation // is optional under PIPE 1.87. When this CRAM is not set, full swing is the default mode rrx_detect_bypass, // normal = 0, bypass = 1 rclkcmpinsertpad, // recognize EDB = 0, PAD = 1 insertion for 8b/10b decode errors rind_error_reporting, // Combined reporting = 0 i.e. 8b/10b error|disparity error=> rxstatus=3'b100 // individual reporting = 1 i.e. 8b/10b error => rxstatus = 3'b111; // disparity error => rxstatus = 3'b100 rphystatus_rst_toggle, // no toggle (gen 2) = 0, toggle (option for gen 1) = 1 rphystatus_delay, // programmable delay for the emulation circuitry of successfull power state // transition. Default delay between the change of power state and the assertion // of ~ 13 parallel cycles. Setting of this CRAM to 3'b000 will result in a delay // of ~ 13 parallel cycles. // PLD - PIPE Interface // TX PIPE Interface: Command txdetectrxloopback, // P0 ==> loopback, P1 ==> RX detection txelecidle, // output buffer control // txcompliance, // compliance pattern command powerdown, // power state control txdeemph, // Selects transmitter de-emphasis under Gen 2 speeds txmargin, // Selects transmitter voltage levels txswing, // Selects transmitter voltage swing levels // TX PIPE Interface: Data txd_ch, // TX data path // RX PIPE Interface: Command/Status rxpolarity, // polarity inversion command rxvalid, // indicates symbol lock and valid data rxelecidle, // indicates receiver detection of electrical idle. rxstatus, // encodes receiver status and error codes when receiving data // encodes compliance pattern speed when doing receiver detection // RX PIPE Interface: Data rxd_ch, // RX data path // PHYStatus Generator phystatus, // communicate completion of power state transitions, receiver // detection, rate change // Commands revloopback, // enables reverse parallel loopback when in PIPE bypass mode polinv_rx, // enables polarity inversion when in PIPE bypass mode // PIPE - PCS Inteface // TX PIPE Interface txd, // TX data path to TX Phase Comp FIFO rev_loopbk, // reverse parallel loopback control to MUX after the encoder tx_elec_idle_comp, // compensated txelecidle from the TX Phase Comp FIFO // synchronous to refclk_b // Auto Speed Negotiation rindv_rx, rmaster_rx, rmaster_up_rx, // Auto Negotiation Module speed_change, // asserted when signaling rate change between Gen 1 and Gen 2 is in process. Sychronization occurs within PIPE module speed_change_centrl, speed_change_quad_up, speed_change_quad_down, // RX PIPE Interface rxd, // RX data path from the RX Phase comp FIFO polinv_rx_int, // polarity inversion control; sychronization occurs at 8b/10b decoder // PIPE - PMA Interface // TX PIPE Interface tx_elec_idle, // command to the output buffer txdetectrx, // command to the PMA module for receiver detection powerstate, // decoded power state: used internally to the PIPE interface sigdetni, // ww25_2008 // RX PIPE Interface rx_found, // PMA indication of receiver being detected rx_detect_valid, // Validation of rx_found rxelectricalidle, // electrical idle detection from Rx Electrical Idle inference module txdetectrxin, //shawn powerstatein, //shawn use_powerstatein, //shawn // PHYStatus Generator power_state_transition_done, // asserted when successful power state transition occurs power_state_transition_done_ena, // validates power_state_transition_done, currently tied to 0 // PIPE-DPRIO interface txdeemph_int, // Selects transmitter de-emphasis under Gen 2 speeds txmargin_int, // Selects transmitter voltage levels txswing_int // Selects transmitter voltage swing levels ); //******************************************************************************** // INCLUDE STATEMENTS //******************************************************************************** //******************************************************************************** // I/O SIGNALS //******************************************************************************** // General signals input txdetectrxin; //shawn input [3:0] powerstatein; //shawn input use_powerstatein; //shawn input pipe_tx_clk; input pipe_rx_clk; input refclk_b; input tx_pipe_reset; input rx_pipe_reset; input refclk_b_reset; // CRAM input rtx_pipe_enable; input rrx_pipe_enable; input rrdwidth_rx; input [2:0] rtx_elec_idle_delay; input rtxswing_sel_ena; input rrx_detect_bypass; input rclkcmpinsertpad; input rind_error_reporting; input rphystatus_rst_toggle; input [2:0] rphystatus_delay; // PLD - PIPE Interface // TX PIPE Interface: Command input txdetectrxloopback; input txelecidle; input [1:0] powerdown; input txdeemph; input [2:0] txmargin; input txswing; // TX PIPE Interface: Data input [43:0] txd_ch; // RX PIPE Interface: Command/Status input rxpolarity; // ww25_2008 - Bringing in signal detect from PMA // PMA - PIPE interface input sigdetni; output rxvalid; output rxelecidle; output [2:0] rxstatus; // RX PIPE Interface: Data output [63:0] rxd_ch; // PHYStatus Generator output phystatus; // Commands input revloopback; input polinv_rx; // PIPE - PCS Inteface // TX PIPE Interface output [43:0] txd; output rev_loopbk; input tx_elec_idle_comp; input rindv_rx; input rmaster_rx; // New bundle mode MDIO, selects master quad input rmaster_up_rx; // New bundle mode MDIO, selects master quad // Auto Negotiation Module input speed_change; input speed_change_centrl; input speed_change_quad_up; input speed_change_quad_down; // RX PIPE Interface input [63:0] rxd; output polinv_rx_int; // PIPE - PMA Interface // TX PIPE Interface output tx_elec_idle; output txdetectrx; output [3:0] powerstate; // RX PIPE Interface input rx_found; input rx_detect_valid; input rxelectricalidle; // PHYStatus Generator input power_state_transition_done; input power_state_transition_done_ena; // PIPE-DPRIO interface output txdeemph_int; output [2:0] txmargin_int; output txswing_int; //******************************************************************************** // PARAMETERS //******************************************************************************** //******************************************************************************** // DECLARATIONS //******************************************************************************** wire phystat_ena; reg rx_found_reg_0; reg rx_found_reg_1; reg rx_detect_valid_reg_0; reg rx_detect_valid_reg_1; wire tx_pipe_reset_n; wire rx_pipe_reset_n; wire refclk_b_reset_n; // reset for txelecidle_d_generator // ww25_2008 - New wire for signal detect wire sigdetni; reg txdetectrx_reg_0; reg txdetectrx_reg_1; reg txdetectrx_reg_2; reg txdetectrx_reg_3; reg txdetectrx_reg_4; reg txdetectrx_reg_5; reg txdetectrx_reg_6; reg bypass_rx_found; reg bypass_rx_detect_valid; wire rx_found_int; wire rx_detect_valid_int; wire latched_p0; wire latched_p0s; wire latched_p1; wire latched_p2; wire p1_sync; wire tmp_txdetectrxin; //shawn //******************************************************************************** // ASSIGN STATEMENTS //******************************************************************************** assign phystat_ena = rtx_pipe_enable || rrx_pipe_enable; assign tx_pipe_reset_n = ~tx_pipe_reset; assign rx_pipe_reset_n = ~rx_pipe_reset; assign refclk_b_reset_n = ~refclk_b_reset; assign rx_found_int = rrx_detect_bypass? bypass_rx_found: rx_found_reg_1; assign rx_detect_valid_int = rrx_detect_bypass? bypass_rx_detect_valid: rx_detect_valid_reg_1; assign tmp_txdetectrxin = (use_powerstatein == 1'b1) ? txdetectrxin : txdetectrx; //shawn assign latched_p0 = (use_powerstatein == 1'b1) ? powerstatein[0] : powerstate [0]; //shawn assign latched_p0s = (use_powerstatein == 1'b1) ? powerstatein[1] : powerstate [1]; //shawn; assign latched_p1 = (use_powerstatein == 1'b1) ? powerstatein[2] : powerstate [2]; //shawn; assign latched_p2 = (use_powerstatein == 1'b1) ? powerstatein[3] : powerstate [3]; //shawn; //******************************************************************************** // SUBMODULE INSTANTIATIONS //******************************************************************************** stratixiv_hssi_tx_pipe_interface tx_pipe_interface_inst ( // General signals .clk (pipe_tx_clk), .refclk_b (refclk_b), .reset_n (tx_pipe_reset_n), .refclk_b_reset_n (refclk_b_reset_n), // CRAM .rtx_pipe_enable (rtx_pipe_enable), .rtx_elec_idle_delay (rtx_elec_idle_delay), .rtxswing_sel_ena (rtxswing_sel_ena), // PLD - PIPE Interface // TX PIPE Interface: Command .txdetectrxloopback (txdetectrxloopback), .txelecidle (txelecidle), // .txcompliance (txcompliance), .powerdown (powerdown), .txdeemph (txdeemph), .txmargin (txmargin), .txswing (txswing), // TX PIPE Interface: Data .txd_ch (txd_ch), // Commands .revloopback (revloopback), // PIPE - PCS Inteface // TX PIPE Interface .txd (txd), .rev_loopbk (rev_loopbk), .tx_elec_idle_comp (tx_elec_idle_comp), // PIPE - PMA Interface .tx_elec_idle (tx_elec_idle), .txdetectrx (txdetectrx), // Central PCS .powerstate (powerstate), // PIPE - DPRIO .txdeemph_int (txdeemph_int), .txmargin_int (txmargin_int), .txswing_int (txswing_int) ); stratixiv_hssi_rx_pipe_interface rx_pipe_interface_inst ( // General signals .clk (pipe_rx_clk), .reset_n (rx_pipe_reset_n), // CRAM .rrx_pipe_enable (rrx_pipe_enable), .rrdwidth_rx (rrdwidth_rx), .rclkcmpinsertpad (rclkcmpinsertpad), .rind_error_reporting (rind_error_reporting), // PLD - PIPE Interface // RX PIPE Interface: Command/Status .rxpolarity (rxpolarity), .rxvalid (rxvalid), .rxelecidle (rxelecidle), .rxstatus (rxstatus), // RX PIPE Interface: Data .rxd_ch (rxd_ch), // Commands .polinv_rx (polinv_rx), // PIPE - PCS Inteface // RX PIPE Interface .rxd (rxd), .polinv_rx_int (polinv_rx_int), // TX PIPE Interface // Latched Power State Signals .latched_p1 (latched_p1), .txdetectrx (tmp_txdetectrxin), //shawn (txdetectrx), // PIPE - PMA Interface // TX PIPE Interface .rx_found (rx_found), .rx_found_sync (rx_found_int), .rx_detect_valid (rx_detect_valid), .rx_detect_valid_sync (rx_detect_valid_int), // ww25_2008 - Bringing in signal detect .sigdetni (sigdetni), // RX PIPE Interface .rxelectricalidle (rxelectricalidle) ); stratixiv_hssi_phystatus_generator phystatus_generator_inst ( // General signals .clk (pipe_rx_clk), .reset_n (rx_pipe_reset_n), //CRAM .phystat_ena (phystat_ena), .rphystatus_rst_toggle (rphystatus_rst_toggle), .rphystatus_delay (rphystatus_delay), // PLD Interface .powerdown (powerdown), .phystatus (phystatus), // Latched Power State Signals .latched_p0 (latched_p0), .latched_p0s (latched_p0s), .latched_p1 (latched_p1), .latched_p2 (latched_p2), .rindv_rx(rindv_rx), .rmaster_rx(rmaster_rx), .rmaster_up_rx(rmaster_up_rx), // Auto Negotiation Module .speed_change(speed_change), .speed_change_centrl(speed_change_centrl), .speed_change_quad_up(speed_change_quad_up), .speed_change_quad_down(speed_change_quad_down), // TX PMA Interface .rx_detect_valid (rx_detect_valid_int), // RX PMA Interface .power_state_transition_done (power_state_transition_done), .power_state_transition_done_ena (power_state_transition_done_ena) ); //******************************************************************************** // MAIN CODE //******************************************************************************** always @ (posedge pipe_rx_clk or negedge rx_pipe_reset_n) begin if (!rx_pipe_reset_n) begin rx_detect_valid_reg_0 <= #1 1'b0; rx_found_reg_0 <= #1 1'b0; end else begin rx_detect_valid_reg_0 <= #1 rx_detect_valid; rx_found_reg_0 <= #1 rx_found; end end always @ (posedge pipe_rx_clk or negedge rx_pipe_reset_n) begin if (!rx_pipe_reset_n) begin rx_detect_valid_reg_1 <= #1 1'b0; rx_found_reg_1 <= #1 1'b0; end else begin rx_detect_valid_reg_1 <= #1 rx_detect_valid_reg_0; rx_found_reg_1 <= #1 rx_found_reg_0; end end always @ (posedge pipe_rx_clk or negedge rx_pipe_reset_n) begin if (!rx_pipe_reset_n) begin txdetectrx_reg_0 <= #1 1'b0; end else begin txdetectrx_reg_0 <= #1 tmp_txdetectrxin; // txdetectrx; shawn end end always @ (posedge pipe_rx_clk or negedge rx_pipe_reset_n) begin if (!rx_pipe_reset_n) begin txdetectrx_reg_1 <= #1 1'b0; end else begin txdetectrx_reg_1 <= #1 txdetectrx_reg_0; end end always @ (posedge pipe_rx_clk or negedge rx_pipe_reset_n) begin if (!rx_pipe_reset_n) begin txdetectrx_reg_2 <= #1 1'b0; end else begin txdetectrx_reg_2 <= #1 txdetectrx_reg_1; end end always @ (posedge pipe_rx_clk or negedge rx_pipe_reset_n) begin if (!rx_pipe_reset_n) begin txdetectrx_reg_3 <= #1 1'b0; end else begin txdetectrx_reg_3 <= #1 txdetectrx_reg_2; end end always @ (posedge pipe_rx_clk or negedge rx_pipe_reset_n) begin if (!rx_pipe_reset_n) begin txdetectrx_reg_4 <= #1 1'b0; end else begin txdetectrx_reg_4 <= #1 txdetectrx_reg_3; end end always @ (posedge pipe_rx_clk or negedge rx_pipe_reset_n) begin if (!rx_pipe_reset_n) begin txdetectrx_reg_5 <= #1 1'b0; end else begin txdetectrx_reg_5 <= #1 txdetectrx_reg_4; end end always @ (posedge pipe_rx_clk or negedge rx_pipe_reset_n) begin if (!rx_pipe_reset_n) begin txdetectrx_reg_6 <= #1 1'b0; end else begin txdetectrx_reg_6 <= #1 txdetectrx_reg_5; end end always @ (posedge pipe_rx_clk or negedge rx_pipe_reset_n) begin if (!rx_pipe_reset_n) begin bypass_rx_found <= #1 1'b0; bypass_rx_detect_valid <= #1 1'b0; end else begin bypass_rx_found <= #1 txdetectrx_reg_6; bypass_rx_detect_valid <= #1 txdetectrx_reg_6; end end endmodule // pipe_interface_top `timescale 1 ps / 1 ps module stratixiv_hssi_tx_digis_txclk_gating ( select_n, clk1, clk2, clk1out_n, clk2out_n ); input select_n; input clk1; input clk2; output clk1out_n; output clk2out_n; assign clk1out_n = ~(select_n | clk1); assign clk2out_n = ~(~select_n | clk2); endmodule // txclk_gating `timescale 1 ns / 1 ps module stratixiv_hssi_tx_digi_txclk_ctl (pld_tx_clk, refclk_pma, txpma_local_clk, txrst, scan_mode, gen2ngen1, gen2ngen1_bundle, tx_div2_sync_centrl, tx_div2_sync_quad_up, tx_div2_sync_quad_down, rindv_tx, rtxwrclksel, rtxrdclksel, rdwidth_tx, rfreerun_tx, rauto_speed_ena, rfreq_sel, rtxpcsclkpwdn, rmaster_tx, rmaster_up_tx, rself_sw_en_tx, refclk_b, wr_clk_pos, fifo_rd_clk, tx_clk_out, refclk_b_raw, wr_clk_pos_raw, fifo_rd_clk_raw, tx_div2_sync_out ); // Clock Inputs input pld_tx_clk; // PLD clock from PLD clock trees, the transmit clock from XGMII. input refclk_pma; // Quad based clk from TXPLL input txpma_local_clk; // Local channel TX PMA clock. // Control Inputs input txrst; // reset for the tx_pcs input scan_mode; // Scan mode enable signal for selecting scan_clk from refclk_pma // New Control Inputs input gen2ngen1; // from PMA for PCIexp Gen1/Gen2 datawidth scaling input gen2ngen1_bundle; // from PMA for PCIexp Gen1/Gen2 datawidth scaling in x4 and x8 input tx_div2_sync_centrl; // divided clock from the central channel (x2, x4 mode) input tx_div2_sync_quad_up; // divided clock from quad above (> x4 mode) input tx_div2_sync_quad_down; // divided clock from quad below (> x4 mode) // MDIO Inputs input rindv_tx; // Selects between indiv chan. mode and bundled mode input rtxwrclksel; // Selects which clock writes into FIFO input rtxrdclksel; // Selects which clock reads from FIFO and also clocks reest of TX logic input rdwidth_tx; // divide by 1 or 2 before feeding to FIFO read clock input rfreerun_tx; // Select whether divider is permamently enabled (free -running) or divider should be enabled / reset by TX PCS reset // New MDIO Inputs input rauto_speed_ena; // auto speed negotiation enable input rfreq_sel; // freq scaling or data width scaling input rtxpcsclkpwdn; // TX clocking power down enable input rmaster_tx; // New bundle mode MDIO, selects master quad input rmaster_up_tx; // New bundle mode MDIO, selects master quad input rself_sw_en_tx; // enables self-switch to have correct /2 clock in all quads in bundle mode // Removed Inputs // input tx_div2_sync_in_ch0; // from the channel zero tx_div2_sync_out // input tx_div2_sync_in_q0_ch0; // From channel0 of Master Quad // input rphfifo_master_sel_tx; // TX Phase comp. FIFO tx_div2_sync selection CRAM // Clock Outputs wtih CTS output refclk_b; // Drives the tx channel clock output wr_clk_pos; // Drives tx phase comp fifo write side output fifo_rd_clk; // Drives tx phase comp fifo read side // Clock Outputs to PLD, w/o CTS output tx_clk_out; // Drives to the PLD clock tree -- unconnected // New Clock Outputs with CTS output refclk_b_raw; // same as refclk_b, but with no clock gating output wr_clk_pos_raw; // same as wr_clk_pos, but with no clock gating output fifo_rd_clk_raw; // same as fifo_rd_clk, but with no clock gating // Control Outputs output tx_div2_sync_out; // Synchronizes the divided by two clock reg fifo_rd_clk_by2; reg gen2ngen1_local_sync; reg [1:0] counter; wire tx_rst_n; wire tx_div2_sync; wire dynamic_div2ndiv1; wire gen2ngen1_local; wire tx_div2_this_quad; wire tx_div2_this_channel; wire tx_div2_other_quad; wire force_master; wire rtxpcsclkpwdn_nscan; // shawn initial begin ------ initial begin fifo_rd_clk_by2 = 1'b0; end // shawn initial end ------ wire select_div1_n; wire clk1out_n; wire clk2out_n; // Old bundle logic: // Select between the local synchronization signal or the global synchronization signal (either from Channel0 or // Channel0 of Master Quad //assign tx_div2_sync = rindv_tx ? tx_div2_sync_out : tx_div2_sync_in; // assign tx_div2_sync = (rphfifo_master_sel_tx == 1'b0) ? tx_div2_sync_in_q0_ch0 : // (rindv_tx == 1'b0) ? tx_div2_sync_in_ch0 : // (rauto_speed_ena & ~rfreq_sel) ? (tx_div2_sync_out | ~gen2ngen1_local_sync) : tx_div2_sync_out; always @(posedge txrst or posedge refclk_b_raw) begin if (txrst) counter <= #1 2'b00; else if ((rauto_speed_ena & ~rfreq_sel & rself_sw_en_tx) & ~force_master) counter <= #1 counter + 1'b1; end assign force_master = ((counter == 2'b11) && (rauto_speed_ena & ~rfreq_sel & rself_sw_en_tx)) ? 1'b1 : 1'b0; assign tx_div2_sync = (rmaster_tx || force_master) ? tx_div2_this_quad : tx_div2_other_quad; assign tx_div2_this_quad = (rindv_tx || force_master) ? tx_div2_this_channel : tx_div2_sync_centrl; assign tx_div2_this_channel = (rauto_speed_ena && ~rfreq_sel) ? (tx_div2_sync_out | ~gen2ngen1_local_sync) : tx_div2_sync_out; assign tx_div2_other_quad = rmaster_up_tx ? tx_div2_sync_quad_up : tx_div2_sync_quad_down; assign gen2ngen1_local = (rindv_tx == 1'b0) ? gen2ngen1_bundle : gen2ngen1; always @(posedge txrst or posedge refclk_b_raw) begin if (txrst) gen2ngen1_local_sync <= #1 1'b0; else gen2ngen1_local_sync <= #1 gen2ngen1_local; end assign dynamic_div2ndiv1 = rdwidth_tx | (gen2ngen1_local_sync & rauto_speed_ena & ~rfreq_sel); // Reset for Divide-by-2 FF assign tx_rst_n = (rfreerun_tx) ? 1'b1 : ~txrst; assign rtxpcsclkpwdn_nscan = rtxpcsclkpwdn & ~scan_mode; // Full speed clock for TX PCS assign refclk_b_raw = (scan_mode || rtxrdclksel) ? refclk_pma : txpma_local_clk; assign refclk_b = rtxpcsclkpwdn_nscan ? 1'b1 : refclk_b_raw; // Divide-by-2 FF always @(negedge tx_rst_n or posedge refclk_b_raw) begin if (~tx_rst_n) fifo_rd_clk_by2 <= 1'b1; else fifo_rd_clk_by2 <= tx_div2_sync; // local divided clock end assign tx_div2_sync_out = ~fifo_rd_clk_by2; // TX FIFO read clock: could be fast or divided by 2 // old code: // assign fifo_rd_clk = ((rdwidth_tx == 1'b0) || scan_mode) ? refclk_b_raw : fifo_rd_clk_by2; assign select_div1_n = ~(scan_mode | ~dynamic_div2ndiv1); stratixiv_hssi_tx_digis_txclk_gating txclk_gating ( .select_n(select_div1_n), .clk1(refclk_b_raw), .clk2(fifo_rd_clk_by2), .clk1out_n(clk1out_n), .clk2out_n(clk2out_n) ); assign fifo_rd_clk_raw = ~(clk1out_n | clk2out_n); assign fifo_rd_clk = rtxpcsclkpwdn_nscan ? 1'b1 : fifo_rd_clk_raw; // TX FIFO write clock: used internal clock when in BIST or scan or HIP assign wr_clk_pos_raw = (scan_mode || rtxwrclksel) ? fifo_rd_clk_raw : pld_tx_clk; assign wr_clk_pos = rtxpcsclkpwdn_nscan ? 1'b1 : wr_clk_pos_raw; // TX Clock Out assign tx_clk_out = fifo_rd_clk; // drives PLD clock tree endmodule // txclk_ctl `timescale 1ps / 1ps module stratixiv_hssi_tx_digis_ram8x49_syn ( data_in, clk, fifo_wr, rst_l, fifo_re, data_out ); input clk; input rst_l; input [7:0] fifo_wr; input [7:0] fifo_re; input [53:0] data_in; output [53:0] data_out; parameter read_access_time = 0; parameter write_access_time = 0; parameter ram_width = 54; reg [ram_width-1:0] data_out_i; reg [ram_width-1:0] ram_array_d_0, ram_array_d_1, ram_array_d_2, ram_array_d_3, ram_array_d_4, ram_array_d_5, ram_array_d_6, ram_array_d_7, ram_array_q_0, ram_array_q_1, ram_array_q_2, ram_array_q_3, ram_array_q_4, ram_array_q_5, ram_array_q_6, ram_array_q_7; wire [ram_width-1:0] data_reg_0, data_reg_1, data_reg_2, data_reg_3, data_reg_4, data_reg_5, data_reg_6, data_reg_7; wire we, re_l; assign we = 1'b1; assign re_l = 1'b0; /* Modelling the read port */ /* Assuming address trigerred operation only */ assign data_reg_0 = ( fifo_wr[0] == 1'b1 ) ? data_in : ram_array_q_0, data_reg_1 = ( fifo_wr[1] == 1'b1 ) ? data_in : ram_array_q_1, data_reg_2 = ( fifo_wr[2] == 1'b1 ) ? data_in : ram_array_q_2, data_reg_3 = ( fifo_wr[3] == 1'b1 ) ? data_in : ram_array_q_3, data_reg_4 = ( fifo_wr[4] == 1'b1 ) ? data_in : ram_array_q_4, data_reg_5 = ( fifo_wr[5] == 1'b1 ) ? data_in : ram_array_q_5, data_reg_6 = ( fifo_wr[6] == 1'b1 ) ? data_in : ram_array_q_6, data_reg_7 = ( fifo_wr[7] == 1'b1 ) ? data_in : ram_array_q_7; assign data_out = re_l ? 54'h21000000000000 : data_out_i; always @( ram_array_q_0 or ram_array_q_1 or ram_array_q_2 or ram_array_q_3 or ram_array_q_4 or ram_array_q_5 or ram_array_q_6 or ram_array_q_7 or fifo_re ) begin case ( fifo_re ) // synopsys parallel_case full_case 8'b00000001 : data_out_i = ram_array_q_0; 8'b00000010 : data_out_i = ram_array_q_1; 8'b00000100 : data_out_i = ram_array_q_2; 8'b00001000 : data_out_i = ram_array_q_3; 8'b00010000 : data_out_i = ram_array_q_4; 8'b00100000 : data_out_i = ram_array_q_5; 8'b01000000 : data_out_i = ram_array_q_6; 8'b10000000 : data_out_i = ram_array_q_7; default : data_out_i = ram_array_q_0; endcase end /* Modelling the write port */ always @(posedge clk or negedge rst_l) begin if(~rst_l) begin ram_array_q_0 <= #write_access_time 54'h21000000000000; ram_array_q_1 <= #write_access_time 54'h21000000000000; ram_array_q_2 <= #write_access_time 54'h21000000000000; ram_array_q_3 <= #write_access_time 54'h21000000000000; ram_array_q_4 <= #write_access_time 54'h21000000000000; ram_array_q_5 <= #write_access_time 54'h21000000000000; ram_array_q_6 <= #write_access_time 54'h21000000000000; ram_array_q_7 <= #write_access_time 54'h21000000000000; end else begin ram_array_q_0 <= #write_access_time ram_array_d_0; ram_array_q_1 <= #write_access_time ram_array_d_1; ram_array_q_2 <= #write_access_time ram_array_d_2; ram_array_q_3 <= #write_access_time ram_array_d_3; ram_array_q_4 <= #write_access_time ram_array_d_4; ram_array_q_5 <= #write_access_time ram_array_d_5; ram_array_q_6 <= #write_access_time ram_array_d_6; ram_array_q_7 <= #write_access_time ram_array_d_7; end end always @( we or data_reg_0 or data_reg_1 or data_reg_2 or data_reg_3 or data_reg_4 or data_reg_5 or data_reg_6 or data_reg_7 or ram_array_q_0 or ram_array_q_1 or ram_array_q_2 or ram_array_q_3 or ram_array_q_4 or ram_array_q_5 or ram_array_q_6 or ram_array_q_7 ) begin if(we) begin ram_array_d_0 = data_reg_0; ram_array_d_1 = data_reg_1; ram_array_d_2 = data_reg_2; ram_array_d_3 = data_reg_3; ram_array_d_4 = data_reg_4; ram_array_d_5 = data_reg_5; ram_array_d_6 = data_reg_6; ram_array_d_7 = data_reg_7; end else begin ram_array_d_0 = ram_array_q_0; ram_array_d_1 = ram_array_q_1; ram_array_d_2 = ram_array_q_2; ram_array_d_3 = ram_array_q_3; ram_array_d_4 = ram_array_q_4; ram_array_d_5 = ram_array_q_5; ram_array_d_6 = ram_array_q_6; ram_array_d_7 = ram_array_q_7; end end endmodule `timescale 1ps / 1ps module stratixiv_hssi_tx_digis_ph_fifo ( // inputs rst_wclk, rst_rclk, wr_clk, rd_clk, bypass_en, //en, lowlatency_en, we, re, din, rphfifo_regmode_tx, rindv_tx, rauto_speed_ena, reset_pc_ptrs, reset_pc_ptrs_centrl, reset_pc_ptrs_quad_up, reset_pc_ptrs_quad_down, rmaster_tx, rmaster_up_tx, // outputs data_out, ph_fifo_full, ph_fifo_empty, wptr_bin, rptr_bin ); // ======= // inputs // ======= input rst_wclk; // wr clk rst input rst_rclk; // rd clk rst input wr_clk; // Write Clock input rd_clk; // Read Clock input bypass_en; // FIFO bypass enable - only for Altera internal debug //input en; // Disable FIFO, reset wptr and rptr // only for Altera internal debug input lowlatency_en; // Enable low latency option input we; // PLD dynamic write pointer enable input re; // PLD dynamic read pointer enable input [53:0] din; // 10-bit code-group bus from deskew module. input rphfifo_regmode_tx; input rindv_tx; input rmaster_tx; input rmaster_up_tx; input rauto_speed_ena; input reset_pc_ptrs; input reset_pc_ptrs_centrl; input reset_pc_ptrs_quad_up; input reset_pc_ptrs_quad_down; // ======= // outputs // ======= output ph_fifo_full; // Indicates overflow (rd_clk) output ph_fifo_empty; // FIFO empty (rd_clk) output [53:0] data_out; // output data (rd_clk synchronous if not FIFO bypass) output [2:0] wptr_bin; // wptr test bus output [2:0] rptr_bin; // rptr test bus // =================== // signal declaration // =================== reg [ 7:0] wptr, rptr; reg [ 7:0] wptr0_pre; reg [ 7:0] wptr0; reg [ 7:0] wptr1; reg [ 2:0] rptr_gray; reg [ 2:0] rptr_gray0; reg [ 2:0] rptr0; reg [ 2:0] rptr1; reg [ 7:0] rptr1_onehot; reg [ 2:0] wptr_bin; // wptr test bus reg [ 2:0] rptr_bin; // rptr test bus reg first_rd; // first read after reset reg [53:0] ram_data_out; wire [53:0] ram_data_out_pre; reg ph_fifo_full, ph_fifo_empty; reg ph_fifo_full_pre; // Invert rst for new FIFO wire rst_n; wire [3:0] fifo_cnt; reg [3:0] fifo_cnt_pre; reg [2:0] wptr1_bin; reg [2:0] rptr1_bin_wclk; wire reset_ptrs_local; reg reset_ptrs_local_sync1; reg reset_ptrs_local_sync2; // ============= // functionality // ============= assign rst_n = ~rst_wclk; assign data_out[53:0] = (bypass_en)? din : ram_data_out; assign reset_ptrs_local = rauto_speed_ena & (rmaster_tx ? (rindv_tx ? reset_pc_ptrs : reset_pc_ptrs_centrl) : (rmaster_up_tx ? reset_pc_ptrs_quad_up : reset_pc_ptrs_quad_down)); //newly added fifo_cnt and fifo_cnt_pre logic for full/empty flag use assign fifo_cnt = (wptr1_bin == rptr1_bin_wclk) ? ((rst_wclk != 1'b1) ? ((fifo_cnt_pre==4'd7 || fifo_cnt_pre==4'd6 || fifo_cnt_pre==4'd8)?4'd8:4'd0) : 4'd0) : ((wptr1_bin > rptr1_bin_wclk) ? (wptr1_bin - rptr1_bin_wclk) : (4'd8 - {1'b0,(rptr1_bin_wclk - wptr1_bin)} )); // ww25.2008 always @ (posedge rst_wclk or posedge wr_clk) begin if (rst_wclk == 1'b1) begin reset_ptrs_local_sync1 <= #1 1'b0; reset_ptrs_local_sync2 <= #1 1'b0; end else if (rphfifo_regmode_tx) begin reset_ptrs_local_sync1 <= #1 1'b0; reset_ptrs_local_sync2 <= #1 1'b0; end else begin reset_ptrs_local_sync1 <= #1 reset_ptrs_local; reset_ptrs_local_sync2 <= #1 reset_ptrs_local_sync1; end end // always @ (posedge rst_wclk or posedge wr_clk) //ECO for S4GX to fix metastability issue // replace the 1st FF with new flop w/o reset // replace the 2nd FF with an enhanced flop always @ (posedge wr_clk) begin if (reset_ptrs_local_sync2 || rphfifo_regmode_tx) rptr0 <= #1 3'h0; else rptr0 <= #1 rptr_gray; end // always @ (posedge rst_wclk or posedge wr_clk) always @ (posedge rst_wclk or posedge wr_clk) begin if (rst_wclk == 1'b1) rptr1 <= #1 3'h0; else if (reset_ptrs_local_sync2 || rphfifo_regmode_tx) rptr1 <= #1 3'h0; else rptr1 <= #1 rptr0; end // always @ (posedge rst_wclk or posedge wr_clk) always @ (posedge rst_wclk or posedge wr_clk) begin if (rst_wclk == 1'b1) begin wptr <= #1 8'h01; wptr0_pre <= #1 8'h01; wptr0 <= #1 8'h01; wptr1 <= #1 8'h01; ph_fifo_full_pre <= #1 1'b0; ph_fifo_full <= #1 1'b0; ph_fifo_empty <= #1 1'b0; fifo_cnt_pre <= #1 4'b0000; // fifo_cnt previous value end // if (rst_wclk == 1'b1) else if (reset_ptrs_local_sync2 || rphfifo_regmode_tx) begin wptr <= #1 8'h01; wptr0_pre <= #1 8'h01; wptr0 <= #1 8'h01; wptr1 <= #1 8'h01; ph_fifo_full_pre <= #1 1'b0; ph_fifo_full <= #1 1'b0; ph_fifo_empty <= #1 1'b0; fifo_cnt_pre <= #1 4'b0000; // fifo_cnt previous value end // if (reset_ptrs_local_sync2) else begin fifo_cnt_pre <= #1 fifo_cnt; ph_fifo_full <= #1 ph_fifo_full_pre; wptr0_pre <= #1 wptr; wptr0 <= #1 wptr0_pre; wptr1 <= #1 wptr0; // wptr operation if (we == 1'b1) wptr <= #1 {wptr[6:0],wptr[7]}; // full condition //$if ({wptr1[6:0],wptr1[7]} == rptr1_onehot) //new full flag requirement if ((fifo_cnt==4'd8) && (!ph_fifo_empty)) ph_fifo_full_pre <= #1 1'b1; //else if (ph_fifo_full_pre == 1'b1 & (wptr1 != rptr1_onehot)) //now become sticky flag until reset //ph_fifo_full_pre <= #1 1'b0; // empty condition //$if ({rptr1_onehot[6:0],rptr1_onehot[7]} == wptr1) //new empty flag requirement if (({wptr1[6:0],wptr1[7]} == rptr1_onehot) && (fifo_cnt_pre==4'd1 || fifo_cnt_pre==4'd0) && (!ph_fifo_full_pre)) //==1 to cover if wptr not moving ph_fifo_empty <= #1 1'b1; //else if (ph_fifo_empty == 1'b1 & ({wptr1[6:0],wptr1[7]} != rptr1_onehot)) //now become sticky flag until reset //ph_fifo_empty <= #1 1'b0; end end // always @ (posedge rst_wclk or posedge wr_clk) // End of ECO always @ (posedge rst_rclk or posedge rd_clk) begin if (rst_rclk == 1'b1) begin first_rd <= #1 1'b1; rptr <= #1 8'h20; end else if (reset_ptrs_local || rphfifo_regmode_tx) begin first_rd <= #1 1'b1; rptr <= #1 8'h20; end else begin if (first_rd == 1'b1 && re == 1'b1) first_rd <= #1 1'b0; // read pointer operation if (re == 1'b1) // low latency option, advance 2 on the first read if (first_rd == 1'b1 && lowlatency_en == 1'b1) rptr <= #1 {rptr[5:0],rptr[7:6]}; else rptr <= #1 {rptr[6:0],rptr[7]}; end end // always @ (posedge rst_rclk or posedge rd_clk) // Instantiate FIFO CORE Module. Fifo 8 words deep, 44 bits wide /*ram8x44_syn ram8x44_syn_1 ( .rst_l (rst_n), .clk (wr_clk), .fifo_wr (wptr), .data_in (din), .fifo_re (rptr), .data_out (ram_data_out_pre) ); */ stratixiv_hssi_tx_digis_ram8x49_syn ram8x49_syn_1 ( .rst_l (rst_n), .clk (wr_clk), .fifo_wr (wptr), .data_in (din), .fifo_re (rptr), .data_out (ram_data_out_pre) ); always @ (posedge rst_rclk or posedge rd_clk) begin if (rst_rclk) begin ram_data_out <= #1 54'h20000000000000; end else if (rphfifo_regmode_tx) begin ram_data_out <= #1 din; end else begin ram_data_out <= #1 ram_data_out_pre; end end // always @ (posedge rst_rclk or posedge rd_clk) always@(wptr) begin case(wptr) 8'h01: wptr_bin = 3'h0; 8'h02: wptr_bin = 3'h1; 8'h04: wptr_bin = 3'h2; 8'h08: wptr_bin = 3'h3; 8'h10: wptr_bin = 3'h4; 8'h20: wptr_bin = 3'h5; 8'h40: wptr_bin = 3'h6; 8'h80: wptr_bin = 3'h7; default: wptr_bin = 3'h7; endcase // case(wptr) end // always@ (wptr) always@(wptr1) begin case(wptr1) 8'h01: wptr1_bin = 3'h0; 8'h02: wptr1_bin = 3'h1; 8'h04: wptr1_bin = 3'h2; 8'h08: wptr1_bin = 3'h3; 8'h10: wptr1_bin = 3'h4; 8'h20: wptr1_bin = 3'h5; 8'h40: wptr1_bin = 3'h6; 8'h80: wptr1_bin = 3'h7; default: wptr1_bin = 3'h7; endcase // case(wptr1) end // always@ (wptr1) always@(rptr) begin case(rptr) 8'h01: rptr_bin = 3'h0; 8'h02: rptr_bin = 3'h1; 8'h04: rptr_bin = 3'h2; 8'h08: rptr_bin = 3'h3; 8'h10: rptr_bin = 3'h4; 8'h20: rptr_bin = 3'h5; 8'h40: rptr_bin = 3'h6; 8'h80: rptr_bin = 3'h7; default: rptr_bin = 3'h7; endcase // case(rptr) end // always@ (rptr) always @ (posedge rst_rclk or posedge rd_clk) begin if (rst_rclk == 1'b1) rptr_gray <= #1 3'h0; else rptr_gray <= #1 rptr_gray0; end always@(rptr) begin case(rptr) 8'h01: rptr_gray0 = 3'h0; 8'h02: rptr_gray0 = 3'h1; 8'h04: rptr_gray0 = 3'h3; 8'h08: rptr_gray0 = 3'h2; 8'h10: rptr_gray0 = 3'h6; 8'h20: rptr_gray0 = 3'h7; 8'h40: rptr_gray0 = 3'h5; 8'h80: rptr_gray0 = 3'h4; default: rptr_gray0 = 3'h0; endcase // case(rptr) end // always@ (rptr) always@(rptr1) begin case(rptr1) 3'h0: rptr1_onehot = 8'h01; 3'h1: rptr1_onehot = 8'h02; 3'h3: rptr1_onehot = 8'h04; 3'h2: rptr1_onehot = 8'h08; 3'h6: rptr1_onehot = 8'h10; 3'h7: rptr1_onehot = 8'h20; 3'h5: rptr1_onehot = 8'h40; 3'h4: rptr1_onehot = 8'h80; default: rptr1_onehot = 8'h01; endcase // case(rptr1) end // always@ (rptr1) always@(rptr1) begin case(rptr1) 3'h0: rptr1_bin_wclk = 3'h0; 3'h1: rptr1_bin_wclk = 3'h1; 3'h3: rptr1_bin_wclk = 3'h2; 3'h2: rptr1_bin_wclk = 3'h3; 3'h6: rptr1_bin_wclk = 3'h4; 3'h7: rptr1_bin_wclk = 3'h5; 3'h5: rptr1_bin_wclk = 3'h6; 3'h4: rptr1_bin_wclk = 3'h7; default: rptr1_bin_wclk = 3'h0; endcase // case(rptr1) end // always@ (rptr1) endmodule // ph_fifo_tx `timescale 1 ps / 1ps module stratixiv_hssi_tx_digi_tx_ctrl ( // inputs soft_reset, fifo_wr_clk, fifo_rd_clk, refclk_b_in, scan_mode, rindv_tx, //is_lane0, p_rlpbk, selftest_en, rdwidth_tx, txfifo_dis, rtxfifo_urst_en, txfifo_urst, rtxfifo_lowlatency_en, rtxphfifopldctl_en, rtx_pipe_enable, pld_we, pld_rd_dis, txd, txd_extend, rforce_disp, tx_data_sg, tx_control_sg, rxd_lpbk, redund_ctl, txd_redun, rforce_kchar, rforce_echar, // PCS bypass rtxpcsbypass_en, // TX PIPE signals txdetectrxloopback, powerdown, revloopback, txswing, txdeemph, txmargin, // RX PIPE signals rxpolarity, polinv_rx, eidleinfersel, // New inputs for new bundling scheme and new PCIE features like autospeed reset_pc_ptrs, reset_pc_ptrs_centrl, reset_pc_ptrs_quad_up, reset_pc_ptrs_quad_down, gen2ngen1, gen2ngen1_bundle, dis_pc_byte, wr_enable_centrl, wr_enable_quad_up, wr_enable_quad_down, rd_enable_centrl, rd_enable_quad_up, rd_enable_quad_down, fifo_select_in_centrl, fifo_select_in_quad_up, fifo_select_in_quad_down, // New MDIO for new bundling scheme and new PCIE features like autospeed rauto_speed_ena, rfreq_sel, rphfifo_regmode_tx, rmaster_tx, rmaster_up_tx, // outputs txd_extend_tc, tx_data_tc, tx_ctl_tc, tx_data_9_tc, rd_enable_sync, k_det, d21_5_eq_n, d2_2_eq_n, wr_enable_out, rd_enable_out, fifo_select_out, ph_fifo_full, ph_fifo_empty, soft_reset_wclk1, soft_reset_rclk1, pipe_electric_idle, // TX PIPE signals txdetectrxloopback_int, powerdown_int, revloopback_int, phfifo_txswing, phfifo_txdeemph, phfifo_txmargin, // RX PIPE signals rxpolarity_int, polinv_rx_int, gray_eidleinfersel, // test bus // fifo_select_out // test_bus[8], bit re-used in test bus wr_enable2, // test_bus[7] wptr_bin, // test_bus[6:4] rd_enable2, // test_bus[3] rptr_bin // test_bus[2:0] ); // *_xgmii = from XGMII interface // *_sg = from selftest_gen // *_rc = from rx_ctrl // ====== // inputs // ====== input soft_reset; // Reset input fifo_wr_clk; // Used to be wr_clk_pos input fifo_rd_clk; // Coming from txclk_xg_ctl input refclk_b_in; // The local reference clock used by the internal // transmit logic. Used to be tx_clk. input scan_mode; // scan enable input p_rlpbk; // Control bit/pin to enable parallel loop back at XGMII input selftest_en; // To select XGMII signals from selftest_gen (*_sg) input rdwidth_tx; // Control bit to support double-width data bus on xgmii. // When set, fifo_wr_clk is running at half frequency // as refclk_b_in and 2-byte/code-group of data should be sampled // at the rising edge of fifo_wr_clk. When DWIDTH=1'b0, the // fifo_wr_clk is running at the same frequency as refclk_b_in. input rindv_tx; //input is_lane0; // lane 0 of the quad input [39:0] rxd_lpbk; // rx data from rx_ctrl. input txfifo_dis; input [39:0] txd; // Tx data // These extension bits may be used to force disparity or other uses. input [3:0] txd_extend; // Extend txd by 2 bits. Used to force disparity. input [31:0] tx_data_sg; // The xgmii data from selftest_gen.. input [3:0] tx_control_sg; // The xgmii control from selftest_gen. input [39:0] txd_redun; // redundant Tx data , unused input [3:0] redund_ctl; // redundant Tx data select, unused input rforce_disp; // Acting with {txd_extend, TXD[9] forces current disparity to 1 or 0 input rforce_kchar; input rforce_echar; input rtxfifo_urst_en; // user reset CRAM enable input txfifo_urst; // user reset input rtxfifo_lowlatency_en; // low latency enable input rtxphfifopldctl_en; // CRAM to enable PLD controlled write/read enable input rtx_pipe_enable; // enable pipe input pld_we; // PLD phase comp. fifo we, level active input pld_rd_dis; // PLD phase comp. fifo rd dis, edge active // PCS Bypass mode input rtxpcsbypass_en; // TX PIPE interface signals input txdetectrxloopback; //input txelecidle; txd[9] //input txcompliance; txd[10] and txd[32] input [1:0] powerdown; input revloopback; input txswing; input txdeemph; input [2:0] txmargin; // RX PIPE interface signals input rxpolarity; input polinv_rx; input [2:0] eidleinfersel; // New Inputs for new bundling scheme and new PCIE features like autospeed input reset_pc_ptrs; input reset_pc_ptrs_centrl; input reset_pc_ptrs_quad_up; input reset_pc_ptrs_quad_down; input gen2ngen1; input gen2ngen1_bundle; input dis_pc_byte; input wr_enable_centrl; input wr_enable_quad_up; input wr_enable_quad_down; input rd_enable_centrl; input rd_enable_quad_up; input rd_enable_quad_down; input fifo_select_in_centrl; input fifo_select_in_quad_up; input fifo_select_in_quad_down; // New MDIO for new bundling scheme and new PCIE features like autospeed input rauto_speed_ena; input rfreq_sel; input rphfifo_regmode_tx; input rmaster_tx; input rmaster_up_tx; // ======= // outputs // ======= output [1:0] txd_extend_tc; // This will go to the encoder. This is serialized (muxed) txd_extend_int. But // txd_extend_int has to go through the FIFOs first to be serialized. output wr_enable_out; // ch0 wr_enable1 output for X4/X8 mode output rd_enable_out; // ch0 rd_enable1 output for X4/X8 mode output [15:0] tx_data_tc; // 8-bit data passed onto the internal transmit logic. output [1:0] tx_ctl_tc; // Control passed onto the internal transmit logic. // Can be bit 8 of the 10-bit code group. output [1:0] tx_data_9_tc; // Bit 9 of the 10-bit code group passed onto the internal transmit logic. output rd_enable_sync; output [1:0] k_det; output [1:0] d21_5_eq_n; output [1:0] d2_2_eq_n; output fifo_select_out; // New output for Rev.B output ph_fifo_full; // fifo full flag output ph_fifo_empty; // fifo empty flag output soft_reset_wclk1; // synchronized reset for BIST; output soft_reset_rclk1; // syncrhonized reset for PIPE output pipe_electric_idle; // PIPE electric idle bit // TX PIPE interface signals output txdetectrxloopback_int; //output txelecidle; txd[9] //output txcompliance; txd[10] and txd[32] output [1:0] powerdown_int; output revloopback_int; output phfifo_txswing; output phfifo_txdeemph; output [2:0] phfifo_txmargin; // RX PIPE interface signals output rxpolarity_int; output polinv_rx_int; output [2:0] gray_eidleinfersel; // test bus // testbus[8] = fifo_select_out // testbus[7] = wr_enable2 // testbus[6:4] = wptr_bin // testbus[3] = rd_enable2 // testbus[2:0] = rptr_bin output wr_enable2; output [2:0] wptr_bin; output rd_enable2; output [2:0] rptr_bin; // ================ // internal signals // ================ reg rd_enable_sync; // Begin: 22 Bits output of this module (44 to 22 / 22 to 22) wire [15:0] tx_data_tc; wire [1:0] tx_ctl_tc; wire [1:0] tx_data_9_tc; wire [1:0] txd_extend_tc; reg [15:0] tx_data_tc_mux; //temp holder for non PCS bypass data branch before mux reg [1:0] tx_ctl_tc_mux; //temp holder for non PCS bypass branch before mux reg [1:0] tx_data_9_tc_mux; //temp holder for non PCS bypass branch before mux reg [1:0] txd_extend_tc_mux; //temp holder for non PCS bypass branch before mux // End: 22 bits output of this module reg [19:0] tx_data_lt; wire [39:0] tx_data; wire [53:0] din0; wire [39:0] fifo_data_out; wire [1:0] tx_data_9_tc_d; wire [1:0] tx_data_9_tc_d_others; wire [1:0] tx_ctl_tc_d; wire [1:0] tx_ctl_tc_d_others; wire [15:0] tx_data_tc_d; wire [17:0] tx_data_tc_d_others; wire [1:0] d21_5_eq_n_d; wire [1:0] d2_2_eq_n_d; reg [1:0] d21_5_eq_n; reg [1:0] d2_2_eq_n; reg [1:0] k_det; reg [1:0] k_det_sync1; reg fifo_select_out; reg txfifo_en_refclk0; reg txfifo_en_refclk1; reg wr_enable0; reg wr_enable0p5; reg wr_enable1; reg wr_enable2; reg rd_enable0; reg rd_enable0p5; reg rd_enable1; reg rd_enable2; wire [3:0] txd_extend_int; wire [1:0] txd_extend_tc_d;// This is registered and sent out to the encoder as txd_extend_tc. // This is serialized (muxed) txd_extend_int. But // txd_extend_int has to go through the FIFOs first to be serialized. wire [1:0] txd_extend_low, txd_extend_high; wire [17:0] txd_data_extend_tmp; reg txfifo_en_rclk0; reg txfifo_en_rclk1; wire txfifo_en; wire soft_reset_local; reg soft_reset_wclk0; reg soft_reset_wclk1_b4scan; wire soft_reset_wclk1_wire; reg soft_reset_rclk0; reg soft_reset_rclk1_b4scan; wire soft_reset_rclk1_wire; wire [53:0] data_out_temp; reg pld_rd_dis0, pld_rd_dis1, pld_rd_dis2, pld_rd_dis_edge; wire [2:0] wptr_bin,rptr_bin; reg pipe_electric_idle; // PIPE electric idle bit // register rd_enable_sync to fast clock domain. Necessary to send out low // byte first after soft_reset. reg rd_enable_sync_refclk_b_in; // PIPE command signals wire [4:0] pipe_cmd; wire [4:0] pipe_cmd_out; wire rxpolarity_int; wire polinv_rx_int; wire rdwidth_or_auto; wire gen2ngen1_int; reg gen2ngen1_reg; reg gen2ngen1_sync; wire [4:0] pipe_tx_trans; // PIPE transmitter settings // {txswing, txdeemph, txmargin} wire [4:0] pipe_tx_trans_out; reg [2:0] gray_eidleinfersel; // ============= // functionality // ============= assign soft_reset_wclk1 = soft_reset_wclk1_wire; assign soft_reset_rclk1 = soft_reset_rclk1_wire; assign txd_extend_int = rforce_disp ? txd_extend : 4'b0000; // GiGE Idle Detection, replaced in 8b10b encoder assign d21_5_eq_n_d[0] = ({tx_ctl_tc_d[0], tx_data_tc_d[7:0]} != {9'b010110101}); assign d21_5_eq_n_d[1] = ({tx_ctl_tc_d[1], tx_data_tc_d[15:8]} != {9'b010110101}); assign d2_2_eq_n_d[0] = ({tx_ctl_tc_d[0], tx_data_tc_d[7:0]} != {9'b001000010}); assign d2_2_eq_n_d[1] = ({tx_ctl_tc_d[1], tx_data_tc_d[15:8]} != {9'b001000010}); assign wr_enable_out = wr_enable1; assign rd_enable_out = rd_enable1; // 2-17-04 BT: Tied the tx_data[9] to 1'b0 in selftest mode since it effects the // disparity input in the 8B/10B encoder assign tx_data[19:0] = (p_rlpbk) ? rxd_lpbk[19:0] : (selftest_en) ? {1'b0, tx_control_sg[1], tx_data_sg[15:8], 1'b0, tx_control_sg[0], tx_data_sg[7:0]} : (redund_ctl) ? txd_redun[19:0] : txd[19:0]; // enable 3G double-width BIST by mapping tx_data_sg[15:8] & tx_control_sg[1] to the 3rd symbol location assign tx_data[39:20] = (p_rlpbk) ? rxd_lpbk[39:20] : (selftest_en) ? {1'b0, tx_control_sg[3], tx_data_sg[31:24], 1'b0, tx_control_sg[1], tx_data_sg[15:8]} : (redund_ctl) ? txd_redun[39:20] : txd[39:20]; assign txfifo_en = (rtxfifo_urst_en)? ~txfifo_urst : 1'b1; // PIPE electric idle is on txd[10] //assign pipe_electric_idle = txd_extend_tc_d[0]; assign soft_reset_local = soft_reset | (rtxfifo_urst_en && txfifo_urst); // PIPE cmd assign pipe_cmd = {powerdown, txdetectrxloopback, revloopback, 1'b0}; assign revloopback_int = txfifo_dis? pipe_cmd[1] : pipe_cmd_out[1]; assign txdetectrxloopback_int = txfifo_dis? pipe_cmd[2] : pipe_cmd_out[2]; assign powerdown_int = txfifo_dis? pipe_cmd[4:3]: pipe_cmd_out[4:3]; assign rxpolarity_int = rxpolarity; assign polinv_rx_int = polinv_rx; assign gen2ngen1_int = rindv_tx ? gen2ngen1: gen2ngen1_bundle; //************************************ // Synchronization of gen2ngen1 //************************************ always @ (posedge soft_reset or posedge refclk_b_in) begin if(soft_reset) begin gen2ngen1_reg <= 1'b0; gen2ngen1_sync <= 1'b0; end else begin gen2ngen1_reg <= gen2ngen1_int; gen2ngen1_sync <= gen2ngen1_reg; end end // always @ (posedge soft_reset or posedge refclk_b_in) assign rdwidth_or_auto = (rdwidth_tx | (rauto_speed_ena & ~rfreq_sel & gen2ngen1_sync)); assign pipe_tx_trans = {txswing, txdeemph, txmargin}; assign phfifo_txswing = txfifo_dis? pipe_tx_trans[4]: pipe_tx_trans_out[4]; assign phfifo_txdeemph = txfifo_dis? pipe_tx_trans[3]: pipe_tx_trans_out[3]; assign phfifo_txmargin = txfifo_dis? pipe_tx_trans [2:0]: pipe_tx_trans_out[2:0]; // synchronize reset input (in refclk_b domain) always @(posedge soft_reset_local or posedge fifo_wr_clk) begin if (soft_reset_local) begin soft_reset_wclk0 <= #1 1'b1; soft_reset_wclk1_b4scan <= #1 1'b1; end else begin soft_reset_wclk0 <= #1 1'b0; soft_reset_wclk1_b4scan <= #1 soft_reset_wclk0; end end // always @ (posedge soft_reset_local or posedge fifo_wr_clk) assign soft_reset_wclk1_wire = (scan_mode)? 1'b0 : soft_reset_wclk1_b4scan; // synchronize reset input (in refclk_b domain) and balance it with fifo_wr_clk reset always @(posedge soft_reset_local or posedge fifo_rd_clk) begin if (soft_reset_local) begin soft_reset_rclk0 <= #1 1'b1; soft_reset_rclk1_b4scan <= #1 1'b1; end else begin soft_reset_rclk0 <= #1 1'b0; soft_reset_rclk1_b4scan <= #1 soft_reset_rclk0; end end // always @ (posedge soft_reset_local or posedge fifo_rd_clk) assign soft_reset_rclk1_wire = (scan_mode)? 1'b0 : soft_reset_rclk1_b4scan; // write enable always @ (posedge soft_reset_wclk1_wire or posedge fifo_wr_clk) begin if (soft_reset_wclk1_wire) begin wr_enable0 <= #1 1'b0; wr_enable0p5 <= #1 1'b0; wr_enable1 <= #1 1'b0; wr_enable2 <= #1 1'b0; end else begin //wr_enable0 <= txfifo_en; //wr_enable0 <= 1'b1; wr_enable0 <= #1 ~(rauto_speed_ena & dis_pc_byte); wr_enable0p5 <= #1 wr_enable0; wr_enable1 <= #1 (rtxphfifopldctl_en)? (wr_enable0p5 && pld_we) : wr_enable0p5; wr_enable2 <= #1 rmaster_tx ? (rindv_tx ? wr_enable1 : wr_enable_centrl) : (rmaster_up_tx ? wr_enable_quad_up : wr_enable_quad_down); end end // always @ (posedge soft_reset_wclk1 or posedge fifo_wr_clk) assign din0 = {pipe_tx_trans,pipe_cmd,txd_extend_int[3:2], tx_data[39:20], txd_extend_int[1:0], tx_data[19:0]}; // Instantiate new FIFO stratixiv_hssi_tx_digis_ph_fifo ph_fifo_tx_1 ( .rst_wclk(soft_reset_wclk1_wire), .rst_rclk(soft_reset_rclk1_wire), .wr_clk(fifo_wr_clk), .rd_clk(fifo_rd_clk), .bypass_en(txfifo_dis), //.en(1'b1), .lowlatency_en(rtxfifo_lowlatency_en), .we(wr_enable2), .re(rd_enable2), .din(din0), .data_out(data_out_temp), .ph_fifo_full(ph_fifo_full), .ph_fifo_empty(ph_fifo_empty), .wptr_bin(wptr_bin), .rptr_bin(rptr_bin), .rphfifo_regmode_tx(rphfifo_regmode_tx), .rindv_tx(rindv_tx), .rmaster_tx(rmaster_tx), .rmaster_up_tx(rmaster_up_tx), .rauto_speed_ena(rauto_speed_ena), .reset_pc_ptrs(reset_pc_ptrs), .reset_pc_ptrs_centrl(reset_pc_ptrs_centrl), .reset_pc_ptrs_quad_up(reset_pc_ptrs_quad_up), .reset_pc_ptrs_quad_down(reset_pc_ptrs_quad_down) ); assign pipe_tx_trans_out = data_out_temp[53:49]; assign pipe_cmd_out = data_out_temp[48: 44]; assign txd_extend_high = data_out_temp[43: 42]; assign fifo_data_out[39:20] = data_out_temp[41: 22]; assign txd_extend_low = data_out_temp[21: 20]; assign fifo_data_out[19:0]= data_out_temp[19: 0]; // Modified Byte Serializer logic to use fifo_select_out to ping-pong between // low and high banks of FIFO during normal mode // Toggle between {19,9} and {39,29} when DWIDTH is set, else fixed to {19,9} assign tx_data_9_tc_d = (~txfifo_dis & rd_enable_sync & (~rdwidth_or_auto | fifo_select_out) & ~rforce_kchar & ~rforce_echar) ? {fifo_data_out[19], fifo_data_out[9]} : (~txfifo_dis & rd_enable_sync & (rdwidth_or_auto & ~fifo_select_out) & ~rforce_kchar & ~rforce_echar) ? {fifo_data_out[39], fifo_data_out[29]} : (txfifo_dis & (~rdwidth_or_auto | ~fifo_select_out) & ~rforce_kchar & ~rforce_echar) ? {tx_data[19], tx_data[9]} : tx_data_9_tc_d_others ; assign tx_data_9_tc_d_others = (~rforce_kchar & rforce_echar) ? 2'b00 : (txfifo_dis & rdwidth_or_auto & fifo_select_out & ~rforce_kchar & ~rforce_echar) ? {tx_data_lt[19], tx_data_lt[9]} : 2'b00; // 8th bit in each word. Toggle between {18,8} and {38,28} when DWIDTH is set, else fixed to {18,8} assign tx_ctl_tc_d = (~txfifo_dis & rd_enable_sync & (~rdwidth_or_auto | fifo_select_out) & ~rforce_kchar & ~rforce_echar) ? {fifo_data_out[18], fifo_data_out[8]} : (~txfifo_dis & rd_enable_sync & (rdwidth_or_auto & ~fifo_select_out) & ~rforce_kchar & ~rforce_echar) ? {fifo_data_out[38], fifo_data_out[28]} : (txfifo_dis & (~rdwidth_or_auto | ~fifo_select_out) & ~rforce_kchar & ~rforce_echar) ? {tx_data[18], tx_data[8]} : tx_ctl_tc_d_others ; // When transmitting Error(FE) or bypassing FIFO, transmit 11 in the former case and transmit bypassed data/ctl in the latter assign tx_ctl_tc_d_others = (~rforce_kchar & rforce_echar) ? 2'b11 : (txfifo_dis & rdwidth_or_auto & fifo_select_out & ~rforce_kchar & ~rforce_echar) ? {tx_data_lt[18], tx_data_lt[8]} : 2'b11; // After rd_enable_sync goes high, start transmitting. Initially, fifo_select_out is zero, so MSByte transmitted first. // Transmit data if not forced Error or K-char. assign txd_extend_tc_d = txd_data_extend_tmp[17:16]; assign tx_data_tc_d = txd_data_extend_tmp[15:0]; assign txd_data_extend_tmp = (~txfifo_dis & rd_enable_sync & (~rdwidth_or_auto | fifo_select_out) & ~rforce_kchar & ~rforce_echar) ? {txd_extend_low, fifo_data_out[17:10], fifo_data_out[7:0]} : (~txfifo_dis & rd_enable_sync & (rdwidth_or_auto & ~fifo_select_out) & ~rforce_kchar & ~rforce_echar) ? {txd_extend_high, fifo_data_out[37:30], fifo_data_out[27:20]} : (txfifo_dis & (~rdwidth_or_auto | ~fifo_select_out) & ~rforce_kchar & ~rforce_echar) ? {txd_extend_int[1:0], tx_data[17:10], tx_data[7:0]} : tx_data_tc_d_others; // When transmitting Error(FE) or bypassing FIFO, transmit FE in the former case and transmit bypassed data/ctl in the latter assign tx_data_tc_d_others = (~rforce_kchar & rforce_echar) ? {2'h0,8'b11111110, 8'b11111110} : (txfifo_dis & rdwidth_or_auto & fifo_select_out & ~rforce_kchar & ~rforce_echar) ? {txd_extend_int[3:2],tx_data_lt[17:10],tx_data_lt[7:0]} : (~rindv_tx) ? {2'h0,8'b00000111, 8'b00000111} : {2'h0,8'b10111100, 8'b10111100} ; // read enable & // read enable sync (for byte serializer output enable) always @(posedge soft_reset_rclk1_wire or posedge fifo_rd_clk) begin if (soft_reset_rclk1_wire) begin pld_rd_dis0 <= #1 1'b0; pld_rd_dis1 <= #1 1'b0; pld_rd_dis2 <= #1 1'b0; pld_rd_dis_edge <= #1 1'b0; rd_enable0 <= #1 1'b0; rd_enable0p5 <= #1 1'b0; rd_enable1 <= #1 1'b0; rd_enable2 <= #1 1'b0; txfifo_en_rclk0 <= #1 1'b0; txfifo_en_rclk1 <= #1 1'b0; rd_enable_sync <= #1 1'b0; end else begin pld_rd_dis0 <= #1 pld_rd_dis; pld_rd_dis1 <= #1 pld_rd_dis0; pld_rd_dis2 <= #1 pld_rd_dis1; pld_rd_dis_edge <= #1 (pld_rd_dis2 != pld_rd_dis1); //rd_enable0 <= txfifo_en; // rd_enable0 <= 1'b1; rd_enable0 <= #1 ~(rauto_speed_ena & dis_pc_byte); rd_enable0p5 <= #1 rd_enable0; rd_enable1 <= #1 (rtxphfifopldctl_en)? (rd_enable0p5 && !pld_rd_dis_edge) : rd_enable0p5; rd_enable2 <= #1 rmaster_tx ? (rindv_tx ? rd_enable1 : rd_enable_centrl) : (rmaster_up_tx ? rd_enable_quad_up : rd_enable_quad_down); //txfifo_en_rclk0 <= txfifo_en; txfifo_en_rclk0 <= #1 1'b1; txfifo_en_rclk1 <= #1 txfifo_en_rclk0; // start with valid data, so rd_enable_sync serves as dout valid // ideally should be "rptr_bin == 3'd7", // but fifo_data_out is registered (1 clk delay). rd_enable_sync is // used in high/low byte selection enable if (rphfifo_regmode_tx) rd_enable_sync <= #1 1'b1; else if (rd_enable_sync == 1'b0 && rptr_bin == 3'd0) rd_enable_sync <= #1 rmaster_tx ? (rindv_tx ? rd_enable1 : rd_enable_centrl) : (rmaster_up_tx ? rd_enable_quad_up : rd_enable_quad_down); else if (txfifo_en_rclk1 == 1'b0) rd_enable_sync <= #1 1'b0; end end // always @ (posedge soft_reset_rclk1 or posedge fifo_rd_clk) always @(posedge soft_reset or posedge refclk_b_in) begin if (soft_reset) begin tx_data_9_tc_mux <= #1 2'b00; tx_ctl_tc_mux <= #1 2'b00; tx_data_tc_mux <= #1 16'h0000; txd_extend_tc_mux <= #1 2'b00; tx_data_lt <= #1 20'h00000; d21_5_eq_n <= #1 2'b11; d2_2_eq_n <= #1 2'b11; k_det_sync1 <= #1 2'b00; k_det <= #1 2'b00; pipe_electric_idle <= #1 1'b0; end else begin tx_data_9_tc_mux <= #1 tx_data_9_tc_d; tx_ctl_tc_mux <= #1 tx_ctl_tc_d; tx_data_tc_mux <= #1 tx_data_tc_d; // PIPE enabled, txd[21] & txd[10] are used as PIPE electric idle // hence in PIPE mode, txd[21] & txd[10](crd_enforce_value) are forced to txd[20] & txd[9] // (crd_enforce_enable) to have crd negative enable. // crd positive enable is not provided in PIPE mode txd_extend_tc_mux <= #1 (rtx_pipe_enable) ? {txd_extend_tc_d[1], tx_data_9_tc_d[0]} : txd_extend_tc_d; pipe_electric_idle <= #1 txd_extend_tc_d[0]; d21_5_eq_n <= #1 d21_5_eq_n_d; d2_2_eq_n <= #1 d2_2_eq_n_d; k_det <= #1 k_det_sync1; if (rdwidth_or_auto && ~fifo_select_out) tx_data_lt <= #1 tx_data[39:20]; if ({tx_ctl_tc_d[0], tx_data_tc_d[7:0]} == 9'b110111100) k_det_sync1[0] <= #1 1'b1; else k_det_sync1[0] <= #1 1'b0; if ({tx_ctl_tc_d[1], tx_data_tc_d[15:8]} == 9'b110111100) k_det_sync1[1] <= #1 1'b1; else k_det_sync1[1] <= #1 1'b0; end end // always @ (posedge soft_reset or posedge refclk_b_in) // byte serializer high/low select always @(posedge soft_reset or posedge refclk_b_in) begin if (soft_reset) begin rd_enable_sync_refclk_b_in <= #1 1'b0; txfifo_en_refclk0 <= #1 1'b0; txfifo_en_refclk1 <= #1 1'b0; fifo_select_out <= #1 1'b0; end else begin //txfifo_en_refclk0 <= txfifo_en; // txfifo_en_refclk0 <= 1'b1; txfifo_en_refclk0 <= #1 ~(rauto_speed_ena & dis_pc_byte); txfifo_en_refclk1 <= #1 txfifo_en_refclk0; if (txfifo_en_refclk1 ==1'b0) rd_enable_sync_refclk_b_in <= #1 1'b0; else if (rd_enable_sync_refclk_b_in == 1'b0) rd_enable_sync_refclk_b_in <= #1 rd_enable2; // was ~fifo_select_in, it allows 1 cycle to send the signal across x4, x8 channels if (rd_enable_sync_refclk_b_in == 1'b1) fifo_select_out <= #1 rmaster_tx ? (rindv_tx ? ~fifo_select_out : ~fifo_select_in_centrl) : (rmaster_up_tx ? ~fifo_select_in_quad_up : ~fifo_select_in_quad_down); else fifo_select_out <= #1 1'b0; end end // always @ (posedge soft_reset or posedge refclk_b_in) assign tx_data_9_tc = (rtxpcsbypass_en & (~rdwidth_or_auto))? tx_data_9_tc_d : tx_data_9_tc_mux; assign tx_ctl_tc = (rtxpcsbypass_en & (~rdwidth_or_auto))? tx_ctl_tc_d : tx_ctl_tc_mux; assign tx_data_tc = (rtxpcsbypass_en & (~rdwidth_or_auto))? tx_data_tc_d : tx_data_tc_mux; assign txd_extend_tc = (rtxpcsbypass_en & (~rdwidth_or_auto))? txd_extend_tc_d : txd_extend_tc_mux; // LMC bin to gray for eidlinfersel always @ (posedge fifo_wr_clk or posedge soft_reset_wclk1_wire) begin if (soft_reset_wclk1_wire) begin gray_eidleinfersel <= 3'b000; end else begin case (eidleinfersel) 3'b000: gray_eidleinfersel <= 3'b000; 3'b001: gray_eidleinfersel <= 3'b001; 3'b010: gray_eidleinfersel <= 3'b011; 3'b011: gray_eidleinfersel <= 3'b010; 3'b100: gray_eidleinfersel <= 3'b110; 3'b101: gray_eidleinfersel <= 3'b111; 3'b110: gray_eidleinfersel <= 3'b101; 3'b111: gray_eidleinfersel <= 3'b100; default: gray_eidleinfersel <= 3'b000; endcase end end endmodule // tx_ctrl //IP Functional Simulation Model //VERSION_BEGIN 12.0 cbx_mgl 2012:05:31:20:09:47:SJ cbx_simgen 2012:05:31:20:08:35:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 // Copyright (C) 1991-2012 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // You may only use these simulation model output files for simulation // purposes and expressly not for synthesis or any other purposes (in which // event Altera disclaims all warranties of any kind). //synopsys translate_off //synthesis_resources = lut 211 mux21 446 oper_add 10 oper_selector 88 `timescale 1 ps / 1 ps module stratixiv_hssi_tx_digi_bist_gen ( bist_ctl_sg, bist_data_sg, rbist_sel, rbisten_tx, rcxpat_chnl_sel, rdwidth_tx, rpma_doublewidth_tx, rpmadwidth_tx, soft_reset, tx_clk) /* synthesis synthesis_clearbox=1 */; output [1:0] bist_ctl_sg; output [15:0] bist_data_sg; input [1:0] rbist_sel; input rbisten_tx; input [1:0] rcxpat_chnl_sel; input rdwidth_tx; input rpma_doublewidth_tx; input rpmadwidth_tx; input soft_reset; input tx_clk; reg ni001l45; reg ni001l46; reg nii00O39; reg nii00O40; reg nii01O41; reg nii01O42; reg nii0il37; reg nii0il38; reg nii0li35; reg nii0li36; reg nii0lO33; reg nii0lO34; reg nii0OO31; reg nii0OO32; reg nii1OO43; reg nii1OO44; reg niii0i23; reg niii0i24; reg niii0O21; reg niii0O22; reg niii1i29; reg niii1i30; reg niii1l27; reg niii1l28; reg niii1O25; reg niii1O26; reg niillO19; reg niillO20; reg niilOi17; reg niilOi18; reg niilOO15; reg niilOO16; reg niiO0i10; reg niiO0i9; reg niiO0O7; reg niiO0O8; reg niiO1i13; reg niiO1i14; reg niiO1l11; reg niiO1l12; reg niiOll5; reg niiOll6; reg niiOOl3; reg niiOOl4; reg nil11i1; reg nil11i2; reg n100i; reg n100l; reg n100O; reg n101i; reg n101l; reg n101O; reg n10ii; reg n10il; reg n10iO; reg n10li; reg n10ll; reg n10lO; reg n10Oi; reg n10Ol; reg n10OO; reg n110i; reg n110l; reg n110O; reg n111i; reg n111l; reg n111O; reg n11ii; reg n11il; reg n11iO; reg n11li; reg n11ll; reg n11lO; reg n11Oi; reg n11Ol; reg n11OO; reg n1i0i; reg n1i0l; reg n1i0O; reg n1i1i; reg n1i1l; reg n1i1O; reg n1iii; reg n1iil; reg n1iiO; reg n1ili; reg n1ill; reg n1ilO; reg n1iOi; reg n1iOl; reg n1iOO; reg n1l0i; reg n1l0l; reg n1l1i; reg n1l1l; reg n1l1O; reg n1lii; reg nliliO; reg nlOOil; reg nlOOiO; reg nlOOli; reg nlOOll; reg nlOOlO; reg nlOOOi; reg nlOOOl; reg nlOOOO; reg n1liO; reg nl00il; reg nl00iO; reg nl00li; reg nl00ll; reg nl00lO; reg nl00Oi; reg nl00Ol; reg nl00OO; reg nl0i0i; reg nl0i0l; reg nl0i0O; reg nl0i1i; reg nl0i1l; reg nl0i1O; reg nl0iii; reg nl0iil; reg nl0iiO; reg nl0ili; reg nl0ill; reg nl0ilO; reg nl0iOi; reg nl0iOl; reg nl0iOO; reg nl0l0i; reg nl0l0l; reg nl0l0O; reg nl0l1i; reg nl0l1l; reg nl0l1O; reg nl0lii; reg nl0lil; reg nl0liO; reg nl0lli; reg nl0lll; reg nl0llO; reg nl0lOi; reg nl0lOl; reg nl0lOO; reg nl0O0i; reg nl0O0l; reg nl0O0O; reg nl0O1i; reg nl0O1l; reg nl0O1O; reg nl0Oii; reg nl0Oil; reg nl0OiO; reg nl0Oli; reg nl0Oll; reg nl0OlO; reg nl0OOi; reg nl0OOl; reg nli11i; reg nl0OOO_clk_prev; wire wire_nl0OOO_PRN; reg nli11O; reg n0lOi; reg niO0l; reg niO0O; reg niOii; reg niOil; reg niOiO; reg niOli; reg niOll; reg niOlO; reg niOOi; reg niOOl; reg niOOO; reg nl00i; reg nl00l; reg nl00O; reg nl01i; reg nl01l; reg nl01O; reg nl0ii; reg nl0il; reg nl0iO; reg nl0li; reg nl0ll; reg nl0lO; reg nl0Oi; reg nl0Ol; reg nl0OO; reg nl10i; reg nl10l; reg nl10O; reg nl11i; reg nl11l; reg nl11O; reg nl1ii; reg nl1il; reg nl1iO; reg nl1li; reg nl1ll; reg nl1lO; reg nl1Oi; reg nl1Ol; reg nl1OO; reg nli0i; reg nli0l; reg nli0O; reg nli1i; reg nli1l; reg nli1O; reg nliil; reg nlili; reg nliiO_clk_prev; wire wire_nliiO_CLRN; wire wire_nliiO_PRN; wire wire_n000i_dataout; wire wire_n000l_dataout; wire wire_n000O_dataout; wire wire_n001i_dataout; wire wire_n001l_dataout; wire wire_n001O_dataout; wire wire_n00i_dataout; wire wire_n00ii_dataout; wire wire_n00il_dataout; wire wire_n00iO_dataout; wire wire_n00l_dataout; wire wire_n00li_dataout; wire wire_n00ll_dataout; wire wire_n00lO_dataout; wire wire_n00O_dataout; wire wire_n010i_dataout; wire wire_n010l_dataout; wire wire_n010O_dataout; wire wire_n011i_dataout; wire wire_n011l_dataout; wire wire_n011O_dataout; wire wire_n01i_dataout; wire wire_n01ii_dataout; wire wire_n01il_dataout; wire wire_n01l_dataout; wire wire_n01li_dataout; wire wire_n01ll_dataout; wire wire_n01lO_dataout; wire wire_n01O_dataout; wire wire_n01Oi_dataout; wire wire_n01Ol_dataout; wire wire_n01OO_dataout; wire wire_n0i_dataout; wire wire_n0ii_dataout; wire wire_n0il_dataout; wire wire_n0iO_dataout; wire wire_n0l_dataout; wire wire_n0l0O_dataout; wire wire_n0li_dataout; wire wire_n0ll_dataout; wire wire_n0llO_dataout; wire wire_n0lO_dataout; wire wire_n0O_dataout; wire wire_n0O0i_dataout; wire wire_n0O1i_dataout; wire wire_n0Oi_dataout; wire wire_n0Oii_dataout; wire wire_n0Ol_dataout; wire wire_n0Oli_dataout; wire wire_n0OO_dataout; wire wire_n0OOi_dataout; wire wire_n1i_dataout; wire wire_n1l_dataout; wire wire_n1lli_dataout; wire wire_n1lll_dataout; wire wire_n1llO_dataout; wire wire_n1lOl_dataout; wire wire_n1lOO_dataout; wire wire_n1O_dataout; wire wire_n1O0i_dataout; wire wire_n1O0l_dataout; wire wire_n1O0O_dataout; wire wire_n1O1i_dataout; wire wire_n1O1l_dataout; wire wire_n1O1O_dataout; wire wire_n1Oii_dataout; wire wire_n1Oil_dataout; wire wire_n1OiO_dataout; wire wire_n1Oli_dataout; wire wire_n1OlO_dataout; wire wire_n1OOi_dataout; wire wire_n1OOl_dataout; wire wire_ni0i_dataout; wire wire_ni0l_dataout; wire wire_ni0O_dataout; wire wire_ni0OO_dataout; wire wire_ni11i_dataout; wire wire_ni1i_dataout; wire wire_ni1l_dataout; wire wire_ni1O_dataout; wire wire_nii_dataout; wire wire_nii0i_dataout; wire wire_nii0l_dataout; wire wire_nii0O_dataout; wire wire_nii1i_dataout; wire wire_nii1l_dataout; wire wire_nii1O_dataout; wire wire_niii_dataout; wire wire_niiii_dataout; wire wire_niiil_dataout; wire wire_niiiO_dataout; wire wire_niil_dataout; wire wire_niili_dataout; wire wire_niill_dataout; wire wire_niilO_dataout; wire wire_niiO_dataout; wire wire_niiOi_dataout; wire wire_niiOl_dataout; wire wire_niiOO_dataout; wire wire_nil_dataout; wire wire_nil0i_dataout; wire wire_nil0l_dataout; wire wire_nil0O_dataout; wire wire_nil1i_dataout; wire wire_nil1l_dataout; wire wire_nil1O_dataout; wire wire_nili_dataout; wire wire_nilii_dataout; wire wire_nilil_dataout; wire wire_niliO_dataout; wire wire_nill_dataout; wire wire_nilli_dataout; wire wire_nilll_dataout; wire wire_nillO_dataout; wire wire_nilO_dataout; wire wire_nilOi_dataout; wire wire_nilOl_dataout; wire wire_nilOO_dataout; wire wire_niO_dataout; wire wire_niO00i_dataout; wire wire_niO00l_dataout; wire wire_niO00O_dataout; wire wire_niO01i_dataout; wire wire_niO01l_dataout; wire wire_niO01O_dataout; wire wire_niO0ii_dataout; wire wire_niO0il_dataout; wire wire_niO0iO_dataout; wire wire_niO0li_dataout; wire wire_niO0ll_dataout; wire wire_niO0lO_dataout; wire wire_niO0Oi_dataout; wire wire_niO0Ol_dataout; wire wire_niO0OO_dataout; wire wire_niO10i_dataout; wire wire_niO10l_dataout; wire wire_niO10O_dataout; wire wire_niO11l_dataout; wire wire_niO11O_dataout; wire wire_niO1i_dataout; wire wire_niO1ii_dataout; wire wire_niO1il_dataout; wire wire_niO1iO_dataout; wire wire_niO1l_dataout; wire wire_niO1li_dataout; wire wire_niO1ll_dataout; wire wire_niO1lO_dataout; wire wire_niO1O_dataout; wire wire_niO1Oi_dataout; wire wire_niO1Ol_dataout; wire wire_niO1OO_dataout; wire wire_niOi_dataout; wire wire_niOi0i_dataout; wire wire_niOi0l_dataout; wire wire_niOi0O_dataout; wire wire_niOi1i_dataout; wire wire_niOi1l_dataout; wire wire_niOi1O_dataout; wire wire_niOiii_dataout; wire wire_niOiil_dataout; wire wire_niOiiO_dataout; wire wire_niOili_dataout; wire wire_niOill_dataout; wire wire_niOilO_dataout; wire wire_niOiOi_dataout; wire wire_niOiOl_dataout; wire wire_niOiOO_dataout; wire wire_niOl_dataout; wire wire_niOl0i_dataout; wire wire_niOl0l_dataout; wire wire_niOl0O_dataout; wire wire_niOl1i_dataout; wire wire_niOl1l_dataout; wire wire_niOl1O_dataout; wire wire_niOlii_dataout; wire wire_niOlil_dataout; wire wire_niOliO_dataout; wire wire_niOlli_dataout; wire wire_niOlll_dataout; wire wire_niOllO_dataout; wire wire_niOlOi_dataout; wire wire_niOlOl_dataout; wire wire_niOlOO_dataout; wire wire_niOO_dataout; wire wire_niOO0i_dataout; wire wire_niOO0l_dataout; wire wire_niOO0O_dataout; wire wire_niOO1i_dataout; wire wire_niOO1l_dataout; wire wire_niOO1O_dataout; wire wire_niOOii_dataout; wire wire_niOOil_dataout; wire wire_niOOiO_dataout; wire wire_niOOli_dataout; wire wire_niOOll_dataout; wire wire_niOOlO_dataout; wire wire_niOOOi_dataout; wire wire_niOOOl_dataout; wire wire_niOOOO_dataout; wire wire_nl000i_dataout; wire wire_nl000l_dataout; wire wire_nl000O_dataout; wire wire_nl001i_dataout; wire wire_nl001l_dataout; wire wire_nl001O_dataout; wire wire_nl00ii_dataout; wire wire_nl010i_dataout; wire wire_nl010l_dataout; wire wire_nl010O_dataout; wire wire_nl011i_dataout; wire wire_nl011l_dataout; wire wire_nl011O_dataout; wire wire_nl01ii_dataout; wire wire_nl01il_dataout; wire wire_nl01iO_dataout; wire wire_nl01li_dataout; wire wire_nl01ll_dataout; wire wire_nl01lO_dataout; wire wire_nl01Oi_dataout; wire wire_nl01Ol_dataout; wire wire_nl01OO_dataout; wire wire_nl0i_dataout; wire wire_nl0l_dataout; wire wire_nl0O_dataout; wire wire_nl100i_dataout; wire wire_nl100l_dataout; wire wire_nl100O_dataout; wire wire_nl101i_dataout; wire wire_nl101l_dataout; wire wire_nl101O_dataout; wire wire_nl10ii_dataout; wire wire_nl10il_dataout; wire wire_nl10iO_dataout; wire wire_nl10li_dataout; wire wire_nl10ll_dataout; wire wire_nl10lO_dataout; wire wire_nl10Oi_dataout; wire wire_nl10Ol_dataout; wire wire_nl10OO_dataout; wire wire_nl110i_dataout; wire wire_nl110l_dataout; wire wire_nl110O_dataout; wire wire_nl111i_dataout; wire wire_nl111l_dataout; wire wire_nl111O_dataout; wire wire_nl11ii_dataout; wire wire_nl11il_dataout; wire wire_nl11iO_dataout; wire wire_nl11li_dataout; wire wire_nl11ll_dataout; wire wire_nl11lO_dataout; wire wire_nl11Oi_dataout; wire wire_nl11Ol_dataout; wire wire_nl11OO_dataout; wire wire_nl1i_dataout; wire wire_nl1i0i_dataout; wire wire_nl1i0l_dataout; wire wire_nl1i0O_dataout; wire wire_nl1i1i_dataout; wire wire_nl1i1l_dataout; wire wire_nl1i1O_dataout; wire wire_nl1iii_dataout; wire wire_nl1iil_dataout; wire wire_nl1iiO_dataout; wire wire_nl1ili_dataout; wire wire_nl1ill_dataout; wire wire_nl1ilO_dataout; wire wire_nl1iOi_dataout; wire wire_nl1iOl_dataout; wire wire_nl1iOO_dataout; wire wire_nl1l_dataout; wire wire_nl1l0i_dataout; wire wire_nl1l0l_dataout; wire wire_nl1l0O_dataout; wire wire_nl1l1i_dataout; wire wire_nl1l1l_dataout; wire wire_nl1l1O_dataout; wire wire_nl1lii_dataout; wire wire_nl1lil_dataout; wire wire_nl1liO_dataout; wire wire_nl1lli_dataout; wire wire_nl1lll_dataout; wire wire_nl1llO_dataout; wire wire_nl1lOi_dataout; wire wire_nl1lOl_dataout; wire wire_nl1lOO_dataout; wire wire_nl1O_dataout; wire wire_nl1O0i_dataout; wire wire_nl1O0l_dataout; wire wire_nl1O0O_dataout; wire wire_nl1O1i_dataout; wire wire_nl1O1l_dataout; wire wire_nl1O1O_dataout; wire wire_nl1Oii_dataout; wire wire_nl1Oil_dataout; wire wire_nl1OiO_dataout; wire wire_nl1Oli_dataout; wire wire_nl1Oll_dataout; wire wire_nl1OlO_dataout; wire wire_nl1OOi_dataout; wire wire_nl1OOl_dataout; wire wire_nl1OOO_dataout; wire wire_nli_dataout; wire wire_nli00i_dataout; wire wire_nli00l_dataout; wire wire_nli00O_dataout; wire wire_nli01i_dataout; wire wire_nli01l_dataout; wire wire_nli01O_dataout; wire wire_nli0ii_dataout; wire wire_nli0il_dataout; wire wire_nli0iO_dataout; wire wire_nli0li_dataout; wire wire_nli10i_dataout; wire wire_nli10l_dataout; wire wire_nli10O_dataout; wire wire_nli1ii_dataout; wire wire_nli1il_dataout; wire wire_nli1iO_dataout; wire wire_nli1li_dataout; wire wire_nli1ll_dataout; wire wire_nli1lO_dataout; wire wire_nli1Oi_dataout; wire wire_nli1Ol_dataout; wire wire_nli1OO_dataout; wire wire_nlii_dataout; wire wire_nlil_dataout; wire wire_nlil0O_dataout; wire wire_nlilii_dataout; wire wire_nlilil_dataout; wire wire_nlill_dataout; wire wire_nlilli_dataout; wire wire_nlilll_dataout; wire wire_nlillO_dataout; wire wire_nlilO_dataout; wire wire_nliO_dataout; wire wire_nliOi_dataout; wire wire_nliOll_dataout; wire wire_nliOO_dataout; wire wire_nll_dataout; wire wire_nll0i_dataout; wire wire_nll0l_dataout; wire wire_nll0O_dataout; wire wire_nll11i_dataout; wire wire_nll1i_dataout; wire wire_nll1l_dataout; wire wire_nll1O_dataout; wire wire_nll1Oi_dataout; wire wire_nlli_dataout; wire wire_nllii_dataout; wire wire_nllil_dataout; wire wire_nlliO_dataout; wire wire_nlll_dataout; wire wire_nlllil_dataout; wire wire_nllliO_dataout; wire wire_nlllli_dataout; wire wire_nlllll_dataout; wire wire_nllllO_dataout; wire wire_nlllOi_dataout; wire wire_nlllOl_dataout; wire wire_nlllOO_dataout; wire wire_nllO_dataout; wire wire_nllO0i_dataout; wire wire_nllO0l_dataout; wire wire_nllO0O_dataout; wire wire_nllO1i_dataout; wire wire_nllO1l_dataout; wire wire_nllO1O_dataout; wire wire_nllOii_dataout; wire wire_nllOil_dataout; wire wire_nllOiO_dataout; wire wire_nllOli_dataout; wire wire_nllOll_dataout; wire wire_nllOlO_dataout; wire wire_nllOOi_dataout; wire wire_nllOOl_dataout; wire wire_nllOOO_dataout; wire wire_nlO_dataout; wire wire_nlO00i_dataout; wire wire_nlO00l_dataout; wire wire_nlO00O_dataout; wire wire_nlO01i_dataout; wire wire_nlO01l_dataout; wire wire_nlO01O_dataout; wire wire_nlO0ii_dataout; wire wire_nlO0il_dataout; wire wire_nlO0iO_dataout; wire wire_nlO0li_dataout; wire wire_nlO0ll_dataout; wire wire_nlO0lO_dataout; wire wire_nlO0Oi_dataout; wire wire_nlO0Ol_dataout; wire wire_nlO0OO_dataout; wire wire_nlO10i_dataout; wire wire_nlO10l_dataout; wire wire_nlO10O_dataout; wire wire_nlO11i_dataout; wire wire_nlO11l_dataout; wire wire_nlO11O_dataout; wire wire_nlO1ii_dataout; wire wire_nlO1il_dataout; wire wire_nlO1iO_dataout; wire wire_nlO1li_dataout; wire wire_nlO1ll_dataout; wire wire_nlO1lO_dataout; wire wire_nlO1Oi_dataout; wire wire_nlO1Ol_dataout; wire wire_nlO1OO_dataout; wire wire_nlOi_dataout; wire wire_nlOi0i_dataout; wire wire_nlOi0O_dataout; wire wire_nlOi1i_dataout; wire wire_nlOi1l_dataout; wire wire_nlOi1O_dataout; wire wire_nlOiii_dataout; wire wire_nlOiil_dataout; wire wire_nlOiiO_dataout; wire wire_nlOili_dataout; wire wire_nlOill_dataout; wire wire_nlOilO_dataout; wire wire_nlOiOi_dataout; wire wire_nlOiOl_dataout; wire wire_nlOiOO_dataout; wire wire_nlOl_dataout; wire wire_nlOl0i_dataout; wire wire_nlOl0l_dataout; wire wire_nlOl0O_dataout; wire wire_nlOl1i_dataout; wire wire_nlOl1l_dataout; wire wire_nlOl1O_dataout; wire wire_nlOlii_dataout; wire wire_nlOlil_dataout; wire wire_nlOliO_dataout; wire wire_nlOlli_dataout; wire wire_nlOlll_dataout; wire wire_nlOllO_dataout; wire wire_nlOlOi_dataout; wire wire_nlOlOl_dataout; wire wire_nlOlOO_dataout; wire wire_nlOO_dataout; wire wire_nlOO0i_dataout; wire wire_nlOO0l_dataout; wire wire_nlOO0O_dataout; wire wire_nlOO1i_dataout; wire wire_nlOO1l_dataout; wire wire_nlOO1O_dataout; wire [8:0] wire_n00Oi_o; wire [3:0] wire_n01iO_o; wire [2:0] wire_n1lOi_o; wire [5:0] wire_n1Oll_o; wire [2:0] wire_n1OOO_o; wire [6:0] wire_nli0ll_o; wire [6:0] wire_nli0lO_o; wire [7:0] wire_nli0Oi_o; wire [2:0] wire_nliOl_o; wire [4:0] wire_nllli_o; wire wire_n0iii_o; wire wire_n0iil_o; wire wire_n0iiO_o; wire wire_n0ilO_o; wire wire_n0iOl_o; wire wire_n0l1i_o; wire wire_n0l1O_o; wire wire_n0lii_o; wire wire_n0lil_o; wire wire_n0liO_o; wire wire_n0lli_o; wire wire_n0lOl_o; wire wire_n0O0l_o; wire wire_n0O1l_o; wire wire_n0Oil_o; wire wire_n0Oll_o; wire wire_n0OOl_o; wire wire_ni00l_o; wire wire_ni01i_o; wire wire_ni01O_o; wire wire_ni0ii_o; wire wire_ni0iO_o; wire wire_ni0ll_o; wire wire_ni0Oi_o; wire wire_ni10i_o; wire wire_ni11l_o; wire wire_ni1Ol_o; wire wire_nil00l_o; wire wire_nil01O_o; wire wire_nil0il_o; wire wire_nil0li_o; wire wire_nil0Oi_o; wire wire_nil1li_o; wire wire_nil1lO_o; wire wire_nil1OO_o; wire wire_nili0i_o; wire wire_nili0O_o; wire wire_nili1i_o; wire wire_niliil_o; wire wire_nilili_o; wire wire_nililO_o; wire wire_niliOl_o; wire wire_nill0O_o; wire wire_nill1i_o; wire wire_nill1O_o; wire wire_nillil_o; wire wire_nillli_o; wire wire_nilllO_o; wire wire_nillOl_o; wire wire_nilO0l_o; wire wire_nilO1i_o; wire wire_nilO1O_o; wire wire_nilOii_o; wire wire_nilOiO_o; wire wire_nilOli_o; wire wire_nilOlO_o; wire wire_nilOOl_o; wire wire_niO11i_o; wire wire_nlilOi_o; wire wire_nliO0l_o; wire wire_nliO1i_o; wire wire_nliO1O_o; wire wire_nliOii_o; wire wire_nliOli_o; wire wire_nliOlO_o; wire wire_nliOOi_o; wire wire_nliOOl_o; wire wire_nll00O_o; wire wire_nll01i_o; wire wire_nll01O_o; wire wire_nll0iO_o; wire wire_nll0lO_o; wire wire_nll0OO_o; wire wire_nll10i_o; wire wire_nll10O_o; wire wire_nll11l_o; wire wire_nll1il_o; wire wire_nll1ll_o; wire wire_nll1Ol_o; wire wire_nlli0i_o; wire wire_nlliil_o; wire wire_nllili_o; wire wire_nllilO_o; wire wire_nlliOi_o; wire wire_nlliOO_o; wire wire_nlll0i_o; wire wire_nlll0O_o; wire wire_nlll1l_o; wire ni000i; wire ni000l; wire ni000O; wire ni001i; wire ni001O; wire ni00ii; wire ni00il; wire ni00iO; wire ni00li; wire ni00ll; wire ni00lO; wire ni00Oi; wire ni00Ol; wire ni00OO; wire ni010i; wire ni010l; wire ni010O; wire ni011i; wire ni011l; wire ni011O; wire ni01ii; wire ni01il; wire ni01iO; wire ni01li; wire ni01ll; wire ni01lO; wire ni01Oi; wire ni01Ol; wire ni01OO; wire ni0i0i; wire ni0i0l; wire ni0i0O; wire ni0i1i; wire ni0i1l; wire ni0i1O; wire ni0iii; wire ni0iil; wire ni0iiO; wire ni0ili; wire ni0ill; wire ni0ilO; wire ni0iOi; wire ni0iOl; wire ni0iOO; wire ni0l0i; wire ni0l0l; wire ni0l0O; wire ni0l1i; wire ni0l1l; wire ni0l1O; wire ni0lii; wire ni0lil; wire ni0liO; wire ni0lli; wire ni0lll; wire ni0llO; wire ni0lOi; wire ni0lOl; wire ni0lOO; wire ni0O0i; wire ni0O0l; wire ni0O0O; wire ni0O1i; wire ni0O1l; wire ni0O1O; wire ni0Oii; wire ni0Oil; wire ni0OiO; wire ni0Oli; wire ni0Oll; wire ni0OlO; wire ni0OOi; wire ni0OOl; wire ni0OOO; wire ni1lll; wire ni1llO; wire ni1lOi; wire ni1lOl; wire ni1lOO; wire ni1O0i; wire ni1O0l; wire ni1O0O; wire ni1O1i; wire ni1O1l; wire ni1O1O; wire ni1Oii; wire ni1Oil; wire ni1OiO; wire ni1Oli; wire ni1Oll; wire ni1OlO; wire ni1OOi; wire ni1OOl; wire ni1OOO; wire nii00l; wire nii01i; wire nii01l; wire nii0ii; wire nii0ll; wire nii0Ol; wire nii10i; wire nii10l; wire nii10O; wire nii11i; wire nii11l; wire nii11O; wire nii1ii; wire nii1il; wire nii1iO; wire nii1li; wire nii1ll; wire nii1lO; wire nii1Oi; wire nii1Ol; wire niii0l; wire niiiil; wire niiiiO; wire niiili; wire niiill; wire niiilO; wire niiiOi; wire niiiOl; wire niiiOO; wire niil0i; wire niil0l; wire niil0O; wire niil1i; wire niil1l; wire niil1O; wire niilii; wire niilil; wire niiliO; wire niilli; wire niilll; wire niilOl; wire niiOil; wire niiOiO; wire niiOli; wire niiOOi; initial ni001l45 = 0; always @ ( posedge tx_clk) ni001l45 <= ni001l46; event ni001l45_event; initial #1 ->ni001l45_event; always @(ni001l45_event) ni001l45 <= {1{1'b1}}; initial ni001l46 = 0; always @ ( posedge tx_clk) ni001l46 <= ni001l45; initial nii00O39 = 0; always @ ( posedge tx_clk) nii00O39 <= nii00O40; event nii00O39_event; initial #1 ->nii00O39_event; always @(nii00O39_event) nii00O39 <= {1{1'b1}}; initial nii00O40 = 0; always @ ( posedge tx_clk) nii00O40 <= nii00O39; initial nii01O41 = 0; always @ ( posedge tx_clk) nii01O41 <= nii01O42; event nii01O41_event; initial #1 ->nii01O41_event; always @(nii01O41_event) nii01O41 <= {1{1'b1}}; initial nii01O42 = 0; always @ ( posedge tx_clk) nii01O42 <= nii01O41; initial nii0il37 = 0; always @ ( posedge tx_clk) nii0il37 <= nii0il38; event nii0il37_event; initial #1 ->nii0il37_event; always @(nii0il37_event) nii0il37 <= {1{1'b1}}; initial nii0il38 = 0; always @ ( posedge tx_clk) nii0il38 <= nii0il37; initial nii0li35 = 0; always @ ( posedge tx_clk) nii0li35 <= nii0li36; event nii0li35_event; initial #1 ->nii0li35_event; always @(nii0li35_event) nii0li35 <= {1{1'b1}}; initial nii0li36 = 0; always @ ( posedge tx_clk) nii0li36 <= nii0li35; initial nii0lO33 = 0; always @ ( posedge tx_clk) nii0lO33 <= nii0lO34; event nii0lO33_event; initial #1 ->nii0lO33_event; always @(nii0lO33_event) nii0lO33 <= {1{1'b1}}; initial nii0lO34 = 0; always @ ( posedge tx_clk) nii0lO34 <= nii0lO33; initial nii0OO31 = 0; always @ ( posedge tx_clk) nii0OO31 <= nii0OO32; event nii0OO31_event; initial #1 ->nii0OO31_event; always @(nii0OO31_event) nii0OO31 <= {1{1'b1}}; initial nii0OO32 = 0; always @ ( posedge tx_clk) nii0OO32 <= nii0OO31; initial nii1OO43 = 0; always @ ( posedge tx_clk) nii1OO43 <= nii1OO44; event nii1OO43_event; initial #1 ->nii1OO43_event; always @(nii1OO43_event) nii1OO43 <= {1{1'b1}}; initial nii1OO44 = 0; always @ ( posedge tx_clk) nii1OO44 <= nii1OO43; initial niii0i23 = 0; always @ ( posedge tx_clk) niii0i23 <= niii0i24; event niii0i23_event; initial #1 ->niii0i23_event; always @(niii0i23_event) niii0i23 <= {1{1'b1}}; initial niii0i24 = 0; always @ ( posedge tx_clk) niii0i24 <= niii0i23; initial niii0O21 = 0; always @ ( posedge tx_clk) niii0O21 <= niii0O22; event niii0O21_event; initial #1 ->niii0O21_event; always @(niii0O21_event) niii0O21 <= {1{1'b1}}; initial niii0O22 = 0; always @ ( posedge tx_clk) niii0O22 <= niii0O21; initial niii1i29 = 0; always @ ( posedge tx_clk) niii1i29 <= niii1i30; event niii1i29_event; initial #1 ->niii1i29_event; always @(niii1i29_event) niii1i29 <= {1{1'b1}}; initial niii1i30 = 0; always @ ( posedge tx_clk) niii1i30 <= niii1i29; initial niii1l27 = 0; always @ ( posedge tx_clk) niii1l27 <= niii1l28; event niii1l27_event; initial #1 ->niii1l27_event; always @(niii1l27_event) niii1l27 <= {1{1'b1}}; initial niii1l28 = 0; always @ ( posedge tx_clk) niii1l28 <= niii1l27; initial niii1O25 = 0; always @ ( posedge tx_clk) niii1O25 <= niii1O26; event niii1O25_event; initial #1 ->niii1O25_event; always @(niii1O25_event) niii1O25 <= {1{1'b1}}; initial niii1O26 = 0; always @ ( posedge tx_clk) niii1O26 <= niii1O25; initial niillO19 = 0; always @ ( posedge tx_clk) niillO19 <= niillO20; event niillO19_event; initial #1 ->niillO19_event; always @(niillO19_event) niillO19 <= {1{1'b1}}; initial niillO20 = 0; always @ ( posedge tx_clk) niillO20 <= niillO19; initial niilOi17 = 0; always @ ( posedge tx_clk) niilOi17 <= niilOi18; event niilOi17_event; initial #1 ->niilOi17_event; always @(niilOi17_event) niilOi17 <= {1{1'b1}}; initial niilOi18 = 0; always @ ( posedge tx_clk) niilOi18 <= niilOi17; initial niilOO15 = 0; always @ ( posedge tx_clk) niilOO15 <= niilOO16; event niilOO15_event; initial #1 ->niilOO15_event; always @(niilOO15_event) niilOO15 <= {1{1'b1}}; initial niilOO16 = 0; always @ ( posedge tx_clk) niilOO16 <= niilOO15; initial niiO0i10 = 0; always @ ( posedge tx_clk) niiO0i10 <= niiO0i9; initial niiO0i9 = 0; always @ ( posedge tx_clk) niiO0i9 <= niiO0i10; event niiO0i9_event; initial #1 ->niiO0i9_event; always @(niiO0i9_event) niiO0i9 <= {1{1'b1}}; initial niiO0O7 = 0; always @ ( posedge tx_clk) niiO0O7 <= niiO0O8; event niiO0O7_event; initial #1 ->niiO0O7_event; always @(niiO0O7_event) niiO0O7 <= {1{1'b1}}; initial niiO0O8 = 0; always @ ( posedge tx_clk) niiO0O8 <= niiO0O7; initial niiO1i13 = 0; always @ ( posedge tx_clk) niiO1i13 <= niiO1i14; event niiO1i13_event; initial #1 ->niiO1i13_event; always @(niiO1i13_event) niiO1i13 <= {1{1'b1}}; initial niiO1i14 = 0; always @ ( posedge tx_clk) niiO1i14 <= niiO1i13; initial niiO1l11 = 0; always @ ( posedge tx_clk) niiO1l11 <= niiO1l12; event niiO1l11_event; initial #1 ->niiO1l11_event; always @(niiO1l11_event) niiO1l11 <= {1{1'b1}}; initial niiO1l12 = 0; always @ ( posedge tx_clk) niiO1l12 <= niiO1l11; initial niiOll5 = 0; always @ ( posedge tx_clk) niiOll5 <= niiOll6; event niiOll5_event; initial #1 ->niiOll5_event; always @(niiOll5_event) niiOll5 <= {1{1'b1}}; initial niiOll6 = 0; always @ ( posedge tx_clk) niiOll6 <= niiOll5; initial niiOOl3 = 0; always @ ( posedge tx_clk) niiOOl3 <= niiOOl4; event niiOOl3_event; initial #1 ->niiOOl3_event; always @(niiOOl3_event) niiOOl3 <= {1{1'b1}}; initial niiOOl4 = 0; always @ ( posedge tx_clk) niiOOl4 <= niiOOl3; initial nil11i1 = 0; always @ ( posedge tx_clk) nil11i1 <= nil11i2; event nil11i1_event; initial #1 ->nil11i1_event; always @(nil11i1_event) nil11i1 <= {1{1'b1}}; initial nil11i2 = 0; always @ ( posedge tx_clk) nil11i2 <= nil11i1; initial begin n100i = 0; n100l = 0; n100O = 0; n101i = 0; n101l = 0; n101O = 0; n10ii = 0; n10il = 0; n10iO = 0; n10li = 0; n10ll = 0; n10lO = 0; n10Oi = 0; n10Ol = 0; n10OO = 0; n110i = 0; n110l = 0; n110O = 0; n111i = 0; n111l = 0; n111O = 0; n11ii = 0; n11il = 0; n11iO = 0; n11li = 0; n11ll = 0; n11lO = 0; n11Oi = 0; n11Ol = 0; n11OO = 0; n1i0i = 0; n1i0l = 0; n1i0O = 0; n1i1i = 0; n1i1l = 0; n1i1O = 0; n1iii = 0; n1iil = 0; n1iiO = 0; n1ili = 0; n1ill = 0; n1ilO = 0; n1iOi = 0; n1iOl = 0; n1iOO = 0; n1l0i = 0; n1l0l = 0; n1l1i = 0; n1l1l = 0; n1l1O = 0; n1lii = 0; nliliO = 0; nlOOil = 0; nlOOiO = 0; nlOOli = 0; nlOOll = 0; nlOOlO = 0; nlOOOi = 0; nlOOOl = 0; nlOOOO = 0; end always @ ( posedge tx_clk or posedge soft_reset) begin if (soft_reset == 1'b1) begin n100i <= 0; n100l <= 0; n100O <= 0; n101i <= 0; n101l <= 0; n101O <= 0; n10ii <= 0; n10il <= 0; n10iO <= 0; n10li <= 0; n10ll <= 0; n10lO <= 0; n10Oi <= 0; n10Ol <= 0; n10OO <= 0; n110i <= 0; n110l <= 0; n110O <= 0; n111i <= 0; n111l <= 0; n111O <= 0; n11ii <= 0; n11il <= 0; n11iO <= 0; n11li <= 0; n11ll <= 0; n11lO <= 0; n11Oi <= 0; n11Ol <= 0; n11OO <= 0; n1i0i <= 0; n1i0l <= 0; n1i0O <= 0; n1i1i <= 0; n1i1l <= 0; n1i1O <= 0; n1iii <= 0; n1iil <= 0; n1iiO <= 0; n1ili <= 0; n1ill <= 0; n1ilO <= 0; n1iOi <= 0; n1iOl <= 0; n1iOO <= 0; n1l0i <= 0; n1l0l <= 0; n1l1i <= 0; n1l1l <= 0; n1l1O <= 0; n1lii <= 0; nliliO <= 0; nlOOil <= 0; nlOOiO <= 0; nlOOli <= 0; nlOOll <= 0; nlOOlO <= 0; nlOOOi <= 0; nlOOOl <= 0; nlOOOO <= 0; end else if (wire_nll_dataout == 1'b1) begin n100i <= wire_nll01O_o; n100l <= wire_nll00O_o; n100O <= wire_nll0iO_o; n101i <= wire_n001O_dataout; n101l <= ni0OlO; n101O <= wire_nliO1i_o; n10ii <= wire_nll0lO_o; n10il <= wire_nll0OO_o; n10iO <= (~ ni0OOi); n10li <= wire_nlli0i_o; n10ll <= (~ ni0OOl); n10lO <= wire_nlliil_o; n10Oi <= wire_nllili_o; n10Ol <= wire_nllilO_o; n10OO <= wire_nlliOi_o; n110i <= wire_n011i_dataout; n110l <= wire_n011l_dataout; n110O <= wire_n011O_dataout; n111i <= wire_n1OlO_dataout; n111l <= wire_n1OOi_dataout; n111O <= wire_n1OOl_dataout; n11ii <= wire_n010i_dataout; n11il <= wire_n01li_dataout; n11iO <= wire_n01ll_dataout; n11li <= wire_n01lO_dataout; n11ll <= wire_n01Oi_dataout; n11lO <= wire_n01Ol_dataout; n11Oi <= wire_n01OO_dataout; n11Ol <= wire_n001i_dataout; n11OO <= wire_n001l_dataout; n1i0i <= wire_nlll0O_o; n1i0l <= wire_nliO1O_o; n1i0O <= wire_nliO0l_o; n1i1i <= wire_nlliOO_o; n1i1l <= wire_nlll1l_o; n1i1O <= wire_nlll0i_o; n1iii <= wire_nliOii_o; n1iil <= wire_nliOli_o; n1iiO <= wire_nliOll_dataout; n1ili <= wire_nliOlO_o; n1ill <= wire_nliOOi_o; n1ilO <= wire_nliOOl_o; n1iOi <= wire_nll11i_dataout; n1iOl <= wire_nll11l_o; n1iOO <= wire_nll10i_o; n1l0i <= wire_nll1Oi_dataout; n1l0l <= wire_nll1Ol_o; n1l1i <= wire_nll10O_o; n1l1l <= wire_nll1il_o; n1l1O <= wire_nll1ll_o; n1lii <= wire_nll01i_o; nliliO <= wire_n1lli_dataout; nlOOil <= wire_n1lll_dataout; nlOOiO <= wire_n1llO_dataout; nlOOli <= wire_n1lOl_dataout; nlOOll <= wire_n1lOO_dataout; nlOOlO <= wire_n1O1i_dataout; nlOOOi <= wire_n1O1l_dataout; nlOOOl <= wire_n1O1O_dataout; nlOOOO <= wire_n1O0i_dataout; end end initial begin n1liO = 0; end always @ ( posedge tx_clk or posedge soft_reset) begin if (soft_reset == 1'b1) begin n1liO <= 1; end else if (wire_nll_dataout == 1'b1) begin n1liO <= niilOl; end end event n1liO_event; initial #1 ->n1liO_event; always @(n1liO_event) n1liO <= 1; initial begin nl00il = 0; nl00iO = 0; nl00li = 0; nl00ll = 0; nl00lO = 0; nl00Oi = 0; nl00Ol = 0; nl00OO = 0; nl0i0i = 0; nl0i0l = 0; nl0i0O = 0; nl0i1i = 0; nl0i1l = 0; nl0i1O = 0; nl0iii = 0; nl0iil = 0; nl0iiO = 0; nl0ili = 0; nl0ill = 0; nl0ilO = 0; nl0iOi = 0; nl0iOl = 0; nl0iOO = 0; nl0l0i = 0; nl0l0l = 0; nl0l0O = 0; nl0l1i = 0; nl0l1l = 0; nl0l1O = 0; nl0lii = 0; nl0lil = 0; nl0liO = 0; nl0lli = 0; nl0lll = 0; nl0llO = 0; nl0lOi = 0; nl0lOl = 0; nl0lOO = 0; nl0O0i = 0; nl0O0l = 0; nl0O0O = 0; nl0O1i = 0; nl0O1l = 0; nl0O1O = 0; nl0Oii = 0; nl0Oil = 0; nl0OiO = 0; nl0Oli = 0; nl0Oll = 0; nl0OlO = 0; nl0OOi = 0; nl0OOl = 0; nli11i = 0; end always @ (tx_clk or wire_nl0OOO_PRN or soft_reset) begin if (wire_nl0OOO_PRN == 1'b0) begin nl00il <= 1; nl00iO <= 1; nl00li <= 1; nl00ll <= 1; nl00lO <= 1; nl00Oi <= 1; nl00Ol <= 1; nl00OO <= 1; nl0i0i <= 1; nl0i0l <= 1; nl0i0O <= 1; nl0i1i <= 1; nl0i1l <= 1; nl0i1O <= 1; nl0iii <= 1; nl0iil <= 1; nl0iiO <= 1; nl0ili <= 1; nl0ill <= 1; nl0ilO <= 1; nl0iOi <= 1; nl0iOl <= 1; nl0iOO <= 1; nl0l0i <= 1; nl0l0l <= 1; nl0l0O <= 1; nl0l1i <= 1; nl0l1l <= 1; nl0l1O <= 1; nl0lii <= 1; nl0lil <= 1; nl0liO <= 1; nl0lli <= 1; nl0lll <= 1; nl0llO <= 1; nl0lOi <= 1; nl0lOl <= 1; nl0lOO <= 1; nl0O0i <= 1; nl0O0l <= 1; nl0O0O <= 1; nl0O1i <= 1; nl0O1l <= 1; nl0O1O <= 1; nl0Oii <= 1; nl0Oil <= 1; nl0OiO <= 1; nl0Oli <= 1; nl0Oll <= 1; nl0OlO <= 1; nl0OOi <= 1; nl0OOl <= 1; nli11i <= 1; end else if (soft_reset == 1'b1) begin nl00il <= 0; nl00iO <= 0; nl00li <= 0; nl00ll <= 0; nl00lO <= 0; nl00Oi <= 0; nl00Ol <= 0; nl00OO <= 0; nl0i0i <= 0; nl0i0l <= 0; nl0i0O <= 0; nl0i1i <= 0; nl0i1l <= 0; nl0i1O <= 0; nl0iii <= 0; nl0iil <= 0; nl0iiO <= 0; nl0ili <= 0; nl0ill <= 0; nl0ilO <= 0; nl0iOi <= 0; nl0iOl <= 0; nl0iOO <= 0; nl0l0i <= 0; nl0l0l <= 0; nl0l0O <= 0; nl0l1i <= 0; nl0l1l <= 0; nl0l1O <= 0; nl0lii <= 0; nl0lil <= 0; nl0liO <= 0; nl0lli <= 0; nl0lll <= 0; nl0llO <= 0; nl0lOi <= 0; nl0lOl <= 0; nl0lOO <= 0; nl0O0i <= 0; nl0O0l <= 0; nl0O0O <= 0; nl0O1i <= 0; nl0O1l <= 0; nl0O1O <= 0; nl0Oii <= 0; nl0Oil <= 0; nl0OiO <= 0; nl0Oli <= 0; nl0Oll <= 0; nl0OlO <= 0; nl0OOi <= 0; nl0OOl <= 0; nli11i <= 0; end else if (tx_clk != nl0OOO_clk_prev && tx_clk == 1'b1) begin nl00il <= wire_nli10i_dataout; nl00iO <= wire_nli10l_dataout; nl00li <= wire_nli10O_dataout; nl00ll <= wire_nli1ii_dataout; nl00lO <= wire_nli1il_dataout; nl00Oi <= wire_nli1iO_dataout; nl00Ol <= wire_nli1li_dataout; nl00OO <= wire_nli1ll_dataout; nl0i0i <= wire_nli1OO_dataout; nl0i0l <= wire_nli01i_dataout; nl0i0O <= wire_nli01l_dataout; nl0i1i <= wire_nli1lO_dataout; nl0i1l <= wire_nli1Oi_dataout; nl0i1O <= wire_nli1Ol_dataout; nl0iii <= wire_nli01O_dataout; nl0iil <= wire_nli00i_dataout; nl0iiO <= wire_nli00l_dataout; nl0ili <= wire_nli00O_dataout; nl0ill <= wire_nli0ii_dataout; nl0ilO <= wire_nli0il_dataout; nl0iOi <= wire_nli0iO_dataout; nl0iOl <= wire_nli0li_dataout; nl0iOO <= (~ (nli11O | nl0OOi)); nl0l0i <= wire_nil01O_o; nl0l0l <= wire_nil00l_o; nl0l0O <= wire_nil0il_o; nl0l1i <= wire_nil1li_o; nl0l1l <= wire_nil1lO_o; nl0l1O <= wire_nil1OO_o; nl0lii <= wire_nil0li_o; nl0lil <= wire_nil0Oi_o; nl0liO <= wire_nili1i_o; nl0lli <= wire_nili0i_o; nl0lll <= wire_nili0O_o; nl0llO <= wire_niliil_o; nl0lOi <= wire_nilili_o; nl0lOl <= wire_nililO_o; nl0lOO <= wire_niliOl_o; nl0O0i <= wire_nillil_o; nl0O0l <= wire_nillli_o; nl0O0O <= wire_nilllO_o; nl0O1i <= wire_nill1i_o; nl0O1l <= wire_nill1O_o; nl0O1O <= wire_nill0O_o; nl0Oii <= wire_nillOl_o; nl0Oil <= wire_nilO1i_o; nl0OiO <= wire_nilO1O_o; nl0Oli <= wire_nilO0l_o; nl0Oll <= wire_nilOii_o; nl0OlO <= wire_nilOiO_o; nl0OOi <= wire_nilOli_o; nl0OOl <= wire_nilOlO_o; nli11i <= wire_nilOOl_o; end nl0OOO_clk_prev <= tx_clk; end assign wire_nl0OOO_PRN = (ni001l46 ^ ni001l45); initial begin nli11O = 0; end always @ ( posedge tx_clk or posedge soft_reset) begin if (soft_reset == 1'b1) begin nli11O <= 1; end else begin nli11O <= wire_niO11i_o; end end event nli11O_event; initial #1 ->nli11O_event; always @(nli11O_event) nli11O <= 1; initial begin n0lOi = 0; niO0l = 0; niO0O = 0; niOii = 0; niOil = 0; niOiO = 0; niOli = 0; niOll = 0; niOlO = 0; niOOi = 0; niOOl = 0; niOOO = 0; nl00i = 0; nl00l = 0; nl00O = 0; nl01i = 0; nl01l = 0; nl01O = 0; nl0ii = 0; nl0il = 0; nl0iO = 0; nl0li = 0; nl0ll = 0; nl0lO = 0; nl0Oi = 0; nl0Ol = 0; nl0OO = 0; nl10i = 0; nl10l = 0; nl10O = 0; nl11i = 0; nl11l = 0; nl11O = 0; nl1ii = 0; nl1il = 0; nl1iO = 0; nl1li = 0; nl1ll = 0; nl1lO = 0; nl1Oi = 0; nl1Ol = 0; nl1OO = 0; nli0i = 0; nli0l = 0; nli0O = 0; nli1i = 0; nli1l = 0; nli1O = 0; nliil = 0; end always @ ( posedge tx_clk or posedge soft_reset) begin if (soft_reset == 1'b1) begin n0lOi <= 0; niO0l <= 0; niO0O <= 0; niOii <= 0; niOil <= 0; niOiO <= 0; niOli <= 0; niOll <= 0; niOlO <= 0; niOOi <= 0; niOOl <= 0; niOOO <= 0; nl00i <= 0; nl00l <= 0; nl00O <= 0; nl01i <= 0; nl01l <= 0; nl01O <= 0; nl0ii <= 0; nl0il <= 0; nl0iO <= 0; nl0li <= 0; nl0ll <= 0; nl0lO <= 0; nl0Oi <= 0; nl0Ol <= 0; nl0OO <= 0; nl10i <= 0; nl10l <= 0; nl10O <= 0; nl11i <= 0; nl11l <= 0; nl11O <= 0; nl1ii <= 0; nl1il <= 0; nl1iO <= 0; nl1li <= 0; nl1ll <= 0; nl1lO <= 0; nl1Oi <= 0; nl1Ol <= 0; nl1OO <= 0; nli0i <= 0; nli0l <= 0; nli0O <= 0; nli1i <= 0; nli1l <= 0; nli1O <= 0; nliil <= 0; end else if (wire_nli_dataout == 1'b1) begin n0lOi <= wire_nlill_dataout; niO0l <= wire_nlilO_dataout; niO0O <= wire_nliOi_dataout; niOii <= wire_nliOO_dataout; niOil <= wire_nll1i_dataout; niOiO <= wire_nll1l_dataout; niOli <= wire_nll1O_dataout; niOll <= wire_nll0i_dataout; niOlO <= niil1l; niOOi <= wire_n0ilO_o; niOOl <= (~ niil1O); niOOO <= niil0i; nl00i <= wire_n0lii_o; nl00l <= wire_n0lil_o; nl00O <= wire_n0liO_o; nl01i <= wire_n0l1i_o; nl01l <= wire_n0l1O_o; nl01O <= wire_n0l0O_dataout; nl0ii <= wire_n0lli_o; nl0il <= wire_n0llO_dataout; nl0iO <= wire_n0lOl_o; nl0li <= wire_n0O1i_dataout; nl0ll <= wire_n0O1l_o; nl0lO <= wire_n0O0i_dataout; nl0Oi <= wire_n0O0l_o; nl0Ol <= wire_n0Oii_dataout; nl0OO <= wire_n0Oil_o; nl10i <= (~ niilil); nl10l <= (~ niiliO); nl10O <= niilli; nl11i <= (~ niil0l); nl11l <= (~ niil0O); nl11O <= (~ niilii); nl1ii <= wire_ni1Ol_o; nl1il <= wire_ni01i_o; nl1iO <= wire_ni01O_o; nl1li <= wire_ni00l_o; nl1ll <= wire_ni0ii_o; nl1lO <= wire_ni0iO_o; nl1Oi <= wire_ni0ll_o; nl1Ol <= wire_ni0Oi_o; nl1OO <= wire_n0iOl_o; nli0i <= wire_n0OOl_o; nli0l <= wire_ni11i_dataout; nli0O <= wire_ni11l_o; nli1i <= wire_n0Oli_dataout; nli1l <= wire_n0Oll_o; nli1O <= wire_n0OOi_dataout; nliil <= wire_ni10i_o; end end initial begin nlili = 0; end always @ (tx_clk or wire_nliiO_PRN or wire_nliiO_CLRN) begin if (wire_nliiO_PRN == 1'b0) begin nlili <= 1; end else if (wire_nliiO_CLRN == 1'b0) begin nlili <= 0; end else if (wire_nli_dataout == 1'b1) if (tx_clk != nliiO_clk_prev && tx_clk == 1'b1) begin nlili <= niilOl; end nliiO_clk_prev <= tx_clk; end assign wire_nliiO_CLRN = (niilOi18 ^ niilOi17), wire_nliiO_PRN = ((niillO20 ^ niillO19) & (~ soft_reset)); event nlili_event; initial #1 ->nlili_event; always @(nlili_event) nlili <= 1; assign wire_n000i_dataout = (n1l1l === 1'b1) ? wire_n00Oi_o[0] : n11il; assign wire_n000l_dataout = (n1l1l === 1'b1) ? wire_n00Oi_o[1] : n11iO; assign wire_n000O_dataout = (n1l1l === 1'b1) ? wire_n00Oi_o[2] : n11li; and(wire_n001i_dataout, wire_n00li_dataout, ~(wire_nlillO_dataout)); and(wire_n001l_dataout, wire_n00ll_dataout, ~(wire_nlillO_dataout)); and(wire_n001O_dataout, wire_n00lO_dataout, ~(wire_nlillO_dataout)); assign wire_n00i_dataout = (niiOil === 1'b1) ? nl0l0l : wire_niii_dataout; assign wire_n00ii_dataout = (n1l1l === 1'b1) ? wire_n00Oi_o[3] : n11ll; assign wire_n00il_dataout = (n1l1l === 1'b1) ? wire_n00Oi_o[4] : n11lO; assign wire_n00iO_dataout = (n1l1l === 1'b1) ? wire_n00Oi_o[5] : n11Oi; assign wire_n00l_dataout = (niiOil === 1'b1) ? nl0l0O : wire_niil_dataout; assign wire_n00li_dataout = (n1l1l === 1'b1) ? wire_n00Oi_o[6] : n11Ol; assign wire_n00ll_dataout = (n1l1l === 1'b1) ? wire_n00Oi_o[7] : n11OO; assign wire_n00lO_dataout = (n1l1l === 1'b1) ? wire_n00Oi_o[8] : n101i; assign wire_n00O_dataout = (niiOil === 1'b1) ? nl0lii : wire_niiO_dataout; and(wire_n010i_dataout, wire_n01il_dataout, ~(wire_nlilll_dataout)); assign wire_n010l_dataout = (wire_nlilli_dataout === 1'b1) ? wire_n01iO_o[0] : n110i; assign wire_n010O_dataout = (wire_nlilli_dataout === 1'b1) ? wire_n01iO_o[1] : n110l; and(wire_n011i_dataout, wire_n010l_dataout, ~(wire_nlilll_dataout)); and(wire_n011l_dataout, wire_n010O_dataout, ~(wire_nlilll_dataout)); and(wire_n011O_dataout, wire_n01ii_dataout, ~(wire_nlilll_dataout)); assign wire_n01i_dataout = (niiOil === 1'b1) ? nl0l1l : wire_ni0i_dataout; assign wire_n01ii_dataout = (wire_nlilli_dataout === 1'b1) ? wire_n01iO_o[2] : n110O; assign wire_n01il_dataout = (wire_nlilli_dataout === 1'b1) ? wire_n01iO_o[3] : n11ii; assign wire_n01l_dataout = (niiOil === 1'b1) ? nl0l1O : wire_ni0l_dataout; and(wire_n01li_dataout, wire_n000i_dataout, ~(wire_nlillO_dataout)); and(wire_n01ll_dataout, wire_n000l_dataout, ~(wire_nlillO_dataout)); and(wire_n01lO_dataout, wire_n000O_dataout, ~(wire_nlillO_dataout)); assign wire_n01O_dataout = (niiOil === 1'b1) ? nl0l0i : wire_ni0O_dataout; and(wire_n01Oi_dataout, wire_n00ii_dataout, ~(wire_nlillO_dataout)); and(wire_n01Ol_dataout, wire_n00il_dataout, ~(wire_nlillO_dataout)); and(wire_n01OO_dataout, wire_n00iO_dataout, ~(wire_nlillO_dataout)); and(wire_n0i_dataout, nl1ll, niiOli); assign wire_n0ii_dataout = (niiOil === 1'b1) ? nl0lil : wire_nili_dataout; assign wire_n0il_dataout = (niiOil === 1'b1) ? nl0liO : wire_nill_dataout; assign wire_n0iO_dataout = (niiOil === 1'b1) ? nl0lli : wire_nilO_dataout; and(wire_n0l_dataout, nl1lO, niiOli); and(wire_n0l0O_dataout, (~ niiOOi), nl0ii); assign wire_n0li_dataout = (niiOil === 1'b1) ? nl0lll : wire_niOi_dataout; assign wire_n0ll_dataout = (niiOil === 1'b1) ? nl0llO : wire_niOl_dataout; and(wire_n0llO_dataout, (~ niiOOi), nl0iO); assign wire_n0lO_dataout = (niiOil === 1'b1) ? nl0lOi : wire_niOO_dataout; and(wire_n0O_dataout, nl1Oi, niiOli); and(wire_n0O0i_dataout, (~ niiOOi), nl0Oi); and(wire_n0O1i_dataout, (~ niiOOi), nl0ll); assign wire_n0Oi_dataout = (niiOil === 1'b1) ? nl0lOl : wire_nl1i_dataout; and(wire_n0Oii_dataout, (~ niiOOi), nl0OO); assign wire_n0Ol_dataout = (niiOil === 1'b1) ? nl0lOO : wire_nl1l_dataout; and(wire_n0Oli_dataout, (~ niiOOi), nli1l); assign wire_n0OO_dataout = (niiOil === 1'b1) ? nl0O1i : wire_nl1O_dataout; and(wire_n0OOi_dataout, (~ niiOOi), nli0i); and(wire_n1i_dataout, nl1il, niiOli); and(wire_n1l_dataout, nl1iO, niiOli); and(wire_n1lli_dataout, wire_n1lOi_o[0], wire_nlilOi_o); and(wire_n1lll_dataout, wire_n1lOi_o[1], wire_nlilOi_o); and(wire_n1llO_dataout, wire_n1lOi_o[2], wire_nlilOi_o); assign wire_n1lOl_dataout = (wire_nlil0O_dataout === 1'b1) ? wire_n1Oll_o[0] : wire_n1O0l_dataout; assign wire_n1lOO_dataout = (wire_nlil0O_dataout === 1'b1) ? wire_n1Oll_o[1] : wire_n1O0O_dataout; and(wire_n1O_dataout, nl1li, niiOli); assign wire_n1O0i_dataout = (wire_nlil0O_dataout === 1'b1) ? wire_n1Oll_o[5] : wire_n1Oli_dataout; and(wire_n1O0l_dataout, nlOOli, ~(wire_nlilii_dataout)); and(wire_n1O0O_dataout, nlOOll, ~(wire_nlilii_dataout)); assign wire_n1O1i_dataout = (wire_nlil0O_dataout === 1'b1) ? wire_n1Oll_o[2] : wire_n1Oii_dataout; assign wire_n1O1l_dataout = (wire_nlil0O_dataout === 1'b1) ? wire_n1Oll_o[3] : wire_n1Oil_dataout; assign wire_n1O1O_dataout = (wire_nlil0O_dataout === 1'b1) ? wire_n1Oll_o[4] : wire_n1OiO_dataout; and(wire_n1Oii_dataout, nlOOlO, ~(wire_nlilii_dataout)); and(wire_n1Oil_dataout, nlOOOi, ~(wire_nlilii_dataout)); and(wire_n1OiO_dataout, nlOOOl, ~(wire_nlilii_dataout)); and(wire_n1Oli_dataout, nlOOOO, ~(wire_nlilii_dataout)); assign wire_n1OlO_dataout = (wire_nlilil_dataout === 1'b1) ? wire_n1OOO_o[0] : n111i; assign wire_n1OOi_dataout = (wire_nlilil_dataout === 1'b1) ? wire_n1OOO_o[1] : n111l; assign wire_n1OOl_dataout = (wire_nlilil_dataout === 1'b1) ? wire_n1OOO_o[2] : n111O; assign wire_ni0i_dataout = (niiOiO === 1'b1) ? n100i : wire_nlii_dataout; assign wire_ni0l_dataout = (niiOiO === 1'b1) ? n100l : wire_nlil_dataout; assign wire_ni0O_dataout = (niiOiO === 1'b1) ? n100O : wire_nliO_dataout; and(wire_ni0OO_dataout, niiiil, ~(niiilO)); and(wire_ni11i_dataout, wire_nillO_dataout, nli0O); assign wire_ni1i_dataout = (niiOil === 1'b1) ? nl0O1l : wire_nl0i_dataout; assign wire_ni1l_dataout = (niiOil === 1'b1) ? nl0iOO : wire_nl0l_dataout; assign wire_ni1O_dataout = (niiOil === 1'b1) ? nl0l1i : wire_nl0O_dataout; and(wire_nii_dataout, nl1Ol, niiOli); and(wire_nii0i_dataout, wire_niiil_dataout, niiOOi); and(wire_nii0l_dataout, wire_niiiO_dataout, niiOOi); assign wire_nii0O_dataout = (niiilO === 1'b1) ? niiiil : niiiiO; and(wire_nii1i_dataout, niiiil, niiilO); and(wire_nii1l_dataout, wire_nii0O_dataout, ~(niiOOi)); assign wire_nii1O_dataout = (niiOOi === 1'b1) ? (~ niiili) : wire_niiii_dataout; assign wire_niii_dataout = (niiOiO === 1'b1) ? n10ii : wire_nlli_dataout; assign wire_niiii_dataout = (niiilO === 1'b1) ? (~ niiiil) : (~ niiiiO); and(wire_niiil_dataout, niiili, ~(niiilO)); and(wire_niiiO_dataout, niiili, niiilO); assign wire_niil_dataout = (niiOiO === 1'b1) ? n10il : wire_nlll_dataout; and(wire_niili_dataout, wire_nil1i_dataout, niiOOi); and(wire_niill_dataout, wire_nil1l_dataout, niiOOi); and(wire_niilO_dataout, wire_nil1O_dataout, niiOOi); assign wire_niiO_dataout = (niiOiO === 1'b1) ? n10iO : wire_nllO_dataout; and(wire_niiOi_dataout, wire_nil0i_dataout, niiOOi); and(wire_niiOl_dataout, (~ niiill), niiOOi); and(wire_niiOO_dataout, niiill, niiOOi); and(wire_nil_dataout, niOlO, niiOli); and(wire_nil0i_dataout, niiilO, niiill); and(wire_nil0l_dataout, wire_nilil_dataout, ~(niiilO)); and(wire_nil0O_dataout, wire_niliO_dataout, ~(niiilO)); and(wire_nil1i_dataout, wire_nil0l_dataout, niiill); and(wire_nil1l_dataout, wire_nil0O_dataout, niiill); and(wire_nil1O_dataout, wire_nilii_dataout, niiill); assign wire_nili_dataout = (niiOiO === 1'b1) ? n10li : wire_nlOi_dataout; and(wire_nilii_dataout, niil1i, ~(niiilO)); and(wire_nilil_dataout, (~ niiiOO), ~(niil1i)); and(wire_niliO_dataout, niiiOO, ~(niil1i)); assign wire_nill_dataout = (niiOiO === 1'b1) ? n10ll : wire_nlOl_dataout; and(wire_nilli_dataout, (~ niiiOl), niiOOi); or(wire_nilll_dataout, wire_nilOl_dataout, niiOOi); and(wire_nillO_dataout, wire_nilOO_dataout, ~(niiOOi)); assign wire_nilO_dataout = (niiOiO === 1'b1) ? n10lO : wire_nlOO_dataout; and(wire_nilOi_dataout, wire_niO1i_dataout, ~(niiOOi)); or(wire_nilOl_dataout, wire_niO1l_dataout, niiilO); and(wire_nilOO_dataout, (~ niiiOl), ~(niiilO)); and(wire_niO_dataout, niOOi, niiOli); assign wire_niO00i_dataout = (niiOOi === 1'b1) ? nl00OO : nl0iil; assign wire_niO00l_dataout = (niiOOi === 1'b1) ? nl0i1i : nl0iiO; assign wire_niO00O_dataout = (niiOOi === 1'b1) ? nl0i1l : nl0ili; assign wire_niO01i_dataout = (niiOOi === 1'b1) ? wire_niOOOi_dataout : wire_niOiOO_dataout; assign wire_niO01l_dataout = (niiOOi === 1'b1) ? wire_niOOOl_dataout : wire_niOl1i_dataout; and(wire_niO01O_dataout, nl0iii, ~(niiOOi)); assign wire_niO0ii_dataout = (niiOOi === 1'b1) ? nl0i1O : nl0ill; assign wire_niO0il_dataout = (niiOOi === 1'b1) ? nl0i0i : nl0ilO; assign wire_niO0iO_dataout = (niiOOi === 1'b1) ? nl0i0l : nl0iOi; assign wire_niO0li_dataout = (niiOOi === 1'b1) ? nl0i0O : nl0iOl; and(wire_niO0ll_dataout, nl00il, niiOOi); and(wire_niO0lO_dataout, nl00iO, niiOOi); and(wire_niO0Oi_dataout, nl00li, niiOOi); and(wire_niO0Ol_dataout, nl00ll, niiOOi); and(wire_niO0OO_dataout, nl00lO, niiOOi); assign wire_niO10i_dataout = (niiOOi === 1'b1) ? wire_niOO1i_dataout : wire_niOi1O_dataout; assign wire_niO10l_dataout = (niiOOi === 1'b1) ? wire_niOO1l_dataout : wire_niOi0i_dataout; assign wire_niO10O_dataout = (niiOOi === 1'b1) ? wire_niOO1O_dataout : wire_niOi0l_dataout; and(wire_niO11l_dataout, wire_nlO_dataout, niiOOi); and(wire_niO11O_dataout, wire_nlO_dataout, ~(niiOOi)); and(wire_niO1i_dataout, wire_niO1O_dataout, ~(niiilO)); assign wire_niO1ii_dataout = (niiOOi === 1'b1) ? wire_niOO0i_dataout : wire_niOi0O_dataout; assign wire_niO1il_dataout = (niiOOi === 1'b1) ? wire_niOO0l_dataout : wire_niOiii_dataout; assign wire_niO1iO_dataout = (niiOOi === 1'b1) ? wire_niOO0O_dataout : wire_niOiil_dataout; and(wire_niO1l_dataout, niiiOi, niiiOl); assign wire_niO1li_dataout = (niiOOi === 1'b1) ? wire_niOOii_dataout : wire_niOiiO_dataout; assign wire_niO1ll_dataout = (niiOOi === 1'b1) ? wire_niOOil_dataout : wire_niOili_dataout; assign wire_niO1lO_dataout = (niiOOi === 1'b1) ? wire_niOOiO_dataout : wire_niOill_dataout; and(wire_niO1O_dataout, (~ niiiOi), niiiOl); assign wire_niO1Oi_dataout = (niiOOi === 1'b1) ? wire_niOOli_dataout : wire_niOilO_dataout; assign wire_niO1Ol_dataout = (niiOOi === 1'b1) ? wire_niOOll_dataout : wire_niOiOi_dataout; assign wire_niO1OO_dataout = (niiOOi === 1'b1) ? wire_niOOlO_dataout : wire_niOiOl_dataout; assign wire_niOi_dataout = (niiOiO === 1'b1) ? n10Oi : wire_n1i_dataout; and(wire_niOi0i_dataout, wire_niOl1O_dataout, ~((~ wire_nlO_dataout))); and(wire_niOi0l_dataout, wire_niOl0i_dataout, ~((~ wire_nlO_dataout))); and(wire_niOi0O_dataout, wire_niOl0l_dataout, ~((~ wire_nlO_dataout))); and(wire_niOi1i_dataout, nl00Oi, niiOOi); and(wire_niOi1l_dataout, nl00Ol, niiOOi); and(wire_niOi1O_dataout, wire_niOl1l_dataout, ~((~ wire_nlO_dataout))); and(wire_niOiii_dataout, wire_niOl0O_dataout, ~((~ wire_nlO_dataout))); and(wire_niOiil_dataout, wire_niOlii_dataout, ~((~ wire_nlO_dataout))); and(wire_niOiiO_dataout, wire_niOlil_dataout, ~((~ wire_nlO_dataout))); and(wire_niOili_dataout, wire_niOliO_dataout, ~((~ wire_nlO_dataout))); and(wire_niOill_dataout, wire_niOlli_dataout, ~((~ wire_nlO_dataout))); and(wire_niOilO_dataout, wire_niOlll_dataout, ~((~ wire_nlO_dataout))); and(wire_niOiOi_dataout, wire_niOllO_dataout, ~((~ wire_nlO_dataout))); and(wire_niOiOl_dataout, wire_niOlOi_dataout, ~((~ wire_nlO_dataout))); and(wire_niOiOO_dataout, wire_niOlOl_dataout, ~((~ wire_nlO_dataout))); assign wire_niOl_dataout = (niiOiO === 1'b1) ? n10Ol : wire_n1l_dataout; and(wire_niOl0i_dataout, nl0O0l, ~(ni01Oi)); and(wire_niOl0l_dataout, nl0O0O, ~(ni01Oi)); and(wire_niOl0O_dataout, nl0Oii, ~(ni01Oi)); or(wire_niOl1i_dataout, wire_niOlOO_dataout, (~ wire_nlO_dataout)); and(wire_niOl1l_dataout, nl0O1O, ~(ni01Oi)); and(wire_niOl1O_dataout, nl0O0i, ~(ni01Oi)); and(wire_niOlii_dataout, nl0Oil, ~(ni01Oi)); and(wire_niOlil_dataout, nl0OiO, ~(ni01Oi)); and(wire_niOliO_dataout, nl0Oli, ~(ni01Oi)); and(wire_niOlli_dataout, nl0Oll, ~(ni01Oi)); or(wire_niOlll_dataout, nl0OlO, ni01Oi); and(wire_niOllO_dataout, nl0OOi, ~(ni01Oi)); and(wire_niOlOi_dataout, nl0OOl, ~(ni01Oi)); and(wire_niOlOl_dataout, nli11i, ~(ni01Oi)); and(wire_niOlOO_dataout, nli11O, ~(ni01Oi)); assign wire_niOO_dataout = (niiOiO === 1'b1) ? n10OO : wire_n1O_dataout; and(wire_niOO0i_dataout, wire_nl111O_dataout, ~((~ wire_nlO_dataout))); and(wire_niOO0l_dataout, wire_nl110i_dataout, ~((~ wire_nlO_dataout))); and(wire_niOO0O_dataout, wire_nl110l_dataout, ~((~ wire_nlO_dataout))); and(wire_niOO1i_dataout, wire_niOOOO_dataout, ~((~ wire_nlO_dataout))); and(wire_niOO1l_dataout, wire_nl111i_dataout, ~((~ wire_nlO_dataout))); and(wire_niOO1O_dataout, wire_nl111l_dataout, ~((~ wire_nlO_dataout))); and(wire_niOOii_dataout, wire_nl110O_dataout, ~((~ wire_nlO_dataout))); and(wire_niOOil_dataout, wire_nl11ii_dataout, ~((~ wire_nlO_dataout))); and(wire_niOOiO_dataout, wire_nl11il_dataout, ~((~ wire_nlO_dataout))); and(wire_niOOli_dataout, wire_nl11iO_dataout, ~((~ wire_nlO_dataout))); and(wire_niOOll_dataout, wire_nl11li_dataout, ~((~ wire_nlO_dataout))); and(wire_niOOlO_dataout, wire_nl11ll_dataout, ~((~ wire_nlO_dataout))); and(wire_niOOOi_dataout, wire_nl11lO_dataout, ~((~ wire_nlO_dataout))); or(wire_niOOOl_dataout, wire_nl11Oi_dataout, (~ wire_nlO_dataout)); and(wire_niOOOO_dataout, nl0O1O, ~(ni01Ol)); and(wire_nl000i_dataout, nl0OOi, ~(wire_nlO_dataout)); and(wire_nl000l_dataout, nl0OOl, ~(wire_nlO_dataout)); or(wire_nl000O_dataout, nli11i, wire_nlO_dataout); and(wire_nl001i_dataout, nl0Oli, ~(wire_nlO_dataout)); and(wire_nl001l_dataout, nl0Oll, ~(wire_nlO_dataout)); and(wire_nl001O_dataout, nl0OlO, ~(wire_nlO_dataout)); and(wire_nl00ii_dataout, nli11O, ~(wire_nlO_dataout)); and(wire_nl010i_dataout, nl0OlO, ~(ni001i)); and(wire_nl010l_dataout, nl0OOi, ~(ni001i)); or(wire_nl010O_dataout, nl0OOl, ni001i); and(wire_nl011i_dataout, nl0OiO, ~(ni001i)); and(wire_nl011l_dataout, nl0Oli, ~(ni001i)); and(wire_nl011O_dataout, nl0Oll, ~(ni001i)); and(wire_nl01ii_dataout, nli11i, ~(ni001i)); and(wire_nl01il_dataout, nli11O, ~(ni001i)); and(wire_nl01iO_dataout, nl0O1O, ~(wire_nlO_dataout)); and(wire_nl01li_dataout, nl0O0i, ~(wire_nlO_dataout)); and(wire_nl01ll_dataout, nl0O0l, ~(wire_nlO_dataout)); and(wire_nl01lO_dataout, nl0O0O, ~(wire_nlO_dataout)); and(wire_nl01Oi_dataout, nl0Oii, ~(wire_nlO_dataout)); and(wire_nl01Ol_dataout, nl0Oil, ~(wire_nlO_dataout)); and(wire_nl01OO_dataout, nl0OiO, ~(wire_nlO_dataout)); assign wire_nl0i_dataout = (niiOiO === 1'b1) ? n1i0i : wire_nii_dataout; assign wire_nl0l_dataout = (niiOiO === 1'b1) ? n101l : wire_nil_dataout; assign wire_nl0O_dataout = (niiOiO === 1'b1) ? n101O : wire_niO_dataout; assign wire_nl100i_dataout = (niiOOi === 1'b1) ? wire_nl1O1i_dataout : wire_nl1i1O_dataout; assign wire_nl100l_dataout = (niiOOi === 1'b1) ? wire_nl1O1l_dataout : wire_nl1i0i_dataout; assign wire_nl100O_dataout = (niiOOi === 1'b1) ? wire_nl1O1O_dataout : wire_nl1i0l_dataout; assign wire_nl101i_dataout = (niiOOi === 1'b1) ? wire_nl1lOi_dataout : wire_nl10OO_dataout; assign wire_nl101l_dataout = (niiOOi === 1'b1) ? wire_nl1lOl_dataout : wire_nl1i1i_dataout; assign wire_nl101O_dataout = (niiOOi === 1'b1) ? wire_nl1lOO_dataout : wire_nl1i1l_dataout; assign wire_nl10ii_dataout = (niiOOi === 1'b1) ? wire_nl1O0i_dataout : wire_nl1i0O_dataout; assign wire_nl10il_dataout = (niiOOi === 1'b1) ? wire_nl1O0l_dataout : wire_nl1iii_dataout; assign wire_nl10iO_dataout = (niiOOi === 1'b1) ? wire_nl1O0O_dataout : wire_nl1iil_dataout; assign wire_nl10li_dataout = (niiOOi === 1'b1) ? wire_nl1Oii_dataout : wire_nl1iiO_dataout; assign wire_nl10ll_dataout = (niiOOi === 1'b1) ? wire_nl1Oil_dataout : wire_nl1ili_dataout; assign wire_nl10lO_dataout = (niiOOi === 1'b1) ? wire_nl1OiO_dataout : wire_nl1ill_dataout; and(wire_nl10Oi_dataout, wire_nl1ilO_dataout, ~((~ wire_nlO_dataout))); and(wire_nl10Ol_dataout, wire_nl1iOi_dataout, ~((~ wire_nlO_dataout))); and(wire_nl10OO_dataout, wire_nl1iOl_dataout, ~((~ wire_nlO_dataout))); and(wire_nl110i_dataout, nl0Oii, ~(ni01Ol)); and(wire_nl110l_dataout, nl0Oil, ~(ni01Ol)); and(wire_nl110O_dataout, nl0OiO, ~(ni01Ol)); and(wire_nl111i_dataout, nl0O0i, ~(ni01Ol)); and(wire_nl111l_dataout, nl0O0l, ~(ni01Ol)); and(wire_nl111O_dataout, nl0O0O, ~(ni01Ol)); and(wire_nl11ii_dataout, nl0Oli, ~(ni01Ol)); and(wire_nl11il_dataout, nl0Oll, ~(ni01Ol)); or(wire_nl11iO_dataout, nl0OlO, ni01Ol); and(wire_nl11li_dataout, nl0OOi, ~(ni01Ol)); and(wire_nl11ll_dataout, nl0OOl, ~(ni01Ol)); and(wire_nl11lO_dataout, nli11i, ~(ni01Ol)); and(wire_nl11Oi_dataout, nli11O, ~(ni01Ol)); assign wire_nl11Ol_dataout = (niiOOi === 1'b1) ? wire_nl1lll_dataout : wire_nl10Oi_dataout; assign wire_nl11OO_dataout = (niiOOi === 1'b1) ? wire_nl1llO_dataout : wire_nl10Ol_dataout; assign wire_nl1i_dataout = (niiOiO === 1'b1) ? n1i1i : wire_n0i_dataout; and(wire_nl1i0i_dataout, wire_nl1l1O_dataout, ~((~ wire_nlO_dataout))); and(wire_nl1i0l_dataout, wire_nl1l0i_dataout, ~((~ wire_nlO_dataout))); and(wire_nl1i0O_dataout, wire_nl1l0l_dataout, ~((~ wire_nlO_dataout))); and(wire_nl1i1i_dataout, wire_nl1iOO_dataout, ~((~ wire_nlO_dataout))); and(wire_nl1i1l_dataout, wire_nl1l1i_dataout, ~((~ wire_nlO_dataout))); and(wire_nl1i1O_dataout, wire_nl1l1l_dataout, ~((~ wire_nlO_dataout))); and(wire_nl1iii_dataout, wire_nl1l0O_dataout, ~((~ wire_nlO_dataout))); and(wire_nl1iil_dataout, wire_nl1lii_dataout, ~((~ wire_nlO_dataout))); and(wire_nl1iiO_dataout, wire_nl1lil_dataout, ~((~ wire_nlO_dataout))); and(wire_nl1ili_dataout, wire_nl1liO_dataout, ~((~ wire_nlO_dataout))); or(wire_nl1ill_dataout, wire_nl1lli_dataout, (~ wire_nlO_dataout)); and(wire_nl1ilO_dataout, nl0O1O, ~(ni01OO)); and(wire_nl1iOi_dataout, nl0O0i, ~(ni01OO)); and(wire_nl1iOl_dataout, nl0O0l, ~(ni01OO)); and(wire_nl1iOO_dataout, nl0O0O, ~(ni01OO)); assign wire_nl1l_dataout = (niiOiO === 1'b1) ? n1i1l : wire_n0l_dataout; and(wire_nl1l0i_dataout, nl0Oli, ~(ni01OO)); and(wire_nl1l0l_dataout, nl0Oll, ~(ni01OO)); and(wire_nl1l0O_dataout, nl0OlO, ~(ni01OO)); and(wire_nl1l1i_dataout, nl0Oii, ~(ni01OO)); and(wire_nl1l1l_dataout, nl0Oil, ~(ni01OO)); and(wire_nl1l1O_dataout, nl0OiO, ~(ni01OO)); and(wire_nl1lii_dataout, nl0OOi, ~(ni01OO)); or(wire_nl1lil_dataout, nl0OOl, ni01OO); and(wire_nl1liO_dataout, nli11i, ~(ni01OO)); and(wire_nl1lli_dataout, nli11O, ~(ni01OO)); and(wire_nl1lll_dataout, wire_nl1Oli_dataout, ~((~ wire_nlO_dataout))); and(wire_nl1llO_dataout, wire_nl1Oll_dataout, ~((~ wire_nlO_dataout))); and(wire_nl1lOi_dataout, wire_nl1OlO_dataout, ~((~ wire_nlO_dataout))); and(wire_nl1lOl_dataout, wire_nl1OOi_dataout, ~((~ wire_nlO_dataout))); and(wire_nl1lOO_dataout, wire_nl1OOl_dataout, ~((~ wire_nlO_dataout))); assign wire_nl1O_dataout = (niiOiO === 1'b1) ? n1i1O : wire_n0O_dataout; and(wire_nl1O0i_dataout, wire_nl011O_dataout, ~((~ wire_nlO_dataout))); and(wire_nl1O0l_dataout, wire_nl010i_dataout, ~((~ wire_nlO_dataout))); and(wire_nl1O0O_dataout, wire_nl010l_dataout, ~((~ wire_nlO_dataout))); and(wire_nl1O1i_dataout, wire_nl1OOO_dataout, ~((~ wire_nlO_dataout))); and(wire_nl1O1l_dataout, wire_nl011i_dataout, ~((~ wire_nlO_dataout))); and(wire_nl1O1O_dataout, wire_nl011l_dataout, ~((~ wire_nlO_dataout))); and(wire_nl1Oii_dataout, wire_nl010O_dataout, ~((~ wire_nlO_dataout))); and(wire_nl1Oil_dataout, wire_nl01ii_dataout, ~((~ wire_nlO_dataout))); or(wire_nl1OiO_dataout, wire_nl01il_dataout, (~ wire_nlO_dataout)); and(wire_nl1Oli_dataout, nl0O1O, ~(ni001i)); and(wire_nl1Oll_dataout, nl0O0i, ~(ni001i)); and(wire_nl1OlO_dataout, nl0O0l, ~(ni001i)); and(wire_nl1OOi_dataout, nl0O0O, ~(ni001i)); and(wire_nl1OOl_dataout, nl0Oii, ~(ni001i)); and(wire_nl1OOO_dataout, nl0Oil, ~(ni001i)); and(wire_nli_dataout, rbisten_tx, ((~ rbist_sel[0]) & rbist_sel[1])); and(wire_nli00i_dataout, wire_nli0Oi_o[1], ni001O); and(wire_nli00l_dataout, wire_nli0Oi_o[2], ni001O); and(wire_nli00O_dataout, wire_nli0Oi_o[3], ni001O); and(wire_nli01i_dataout, wire_nli0lO_o[5], ni001O); and(wire_nli01l_dataout, wire_nli0lO_o[6], ni001O); and(wire_nli01O_dataout, wire_nli0Oi_o[0], ni001O); and(wire_nli0ii_dataout, wire_nli0Oi_o[4], ni001O); and(wire_nli0il_dataout, wire_nli0Oi_o[5], ni001O); and(wire_nli0iO_dataout, wire_nli0Oi_o[6], ni001O); and(wire_nli0li_dataout, wire_nli0Oi_o[7], ni001O); and(wire_nli10i_dataout, wire_nli0ll_o[0], ni001O); and(wire_nli10l_dataout, wire_nli0ll_o[1], ni001O); and(wire_nli10O_dataout, wire_nli0ll_o[2], ni001O); and(wire_nli1ii_dataout, wire_nli0ll_o[3], ni001O); and(wire_nli1il_dataout, wire_nli0ll_o[4], ni001O); and(wire_nli1iO_dataout, wire_nli0ll_o[5], ni001O); and(wire_nli1li_dataout, wire_nli0ll_o[6], ni001O); and(wire_nli1ll_dataout, wire_nli0lO_o[0], ni001O); and(wire_nli1lO_dataout, wire_nli0lO_o[1], ni001O); and(wire_nli1Oi_dataout, wire_nli0lO_o[2], ni001O); and(wire_nli1Ol_dataout, wire_nli0lO_o[3], ni001O); and(wire_nli1OO_dataout, wire_nli0lO_o[4], ni001O); and(wire_nlii_dataout, niOOl, niiOli); and(wire_nlil_dataout, niOOO, niiOli); and(wire_nlil0O_dataout, wire_nllO1O_dataout, n1iOl); and(wire_nlilii_dataout, wire_nllO0i_dataout, n1iOl); and(wire_nlilil_dataout, niiOOi, n1iOO); and(wire_nlill_dataout, wire_nliOl_o[0], wire_n0iiO_o); and(wire_nlilli_dataout, wire_nlO10l_dataout, n1l1i); and(wire_nlilll_dataout, wire_nlO10O_dataout, n1l1i); and(wire_nlillO_dataout, wire_nlOi0O_dataout, n1l1l); and(wire_nlilO_dataout, wire_nliOl_o[1], wire_n0iiO_o); and(wire_nliO_dataout, nl11i, niiOli); and(wire_nliOi_dataout, wire_nliOl_o[2], wire_n0iiO_o); and(wire_nliOll_dataout, (~ niiOOi), n1ilO); assign wire_nliOO_dataout = (wire_n0iii_o === 1'b1) ? wire_nllli_o[0] : wire_nll0l_dataout; and(wire_nll_dataout, rbisten_tx, (rbist_sel[0] & (~ rbist_sel[1]))); assign wire_nll0i_dataout = (wire_n0iii_o === 1'b1) ? wire_nllli_o[4] : wire_nlliO_dataout; and(wire_nll0l_dataout, niOii, ~(wire_n0iil_o)); and(wire_nll0O_dataout, niOil, ~(wire_n0iil_o)); and(wire_nll11i_dataout, wire_nlO1ll_dataout, n1l1i); assign wire_nll1i_dataout = (wire_n0iii_o === 1'b1) ? wire_nllli_o[1] : wire_nll0O_dataout; assign wire_nll1l_dataout = (wire_n0iii_o === 1'b1) ? wire_nllli_o[2] : wire_nllii_dataout; assign wire_nll1O_dataout = (wire_n0iii_o === 1'b1) ? wire_nllli_o[3] : wire_nllil_dataout; and(wire_nll1Oi_dataout, wire_nlOlOO_dataout, n1l0l); and(wire_nlli_dataout, nl11l, niiOli); and(wire_nllii_dataout, niOiO, ~(wire_n0iil_o)); and(wire_nllil_dataout, niOli, ~(wire_n0iil_o)); and(wire_nlliO_dataout, niOll, ~(wire_n0iil_o)); and(wire_nlll_dataout, nl11O, niiOli); and(wire_nlllil_dataout, ni0l0l, ~(ni0Oii)); and(wire_nllliO_dataout, ni0l0l, ni0Oii); and(wire_nlllli_dataout, wire_nlllOl_dataout, ~(niiOOi)); assign wire_nlllll_dataout = (niiOOi === 1'b1) ? (~ ni0lii) : wire_nlllOO_dataout; and(wire_nllllO_dataout, wire_nllO1i_dataout, niiOOi); and(wire_nlllOi_dataout, wire_nllO1l_dataout, niiOOi); assign wire_nlllOl_dataout = (ni0Oii === 1'b1) ? ni0l0l : ni0l0O; assign wire_nlllOO_dataout = (ni0Oii === 1'b1) ? (~ ni0l0l) : (~ ni0l0O); and(wire_nllO_dataout, nl10i, niiOli); assign wire_nllO0i_dataout = (niiOOi === 1'b1) ? ni0lil : ni0liO; and(wire_nllO0l_dataout, wire_nllOll_dataout, niiOOi); and(wire_nllO0O_dataout, wire_nllOlO_dataout, niiOOi); and(wire_nllO1i_dataout, ni0lii, ~(ni0Oii)); and(wire_nllO1l_dataout, ni0lii, ni0Oii); assign wire_nllO1O_dataout = (niiOOi === 1'b1) ? (~ ni0lil) : (~ ni0liO); and(wire_nllOii_dataout, wire_nllOOi_dataout, niiOOi); and(wire_nllOil_dataout, wire_nllOOl_dataout, niiOOi); and(wire_nllOiO_dataout, wire_nllOOO_dataout, niiOOi); and(wire_nllOli_dataout, ni0lli, niiOOi); and(wire_nllOll_dataout, wire_nlO11i_dataout, ~(ni0lli)); and(wire_nllOlO_dataout, wire_nlO11l_dataout, ~(ni0lli)); and(wire_nllOOi_dataout, wire_nlO11O_dataout, ~(ni0lli)); and(wire_nllOOl_dataout, wire_nlO10i_dataout, ~(ni0lli)); and(wire_nllOOO_dataout, (~ ni0lll), ~(ni0lli)); and(wire_nlO_dataout, rbisten_tx, (((~ rbist_sel[0]) & (~ rbist_sel[1])) & (niiOll6 ^ niiOll5))); and(wire_nlO00i_dataout, wire_nlO0li_dataout, ~(ni0lOO)); and(wire_nlO00l_dataout, ni0lOi, ~(ni0lOO)); and(wire_nlO00O_dataout, wire_nlO0ll_dataout, ~(ni0lOi)); and(wire_nlO01i_dataout, wire_nlO0ii_dataout, ~(ni0lOO)); and(wire_nlO01l_dataout, wire_nlO0il_dataout, ~(ni0lOO)); and(wire_nlO01O_dataout, wire_nlO0iO_dataout, ~(ni0lOO)); and(wire_nlO0ii_dataout, wire_nlO0lO_dataout, ~(ni0lOi)); and(wire_nlO0il_dataout, wire_nlO0Oi_dataout, ~(ni0lOi)); and(wire_nlO0iO_dataout, wire_nlO0Ol_dataout, ~(ni0lOi)); and(wire_nlO0li_dataout, (~ ni0lOl), ~(ni0lOi)); and(wire_nlO0ll_dataout, wire_nlO0OO_dataout, ni0lOl); and(wire_nlO0lO_dataout, wire_nlOi1i_dataout, ni0lOl); and(wire_nlO0Oi_dataout, wire_nlOi1l_dataout, ni0lOl); and(wire_nlO0Ol_dataout, ni0Oii, ni0lOl); and(wire_nlO0OO_dataout, wire_nlOi1O_dataout, ~(ni0Oii)); and(wire_nlO10i_dataout, ni0Oii, ni0lll); or(wire_nlO10l_dataout, (~ ni0llO), ~(niiOOi)); and(wire_nlO10O_dataout, ni0llO, niiOOi); and(wire_nlO11i_dataout, wire_nlO0OO_dataout, ni0lll); and(wire_nlO11l_dataout, wire_nlOi1i_dataout, ni0lll); and(wire_nlO11O_dataout, wire_nlOi1l_dataout, ni0lll); and(wire_nlO1ii_dataout, wire_nlO1OO_dataout, ~(niiOOi)); and(wire_nlO1il_dataout, wire_nlO01i_dataout, ~(niiOOi)); and(wire_nlO1iO_dataout, wire_nlO01l_dataout, ~(niiOOi)); and(wire_nlO1li_dataout, wire_nlO01O_dataout, ~(niiOOi)); assign wire_nlO1ll_dataout = (niiOOi === 1'b1) ? ni0llO : ni0lOO; and(wire_nlO1lO_dataout, wire_nlO00i_dataout, ~(niiOOi)); and(wire_nlO1Oi_dataout, (~ ni0llO), niiOOi); and(wire_nlO1Ol_dataout, wire_nlO00l_dataout, ~(niiOOi)); and(wire_nlO1OO_dataout, wire_nlO00O_dataout, ~(ni0lOO)); and(wire_nlOi_dataout, nl10l, niiOli); and(wire_nlOi0i_dataout, ni0Oli, ~(ni0Oll)); assign wire_nlOi0O_dataout = (niiOOi === 1'b1) ? wire_nlOl1O_dataout : wire_nlOiiO_dataout; and(wire_nlOi1i_dataout, wire_nlOi0i_dataout, ~(ni0Oii)); and(wire_nlOi1l_dataout, ni0Oll, ~(ni0Oii)); and(wire_nlOi1O_dataout, (~ ni0Oli), ~(ni0Oll)); assign wire_nlOiii_dataout = (niiOOi === 1'b1) ? wire_nlOl0i_dataout : wire_nlOili_dataout; assign wire_nlOiil_dataout = (niiOOi === 1'b1) ? wire_nlOl0l_dataout : wire_nlOill_dataout; assign wire_nlOiiO_dataout = (ni0Oii === 1'b1) ? wire_nlOiOO_dataout : wire_nlOilO_dataout; assign wire_nlOili_dataout = (ni0Oii === 1'b1) ? wire_nlOl1i_dataout : wire_nlOiOi_dataout; assign wire_nlOill_dataout = (ni0Oii === 1'b1) ? wire_nlOl1l_dataout : wire_nlOiOl_dataout; and(wire_nlOilO_dataout, ni0O1i, ~(ni0O0i)); or(wire_nlOiOi_dataout, ni0O1i, ni0O0i); and(wire_nlOiOl_dataout, (~ ni0O1i), ~(ni0O0i)); and(wire_nlOiOO_dataout, ni0O1l, ~(ni0O0O)); and(wire_nlOl_dataout, nl10O, niiOli); assign wire_nlOl0i_dataout = (ni0Oii === 1'b1) ? wire_nlOlli_dataout : wire_nlOlii_dataout; assign wire_nlOl0l_dataout = (ni0Oii === 1'b1) ? wire_nlOlll_dataout : wire_nlOlil_dataout; and(wire_nlOl0O_dataout, ni0O0i, ~(ni0O1O)); or(wire_nlOl1i_dataout, ni0O1l, ni0O0O); and(wire_nlOl1l_dataout, (~ ni0O1l), ~(ni0O0O)); assign wire_nlOl1O_dataout = (ni0Oii === 1'b1) ? wire_nlOliO_dataout : wire_nlOl0O_dataout; or(wire_nlOlii_dataout, ni0O0i, ni0O1O); and(wire_nlOlil_dataout, (~ ni0O0i), ~(ni0O1O)); and(wire_nlOliO_dataout, ni0O0O, ~(ni0O0l)); or(wire_nlOlli_dataout, ni0O0O, ni0O0l); and(wire_nlOlll_dataout, (~ ni0O0O), ~(ni0O0l)); and(wire_nlOllO_dataout, (~ ni0OiO), niiOOi); or(wire_nlOlOi_dataout, wire_nlOO1l_dataout, niiOOi); and(wire_nlOlOl_dataout, ni0Oii, ~(niiOOi)); and(wire_nlOlOO_dataout, wire_nlOO1O_dataout, ~(niiOOi)); and(wire_nlOO_dataout, nl1ii, niiOli); and(wire_nlOO0i_dataout, wire_nlOO0O_dataout, ~(ni0Oii)); and(wire_nlOO0l_dataout, ni0Oil, ni0OiO); and(wire_nlOO0O_dataout, (~ ni0Oil), ni0OiO); and(wire_nlOO1i_dataout, wire_nlOO0i_dataout, ~(niiOOi)); and(wire_nlOO1l_dataout, wire_nlOO0l_dataout, ~(ni0Oii)); and(wire_nlOO1O_dataout, (~ ni0OiO), ~(ni0Oii)); oper_add n00Oi ( .a({n101i, n11OO, n11Ol, n11Oi, n11lO, n11ll, n11li, n11iO, n11il}), .b({{8{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_n00Oi_o)); defparam n00Oi.sgate_representation = 0, n00Oi.width_a = 9, n00Oi.width_b = 9, n00Oi.width_o = 9; oper_add n01iO ( .a({n11ii, n110O, n110l, n110i}), .b({{3{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_n01iO_o)); defparam n01iO.sgate_representation = 0, n01iO.width_a = 4, n01iO.width_b = 4, n01iO.width_o = 4; oper_add n1lOi ( .a({nlOOiO, nlOOil, nliliO}), .b({{2{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_n1lOi_o)); defparam n1lOi.sgate_representation = 0, n1lOi.width_a = 3, n1lOi.width_b = 3, n1lOi.width_o = 3; oper_add n1Oll ( .a({nlOOOO, nlOOOl, nlOOOi, nlOOlO, nlOOll, nlOOli}), .b({{5{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_n1Oll_o)); defparam n1Oll.sgate_representation = 0, n1Oll.width_a = 6, n1Oll.width_b = 6, n1Oll.width_o = 6; oper_add n1OOO ( .a({n111O, n111l, n111i}), .b({{2{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_n1OOO_o)); defparam n1OOO.sgate_representation = 0, n1OOO.width_a = 3, n1OOO.width_b = 3, n1OOO.width_o = 3; oper_add nli0ll ( .a({nl00Ol, nl00Oi, nl00lO, nl00ll, nl00li, nl00iO, nl00il}), .b({{6{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_nli0ll_o)); defparam nli0ll.sgate_representation = 0, nli0ll.width_a = 7, nli0ll.width_b = 7, nli0ll.width_o = 7; oper_add nli0lO ( .a({nl0i0O, nl0i0l, nl0i0i, nl0i1O, nl0i1l, nl0i1i, nl00OO}), .b({{6{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_nli0lO_o)); defparam nli0lO.sgate_representation = 0, nli0lO.width_a = 7, nli0lO.width_b = 7, nli0lO.width_o = 7; oper_add nli0Oi ( .a({nl0iOl, nl0iOi, nl0ilO, nl0ill, nl0ili, nl0iiO, nl0iil, nl0iii}), .b({{7{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_nli0Oi_o)); defparam nli0Oi.sgate_representation = 0, nli0Oi.width_a = 8, nli0Oi.width_b = 8, nli0Oi.width_o = 8; oper_add nliOl ( .a({((niilOO16 ^ niilOO15) & niO0O), niO0l, n0lOi}), .b({{2{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_nliOl_o)); defparam nliOl.sgate_representation = 0, nliOl.width_a = 3, nliOl.width_b = 3, nliOl.width_o = 3; oper_add nllli ( .a({niOll, niOli, niOiO, ((niiO1i14 ^ niiO1i13) & niOil), niOii}), .b({{4{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_nllli_o)); defparam nllli.sgate_representation = 0, nllli.width_a = 5, nllli.width_b = 5, nllli.width_o = 5; oper_selector n0iii ( .data({1'b0, wire_niiOl_dataout, (~ niiill)}), .o(wire_n0iii_o), .sel({nii10l, nl0iO, nl0il})); defparam n0iii.width_data = 3, n0iii.width_sel = 3; oper_selector n0iil ( .data({1'b0, wire_niiOO_dataout, niiill}), .o(wire_n0iil_o), .sel({nii10l, nl0iO, nl0il})); defparam n0iil.width_data = 3, n0iil.width_sel = 3; oper_selector n0iiO ( .data({1'b0, wire_nilOi_dataout, wire_nii1O_dataout, {2{(~ niiiil)}}}), .o(wire_n0iiO_o), .sel({ni0OOO, nli0O, nl01l, nl01i, nl1OO})); defparam n0iiO.width_data = 5, n0iiO.width_sel = 5; oper_selector n0ilO ( .data({1'b0, niiOOi}), .o(wire_n0ilO_o), .sel({nii11i, (~ nii11i)})); defparam n0ilO.width_data = 2, n0ilO.width_sel = 2; oper_selector n0iOl ( .data({1'b0, niiiil, (~ niiiil)}), .o(wire_n0iOl_o), .sel({nii11l, nl01i, nl1OO})); defparam n0iOl.width_data = 3, n0iOl.width_sel = 3; oper_selector n0l1i ( .data({1'b0, wire_nii1l_dataout, (~ niiiil)}), .o(wire_n0l1i_o), .sel({nii11O, nl01l, nl01i})); defparam n0l1i.width_data = 3, n0l1i.width_sel = 3; oper_selector n0l1O ( .data({1'b0, niiOOi, 1'b1, wire_nii1O_dataout}), .o(wire_n0l1O_o), .sel({nii10i, nl0ii, (((nl00O | nl00l) | nl00i) | nl01O), nl01l})); defparam n0l1O.width_data = 4, n0l1O.width_sel = 4; oper_selector n0lii ( .data({1'b0, wire_niili_dataout, wire_nil1i_dataout}), .o(wire_n0lii_o), .sel({nii10l, nl0iO, nl0il})); defparam n0lii.width_data = 3, n0lii.width_sel = 3; oper_selector n0lil ( .data({1'b0, wire_niill_dataout, wire_nil1l_dataout}), .o(wire_n0lil_o), .sel({nii10l, nl0iO, nl0il})); defparam n0lil.width_data = 3, n0lil.width_sel = 3; oper_selector n0liO ( .data({1'b0, wire_niilO_dataout, wire_nil1O_dataout}), .o(wire_n0liO_o), .sel({nii10l, nl0iO, nl0il})); defparam n0liO.width_data = 3, n0liO.width_sel = 3; oper_selector n0lli ( .data({1'b0, wire_niiOi_dataout, wire_nil0i_dataout}), .o(wire_n0lli_o), .sel({nii10l, nl0iO, nl0il})); defparam n0lli.width_data = 3, n0lli.width_sel = 3; oper_selector n0lOl ( .data({1'b0, niiOOi, 1'b1}), .o(wire_n0lOl_o), .sel({nii10O, nl0ll, nl0li})); defparam n0lOl.width_data = 3, n0lOl.width_sel = 3; oper_selector n0O0l ( .data({1'b0, niiOOi, 1'b1}), .o(wire_n0O0l_o), .sel({nii1il, nl0OO, nl0Ol})); defparam n0O0l.width_data = 3, n0O0l.width_sel = 3; oper_selector n0O1l ( .data({1'b0, niiOOi, 1'b1}), .o(wire_n0O1l_o), .sel({nii1ii, nl0Oi, nl0lO})); defparam n0O1l.width_data = 3, n0O1l.width_sel = 3; oper_selector n0Oil ( .data({1'b0, niiOOi, 1'b1}), .o(wire_n0Oil_o), .sel({nii1iO, nli1l, nli1i})); defparam n0Oil.width_data = 3, n0Oil.width_sel = 3; oper_selector n0Oll ( .data({1'b0, niiOOi, 1'b1}), .o(wire_n0Oll_o), .sel({nii1li, nli0i, nli1O})); defparam n0Oll.width_data = 3, n0Oll.width_sel = 3; oper_selector n0OOl ( .data({1'b0, niiOOi, wire_nilll_dataout, 1'b1, wire_niiOl_dataout, (~ niiill)}), .o(wire_n0OOl_o), .sel({nii1ll, nliil, nli0O, nli0l, nl0iO, nl0il})); defparam n0OOl.width_data = 6, n0OOl.width_sel = 6; oper_selector ni00l ( .data({1'b0, niiOOi}), .o(wire_ni00l_o), .sel({nii00l, (~ nii00l)})); defparam ni00l.width_data = 2, ni00l.width_sel = 2; oper_selector ni01i ( .data({1'b0, ((nii1OO44 ^ nii1OO43) & niiOOi)}), .o(wire_ni01i_o), .sel({nii01i, (~ nii01i)})); defparam ni01i.width_data = 2, ni01i.width_sel = 2; oper_selector ni01O ( .data({1'b0, niiOOi}), .o(wire_ni01O_o), .sel({nii01l, (~ nii01l)})); defparam ni01O.width_data = 2, ni01O.width_sel = 2; oper_selector ni0ii ( .data({1'b0, niiOOi}), .o(wire_ni0ii_o), .sel({nii0ii, ((nii00O40 ^ nii00O39) & (~ nii0ii))})); defparam ni0ii.width_data = 2, ni0ii.width_sel = 2; oper_selector ni0iO ( .data({1'b0, niiOOi}), .o(wire_ni0iO_o), .sel({((nii0li36 ^ nii0li35) & nii0ll), (~ nii0ll)})); defparam ni0iO.width_data = 2, ni0iO.width_sel = 2; oper_selector ni0ll ( .data({1'b0, niiOOi}), .o(wire_ni0ll_o), .sel({nii0Ol, (~ nii0Ol)})); defparam ni0ll.width_data = 2, ni0ll.width_sel = 2; oper_selector ni0Oi ( .data({1'b0, ((nii0OO32 ^ nii0OO31) & wire_nilli_dataout), ((niii1i30 ^ niii1i29) & niiOOi), {7{niiOOi}}}), .o(wire_ni0Oi_o), .sel({((niii1l28 ^ niii1l27) & niii0l), nli0O, nli0i, nl0OO, nl0ll, nl0ii, nl00O, ((niii1O26 ^ niii1O25) & nl00l), ((niii0i24 ^ niii0i23) & nl00i), nl01l})); defparam ni0Oi.width_data = 10, ni0Oi.width_sel = 10; oper_selector ni10i ( .data({niiilO, 1'b0, wire_nii0l_dataout, wire_nii1i_dataout}), .o(wire_ni10i_o), .sel({nlili, nii1Oi, nl01l, nl1OO})); defparam ni10i.width_data = 4, ni10i.width_sel = 4; oper_selector ni11l ( .data({(~ niiilO), (~ niiOOi), wire_nilOi_dataout, 1'b0, wire_nii0i_dataout, wire_ni0OO_dataout}), .o(wire_ni11l_o), .sel({nlili, nliil, nli0O, nii1lO, nl01l, nl1OO})); defparam ni11l.width_data = 6, ni11l.width_sel = 6; oper_selector ni1Ol ( .data({1'b0, niiOOi}), .o(wire_ni1Ol_o), .sel({nii1Ol, (~ nii1Ol)})); defparam ni1Ol.width_data = 2, ni1Ol.width_sel = 2; oper_selector nil00l ( .data({1'b0, 1'b1, wire_niO00O_dataout}), .o(wire_nil00l_o), .sel({(nli11O | nl0O0l), ni1lOO, nl0OOi})); defparam nil00l.width_data = 3, nil00l.width_sel = 3; oper_selector nil01O ( .data({1'b0, 1'b1, niiOOi, wire_niO00l_dataout}), .o(wire_nil01O_o), .sel({nli11O, ni1lOl, nl0OOl, nl0OOi})); defparam nil01O.width_data = 4, nil01O.width_sel = 4; oper_selector nil0il ( .data({1'b0, 1'b1, wire_niO0ii_dataout}), .o(wire_nil0il_o), .sel({nli11O, ni1O1i, nl0OOi})); defparam nil0il.width_data = 3, nil0il.width_sel = 3; oper_selector nil0li ( .data({1'b0, 1'b1, wire_niO0il_dataout}), .o(wire_nil0li_o), .sel({ni1O1O, ni1O1l, nl0OOi})); defparam nil0li.width_data = 3, nil0li.width_sel = 3; oper_selector nil0Oi ( .data({1'b0, (~ niiOOi), wire_niO0iO_dataout, 1'b1}), .o(wire_nil0Oi_o), .sel({ni1O0l, nl0OOl, nl0OOi, ni1O0i})); defparam nil0Oi.width_data = 4, nil0Oi.width_sel = 4; oper_selector nil1li ( .data({1'b0, niiOOi}), .o(wire_nil1li_o), .sel({ni1lll, (~ ni1lll)})); defparam nil1li.width_data = 2, nil1li.width_sel = 2; oper_selector nil1lO ( .data({1'b0, (~ niiOOi), wire_niO01O_dataout, 1'b1}), .o(wire_nil1lO_o), .sel({ni1llO, nl0OOl, nl0OOi, (nl0O0l | nl0O1O)})); defparam nil1lO.width_data = 4, nil1lO.width_sel = 4; oper_selector nil1OO ( .data({1'b0, (~ niiOOi), wire_niO00i_dataout, 1'b1}), .o(wire_nil1OO_o), .sel({ni1lOi, nl0OOl, nl0OOi, (nl0O0l | nl0O0i)})); defparam nil1OO.width_data = 4, nil1OO.width_sel = 4; oper_selector nili0i ( .data({1'b0, niiOOi}), .o(wire_nili0i_o), .sel({ni1Oil, (~ ni1Oil)})); defparam nili0i.width_data = 2, nili0i.width_sel = 2; oper_selector nili0O ( .data({1'b0, niiOOi, wire_niO0ll_dataout, niiOOi}), .o(wire_nili0O_o), .sel({ni1OiO, nl0OOl, nl0OOi, nl0O0O})); defparam nili0O.width_data = 4, nili0O.width_sel = 4; oper_selector nili1i ( .data({1'b0, 1'b1, wire_niO0li_dataout}), .o(wire_nili1i_o), .sel({ni1Oii, ni1O0O, nl0OOi})); defparam nili1i.width_data = 3, nili1i.width_sel = 3; oper_selector niliil ( .data({1'b0, niiOOi, wire_niO0lO_dataout, {5{niiOOi}}}), .o(wire_niliil_o), .sel({ni1Oli, nli11i, nl0OOi, nl0OlO, nl0Oli, nl0Oil, nl0O0O, nl0O0i})); defparam niliil.width_data = 8, niliil.width_sel = 8; oper_selector nilili ( .data({1'b0, {2{niiOOi}}, wire_niO0Oi_dataout, {4{niiOOi}}}), .o(wire_nilili_o), .sel({ni1Oll, nli11i, nl0OOl, nl0OOi, nl0OlO, nl0Oli, nl0Oil, nl0O0i})); defparam nilili.width_data = 8, nilili.width_sel = 8; oper_selector nililO ( .data({1'b0, {2{niiOOi}}, wire_niO0Ol_dataout, {5{niiOOi}}}), .o(wire_nililO_o), .sel({ni1OlO, nli11i, nl0OOl, nl0OOi, nl0OlO, nl0Oli, nl0Oil, nl0O0O, nl0O0i})); defparam nililO.width_data = 9, nililO.width_sel = 9; oper_selector niliOl ( .data({1'b0, {2{niiOOi}}, wire_niO0OO_dataout, {4{niiOOi}}}), .o(wire_niliOl_o), .sel({ni1OOi, nli11i, nl0OOl, nl0OOi, nl0OlO, nl0Oli, nl0O0O, nl0O0i})); defparam niliOl.width_data = 8, niliOl.width_sel = 8; oper_selector nill0O ( .data({wire_nl01iO_dataout, wire_nl11Ol_dataout, 1'b0, wire_niO10i_dataout, wire_niO11O_dataout}), .o(wire_nill0O_o), .sel({nli11O, nli11i, ni011i, nl0OOi, nl0O0i})); defparam nill0O.width_data = 5, nill0O.width_sel = 5; oper_selector nill1i ( .data({1'b0, niiOOi, wire_niOi1i_dataout, {4{niiOOi}}}), .o(wire_nill1i_o), .sel({ni1OOl, nl0OOl, nl0OOi, nl0Oli, nl0Oil, nl0O0O, nl0O0i})); defparam nill1i.width_data = 7, nill1i.width_sel = 7; oper_selector nill1O ( .data({1'b0, {2{niiOOi}}, wire_niOi1l_dataout, {3{niiOOi}}}), .o(wire_nill1O_o), .sel({ni1OOO, nli11i, nl0OOl, nl0OOi, nl0Oil, nl0O0O, nl0O0i})); defparam nill1O.width_data = 7, nill1O.width_sel = 7; oper_selector nillil ( .data({wire_nl01li_dataout, wire_nl11OO_dataout, 1'b0, wire_niO10l_dataout, wire_niO11l_dataout, wire_nlO_dataout}), .o(wire_nillil_o), .sel({nli11O, nli11i, ni011l, nl0OOi, nl0O0O, nl0O0l})); defparam nillil.width_data = 6, nillil.width_sel = 6; oper_selector nillli ( .data({wire_nl01ll_dataout, wire_nl101i_dataout, 1'b0, wire_niO10O_dataout, wire_niO11O_dataout}), .o(wire_nillli_o), .sel({nli11O, nli11i, ni011O, nl0OOi, nl0O0O})); defparam nillli.width_data = 5, nillli.width_sel = 5; oper_selector nilllO ( .data({wire_nl01lO_dataout, wire_nl101l_dataout, 1'b0, wire_niO1ii_dataout, wire_niO11l_dataout, wire_nlO_dataout}), .o(wire_nilllO_o), .sel({nli11O, nli11i, ni010i, nl0OOi, nl0Oil, nl0Oii})); defparam nilllO.width_data = 6, nilllO.width_sel = 6; oper_selector nillOl ( .data({wire_nl01Oi_dataout, wire_nl101O_dataout, 1'b0, wire_niO1il_dataout, wire_niO11O_dataout}), .o(wire_nillOl_o), .sel({nli11O, nli11i, ni010l, nl0OOi, nl0Oil})); defparam nillOl.width_data = 5, nillOl.width_sel = 5; oper_selector nilO0l ( .data({wire_nl001i_dataout, wire_nl100O_dataout, 1'b0, wire_niO1ll_dataout, wire_niO11l_dataout, wire_nlO_dataout}), .o(wire_nilO0l_o), .sel({nli11O, nli11i, ni01il, nl0OOi, nl0OlO, nl0Oll})); defparam nilO0l.width_data = 6, nilO0l.width_sel = 6; oper_selector nilO1i ( .data({wire_nl01Ol_dataout, wire_nl100i_dataout, 1'b0, wire_niO1iO_dataout, wire_niO11l_dataout, wire_nlO_dataout}), .o(wire_nilO1i_o), .sel({nli11O, nli11i, ni010O, nl0OOi, nl0Oli, nl0OiO})); defparam nilO1i.width_data = 6, nilO1i.width_sel = 6; oper_selector nilO1O ( .data({wire_nl01OO_dataout, wire_nl100l_dataout, 1'b0, wire_niO1li_dataout, wire_niO11O_dataout}), .o(wire_nilO1O_o), .sel({nli11O, nli11i, ni01ii, nl0OOi, nl0Oli})); defparam nilO1O.width_data = 5, nilO1O.width_sel = 5; oper_selector nilOii ( .data({wire_nl001l_dataout, wire_nl10ii_dataout, 1'b0, wire_niO1lO_dataout, wire_niO11O_dataout}), .o(wire_nilOii_o), .sel({nli11O, nli11i, ni01iO, nl0OOi, nl0OlO})); defparam nilOii.width_data = 5, nilOii.width_sel = 5; oper_selector nilOiO ( .data({wire_nl001O_dataout, wire_nl10il_dataout, 1'b0, wire_niO1Oi_dataout}), .o(wire_nilOiO_o), .sel({nli11O, nli11i, ni01ll, nl0OOi})); defparam nilOiO.width_data = 4, nilOiO.width_sel = 4; oper_selector nilOli ( .data({wire_nl000i_dataout, wire_nl10iO_dataout, wire_nlO_dataout, wire_niO1Ol_dataout, 1'b0}), .o(wire_nilOli_o), .sel({nli11O, nli11i, nl0OOl, nl0OOi, ni01li})); defparam nilOli.width_data = 5, nilOli.width_sel = 5; oper_selector nilOlO ( .data({wire_nl000l_dataout, wire_nl10li_dataout, 1'b0, wire_niO1OO_dataout}), .o(wire_nilOlO_o), .sel({nli11O, nli11i, ni01ll, nl0OOi})); defparam nilOlO.width_data = 4, nilOlO.width_sel = 4; oper_selector nilOOl ( .data({wire_nl000O_dataout, wire_nl10ll_dataout, 1'b0, wire_niO01i_dataout, wire_niO11l_dataout, wire_nlO_dataout}), .o(wire_nilOOl_o), .sel({nli11O, nli11i, ni01lO, nl0OOi, nl0O0i, nl0O1O})); defparam nilOOl.width_data = 6, nilOOl.width_sel = 6; oper_selector niO11i ( .data({wire_nl00ii_dataout, wire_nl10lO_dataout, (~ wire_nlO_dataout), wire_niO01l_dataout, {10{(~ wire_nlO_dataout)}}}), .o(wire_niO11i_o), .sel({nli11O, nli11i, nl0OOl, nl0OOi, nl0OlO, nl0Oll, nl0Oli, nl0OiO, nl0Oil, nl0Oii, nl0O0O, nl0O0l, nl0O0i, nl0O1O})); defparam niO11i.width_data = 14, niO11i.width_sel = 14; oper_selector nlilOi ( .data({1'b0, wire_nlOO1i_dataout, wire_nlllll_dataout, {2{(~ ni0l0l)}}}), .o(wire_nlilOi_o), .sel({ni000i, n1l0l, n1iii, n1i0O, n1i0l})); defparam nlilOi.width_data = 5, nlilOi.width_sel = 5; oper_selector nliO0l ( .data({1'b0, wire_nlllli_dataout, (~ ni0l0l)}), .o(wire_nliO0l_o), .sel({ni00ii, n1iii, n1i0O})); defparam nliO0l.width_data = 3, nliO0l.width_sel = 3; oper_selector nliO1i ( .data({1'b0, niiOOi}), .o(wire_nliO1i_o), .sel({ni000l, (~ ni000l)})); defparam nliO1i.width_data = 2, nliO1i.width_sel = 2; oper_selector nliO1O ( .data({1'b0, ni0l0l, (~ ni0l0l)}), .o(wire_nliO1O_o), .sel({ni000O, n1i0O, n1i0l})); defparam nliO1O.width_data = 3, nliO1O.width_sel = 3; oper_selector nliOii ( .data({1'b0, niiOOi, 1'b1, wire_nlllll_dataout}), .o(wire_nliOii_o), .sel({ni00il, n1ilO, (((n1ill | n1ili) | n1iiO) | n1iil), n1iii})); defparam nliOii.width_data = 4, nliOii.width_sel = 4; oper_selector nliOli ( .data({1'b0, wire_nlO1ii_dataout, wire_nllO0l_dataout}), .o(wire_nliOli_o), .sel({ni00iO, n1l1i, n1iOO})); defparam nliOli.width_data = 3, nliOli.width_sel = 3; oper_selector nliOlO ( .data({1'b0, wire_nlO1il_dataout, wire_nllO0O_dataout}), .o(wire_nliOlO_o), .sel({ni00iO, n1l1i, n1iOO})); defparam nliOlO.width_data = 3, nliOlO.width_sel = 3; oper_selector nliOOi ( .data({1'b0, wire_nlO1iO_dataout, wire_nllOii_dataout}), .o(wire_nliOOi_o), .sel({ni00iO, n1l1i, n1iOO})); defparam nliOOi.width_data = 3, nliOOi.width_sel = 3; oper_selector nliOOl ( .data({1'b0, wire_nlO1li_dataout, wire_nllOil_dataout}), .o(wire_nliOOl_o), .sel({ni00iO, n1l1i, n1iOO})); defparam nliOOl.width_data = 3, nliOOl.width_sel = 3; oper_selector nll00O ( .data({1'b0, 1'b1, (~ niiOOi)}), .o(wire_nll00O_o), .sel({ni0i0l, ni0i0i, n1iOi})); defparam nll00O.width_data = 3, nll00O.width_sel = 3; oper_selector nll01i ( .data({ni0Oii, 1'b0, wire_nlllOi_dataout, wire_nllliO_dataout}), .o(wire_nll01i_o), .sel({n1liO, ni0i1i, n1iii, n1i0l})); defparam nll01i.width_data = 4, nll01i.width_sel = 4; oper_selector nll01O ( .data({1'b0, 1'b1, (~ niiOOi)}), .o(wire_nll01O_o), .sel({ni0i1O, ni0i1l, n1iOi})); defparam nll01O.width_data = 3, nll01O.width_sel = 3; oper_selector nll0iO ( .data({1'b0, 1'b1, niiOOi}), .o(wire_nll0iO_o), .sel({ni0iii, ni0i0O, n1iOi})); defparam nll0iO.width_data = 3, nll0iO.width_sel = 3; oper_selector nll0lO ( .data({1'b0, 1'b1, (~ niiOOi)}), .o(wire_nll0lO_o), .sel({ni0iiO, ni0iil, n1iOi})); defparam nll0lO.width_data = 3, nll0lO.width_sel = 3; oper_selector nll0OO ( .data({1'b0, 1'b1, niiOOi}), .o(wire_nll0OO_o), .sel({(((n1liO | n1l1O) | n1iOO) | n1iil), ni0ili, n1iOi})); defparam nll0OO.width_data = 3, nll0OO.width_sel = 3; oper_selector nll10i ( .data({1'b0, wire_nlO1lO_dataout, wire_nllOiO_dataout, wire_nllO0i_dataout}), .o(wire_nll10i_o), .sel({ni00ll, n1l1i, n1iOO, n1iOl})); defparam nll10i.width_data = 4, nll10i.width_sel = 4; oper_selector nll10O ( .data({1'b0, wire_nlOiii_dataout, wire_nlO1Oi_dataout, (~ niiOOi)}), .o(wire_nll10O_o), .sel({ni00lO, n1l1l, n1l1i, n1iOO})); defparam nll10O.width_data = 4, nll10O.width_sel = 4; oper_selector nll11l ( .data({1'b0, 1'b1, wire_nllO1O_dataout}), .o(wire_nll11l_o), .sel({ni00li, n1iOi, n1iOl})); defparam nll11l.width_data = 3, nll11l.width_sel = 3; oper_selector nll1il ( .data({1'b0, wire_nlOlOi_dataout, 1'b1, wire_nlOiil_dataout, wire_nlO1Ol_dataout, wire_nllOli_dataout}), .o(wire_nll1il_o), .sel({ni00Oi, n1l0l, (n1l0i | n1l1O), n1l1l, n1l1i, n1iOO})); defparam nll1il.width_data = 6, nll1il.width_sel = 6; oper_selector nll1ll ( .data({1'b0, niiOOi, wire_nlOlOl_dataout}), .o(wire_nll1ll_o), .sel({ni00Ol, n1lii, n1l0l})); defparam nll1ll.width_data = 3, nll1ll.width_sel = 3; oper_selector nll1Ol ( .data({(~ ni0Oii), (~ niiOOi), wire_nlOO1i_dataout, 1'b0, wire_nllllO_dataout, wire_nlllil_dataout}), .o(wire_nll1Ol_o), .sel({n1liO, n1lii, n1l0l, ni00OO, n1iii, n1i0l})); defparam nll1Ol.width_data = 6, nll1Ol.width_sel = 6; oper_selector nlli0i ( .data({1'b0, 1'b1, niiOOi}), .o(wire_nlli0i_o), .sel({ni0ilO, ni0ill, n1iOi})); defparam nlli0i.width_data = 3, nlli0i.width_sel = 3; oper_selector nlliil ( .data({1'b0, niiOOi}), .o(wire_nlliil_o), .sel({ni0iOi, (~ ni0iOi)})); defparam nlliil.width_data = 2, nlliil.width_sel = 2; oper_selector nllili ( .data({1'b0, niiOOi}), .o(wire_nllili_o), .sel({ni0iOl, (~ ni0iOl)})); defparam nllili.width_data = 2, nllili.width_sel = 2; oper_selector nllilO ( .data({1'b0, niiOOi}), .o(wire_nllilO_o), .sel({ni0l1i, (~ ni0l1i)})); defparam nllilO.width_data = 2, nllilO.width_sel = 2; oper_selector nlliOi ( .data({1'b0, niiOOi}), .o(wire_nlliOi_o), .sel({ni0iOO, (~ ni0iOO)})); defparam nlliOi.width_data = 2, nlliOi.width_sel = 2; oper_selector nlliOO ( .data({1'b0, niiOOi}), .o(wire_nlliOO_o), .sel({ni0l1i, (~ ni0l1i)})); defparam nlliOO.width_data = 2, nlliOO.width_sel = 2; oper_selector nlll0i ( .data({1'b0, niiOOi}), .o(wire_nlll0i_o), .sel({ni0l1O, (~ ni0l1O)})); defparam nlll0i.width_data = 2, nlll0i.width_sel = 2; oper_selector nlll0O ( .data({1'b0, wire_nlOllO_dataout, {9{niiOOi}}}), .o(wire_nlll0O_o), .sel({ni0l0i, n1l0l, n1l1i, n1iOO, n1iOi, n1iOl, n1ilO, n1ill, n1ili, n1iil, n1iii})); defparam nlll0O.width_data = 11, nlll0O.width_sel = 11; oper_selector nlll1l ( .data({1'b0, niiOOi}), .o(wire_nlll1l_o), .sel({ni0l1l, (~ ni0l1l)})); defparam nlll1l.width_data = 2, nlll1l.width_sel = 2; assign bist_ctl_sg = {wire_ni1O_dataout, wire_ni1l_dataout}, bist_data_sg = {wire_ni1i_dataout, wire_n0OO_dataout, wire_n0Ol_dataout, wire_n0Oi_dataout, wire_n0lO_dataout, wire_n0ll_dataout, wire_n0li_dataout, wire_n0iO_dataout, wire_n0il_dataout, wire_n0ii_dataout, wire_n00O_dataout, wire_n00l_dataout, wire_n00i_dataout, wire_n01O_dataout, wire_n01l_dataout, wire_n01i_dataout}, ni000i = (((((((((((((n1liO | n1lii) | n1l0i) | n1l1O) | n1l1l) | n1l1i) | n1iOO) | n1iOl) | n1iOi) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iil), ni000l = ((((((((((((n1liO | n1lii) | n1l0l) | n1l0i) | n1l1O) | n1l1l) | n1l1i) | n1iOO) | n1iOl) | n1iOi) | n1iiO) | n1i0O) | n1i0l), ni000O = (((((((((((((((n1liO | n1lii) | n1l0l) | n1l0i) | n1l1O) | n1l1l) | n1l1i) | n1iOO) | n1iOl) | n1iOi) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iil) | n1iii), ni001i = ((((((((~ nl0iOl) & (~ nl0iOi)) & (~ nl0ilO)) & (~ nl0ill)) & (~ nl0ili)) & nl0iiO) & nl0iil) & nl0iii), ni001O = (nli11i | nl0OOi), ni00ii = (((((((((((((((n1liO | n1lii) | n1l0l) | n1l0i) | n1l1O) | n1l1l) | n1l1i) | n1iOO) | n1iOl) | n1iOi) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iil) | n1i0l), ni00il = (((((((((((n1liO | n1lii) | n1l0l) | n1l0i) | n1l1O) | n1l1l) | n1l1i) | n1iOO) | n1iOl) | n1iOi) | n1i0O) | n1i0l), ni00iO = (((((((((((((((n1liO | n1lii) | n1l0l) | n1l0i) | n1l1O) | n1l1l) | n1iOl) | n1iOi) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iil) | n1iii) | n1i0O) | n1i0l), ni00li = (((((((((((((((n1liO | n1lii) | n1l0l) | n1l0i) | n1l1O) | n1l1l) | n1l1i) | n1iOO) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iil) | n1iii) | n1i0O) | n1i0l), ni00ll = ((((((((((((((n1liO | n1lii) | n1l0l) | n1l0i) | n1l1O) | n1l1l) | n1iOi) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iil) | n1iii) | n1i0O) | n1i0l), ni00lO = ((((((((((((((n1liO | n1lii) | n1l0l) | n1l0i) | n1l1O) | n1iOl) | n1iOi) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iil) | n1iii) | n1i0O) | n1i0l), ni00Oi = (((((((((((n1liO | n1lii) | n1iOl) | n1iOi) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iil) | n1iii) | n1i0O) | n1i0l), ni00Ol = (((((((((((((((n1liO | n1l0i) | n1l1O) | n1l1l) | n1l1i) | n1iOO) | n1iOl) | n1iOi) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iil) | n1iii) | n1i0O) | n1i0l), ni00OO = ((((((((((((n1l0i | n1l1O) | n1l1l) | n1l1i) | n1iOO) | n1iOl) | n1iOi) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iil) | n1i0O), ni010i = ((((((((nl0OOl | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0O0O) | nl0O0l) | nl0O0i) | nl0O1O), ni010l = (((((((((nl0OOl | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oii) | nl0O0O) | nl0O0l) | nl0O0i) | nl0O1O), ni010O = ((((((((nl0OOl | nl0OlO) | nl0Oll) | nl0Oil) | nl0Oii) | nl0O0O) | nl0O0l) | nl0O0i) | nl0O1O), ni011i = (((((((((nl0OOl | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0O) | nl0O0l) | nl0O1O), ni011l = ((((((((nl0OOl | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0i) | nl0O1O), ni011O = (((((((((nl0OOl | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0l) | nl0O0i) | nl0O1O), ni01ii = (((((((((nl0OOl | nl0OlO) | nl0Oll) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0O) | nl0O0l) | nl0O0i) | nl0O1O), ni01il = ((((((((nl0OOl | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0O) | nl0O0l) | nl0O0i) | nl0O1O), ni01iO = (((((((((nl0OOl | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0O) | nl0O0l) | nl0O0i) | nl0O1O), ni01li = (((((((((nl0OlO | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0O) | nl0O0l) | nl0O0i) | nl0O1O), ni01ll = ((((((((((nl0OOl | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0O) | nl0O0l) | nl0O0i) | nl0O1O), ni01lO = ((((((((nl0OOl | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0O) | nl0O0l), ni01Oi = (((((((nl0iOl & nl0iOi) & nl0ilO) & nl0ill) & nl0ili) & nl0iiO) & nl0iil) & nl0iii), ni01Ol = ((((((nl00Ol & nl00Oi) & nl00lO) & nl00ll) & nl00li) & nl00iO) & nl00il), ni01OO = ((((((((~ nl0iOl) & (~ nl0iOi)) & (~ nl0ilO)) & nl0ill) & (~ nl0ili)) & (~ nl0iiO)) & (~ nl0iil)) & (~ nl0iii)), ni0i0i = ((((((n1lii | n1l1O) | n1l1l) | n1iOO) | n1ill) | n1ili) | n1iil), ni0i0l = (((((((((n1liO | n1l0l) | n1l0i) | n1l1i) | n1iOl) | n1ilO) | n1iiO) | n1iii) | n1i0O) | n1i0l), ni0i0O = (((((((((((n1l0l | n1l0i) | n1l1l) | n1l1i) | n1iOl) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iii) | n1i0O) | n1i0l), ni0i1i = ((((((((((((((n1lii | n1l0l) | n1l0i) | n1l1O) | n1l1l) | n1l1i) | n1iOO) | n1iOl) | n1iOi) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iil) | n1i0O), ni0i1l = (((((((((n1lii | n1l0l) | n1l0i) | n1l1O) | n1iOO) | n1iOl) | n1ilO) | n1ill) | n1iiO) | n1iil), ni0i1O = ((((((n1liO | n1l1l) | n1l1i) | n1ili) | n1iii) | n1i0O) | n1i0l), ni0iii = ((((n1liO | n1lii) | n1l1O) | n1iOO) | n1iil), ni0iil = (((((((((((n1lii | n1l1O) | n1l1l) | n1iOO) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iil) | n1iii) | n1i0O) | n1i0l), ni0iiO = ((((n1liO | n1l0l) | n1l0i) | n1l1i) | n1iOl), ni0ili = ((((((((((((n1lii | n1l0l) | n1l0i) | n1l1l) | n1l1i) | n1iOl) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iii) | n1i0O) | n1i0l), ni0ill = (((((((n1lii | n1l0l) | n1l0i) | n1l1l) | n1l1i) | n1iOO) | n1iiO) | n1i0O), ni0ilO = ((((((((n1liO | n1l1O) | n1iOl) | n1ilO) | n1ill) | n1ili) | n1iil) | n1iii) | n1i0l), ni0iOi = (((((((((((n1liO | n1l0i) | n1l1O) | n1l1l) | n1iOO) | n1ill) | n1ili) | n1iiO) | n1iil) | n1iii) | n1i0O) | n1i0l), ni0iOl = (((((((((((((n1liO | n1lii) | n1l0l) | n1l0i) | n1iOO) | n1iOl) | n1ilO) | n1ill) | n1ili) | n1iiO) | n1iil) | n1iii) | n1i0O) | n1i0l), ni0iOO = ((((((((n1liO | n1lii) | n1l0l) | n1l0i) | n1iOO) | n1iOl) | n1iiO) | n1i0O) | n1i0l), ni0l0i = (((((((n1liO | n1lii) | n1l0i) | n1l1O) | n1l1l) | n1iiO) | n1i0O) | n1i0l), ni0l0l = ((nlOOiO & (~ nlOOil)) & nliliO), ni0l0O = ((nlOOiO & nlOOil) & (~ nliliO)), ni0l1i = ((((((n1liO | n1l0i) | n1l1i) | n1iOi) | n1iiO) | n1i0O) | n1i0l), ni0l1l = ((((((n1liO | n1lii) | n1l0l) | n1l0i) | n1iiO) | n1i0O) | n1i0l), ni0l1O = ((((((((((n1liO | n1l0i) | n1iOl) | n1iOi) | n1ill) | n1ili) | n1iiO) | n1iil) | n1iii) | n1i0O) | n1i0l), ni0lii = (((~ nlOOiO) & nlOOil) & (~ nliliO)), ni0lil = ((((((~ nlOOOO) & nlOOOl) & (~ nlOOOi)) & (~ nlOOlO)) & nlOOll) & nlOOli), ni0liO = (((((nlOOOO & (~ nlOOOl)) & (~ nlOOOi)) & nlOOlO) & nlOOll) & nlOOli), ni0lli = (((~ n111O) & n111l) & n111i), ni0lll = ((n111O & n111l) & n111i), ni0llO = ((((~ n11ii) & (~ n110O)) & n110l) & (~ n110i)), ni0lOi = ((((~ n11ii) & n110O) & n110l) & n110i), ni0lOl = (((n11ii & n110O) & n110l) & n110i), ni0lOO = (((((~ n11ii) & (~ n110O)) & n110l) & n110i) | (((n11ii & (~ n110O)) & n110l) & n110i)), ni0O0i = (((((((((~ n101i) & n11OO) & (~ n11Ol)) & (~ n11Oi)) & (~ n11lO)) & (~ n11ll)) & (~ n11li)) & n11iO) & n11il), ni0O0l = (((((((((~ n101i) & (~ n11OO)) & n11Ol) & (~ n11Oi)) & (~ n11lO)) & (~ n11ll)) & (~ n11li)) & (~ n11iO)) & (~ n11il)), ni0O0O = (((((((((~ n101i) & n11OO) & (~ n11Ol)) & (~ n11Oi)) & (~ n11lO)) & (~ n11ll)) & (~ n11li)) & n11iO) & (~ n11il)), ni0O1i = ((((((((n101i & (~ n11OO)) & (~ n11Ol)) & (~ n11Oi)) & (~ n11lO)) & (~ n11ll)) & n11li) & n11iO) & n11il), ni0O1l = ((((((((n101i & (~ n11OO)) & (~ n11Ol)) & (~ n11Oi)) & (~ n11lO)) & (~ n11ll)) & n11li) & n11iO) & (~ n11il)), ni0O1O = (((((((((~ n101i) & (~ n11OO)) & n11Ol) & (~ n11Oi)) & (~ n11lO)) & (~ n11ll)) & (~ n11li)) & (~ n11iO)) & n11il), ni0Oii = ((~ rcxpat_chnl_sel[0]) & (~ rcxpat_chnl_sel[1])), ni0Oil = (((~ nlOOiO) & (~ nlOOil)) & nliliO), ni0OiO = (ni0Oll | ni0Oli), ni0Oli = ((~ rcxpat_chnl_sel[0]) & rcxpat_chnl_sel[1]), ni0Oll = (rcxpat_chnl_sel[0] & (~ rcxpat_chnl_sel[1])), ni0OlO = ((((n1lii | n1iiO) | n1iii) | n1i0O) | n1i0l), ni0OOi = ((((((n1liO | n1l0l) | n1l0i) | n1l1O) | n1ill) | n1ili) | n1i0l), ni0OOl = ((((((n1liO | n1l0l) | n1l1O) | n1l1l) | n1ili) | n1i0O) | n1i0l), ni0OOO = (((((((((((((((((((nlili | nliil) | nli0l) | nli0i) | nli1O) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0Oi) | nl0lO) | nl0ll) | nl0li) | nl0iO) | nl0il) | nl0ii) | nl00O) | nl00l) | nl00i) | nl01O), ni1lll = ((((((nli11O | nl0OOi) | nl0Oll) | nl0OiO) | nl0Oii) | nl0O0l) | nl0O1O), ni1llO = (((((((((nli11O | nli11i) | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0O) | nl0O0i), ni1lOi = (((((((((nli11O | nli11i) | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0O) | nl0O1O), ni1lOl = ((((((((((nli11i | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0O) | nl0O0l) | nl0O0i) | nl0O1O), ni1lOO = ((((((((((nli11i | nl0OOl) | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0O) | nl0O0i) | nl0O1O), ni1O0i = ((((((nl0Oli | nl0OiO) | nl0Oii) | nl0O0O) | nl0O0l) | nl0O0i) | nl0O1O), ni1O0l = ((((nli11O | nli11i) | nl0OlO) | nl0Oll) | nl0Oil), ni1O0O = (((((((nli11i | nl0OOl) | nl0Oil) | nl0Oii) | nl0O0O) | nl0O0l) | nl0O0i) | nl0O1O), ni1O1i = (((((((((((nli11i | nl0OOl) | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0O) | nl0O0l) | nl0O0i) | nl0O1O), ni1O1l = (((((((nli11i | nl0OOl) | nl0Oll) | nl0OiO) | nl0O0O) | nl0O0l) | nl0O0i) | nl0O1O), ni1O1O = ((((nli11O | nl0OlO) | nl0Oli) | nl0Oil) | nl0Oii), ni1Oii = ((((nli11O | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO), ni1Oil = (((((((((nli11O | nli11i) | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0l) | nl0O1O), ni1OiO = ((((((((((nli11O | nli11i) | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0l) | nl0O0i) | nl0O1O), ni1Oli = ((((((nli11O | nl0OOl) | nl0Oll) | nl0OiO) | nl0Oii) | nl0O0l) | nl0O1O), ni1Oll = ((((((nli11O | nl0Oll) | nl0OiO) | nl0Oii) | nl0O0O) | nl0O0l) | nl0O1O), ni1OlO = (((((nli11O | nl0Oll) | nl0OiO) | nl0Oii) | nl0O0l) | nl0O1O), ni1OOi = ((((((nli11O | nl0Oll) | nl0OiO) | nl0Oil) | nl0Oii) | nl0O0l) | nl0O1O), ni1OOl = (((((((nli11O | nli11i) | nl0OlO) | nl0Oll) | nl0OiO) | nl0Oii) | nl0O0l) | nl0O1O), ni1OOO = (((((((nli11O | nl0OlO) | nl0Oll) | nl0Oli) | nl0OiO) | nl0Oii) | nl0O0l) | nl0O1O), nii00l = (((((((((((((((nlili | nliil) | nli0O) | nli0l) | nli0i) | nli1O) | nli1l) | nli1i) | nl0Ol) | nl0Oi) | nl0lO) | nl0li) | nl0il) | nl01O) | nl01i) | nl1OO), nii01i = (((((((((((((((((((nlili | nliil) | nli0O) | nli0l) | nli1O) | nli1i) | nl0Ol) | nl0Oi) | nl0lO) | nl0li) | nl0iO) | nl0il) | nl0ii) | nl00O) | nl00l) | nl00i) | nl01O) | nl01l) | nl01i) | nl1OO), nii01l = (((((((((((((nlili | nli0l) | nli1O) | nli1i) | nl0Ol) | nl0lO) | nl0ll) | nl0li) | nl0iO) | nl0il) | nl01O) | nl01i) | nl1OO) | (~ (nii01O42 ^ nii01O41))), nii0ii = (((((((((((((nlili | nli0l) | nli1O) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0lO) | nl0li) | nl0il) | nl01O) | nl01i) | nl1OO) | (~ (nii0il38 ^ nii0il37))), nii0ll = ((((((((((((((((((nlili | nliil) | nli0O) | nli0l) | nli0i) | nli1O) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0Oi) | nl0lO) | nl0li) | nl0iO) | nl0il) | nl01O) | nl01i) | nl1OO) | (~ (nii0lO34 ^ nii0lO33))), nii0Ol = ((((((((((((((((nlili | nli0l) | nli1O) | nli1i) | nl0OO) | nl0Ol) | nl0Oi) | nl0lO) | nl0li) | nl0il) | nl00O) | nl00l) | nl00i) | nl01O) | nl01l) | nl01i) | nl1OO), nii10i = (((((((((((((((((nlili | nliil) | nli0O) | nli0l) | nli0i) | nli1O) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0Oi) | nl0lO) | nl0ll) | nl0li) | nl0iO) | nl0il) | nl01i) | nl1OO), nii10l = (((((((((((((((((((((nlili | nliil) | nli0O) | nli0l) | nli0i) | nli1O) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0Oi) | nl0lO) | nl0ll) | nl0li) | nl0ii) | nl00O) | nl00l) | nl00i) | nl01O) | nl01l) | nl01i) | nl1OO), nii10O = (((((((((((((((((((((nlili | nliil) | nli0O) | nli0l) | nli0i) | nli1O) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0Oi) | nl0lO) | nl0iO) | nl0il) | nl0ii) | nl00O) | nl00l) | nl00i) | nl01O) | nl01l) | nl01i) | nl1OO), nii11i = ((((((((((((((((((nlili | nliil) | nli0O) | nli0l) | nli0i) | nli1O) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0Oi) | nl0lO) | nl0ll) | nl0li) | nl0iO) | nl0il) | nl01O) | nl01i) | nl1OO), nii11l = (((((((((((((((((((((nlili | nliil) | nli0O) | nli0l) | nli0i) | nli1O) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0Oi) | nl0lO) | nl0ll) | nl0li) | nl0iO) | nl0il) | nl0ii) | nl00O) | nl00l) | nl00i) | nl01O) | nl01l), nii11O = (((((((((((((((((((((nlili | nliil) | nli0O) | nli0l) | nli0i) | nli1O) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0Oi) | nl0lO) | nl0ll) | nl0li) | nl0iO) | nl0il) | nl0ii) | nl00O) | nl00l) | nl00i) | nl01O) | nl1OO), nii1ii = (((((((((((((((((((((nlili | nliil) | nli0O) | nli0l) | nli0i) | nli1O) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0ll) | nl0li) | nl0iO) | nl0il) | nl0ii) | nl00O) | nl00l) | nl00i) | nl01O) | nl01l) | nl01i) | nl1OO), nii1il = (((((((((((((((((((((nlili | nliil) | nli0O) | nli0l) | nli0i) | nli1O) | nli1l) | nli1i) | nl0Oi) | nl0lO) | nl0ll) | nl0li) | nl0iO) | nl0il) | nl0ii) | nl00O) | nl00l) | nl00i) | nl01O) | nl01l) | nl01i) | nl1OO), nii1iO = (((((((((((((((((((((nlili | nliil) | nli0O) | nli0l) | nli0i) | nli1O) | nl0OO) | nl0Ol) | nl0Oi) | nl0lO) | nl0ll) | nl0li) | nl0iO) | nl0il) | nl0ii) | nl00O) | nl00l) | nl00i) | nl01O) | nl01l) | nl01i) | nl1OO), nii1li = (((((((((((((((((((((nlili | nliil) | nli0O) | nli0l) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0Oi) | nl0lO) | nl0ll) | nl0li) | nl0iO) | nl0il) | nl0ii) | nl00O) | nl00l) | nl00i) | nl01O) | nl01l) | nl01i) | nl1OO), nii1ll = ((((((((((((((((((nlili | nli0i) | nli1O) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0Oi) | nl0lO) | nl0ll) | nl0li) | nl0ii) | nl00O) | nl00l) | nl00i) | nl01O) | nl01l) | nl01i) | nl1OO), nii1lO = ((((((((((((((((((nli0l | nli0i) | nli1O) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0Oi) | nl0lO) | nl0ll) | nl0li) | nl0iO) | nl0il) | nl0ii) | nl00O) | nl00l) | nl00i) | nl01O) | nl01i), nii1Oi = ((((((((((((((((((((nliil | nli0O) | nli0l) | nli0i) | nli1O) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0Oi) | nl0lO) | nl0ll) | nl0li) | nl0iO) | nl0il) | nl0ii) | nl00O) | nl00l) | nl00i) | nl01O) | nl01i), nii1Ol = (((((((((((((((nlili | nli0l) | nli1O) | nli1i) | nl0Ol) | nl0Oi) | nl0lO) | nl0li) | nl0il) | nl00O) | nl00l) | nl00i) | nl01O) | nl01l) | nl01i) | nl1OO), niii0l = (((((((((((((((nlili | nliil) | nli0l) | nli1O) | nli1l) | nli1i) | nl0Ol) | nl0Oi) | nl0lO) | nl0li) | nl0iO) | nl0il) | nl01O) | nl01i) | nl1OO) | (~ (niii0O22 ^ niii0O21))), niiiil = ((niO0O & (~ niO0l)) & n0lOi), niiiiO = ((niO0O & niO0l) & (~ n0lOi)), niiili = (((~ niO0O) & niO0l) & (~ n0lOi)), niiill = ((((niOll & niOli) & niOiO) & niOil) & (~ niOii)), niiilO = ((~ rcxpat_chnl_sel[0]) & (~ rcxpat_chnl_sel[1])), niiiOi = (((~ niO0O) & (~ niO0l)) & n0lOi), niiiOl = (niil1i | niiiOO), niiiOO = ((~ rcxpat_chnl_sel[0]) & rcxpat_chnl_sel[1]), niil0i = (((((((((nliil | nli0i) | nli1O) | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl0Oi) | nl0ll) | nl0li), niil0l = (((((((((nlili | nliil) | nli1l) | nl0OO) | nl0Oi) | nl0li) | nl0il) | nl0ii) | nl00O) | nl00i), niil0O = (((((((((nlili | nli0O) | nli0l) | nli1O) | nli1l) | nli1i) | nl0Oi) | nl0lO) | nl0iO) | nl00l), niil1i = (rcxpat_chnl_sel[0] & (~ rcxpat_chnl_sel[1])), niil1l = ((((nliil | nl01O) | nl01l) | nl01i) | nl1OO), niil1O = (((((((nlili | nli0i) | nl0lO) | nl0ll) | nl0ii) | nl01l) | nl01i) | nl1OO), niilii = (((((nlili | nli1l) | nli1i) | nl0OO) | nl0Ol) | nl00l), niilil = (((((((((((nlili | nli0O) | nli0l) | nli1O) | nli1i) | nl0Ol) | nl0lO) | nl0ll) | nl0il) | nl00l) | nl00i) | nl1OO), niiliO = (((((((((nlili | nli0i) | nli1l) | nl0Ol) | nl0Oi) | nl0lO) | nl0iO) | nl00l) | nl01l) | nl1OO), niilli = (((((((((nliil | nli0l) | nli0i) | nli1O) | nl0Ol) | nl0Oi) | nl0li) | nl0ii) | nl01O) | nl01l), niilll = 1'b1, niilOl = 1'b0, niiOil = (((~ rbist_sel[0]) & (~ rbist_sel[1])) & (niiO0O8 ^ niiO0O7)), niiOiO = ((rbist_sel[0] & (~ rbist_sel[1])) & (niiO0i10 ^ niiO0i9)), niiOli = (((~ rbist_sel[0]) & rbist_sel[1]) & (niiO1l12 ^ niiO1l11)), niiOOi = ((((rpmadwidth_tx & (~ rpma_doublewidth_tx)) & (nil11i2 ^ nil11i1)) & rdwidth_tx) | ((rpmadwidth_tx & rpma_doublewidth_tx) & (niiOOl4 ^ niiOOl3))); endmodule //stratixiv_hssi_tx_digi_bist_gen //synopsys translate_on //VALID FILE //IP Functional Simulation Model //VERSION_BEGIN 12.0 cbx_mgl 2012:05:31:20:09:47:SJ cbx_simgen 2012:05:31:20:08:35:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 // Copyright (C) 1991-2012 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // You may only use these simulation model output files for simulation // purposes and expressly not for synthesis or any other purposes (in which // event Altera disclaims all warranties of any kind). //synopsys translate_off //synthesis_resources = lut 106 mux21 189 oper_add 1 oper_decoder 1 oper_mux 23 oper_selector 23 `timescale 1 ps / 1 ps module stratixiv_hssi_tx_digi_prbs_gen ( cid_en, prbs_out, rcid_len, rcid_pattern, rpma_doublewidth_tx, rpmadwidth_tx, rprbs_en_tx, rprbs_sel, soft_reset, tx_clk) /* synthesis synthesis_clearbox=1 */; input cid_en; output [19:0] prbs_out; input [7:0] rcid_len; input rcid_pattern; input rpma_doublewidth_tx; input rpmadwidth_tx; input rprbs_en_tx; input [2:0] rprbs_sel; input soft_reset; input tx_clk; reg nll00l33; reg nll00l34; reg nll01i37; reg nll01i38; reg nll01O35; reg nll01O36; reg nll0ii31; reg nll0ii32; reg nll0iO29; reg nll0iO30; reg nll0Ol27; reg nll0Ol28; reg nll1ii45; reg nll1ii46; reg nll1li43; reg nll1li44; reg nll1lO41; reg nll1lO42; reg nll1Ol39; reg nll1Ol40; reg nlli0l23; reg nlli0l24; reg nlli1O25; reg nlli1O26; reg nlliil21; reg nlliil22; reg nlliiO19; reg nlliiO20; reg nllill17; reg nllill18; reg nlliOi15; reg nlliOi16; reg nlll0O11; reg nlll0O12; reg nlll1i13; reg nlll1i14; reg nlllil10; reg nlllil9; reg nllliO7; reg nllliO8; reg nlllli5; reg nlllli6; reg nlllll3; reg nlllll4; reg nlllOl1; reg nlllOl2; reg ni0O; reg nlO0Ol; reg nlO0OO; reg nlOi0i; reg nlOi0l; reg nlOi0O; reg nlOi1i; reg nlOi1l; reg nlOi1O; reg nlOiii; reg nlOiil; reg nlOiiO; reg nlOili; reg nlOill; reg nlOilO; reg nlOiOi; reg nlOiOl; reg nlOiOO; reg nlOl1i; reg nlOl1l; reg nlOl1O; reg ni0l_clk_prev; wire wire_ni0l_PRN; reg n0i; reg n1i; reg n1l; reg n1O; reg nili; reg nill; reg nlll; reg nllO; reg nlOi; reg nlOl; reg nlOl0i; reg nlOl0l; reg nlOl0O; reg nlOlii; reg nlOlil; reg nlOliO; reg nlOlli; reg nlOlll; reg nlOllO; reg nlOlOi; reg nlOlOl; reg nlOlOO; reg nlOO; reg nlOO0i; reg nlOO0l; reg nlOO0O; reg nlOO1i; reg nlOO1l; reg nlOO1O; reg nlOOii; reg nlOOil; reg nlOOiO; reg nlOOli; reg nlOOll; reg nlOOlO; reg nO; wire wire_nl_CLRN; reg nilO; reg nlil; reg nlli; wire wire_nliO_PRN; wire wire_n0l_dataout; wire wire_n0O_dataout; wire wire_n100i_dataout; wire wire_n100l_dataout; wire wire_n100O_dataout; wire wire_n101i_dataout; wire wire_n101l_dataout; wire wire_n101O_dataout; wire wire_n10i_dataout; wire wire_n10ii_dataout; wire wire_n10il_dataout; wire wire_n10iO_dataout; wire wire_n10l_dataout; wire wire_n10li_dataout; wire wire_n10ll_dataout; wire wire_n10lO_dataout; wire wire_n10O_dataout; wire wire_n10Oi_dataout; wire wire_n10Ol_dataout; wire wire_n10OO_dataout; wire wire_n110i_dataout; wire wire_n110l_dataout; wire wire_n110O_dataout; wire wire_n111i_dataout; wire wire_n111l_dataout; wire wire_n111O_dataout; wire wire_n11i_dataout; wire wire_n11ii_dataout; wire wire_n11il_dataout; wire wire_n11iO_dataout; wire wire_n11l_dataout; wire wire_n11li_dataout; wire wire_n11ll_dataout; wire wire_n11lO_dataout; wire wire_n11O_dataout; wire wire_n11Oi_dataout; wire wire_n11Ol_dataout; wire wire_n11OO_dataout; wire wire_n1i0i_dataout; wire wire_n1i0l_dataout; wire wire_n1i0O_dataout; wire wire_n1i1i_dataout; wire wire_n1i1l_dataout; wire wire_n1i1O_dataout; wire wire_n1ii_dataout; wire wire_n1iii_dataout; wire wire_n1iil_dataout; wire wire_n1iiO_dataout; wire wire_n1il_dataout; wire wire_n1ili_dataout; wire wire_n1ill_dataout; wire wire_n1ilO_dataout; wire wire_n1iO_dataout; wire wire_n1iOi_dataout; wire wire_n1iOl_dataout; wire wire_n1iOO_dataout; wire wire_n1l0i_dataout; wire wire_n1l0l_dataout; wire wire_n1l0O_dataout; wire wire_n1l1i_dataout; wire wire_n1l1l_dataout; wire wire_n1l1O_dataout; wire wire_n1li_dataout; wire wire_n1lii_dataout; wire wire_n1lil_dataout; wire wire_n1liO_dataout; wire wire_n1ll_dataout; wire wire_n1lli_dataout; wire wire_n1lll_dataout; wire wire_n1llO_dataout; wire wire_n1lOi_dataout; wire wire_n1lOl_dataout; wire wire_n1lOO_dataout; wire wire_n1O0i_dataout; wire wire_n1O0l_dataout; wire wire_n1O1i_dataout; wire wire_n1O1l_dataout; wire wire_n1O1O_dataout; wire wire_nii_dataout; wire wire_niiil_dataout; wire wire_niiiO_dataout; wire wire_niili_dataout; wire wire_niill_dataout; wire wire_niilO_dataout; wire wire_niiOi_dataout; wire wire_niiOl_dataout; wire wire_niiOO_dataout; wire wire_nil_dataout; wire wire_nil0i_dataout; wire wire_nil0l_dataout; wire wire_nil0O_dataout; wire wire_nil1i_dataout; wire wire_nil1l_dataout; wire wire_nil1O_dataout; wire wire_nilii_dataout; wire wire_nilil_dataout; wire wire_niliO_dataout; wire wire_nilli_dataout; wire wire_nilll_dataout; wire wire_nillO_dataout; wire wire_nilOi_dataout; wire wire_nilOl_dataout; wire wire_nilOO_dataout; wire wire_niO_dataout; wire wire_niO0i_dataout; wire wire_niO0l_dataout; wire wire_niO0O_dataout; wire wire_niO1i_dataout; wire wire_niO1l_dataout; wire wire_niO1O_dataout; wire wire_niOi_dataout; wire wire_niOii_dataout; wire wire_niOil_dataout; wire wire_niOiO_dataout; wire wire_niOl_dataout; wire wire_niOli_dataout; wire wire_niOll_dataout; wire wire_niOlO_dataout; wire wire_niOOi_dataout; wire wire_niOOl_dataout; wire wire_niOOO_dataout; wire wire_nl0i_dataout; wire wire_nl0iO_dataout; wire wire_nl0li_dataout; wire wire_nl0ll_dataout; wire wire_nl0lO_dataout; wire wire_nl0Oi_dataout; wire wire_nl0Ol_dataout; wire wire_nl0OO_dataout; wire wire_nl10i_dataout; wire wire_nl10l_dataout; wire wire_nl10O_dataout; wire wire_nl11i_dataout; wire wire_nl11l_dataout; wire wire_nl11O_dataout; wire wire_nl1ii_dataout; wire wire_nl1il_dataout; wire wire_nl1O_dataout; wire wire_nli_dataout; wire wire_nli0i_dataout; wire wire_nli0l_dataout; wire wire_nli0O_dataout; wire wire_nli1i_dataout; wire wire_nli1l_dataout; wire wire_nli1O_dataout; wire wire_nliii_dataout; wire wire_nliil_dataout; wire wire_nliiO_dataout; wire wire_nlili_dataout; wire wire_nlill_dataout; wire wire_nlilO_dataout; wire wire_nliOi_dataout; wire wire_nliOl_dataout; wire wire_nliOO_dataout; wire wire_nll_dataout; wire wire_nll0i_dataout; wire wire_nll0l_dataout; wire wire_nll0O_dataout; wire wire_nll1i_dataout; wire wire_nll1l_dataout; wire wire_nll1O_dataout; wire wire_nllii_dataout; wire wire_nllil_dataout; wire wire_nlliO_dataout; wire wire_nllli_dataout; wire wire_nllll_dataout; wire wire_nlllO_dataout; wire wire_nllOi_dataout; wire wire_nllOl_dataout; wire wire_nllOO_dataout; wire wire_nlO_dataout; wire wire_nlO0i_dataout; wire wire_nlO0l_dataout; wire wire_nlO0O_dataout; wire wire_nlO1i_dataout; wire wire_nlO1l_dataout; wire wire_nlO1O_dataout; wire wire_nlOii_dataout; wire wire_nlOil_dataout; wire wire_nlOiO_dataout; wire wire_nlOli_dataout; wire wire_nlOll_dataout; wire wire_nlOlO_dataout; wire wire_nlOOi_dataout; wire wire_nlOOl_dataout; wire wire_nlOOO_dataout; wire wire_nlOOOi_dataout; wire wire_nlOOOl_dataout; wire wire_nlOOOO_dataout; wire [8:0] wire_ni_o; wire [31:0] wire_n00ii_o; wire wire_n00il_o; wire wire_n00iO_o; wire wire_n00li_o; wire wire_n00ll_o; wire wire_n00lO_o; wire wire_n00Oi_o; wire wire_n00Ol_o; wire wire_n00OO_o; wire wire_n0i0i_o; wire wire_n0i0l_o; wire wire_n0i0O_o; wire wire_n0i1i_o; wire wire_n0i1l_o; wire wire_n0i1O_o; wire wire_n0iii_o; wire wire_n0iil_o; wire wire_n0iiO_o; wire wire_n0ili_o; wire wire_n0ill_o; wire wire_n0ilO_o; wire wire_n0iOi_o; wire wire_n0iOl_o; wire wire_n0iOO_o; wire wire_n000i_o; wire wire_n001O_o; wire wire_n010i_o; wire wire_n010O_o; wire wire_n011i_o; wire wire_n011l_o; wire wire_n011O_o; wire wire_n01iO_o; wire wire_n01ll_o; wire wire_n01lO_o; wire wire_n01Oi_o; wire wire_n01Ol_o; wire wire_n1O0O_o; wire wire_n1Oii_o; wire wire_n1Oil_o; wire wire_n1OiO_o; wire wire_n1Oli_o; wire wire_n1Oll_o; wire wire_n1OlO_o; wire wire_n1OOi_o; wire wire_niOO_o; wire wire_nl1i_o; wire wire_nl1l_o; wire nliiOO; wire nlil0i; wire nlil0l; wire nlil0O; wire nlil1i; wire nlil1l; wire nlil1O; wire nlilii; wire nlilil; wire nliliO; wire nlilli; wire nlilll; wire nlillO; wire nlilOi; wire nlilOl; wire nlilOO; wire nliO0i; wire nliO0l; wire nliO0O; wire nliO1i; wire nliO1l; wire nliO1O; wire nliOii; wire nliOil; wire nliOiO; wire nliOli; wire nliOll; wire nliOlO; wire nliOOi; wire nliOOl; wire nliOOO; wire nll0ll; wire nll0lO; wire nll0Oi; wire nll10i; wire nll10l; wire nll10O; wire nll11i; wire nll11l; wire nll11O; wire nll1iO; wire nlli0i; wire nlli1i; wire nlli1l; wire nlliii; wire nllili; wire nllilO; wire nlliOl; wire nlliOO; wire nlll0i; wire nlll0l; wire nlll1O; wire nllllO; initial nll00l33 = 0; always @ ( posedge tx_clk) nll00l33 <= nll00l34; event nll00l33_event; initial #1 ->nll00l33_event; always @(nll00l33_event) nll00l33 <= {1{1'b1}}; initial nll00l34 = 0; always @ ( posedge tx_clk) nll00l34 <= nll00l33; initial nll01i37 = 0; always @ ( posedge tx_clk) nll01i37 <= nll01i38; event nll01i37_event; initial #1 ->nll01i37_event; always @(nll01i37_event) nll01i37 <= {1{1'b1}}; initial nll01i38 = 0; always @ ( posedge tx_clk) nll01i38 <= nll01i37; initial nll01O35 = 0; always @ ( posedge tx_clk) nll01O35 <= nll01O36; event nll01O35_event; initial #1 ->nll01O35_event; always @(nll01O35_event) nll01O35 <= {1{1'b1}}; initial nll01O36 = 0; always @ ( posedge tx_clk) nll01O36 <= nll01O35; initial nll0ii31 = 0; always @ ( posedge tx_clk) nll0ii31 <= nll0ii32; event nll0ii31_event; initial #1 ->nll0ii31_event; always @(nll0ii31_event) nll0ii31 <= {1{1'b1}}; initial nll0ii32 = 0; always @ ( posedge tx_clk) nll0ii32 <= nll0ii31; initial nll0iO29 = 0; always @ ( posedge tx_clk) nll0iO29 <= nll0iO30; event nll0iO29_event; initial #1 ->nll0iO29_event; always @(nll0iO29_event) nll0iO29 <= {1{1'b1}}; initial nll0iO30 = 0; always @ ( posedge tx_clk) nll0iO30 <= nll0iO29; initial nll0Ol27 = 0; always @ ( posedge tx_clk) nll0Ol27 <= nll0Ol28; event nll0Ol27_event; initial #1 ->nll0Ol27_event; always @(nll0Ol27_event) nll0Ol27 <= {1{1'b1}}; initial nll0Ol28 = 0; always @ ( posedge tx_clk) nll0Ol28 <= nll0Ol27; initial nll1ii45 = 0; always @ ( posedge tx_clk) nll1ii45 <= nll1ii46; event nll1ii45_event; initial #1 ->nll1ii45_event; always @(nll1ii45_event) nll1ii45 <= {1{1'b1}}; initial nll1ii46 = 0; always @ ( posedge tx_clk) nll1ii46 <= nll1ii45; initial nll1li43 = 0; always @ ( posedge tx_clk) nll1li43 <= nll1li44; event nll1li43_event; initial #1 ->nll1li43_event; always @(nll1li43_event) nll1li43 <= {1{1'b1}}; initial nll1li44 = 0; always @ ( posedge tx_clk) nll1li44 <= nll1li43; initial nll1lO41 = 0; always @ ( posedge tx_clk) nll1lO41 <= nll1lO42; event nll1lO41_event; initial #1 ->nll1lO41_event; always @(nll1lO41_event) nll1lO41 <= {1{1'b1}}; initial nll1lO42 = 0; always @ ( posedge tx_clk) nll1lO42 <= nll1lO41; initial nll1Ol39 = 0; always @ ( posedge tx_clk) nll1Ol39 <= nll1Ol40; event nll1Ol39_event; initial #1 ->nll1Ol39_event; always @(nll1Ol39_event) nll1Ol39 <= {1{1'b1}}; initial nll1Ol40 = 0; always @ ( posedge tx_clk) nll1Ol40 <= nll1Ol39; initial nlli0l23 = 0; always @ ( posedge tx_clk) nlli0l23 <= nlli0l24; event nlli0l23_event; initial #1 ->nlli0l23_event; always @(nlli0l23_event) nlli0l23 <= {1{1'b1}}; initial nlli0l24 = 0; always @ ( posedge tx_clk) nlli0l24 <= nlli0l23; initial nlli1O25 = 0; always @ ( posedge tx_clk) nlli1O25 <= nlli1O26; event nlli1O25_event; initial #1 ->nlli1O25_event; always @(nlli1O25_event) nlli1O25 <= {1{1'b1}}; initial nlli1O26 = 0; always @ ( posedge tx_clk) nlli1O26 <= nlli1O25; initial nlliil21 = 0; always @ ( posedge tx_clk) nlliil21 <= nlliil22; event nlliil21_event; initial #1 ->nlliil21_event; always @(nlliil21_event) nlliil21 <= {1{1'b1}}; initial nlliil22 = 0; always @ ( posedge tx_clk) nlliil22 <= nlliil21; initial nlliiO19 = 0; always @ ( posedge tx_clk) nlliiO19 <= nlliiO20; event nlliiO19_event; initial #1 ->nlliiO19_event; always @(nlliiO19_event) nlliiO19 <= {1{1'b1}}; initial nlliiO20 = 0; always @ ( posedge tx_clk) nlliiO20 <= nlliiO19; initial nllill17 = 0; always @ ( posedge tx_clk) nllill17 <= nllill18; event nllill17_event; initial #1 ->nllill17_event; always @(nllill17_event) nllill17 <= {1{1'b1}}; initial nllill18 = 0; always @ ( posedge tx_clk) nllill18 <= nllill17; initial nlliOi15 = 0; always @ ( posedge tx_clk) nlliOi15 <= nlliOi16; event nlliOi15_event; initial #1 ->nlliOi15_event; always @(nlliOi15_event) nlliOi15 <= {1{1'b1}}; initial nlliOi16 = 0; always @ ( posedge tx_clk) nlliOi16 <= nlliOi15; initial nlll0O11 = 0; always @ ( posedge tx_clk) nlll0O11 <= nlll0O12; event nlll0O11_event; initial #1 ->nlll0O11_event; always @(nlll0O11_event) nlll0O11 <= {1{1'b1}}; initial nlll0O12 = 0; always @ ( posedge tx_clk) nlll0O12 <= nlll0O11; initial nlll1i13 = 0; always @ ( posedge tx_clk) nlll1i13 <= nlll1i14; event nlll1i13_event; initial #1 ->nlll1i13_event; always @(nlll1i13_event) nlll1i13 <= {1{1'b1}}; initial nlll1i14 = 0; always @ ( posedge tx_clk) nlll1i14 <= nlll1i13; initial nlllil10 = 0; always @ ( posedge tx_clk) nlllil10 <= nlllil9; initial nlllil9 = 0; always @ ( posedge tx_clk) nlllil9 <= nlllil10; event nlllil9_event; initial #1 ->nlllil9_event; always @(nlllil9_event) nlllil9 <= {1{1'b1}}; initial nllliO7 = 0; always @ ( posedge tx_clk) nllliO7 <= nllliO8; event nllliO7_event; initial #1 ->nllliO7_event; always @(nllliO7_event) nllliO7 <= {1{1'b1}}; initial nllliO8 = 0; always @ ( posedge tx_clk) nllliO8 <= nllliO7; initial nlllli5 = 0; always @ ( posedge tx_clk) nlllli5 <= nlllli6; event nlllli5_event; initial #1 ->nlllli5_event; always @(nlllli5_event) nlllli5 <= {1{1'b1}}; initial nlllli6 = 0; always @ ( posedge tx_clk) nlllli6 <= nlllli5; initial nlllll3 = 0; always @ ( posedge tx_clk) nlllll3 <= nlllll4; event nlllll3_event; initial #1 ->nlllll3_event; always @(nlllll3_event) nlllll3 <= {1{1'b1}}; initial nlllll4 = 0; always @ ( posedge tx_clk) nlllll4 <= nlllll3; initial nlllOl1 = 0; always @ ( posedge tx_clk) nlllOl1 <= nlllOl2; event nlllOl1_event; initial #1 ->nlllOl1_event; always @(nlllOl1_event) nlllOl1 <= {1{1'b1}}; initial nlllOl2 = 0; always @ ( posedge tx_clk) nlllOl2 <= nlllOl1; initial begin ni0O = 0; nlO0Ol = 0; nlO0OO = 0; nlOi0i = 0; nlOi0l = 0; nlOi0O = 0; nlOi1i = 0; nlOi1l = 0; nlOi1O = 0; nlOiii = 0; nlOiil = 0; nlOiiO = 0; nlOili = 0; nlOill = 0; nlOilO = 0; nlOiOi = 0; nlOiOl = 0; nlOiOO = 0; nlOl1i = 0; nlOl1l = 0; nlOl1O = 0; end always @ (tx_clk or wire_ni0l_PRN or soft_reset) begin if (wire_ni0l_PRN == 1'b0) begin ni0O <= 1; nlO0Ol <= 1; nlO0OO <= 1; nlOi0i <= 1; nlOi0l <= 1; nlOi0O <= 1; nlOi1i <= 1; nlOi1l <= 1; nlOi1O <= 1; nlOiii <= 1; nlOiil <= 1; nlOiiO <= 1; nlOili <= 1; nlOill <= 1; nlOilO <= 1; nlOiOi <= 1; nlOiOl <= 1; nlOiOO <= 1; nlOl1i <= 1; nlOl1l <= 1; nlOl1O <= 1; end else if (soft_reset == 1'b1) begin ni0O <= 0; nlO0Ol <= 0; nlO0OO <= 0; nlOi0i <= 0; nlOi0l <= 0; nlOi0O <= 0; nlOi1i <= 0; nlOi1l <= 0; nlOi1O <= 0; nlOiii <= 0; nlOiil <= 0; nlOiiO <= 0; nlOili <= 0; nlOill <= 0; nlOilO <= 0; nlOiOi <= 0; nlOiOl <= 0; nlOiOO <= 0; nlOl1i <= 0; nlOl1l <= 0; nlOl1O <= 0; end else if (nlliii == 1'b0) if (tx_clk != ni0l_clk_prev && tx_clk == 1'b1) begin ni0O <= wire_n100O_dataout; nlO0Ol <= wire_n10ii_dataout; nlO0OO <= wire_n10il_dataout; nlOi0i <= wire_n10lO_dataout; nlOi0l <= wire_n10Oi_dataout; nlOi0O <= wire_n10Ol_dataout; nlOi1i <= wire_n10iO_dataout; nlOi1l <= wire_n10li_dataout; nlOi1O <= wire_n10ll_dataout; nlOiii <= wire_n10OO_dataout; nlOiil <= wire_n1i1i_dataout; nlOiiO <= wire_n1i1l_dataout; nlOili <= wire_n1i1O_dataout; nlOill <= wire_n1i0i_dataout; nlOilO <= wire_n1i0l_dataout; nlOiOi <= wire_n1i0O_dataout; nlOiOl <= wire_n1iii_dataout; nlOiOO <= wire_n1iil_dataout; nlOl1i <= wire_n1iiO_dataout; nlOl1l <= wire_n1ili_dataout; nlOl1O <= wire_n1ill_dataout; end ni0l_clk_prev <= tx_clk; end assign wire_ni0l_PRN = (nlli1O26 ^ nlli1O25); initial begin n0i = 0; n1i = 0; n1l = 0; n1O = 0; nili = 0; nill = 0; nlll = 0; nllO = 0; nlOi = 0; nlOl = 0; nlOl0i = 0; nlOl0l = 0; nlOl0O = 0; nlOlii = 0; nlOlil = 0; nlOliO = 0; nlOlli = 0; nlOlll = 0; nlOllO = 0; nlOlOi = 0; nlOlOl = 0; nlOlOO = 0; nlOO = 0; nlOO0i = 0; nlOO0l = 0; nlOO0O = 0; nlOO1i = 0; nlOO1l = 0; nlOO1O = 0; nlOOii = 0; nlOOil = 0; nlOOiO = 0; nlOOli = 0; nlOOll = 0; nlOOlO = 0; nO = 0; end always @ ( posedge tx_clk or negedge wire_nl_CLRN) begin if (wire_nl_CLRN == 1'b0) begin n0i <= 0; n1i <= 0; n1l <= 0; n1O <= 0; nili <= 0; nill <= 0; nlll <= 0; nllO <= 0; nlOi <= 0; nlOl <= 0; nlOl0i <= 0; nlOl0l <= 0; nlOl0O <= 0; nlOlii <= 0; nlOlil <= 0; nlOliO <= 0; nlOlli <= 0; nlOlll <= 0; nlOllO <= 0; nlOlOi <= 0; nlOlOl <= 0; nlOlOO <= 0; nlOO <= 0; nlOO0i <= 0; nlOO0l <= 0; nlOO0O <= 0; nlOO1i <= 0; nlOO1l <= 0; nlOO1O <= 0; nlOOii <= 0; nlOOil <= 0; nlOOiO <= 0; nlOOli <= 0; nlOOll <= 0; nlOOlO <= 0; nO <= 0; end else begin n0i <= nO; n1i <= wire_nli_dataout; n1l <= wire_nll_dataout; n1O <= wire_nlO_dataout; nili <= nill; nill <= rprbs_en_tx; nlll <= wire_n0l_dataout; nllO <= wire_n0O_dataout; nlOi <= wire_nii_dataout; nlOl <= wire_nil_dataout; nlOl0i <= wire_nlOOOi_dataout; nlOl0l <= wire_nlOOOl_dataout; nlOl0O <= wire_nlOOOO_dataout; nlOlii <= wire_n111i_dataout; nlOlil <= wire_n111l_dataout; nlOliO <= wire_n111O_dataout; nlOlli <= wire_n110i_dataout; nlOlll <= wire_n110l_dataout; nlOllO <= wire_n110O_dataout; nlOlOi <= wire_n11ii_dataout; nlOlOl <= wire_n11il_dataout; nlOlOO <= wire_n11iO_dataout; nlOO <= wire_niO_dataout; nlOO0i <= wire_n11Oi_dataout; nlOO0l <= wire_n11Ol_dataout; nlOO0O <= wire_n11OO_dataout; nlOO1i <= wire_n11li_dataout; nlOO1l <= wire_n11ll_dataout; nlOO1O <= wire_n11lO_dataout; nlOOii <= wire_n101i_dataout; nlOOil <= wire_n101l_dataout; nlOOiO <= wire_n101O_dataout; nlOOli <= wire_n100i_dataout; nlOOll <= wire_n100l_dataout; nlOOlO <= nili; nO <= cid_en; end end assign wire_nl_CLRN = ((nlllOl2 ^ nlllOl1) & (~ soft_reset)); initial begin nilO = 0; nlil = 0; end always @ ( posedge tx_clk or posedge soft_reset) begin if (soft_reset == 1'b1) begin nilO <= 0; nlil <= 0; end else if (nlll0l == 1'b1) begin nilO <= wire_niOO_o; nlil <= wire_nl1i_o; end end initial begin nlli = 0; end always @ ( posedge tx_clk or negedge wire_nliO_PRN) begin if (wire_nliO_PRN == 1'b0) begin nlli <= 1; end else if (nlll0l == 1'b1) begin nlli <= wire_nl1l_o; end end assign wire_nliO_PRN = ((nlll0O12 ^ nlll0O11) & (~ soft_reset)); event nlli_event; initial #1 ->nlli_event; always @(nlli_event) nlli <= 1; assign wire_n0l_dataout = (wire_niOi_dataout === 1'b1) ? wire_ni_o[1] : rcid_len[0]; assign wire_n0O_dataout = (wire_niOi_dataout === 1'b1) ? wire_ni_o[2] : rcid_len[1]; assign wire_n100i_dataout = (nlliii === 1'b1) ? (~ nlli0i) : wire_n1O1O_dataout; assign wire_n100l_dataout = (nlliii === 1'b1) ? (~ nlli0i) : wire_n1O0i_dataout; assign wire_n100O_dataout = (nlOOlO === 1'b1) ? wire_n1O0l_dataout : ni0O; assign wire_n101i_dataout = (nlliii === 1'b1) ? (~ (wire_n00ii_o[16] | wire_n00ii_o[2])) : wire_n1lOO_dataout; assign wire_n101l_dataout = (nlliii === 1'b1) ? (~ nlli0i) : wire_n1O1i_dataout; assign wire_n101O_dataout = (nlliii === 1'b1) ? (~ nlli0i) : wire_n1O1l_dataout; and(wire_n10i_dataout, nlOO0i, nlli1l); assign wire_n10ii_dataout = (nlOOlO === 1'b1) ? wire_n1O0O_o : nlO0Ol; assign wire_n10il_dataout = (nlOOlO === 1'b1) ? wire_n1Oii_o : nlO0OO; assign wire_n10iO_dataout = (nlOOlO === 1'b1) ? wire_n1Oil_o : nlOi1i; and(wire_n10l_dataout, nlOO0l, nlli1l); assign wire_n10li_dataout = (nlOOlO === 1'b1) ? wire_n1OiO_o : nlOi1l; assign wire_n10ll_dataout = (nlOOlO === 1'b1) ? wire_n1Oli_o : nlOi1O; assign wire_n10lO_dataout = (nlOOlO === 1'b1) ? wire_n1Oll_o : nlOi0i; and(wire_n10O_dataout, nlOO0O, nlli1l); assign wire_n10Oi_dataout = (nlOOlO === 1'b1) ? wire_n1OlO_o : nlOi0l; assign wire_n10Ol_dataout = (nlOOlO === 1'b1) ? wire_n1OOi_o : nlOi0O; assign wire_n10OO_dataout = (nlOOlO === 1'b1) ? wire_n011i_o : nlOiii; or(wire_n110i_dataout, wire_n1l1O_dataout, nlliii); assign wire_n110l_dataout = (nlliii === 1'b1) ? (~ nlli0i) : wire_n1l0i_dataout; assign wire_n110O_dataout = (nlliii === 1'b1) ? (~ nlli0i) : wire_n1l0l_dataout; assign wire_n111i_dataout = (nlliii === 1'b1) ? (~ nlli0i) : wire_n1iOO_dataout; assign wire_n111l_dataout = (nlliii === 1'b1) ? (~ nlli0i) : wire_n1l1i_dataout; assign wire_n111O_dataout = (nlliii === 1'b1) ? (~ nlli0i) : wire_n1l1l_dataout; and(wire_n11i_dataout, nlOO1i, nlli1l); assign wire_n11ii_dataout = (nlliii === 1'b1) ? (~ nlli0i) : wire_n1l0O_dataout; assign wire_n11il_dataout = (nlliii === 1'b1) ? (~ nlli0i) : wire_n1lii_dataout; assign wire_n11iO_dataout = (nlliii === 1'b1) ? (~ nlli0i) : wire_n1lil_dataout; and(wire_n11l_dataout, nlOO1l, nlli1l); assign wire_n11li_dataout = (nlliii === 1'b1) ? (~ wire_n00ii_o[2]) : wire_n1liO_dataout; assign wire_n11ll_dataout = (nlliii === 1'b1) ? (~ wire_n00ii_o[2]) : wire_n1lli_dataout; assign wire_n11lO_dataout = (nlliii === 1'b1) ? (~ nlli0i) : wire_n1lll_dataout; and(wire_n11O_dataout, nlOO1O, nlli1l); assign wire_n11Oi_dataout = (nlliii === 1'b1) ? (~ nlli0i) : wire_n1llO_dataout; assign wire_n11Ol_dataout = (nlliii === 1'b1) ? (~ nlli0i) : wire_n1lOi_dataout; assign wire_n11OO_dataout = (nlliii === 1'b1) ? (~ nlli0i) : wire_n1lOl_dataout; assign wire_n1i0i_dataout = (nlOOlO === 1'b1) ? wire_n010O_o : nlOill; assign wire_n1i0l_dataout = (nlOOlO === 1'b1) ? wire_n01iO_o : nlOilO; assign wire_n1i0O_dataout = (nlOOlO === 1'b1) ? wire_n01ll_o : nlOiOi; assign wire_n1i1i_dataout = (nlOOlO === 1'b1) ? wire_n011l_o : nlOiil; assign wire_n1i1l_dataout = (nlOOlO === 1'b1) ? wire_n011O_o : nlOiiO; assign wire_n1i1O_dataout = (nlOOlO === 1'b1) ? wire_n010i_o : nlOili; and(wire_n1ii_dataout, nlOOii, nlli1l); assign wire_n1iii_dataout = (nlOOlO === 1'b1) ? wire_n01lO_o : nlOiOl; assign wire_n1iil_dataout = (nlOOlO === 1'b1) ? wire_n01Oi_o : nlOiOO; assign wire_n1iiO_dataout = (nlOOlO === 1'b1) ? wire_n01Ol_o : nlOl1i; and(wire_n1il_dataout, nlOOil, nlli1l); assign wire_n1ili_dataout = (nlOOlO === 1'b1) ? wire_n001O_o : nlOl1l; assign wire_n1ill_dataout = (nlOOlO === 1'b1) ? wire_n000i_o : nlOl1O; assign wire_n1ilO_dataout = (nlOOlO === 1'b1) ? wire_n00il_o : nlOl0i; and(wire_n1iO_dataout, nlOOiO, nlli1l); assign wire_n1iOi_dataout = (nlOOlO === 1'b1) ? wire_n00iO_o : nlOl0l; assign wire_n1iOl_dataout = (nlOOlO === 1'b1) ? wire_n00li_o : nlOl0O; assign wire_n1iOO_dataout = (nlOOlO === 1'b1) ? wire_n00ll_o : nlOlii; assign wire_n1l0i_dataout = (nlOOlO === 1'b1) ? wire_n00OO_o : nlOlll; assign wire_n1l0l_dataout = (nlOOlO === 1'b1) ? wire_n0i1i_o : nlOllO; assign wire_n1l0O_dataout = (nlOOlO === 1'b1) ? wire_n0i1l_o : nlOlOi; assign wire_n1l1i_dataout = (nlOOlO === 1'b1) ? wire_n00lO_o : nlOlil; assign wire_n1l1l_dataout = (nlOOlO === 1'b1) ? wire_n00Oi_o : nlOliO; assign wire_n1l1O_dataout = (nlOOlO === 1'b1) ? wire_n00Ol_o : nlOlli; and(wire_n1li_dataout, nlOOli, nlli1l); assign wire_n1lii_dataout = (nlOOlO === 1'b1) ? wire_n0i1O_o : nlOlOl; assign wire_n1lil_dataout = (nlOOlO === 1'b1) ? wire_n0i0i_o : nlOlOO; assign wire_n1liO_dataout = (nlOOlO === 1'b1) ? wire_n0i0l_o : nlOO1i; and(wire_n1ll_dataout, nlOOll, nlli1l); assign wire_n1lli_dataout = (nlOOlO === 1'b1) ? wire_n0i0O_o : nlOO1l; assign wire_n1lll_dataout = (nlOOlO === 1'b1) ? wire_n0iii_o : nlOO1O; assign wire_n1llO_dataout = (nlOOlO === 1'b1) ? wire_n0iil_o : nlOO0i; assign wire_n1lOi_dataout = (nlOOlO === 1'b1) ? wire_n0iiO_o : nlOO0l; assign wire_n1lOl_dataout = (nlOOlO === 1'b1) ? wire_n0ili_o : nlOO0O; assign wire_n1lOO_dataout = (nlOOlO === 1'b1) ? wire_n0ill_o : nlOOii; assign wire_n1O0i_dataout = (nlOOlO === 1'b1) ? wire_n0iOO_o : nlOOll; assign wire_n1O0l_dataout = (wire_n00ii_o[11] === 1'b1) ? (~ ni0O) : ni0O; assign wire_n1O1i_dataout = (nlOOlO === 1'b1) ? wire_n0ilO_o : nlOOil; assign wire_n1O1l_dataout = (nlOOlO === 1'b1) ? wire_n0iOi_o : nlOOiO; assign wire_n1O1O_dataout = (nlOOlO === 1'b1) ? wire_n0iOl_o : nlOOli; assign wire_nii_dataout = (wire_niOi_dataout === 1'b1) ? wire_ni_o[3] : rcid_len[2]; or(wire_niiil_dataout, wire_niO1i_dataout, (~ ni0O)); or(wire_niiiO_dataout, wire_niO1l_dataout, (~ ni0O)); or(wire_niili_dataout, wire_niO1O_dataout, (~ ni0O)); or(wire_niill_dataout, wire_niO0i_dataout, (~ ni0O)); or(wire_niilO_dataout, wire_niO0l_dataout, (~ ni0O)); and(wire_niiOi_dataout, wire_niO0O_dataout, ~((~ ni0O))); or(wire_niiOl_dataout, wire_niOii_dataout, (~ ni0O)); and(wire_niiOO_dataout, wire_niOil_dataout, ~((~ ni0O))); assign wire_nil_dataout = (wire_niOi_dataout === 1'b1) ? wire_ni_o[4] : rcid_len[3]; and(wire_nil0i_dataout, wire_niOlO_dataout, ~((~ ni0O))); and(wire_nil0l_dataout, wire_niOOi_dataout, ~((~ ni0O))); and(wire_nil0O_dataout, wire_niOOl_dataout, ~((~ ni0O))); or(wire_nil1i_dataout, wire_niOiO_dataout, (~ ni0O)); or(wire_nil1l_dataout, wire_niOli_dataout, (~ ni0O)); and(wire_nil1O_dataout, wire_niOll_dataout, ~((~ ni0O))); and(wire_nilii_dataout, wire_niOOO_dataout, ~((~ ni0O))); and(wire_nilil_dataout, wire_nl11i_dataout, ~((~ ni0O))); and(wire_niliO_dataout, wire_nl11l_dataout, ~((~ ni0O))); and(wire_nilli_dataout, wire_nl11O_dataout, ~((~ ni0O))); and(wire_nilll_dataout, wire_nl10i_dataout, ~((~ ni0O))); and(wire_nillO_dataout, wire_nl10l_dataout, ~((~ ni0O))); and(wire_nilOi_dataout, wire_nl10O_dataout, ~((~ ni0O))); and(wire_nilOl_dataout, wire_nl1ii_dataout, ~((~ ni0O))); and(wire_nilOO_dataout, wire_nl1il_dataout, ~((~ ni0O))); assign wire_niO_dataout = (wire_niOi_dataout === 1'b1) ? wire_ni_o[5] : rcid_len[4]; and(wire_niO0i_dataout, nlOlii, ~(ni0O)); and(wire_niO0l_dataout, nlOlil, ~(ni0O)); or(wire_niO0O_dataout, nlOliO, ni0O); and(wire_niO1i_dataout, nlOl0i, ~(ni0O)); and(wire_niO1l_dataout, nlOl0l, ~(ni0O)); and(wire_niO1O_dataout, nlOl0O, ~(ni0O)); and(wire_niOi_dataout, nlil, nlll0l); and(wire_niOii_dataout, nlOlli, ~(ni0O)); or(wire_niOil_dataout, nlOlll, ni0O); and(wire_niOiO_dataout, nlOllO, ~(ni0O)); and(wire_niOl_dataout, nlli, nlll0l); and(wire_niOli_dataout, nlOlOi, ~(ni0O)); and(wire_niOll_dataout, nlOlOl, ~(ni0O)); and(wire_niOlO_dataout, nlOlOO, ~(ni0O)); and(wire_niOOi_dataout, nlOO1i, ~(ni0O)); and(wire_niOOl_dataout, nlOO1l, ~(ni0O)); and(wire_niOOO_dataout, nlOO1O, ~(ni0O)); and(wire_nl0i_dataout, nlliOl, ~(nlliOO)); and(wire_nl0iO_dataout, wire_nliOl_dataout, ~(wire_niOl_dataout)); or(wire_nl0li_dataout, wire_nliOO_dataout, wire_niOl_dataout); and(wire_nl0ll_dataout, wire_nll1i_dataout, ~(wire_niOl_dataout)); or(wire_nl0lO_dataout, wire_nll1l_dataout, wire_niOl_dataout); or(wire_nl0Oi_dataout, wire_nll1O_dataout, wire_niOl_dataout); and(wire_nl0Ol_dataout, wire_nll0i_dataout, ~(wire_niOl_dataout)); or(wire_nl0OO_dataout, wire_nll0l_dataout, wire_niOl_dataout); and(wire_nl10i_dataout, nlOOii, ~(ni0O)); and(wire_nl10l_dataout, nlOOil, ~(ni0O)); and(wire_nl10O_dataout, nlOOiO, ~(ni0O)); and(wire_nl11i_dataout, nlOO0i, ~(ni0O)); and(wire_nl11l_dataout, nlOO0l, ~(ni0O)); and(wire_nl11O_dataout, nlOO0O, ~(ni0O)); and(wire_nl1ii_dataout, nlOOli, ~(ni0O)); and(wire_nl1il_dataout, nlOOll, ~(ni0O)); and(wire_nl1O_dataout, (~ nlliOl), ~(nlliOO)); assign wire_nli_dataout = (wire_niOi_dataout === 1'b1) ? wire_ni_o[6] : rcid_len[5]; and(wire_nli0i_dataout, wire_nlliO_dataout, ~(wire_niOl_dataout)); and(wire_nli0l_dataout, wire_nllli_dataout, ~(wire_niOl_dataout)); and(wire_nli0O_dataout, wire_nllll_dataout, ~(wire_niOl_dataout)); and(wire_nli1i_dataout, wire_nll0O_dataout, ~(wire_niOl_dataout)); and(wire_nli1l_dataout, wire_nllii_dataout, ~(wire_niOl_dataout)); and(wire_nli1O_dataout, wire_nllil_dataout, ~(wire_niOl_dataout)); and(wire_nliii_dataout, wire_nlllO_dataout, ~(wire_niOl_dataout)); and(wire_nliil_dataout, wire_nllOi_dataout, ~(wire_niOl_dataout)); and(wire_nliiO_dataout, wire_nllOl_dataout, ~(wire_niOl_dataout)); and(wire_nlili_dataout, wire_nllOO_dataout, ~(wire_niOl_dataout)); and(wire_nlill_dataout, wire_nlO1i_dataout, ~(wire_niOl_dataout)); and(wire_nlilO_dataout, wire_nlO1l_dataout, ~(wire_niOl_dataout)); and(wire_nliOi_dataout, wire_nlO1O_dataout, ~(wire_niOl_dataout)); assign wire_nliOl_dataout = (wire_niOi_dataout === 1'b1) ? rcid_pattern : nlOl0i; assign wire_nliOO_dataout = (wire_niOi_dataout === 1'b1) ? rcid_pattern : nlOl0l; assign wire_nll_dataout = (wire_niOi_dataout === 1'b1) ? wire_ni_o[7] : rcid_len[6]; assign wire_nll0i_dataout = (wire_niOi_dataout === 1'b1) ? rcid_pattern : nlOliO; assign wire_nll0l_dataout = (wire_niOi_dataout === 1'b1) ? rcid_pattern : nlOlli; assign wire_nll0O_dataout = (wire_niOi_dataout === 1'b1) ? rcid_pattern : nlOlll; assign wire_nll1i_dataout = (wire_niOi_dataout === 1'b1) ? rcid_pattern : nlOl0O; assign wire_nll1l_dataout = (wire_niOi_dataout === 1'b1) ? rcid_pattern : nlOlii; assign wire_nll1O_dataout = (wire_niOi_dataout === 1'b1) ? rcid_pattern : nlOlil; and(wire_nllii_dataout, nlOllO, ~(wire_niOi_dataout)); and(wire_nllil_dataout, nlOlOi, ~(wire_niOi_dataout)); and(wire_nlliO_dataout, nlOlOl, ~(wire_niOi_dataout)); and(wire_nllli_dataout, nlOlOO, ~(wire_niOi_dataout)); and(wire_nllll_dataout, nlOO1i, ~(wire_niOi_dataout)); and(wire_nlllO_dataout, nlOO1l, ~(wire_niOi_dataout)); and(wire_nllOi_dataout, nlOO1O, ~(wire_niOi_dataout)); and(wire_nllOl_dataout, nlOO0i, ~(wire_niOi_dataout)); and(wire_nllOO_dataout, nlOO0l, ~(wire_niOi_dataout)); assign wire_nlO_dataout = (wire_niOi_dataout === 1'b1) ? wire_ni_o[8] : rcid_len[7]; assign wire_nlO0i_dataout = (nlli1l === 1'b1) ? nlOl0i : ((nll0Oi ^ nlOl0l) ^ nlOl0i); assign wire_nlO0l_dataout = (nlli1l === 1'b1) ? nlOl0l : ((nlli1i ^ nlOl0O) ^ nlOl0l); assign wire_nlO0O_dataout = (nlli1l === 1'b1) ? nlOl0O : ((((((((nlli1i ^ nlOliO) ^ (~ (nll01i38 ^ nll01i37))) ^ nlOlii) ^ (~ (nll1Ol40 ^ nll1Ol39))) ^ nlOl0O) ^ nlOl0l) ^ nlOl0i) ^ (~ (nll1lO42 ^ nll1lO41))); and(wire_nlO1i_dataout, nlOO0O, ~(wire_niOi_dataout)); and(wire_nlO1l_dataout, nlOOii, ~(wire_niOi_dataout)); and(wire_nlO1O_dataout, nlOOil, ~(wire_niOi_dataout)); assign wire_nlOii_dataout = (nlli1l === 1'b1) ? nlOlii : (((((((nlOlll ^ nlOliO) ^ nlOlil) ^ nlOlii) ^ (~ (nll00l34 ^ nll00l33))) ^ nlOl0O) ^ nlOl0i) ^ (~ (nll01O36 ^ nll01O35))); assign wire_nlOil_dataout = (nlli1l === 1'b1) ? nlOlil : (nll0ll ^ nlOl0i); assign wire_nlOiO_dataout = (nlli1l === 1'b1) ? nlOliO : (nll0lO ^ nlOl0l); assign wire_nlOli_dataout = (nlli1l === 1'b1) ? nlOlli : ((nll0Oi ^ nlOl0O) ^ (~ (nll0ii32 ^ nll0ii31))); assign wire_nlOll_dataout = (nlli1l === 1'b1) ? nlOlll : ((nlli1i ^ nlOlii) ^ (~ (nll0iO30 ^ nll0iO29))); and(wire_nlOlO_dataout, nlOllO, nlli1l); and(wire_nlOOi_dataout, nlOlOi, nlli1l); and(wire_nlOOl_dataout, nlOlOl, nlli1l); and(wire_nlOOO_dataout, nlOlOO, nlli1l); assign wire_nlOOOi_dataout = (nlliii === 1'b1) ? (~ nlli0i) : wire_n1ilO_dataout; assign wire_nlOOOl_dataout = (nlliii === 1'b1) ? (~ nlli0i) : wire_n1iOi_dataout; assign wire_nlOOOO_dataout = (nlliii === 1'b1) ? (~ nlli0i) : wire_n1iOl_dataout; oper_add ni ( .a({((nlllil10 ^ nlllil9) & n1O), ((nllliO8 ^ nllliO7) & n1l), n1i, nlOO, ((nlllli6 ^ nlllli5) & nlOl), nlOi, nllO, ((nlllll4 ^ nlllll3) & nlll), 1'b1}), .b({{7{1'b1}}, 1'b0, 1'b1}), .cin(1'b0), .cout(), .o(wire_ni_o)); defparam ni.sgate_representation = 0, ni.width_a = 9, ni.width_b = 9, ni.width_o = 9; oper_decoder n00ii ( .i({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]}), .o(wire_n00ii_o)); defparam n00ii.width_i = 5, n00ii.width_o = 32; oper_mux n00il ( .data({{3{1'b0}}, {3{1'b1}}, ((nlOO0l ^ nlOlii) ^ nlOOli), nliOOO, {5{1'b0}}, 1'b1, nliliO, (nlOlOl ^ nlOlOi), {4{1'b0}}, wire_niiil_dataout, {2{1'b1}}, nll1iO, {3{1'b0}}, nliO1l, 1'b0, (nlOl0O ^ nlOl0l), 1'b1, wire_nlO0i_dataout}), .o(wire_n00il_o), .sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]})); defparam n00il.width_data = 32, n00il.width_sel = 5; oper_mux n00iO ( .data({{3{1'b0}}, {2{1'b1}}, 1'b0, ((nlOO0O ^ nlOlil) ^ nlOOll), nll11i, {6{1'b0}}, nlilli, (nlOlOO ^ nlOlOl), {4{1'b0}}, wire_niiiO_dataout, 1'b1, 1'b0, nll10O, {3{1'b0}}, nliO1O, 1'b0, (nlOlii ^ nlOl0O), 1'b0, wire_nlO0l_dataout}), .o(wire_n00iO_o), .sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]})); defparam n00iO.width_data = 32, n00iO.width_sel = 5; oper_mux n00li ( .data({{3{1'b0}}, {3{1'b1}}, (nlOliO ^ nlOl0i), nliOli, {5{1'b0}}, 1'b1, nlilll, nll11O, {4{1'b0}}, wire_niili_dataout, {2{1'b1}}, nll10l, {3{1'b0}}, nliO0i, 1'b0, nll0ll, 1'b1, wire_nlO0O_dataout}), .o(wire_n00li_o), .sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]})); defparam n00li.width_data = 32, n00li.width_sel = 5; oper_mux n00ll ( .data({{3{1'b0}}, {2{1'b1}}, 1'b0, (nlOlli ^ nlOl0l), nliOll, {6{1'b0}}, nlillO, nll10i, {4{1'b0}}, wire_niill_dataout, 1'b1, 1'b0, (nlOlli ^ nlOlii), {3{1'b0}}, nliO0l, 1'b0, nll0lO, 1'b0, wire_nlOii_dataout}), .o(wire_n00ll_o), .sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]})); defparam n00ll.width_data = 32, n00ll.width_sel = 5; oper_mux n00lO ( .data({{3{1'b0}}, {3{1'b1}}, nliliO, nliOlO, {5{1'b0}}, 1'b1, nlilOi, nliOOO, {4{1'b0}}, wire_niilO_dataout, {2{1'b1}}, (nlOlll ^ nlOlil), {3{1'b0}}, nliO0O, 1'b0, nll0Oi, 1'b1, wire_nlOil_dataout}), .o(wire_n00lO_o), .sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]})); defparam n00lO.width_data = 32, n00lO.width_sel = 5; oper_mux n00Oi ( .data({{6{1'b0}}, nlilli, nliOOl, {6{1'b0}}, nlilOl, nll11i, {4{1'b0}}, wire_niiOi_dataout, {2{1'b0}}, (nlOllO ^ nlOliO), {3{1'b0}}, nliOii, 1'b0, nlli1i, 1'b0, wire_nlOiO_dataout}), .o(wire_n00Oi_o), .sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]})); defparam n00Oi.width_data = 32, n00Oi.width_sel = 5; oper_mux n00Ol ( .data({{3{1'b0}}, 1'b1, 1'b0, 1'b1, nlilll, (nliO0O ^ nlOO1l), {5{1'b0}}, 1'b1, nlilOO, (nliO1l ^ nlOlOi), {4{1'b0}}, wire_niiOl_dataout, 1'b0, 1'b1, (nlOlOi ^ nlOlli), {3{1'b0}}, nliOil, 1'b0, ((nlOlll ^ nlOl0l) ^ nlOl0O), 1'b1, wire_nlOli_dataout}), .o(wire_n00Ol_o), .sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]})); defparam n00Ol.width_data = 32, n00Ol.width_sel = 5; oper_mux n00OO ( .data({{6{1'b0}}, nlillO, nll11l, {6{1'b0}}, nliO1i, (nlOlOO ^ nlOlOi), {4{1'b0}}, wire_niiOO_dataout, {2{1'b0}}, (nll1iO ^ nlOlll), {3{1'b0}}, nliOiO, 1'b0, (nlOlii ^ nlOl0l), 1'b0, wire_nlOll_dataout}), .o(wire_n00OO_o), .sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]})); defparam n00OO.width_data = 32, n00OO.width_sel = 5; oper_mux n0i0i ( .data({{4{1'b0}}, 1'b1, 1'b0, nliO1i, (nlOOil ^ nlOO0O), {6{1'b0}}, nliO0l, nll11l, {4{1'b0}}, wire_nil0i_dataout, {6{1'b0}}, nlOlii, {3{1'b0}}, wire_nlOOO_dataout}), .o(wire_n0i0i_o), .sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]})); defparam n0i0i.width_data = 32, n0i0i.width_sel = 5; oper_mux n0i0l ( .data({{4{1'b0}}, {2{1'b1}}, nliO1l, ((nlOOii ^ nlOO1O) ^ nlOO1l), {5{1'b0}}, 1'b1, nliO0O, ((nlOO1O ^ nlOlOl) ^ nlOlOi), {4{1'b0}}, wire_nil0l_dataout, {6{1'b0}}, nlOlil, {3{1'b0}}, wire_n11i_dataout}), .o(wire_n0i0l_o), .sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]})); defparam n0i0l.width_data = 32, n0i0l.width_sel = 5; oper_mux n0i0O ( .data({{4{1'b0}}, 1'b1, 1'b0, nliO1O, ((nlOOil ^ nlOO0i) ^ nlOO1O), {6{1'b0}}, nliOii, ((nlOO0i ^ nlOlOO) ^ nlOlOl), {4{1'b0}}, wire_nil0O_dataout, {6{1'b0}}, nlOliO, {3{1'b0}}, wire_n11l_dataout}), .o(wire_n0i0O_o), .sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]})); defparam n0i0O.width_data = 32, n0i0O.width_sel = 5; oper_mux n0i1i ( .data({{3{1'b0}}, 1'b1, 1'b0, 1'b1, nlilOi, (nlOO0l ^ nlOO1O), {5{1'b0}}, 1'b1, nliO1l, (nlOO1i ^ nlOlOl), {4{1'b0}}, wire_nil1i_dataout, 1'b0, 1'b1, (nll10O ^ nlOllO), {3{1'b0}}, nlOl0i, {3{1'b0}}, wire_nlOlO_dataout}), .o(wire_n0i1i_o), .sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]})); defparam n0i1i.width_data = 32, n0i1i.width_sel = 5; oper_mux n0i1l ( .data({{3{1'b0}}, 1'b1, {2{1'b0}}, nlilOl, (nlOO0O ^ nlOO0i), {6{1'b0}}, nliO1O, (nlOO1l ^ nlOlOO), {4{1'b0}}, wire_nil1l_dataout, {2{1'b0}}, (nll10l ^ nlOlOi), {3{1'b0}}, nlOl0l, {3{1'b0}}, wire_nlOOi_dataout}), .o(wire_n0i1l_o), .sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]})); defparam n0i1l.width_data = 32, n0i1l.width_sel = 5; oper_mux n0i1O ( .data({{4{1'b0}}, {2{1'b1}}, nlilOO, (nlOOii ^ nlOO0l), {5{1'b0}}, 1'b1, nliO0i, (nlOO1O ^ nlOO1i), {4{1'b0}}, wire_nil1O_dataout, {6{1'b0}}, nlOl0O, {3{1'b0}}, wire_nlOOl_dataout}), .o(wire_n0i1O_o), .sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]})); defparam n0i1O.width_data = 32, n0i1O.width_sel = 5; oper_mux n0iii ( .data({{4{1'b0}}, {2{1'b1}}, nliO0i, ((nliOli ^ nlOO1O) ^ nlOO1l), {5{1'b0}}, 1'b1, nliOil, ((nll11O ^ nlOlOl) ^ nlOlOi), {4{1'b0}}, wire_nilii_dataout, {6{1'b0}}, nlOlli, {3{1'b0}}, wire_n11O_dataout}), .o(wire_n0iii_o), .sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]})); defparam n0iii.width_data = 32, n0iii.width_sel = 5; oper_mux n0iil ( .data({{3{1'b0}}, 1'b1, {2{1'b0}}, nliO0l, ((nliOll ^ nlOO0i) ^ nlOO1O), {6{1'b0}}, nliOiO, ((nll10i ^ nlOlOO) ^ nlOlOl), {4{1'b0}}, wire_nilil_dataout, {6{1'b0}}, nlOlll, {3{1'b0}}, wire_n10i_dataout}), .o(wire_n0iil_o), .sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]})); defparam n0iil.width_data = 32, n0iil.width_sel = 5; oper_mux n0iiO ( .data({{5{1'b0}}, 1'b1, nliO0O, ((nliOlO ^ nlOO0l) ^ nlOO0i), {6{1'b0}}, nlOl0i, {5{1'b0}}, wire_niliO_dataout, {6{1'b0}}, nlOllO, {3{1'b0}}, wire_n10l_dataout}), .o(wire_n0iiO_o), .sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]})); defparam n0iiO.width_data = 32, n0iiO.width_sel = 5; oper_mux n0ili ( .data({{3{1'b0}}, 1'b1, {2{1'b0}}, nliOii, (nliOOi ^ nlOO0l), {6{1'b0}}, nlOl0l, {5{1'b0}}, wire_nilli_dataout, {6{1'b0}}, nlOlOi, {3{1'b0}}, wire_n10O_dataout}), .o(wire_n0ili_o), .sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]})); defparam n0ili.width_data = 32, n0ili.width_sel = 5; oper_mux n0ill ( .data({{5{1'b0}}, 1'b1, nliOil, ((nliOOi ^ nlOO1O) ^ nlOO1l), {6{1'b0}}, nlOl0O, {5{1'b0}}, wire_nilll_dataout, {6{1'b0}}, nlOlOl, {3{1'b0}}, wire_n1ii_dataout}), .o(wire_n0ill_o), .sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]})); defparam n0ill.width_data = 32, n0ill.width_sel = 5; oper_mux n0ilO ( .data({{6{1'b0}}, nliOiO, ((nliOOl ^ nlOO0i) ^ nlOO1l), {6{1'b0}}, nlOlii, {5{1'b0}}, wire_nillO_dataout, {6{1'b0}}, nlOlOO, {3{1'b0}}, wire_n1il_dataout}), .o(wire_n0ilO_o), .sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]})); defparam n0ilO.width_data = 32, n0ilO.width_sel = 5; oper_mux n0iOi ( .data({{6{1'b0}}, nlOl0i, {7{1'b0}}, nlOlil, {5{1'b0}}, wire_nilOi_dataout, {6{1'b0}}, nlOO1i, {3{1'b0}}, wire_n1iO_dataout}), .o(wire_n0iOi_o), .sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]})); defparam n0iOi.width_data = 32, n0iOi.width_sel = 5; oper_mux n0iOl ( .data({{6{1'b0}}, nlOl0l, {7{1'b0}}, nlOliO, {5{1'b0}}, wire_nilOl_dataout, {6{1'b0}}, nlOO1l, {3{1'b0}}, wire_n1li_dataout}), .o(wire_n0iOl_o), .sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]})); defparam n0iOl.width_data = 32, n0iOl.width_sel = 5; oper_mux n0iOO ( .data({{6{1'b0}}, nlOl0O, {7{1'b0}}, nlOlli, {5{1'b0}}, wire_nilOO_dataout, {6{1'b0}}, nlOO1O, {3{1'b0}}, wire_n1ll_dataout}), .o(wire_n0iOO_o), .sel({rpma_doublewidth_tx, rpmadwidth_tx, rprbs_sel[2:0]})); defparam n0iOO.width_data = 32, n0iOO.width_sel = 5; oper_selector n000i ( .data({1'b0, nlOOil, nlOlii, wire_nliOi_dataout}), .o(wire_n000i_o), .sel({nlilil, nlilii, wire_n00ii_o[25], wire_n00ii_o[0]})); defparam n000i.width_data = 4, n000i.width_sel = 4; oper_selector n001O ( .data({1'b0, nlOOii, nlOlil, wire_nlilO_dataout}), .o(wire_n001O_o), .sel({nlilil, nlilii, wire_n00ii_o[25], wire_n00ii_o[0]})); defparam n001O.width_data = 4, n001O.width_sel = 4; oper_selector n010i ( .data({1'b0, nlOlOO, nlOlOi, nlOO1l, wire_nli0l_dataout}), .o(wire_n010i_o), .sel({nlil0O, nlil1l, nlil0i, wire_n00ii_o[17], wire_n00ii_o[0]})); defparam n010i.width_data = 5, n010i.width_sel = 5; oper_selector n010O ( .data({1'b0, nlOO1i, nlOlOl, wire_nli0O_dataout}), .o(wire_n010O_o), .sel({nlil0O, nlil1O, ((wire_n00ii_o[16] | wire_n00ii_o[25]) | wire_n00ii_o[18]), wire_n00ii_o[0]})); defparam n010O.width_data = 4, n010O.width_sel = 4; oper_selector n011i ( .data({1'b0, nlOllO, nlOO1O, nlOO0l, wire_nli1l_dataout}), .o(wire_n011i_o), .sel({nlilil, nlil0l, wire_n00ii_o[25], nlil0i, wire_n00ii_o[0]})); defparam n011i.width_data = 5, n011i.width_sel = 5; oper_selector n011l ( .data({1'b0, nlOlOi, nlOO1l, nlOO0O, wire_nli1O_dataout}), .o(wire_n011l_o), .sel({nlilil, nlil0l, wire_n00ii_o[25], nlil0i, wire_n00ii_o[0]})); defparam n011l.width_data = 5, n011l.width_sel = 5; oper_selector n011O ( .data({1'b0, nlOlOl, nlOO1i, nlOllO, nlOO1O, wire_nli0i_dataout}), .o(wire_n011O_o), .sel({nlil0O, nlil0l, wire_n00ii_o[25], nlil0i, wire_n00ii_o[17], wire_n00ii_o[0]})); defparam n011O.width_data = 6, n011O.width_sel = 6; oper_selector n01iO ( .data({1'b0, nlOO1l, nlOlOi, nlOlOO, wire_nliii_dataout}), .o(wire_n01iO_o), .sel({nlil0O, nlil0l, wire_n00ii_o[25], ((wire_n00ii_o[16] | wire_n00ii_o[18]) | wire_n00ii_o[17]), wire_n00ii_o[0]})); defparam n01iO.width_data = 5, n01iO.width_sel = 5; oper_selector n01ll ( .data({1'b0, nlOO1O, nlOllO, nlOO1i, nlOlOl, wire_nliil_dataout}), .o(wire_n01ll_o), .sel({nlil0O, nlil0l, wire_n00ii_o[25], nlil0i, wire_n00ii_o[17], wire_n00ii_o[0]})); defparam n01ll.width_data = 6, n01ll.width_sel = 6; oper_selector n01lO ( .data({1'b0, nlOO0i, nlOlll, nlOO1l, nlOlOi, wire_nliiO_dataout}), .o(wire_n01lO_o), .sel({nlil0O, nlil0l, wire_n00ii_o[25], nlil0i, wire_n00ii_o[17], wire_n00ii_o[0]})); defparam n01lO.width_data = 6, n01lO.width_sel = 6; oper_selector n01Oi ( .data({1'b0, nlOO0l, nlOlli, nlOO1O, nlOllO, wire_nlili_dataout}), .o(wire_n01Oi_o), .sel({nlil0O, nlil0l, wire_n00ii_o[25], nlil0i, wire_n00ii_o[17], wire_n00ii_o[0]})); defparam n01Oi.width_data = 6, n01Oi.width_sel = 6; oper_selector n01Ol ( .data({1'b0, nlOO0O, nlOliO, nlOO0i, nlOlll, wire_nlill_dataout}), .o(wire_n01Ol_o), .sel({nlil0O, nlil0l, wire_n00ii_o[25], nlil0i, wire_n00ii_o[17], wire_n00ii_o[0]})); defparam n01Ol.width_data = 6, n01Ol.width_sel = 6; oper_selector n1O0O ( .data({1'b0, nlOl0i, nlOOll, wire_nl0iO_dataout}), .o(wire_n1O0O_o), .sel({nlil1i, nlilii, nliiOO, wire_n00ii_o[0]})); defparam n1O0O.width_data = 4, n1O0O.width_sel = 4; oper_selector n1Oii ( .data({1'b0, nlOl0l, nlOOli, wire_nl0li_dataout}), .o(wire_n1Oii_o), .sel({nlil1i, nlilii, nliiOO, wire_n00ii_o[0]})); defparam n1Oii.width_data = 4, n1Oii.width_sel = 4; oper_selector n1Oil ( .data({1'b0, nlOl0O, nlOOiO, wire_nl0ll_dataout}), .o(wire_n1Oil_o), .sel({nlil1i, nlilii, nliiOO, wire_n00ii_o[0]})); defparam n1Oil.width_data = 4, n1Oil.width_sel = 4; oper_selector n1OiO ( .data({1'b0, nlOlii, nlOOil, wire_nl0lO_dataout}), .o(wire_n1OiO_o), .sel({nlil1i, nlilii, nliiOO, wire_n00ii_o[0]})); defparam n1OiO.width_data = 4, n1OiO.width_sel = 4; oper_selector n1Oli ( .data({1'b0, nlOlil, nlOOii, wire_nl0Oi_dataout}), .o(wire_n1Oli_o), .sel({nlil1i, nlilii, nliiOO, wire_n00ii_o[0]})); defparam n1Oli.width_data = 4, n1Oli.width_sel = 4; oper_selector n1Oll ( .data({1'b0, nlOliO, nlOO0O, wire_nl0Ol_dataout}), .o(wire_n1Oll_o), .sel({nlil1i, nlilii, nliiOO, wire_n00ii_o[0]})); defparam n1Oll.width_data = 4, n1Oll.width_sel = 4; oper_selector n1OlO ( .data({1'b0, nlOlli, nlOO0l, wire_nl0OO_dataout}), .o(wire_n1OlO_o), .sel({nlil1i, nlilii, nliiOO, wire_n00ii_o[0]})); defparam n1OlO.width_data = 4, n1OlO.width_sel = 4; oper_selector n1OOi ( .data({1'b0, nlOlll, nlOO0i, wire_nli1i_dataout}), .o(wire_n1OOi_o), .sel({nlil1i, nlilii, nliiOO, wire_n00ii_o[0]})); defparam n1OOi.width_data = 4, n1OOi.width_sel = 4; oper_selector niOO ( .data({nllilO, wire_nl1O_dataout, nllili}), .o(wire_niOO_o), .sel({nlli, nilO, ((nlliil22 ^ nlliil21) & nlil)})); defparam niOO.width_data = 3, niOO.width_sel = 3; oper_selector nl1i ( .data({1'b0, ((nlliiO20 ^ nlliiO19) & nlliOO), (~ nllili)}), .o(wire_nl1i_o), .sel({nlli, nilO, ((nllill18 ^ nllill17) & nlil)})); defparam nl1i.width_data = 3, nl1i.width_sel = 3; oper_selector nl1l ( .data({(~ nllilO), wire_nl0i_dataout, 1'b0}), .o(wire_nl1l_o), .sel({nlli, ((nlliOi16 ^ nlliOi15) & nilO), nlil})); defparam nl1l.width_data = 3, nl1l.width_sel = 3; assign nliiOO = ((wire_n00ii_o[25] | wire_n00ii_o[17]) | wire_n00ii_o[4]), nlil0i = (wire_n00ii_o[16] | wire_n00ii_o[18]), nlil0l = (((((((((wire_n00ii_o[24] | wire_n00ii_o[2]) | wire_n00ii_o[28]) | wire_n00ii_o[27]) | wire_n00ii_o[26]) | wire_n00ii_o[11]) | wire_n00ii_o[10]) | wire_n00ii_o[9]) | wire_n00ii_o[8]) | wire_n00ii_o[1]), nlil0O = ((((((((((((((((wire_n00ii_o[31] | wire_n00ii_o[30]) | wire_n00ii_o[29]) | wire_n00ii_o[23]) | wire_n00ii_o[22]) | wire_n00ii_o[21]) | wire_n00ii_o[20]) | wire_n00ii_o[19]) | wire_n00ii_o[15]) | wire_n00ii_o[14]) | wire_n00ii_o[13]) | wire_n00ii_o[12]) | wire_n00ii_o[7]) | wire_n00ii_o[6]) | wire_n00ii_o[5]) | wire_n00ii_o[4]) | wire_n00ii_o[3]), nlil1i = (((((((((((((((wire_n00ii_o[31] | wire_n00ii_o[30]) | wire_n00ii_o[29]) | wire_n00ii_o[23]) | wire_n00ii_o[22]) | wire_n00ii_o[21]) | wire_n00ii_o[20]) | wire_n00ii_o[19]) | wire_n00ii_o[15]) | wire_n00ii_o[14]) | wire_n00ii_o[13]) | wire_n00ii_o[12]) | wire_n00ii_o[7]) | wire_n00ii_o[6]) | wire_n00ii_o[5]) | wire_n00ii_o[3]), nlil1l = ((((((((((wire_n00ii_o[24] | wire_n00ii_o[2]) | wire_n00ii_o[28]) | wire_n00ii_o[27]) | wire_n00ii_o[26]) | wire_n00ii_o[25]) | wire_n00ii_o[11]) | wire_n00ii_o[10]) | wire_n00ii_o[9]) | wire_n00ii_o[8]) | wire_n00ii_o[1]), nlil1O = ((((((((((wire_n00ii_o[24] | wire_n00ii_o[2]) | wire_n00ii_o[28]) | wire_n00ii_o[27]) | wire_n00ii_o[26]) | wire_n00ii_o[17]) | wire_n00ii_o[11]) | wire_n00ii_o[10]) | wire_n00ii_o[9]) | wire_n00ii_o[8]) | wire_n00ii_o[1]), nlilii = (((((((((((wire_n00ii_o[24] | wire_n00ii_o[16]) | wire_n00ii_o[2]) | wire_n00ii_o[28]) | wire_n00ii_o[27]) | wire_n00ii_o[26]) | wire_n00ii_o[18]) | wire_n00ii_o[11]) | wire_n00ii_o[10]) | wire_n00ii_o[9]) | wire_n00ii_o[8]) | wire_n00ii_o[1]), nlilil = (((((((((((((((((wire_n00ii_o[31] | wire_n00ii_o[30]) | wire_n00ii_o[29]) | wire_n00ii_o[23]) | wire_n00ii_o[22]) | wire_n00ii_o[21]) | wire_n00ii_o[20]) | wire_n00ii_o[19]) | wire_n00ii_o[17]) | wire_n00ii_o[15]) | wire_n00ii_o[14]) | wire_n00ii_o[13]) | wire_n00ii_o[12]) | wire_n00ii_o[7]) | wire_n00ii_o[6]) | wire_n00ii_o[5]) | wire_n00ii_o[4]) | wire_n00ii_o[3]), nliliO = (nlOlll ^ nlOl0O), nlilli = (nlOllO ^ nlOlii), nlilll = (nlOlOi ^ nlOlil), nlillO = (nlOlOl ^ nlOliO), nlilOi = (nlOlOO ^ nlOlli), nlilOl = (nlOO1i ^ nlOlll), nlilOO = (nlOO1l ^ nlOllO), nliO0i = (nlOO0O ^ nlOO1i), nliO0l = (nlOOii ^ nlOO1l), nliO0O = (nlOOil ^ nlOO1O), nliO1i = (nlOO1O ^ nlOlOi), nliO1l = (nlOO0i ^ nlOlOl), nliO1O = (nlOO0l ^ nlOlOO), nliOii = (nlOOiO ^ nlOO0i), nliOil = (nlOOli ^ nlOO0l), nliOiO = (nlOOll ^ nlOO0O), nliOli = (nlOO0l ^ nlOO0i), nliOll = (nlOO0O ^ nlOO0l), nliOlO = (nlOOii ^ nlOO0O), nliOOi = (nliOOl ^ nlOO0O), nliOOl = (nlOOil ^ nlOOii), nliOOO = (nlOO1O ^ nlOO1l), nll0ll = (nlOlil ^ nlOlii), nll0lO = (nlOliO ^ nlOlil), nll0Oi = ((nlOlli ^ nlOliO) ^ (~ (nll0Ol28 ^ nll0Ol27))), nll10i = (nlOO1l ^ nlOO1i), nll10l = (nlOliO ^ nlOl0O), nll10O = ((nlOlil ^ nlOl0l) ^ (~ (nll1ii46 ^ nll1ii45))), nll11i = (nlOO0i ^ nlOO1O), nll11l = (nlOO0i ^ nlOO1l), nll11O = (nlOO1i ^ nlOlOO), nll1iO = ((nlOlii ^ nlOl0i) ^ (~ (nll1li44 ^ nll1li43))), nlli0i = (((wire_n00ii_o[24] | wire_n00ii_o[16]) | wire_n00ii_o[2]) | (~ (nlli0l24 ^ nlli0l23))), nlli1i = (nlOlll ^ nlOlli), nlli1l = (wire_niOl_dataout | wire_niOi_dataout), nlliii = (nili & (~ nlOOlO)), nllili = ((((((((~ n1O) & (~ n1l)) & (~ n1i)) & (~ nlOO)) & (~ nlOl)) & (~ nlOi)) & (~ nllO)) & nlll), nllilO = (((((((nlOlll & nlOlli) & nlOliO) & nlOlil) & nlOlii) & nlOl0O) & nlOl0l) & nlOl0i), nlliOl = ((((((((~ nlOlll) & nlOlli) & (~ nlOliO)) & nlOlil) & (~ nlOlii)) & (~ nlOl0O)) & (~ nlOl0l)) & (~ nlOl0i)), nlliOO = (((n0i & (~ nlll0i)) & nlll1O) & (nlll1i14 ^ nlll1i13)), nlll0i = ((((((((~ n1O) & (~ n1l)) & (~ n1i)) & (~ nlOO)) & (~ nlOl)) & (~ nlOi)) & (~ nllO)) & (~ nlll)), nlll0l = (((((~ rpmadwidth_tx) & (~ rpma_doublewidth_tx)) & (~ rprbs_sel[0])) & (~ rprbs_sel[1])) & (~ rprbs_sel[2])), nlll1O = (((((((nlOlll & nlOlli) & (~ nlOliO)) & nlOlil) & nlOlii) & (~ nlOl0O)) & (~ nlOl0l)) & (~ nlOl0i)), nllllO = 1'b1, prbs_out = {nlOl1O, nlOl1l, nlOl1i, nlOiOO, nlOiOl, nlOiOi, nlOilO, nlOill, nlOili, nlOiiO, nlOiil, nlOiii, nlOi0O, nlOi0l, nlOi0i, nlOi1O, nlOi1l, nlOi1i, nlO0OO, nlO0Ol}; endmodule //stratixiv_hssi_tx_digi_prbs_gen //synopsys translate_on //VALID FILE //IP Functional Simulation Model //VERSION_BEGIN 12.0 cbx_mgl 2012:05:31:20:09:47:SJ cbx_simgen 2012:05:31:20:08:35:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 // Copyright (C) 1991-2012 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // You may only use these simulation model output files for simulation // purposes and expressly not for synthesis or any other purposes (in which // event Altera disclaims all warranties of any kind). //synopsys translate_off //synthesis_resources = lut 139 mux21 168 oper_decoder 2 oper_mux 184 `timescale 1 ps / 1 ps module stratixiv_hssi_tx_digi_enc_chnl_top ( cascaded_8b10b_en, clk, d21_5_eq_n, d2_2_eq_n, disp_out_3b, doublewidth, dwidth, endec, enpolinv_tx, ge_xaui_sel, ib_force_disparity, k_det, prbs_en, pudr, r8b10b_enc_ibm_en, renbitrev_tx, rendec_data_sel_tx, renpolinv_tx, rensymswap_tx, rev_loop_data, rev_loopbk, rforce_disp, rrev_loopbk, rst, rtxbitslip_en, tx_boundary_sel, tx_ctl_pre_en, tx_ctl_tc, tx_ctl_ts, tx_data_9_pre_en, tx_data_9_tc, tx_data_pg, tx_data_pre_en, tx_data_tc, tx_data_ts, txd_extend_tc, txlp20b) /* synthesis synthesis_clearbox=1 */; input cascaded_8b10b_en; input clk; input d21_5_eq_n; input d2_2_eq_n; output [1:0] disp_out_3b; input doublewidth; input dwidth; input endec; input enpolinv_tx; input ge_xaui_sel; input ib_force_disparity; input k_det; input prbs_en; output [19:0] pudr; input r8b10b_enc_ibm_en; input renbitrev_tx; input rendec_data_sel_tx; input renpolinv_tx; input rensymswap_tx; input [19:0] rev_loop_data; input rev_loopbk; input rforce_disp; input rrev_loopbk; input rst; input rtxbitslip_en; input [4:0] tx_boundary_sel; output [1:0] tx_ctl_pre_en; input [1:0] tx_ctl_tc; input tx_ctl_ts; output [1:0] tx_data_9_pre_en; input [1:0] tx_data_9_tc; input [19:0] tx_data_pg; output [15:0] tx_data_pre_en; input [15:0] tx_data_tc; input [7:0] tx_data_ts; input [1:0] txd_extend_tc; output [19:0] txlp20b; reg ni0O0l49; reg ni0O0l50; reg ni0O0O47; reg ni0O0O48; reg ni0Oii45; reg ni0Oii46; reg ni0OiO43; reg ni0OiO44; reg ni0Oli41; reg ni0Oli42; reg ni0Oll39; reg ni0Oll40; reg ni0OlO37; reg ni0OlO38; reg ni0OOi35; reg ni0OOi36; reg ni0OOl33; reg ni0OOl34; reg ni0OOO31; reg ni0OOO32; reg nii00i5; reg nii00i6; reg nii01l7; reg nii01l8; reg nii0ii3; reg nii0ii4; reg nii0iO1; reg nii0iO2; reg nii10i23; reg nii10i24; reg nii10l21; reg nii10l22; reg nii10O19; reg nii10O20; reg nii11i29; reg nii11i30; reg nii11l27; reg nii11l28; reg nii11O25; reg nii11O26; reg nii1ii17; reg nii1ii18; reg nii1il15; reg nii1il16; reg nii1li13; reg nii1li14; reg nii1lO11; reg nii1lO12; reg nii1OO10; reg nii1OO9; reg n01li; reg n01iO_clk_prev; wire wire_n01iO_PRN; wire wire_n01iO_ENA; reg n000i; reg n000l; reg n000O; reg n001i; reg n001l; reg n001O; reg n00ii; reg n00il; reg n00iO; reg n00li; reg n00ll; reg n00lO; reg n00Oi; reg n00Ol; reg n00OO; reg n01ii; reg n01il; reg n01lO; reg n01Oi; reg n01Ol; reg n01OO; reg n0i1i; reg n0i1l; reg n0i1O; reg n0iiO; reg n0ill; reg n0iOl; reg n0iOO; reg n0l0l; reg n0l1i; reg n0l1l; reg n0l1O; reg n0lii; reg n0lil; reg n0liO; reg n0lli; reg n0lll; reg n0llO; reg n0lOi; reg ni00i; reg ni01l; reg ni0ii; reg ni0il; reg ni0iO; reg ni0li; reg ni0ll; reg ni0Ol; reg ni1li; reg ni1ll; reg nii0Oi; reg nii0Ol; reg nii0OO; reg niii0i; reg niii0l; reg niii0O; reg niii1i; reg niii1l; reg niii1O; reg niiiii; reg niiiil; reg niiiiO; reg niiili; reg niiill; reg niiilO; reg niiiOi; reg niiiOl; reg niiiOO; reg niil1i; reg ni0Oi_clk_prev; wire wire_ni0Oi_CLRN; wire wire_ni0Oi_PRN; reg n0i0i; reg n0i0l; reg n0i0O; reg n0iii; reg n0iil; reg n0ili; reg n0ilO; reg n0iOi; reg n0l0i; reg n0l0O; reg ni00l; reg ni00O; reg ni01i; reg ni01O; reg ni0lO; reg ni1lO; reg ni1Oi; reg ni1Ol; reg ni1OO; reg nii1i; reg ni0OO_clk_prev; wire wire_ni0OO_CLRN; wire wire_ni0OO_PRN; wire wire_n00i_dataout; wire wire_n00l_dataout; wire wire_n00O_dataout; wire wire_n01i_dataout; wire wire_n01l_dataout; wire wire_n01ll_dataout; wire wire_n01O_dataout; wire wire_n0ii_dataout; wire wire_n0il_dataout; wire wire_n0iO_dataout; wire wire_n0li_dataout; wire wire_n0ll_dataout; wire wire_n0lO_dataout; wire wire_n0O_dataout; wire wire_n0O0i_dataout; wire wire_n0O0l_dataout; wire wire_n0O0O_dataout; wire wire_n0O1l_dataout; wire wire_n0O1O_dataout; wire wire_n0Oi_dataout; wire wire_n0Ol_dataout; wire wire_n0OO_dataout; wire wire_n0OOi_dataout; wire wire_n0OOl_dataout; wire wire_n10i_dataout; wire wire_n10l_dataout; wire wire_n10O_dataout; wire wire_n11i_dataout; wire wire_n11l_dataout; wire wire_n11O_dataout; wire wire_n1ii_dataout; wire wire_n1il_dataout; wire wire_n1iO_dataout; wire wire_n1li_dataout; wire wire_n1ll_dataout; wire wire_n1lO_dataout; wire wire_n1Oi_dataout; wire wire_n1Ol_dataout; wire wire_n1OO_dataout; wire wire_ni0i_dataout; wire wire_ni0l_dataout; wire wire_ni0O_dataout; wire wire_ni10i_dataout; wire wire_ni10l_dataout; wire wire_ni1i_dataout; wire wire_ni1l_dataout; wire wire_ni1O_dataout; wire wire_nii_dataout; wire wire_nii0i_dataout; wire wire_nii0l_dataout; wire wire_nii0O_dataout; wire wire_nii1l_dataout; wire wire_nii1O_dataout; wire wire_niii_dataout; wire wire_niiii_dataout; wire wire_niiil_dataout; wire wire_niiiO_dataout; wire wire_niil_dataout; wire wire_niili_dataout; wire wire_niill_dataout; wire wire_niilO_dataout; wire wire_niiO_dataout; wire wire_niiOi_dataout; wire wire_niiOl_dataout; wire wire_niiOO_dataout; wire wire_nil_dataout; wire wire_nil00l_dataout; wire wire_nil00O_dataout; wire wire_nil0i_dataout; wire wire_nil0l_dataout; wire wire_nil0O_dataout; wire wire_nil0OO_dataout; wire wire_nil1i_dataout; wire wire_nil1l_dataout; wire wire_nil1O_dataout; wire wire_nili_dataout; wire wire_nili1i_dataout; wire wire_niliOl_dataout; wire wire_niliOO_dataout; wire wire_nill_dataout; wire wire_nill0i_dataout; wire wire_nill0l_dataout; wire wire_nill0O_dataout; wire wire_nill1i_dataout; wire wire_nill1l_dataout; wire wire_nill1O_dataout; wire wire_nillii_dataout; wire wire_nillil_dataout; wire wire_nilO_dataout; wire wire_nilO0i_dataout; wire wire_nilO0l_dataout; wire wire_nilO0O_dataout; wire wire_nilOii_dataout; wire wire_nilOil_dataout; wire wire_nilOiO_dataout; wire wire_nilOli_dataout; wire wire_nilOll_dataout; wire wire_nilOlO_dataout; wire wire_nilOOi_dataout; wire wire_nilOOl_dataout; wire wire_nilOOO_dataout; wire wire_niO_dataout; wire wire_niOi_dataout; wire wire_niOl_dataout; wire wire_niOlOi_dataout; wire wire_niOO_dataout; wire wire_niOOOi_dataout; wire wire_niOOOl_dataout; wire wire_niOOOO_dataout; wire wire_nl000i_dataout; wire wire_nl000l_dataout; wire wire_nl001i_dataout; wire wire_nl001l_dataout; wire wire_nl001O_dataout; wire wire_nl00ll_dataout; wire wire_nl010O_dataout; wire wire_nl01iO_dataout; wire wire_nl01li_dataout; wire wire_nl01Ol_dataout; wire wire_nl0i_dataout; wire wire_nl0l_dataout; wire wire_nl0O_dataout; wire wire_nl10Ol_dataout; wire wire_nl10OO_dataout; wire wire_nl111i_dataout; wire wire_nl111l_dataout; wire wire_nl111O_dataout; wire wire_nl1i_dataout; wire wire_nl1i0O_dataout; wire wire_nl1iii_dataout; wire wire_nl1l_dataout; wire wire_nl1O_dataout; wire wire_nli_dataout; wire wire_nli0il_dataout; wire wire_nli0iO_dataout; wire wire_nli0li_dataout; wire wire_nli0ll_dataout; wire wire_nli0lO_dataout; wire wire_nli0Oi_dataout; wire wire_nli1il_dataout; wire wire_nlii_dataout; wire wire_nlil_dataout; wire wire_nliliO_dataout; wire wire_nlilli_dataout; wire wire_nliO_dataout; wire wire_nliO1i_dataout; wire wire_nliO1l_dataout; wire wire_nll_dataout; wire wire_nlli_dataout; wire wire_nlli0i_dataout; wire wire_nlli0l_dataout; wire wire_nlli1i_dataout; wire wire_nlliiO_dataout; wire wire_nllill_dataout; wire wire_nllilO_dataout; wire wire_nlliOi_dataout; wire wire_nlliOl_dataout; wire wire_nlliOO_dataout; wire wire_nlll0O_dataout; wire wire_nlOii_dataout; wire wire_nlOil_dataout; wire wire_nlOiO_dataout; wire wire_nlOli_dataout; wire wire_nlOll_dataout; wire wire_nlOlO_dataout; wire wire_nlOOi_dataout; wire wire_nlOOl_dataout; wire wire_nlOOO_dataout; wire [31:0] wire_nili1O_o; wire [15:0] wire_nillli_o; wire wire_n010i_o; wire wire_n010l_o; wire wire_n010O_o; wire wire_n011i_o; wire wire_n011l_o; wire wire_n011O_o; wire wire_n1O0i_o; wire wire_n1O0l_o; wire wire_n1O0O_o; wire wire_n1O1l_o; wire wire_n1O1O_o; wire wire_n1Oii_o; wire wire_n1Oil_o; wire wire_n1OiO_o; wire wire_n1Oli_o; wire wire_n1Oll_o; wire wire_n1OlO_o; wire wire_n1OOi_o; wire wire_n1OOl_o; wire wire_n1OOO_o; wire wire_niil0i_o; wire wire_niil0l_o; wire wire_niil0O_o; wire wire_niil1l_o; wire wire_niil1O_o; wire wire_niilii_o; wire wire_niilil_o; wire wire_niiliO_o; wire wire_niilli_o; wire wire_niilll_o; wire wire_niillO_o; wire wire_niilOi_o; wire wire_niilOl_o; wire wire_niilOO_o; wire wire_niiO0i_o; wire wire_niiO0l_o; wire wire_niiO0O_o; wire wire_niiO1i_o; wire wire_niiO1l_o; wire wire_niiO1O_o; wire wire_niiOii_o; wire wire_niiOil_o; wire wire_niiOiO_o; wire wire_niiOli_o; wire wire_niiOll_o; wire wire_niiOlO_o; wire wire_niiOOi_o; wire wire_niiOOl_o; wire wire_niiOOO_o; wire wire_nil00i_o; wire wire_nil01i_o; wire wire_nil01l_o; wire wire_nil01O_o; wire wire_nil0ii_o; wire wire_nil0il_o; wire wire_nil0iO_o; wire wire_nil0li_o; wire wire_nil0ll_o; wire wire_nil0lO_o; wire wire_nil0Oi_o; wire wire_nil0Ol_o; wire wire_nil10i_o; wire wire_nil10l_o; wire wire_nil10O_o; wire wire_nil11i_o; wire wire_nil11l_o; wire wire_nil11O_o; wire wire_nil1ii_o; wire wire_nil1il_o; wire wire_nil1iO_o; wire wire_nil1li_o; wire wire_nil1ll_o; wire wire_nil1lO_o; wire wire_nil1Oi_o; wire wire_nil1Ol_o; wire wire_nil1OO_o; wire wire_nili0i_o; wire wire_nili0l_o; wire wire_nili0O_o; wire wire_nilii_o; wire wire_niliii_o; wire wire_niliil_o; wire wire_niliiO_o; wire wire_nilil_o; wire wire_nilili_o; wire wire_nilill_o; wire wire_nililO_o; wire wire_niliO_o; wire wire_niliOi_o; wire wire_nilli_o; wire wire_nilll_o; wire wire_nillll_o; wire wire_nilllO_o; wire wire_nillO_o; wire wire_nillOi_o; wire wire_nillOl_o; wire wire_nillOO_o; wire wire_nilO1i_o; wire wire_nilO1l_o; wire wire_nilO1O_o; wire wire_nilOi_o; wire wire_nilOl_o; wire wire_nilOO_o; wire wire_niO0i_o; wire wire_niO0l_o; wire wire_niO0O_o; wire wire_niO1i_o; wire wire_niO1l_o; wire wire_niO1O_o; wire wire_niOii_o; wire wire_niOil_o; wire wire_niOiO_o; wire wire_niOli_o; wire wire_niOll_o; wire wire_niOlO_o; wire wire_niOOi_o; wire wire_niOOl_o; wire wire_niOOO_o; wire wire_nl00i_o; wire wire_nl00l_o; wire wire_nl00O_o; wire wire_nl01i_o; wire wire_nl01l_o; wire wire_nl01O_o; wire wire_nl0ii_o; wire wire_nl0il_o; wire wire_nl0iO_o; wire wire_nl0li_o; wire wire_nl0ll_o; wire wire_nl0lO_o; wire wire_nl0Oi_o; wire wire_nl0Ol_o; wire wire_nl0OO_o; wire wire_nl10i_o; wire wire_nl10l_o; wire wire_nl10O_o; wire wire_nl11i_o; wire wire_nl11l_o; wire wire_nl11O_o; wire wire_nl1ii_o; wire wire_nl1il_o; wire wire_nl1iO_o; wire wire_nl1li_o; wire wire_nl1ll_o; wire wire_nl1lO_o; wire wire_nl1Oi_o; wire wire_nl1Ol_o; wire wire_nl1OO_o; wire wire_nli0i_o; wire wire_nli0l_o; wire wire_nli0O_o; wire wire_nli1i_o; wire wire_nli1l_o; wire wire_nli1O_o; wire wire_nliii_o; wire wire_nliil_o; wire wire_nliiO_o; wire wire_nlili_o; wire wire_nlill_o; wire wire_nlilO_o; wire wire_nliOi_o; wire wire_nliOl_o; wire wire_nliOO_o; wire wire_nll0i_o; wire wire_nll0l_o; wire wire_nll0O_o; wire wire_nll1i_o; wire wire_nll1l_o; wire wire_nll1O_o; wire wire_nllii_o; wire wire_nllil_o; wire wire_nlliO_o; wire wire_nllli_o; wire wire_nllll_o; wire wire_nlllO_o; wire wire_nllOi_o; wire wire_nllOl_o; wire wire_nllOO_o; wire wire_nlO0i_o; wire wire_nlO0l_o; wire wire_nlO0O_o; wire wire_nlO1i_o; wire wire_nlO1l_o; wire wire_nlO1O_o; wire ni000i; wire ni000l; wire ni000O; wire ni001i; wire ni001l; wire ni001O; wire ni00ii; wire ni00il; wire ni00iO; wire ni00li; wire ni00ll; wire ni00lO; wire ni00Oi; wire ni00Ol; wire ni00OO; wire ni01il; wire ni01iO; wire ni01li; wire ni01ll; wire ni01lO; wire ni01Oi; wire ni01Ol; wire ni01OO; wire ni0i0i; wire ni0i0l; wire ni0i0O; wire ni0i1i; wire ni0i1l; wire ni0i1O; wire ni0iii; wire ni0iil; wire ni0iiO; wire ni0ili; wire ni0ill; wire ni0ilO; wire ni0iOi; wire ni0iOl; wire ni0iOO; wire ni0l0i; wire ni0l0l; wire ni0l0O; wire ni0l1i; wire ni0l1l; wire ni0l1O; wire ni0lii; wire ni0lil; wire ni0liO; wire ni0lli; wire ni0lll; wire ni0llO; wire ni0lOi; wire ni0lOl; wire ni0lOO; wire ni0O0i; wire ni0O1i; wire ni0O1l; wire ni0O1O; wire ni0Oil; wire nii00O; wire nii1iO; wire nii1Ol; initial ni0O0l49 = 0; always @ ( posedge clk) ni0O0l49 <= ni0O0l50; event ni0O0l49_event; initial #1 ->ni0O0l49_event; always @(ni0O0l49_event) ni0O0l49 <= {1{1'b1}}; initial ni0O0l50 = 0; always @ ( posedge clk) ni0O0l50 <= ni0O0l49; initial ni0O0O47 = 0; always @ ( posedge clk) ni0O0O47 <= ni0O0O48; event ni0O0O47_event; initial #1 ->ni0O0O47_event; always @(ni0O0O47_event) ni0O0O47 <= {1{1'b1}}; initial ni0O0O48 = 0; always @ ( posedge clk) ni0O0O48 <= ni0O0O47; initial ni0Oii45 = 0; always @ ( posedge clk) ni0Oii45 <= ni0Oii46; event ni0Oii45_event; initial #1 ->ni0Oii45_event; always @(ni0Oii45_event) ni0Oii45 <= {1{1'b1}}; initial ni0Oii46 = 0; always @ ( posedge clk) ni0Oii46 <= ni0Oii45; initial ni0OiO43 = 0; always @ ( posedge clk) ni0OiO43 <= ni0OiO44; event ni0OiO43_event; initial #1 ->ni0OiO43_event; always @(ni0OiO43_event) ni0OiO43 <= {1{1'b1}}; initial ni0OiO44 = 0; always @ ( posedge clk) ni0OiO44 <= ni0OiO43; initial ni0Oli41 = 0; always @ ( posedge clk) ni0Oli41 <= ni0Oli42; event ni0Oli41_event; initial #1 ->ni0Oli41_event; always @(ni0Oli41_event) ni0Oli41 <= {1{1'b1}}; initial ni0Oli42 = 0; always @ ( posedge clk) ni0Oli42 <= ni0Oli41; initial ni0Oll39 = 0; always @ ( posedge clk) ni0Oll39 <= ni0Oll40; event ni0Oll39_event; initial #1 ->ni0Oll39_event; always @(ni0Oll39_event) ni0Oll39 <= {1{1'b1}}; initial ni0Oll40 = 0; always @ ( posedge clk) ni0Oll40 <= ni0Oll39; initial ni0OlO37 = 0; always @ ( posedge clk) ni0OlO37 <= ni0OlO38; event ni0OlO37_event; initial #1 ->ni0OlO37_event; always @(ni0OlO37_event) ni0OlO37 <= {1{1'b1}}; initial ni0OlO38 = 0; always @ ( posedge clk) ni0OlO38 <= ni0OlO37; initial ni0OOi35 = 0; always @ ( posedge clk) ni0OOi35 <= ni0OOi36; event ni0OOi35_event; initial #1 ->ni0OOi35_event; always @(ni0OOi35_event) ni0OOi35 <= {1{1'b1}}; initial ni0OOi36 = 0; always @ ( posedge clk) ni0OOi36 <= ni0OOi35; initial ni0OOl33 = 0; always @ ( posedge clk) ni0OOl33 <= ni0OOl34; event ni0OOl33_event; initial #1 ->ni0OOl33_event; always @(ni0OOl33_event) ni0OOl33 <= {1{1'b1}}; initial ni0OOl34 = 0; always @ ( posedge clk) ni0OOl34 <= ni0OOl33; initial ni0OOO31 = 0; always @ ( posedge clk) ni0OOO31 <= ni0OOO32; event ni0OOO31_event; initial #1 ->ni0OOO31_event; always @(ni0OOO31_event) ni0OOO31 <= {1{1'b1}}; initial ni0OOO32 = 0; always @ ( posedge clk) ni0OOO32 <= ni0OOO31; initial nii00i5 = 0; always @ ( posedge clk) nii00i5 <= nii00i6; event nii00i5_event; initial #1 ->nii00i5_event; always @(nii00i5_event) nii00i5 <= {1{1'b1}}; initial nii00i6 = 0; always @ ( posedge clk) nii00i6 <= nii00i5; initial nii01l7 = 0; always @ ( posedge clk) nii01l7 <= nii01l8; event nii01l7_event; initial #1 ->nii01l7_event; always @(nii01l7_event) nii01l7 <= {1{1'b1}}; initial nii01l8 = 0; always @ ( posedge clk) nii01l8 <= nii01l7; initial nii0ii3 = 0; always @ ( posedge clk) nii0ii3 <= nii0ii4; event nii0ii3_event; initial #1 ->nii0ii3_event; always @(nii0ii3_event) nii0ii3 <= {1{1'b1}}; initial nii0ii4 = 0; always @ ( posedge clk) nii0ii4 <= nii0ii3; initial nii0iO1 = 0; always @ ( posedge clk) nii0iO1 <= nii0iO2; event nii0iO1_event; initial #1 ->nii0iO1_event; always @(nii0iO1_event) nii0iO1 <= {1{1'b1}}; initial nii0iO2 = 0; always @ ( posedge clk) nii0iO2 <= nii0iO1; initial nii10i23 = 0; always @ ( posedge clk) nii10i23 <= nii10i24; event nii10i23_event; initial #1 ->nii10i23_event; always @(nii10i23_event) nii10i23 <= {1{1'b1}}; initial nii10i24 = 0; always @ ( posedge clk) nii10i24 <= nii10i23; initial nii10l21 = 0; always @ ( posedge clk) nii10l21 <= nii10l22; event nii10l21_event; initial #1 ->nii10l21_event; always @(nii10l21_event) nii10l21 <= {1{1'b1}}; initial nii10l22 = 0; always @ ( posedge clk) nii10l22 <= nii10l21; initial nii10O19 = 0; always @ ( posedge clk) nii10O19 <= nii10O20; event nii10O19_event; initial #1 ->nii10O19_event; always @(nii10O19_event) nii10O19 <= {1{1'b1}}; initial nii10O20 = 0; always @ ( posedge clk) nii10O20 <= nii10O19; initial nii11i29 = 0; always @ ( posedge clk) nii11i29 <= nii11i30; event nii11i29_event; initial #1 ->nii11i29_event; always @(nii11i29_event) nii11i29 <= {1{1'b1}}; initial nii11i30 = 0; always @ ( posedge clk) nii11i30 <= nii11i29; initial nii11l27 = 0; always @ ( posedge clk) nii11l27 <= nii11l28; event nii11l27_event; initial #1 ->nii11l27_event; always @(nii11l27_event) nii11l27 <= {1{1'b1}}; initial nii11l28 = 0; always @ ( posedge clk) nii11l28 <= nii11l27; initial nii11O25 = 0; always @ ( posedge clk) nii11O25 <= nii11O26; event nii11O25_event; initial #1 ->nii11O25_event; always @(nii11O25_event) nii11O25 <= {1{1'b1}}; initial nii11O26 = 0; always @ ( posedge clk) nii11O26 <= nii11O25; initial nii1ii17 = 0; always @ ( posedge clk) nii1ii17 <= nii1ii18; event nii1ii17_event; initial #1 ->nii1ii17_event; always @(nii1ii17_event) nii1ii17 <= {1{1'b1}}; initial nii1ii18 = 0; always @ ( posedge clk) nii1ii18 <= nii1ii17; initial nii1il15 = 0; always @ ( posedge clk) nii1il15 <= nii1il16; event nii1il15_event; initial #1 ->nii1il15_event; always @(nii1il15_event) nii1il15 <= {1{1'b1}}; initial nii1il16 = 0; always @ ( posedge clk) nii1il16 <= nii1il15; initial nii1li13 = 0; always @ ( posedge clk) nii1li13 <= nii1li14; event nii1li13_event; initial #1 ->nii1li13_event; always @(nii1li13_event) nii1li13 <= {1{1'b1}}; initial nii1li14 = 0; always @ ( posedge clk) nii1li14 <= nii1li13; initial nii1lO11 = 0; always @ ( posedge clk) nii1lO11 <= nii1lO12; event nii1lO11_event; initial #1 ->nii1lO11_event; always @(nii1lO11_event) nii1lO11 <= {1{1'b1}}; initial nii1lO12 = 0; always @ ( posedge clk) nii1lO12 <= nii1lO11; initial nii1OO10 = 0; always @ ( posedge clk) nii1OO10 <= nii1OO9; initial nii1OO9 = 0; always @ ( posedge clk) nii1OO9 <= nii1OO10; event nii1OO9_event; initial #1 ->nii1OO9_event; always @(nii1OO9_event) nii1OO9 <= {1{1'b1}}; initial begin n01li = 0; end always @ (clk or wire_n01iO_PRN or rst) begin if (wire_n01iO_PRN == 1'b0) begin n01li <= 1; end else if (rst == 1'b1) begin n01li <= 0; end else if (wire_n01iO_ENA == 1'b1) if (clk != n01iO_clk_prev && clk == 1'b1) begin n01li <= ni0Oil; end n01iO_clk_prev <= clk; end assign wire_n01iO_ENA = ((ib_force_disparity & tx_data_9_tc[0]) & (~ n01li)), wire_n01iO_PRN = (ni0O0l50 ^ ni0O0l49); initial begin n000i = 0; n000l = 0; n000O = 0; n001i = 0; n001l = 0; n001O = 0; n00ii = 0; n00il = 0; n00iO = 0; n00li = 0; n00ll = 0; n00lO = 0; n00Oi = 0; n00Ol = 0; n00OO = 0; n01ii = 0; n01il = 0; n01lO = 0; n01Oi = 0; n01Ol = 0; n01OO = 0; n0i1i = 0; n0i1l = 0; n0i1O = 0; n0iiO = 0; n0ill = 0; n0iOl = 0; n0iOO = 0; n0l0l = 0; n0l1i = 0; n0l1l = 0; n0l1O = 0; n0lii = 0; n0lil = 0; n0liO = 0; n0lli = 0; n0lll = 0; n0llO = 0; n0lOi = 0; ni00i = 0; ni01l = 0; ni0ii = 0; ni0il = 0; ni0iO = 0; ni0li = 0; ni0ll = 0; ni0Ol = 0; ni1li = 0; ni1ll = 0; nii0Oi = 0; nii0Ol = 0; nii0OO = 0; niii0i = 0; niii0l = 0; niii0O = 0; niii1i = 0; niii1l = 0; niii1O = 0; niiiii = 0; niiiil = 0; niiiiO = 0; niiili = 0; niiill = 0; niiilO = 0; niiiOi = 0; niiiOl = 0; niiiOO = 0; niil1i = 0; end always @ (clk or wire_ni0Oi_PRN or wire_ni0Oi_CLRN) begin if (wire_ni0Oi_PRN == 1'b0) begin n000i <= 1; n000l <= 1; n000O <= 1; n001i <= 1; n001l <= 1; n001O <= 1; n00ii <= 1; n00il <= 1; n00iO <= 1; n00li <= 1; n00ll <= 1; n00lO <= 1; n00Oi <= 1; n00Ol <= 1; n00OO <= 1; n01ii <= 1; n01il <= 1; n01lO <= 1; n01Oi <= 1; n01Ol <= 1; n01OO <= 1; n0i1i <= 1; n0i1l <= 1; n0i1O <= 1; n0iiO <= 1; n0ill <= 1; n0iOl <= 1; n0iOO <= 1; n0l0l <= 1; n0l1i <= 1; n0l1l <= 1; n0l1O <= 1; n0lii <= 1; n0lil <= 1; n0liO <= 1; n0lli <= 1; n0lll <= 1; n0llO <= 1; n0lOi <= 1; ni00i <= 1; ni01l <= 1; ni0ii <= 1; ni0il <= 1; ni0iO <= 1; ni0li <= 1; ni0ll <= 1; ni0Ol <= 1; ni1li <= 1; ni1ll <= 1; nii0Oi <= 1; nii0Ol <= 1; nii0OO <= 1; niii0i <= 1; niii0l <= 1; niii0O <= 1; niii1i <= 1; niii1l <= 1; niii1O <= 1; niiiii <= 1; niiiil <= 1; niiiiO <= 1; niiili <= 1; niiill <= 1; niiilO <= 1; niiiOi <= 1; niiiOl <= 1; niiiOO <= 1; niil1i <= 1; end else if (wire_ni0Oi_CLRN == 1'b0) begin n000i <= 0; n000l <= 0; n000O <= 0; n001i <= 0; n001l <= 0; n001O <= 0; n00ii <= 0; n00il <= 0; n00iO <= 0; n00li <= 0; n00ll <= 0; n00lO <= 0; n00Oi <= 0; n00Ol <= 0; n00OO <= 0; n01ii <= 0; n01il <= 0; n01lO <= 0; n01Oi <= 0; n01Ol <= 0; n01OO <= 0; n0i1i <= 0; n0i1l <= 0; n0i1O <= 0; n0iiO <= 0; n0ill <= 0; n0iOl <= 0; n0iOO <= 0; n0l0l <= 0; n0l1i <= 0; n0l1l <= 0; n0l1O <= 0; n0lii <= 0; n0lil <= 0; n0liO <= 0; n0lli <= 0; n0lll <= 0; n0llO <= 0; n0lOi <= 0; ni00i <= 0; ni01l <= 0; ni0ii <= 0; ni0il <= 0; ni0iO <= 0; ni0li <= 0; ni0ll <= 0; ni0Ol <= 0; ni1li <= 0; ni1ll <= 0; nii0Oi <= 0; nii0Ol <= 0; nii0OO <= 0; niii0i <= 0; niii0l <= 0; niii0O <= 0; niii1i <= 0; niii1l <= 0; niii1O <= 0; niiiii <= 0; niiiil <= 0; niiiiO <= 0; niiili <= 0; niiill <= 0; niiilO <= 0; niiiOi <= 0; niiiOl <= 0; niiiOO <= 0; niil1i <= 0; end else if (clk != ni0Oi_clk_prev && clk == 1'b1) begin n000i <= tx_data_tc[3]; n000l <= tx_data_tc[4]; n000O <= tx_data_tc[5]; n001i <= tx_data_tc[0]; n001l <= tx_data_tc[1]; n001O <= tx_data_tc[2]; n00ii <= tx_data_tc[6]; n00il <= tx_data_tc[7]; n00iO <= tx_data_tc[8]; n00li <= tx_data_tc[9]; n00ll <= tx_data_tc[10]; n00lO <= tx_data_tc[11]; n00Oi <= tx_data_tc[12]; n00Ol <= tx_data_tc[13]; n00OO <= tx_data_tc[14]; n01ii <= rev_loopbk; n01il <= wire_n01ll_dataout; n01lO <= tx_data_9_tc[0]; n01Oi <= tx_data_9_tc[1]; n01Ol <= tx_ctl_tc[0]; n01OO <= tx_ctl_tc[1]; n0i1i <= tx_data_tc[15]; n0i1l <= n0lOi; n0i1O <= ni1ll; n0iiO <= ni01l; n0ill <= ni00i; n0iOl <= ni0ii; n0iOO <= ni0il; n0l0l <= ni0Ol; n0l1i <= ni0iO; n0l1l <= ni0li; n0l1O <= ni0ll; n0lii <= n0lil; n0lil <= rensymswap_tx; n0liO <= n0lli; n0lli <= renbitrev_tx; n0lll <= n0llO; n0llO <= (renpolinv_tx & enpolinv_tx); n0lOi <= wire_nii1l_dataout; ni00i <= wire_niill_dataout; ni01l <= wire_niiiO_dataout; ni0ii <= wire_niiOl_dataout; ni0il <= wire_niiOO_dataout; ni0iO <= wire_nil1i_dataout; ni0li <= wire_nil1l_dataout; ni0ll <= wire_nil1O_dataout; ni0Ol <= wire_nil0l_dataout; ni1li <= n01ii; ni1ll <= wire_nii1O_dataout; nii0Oi <= wire_niliO_o; nii0Ol <= wire_nilli_o; nii0OO <= wire_nilll_o; niii0i <= wire_nilOO_o; niii0l <= wire_niO1i_o; niii0O <= wire_niO1l_o; niii1i <= wire_nillO_o; niii1l <= wire_nilOi_o; niii1O <= wire_nilOl_o; niiiii <= wire_niO1O_o; niiiil <= wire_niO0i_o; niiiiO <= wire_niO0l_o; niiili <= wire_niO0O_o; niiill <= wire_niOii_o; niiilO <= wire_niOil_o; niiiOi <= wire_niOiO_o; niiiOl <= wire_niOli_o; niiiOO <= wire_niOll_o; niil1i <= wire_nilil_o; end ni0Oi_clk_prev <= clk; end assign wire_ni0Oi_CLRN = ((ni0Oii46 ^ ni0Oii45) & (~ rst)), wire_ni0Oi_PRN = (ni0O0O48 ^ ni0O0O47); initial begin n0i0i = 0; n0i0l = 0; n0i0O = 0; n0iii = 0; n0iil = 0; n0ili = 0; n0ilO = 0; n0iOi = 0; n0l0i = 0; n0l0O = 0; ni00l = 0; ni00O = 0; ni01i = 0; ni01O = 0; ni0lO = 0; ni1lO = 0; ni1Oi = 0; ni1Ol = 0; ni1OO = 0; nii1i = 0; end always @ (clk or wire_ni0OO_PRN or wire_ni0OO_CLRN) begin if (wire_ni0OO_PRN == 1'b0) begin n0i0i <= 1; n0i0l <= 1; n0i0O <= 1; n0iii <= 1; n0iil <= 1; n0ili <= 1; n0ilO <= 1; n0iOi <= 1; n0l0i <= 1; n0l0O <= 1; ni00l <= 1; ni00O <= 1; ni01i <= 1; ni01O <= 1; ni0lO <= 1; ni1lO <= 1; ni1Oi <= 1; ni1Ol <= 1; ni1OO <= 1; nii1i <= 1; end else if (wire_ni0OO_CLRN == 1'b0) begin n0i0i <= 0; n0i0l <= 0; n0i0O <= 0; n0iii <= 0; n0iil <= 0; n0ili <= 0; n0ilO <= 0; n0iOi <= 0; n0l0i <= 0; n0l0O <= 0; ni00l <= 0; ni00O <= 0; ni01i <= 0; ni01O <= 0; ni0lO <= 0; ni1lO <= 0; ni1Oi <= 0; ni1Ol <= 0; ni1OO <= 0; nii1i <= 0; end else if (clk != ni0OO_clk_prev && clk == 1'b1) begin n0i0i <= ni1lO; n0i0l <= ni1Oi; n0i0O <= ni1Ol; n0iii <= ni1OO; n0iil <= ni01i; n0ili <= ni01O; n0ilO <= ni00l; n0iOi <= ni00O; n0l0i <= ni0lO; n0l0O <= nii1i; ni00l <= wire_niilO_dataout; ni00O <= wire_niiOi_dataout; ni01i <= wire_niiil_dataout; ni01O <= wire_niili_dataout; ni0lO <= wire_nil0i_dataout; ni1lO <= wire_nii0i_dataout; ni1Oi <= wire_nii0l_dataout; ni1Ol <= wire_nii0O_dataout; ni1OO <= wire_niiii_dataout; nii1i <= wire_nil0O_dataout; end ni0OO_clk_prev <= clk; end assign wire_ni0OO_CLRN = (ni0Oli42 ^ ni0Oli41), wire_ni0OO_PRN = ((ni0OiO44 ^ ni0OiO43) & (~ rst)); event n0i0i_event; event n0i0l_event; event n0i0O_event; event n0iii_event; event n0iil_event; event n0ili_event; event n0ilO_event; event n0iOi_event; event n0l0i_event; event n0l0O_event; event ni00l_event; event ni00O_event; event ni01i_event; event ni01O_event; event ni0lO_event; event ni1lO_event; event ni1Oi_event; event ni1Ol_event; event ni1OO_event; event nii1i_event; initial #1 ->n0i0i_event; initial #1 ->n0i0l_event; initial #1 ->n0i0O_event; initial #1 ->n0iii_event; initial #1 ->n0iil_event; initial #1 ->n0ili_event; initial #1 ->n0ilO_event; initial #1 ->n0iOi_event; initial #1 ->n0l0i_event; initial #1 ->n0l0O_event; initial #1 ->ni00l_event; initial #1 ->ni00O_event; initial #1 ->ni01i_event; initial #1 ->ni01O_event; initial #1 ->ni0lO_event; initial #1 ->ni1lO_event; initial #1 ->ni1Oi_event; initial #1 ->ni1Ol_event; initial #1 ->ni1OO_event; initial #1 ->nii1i_event; always @(n0i0i_event) n0i0i <= 1; always @(n0i0l_event) n0i0l <= 1; always @(n0i0O_event) n0i0O <= 1; always @(n0iii_event) n0iii <= 1; always @(n0iil_event) n0iil <= 1; always @(n0ili_event) n0ili <= 1; always @(n0ilO_event) n0ilO <= 1; always @(n0iOi_event) n0iOi <= 1; always @(n0l0i_event) n0l0i <= 1; always @(n0l0O_event) n0l0O <= 1; always @(ni00l_event) ni00l <= 1; always @(ni00O_event) ni00O <= 1; always @(ni01i_event) ni01i <= 1; always @(ni01O_event) ni01O <= 1; always @(ni0lO_event) ni0lO <= 1; always @(ni1lO_event) ni1lO <= 1; always @(ni1Oi_event) ni1Oi <= 1; always @(ni1Ol_event) ni1Ol <= 1; always @(ni1OO_event) ni1OO <= 1; always @(nii1i_event) nii1i <= 1; assign wire_n00i_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[11] : wire_ni0l_dataout; assign wire_n00l_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[12] : wire_ni0O_dataout; assign wire_n00O_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[13] : wire_niii_dataout; assign wire_n01i_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[8] : wire_ni1l_dataout; assign wire_n01l_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[9] : wire_ni1O_dataout; assign wire_n01ll_dataout = (cascaded_8b10b_en === 1'b1) ? wire_nlli1i_dataout : wire_nl010O_dataout; assign wire_n01O_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[10] : wire_ni0i_dataout; assign wire_n0ii_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[14] : wire_niil_dataout; assign wire_n0il_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[15] : wire_niiO_dataout; and(wire_n0iO_dataout, wire_nili_dataout, ~(nii1Ol)); and(wire_n0li_dataout, wire_nill_dataout, ~(nii1Ol)); and(wire_n0ll_dataout, wire_nilO_dataout, ~(nii1Ol)); and(wire_n0lO_dataout, wire_niOi_dataout, ~(nii1Ol)); assign wire_n0O_dataout = (rendec_data_sel_tx === 1'b1) ? tx_ctl_tc[0] : tx_ctl_ts; assign wire_n0O0i_dataout = (ib_force_disparity === 1'b1) ? (((~ n01li) & tx_data_9_tc[0]) | n01il) : wire_n0O0l_dataout; or(wire_n0O0l_dataout, wire_n0O0O_dataout, ((rforce_disp & (~ txd_extend_tc[0])) & tx_data_9_tc[0])); and(wire_n0O0O_dataout, n01il, ~(((rforce_disp & txd_extend_tc[0]) & tx_data_9_tc[0]))); assign wire_n0O1l_dataout = (cascaded_8b10b_en === 1'b1) ? wire_ni10i_dataout : wire_n0O0i_dataout; assign wire_n0O1O_dataout = (cascaded_8b10b_en === 1'b1) ? wire_n0OOi_dataout : wire_nl010O_dataout; or(wire_n0Oi_dataout, wire_niOl_dataout, nii1Ol); and(wire_n0Ol_dataout, wire_niOO_dataout, ~(nii1Ol)); or(wire_n0OO_dataout, wire_nl1i_dataout, nii1Ol); or(wire_n0OOi_dataout, wire_n0OOl_dataout, ((rforce_disp & (~ txd_extend_tc[1])) & tx_data_9_tc[1])); and(wire_n0OOl_dataout, wire_nl010O_dataout, ~(((rforce_disp & txd_extend_tc[1]) & tx_data_9_tc[1]))); and(wire_n10i_dataout, tx_data_tc[12], rendec_data_sel_tx); and(wire_n10l_dataout, tx_data_tc[13], rendec_data_sel_tx); and(wire_n10O_dataout, tx_data_tc[14], rendec_data_sel_tx); and(wire_n11i_dataout, tx_data_tc[9], rendec_data_sel_tx); and(wire_n11l_dataout, tx_data_tc[10], rendec_data_sel_tx); and(wire_n11O_dataout, tx_data_tc[11], rendec_data_sel_tx); and(wire_n1ii_dataout, tx_data_tc[15], rendec_data_sel_tx); assign wire_n1il_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[0] : wire_n0iO_dataout; assign wire_n1iO_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[1] : wire_n0li_dataout; assign wire_n1li_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[2] : wire_n0ll_dataout; assign wire_n1ll_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[3] : wire_n0lO_dataout; assign wire_n1lO_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[4] : wire_n0Oi_dataout; assign wire_n1Oi_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[5] : wire_n0Ol_dataout; assign wire_n1Ol_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[6] : wire_n0OO_dataout; assign wire_n1OO_dataout = (cascaded_8b10b_en === 1'b1) ? tx_data_tc[7] : wire_ni1i_dataout; and(wire_ni0i_dataout, wire_nl0l_dataout, ~(nii1Ol)); and(wire_ni0l_dataout, wire_nl0O_dataout, ~(nii1Ol)); and(wire_ni0O_dataout, wire_nlii_dataout, ~(nii1Ol)); or(wire_ni10i_dataout, wire_ni10l_dataout, ((rforce_disp & (~ txd_extend_tc[0])) & tx_data_9_tc[0])); and(wire_ni10l_dataout, n01il, ~(((rforce_disp & txd_extend_tc[0]) & tx_data_9_tc[0]))); and(wire_ni1i_dataout, wire_nl1l_dataout, ~(nii1Ol)); and(wire_ni1l_dataout, wire_nl1O_dataout, ~(nii1Ol)); and(wire_ni1O_dataout, wire_nl0i_dataout, ~(nii1Ol)); and(wire_nii_dataout, tx_ctl_tc[1], rendec_data_sel_tx); assign wire_nii0i_dataout = (rtxbitslip_en === 1'b1) ? wire_niil0i_o : wire_niliO_o; assign wire_nii0l_dataout = (rtxbitslip_en === 1'b1) ? wire_niil0l_o : wire_nilli_o; assign wire_nii0O_dataout = (rtxbitslip_en === 1'b1) ? wire_niil0O_o : wire_nilll_o; assign wire_nii1l_dataout = (rtxbitslip_en === 1'b1) ? wire_niil1l_o : wire_nilii_o; assign wire_nii1O_dataout = (rtxbitslip_en === 1'b1) ? wire_niil1O_o : wire_nilil_o; and(wire_niii_dataout, wire_nlil_dataout, ~(nii1Ol)); assign wire_niiii_dataout = (rtxbitslip_en === 1'b1) ? wire_niilii_o : wire_nillO_o; assign wire_niiil_dataout = (rtxbitslip_en === 1'b1) ? wire_niilil_o : wire_nilOi_o; assign wire_niiiO_dataout = (rtxbitslip_en === 1'b1) ? wire_niiliO_o : wire_nilOl_o; and(wire_niil_dataout, wire_nliO_dataout, ~(nii1Ol)); assign wire_niili_dataout = (rtxbitslip_en === 1'b1) ? wire_niilli_o : wire_nilOO_o; assign wire_niill_dataout = (rtxbitslip_en === 1'b1) ? wire_niilll_o : wire_niO1i_o; assign wire_niilO_dataout = (rtxbitslip_en === 1'b1) ? wire_niillO_o : wire_niO1l_o; and(wire_niiO_dataout, wire_nlli_dataout, ~(nii1Ol)); assign wire_niiOi_dataout = (rtxbitslip_en === 1'b1) ? wire_niilOi_o : wire_niO1O_o; assign wire_niiOl_dataout = (rtxbitslip_en === 1'b1) ? wire_niilOl_o : wire_niO0i_o; assign wire_niiOO_dataout = (rtxbitslip_en === 1'b1) ? wire_niilOO_o : wire_niO0l_o; assign wire_nil_dataout = (cascaded_8b10b_en === 1'b1) ? tx_ctl_tc[0] : wire_nli_dataout; and(wire_nil00l_dataout, wire_nilOO_o, ~(ni01il)); and(wire_nil00O_dataout, wire_niO1i_o, ~(ni01il)); assign wire_nil0i_dataout = (rtxbitslip_en === 1'b1) ? wire_niiO0i_o : wire_niOiO_o; assign wire_nil0l_dataout = (rtxbitslip_en === 1'b1) ? wire_niiO0l_o : wire_niOli_o; assign wire_nil0O_dataout = (rtxbitslip_en === 1'b1) ? wire_niiO0O_o : wire_niOll_o; and(wire_nil0OO_dataout, wire_niOli_o, ~(ni01il)); assign wire_nil1i_dataout = (rtxbitslip_en === 1'b1) ? wire_niiO1i_o : wire_niO0O_o; assign wire_nil1l_dataout = (rtxbitslip_en === 1'b1) ? wire_niiO1l_o : wire_niOii_o; assign wire_nil1O_dataout = (rtxbitslip_en === 1'b1) ? wire_niiO1O_o : wire_niOil_o; or(wire_nili_dataout, wire_nlOii_dataout, nii1iO); and(wire_nili1i_dataout, wire_niOll_o, ~(ni01il)); and(wire_niliOl_dataout, wire_niO1l_o, ni01iO); and(wire_niliOO_dataout, wire_niO1O_o, ni01iO); and(wire_nill_dataout, wire_nlOil_dataout, ~(nii1iO)); and(wire_nill0i_dataout, wire_niOii_o, ni01iO); and(wire_nill0l_dataout, wire_niOil_o, ni01iO); and(wire_nill0O_dataout, wire_niOiO_o, ni01iO); and(wire_nill1i_dataout, wire_niO0i_o, ni01iO); and(wire_nill1l_dataout, wire_niO0l_o, ni01iO); and(wire_nill1O_dataout, wire_niO0O_o, ni01iO); and(wire_nillii_dataout, wire_niOli_o, ni01iO); and(wire_nillil_dataout, wire_niOll_o, ni01iO); or(wire_nilO_dataout, wire_nlOiO_dataout, nii1iO); and(wire_nilO0i_dataout, wire_nilOO_o, ~(ni01li)); and(wire_nilO0l_dataout, wire_niO1i_o, ~(ni01li)); and(wire_nilO0O_dataout, wire_niO1l_o, ~(ni01li)); and(wire_nilOii_dataout, wire_niO1O_o, ~(ni01li)); and(wire_nilOil_dataout, wire_niO0i_o, ~(ni01li)); and(wire_nilOiO_dataout, wire_niO0l_o, ~(ni01li)); and(wire_nilOli_dataout, wire_niO0O_o, ~(ni01li)); and(wire_nilOll_dataout, wire_niOii_o, ~(ni01li)); and(wire_nilOlO_dataout, wire_niOil_o, ~(ni01li)); and(wire_nilOOi_dataout, wire_niOiO_o, ~(ni01li)); and(wire_nilOOl_dataout, wire_niOli_o, ~(ni01li)); and(wire_nilOOO_dataout, wire_niOll_o, ~(ni01li)); assign wire_niO_dataout = (cascaded_8b10b_en === 1'b1) ? tx_ctl_tc[1] : wire_nll_dataout; and(wire_niOi_dataout, wire_nlOli_dataout, ~(nii1iO)); and(wire_niOl_dataout, wire_nlOll_dataout, ~(nii1iO)); assign wire_niOlOi_dataout = (((ni00il | ((wire_nl1iii_dataout | ni00ll) | ni00li)) | ni001i) === 1'b1) ? (~ wire_n0O1l_dataout) : wire_n0O1l_dataout; and(wire_niOO_dataout, wire_nlOlO_dataout, ~(nii1iO)); assign wire_niOOOi_dataout = (ni01OO === 1'b1) ? (~ wire_n1il_dataout) : wire_n1il_dataout; assign wire_niOOOl_dataout = (ni01OO === 1'b1) ? (~ wire_nl1i0O_dataout) : wire_nl1i0O_dataout; assign wire_niOOOO_dataout = (ni01OO === 1'b1) ? (~ wire_nl10OO_dataout) : wire_nl10OO_dataout; assign wire_nl000i_dataout = (ni0i0i === 1'b1) ? (~ wire_n1OO_dataout) : wire_n1OO_dataout; assign wire_nl000l_dataout = (ni0i0i === 1'b1) ? (~ wire_nl01iO_dataout) : wire_nl01iO_dataout; and(wire_nl001i_dataout, wire_n1Oi_dataout, ~(ni0i1O)); assign wire_nl001l_dataout = (ni0i0i === 1'b1) ? (~ wire_nl001i_dataout) : wire_nl001i_dataout; assign wire_nl001O_dataout = (ni0i0i === 1'b1) ? (~ wire_nl01Ol_dataout) : wire_nl01Ol_dataout; assign wire_nl00ll_dataout = (r8b10b_enc_ibm_en === 1'b1) ? ni0iii : wire_nil_dataout; assign wire_nl010O_dataout = ((ni0i1i | (wire_n1OO_dataout & ni0i0O)) === 1'b1) ? (~ wire_niOlOi_dataout) : wire_niOlOi_dataout; or(wire_nl01iO_dataout, wire_nl01li_dataout, ni0i1O); and(wire_nl01li_dataout, (~ ni0i0O), ~(wire_n1OO_dataout)); assign wire_nl01Ol_dataout = (ni0i1i === 1'b1) ? (~ wire_n1Ol_dataout) : wire_n1Ol_dataout; and(wire_nl0i_dataout, wire_n11i_dataout, ~(nii1iO)); and(wire_nl0l_dataout, wire_n11l_dataout, ~(nii1iO)); and(wire_nl0O_dataout, wire_n11O_dataout, ~(nii1iO)); assign wire_nl10Ol_dataout = (ni00li === 1'b1) ? (~ wire_n1ll_dataout) : wire_n1ll_dataout; assign wire_nl10OO_dataout = (((wire_n1lO_dataout & (wire_n1ll_dataout & ((~ wire_n1li_dataout) & ((~ wire_n1iO_dataout) & (~ wire_n1il_dataout))))) | ni00ll) === 1'b1) ? (~ wire_n1li_dataout) : wire_n1li_dataout; assign wire_nl111i_dataout = (ni01OO === 1'b1) ? (~ wire_nl10Ol_dataout) : wire_nl10Ol_dataout; assign wire_nl111l_dataout = (ni01OO === 1'b1) ? (~ ni000O) : ni000O; assign wire_nl111O_dataout = (ni01OO === 1'b1) ? (~ ni001O) : ni001O; or(wire_nl1i_dataout, wire_nlOOi_dataout, nii1iO); assign wire_nl1i0O_dataout = (ni00lO === 1'b1) ? (~ wire_n1iO_dataout) : wire_n1iO_dataout; assign wire_nl1iii_dataout = (r8b10b_enc_ibm_en === 1'b1) ? ni0iii : wire_nil_dataout; or(wire_nl1l_dataout, wire_nlOOl_dataout, nii1iO); and(wire_nl1O_dataout, wire_nlOOO_dataout, ~(nii1iO)); and(wire_nli_dataout, wire_n0O_dataout, ~(nii00O)); assign wire_nli0il_dataout = (ni0ilO === 1'b1) ? (~ wire_n01i_dataout) : wire_n01i_dataout; assign wire_nli0iO_dataout = (ni0ilO === 1'b1) ? (~ wire_nliO1i_dataout) : wire_nliO1i_dataout; assign wire_nli0li_dataout = (ni0ilO === 1'b1) ? (~ wire_nlilli_dataout) : wire_nlilli_dataout; assign wire_nli0ll_dataout = (ni0ilO === 1'b1) ? (~ wire_nliliO_dataout) : wire_nliliO_dataout; assign wire_nli0lO_dataout = (ni0ilO === 1'b1) ? (~ ni0l1O) : ni0l1O; assign wire_nli0Oi_dataout = (ni0ilO === 1'b1) ? (~ ni0iOO) : ni0iOO; assign wire_nli1il_dataout = (((ni0l0l | ((wire_nliO1l_dataout | ni0lil) | ni0lii)) | ni0iOi) === 1'b1) ? (~ wire_n0O1O_dataout) : wire_n0O1O_dataout; and(wire_nlii_dataout, wire_n10i_dataout, ~(nii1iO)); and(wire_nlil_dataout, wire_n10l_dataout, ~(nii1iO)); assign wire_nliliO_dataout = (ni0lii === 1'b1) ? (~ wire_n00i_dataout) : wire_n00i_dataout; assign wire_nlilli_dataout = (((wire_n00l_dataout & (wire_n00i_dataout & ((~ wire_n01O_dataout) & ((~ wire_n01l_dataout) & (~ wire_n01i_dataout))))) | ni0lil) === 1'b1) ? (~ wire_n01O_dataout) : wire_n01O_dataout; and(wire_nliO_dataout, wire_n10O_dataout, ~(nii1iO)); assign wire_nliO1i_dataout = (ni0liO === 1'b1) ? (~ wire_n01l_dataout) : wire_n01l_dataout; assign wire_nliO1l_dataout = (r8b10b_enc_ibm_en === 1'b1) ? ni0O0i : wire_niO_dataout; and(wire_nll_dataout, wire_nii_dataout, ~(nii00O)); and(wire_nlli_dataout, wire_n1ii_dataout, ~(nii1iO)); or(wire_nlli0i_dataout, wire_nlli0l_dataout, ni0lOO); and(wire_nlli0l_dataout, (~ ni0O1O), ~(wire_n0il_dataout)); assign wire_nlli1i_dataout = ((ni0lOi | (wire_n0il_dataout & ni0O1O)) === 1'b1) ? (~ wire_nli1il_dataout) : wire_nli1il_dataout; assign wire_nlliiO_dataout = (ni0lOi === 1'b1) ? (~ wire_n0ii_dataout) : wire_n0ii_dataout; and(wire_nllill_dataout, wire_n00O_dataout, ~(ni0lOO)); assign wire_nllilO_dataout = (ni0O1i === 1'b1) ? (~ wire_nllill_dataout) : wire_nllill_dataout; assign wire_nlliOi_dataout = (ni0O1i === 1'b1) ? (~ wire_nlliiO_dataout) : wire_nlliiO_dataout; assign wire_nlliOl_dataout = (ni0O1i === 1'b1) ? (~ wire_n0il_dataout) : wire_n0il_dataout; assign wire_nlliOO_dataout = (ni0O1i === 1'b1) ? (~ wire_nlli0i_dataout) : wire_nlli0i_dataout; assign wire_nlll0O_dataout = (r8b10b_enc_ibm_en === 1'b1) ? ni0O0i : wire_niO_dataout; assign wire_nlOii_dataout = (rendec_data_sel_tx === 1'b1) ? tx_data_tc[0] : tx_data_ts[0]; assign wire_nlOil_dataout = (rendec_data_sel_tx === 1'b1) ? tx_data_tc[1] : tx_data_ts[1]; assign wire_nlOiO_dataout = (rendec_data_sel_tx === 1'b1) ? tx_data_tc[2] : tx_data_ts[2]; assign wire_nlOli_dataout = (rendec_data_sel_tx === 1'b1) ? tx_data_tc[3] : tx_data_ts[3]; assign wire_nlOll_dataout = (rendec_data_sel_tx === 1'b1) ? tx_data_tc[4] : tx_data_ts[4]; assign wire_nlOlO_dataout = (rendec_data_sel_tx === 1'b1) ? tx_data_tc[5] : tx_data_ts[5]; assign wire_nlOOi_dataout = (rendec_data_sel_tx === 1'b1) ? tx_data_tc[6] : tx_data_ts[6]; assign wire_nlOOl_dataout = (rendec_data_sel_tx === 1'b1) ? tx_data_tc[7] : tx_data_ts[7]; and(wire_nlOOO_dataout, tx_data_tc[8], rendec_data_sel_tx); oper_decoder nili1O ( .i({tx_boundary_sel[4:0]}), .o(wire_nili1O_o)); defparam nili1O.width_i = 5, nili1O.width_o = 32; oper_decoder nillli ( .i({tx_boundary_sel[3:0]}), .o(wire_nillli_o)); defparam nillli.width_i = 4, nillli.width_o = 16; oper_mux n010i ( .data({{4{tx_data_pg[17]}}, rev_loop_data[17], wire_nlliOi_dataout, tx_data_pg[17], wire_nlliOi_dataout, {4{tx_data_pg[17]}}, rev_loop_data[17], tx_data_tc[15], tx_data_pg[17], tx_data_tc[15]}), .o(wire_n010i_o), .sel({endec, prbs_en, rrev_loopbk, ni1li})); defparam n010i.width_data = 16, n010i.width_sel = 4; oper_mux n010l ( .data({{4{tx_data_pg[18]}}, rev_loop_data[18], wire_nlliOl_dataout, tx_data_pg[18], wire_nlliOl_dataout, {4{tx_data_pg[18]}}, rev_loop_data[18], tx_ctl_tc[1], tx_data_pg[18], tx_ctl_tc[1]}), .o(wire_n010l_o), .sel({endec, prbs_en, rrev_loopbk, ni1li})); defparam n010l.width_data = 16, n010l.width_sel = 4; oper_mux n010O ( .data({{4{tx_data_pg[19]}}, rev_loop_data[19], wire_nlliOO_dataout, tx_data_pg[19], wire_nlliOO_dataout, {4{tx_data_pg[19]}}, rev_loop_data[19], tx_data_9_tc[1], tx_data_pg[19], tx_data_9_tc[1]}), .o(wire_n010O_o), .sel({endec, prbs_en, rrev_loopbk, ni1li})); defparam n010O.width_data = 16, n010O.width_sel = 4; oper_mux n011i ( .data({{4{tx_data_pg[14]}}, rev_loop_data[14], wire_nli0lO_dataout, tx_data_pg[14], wire_nli0lO_dataout, {4{tx_data_pg[14]}}, rev_loop_data[14], tx_data_tc[12], tx_data_pg[14], tx_data_tc[12]}), .o(wire_n011i_o), .sel({endec, prbs_en, rrev_loopbk, ni1li})); defparam n011i.width_data = 16, n011i.width_sel = 4; oper_mux n011l ( .data({{4{tx_data_pg[15]}}, rev_loop_data[15], wire_nli0Oi_dataout, tx_data_pg[15], wire_nli0Oi_dataout, {4{tx_data_pg[15]}}, rev_loop_data[15], tx_data_tc[13], tx_data_pg[15], tx_data_tc[13]}), .o(wire_n011l_o), .sel({endec, prbs_en, rrev_loopbk, ni1li})); defparam n011l.width_data = 16, n011l.width_sel = 4; oper_mux n011O ( .data({{4{tx_data_pg[16]}}, rev_loop_data[16], wire_nllilO_dataout, tx_data_pg[16], wire_nllilO_dataout, {4{tx_data_pg[16]}}, rev_loop_data[16], tx_data_tc[14], tx_data_pg[16], tx_data_tc[14]}), .o(wire_n011O_o), .sel({endec, prbs_en, rrev_loopbk, ni1li})); defparam n011O.width_data = 16, n011O.width_sel = 4; oper_mux n1O0i ( .data({{4{tx_data_pg[2]}}, rev_loop_data[2], wire_niOOOO_dataout, tx_data_pg[2], wire_niOOOO_dataout, {4{tx_data_pg[2]}}, rev_loop_data[2], tx_data_tc[2], tx_data_pg[2], tx_data_tc[2]}), .o(wire_n1O0i_o), .sel({endec, prbs_en, rrev_loopbk, ni1li})); defparam n1O0i.width_data = 16, n1O0i.width_sel = 4; oper_mux n1O0l ( .data({{4{tx_data_pg[3]}}, rev_loop_data[3], wire_nl111i_dataout, tx_data_pg[3], wire_nl111i_dataout, {4{tx_data_pg[3]}}, rev_loop_data[3], tx_data_tc[3], tx_data_pg[3], tx_data_tc[3]}), .o(wire_n1O0l_o), .sel({endec, prbs_en, rrev_loopbk, ni1li})); defparam n1O0l.width_data = 16, n1O0l.width_sel = 4; oper_mux n1O0O ( .data({{4{tx_data_pg[4]}}, rev_loop_data[4], wire_nl111l_dataout, tx_data_pg[4], wire_nl111l_dataout, {4{tx_data_pg[4]}}, rev_loop_data[4], tx_data_tc[4], tx_data_pg[4], tx_data_tc[4]}), .o(wire_n1O0O_o), .sel({endec, prbs_en, rrev_loopbk, ni1li})); defparam n1O0O.width_data = 16, n1O0O.width_sel = 4; oper_mux n1O1l ( .data({{4{tx_data_pg[0]}}, rev_loop_data[0], wire_niOOOi_dataout, tx_data_pg[0], wire_niOOOi_dataout, {4{tx_data_pg[0]}}, rev_loop_data[0], tx_data_tc[0], tx_data_pg[0], tx_data_tc[0]}), .o(wire_n1O1l_o), .sel({endec, prbs_en, rrev_loopbk, ni1li})); defparam n1O1l.width_data = 16, n1O1l.width_sel = 4; oper_mux n1O1O ( .data({{4{tx_data_pg[1]}}, rev_loop_data[1], wire_niOOOl_dataout, tx_data_pg[1], wire_niOOOl_dataout, {4{tx_data_pg[1]}}, rev_loop_data[1], tx_data_tc[1], tx_data_pg[1], tx_data_tc[1]}), .o(wire_n1O1O_o), .sel({endec, prbs_en, rrev_loopbk, ni1li})); defparam n1O1O.width_data = 16, n1O1O.width_sel = 4; oper_mux n1Oii ( .data({{4{tx_data_pg[5]}}, rev_loop_data[5], wire_nl111O_dataout, tx_data_pg[5], wire_nl111O_dataout, {4{tx_data_pg[5]}}, rev_loop_data[5], tx_data_tc[5], tx_data_pg[5], tx_data_tc[5]}), .o(wire_n1Oii_o), .sel({endec, prbs_en, rrev_loopbk, ni1li})); defparam n1Oii.width_data = 16, n1Oii.width_sel = 4; oper_mux n1Oil ( .data({{4{tx_data_pg[6]}}, rev_loop_data[6], wire_nl001l_dataout, tx_data_pg[6], wire_nl001l_dataout, {4{tx_data_pg[6]}}, rev_loop_data[6], tx_data_tc[6], tx_data_pg[6], tx_data_tc[6]}), .o(wire_n1Oil_o), .sel({endec, prbs_en, rrev_loopbk, ni1li})); defparam n1Oil.width_data = 16, n1Oil.width_sel = 4; oper_mux n1OiO ( .data({{4{tx_data_pg[7]}}, rev_loop_data[7], wire_nl001O_dataout, tx_data_pg[7], wire_nl001O_dataout, {4{tx_data_pg[7]}}, rev_loop_data[7], tx_data_tc[7], tx_data_pg[7], tx_data_tc[7]}), .o(wire_n1OiO_o), .sel({endec, prbs_en, rrev_loopbk, ni1li})); defparam n1OiO.width_data = 16, n1OiO.width_sel = 4; oper_mux n1Oli ( .data({{4{tx_data_pg[8]}}, rev_loop_data[8], wire_nl000i_dataout, tx_data_pg[8], wire_nl000i_dataout, {4{tx_data_pg[8]}}, rev_loop_data[8], tx_ctl_tc[1], tx_data_pg[8], tx_ctl_tc[0]}), .o(wire_n1Oli_o), .sel({endec, prbs_en, rrev_loopbk, ni1li})); defparam n1Oli.width_data = 16, n1Oli.width_sel = 4; oper_mux n1Oll ( .data({{4{tx_data_pg[9]}}, rev_loop_data[9], wire_nl000l_dataout, tx_data_pg[9], wire_nl000l_dataout, {4{tx_data_pg[9]}}, rev_loop_data[9], tx_data_9_tc[0], tx_data_pg[9], tx_data_9_tc[0]}), .o(wire_n1Oll_o), .sel({endec, prbs_en, rrev_loopbk, ni1li})); defparam n1Oll.width_data = 16, n1Oll.width_sel = 4; oper_mux n1OlO ( .data({{4{tx_data_pg[10]}}, rev_loop_data[10], wire_nli0il_dataout, tx_data_pg[10], wire_nli0il_dataout, {4{tx_data_pg[10]}}, rev_loop_data[10], tx_data_tc[8], tx_data_pg[10], tx_data_tc[8]}), .o(wire_n1OlO_o), .sel({endec, prbs_en, rrev_loopbk, ni1li})); defparam n1OlO.width_data = 16, n1OlO.width_sel = 4; oper_mux n1OOi ( .data({{4{tx_data_pg[11]}}, rev_loop_data[11], wire_nli0iO_dataout, tx_data_pg[11], wire_nli0iO_dataout, {4{tx_data_pg[11]}}, rev_loop_data[11], tx_data_tc[9], tx_data_pg[11], tx_data_tc[9]}), .o(wire_n1OOi_o), .sel({endec, prbs_en, rrev_loopbk, ni1li})); defparam n1OOi.width_data = 16, n1OOi.width_sel = 4; oper_mux n1OOl ( .data({{4{tx_data_pg[12]}}, rev_loop_data[12], wire_nli0li_dataout, tx_data_pg[12], wire_nli0li_dataout, {4{tx_data_pg[12]}}, rev_loop_data[12], tx_data_tc[10], tx_data_pg[12], tx_data_tc[10]}), .o(wire_n1OOl_o), .sel({endec, prbs_en, rrev_loopbk, ni1li})); defparam n1OOl.width_data = 16, n1OOl.width_sel = 4; oper_mux n1OOO ( .data({{4{tx_data_pg[13]}}, rev_loop_data[13], wire_nli0ll_dataout, tx_data_pg[13], wire_nli0ll_dataout, {4{tx_data_pg[13]}}, rev_loop_data[13], tx_data_tc[11], tx_data_pg[13], tx_data_tc[11]}), .o(wire_n1OOO_o), .sel({endec, prbs_en, rrev_loopbk, ni1li})); defparam n1OOO.width_data = 16, n1OOO.width_sel = 4; oper_mux niil0i ( .data({wire_niiOiO_o, wire_nil1Ol_o, wire_nili0O_o, wire_nillOi_o}), .o(wire_niil0i_o), .sel({doublewidth, dwidth})); defparam niil0i.width_data = 4, niil0i.width_sel = 2; oper_mux niil0l ( .data({wire_niiOli_o, wire_nil1OO_o, wire_niliii_o, wire_nillOl_o}), .o(wire_niil0l_o), .sel({doublewidth, dwidth})); defparam niil0l.width_data = 4, niil0l.width_sel = 2; oper_mux niil0O ( .data({wire_niiOll_o, wire_nil01i_o, wire_niliil_o, wire_nillOO_o}), .o(wire_niil0O_o), .sel({doublewidth, dwidth})); defparam niil0O.width_data = 4, niil0O.width_sel = 2; oper_mux niil1l ( .data({wire_niiOii_o, wire_nil1lO_o, wire_nili0i_o, wire_nillll_o}), .o(wire_niil1l_o), .sel({doublewidth, dwidth})); defparam niil1l.width_data = 4, niil1l.width_sel = 2; oper_mux niil1O ( .data({wire_niiOil_o, wire_nil1Oi_o, wire_nili0l_o, wire_nilllO_o}), .o(wire_niil1O_o), .sel({doublewidth, dwidth})); defparam niil1O.width_data = 4, niil1O.width_sel = 2; oper_mux niilii ( .data({wire_niiOlO_o, wire_nil01l_o, wire_niliiO_o, wire_nilO1i_o}), .o(wire_niilii_o), .sel({doublewidth, dwidth})); defparam niilii.width_data = 4, niilii.width_sel = 2; oper_mux niilil ( .data({wire_niiOOi_o, wire_nil01O_o, wire_nilili_o, wire_nilO1l_o}), .o(wire_niilil_o), .sel({doublewidth, dwidth})); defparam niilil.width_data = 4, niilil.width_sel = 2; oper_mux niiliO ( .data({wire_niiOOl_o, wire_nil00i_o, wire_nilill_o, wire_nilO1O_o}), .o(wire_niiliO_o), .sel({doublewidth, dwidth})); defparam niiliO.width_data = 4, niiliO.width_sel = 2; oper_mux niilli ( .data({wire_niiOOO_o, wire_nil00l_dataout, wire_nililO_o, wire_nilO0i_dataout}), .o(wire_niilli_o), .sel({doublewidth, dwidth})); defparam niilli.width_data = 4, niilli.width_sel = 2; oper_mux niilll ( .data({wire_nil11i_o, wire_nil00O_dataout, wire_niliOi_o, wire_nilO0l_dataout}), .o(wire_niilll_o), .sel({doublewidth, dwidth})); defparam niilll.width_data = 4, niilll.width_sel = 2; oper_mux niillO ( .data({wire_nil11l_o, wire_nil0ii_o, wire_niliOl_dataout, wire_nilO0O_dataout}), .o(wire_niillO_o), .sel({doublewidth, dwidth})); defparam niillO.width_data = 4, niillO.width_sel = 2; oper_mux niilOi ( .data({wire_nil11O_o, wire_nil0il_o, wire_niliOO_dataout, wire_nilOii_dataout}), .o(wire_niilOi_o), .sel({doublewidth, dwidth})); defparam niilOi.width_data = 4, niilOi.width_sel = 2; oper_mux niilOl ( .data({wire_nil10i_o, wire_nil0iO_o, wire_nill1i_dataout, wire_nilOil_dataout}), .o(wire_niilOl_o), .sel({doublewidth, dwidth})); defparam niilOl.width_data = 4, niilOl.width_sel = 2; oper_mux niilOO ( .data({wire_nil10l_o, wire_nil0li_o, wire_nill1l_dataout, wire_nilOiO_dataout}), .o(wire_niilOO_o), .sel({doublewidth, dwidth})); defparam niilOO.width_data = 4, niilOO.width_sel = 2; oper_mux niiO0i ( .data({wire_nil1iO_o, wire_nil0Ol_o, wire_nill0O_dataout, wire_nilOOi_dataout}), .o(wire_niiO0i_o), .sel({doublewidth, dwidth})); defparam niiO0i.width_data = 4, niiO0i.width_sel = 2; oper_mux niiO0l ( .data({wire_nil1li_o, wire_nil0OO_dataout, wire_nillii_dataout, wire_nilOOl_dataout}), .o(wire_niiO0l_o), .sel({doublewidth, dwidth})); defparam niiO0l.width_data = 4, niiO0l.width_sel = 2; oper_mux niiO0O ( .data({wire_nil1ll_o, wire_nili1i_dataout, wire_nillil_dataout, wire_nilOOO_dataout}), .o(wire_niiO0O_o), .sel({doublewidth, dwidth})); defparam niiO0O.width_data = 4, niiO0O.width_sel = 2; oper_mux niiO1i ( .data({wire_nil10O_o, wire_nil0ll_o, wire_nill1O_dataout, wire_nilOli_dataout}), .o(wire_niiO1i_o), .sel({doublewidth, dwidth})); defparam niiO1i.width_data = 4, niiO1i.width_sel = 2; oper_mux niiO1l ( .data({wire_nil1ii_o, wire_nil0lO_o, wire_nill0i_dataout, wire_nilOll_dataout}), .o(wire_niiO1l_o), .sel({doublewidth, dwidth})); defparam niiO1l.width_data = 4, niiO1l.width_sel = 2; oper_mux niiO1O ( .data({wire_nil1il_o, wire_nil0Oi_o, wire_nill0l_dataout, wire_nilOlO_dataout}), .o(wire_niiO1O_o), .sel({doublewidth, dwidth})); defparam niiO1O.width_data = 4, niiO1O.width_sel = 2; oper_mux niiOii ( .data({{12{wire_nilii_o}}, niil1i, nii0Oi, nii0Ol, nii0OO, niii1i, niii1l, niii1O, niii0i, niii0l, niii0O, niiiii, niiiil, niiiiO, niiili, niiill, niiilO, niiiOi, niiiOl, niiiOO, wire_nilii_o}), .o(wire_niiOii_o), .sel({tx_boundary_sel[4:0]})); defparam niiOii.width_data = 32, niiOii.width_sel = 5; oper_mux niiOil ( .data({{12{wire_nilil_o}}, nii0Oi, nii0Ol, nii0OO, niii1i, niii1l, niii1O, niii0i, niii0l, niii0O, niiiii, niiiil, niiiiO, niiili, niiill, niiilO, niiiOi, niiiOl, niiiOO, wire_nilii_o, wire_nilil_o}), .o(wire_niiOil_o), .sel({tx_boundary_sel[4:0]})); defparam niiOil.width_data = 32, niiOil.width_sel = 5; oper_mux niiOiO ( .data({{12{wire_niliO_o}}, nii0Ol, nii0OO, niii1i, niii1l, niii1O, niii0i, niii0l, niii0O, niiiii, niiiil, niiiiO, niiili, niiill, niiilO, niiiOi, niiiOl, niiiOO, wire_nilii_o, wire_nilil_o, wire_niliO_o}), .o(wire_niiOiO_o), .sel({tx_boundary_sel[4:0]})); defparam niiOiO.width_data = 32, niiOiO.width_sel = 5; oper_mux niiOli ( .data({{12{wire_nilli_o}}, nii0OO, niii1i, niii1l, niii1O, niii0i, niii0l, niii0O, niiiii, niiiil, niiiiO, niiili, niiill, niiilO, niiiOi, niiiOl, niiiOO, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o}), .o(wire_niiOli_o), .sel({tx_boundary_sel[4:0]})); defparam niiOli.width_data = 32, niiOli.width_sel = 5; oper_mux niiOll ( .data({{12{wire_nilll_o}}, niii1i, niii1l, niii1O, niii0i, niii0l, niii0O, niiiii, niiiil, niiiiO, niiili, niiill, niiilO, niiiOi, niiiOl, niiiOO, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o}), .o(wire_niiOll_o), .sel({tx_boundary_sel[4:0]})); defparam niiOll.width_data = 32, niiOll.width_sel = 5; oper_mux niiOlO ( .data({{12{wire_nillO_o}}, niii1l, niii1O, niii0i, niii0l, niii0O, niiiii, niiiil, niiiiO, niiili, niiill, niiilO, niiiOi, niiiOl, niiiOO, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o}), .o(wire_niiOlO_o), .sel({tx_boundary_sel[4:0]})); defparam niiOlO.width_data = 32, niiOlO.width_sel = 5; oper_mux niiOOi ( .data({{12{wire_nilOi_o}}, niii1O, niii0i, niii0l, niii0O, niiiii, niiiil, niiiiO, niiili, niiill, niiilO, niiiOi, niiiOl, niiiOO, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o}), .o(wire_niiOOi_o), .sel({tx_boundary_sel[4:0]})); defparam niiOOi.width_data = 32, niiOOi.width_sel = 5; oper_mux niiOOl ( .data({{12{wire_nilOl_o}}, niii0i, niii0l, niii0O, niiiii, niiiil, niiiiO, niiili, niiill, niiilO, niiiOi, niiiOl, niiiOO, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o, wire_nilOl_o}), .o(wire_niiOOl_o), .sel({tx_boundary_sel[4:0]})); defparam niiOOl.width_data = 32, niiOOl.width_sel = 5; oper_mux niiOOO ( .data({{12{wire_nilOO_o}}, niii0l, niii0O, niiiii, niiiil, niiiiO, niiili, niiill, niiilO, niiiOi, niiiOl, niiiOO, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o, wire_nilOl_o, wire_nilOO_o}), .o(wire_niiOOO_o), .sel({tx_boundary_sel[4:0]})); defparam niiOOO.width_data = 32, niiOOO.width_sel = 5; oper_mux nil00i ( .data({{16{wire_nilOl_o}}, niii0O, niiiii, niiiil, niiiiO, niiili, niiill, niiilO, niiiOi, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o, wire_nilOl_o}), .o(wire_nil00i_o), .sel({tx_boundary_sel[4:0]})); defparam nil00i.width_data = 32, nil00i.width_sel = 5; oper_mux nil01i ( .data({{16{wire_nilll_o}}, niii1i, niii1l, niii1O, niii0O, niiiii, niiiil, niiiiO, niiili, niiill, niiilO, niiiOi, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o}), .o(wire_nil01i_o), .sel({tx_boundary_sel[4:0]})); defparam nil01i.width_data = 32, nil01i.width_sel = 5; oper_mux nil01l ( .data({{16{wire_nillO_o}}, niii1l, niii1O, niii0O, niiiii, niiiil, niiiiO, niiili, niiill, niiilO, niiiOi, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o}), .o(wire_nil01l_o), .sel({tx_boundary_sel[4:0]})); defparam nil01l.width_data = 32, nil01l.width_sel = 5; oper_mux nil01O ( .data({{16{wire_nilOi_o}}, niii1O, niii0O, niiiii, niiiil, niiiiO, niiili, niiill, niiilO, niiiOi, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o}), .o(wire_nil01O_o), .sel({tx_boundary_sel[4:0]})); defparam nil01O.width_data = 32, nil01O.width_sel = 5; oper_mux nil0ii ( .data({{16{wire_niO1l_o}}, niiiii, niiiil, niiiiO, niiili, niiill, niiilO, niiiOi, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o, wire_nilOl_o, wire_niO1l_o}), .o(wire_nil0ii_o), .sel({tx_boundary_sel[4:0]})); defparam nil0ii.width_data = 32, nil0ii.width_sel = 5; oper_mux nil0il ( .data({{16{wire_niO1O_o}}, niiiil, niiiiO, niiili, niiill, niiilO, niiiOi, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o, wire_nilOl_o, wire_niO1l_o, wire_niO1O_o}), .o(wire_nil0il_o), .sel({tx_boundary_sel[4:0]})); defparam nil0il.width_data = 32, nil0il.width_sel = 5; oper_mux nil0iO ( .data({{16{wire_niO0i_o}}, niiiiO, niiili, niiill, niiilO, niiiOi, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o, wire_nilOl_o, wire_niO1l_o, wire_niO1O_o, wire_niO0i_o}), .o(wire_nil0iO_o), .sel({tx_boundary_sel[4:0]})); defparam nil0iO.width_data = 32, nil0iO.width_sel = 5; oper_mux nil0li ( .data({{16{wire_niO0l_o}}, niiili, niiill, niiilO, niiiOi, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o, wire_nilOl_o, wire_niO1l_o, wire_niO1O_o, wire_niO0i_o, wire_niO0l_o}), .o(wire_nil0li_o), .sel({tx_boundary_sel[4:0]})); defparam nil0li.width_data = 32, nil0li.width_sel = 5; oper_mux nil0ll ( .data({{16{wire_niO0O_o}}, niiill, niiilO, niiiOi, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o, wire_nilOl_o, wire_niO1l_o, wire_niO1O_o, wire_niO0i_o, wire_niO0l_o, wire_niO0O_o}), .o(wire_nil0ll_o), .sel({tx_boundary_sel[4:0]})); defparam nil0ll.width_data = 32, nil0ll.width_sel = 5; oper_mux nil0lO ( .data({{16{wire_niOii_o}}, niiilO, niiiOi, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o, wire_nilOl_o, wire_niO1l_o, wire_niO1O_o, wire_niO0i_o, wire_niO0l_o, wire_niO0O_o, wire_niOii_o}), .o(wire_nil0lO_o), .sel({tx_boundary_sel[4:0]})); defparam nil0lO.width_data = 32, nil0lO.width_sel = 5; oper_mux nil0Oi ( .data({{16{wire_niOil_o}}, niiiOi, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o, wire_nilOl_o, wire_niO1l_o, wire_niO1O_o, wire_niO0i_o, wire_niO0l_o, wire_niO0O_o, wire_niOii_o, wire_niOil_o}), .o(wire_nil0Oi_o), .sel({tx_boundary_sel[4:0]})); defparam nil0Oi.width_data = 32, nil0Oi.width_sel = 5; oper_mux nil0Ol ( .data({{16{wire_niOiO_o}}, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o, wire_nilOl_o, wire_niO1l_o, wire_niO1O_o, wire_niO0i_o, wire_niO0l_o, wire_niO0O_o, wire_niOii_o, wire_niOil_o, wire_niOiO_o}), .o(wire_nil0Ol_o), .sel({tx_boundary_sel[4:0]})); defparam nil0Ol.width_data = 32, nil0Ol.width_sel = 5; oper_mux nil10i ( .data({{12{wire_niO0i_o}}, niiiiO, niiili, niiill, niiilO, niiiOi, niiiOl, niiiOO, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o, wire_nilOl_o, wire_nilOO_o, wire_niO1i_o, wire_niO1l_o, wire_niO1O_o, wire_niO0i_o}), .o(wire_nil10i_o), .sel({tx_boundary_sel[4:0]})); defparam nil10i.width_data = 32, nil10i.width_sel = 5; oper_mux nil10l ( .data({{12{wire_niO0l_o}}, niiili, niiill, niiilO, niiiOi, niiiOl, niiiOO, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o, wire_nilOl_o, wire_nilOO_o, wire_niO1i_o, wire_niO1l_o, wire_niO1O_o, wire_niO0i_o, wire_niO0l_o}), .o(wire_nil10l_o), .sel({tx_boundary_sel[4:0]})); defparam nil10l.width_data = 32, nil10l.width_sel = 5; oper_mux nil10O ( .data({{12{wire_niO0O_o}}, niiill, niiilO, niiiOi, niiiOl, niiiOO, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o, wire_nilOl_o, wire_nilOO_o, wire_niO1i_o, wire_niO1l_o, wire_niO1O_o, wire_niO0i_o, wire_niO0l_o, wire_niO0O_o}), .o(wire_nil10O_o), .sel({tx_boundary_sel[4:0]})); defparam nil10O.width_data = 32, nil10O.width_sel = 5; oper_mux nil11i ( .data({{12{wire_niO1i_o}}, niii0O, niiiii, niiiil, niiiiO, niiili, niiill, niiilO, niiiOi, niiiOl, niiiOO, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o, wire_nilOl_o, wire_nilOO_o, wire_niO1i_o}), .o(wire_nil11i_o), .sel({tx_boundary_sel[4:0]})); defparam nil11i.width_data = 32, nil11i.width_sel = 5; oper_mux nil11l ( .data({{12{wire_niO1l_o}}, niiiii, niiiil, niiiiO, niiili, niiill, niiilO, niiiOi, niiiOl, niiiOO, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o, wire_nilOl_o, wire_nilOO_o, wire_niO1i_o, wire_niO1l_o}), .o(wire_nil11l_o), .sel({tx_boundary_sel[4:0]})); defparam nil11l.width_data = 32, nil11l.width_sel = 5; oper_mux nil11O ( .data({{12{wire_niO1O_o}}, niiiil, niiiiO, niiili, niiill, niiilO, niiiOi, niiiOl, niiiOO, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o, wire_nilOl_o, wire_nilOO_o, wire_niO1i_o, wire_niO1l_o, wire_niO1O_o}), .o(wire_nil11O_o), .sel({tx_boundary_sel[4:0]})); defparam nil11O.width_data = 32, nil11O.width_sel = 5; oper_mux nil1ii ( .data({{12{wire_niOii_o}}, niiilO, niiiOi, niiiOl, niiiOO, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o, wire_nilOl_o, wire_nilOO_o, wire_niO1i_o, wire_niO1l_o, wire_niO1O_o, wire_niO0i_o, wire_niO0l_o, wire_niO0O_o, wire_niOii_o}), .o(wire_nil1ii_o), .sel({tx_boundary_sel[4:0]})); defparam nil1ii.width_data = 32, nil1ii.width_sel = 5; oper_mux nil1il ( .data({{12{wire_niOil_o}}, niiiOi, niiiOl, niiiOO, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o, wire_nilOl_o, wire_nilOO_o, wire_niO1i_o, wire_niO1l_o, wire_niO1O_o, wire_niO0i_o, wire_niO0l_o, wire_niO0O_o, wire_niOii_o, wire_niOil_o}), .o(wire_nil1il_o), .sel({tx_boundary_sel[4:0]})); defparam nil1il.width_data = 32, nil1il.width_sel = 5; oper_mux nil1iO ( .data({{12{wire_niOiO_o}}, niiiOl, niiiOO, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o, wire_nilOl_o, wire_nilOO_o, wire_niO1i_o, wire_niO1l_o, wire_niO1O_o, wire_niO0i_o, wire_niO0l_o, wire_niO0O_o, wire_niOii_o, wire_niOil_o, wire_niOiO_o}), .o(wire_nil1iO_o), .sel({tx_boundary_sel[4:0]})); defparam nil1iO.width_data = 32, nil1iO.width_sel = 5; oper_mux nil1li ( .data({{12{wire_niOli_o}}, niiiOO, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o, wire_nilOl_o, wire_nilOO_o, wire_niO1i_o, wire_niO1l_o, wire_niO1O_o, wire_niO0i_o, wire_niO0l_o, wire_niO0O_o, wire_niOii_o, wire_niOil_o, wire_niOiO_o, wire_niOli_o}), .o(wire_nil1li_o), .sel({tx_boundary_sel[4:0]})); defparam nil1li.width_data = 32, nil1li.width_sel = 5; oper_mux nil1ll ( .data({{12{wire_niOll_o}}, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o, wire_nilOl_o, wire_nilOO_o, wire_niO1i_o, wire_niO1l_o, wire_niO1O_o, wire_niO0i_o, wire_niO0l_o, wire_niO0O_o, wire_niOii_o, wire_niOil_o, wire_niOiO_o, wire_niOli_o, wire_niOll_o}), .o(wire_nil1ll_o), .sel({tx_boundary_sel[4:0]})); defparam nil1ll.width_data = 32, nil1ll.width_sel = 5; oper_mux nil1lO ( .data({{16{wire_nilii_o}}, niil1i, nii0Oi, nii0Ol, nii0OO, niii1i, niii1l, niii1O, niii0O, niiiii, niiiil, niiiiO, niiili, niiill, niiilO, niiiOi, wire_nilii_o}), .o(wire_nil1lO_o), .sel({tx_boundary_sel[4:0]})); defparam nil1lO.width_data = 32, nil1lO.width_sel = 5; oper_mux nil1Oi ( .data({{16{wire_nilil_o}}, nii0Oi, nii0Ol, nii0OO, niii1i, niii1l, niii1O, niii0O, niiiii, niiiil, niiiiO, niiili, niiill, niiilO, niiiOi, wire_nilii_o, wire_nilil_o}), .o(wire_nil1Oi_o), .sel({tx_boundary_sel[4:0]})); defparam nil1Oi.width_data = 32, nil1Oi.width_sel = 5; oper_mux nil1Ol ( .data({{16{wire_niliO_o}}, nii0Ol, nii0OO, niii1i, niii1l, niii1O, niii0O, niiiii, niiiil, niiiiO, niiili, niiill, niiilO, niiiOi, wire_nilii_o, wire_nilil_o, wire_niliO_o}), .o(wire_nil1Ol_o), .sel({tx_boundary_sel[4:0]})); defparam nil1Ol.width_data = 32, nil1Ol.width_sel = 5; oper_mux nil1OO ( .data({{16{wire_nilli_o}}, nii0OO, niii1i, niii1l, niii1O, niii0O, niiiii, niiiil, niiiiO, niiili, niiill, niiilO, niiiOi, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o}), .o(wire_nil1OO_o), .sel({tx_boundary_sel[4:0]})); defparam nil1OO.width_data = 32, nil1OO.width_sel = 5; oper_mux nili0i ( .data({{6{wire_nilii_o}}, niil1i, nii0Oi, nii0Ol, nii0OO, niii1i, niii1l, niii1O, niii0i, niii0l, wire_nilii_o}), .o(wire_nili0i_o), .sel({tx_boundary_sel[3:0]})); defparam nili0i.width_data = 16, nili0i.width_sel = 4; oper_mux nili0l ( .data({{6{wire_nilil_o}}, nii0Oi, nii0Ol, nii0OO, niii1i, niii1l, niii1O, niii0i, niii0l, wire_nilii_o, wire_nilil_o}), .o(wire_nili0l_o), .sel({tx_boundary_sel[3:0]})); defparam nili0l.width_data = 16, nili0l.width_sel = 4; oper_mux nili0O ( .data({{6{wire_niliO_o}}, nii0Ol, nii0OO, niii1i, niii1l, niii1O, niii0i, niii0l, wire_nilii_o, wire_nilil_o, wire_niliO_o}), .o(wire_nili0O_o), .sel({tx_boundary_sel[3:0]})); defparam nili0O.width_data = 16, nili0O.width_sel = 4; oper_mux nilii ( .data({wire_niOlO_o, wire_nl01l_o, wire_nliii_o, wire_nlllO_o}), .o(wire_nilii_o), .sel({doublewidth, dwidth})); defparam nilii.width_data = 4, nilii.width_sel = 2; oper_mux niliii ( .data({{6{wire_nilli_o}}, nii0OO, niii1i, niii1l, niii1O, niii0i, niii0l, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o}), .o(wire_niliii_o), .sel({tx_boundary_sel[3:0]})); defparam niliii.width_data = 16, niliii.width_sel = 4; oper_mux niliil ( .data({{6{wire_nilll_o}}, niii1i, niii1l, niii1O, niii0i, niii0l, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o}), .o(wire_niliil_o), .sel({tx_boundary_sel[3:0]})); defparam niliil.width_data = 16, niliil.width_sel = 4; oper_mux niliiO ( .data({{6{wire_nillO_o}}, niii1l, niii1O, niii0i, niii0l, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o}), .o(wire_niliiO_o), .sel({tx_boundary_sel[3:0]})); defparam niliiO.width_data = 16, niliiO.width_sel = 4; oper_mux nilil ( .data({wire_niOOi_o, wire_nl01O_o, wire_nliil_o, wire_nllOi_o}), .o(wire_nilil_o), .sel({doublewidth, dwidth})); defparam nilil.width_data = 4, nilil.width_sel = 2; oper_mux nilili ( .data({{6{wire_nilOi_o}}, niii1O, niii0i, niii0l, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o}), .o(wire_nilili_o), .sel({tx_boundary_sel[3:0]})); defparam nilili.width_data = 16, nilili.width_sel = 4; oper_mux nilill ( .data({{6{wire_nilOl_o}}, niii0i, niii0l, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o, wire_nilOl_o}), .o(wire_nilill_o), .sel({tx_boundary_sel[3:0]})); defparam nilill.width_data = 16, nilill.width_sel = 4; oper_mux nililO ( .data({{6{wire_nilOO_o}}, niii0l, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o, wire_nilOl_o, wire_nilOO_o}), .o(wire_nililO_o), .sel({tx_boundary_sel[3:0]})); defparam nililO.width_data = 16, nililO.width_sel = 4; oper_mux niliO ( .data({wire_niOOl_o, wire_nl00i_o, wire_nliiO_o, wire_nllOl_o}), .o(wire_niliO_o), .sel({doublewidth, dwidth})); defparam niliO.width_data = 4, niliO.width_sel = 2; oper_mux niliOi ( .data({{6{wire_niO1i_o}}, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o, wire_nilOl_o, wire_nilOO_o, wire_niO1i_o}), .o(wire_niliOi_o), .sel({tx_boundary_sel[3:0]})); defparam niliOi.width_data = 16, niliOi.width_sel = 4; oper_mux nilli ( .data({wire_niOOO_o, wire_nl00l_o, wire_nlili_o, wire_nllOO_o}), .o(wire_nilli_o), .sel({doublewidth, dwidth})); defparam nilli.width_data = 4, nilli.width_sel = 2; oper_mux nilll ( .data({wire_nl11i_o, wire_nl00O_o, wire_nlill_o, wire_nlO1i_o}), .o(wire_nilll_o), .sel({doublewidth, dwidth})); defparam nilll.width_data = 4, nilll.width_sel = 2; oper_mux nillll ( .data({{8{wire_nilii_o}}, niil1i, nii0Oi, nii0Ol, nii0OO, niii1i, niii1l, niii1O, wire_nilii_o}), .o(wire_nillll_o), .sel({tx_boundary_sel[3:0]})); defparam nillll.width_data = 16, nillll.width_sel = 4; oper_mux nilllO ( .data({{8{wire_nilil_o}}, nii0Oi, nii0Ol, nii0OO, niii1i, niii1l, niii1O, wire_nilii_o, wire_nilil_o}), .o(wire_nilllO_o), .sel({tx_boundary_sel[3:0]})); defparam nilllO.width_data = 16, nilllO.width_sel = 4; oper_mux nillO ( .data({wire_nl11l_o, wire_nl0ii_o, wire_nlilO_o, wire_nlO1l_o}), .o(wire_nillO_o), .sel({doublewidth, dwidth})); defparam nillO.width_data = 4, nillO.width_sel = 2; oper_mux nillOi ( .data({{8{wire_niliO_o}}, nii0Ol, nii0OO, niii1i, niii1l, niii1O, wire_nilii_o, wire_nilil_o, wire_niliO_o}), .o(wire_nillOi_o), .sel({tx_boundary_sel[3:0]})); defparam nillOi.width_data = 16, nillOi.width_sel = 4; oper_mux nillOl ( .data({{8{wire_nilli_o}}, nii0OO, niii1i, niii1l, niii1O, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o}), .o(wire_nillOl_o), .sel({tx_boundary_sel[3:0]})); defparam nillOl.width_data = 16, nillOl.width_sel = 4; oper_mux nillOO ( .data({{8{wire_nilll_o}}, niii1i, niii1l, niii1O, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o}), .o(wire_nillOO_o), .sel({tx_boundary_sel[3:0]})); defparam nillOO.width_data = 16, nillOO.width_sel = 4; oper_mux nilO1i ( .data({{8{wire_nillO_o}}, niii1l, niii1O, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o}), .o(wire_nilO1i_o), .sel({tx_boundary_sel[3:0]})); defparam nilO1i.width_data = 16, nilO1i.width_sel = 4; oper_mux nilO1l ( .data({{8{wire_nilOi_o}}, niii1O, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o}), .o(wire_nilO1l_o), .sel({tx_boundary_sel[3:0]})); defparam nilO1l.width_data = 16, nilO1l.width_sel = 4; oper_mux nilO1O ( .data({{8{wire_nilOl_o}}, wire_nilii_o, wire_nilil_o, wire_niliO_o, wire_nilli_o, wire_nilll_o, wire_nillO_o, wire_nilOi_o, wire_nilOl_o}), .o(wire_nilO1O_o), .sel({tx_boundary_sel[3:0]})); defparam nilO1O.width_data = 16, nilO1O.width_sel = 4; oper_mux nilOi ( .data({wire_nl11O_o, wire_nl0il_o, wire_nliOi_o, wire_nlO1O_o}), .o(wire_nilOi_o), .sel({doublewidth, dwidth})); defparam nilOi.width_data = 4, nilOi.width_sel = 2; oper_mux nilOl ( .data({wire_nl10i_o, wire_nl0iO_o, wire_nliOl_o, wire_nlO0i_o}), .o(wire_nilOl_o), .sel({doublewidth, dwidth})); defparam nilOl.width_data = 4, nilOl.width_sel = 2; oper_mux nilOO ( .data({wire_nl10l_o, wire_nl0li_o, wire_nliOO_o, wire_nlO0l_o}), .o(wire_nilOO_o), .sel({doublewidth, dwidth})); defparam nilOO.width_data = 4, nilOO.width_sel = 2; oper_mux niO0i ( .data({wire_nl1iO_o, wire_nl0Ol_o, {2{wire_nll0i_o}}}), .o(wire_niO0i_o), .sel({doublewidth, dwidth})); defparam niO0i.width_data = 4, niO0i.width_sel = 2; oper_mux niO0l ( .data({wire_nl1li_o, wire_nl0OO_o, {2{wire_nll0l_o}}}), .o(wire_niO0l_o), .sel({doublewidth, dwidth})); defparam niO0l.width_data = 4, niO0l.width_sel = 2; oper_mux niO0O ( .data({wire_nl1ll_o, wire_nli1i_o, {2{wire_nll0O_o}}}), .o(wire_niO0O_o), .sel({doublewidth, dwidth})); defparam niO0O.width_data = 4, niO0O.width_sel = 2; oper_mux niO1i ( .data({wire_nl10O_o, wire_nl0ll_o, wire_nll1i_o, wire_nlO0O_o}), .o(wire_niO1i_o), .sel({doublewidth, dwidth})); defparam niO1i.width_data = 4, niO1i.width_sel = 2; oper_mux niO1l ( .data({wire_nl1ii_o, wire_nl0lO_o, {2{wire_nll1l_o}}}), .o(wire_niO1l_o), .sel({doublewidth, dwidth})); defparam niO1l.width_data = 4, niO1l.width_sel = 2; oper_mux niO1O ( .data({wire_nl1il_o, wire_nl0Oi_o, {2{wire_nll1O_o}}}), .o(wire_niO1O_o), .sel({doublewidth, dwidth})); defparam niO1O.width_data = 4, niO1O.width_sel = 2; oper_mux niOii ( .data({wire_nl1lO_o, wire_nli1l_o, {2{wire_nllii_o}}}), .o(wire_niOii_o), .sel({doublewidth, dwidth})); defparam niOii.width_data = 4, niOii.width_sel = 2; oper_mux niOil ( .data({wire_nl1Oi_o, wire_nli1O_o, {2{wire_nllil_o}}}), .o(wire_niOil_o), .sel({doublewidth, dwidth})); defparam niOil.width_data = 4, niOil.width_sel = 2; oper_mux niOiO ( .data({wire_nl1Ol_o, wire_nli0i_o, {2{wire_nlliO_o}}}), .o(wire_niOiO_o), .sel({doublewidth, dwidth})); defparam niOiO.width_data = 4, niOiO.width_sel = 2; oper_mux niOli ( .data({wire_nl1OO_o, wire_nli0l_o, {2{wire_nllli_o}}}), .o(wire_niOli_o), .sel({doublewidth, dwidth})); defparam niOli.width_data = 4, niOli.width_sel = 2; oper_mux niOll ( .data({wire_nl01i_o, wire_nli0O_o, {2{wire_nllll_o}}}), .o(wire_niOll_o), .sel({doublewidth, dwidth})); defparam niOll.width_data = 4, niOll.width_sel = 2; oper_mux niOlO ( .data({(~ wire_n1Oll_o), (~ wire_n010O_o), (~ wire_n1OlO_o), (~ wire_n1O1l_o), wire_n1Oll_o, wire_n010O_o, wire_n1OlO_o, wire_n1O1l_o}), .o(wire_niOlO_o), .sel({n0lll, n0liO, n0lii})); defparam niOlO.width_data = 8, niOlO.width_sel = 3; oper_mux niOOi ( .data({(~ wire_n1Oli_o), (~ wire_n010l_o), (~ wire_n1OOi_o), (~ wire_n1O1O_o), wire_n1Oli_o, wire_n010l_o, wire_n1OOi_o, wire_n1O1O_o}), .o(wire_niOOi_o), .sel({n0lll, n0liO, n0lii})); defparam niOOi.width_data = 8, niOOi.width_sel = 3; oper_mux niOOl ( .data({(~ wire_n1OiO_o), (~ wire_n010i_o), (~ wire_n1OOl_o), (~ wire_n1O0i_o), wire_n1OiO_o, wire_n010i_o, wire_n1OOl_o, wire_n1O0i_o}), .o(wire_niOOl_o), .sel({n0lll, n0liO, n0lii})); defparam niOOl.width_data = 8, niOOl.width_sel = 3; oper_mux niOOO ( .data({(~ wire_n1Oil_o), (~ wire_n011O_o), (~ wire_n1OOO_o), (~ wire_n1O0l_o), wire_n1Oil_o, wire_n011O_o, wire_n1OOO_o, wire_n1O0l_o}), .o(wire_niOOO_o), .sel({n0lll, n0liO, n0lii})); defparam niOOO.width_data = 8, niOOO.width_sel = 3; oper_mux nl00i ( .data({(~ wire_n1Oii_o), (~ wire_n011l_o), (~ wire_n1OOl_o), (~ wire_n1O0i_o), wire_n1Oii_o, wire_n011l_o, wire_n1OOl_o, wire_n1O0i_o}), .o(wire_nl00i_o), .sel({n0lll, n0liO, n0lii})); defparam nl00i.width_data = 8, nl00i.width_sel = 3; oper_mux nl00l ( .data({(~ wire_n1O0O_o), (~ wire_n011i_o), (~ wire_n1OOO_o), (~ wire_n1O0l_o), wire_n1O0O_o, wire_n011i_o, wire_n1OOO_o, wire_n1O0l_o}), .o(wire_nl00l_o), .sel({n0lll, n0liO, n0lii})); defparam nl00l.width_data = 8, nl00l.width_sel = 3; oper_mux nl00O ( .data({(~ wire_n1O0l_o), (~ wire_n1OOO_o), (~ wire_n011i_o), (~ wire_n1O0O_o), wire_n1O0l_o, wire_n1OOO_o, wire_n011i_o, wire_n1O0O_o}), .o(wire_nl00O_o), .sel({n0lll, n0liO, n0lii})); defparam nl00O.width_data = 8, nl00O.width_sel = 3; oper_mux nl01i ( .data({(~ wire_n1OlO_o), (~ wire_n1O1l_o), (~ wire_n1Oll_o), (~ wire_n010O_o), wire_n1OlO_o, wire_n1O1l_o, wire_n1Oll_o, wire_n010O_o}), .o(wire_nl01i_o), .sel({n0lll, n0liO, n0lii})); defparam nl01i.width_data = 8, nl01i.width_sel = 3; oper_mux nl01l ( .data({(~ wire_n1OiO_o), (~ wire_n010i_o), (~ wire_n1OlO_o), (~ wire_n1O1l_o), wire_n1OiO_o, wire_n010i_o, wire_n1OlO_o, wire_n1O1l_o}), .o(wire_nl01l_o), .sel({n0lll, n0liO, n0lii})); defparam nl01l.width_data = 8, nl01l.width_sel = 3; oper_mux nl01O ( .data({(~ wire_n1Oil_o), (~ wire_n011O_o), (~ wire_n1OOi_o), (~ wire_n1O1O_o), wire_n1Oil_o, wire_n011O_o, wire_n1OOi_o, wire_n1O1O_o}), .o(wire_nl01O_o), .sel({n0lll, n0liO, n0lii})); defparam nl01O.width_data = 8, nl01O.width_sel = 3; oper_mux nl0ii ( .data({(~ wire_n1O0i_o), (~ wire_n1OOl_o), (~ wire_n011l_o), (~ wire_n1Oii_o), wire_n1O0i_o, wire_n1OOl_o, wire_n011l_o, wire_n1Oii_o}), .o(wire_nl0ii_o), .sel({n0lll, n0liO, n0lii})); defparam nl0ii.width_data = 8, nl0ii.width_sel = 3; oper_mux nl0il ( .data({(~ wire_n1O1O_o), (~ wire_n1OOi_o), (~ wire_n011O_o), (~ wire_n1Oil_o), wire_n1O1O_o, wire_n1OOi_o, wire_n011O_o, wire_n1Oil_o}), .o(wire_nl0il_o), .sel({n0lll, n0liO, n0lii})); defparam nl0il.width_data = 8, nl0il.width_sel = 3; oper_mux nl0iO ( .data({(~ wire_n1O1l_o), (~ wire_n1OlO_o), (~ wire_n010i_o), (~ wire_n1OiO_o), wire_n1O1l_o, wire_n1OlO_o, wire_n010i_o, wire_n1OiO_o}), .o(wire_nl0iO_o), .sel({n0lll, n0liO, n0lii})); defparam nl0iO.width_data = 8, nl0iO.width_sel = 3; oper_mux nl0li ( .data({{4{(~ wire_n1Oli_o)}}, {4{wire_n1Oli_o}}}), .o(wire_nl0li_o), .sel({n0lll, n0liO, n0lii})); defparam nl0li.width_data = 8, nl0li.width_sel = 3; oper_mux nl0ll ( .data({{4{(~ wire_n1Oll_o)}}, {4{wire_n1Oll_o}}}), .o(wire_nl0ll_o), .sel({n0lll, n0liO, n0lii})); defparam nl0ll.width_data = 8, nl0ll.width_sel = 3; oper_mux nl0lO ( .data({(~ wire_n010i_o), (~ wire_n1OiO_o), (~ wire_n1O1l_o), (~ wire_n1OlO_o), wire_n010i_o, wire_n1OiO_o, wire_n1O1l_o, wire_n1OlO_o}), .o(wire_nl0lO_o), .sel({n0lll, n0liO, n0lii})); defparam nl0lO.width_data = 8, nl0lO.width_sel = 3; oper_mux nl0Oi ( .data({(~ wire_n011O_o), (~ wire_n1Oil_o), (~ wire_n1O1O_o), (~ wire_n1OOi_o), wire_n011O_o, wire_n1Oil_o, wire_n1O1O_o, wire_n1OOi_o}), .o(wire_nl0Oi_o), .sel({n0lll, n0liO, n0lii})); defparam nl0Oi.width_data = 8, nl0Oi.width_sel = 3; oper_mux nl0Ol ( .data({(~ wire_n011l_o), (~ wire_n1Oii_o), (~ wire_n1O0i_o), (~ wire_n1OOl_o), wire_n011l_o, wire_n1Oii_o, wire_n1O0i_o, wire_n1OOl_o}), .o(wire_nl0Ol_o), .sel({n0lll, n0liO, n0lii})); defparam nl0Ol.width_data = 8, nl0Ol.width_sel = 3; oper_mux nl0OO ( .data({(~ wire_n011i_o), (~ wire_n1O0O_o), (~ wire_n1O0l_o), (~ wire_n1OOO_o), wire_n011i_o, wire_n1O0O_o, wire_n1O0l_o, wire_n1OOO_o}), .o(wire_nl0OO_o), .sel({n0lll, n0liO, n0lii})); defparam nl0OO.width_data = 8, nl0OO.width_sel = 3; oper_mux nl10i ( .data({(~ wire_n1O0i_o), (~ wire_n1OOl_o), (~ wire_n010i_o), (~ wire_n1OiO_o), wire_n1O0i_o, wire_n1OOl_o, wire_n010i_o, wire_n1OiO_o}), .o(wire_nl10i_o), .sel({n0lll, n0liO, n0lii})); defparam nl10i.width_data = 8, nl10i.width_sel = 3; oper_mux nl10l ( .data({(~ wire_n1O1O_o), (~ wire_n1OOi_o), (~ wire_n010l_o), (~ wire_n1Oli_o), wire_n1O1O_o, wire_n1OOi_o, wire_n010l_o, wire_n1Oli_o}), .o(wire_nl10l_o), .sel({n0lll, n0liO, n0lii})); defparam nl10l.width_data = 8, nl10l.width_sel = 3; oper_mux nl10O ( .data({(~ wire_n1O1l_o), (~ wire_n1OlO_o), (~ wire_n010O_o), (~ wire_n1Oll_o), wire_n1O1l_o, wire_n1OlO_o, wire_n010O_o, wire_n1Oll_o}), .o(wire_nl10O_o), .sel({n0lll, n0liO, n0lii})); defparam nl10O.width_data = 8, nl10O.width_sel = 3; oper_mux nl11i ( .data({(~ wire_n1Oii_o), (~ wire_n011l_o), (~ wire_n011i_o), (~ wire_n1O0O_o), wire_n1Oii_o, wire_n011l_o, wire_n011i_o, wire_n1O0O_o}), .o(wire_nl11i_o), .sel({n0lll, n0liO, n0lii})); defparam nl11i.width_data = 8, nl11i.width_sel = 3; oper_mux nl11l ( .data({(~ wire_n1O0O_o), (~ wire_n011i_o), (~ wire_n011l_o), (~ wire_n1Oii_o), wire_n1O0O_o, wire_n011i_o, wire_n011l_o, wire_n1Oii_o}), .o(wire_nl11l_o), .sel({n0lll, n0liO, n0lii})); defparam nl11l.width_data = 8, nl11l.width_sel = 3; oper_mux nl11O ( .data({(~ wire_n1O0l_o), (~ wire_n1OOO_o), (~ wire_n011O_o), (~ wire_n1Oil_o), wire_n1O0l_o, wire_n1OOO_o, wire_n011O_o, wire_n1Oil_o}), .o(wire_nl11O_o), .sel({n0lll, n0liO, n0lii})); defparam nl11O.width_data = 8, nl11O.width_sel = 3; oper_mux nl1ii ( .data({(~ wire_n010O_o), (~ wire_n1Oll_o), (~ wire_n1O1l_o), (~ wire_n1OlO_o), wire_n010O_o, wire_n1Oll_o, wire_n1O1l_o, wire_n1OlO_o}), .o(wire_nl1ii_o), .sel({n0lll, n0liO, n0lii})); defparam nl1ii.width_data = 8, nl1ii.width_sel = 3; oper_mux nl1il ( .data({(~ wire_n010l_o), (~ wire_n1Oli_o), (~ wire_n1O1O_o), (~ wire_n1OOi_o), wire_n010l_o, wire_n1Oli_o, wire_n1O1O_o, wire_n1OOi_o}), .o(wire_nl1il_o), .sel({n0lll, n0liO, n0lii})); defparam nl1il.width_data = 8, nl1il.width_sel = 3; oper_mux nl1iO ( .data({(~ wire_n010i_o), (~ wire_n1OiO_o), (~ wire_n1O0i_o), (~ wire_n1OOl_o), wire_n010i_o, wire_n1OiO_o, wire_n1O0i_o, wire_n1OOl_o}), .o(wire_nl1iO_o), .sel({n0lll, n0liO, n0lii})); defparam nl1iO.width_data = 8, nl1iO.width_sel = 3; oper_mux nl1li ( .data({(~ wire_n011O_o), (~ wire_n1Oil_o), (~ wire_n1O0l_o), (~ wire_n1OOO_o), wire_n011O_o, wire_n1Oil_o, wire_n1O0l_o, wire_n1OOO_o}), .o(wire_nl1li_o), .sel({n0lll, n0liO, n0lii})); defparam nl1li.width_data = 8, nl1li.width_sel = 3; oper_mux nl1ll ( .data({(~ wire_n011l_o), (~ wire_n1Oii_o), (~ wire_n1O0O_o), (~ wire_n011i_o), wire_n011l_o, wire_n1Oii_o, wire_n1O0O_o, wire_n011i_o}), .o(wire_nl1ll_o), .sel({n0lll, n0liO, n0lii})); defparam nl1ll.width_data = 8, nl1ll.width_sel = 3; oper_mux nl1lO ( .data({(~ wire_n011i_o), (~ wire_n1O0O_o), (~ wire_n1Oii_o), (~ wire_n011l_o), wire_n011i_o, wire_n1O0O_o, wire_n1Oii_o, wire_n011l_o}), .o(wire_nl1lO_o), .sel({n0lll, n0liO, n0lii})); defparam nl1lO.width_data = 8, nl1lO.width_sel = 3; oper_mux nl1Oi ( .data({(~ wire_n1OOO_o), (~ wire_n1O0l_o), (~ wire_n1Oil_o), (~ wire_n011O_o), wire_n1OOO_o, wire_n1O0l_o, wire_n1Oil_o, wire_n011O_o}), .o(wire_nl1Oi_o), .sel({n0lll, n0liO, n0lii})); defparam nl1Oi.width_data = 8, nl1Oi.width_sel = 3; oper_mux nl1Ol ( .data({(~ wire_n1OOl_o), (~ wire_n1O0i_o), (~ wire_n1OiO_o), (~ wire_n010i_o), wire_n1OOl_o, wire_n1O0i_o, wire_n1OiO_o, wire_n010i_o}), .o(wire_nl1Ol_o), .sel({n0lll, n0liO, n0lii})); defparam nl1Ol.width_data = 8, nl1Ol.width_sel = 3; oper_mux nl1OO ( .data({(~ wire_n1OOi_o), (~ wire_n1O1O_o), (~ wire_n1Oli_o), (~ wire_n010l_o), wire_n1OOi_o, wire_n1O1O_o, wire_n1Oli_o, wire_n010l_o}), .o(wire_nl1OO_o), .sel({n0lll, n0liO, n0lii})); defparam nl1OO.width_data = 8, nl1OO.width_sel = 3; oper_mux nli0i ( .data({(~ wire_n1OlO_o), (~ wire_n1O1l_o), (~ wire_n1OiO_o), (~ wire_n010i_o), wire_n1OlO_o, wire_n1O1l_o, wire_n1OiO_o, wire_n010i_o}), .o(wire_nli0i_o), .sel({n0lll, n0liO, n0lii})); defparam nli0i.width_data = 8, nli0i.width_sel = 3; oper_mux nli0l ( .data({{4{(~ wire_n010l_o)}}, {4{wire_n010l_o}}}), .o(wire_nli0l_o), .sel({n0lll, n0liO, n0lii})); defparam nli0l.width_data = 8, nli0l.width_sel = 3; oper_mux nli0O ( .data({{4{(~ wire_n010O_o)}}, {4{wire_n010O_o}}}), .o(wire_nli0O_o), .sel({n0lll, n0liO, n0lii})); defparam nli0O.width_data = 8, nli0O.width_sel = 3; oper_mux nli1i ( .data({(~ wire_n1OOO_o), (~ wire_n1O0l_o), (~ wire_n1O0O_o), (~ wire_n011i_o), wire_n1OOO_o, wire_n1O0l_o, wire_n1O0O_o, wire_n011i_o}), .o(wire_nli1i_o), .sel({n0lll, n0liO, n0lii})); defparam nli1i.width_data = 8, nli1i.width_sel = 3; oper_mux nli1l ( .data({(~ wire_n1OOl_o), (~ wire_n1O0i_o), (~ wire_n1Oii_o), (~ wire_n011l_o), wire_n1OOl_o, wire_n1O0i_o, wire_n1Oii_o, wire_n011l_o}), .o(wire_nli1l_o), .sel({n0lll, n0liO, n0lii})); defparam nli1l.width_data = 8, nli1l.width_sel = 3; oper_mux nli1O ( .data({(~ wire_n1OOi_o), (~ wire_n1O1O_o), (~ wire_n1Oil_o), (~ wire_n011O_o), wire_n1OOi_o, wire_n1O1O_o, wire_n1Oil_o, wire_n011O_o}), .o(wire_nli1O_o), .sel({n0lll, n0liO, n0lii})); defparam nli1O.width_data = 8, nli1O.width_sel = 3; oper_mux nliii ( .data({(~ wire_n1Oll_o), (~ wire_n1O1l_o), wire_n1Oll_o, wire_n1O1l_o}), .o(wire_nliii_o), .sel({n0lll, n0liO})); defparam nliii.width_data = 4, nliii.width_sel = 2; oper_mux nliil ( .data({(~ wire_n1Oli_o), (~ wire_n1O1O_o), wire_n1Oli_o, wire_n1O1O_o}), .o(wire_nliil_o), .sel({n0lll, n0liO})); defparam nliil.width_data = 4, nliil.width_sel = 2; oper_mux nliiO ( .data({(~ wire_n1OiO_o), (~ wire_n1O0i_o), wire_n1OiO_o, wire_n1O0i_o}), .o(wire_nliiO_o), .sel({n0lll, n0liO})); defparam nliiO.width_data = 4, nliiO.width_sel = 2; oper_mux nlili ( .data({(~ wire_n1Oil_o), (~ wire_n1O0l_o), wire_n1Oil_o, wire_n1O0l_o}), .o(wire_nlili_o), .sel({n0lll, n0liO})); defparam nlili.width_data = 4, nlili.width_sel = 2; oper_mux nlill ( .data({(~ wire_n1Oii_o), (~ wire_n1O0O_o), wire_n1Oii_o, wire_n1O0O_o}), .o(wire_nlill_o), .sel({n0lll, n0liO})); defparam nlill.width_data = 4, nlill.width_sel = 2; oper_mux nlilO ( .data({(~ wire_n1O0O_o), (~ wire_n1Oii_o), wire_n1O0O_o, wire_n1Oii_o}), .o(wire_nlilO_o), .sel({n0lll, n0liO})); defparam nlilO.width_data = 4, nlilO.width_sel = 2; oper_mux nliOi ( .data({(~ wire_n1O0l_o), (~ wire_n1Oil_o), wire_n1O0l_o, wire_n1Oil_o}), .o(wire_nliOi_o), .sel({n0lll, n0liO})); defparam nliOi.width_data = 4, nliOi.width_sel = 2; oper_mux nliOl ( .data({(~ wire_n1O0i_o), (~ wire_n1OiO_o), wire_n1O0i_o, wire_n1OiO_o}), .o(wire_nliOl_o), .sel({n0lll, n0liO})); defparam nliOl.width_data = 4, nliOl.width_sel = 2; oper_mux nliOO ( .data({(~ wire_n1O1O_o), (~ wire_n1Oli_o), wire_n1O1O_o, wire_n1Oli_o}), .o(wire_nliOO_o), .sel({n0lll, n0liO})); defparam nliOO.width_data = 4, nliOO.width_sel = 2; oper_mux nll0i ( .data({{2{(~ wire_n1OOl_o)}}, {2{wire_n1OOl_o}}}), .o(wire_nll0i_o), .sel({n0lll, n0liO})); defparam nll0i.width_data = 4, nll0i.width_sel = 2; oper_mux nll0l ( .data({{2{(~ wire_n1OOO_o)}}, {2{wire_n1OOO_o}}}), .o(wire_nll0l_o), .sel({n0lll, n0liO})); defparam nll0l.width_data = 4, nll0l.width_sel = 2; oper_mux nll0O ( .data({{2{(~ wire_n011i_o)}}, {2{wire_n011i_o}}}), .o(wire_nll0O_o), .sel({n0lll, n0liO})); defparam nll0O.width_data = 4, nll0O.width_sel = 2; oper_mux nll1i ( .data({(~ wire_n1O1l_o), (~ wire_n1Oll_o), wire_n1O1l_o, wire_n1Oll_o}), .o(wire_nll1i_o), .sel({n0lll, n0liO})); defparam nll1i.width_data = 4, nll1i.width_sel = 2; oper_mux nll1l ( .data({{2{(~ wire_n1OlO_o)}}, {2{wire_n1OlO_o}}}), .o(wire_nll1l_o), .sel({n0lll, n0liO})); defparam nll1l.width_data = 4, nll1l.width_sel = 2; oper_mux nll1O ( .data({{2{(~ wire_n1OOi_o)}}, {2{wire_n1OOi_o}}}), .o(wire_nll1O_o), .sel({n0lll, n0liO})); defparam nll1O.width_data = 4, nll1O.width_sel = 2; oper_mux nllii ( .data({{2{(~ wire_n011l_o)}}, {2{wire_n011l_o}}}), .o(wire_nllii_o), .sel({n0lll, n0liO})); defparam nllii.width_data = 4, nllii.width_sel = 2; oper_mux nllil ( .data({{2{(~ wire_n011O_o)}}, {2{wire_n011O_o}}}), .o(wire_nllil_o), .sel({n0lll, n0liO})); defparam nllil.width_data = 4, nllil.width_sel = 2; oper_mux nlliO ( .data({((ni0Oll40 ^ ni0Oll39) & (~ wire_n010i_o)), (~ wire_n010i_o), wire_n010i_o, ((ni0OlO38 ^ ni0OlO37) & wire_n010i_o)}), .o(wire_nlliO_o), .sel({n0lll, n0liO})); defparam nlliO.width_data = 4, nlliO.width_sel = 2; oper_mux nllli ( .data({(~ wire_n010l_o), ((ni0OOi36 ^ ni0OOi35) & (~ wire_n010l_o)), {2{wire_n010l_o}}}), .o(wire_nllli_o), .sel({n0lll, n0liO})); defparam nllli.width_data = 4, nllli.width_sel = 2; oper_mux nllll ( .data({{2{(~ wire_n010O_o)}}, {2{wire_n010O_o}}}), .o(wire_nllll_o), .sel({n0lll, n0liO})); defparam nllll.width_data = 4, nllll.width_sel = 2; oper_mux nlllO ( .data({(~ wire_n1OiO_o), (~ wire_n1O1l_o), wire_n1OiO_o, wire_n1O1l_o}), .o(wire_nlllO_o), .sel({n0lll, n0liO})); defparam nlllO.width_data = 4, nlllO.width_sel = 2; oper_mux nllOi ( .data({(~ wire_n1Oil_o), ((ni0OOl34 ^ ni0OOl33) & (~ wire_n1O1O_o)), wire_n1Oil_o, wire_n1O1O_o}), .o(wire_nllOi_o), .sel({n0lll, n0liO})); defparam nllOi.width_data = 4, nllOi.width_sel = 2; oper_mux nllOl ( .data({(~ wire_n1Oii_o), (~ wire_n1O0i_o), wire_n1Oii_o, wire_n1O0i_o}), .o(wire_nllOl_o), .sel({n0lll, n0liO})); defparam nllOl.width_data = 4, nllOl.width_sel = 2; oper_mux nllOO ( .data({(~ wire_n1O0O_o), (~ wire_n1O0l_o), wire_n1O0O_o, ((ni0OOO32 ^ ni0OOO31) & wire_n1O0l_o)}), .o(wire_nllOO_o), .sel({n0lll, n0liO})); defparam nllOO.width_data = 4, nllOO.width_sel = 2; oper_mux nlO0i ( .data({(~ wire_n1O1l_o), (~ wire_n1OiO_o), wire_n1O1l_o, wire_n1OiO_o}), .o(wire_nlO0i_o), .sel({n0lll, ((nii10l22 ^ nii10l21) & n0liO)})); defparam nlO0i.width_data = 4, nlO0i.width_sel = 2; oper_mux nlO0l ( .data({((nii10O20 ^ nii10O19) & (~ wire_n1Oli_o)), (~ wire_n1Oli_o), {2{wire_n1Oli_o}}}), .o(wire_nlO0l_o), .sel({((nii1ii18 ^ nii1ii17) & n0lll), n0liO})); defparam nlO0l.width_data = 4, nlO0l.width_sel = 2; oper_mux nlO0O ( .data({{2{(~ wire_n1Oll_o)}}, ((nii1il16 ^ nii1il15) & wire_n1Oll_o), wire_n1Oll_o}), .o(wire_nlO0O_o), .sel({n0lll, n0liO})); defparam nlO0O.width_data = 4, nlO0O.width_sel = 2; oper_mux nlO1i ( .data({((nii11i30 ^ nii11i29) & (~ wire_n1O0l_o)), (~ wire_n1O0O_o), wire_n1O0l_o, wire_n1O0O_o}), .o(wire_nlO1i_o), .sel({n0lll, n0liO})); defparam nlO1i.width_data = 4, nlO1i.width_sel = 2; oper_mux nlO1l ( .data({(~ wire_n1O0i_o), ((nii11l28 ^ nii11l27) & (~ wire_n1Oii_o)), ((nii11O26 ^ nii11O25) & wire_n1O0i_o), wire_n1Oii_o}), .o(wire_nlO1l_o), .sel({n0lll, n0liO})); defparam nlO1l.width_data = 4, nlO1l.width_sel = 2; oper_mux nlO1O ( .data({(~ wire_n1O1O_o), (~ wire_n1Oil_o), wire_n1O1O_o, wire_n1Oil_o}), .o(wire_nlO1O_o), .sel({((nii10i24 ^ nii10i23) & n0lll), n0liO})); defparam nlO1O.width_data = 4, nlO1O.width_sel = 2; assign disp_out_3b = {wire_nlli1i_dataout, wire_nl010O_dataout}, ni000i = (((((~ wire_n1ll_dataout) & (wire_n1li_dataout & ni01ll)) | (wire_n1ll_dataout & ((~ wire_n1li_dataout) & ni01ll))) | (wire_n1ll_dataout & (wire_n1li_dataout & ((~ wire_n1iO_dataout) & wire_n1il_dataout)))) | (wire_n1ll_dataout & (wire_n1li_dataout & (wire_n1iO_dataout & (~ wire_n1il_dataout))))), ni000l = (((((((~ wire_n1ll_dataout) & ((~ wire_n1li_dataout) & (wire_n1iO_dataout & wire_n1il_dataout))) | ((~ wire_n1ll_dataout) & (wire_n1li_dataout & ni01Ol))) | ((~ wire_n1ll_dataout) & (wire_n1li_dataout & ni01Oi))) | (wire_n1ll_dataout & ((~ wire_n1li_dataout) & ni01Ol))) | (wire_n1ll_dataout & ((~ wire_n1li_dataout) & ni01Oi))) | (wire_n1ll_dataout & (wire_n1li_dataout & ((~ wire_n1iO_dataout) & (~ wire_n1il_dataout))))), ni000O = (ni00il | (wire_n1lO_dataout & ni00ii)), ni001i = (wire_n1lO_dataout & ((wire_n1ll_dataout & ni00iO) | ni000i)), ni001l = (wire_nl1iii_dataout & ni000l), ni001O = ((((~ wire_n1lO_dataout) | wire_nl1iii_dataout) & ni000l) | (wire_n1lO_dataout & (((~ ni000i) & (~ ni000l)) & ni00ii))), ni00ii = ((~ wire_n1ll_dataout) | (wire_n1li_dataout | (wire_n1iO_dataout | wire_n1il_dataout))), ni00il = ((~ wire_n1lO_dataout) & ni00iO), ni00iO = (((((~ wire_n1ll_dataout) & ((~ wire_n1li_dataout) & ((~ wire_n1iO_dataout) & wire_n1il_dataout))) | ((~ wire_n1ll_dataout) & ((~ wire_n1li_dataout) & (wire_n1iO_dataout & (~ wire_n1il_dataout))))) | ((~ wire_n1ll_dataout) & (wire_n1li_dataout & ni01lO))) | (wire_n1ll_dataout & ((~ wire_n1li_dataout) & ni01lO))), ni00li = (wire_n1ll_dataout & (wire_n1li_dataout & (wire_n1iO_dataout & wire_n1il_dataout))), ni00ll = ((~ wire_n1ll_dataout) & ((~ wire_n1li_dataout) & ((~ wire_n1iO_dataout) & (~ wire_n1il_dataout)))), ni00lO = (ni00li | ni00ll), ni00Oi = ((((wire_n1lO_dataout & wire_n1ll_dataout) & wire_n1li_dataout) & (~ wire_n1iO_dataout)) & (~ wire_n1il_dataout)), ni00Ol = (wire_n1iO_dataout & wire_n1il_dataout), ni00OO = ((~ wire_n1iO_dataout) & (~ wire_n1il_dataout)), ni01il = ((((((((((((((wire_nili1O_o[15] | wire_nili1O_o[14]) | wire_nili1O_o[13]) | wire_nili1O_o[12]) | wire_nili1O_o[11]) | wire_nili1O_o[10]) | wire_nili1O_o[9]) | wire_nili1O_o[8]) | wire_nili1O_o[7]) | wire_nili1O_o[6]) | wire_nili1O_o[5]) | wire_nili1O_o[4]) | wire_nili1O_o[3]) | wire_nili1O_o[2]) | wire_nili1O_o[1]), ni01iO = ((((((wire_nillli_o[15] | wire_nillli_o[14]) | wire_nillli_o[13]) | wire_nillli_o[12]) | wire_nillli_o[11]) | wire_nillli_o[10]) | wire_nillli_o[0]), ni01li = ((((((wire_nillli_o[7] | wire_nillli_o[6]) | wire_nillli_o[5]) | wire_nillli_o[4]) | wire_nillli_o[3]) | wire_nillli_o[2]) | wire_nillli_o[1]), ni01ll = (wire_n1iO_dataout & wire_n1il_dataout), ni01lO = ((~ wire_n1iO_dataout) & (~ wire_n1il_dataout)), ni01Oi = (wire_n1iO_dataout & (~ wire_n1il_dataout)), ni01Ol = ((~ wire_n1iO_dataout) & wire_n1il_dataout), ni01OO = (((((((~ wire_n1ll_dataout) & (wire_n1li_dataout & (wire_n1iO_dataout & wire_n1il_dataout))) | (wire_n1lO_dataout & ni00ll)) | (wire_n1lO_dataout & ni00li)) | (wire_n1lO_dataout & ni000i)) | ni001l) ^ ((~ wire_n0O1l_dataout) & (ni001l | ((ni00lO | ((~ wire_n1lO_dataout) & (((~ wire_n1ll_dataout) & ni000i) | ni00iO))) | ni001i)))), ni0i0i = ((((~ wire_niOlOi_dataout) & (wire_nl00ll_dataout & (~ ni0i0O))) | ni0i0l) ^ ((~ wire_niOlOi_dataout) & ni0i0O)), ni0i0l = (wire_n1Ol_dataout & wire_n1Oi_dataout), ni0i0O = (ni0i0l | ni0i1l), ni0i1i = ((~ wire_n1OO_dataout) & ni0i1l), ni0i1l = ((~ wire_n1Ol_dataout) & (~ wire_n1Oi_dataout)), ni0i1O = (wire_n1OO_dataout & (wire_n1Ol_dataout & (wire_n1Oi_dataout & ((((~ wire_niOlOi_dataout) & ((wire_n1lO_dataout & (~ wire_n1ll_dataout)) & (((((~ wire_n1ll_dataout) & ((~ wire_n1li_dataout) & ((~ wire_n1iO_dataout) & wire_n1il_dataout))) | ((~ wire_n1ll_dataout) & ((~ wire_n1li_dataout) & (wire_n1iO_dataout & (~ wire_n1il_dataout))))) | ((~ wire_n1ll_dataout) & (wire_n1li_dataout & ni00OO))) | (wire_n1ll_dataout & ((~ wire_n1li_dataout) & ni00OO))))) | (wire_niOlOi_dataout & (((~ wire_n1lO_dataout) & wire_n1ll_dataout) & (((((~ wire_n1ll_dataout) & (wire_n1li_dataout & ni00Ol)) | (wire_n1ll_dataout & ((~ wire_n1li_dataout) & ni00Ol))) | (wire_n1ll_dataout & (wire_n1li_dataout & ((~ wire_n1iO_dataout) & wire_n1il_dataout)))) | (wire_n1ll_dataout & (wire_n1li_dataout & (wire_n1iO_dataout & (~ wire_n1il_dataout)))))))) | (wire_n1OO_dataout & (wire_n1Ol_dataout & (wire_nil_dataout & wire_n1Oi_dataout))))))), ni0iii = (wire_nil_dataout & ni00Oi), ni0iil = (wire_n01l_dataout & wire_n01i_dataout), ni0iiO = ((~ wire_n01l_dataout) & (~ wire_n01i_dataout)), ni0ili = (wire_n01l_dataout & (~ wire_n01i_dataout)), ni0ill = ((~ wire_n01l_dataout) & wire_n01i_dataout), ni0ilO = (((((((~ wire_n00i_dataout) & (wire_n01O_dataout & (wire_n01l_dataout & wire_n01i_dataout))) | (wire_n00l_dataout & ni0lil)) | (wire_n00l_dataout & ni0lii)) | (wire_n00l_dataout & ni0l1i)) | ni0iOl) ^ ((~ wire_n0O1O_dataout) & (ni0iOl | ((ni0liO | ((~ wire_n00l_dataout) & (((~ wire_n00i_dataout) & ni0l1i) | ni0l0O))) | ni0iOi)))), ni0iOi = (wire_n00l_dataout & ((wire_n00i_dataout & ni0l0O) | ni0l1i)), ni0iOl = (wire_nliO1l_dataout & ni0l1l), ni0iOO = ((((~ wire_n00l_dataout) | wire_nliO1l_dataout) & ni0l1l) | (wire_n00l_dataout & (((~ ni0l1i) & (~ ni0l1l)) & ni0l0i))), ni0l0i = ((~ wire_n00i_dataout) | (wire_n01O_dataout | (wire_n01l_dataout | wire_n01i_dataout))), ni0l0l = ((~ wire_n00l_dataout) & ni0l0O), ni0l0O = (((((~ wire_n00i_dataout) & ((~ wire_n01O_dataout) & ((~ wire_n01l_dataout) & wire_n01i_dataout))) | ((~ wire_n00i_dataout) & ((~ wire_n01O_dataout) & (wire_n01l_dataout & (~ wire_n01i_dataout))))) | ((~ wire_n00i_dataout) & (wire_n01O_dataout & ni0iiO))) | (wire_n00i_dataout & ((~ wire_n01O_dataout) & ni0iiO))), ni0l1i = (((((~ wire_n00i_dataout) & (wire_n01O_dataout & ni0iil)) | (wire_n00i_dataout & ((~ wire_n01O_dataout) & ni0iil))) | (wire_n00i_dataout & (wire_n01O_dataout & ((~ wire_n01l_dataout) & wire_n01i_dataout)))) | (wire_n00i_dataout & (wire_n01O_dataout & (wire_n01l_dataout & (~ wire_n01i_dataout))))), ni0l1l = (((((((~ wire_n00i_dataout) & ((~ wire_n01O_dataout) & (wire_n01l_dataout & wire_n01i_dataout))) | ((~ wire_n00i_dataout) & (wire_n01O_dataout & ni0ill))) | ((~ wire_n00i_dataout) & (wire_n01O_dataout & ni0ili))) | (wire_n00i_dataout & ((~ wire_n01O_dataout) & ni0ill))) | (wire_n00i_dataout & ((~ wire_n01O_dataout) & ni0ili))) | (wire_n00i_dataout & (wire_n01O_dataout & ((~ wire_n01l_dataout) & (~ wire_n01i_dataout))))), ni0l1O = (ni0l0l | (wire_n00l_dataout & ni0l0i)), ni0lii = (wire_n00i_dataout & (wire_n01O_dataout & (wire_n01l_dataout & wire_n01i_dataout))), ni0lil = ((~ wire_n00i_dataout) & ((~ wire_n01O_dataout) & ((~ wire_n01l_dataout) & (~ wire_n01i_dataout)))), ni0liO = (ni0lii | ni0lil), ni0lli = ((((wire_n00l_dataout & wire_n00i_dataout) & wire_n01O_dataout) & (~ wire_n01l_dataout)) & (~ wire_n01i_dataout)), ni0lll = (wire_n01l_dataout & wire_n01i_dataout), ni0llO = ((~ wire_n01l_dataout) & (~ wire_n01i_dataout)), ni0lOi = ((~ wire_n0il_dataout) & ni0lOl), ni0lOl = ((~ wire_n0ii_dataout) & (~ wire_n00O_dataout)), ni0lOO = (wire_n0il_dataout & (wire_n0ii_dataout & (wire_n00O_dataout & ((((~ wire_nli1il_dataout) & ((wire_n00l_dataout & (~ wire_n00i_dataout)) & (((((~ wire_n00i_dataout) & ((~ wire_n01O_dataout) & ((~ wire_n01l_dataout) & wire_n01i_dataout))) | ((~ wire_n00i_dataout) & ((~ wire_n01O_dataout) & (wire_n01l_dataout & (~ wire_n01i_dataout))))) | ((~ wire_n00i_dataout) & (wire_n01O_dataout & ni0llO))) | (wire_n00i_dataout & ((~ wire_n01O_dataout) & ni0llO))))) | (wire_nli1il_dataout & (((~ wire_n00l_dataout) & wire_n00i_dataout) & (((((~ wire_n00i_dataout) & (wire_n01O_dataout & ni0lll)) | (wire_n00i_dataout & ((~ wire_n01O_dataout) & ni0lll))) | (wire_n00i_dataout & (wire_n01O_dataout & ((~ wire_n01l_dataout) & wire_n01i_dataout)))) | (wire_n00i_dataout & (wire_n01O_dataout & (wire_n01l_dataout & (~ wire_n01i_dataout)))))))) | (wire_n0il_dataout & (wire_n0ii_dataout & (wire_niO_dataout & wire_n00O_dataout))))))), ni0O0i = (wire_niO_dataout & ni0lli), ni0O1i = ((((~ wire_nli1il_dataout) & (wire_nlll0O_dataout & (~ ni0O1O))) | ni0O1l) ^ ((~ wire_nli1il_dataout) & ni0O1O)), ni0O1l = (wire_n0ii_dataout & wire_n00O_dataout), ni0O1O = (ni0O1l | ni0lOl), ni0Oil = 1'b1, nii00O = ((((((d21_5_eq_n & d2_2_eq_n) & (nii0iO2 ^ nii0iO1)) & ge_xaui_sel) & (~ tx_ctl_tc[0])) & (nii0ii4 ^ nii0ii3)) & k_det), nii1iO = (((((((d21_5_eq_n & d2_2_eq_n) & (nii1lO12 ^ nii1lO11)) & ge_xaui_sel) & (~ tx_ctl_tc[0])) & (nii1li14 ^ nii1li13)) & k_det) & (~ n01il)), nii1Ol = ((((((((d21_5_eq_n & d2_2_eq_n) & (nii00i6 ^ nii00i5)) & ge_xaui_sel) & (~ tx_ctl_tc[0])) & k_det) & (nii01l8 ^ nii01l7)) & n01il) & (nii1OO10 ^ nii1OO9)), pudr = {nii1i, ni0Ol, ni0lO, ni0ll, ni0li, ni0iO, ni0il, ni0ii, ni00O, ni00l, ni00i, ni01O, ni01l, ni01i, ni1OO, ni1Ol, ni1Oi, ni1lO, ni1ll, n0lOi}, tx_ctl_pre_en = {n01OO, n01Ol}, tx_data_9_pre_en = {n01Oi, n01lO}, tx_data_pre_en = {n0i1i, n00OO, n00Ol, n00Oi, n00lO, n00ll, n00li, n00iO, n00il, n00ii, n000O, n000l, n000i, n001O, n001l, n001i}, txlp20b = {n0l0O, n0l0l, n0l0i, n0l1O, n0l1l, n0l1i, n0iOO, n0iOl, n0iOi, n0ilO, n0ill, n0ili, n0iiO, n0iil, n0iii, n0i0O, n0i0l, n0i0i, n0i1O, n0i1l}; endmodule //stratixiv_hssi_tx_digi_enc_chnl_top //synopsys translate_on //VALID FILE //IP Functional Simulation Model //VERSION_BEGIN 12.0 cbx_mgl 2012:05:31:20:09:47:SJ cbx_simgen 2012:05:31:20:08:35:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 // Copyright (C) 1991-2012 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // You may only use these simulation model output files for simulation // purposes and expressly not for synthesis or any other purposes (in which // event Altera disclaims all warranties of any kind). //synopsys translate_off //synthesis_resources = lut 12 mux21 13 `timescale 1 ps / 1 ps module stratixiv_hssi_tx_digi_iq_pipe_tx ( fifo_rd_clk_raw, fifo_select_in_centrl, fifo_select_in_pipe_quad_down, fifo_select_in_pipe_quad_up, fifo_select_out_pipe, rd_enable_in_centrl, rd_enable_in_pipe_quad_down, rd_enable_in_pipe_quad_up, rd_enable_out_pipe, refclk_b_raw, rfreerun_tx, rmaster_tx, rmaster_up_tx, rpipeline_bypass_tx, soft_reset_rclk1, soft_reset_wclk1, tx_div2_sync_in_centrl, tx_div2_sync_in_pipe_quad_down, tx_div2_sync_in_pipe_quad_up, tx_div2_sync_out_pipe, txrst, wr_clk_pos_raw, wr_enable_in_centrl, wr_enable_in_pipe_quad_down, wr_enable_in_pipe_quad_up, wr_enable_out_pipe) /* synthesis synthesis_clearbox=1 */; input fifo_rd_clk_raw; input fifo_select_in_centrl; input fifo_select_in_pipe_quad_down; input fifo_select_in_pipe_quad_up; output fifo_select_out_pipe; input rd_enable_in_centrl; input rd_enable_in_pipe_quad_down; input rd_enable_in_pipe_quad_up; output rd_enable_out_pipe; input refclk_b_raw; input rfreerun_tx; input rmaster_tx; input rmaster_up_tx; input rpipeline_bypass_tx; input soft_reset_rclk1; input soft_reset_wclk1; input tx_div2_sync_in_centrl; input tx_div2_sync_in_pipe_quad_down; input tx_div2_sync_in_pipe_quad_up; output tx_div2_sync_out_pipe; input txrst; input wr_clk_pos_raw; input wr_enable_in_centrl; input wr_enable_in_pipe_quad_down; input wr_enable_in_pipe_quad_up; output wr_enable_out_pipe; reg n0ii7; reg n0ii8; reg n0il5; reg n0il6; reg n0li3; reg n0li4; reg n0Oi1; reg n0Oi2; reg n1l; reg n1i_clk_prev; wire wire_n1i_CLRN; reg nO; wire wire_nl_CLRN; reg ni; reg nlO_clk_prev; wire wire_nlO_CLRN; reg nlOO; reg nlOl_clk_prev; wire wire_nlOl_PRN; wire wire_n0i_dataout; wire wire_n0l_dataout; wire wire_n0O_dataout; wire wire_n1O_dataout; wire wire_nii_dataout; wire wire_nil_dataout; wire wire_niO_dataout; wire wire_nli_dataout; wire wire_nll_dataout; wire wire_nlli_dataout; wire wire_nlll_dataout; wire wire_nllO_dataout; wire wire_nlOi_dataout; wire n0ll; initial n0ii7 = 0; always @ ( posedge refclk_b_raw) n0ii7 <= n0ii8; event n0ii7_event; initial #1 ->n0ii7_event; always @(n0ii7_event) n0ii7 <= {1{1'b1}}; initial n0ii8 = 0; always @ ( posedge refclk_b_raw) n0ii8 <= n0ii7; initial n0il5 = 0; always @ ( posedge refclk_b_raw) n0il5 <= n0il6; event n0il5_event; initial #1 ->n0il5_event; always @(n0il5_event) n0il5 <= {1{1'b1}}; initial n0il6 = 0; always @ ( posedge refclk_b_raw) n0il6 <= n0il5; initial n0li3 = 0; always @ ( posedge refclk_b_raw) n0li3 <= n0li4; event n0li3_event; initial #1 ->n0li3_event; always @(n0li3_event) n0li3 <= {1{1'b1}}; initial n0li4 = 0; always @ ( posedge refclk_b_raw) n0li4 <= n0li3; initial n0Oi1 = 0; always @ ( posedge refclk_b_raw) n0Oi1 <= n0Oi2; event n0Oi1_event; initial #1 ->n0Oi1_event; always @(n0Oi1_event) n0Oi1 <= {1{1'b1}}; initial n0Oi2 = 0; always @ ( posedge refclk_b_raw) n0Oi2 <= n0Oi1; initial begin n1l = 0; end always @ (refclk_b_raw or wire_n1O_dataout or wire_n1i_CLRN) begin if (wire_n1O_dataout == 1'b1) begin n1l <= 1; end else if (wire_n1i_CLRN == 1'b0) begin n1l <= 0; end else if (refclk_b_raw != n1i_clk_prev && refclk_b_raw == 1'b1) begin n1l <= wire_nli_dataout; end n1i_clk_prev <= refclk_b_raw; end assign wire_n1i_CLRN = (n0il6 ^ n0il5); event n1l_event; initial #1 ->n1l_event; always @(n1l_event) n1l <= 1; initial begin nO = 0; end always @ ( posedge fifo_rd_clk_raw or negedge wire_nl_CLRN) begin if (wire_nl_CLRN == 1'b0) begin nO <= 0; end else begin nO <= wire_n0i_dataout; end end assign wire_nl_CLRN = ((n0Oi2 ^ n0Oi1) & (~ soft_reset_rclk1)); initial begin ni = 0; end always @ (refclk_b_raw or txrst or wire_nlO_CLRN) begin if (txrst == 1'b1) begin ni <= 1; end else if (wire_nlO_CLRN == 1'b0) begin ni <= 0; end else if (refclk_b_raw != nlO_clk_prev && refclk_b_raw == 1'b1) begin ni <= wire_nil_dataout; end nlO_clk_prev <= refclk_b_raw; end assign wire_nlO_CLRN = (n0li4 ^ n0li3); event ni_event; initial #1 ->ni_event; always @(ni_event) ni <= 1; initial begin nlOO = 0; end always @ (wr_clk_pos_raw or wire_nlOl_PRN or soft_reset_wclk1) begin if (wire_nlOl_PRN == 1'b0) begin nlOO <= 1; end else if (soft_reset_wclk1 == 1'b1) begin nlOO <= 0; end else if (wr_clk_pos_raw != nlOl_clk_prev && wr_clk_pos_raw == 1'b1) begin nlOO <= wire_n0O_dataout; end nlOl_clk_prev <= wr_clk_pos_raw; end assign wire_nlOl_PRN = (n0ii8 ^ n0ii7); assign wire_n0i_dataout = ((~ rmaster_tx) === 1'b1) ? wire_n0l_dataout : rd_enable_in_centrl; assign wire_n0l_dataout = (rmaster_up_tx === 1'b1) ? rd_enable_in_pipe_quad_up : rd_enable_in_pipe_quad_down; assign wire_n0O_dataout = ((~ rmaster_tx) === 1'b1) ? wire_nii_dataout : wr_enable_in_centrl; and(wire_n1O_dataout, txrst, ~(rfreerun_tx)); assign wire_nii_dataout = (rmaster_up_tx === 1'b1) ? wr_enable_in_pipe_quad_up : wr_enable_in_pipe_quad_down; assign wire_nil_dataout = ((~ rmaster_tx) === 1'b1) ? wire_niO_dataout : fifo_select_in_centrl; assign wire_niO_dataout = (rmaster_up_tx === 1'b1) ? fifo_select_in_pipe_quad_up : fifo_select_in_pipe_quad_down; assign wire_nli_dataout = ((~ rmaster_tx) === 1'b1) ? wire_nll_dataout : tx_div2_sync_in_centrl; assign wire_nll_dataout = (rmaster_up_tx === 1'b1) ? tx_div2_sync_in_pipe_quad_up : tx_div2_sync_in_pipe_quad_down; assign wire_nlli_dataout = (rpipeline_bypass_tx === 1'b1) ? wire_n0i_dataout : nO; assign wire_nlll_dataout = (rpipeline_bypass_tx === 1'b1) ? wire_n0O_dataout : nlOO; assign wire_nllO_dataout = (rpipeline_bypass_tx === 1'b1) ? wire_nil_dataout : ni; assign wire_nlOi_dataout = (rpipeline_bypass_tx === 1'b1) ? wire_nli_dataout : n1l; assign fifo_select_out_pipe = wire_nllO_dataout, n0ll = 1'b1, rd_enable_out_pipe = wire_nlli_dataout, tx_div2_sync_out_pipe = wire_nlOi_dataout, wr_enable_out_pipe = wire_nlll_dataout; endmodule //stratixiv_hssi_tx_digi_iq_pipe_tx //synopsys translate_on //VALID FILE `timescale 1ps / 1ps module stratixiv_hssi_tx_digi (txpcs_rst, scan_mode, txd, pld_tx_clk, polinv_tx, rev_loop_data, wrenable_tx, rddisable_tx, phfifourst_tx, txdetectrxloopback, powerdown, revloopback, txswing, pcs_txdeemph, pcs_txmargin, rxpolarity, polinv_rx, full_tx, empty_tx, tx_data_ts, tx_ctl_ts, refclk_pma, txpma_local_clk, tx_clk_out, tx_data_tc, tx_ctl_tc, pudr, rd_enable_sync, refclk_b, txlp20b, tx_pipe_clk, encoder_testbus, tx_ctrl_testbus, tx_pipe_soft_reset, tx_pipe_electidle, txdetectrxloopback_int, powerdown_int, revloopback_int, phfifo_txswing, phfifo_txdeemph, phfifo_txmargin, rxpolarity_int, polinv_rx_int, rrev_loopbk, rev_loopbk, eidleinfersel, gray_eidleinfersel,rbisten_tx, rforce_disp, rib_force_disp, rforce_echar, rforce_kchar, rendec_tx, rge_xaui_tx, rdwidth_tx, rtxfifo_dis, rcascaded_8b10b_en_tx, rprbsen_tx, rprbs_sel, rbist_sel, rcxpat_chnl_en, renpolinv_tx, rphfifopldentx, rphfifoursttx, rfreerun_tx, rtxwrclksel, rtxrdclksel, renbitrev_tx, rensymswap_tx, r8b10b_enc_ibm_en, rtxfifo_lowlatency_en, rpmadwidth_tx, rpma_doublewidth_tx, rtx_pipe_enable, rindv_tx, rendec_data_sel_tx, rtxpcsbypass_en, rtxpcsclkpwdn, rauto_speed_ena, rfreq_sel, gen2ngen1, gen2ngen1_bundle, rcid_pattern_tx, rcid_len_tx, tx_div2_sync_in_centrl, tx_div2_sync_in_quad_up, tx_div2_sync_in_quad_down, wr_enable_in_centrl, wr_enable_in_quad_up, wr_enable_in_quad_down, rd_enable_in_centrl, rd_enable_in_quad_up, rd_enable_in_quad_down, fifo_select_in_centrl, fifo_select_in_quad_up, fifo_select_in_quad_down, dis_pc_byte, reset_pc_ptrs, reset_pc_ptrs_in_centrl, reset_pc_ptrs_in_quad_up, reset_pc_ptrs_in_quad_down, tx_div2_sync_in_pipe_quad_up, tx_div2_sync_in_pipe_quad_down, wr_enable_in_pipe_quad_up, wr_enable_in_pipe_quad_down, rd_enable_in_pipe_quad_up, rd_enable_in_pipe_quad_down, fifo_select_in_pipe_quad_up, fifo_select_in_pipe_quad_down, rmaster_tx, rmaster_up_tx, rself_sw_en_tx, rpipeline_bypass_tx, rphfifo_regmode_tx, rtxbitslip_en, tx_div2_sync_out_pipe_up, fifo_select_out_pipe_up, wr_enable_out_pipe_up, rd_enable_out_pipe_up, tx_div2_sync_out_pipe_down, fifo_select_out_pipe_down, wr_enable_out_pipe_down, rd_enable_out_pipe_down, prbs_cid_en, tx_boundary_sel ); // Reset inputs input txpcs_rst; // TX PCS resets // Scan inputs input scan_mode; // 1'b1 = scan mode active; // 1'b0 = normal mode // TX PCS channel inputs/outputs input [43:0] txd; // TXD data bus from PLD input pld_tx_clk; // XGMII tx clock for this lane from PLD input polinv_tx; // TX polarity inversion dynamic control signal input [7:0] tx_data_ts; // 8-bit tx data from 10G ethernet // tx state machine (tx_sm) input tx_ctl_ts; // 1-bit tx control from 10G ethernet tx state machine (tx_sm) input refclk_pma; // Global parallel clock from TX PLL input txpma_local_clk; // Individual TX PMA clock from TX PMA Extension input rev_loopbk; // Dynamic signal causes reverse loopback input [19:0] rev_loop_data; // 10 bit data from RX rate matching FIFO, reverse loopback input wrenable_tx; // TX phase comp. FIFO write enable control signal input rddisable_tx; // TX phase comp. FIFO read disable control signal input phfifourst_tx; // TX phase comp. FIFO user reset // TX PIPE interface signals input txdetectrxloopback; //input txelecidle; txd[9] //input txcompliance; txd[10] and txd[32] input [1:0] powerdown; input revloopback; // push through TX Phase Comp FIFO input txswing; input pcs_txdeemph; input [2:0] pcs_txmargin; // RX PIPE interface signals input rxpolarity; input polinv_rx; input [2:0] eidleinfersel; input rtxpcsclkpwdn; input rauto_speed_ena; input rfreq_sel; input gen2ngen1; input gen2ngen1_bundle; input prbs_cid_en; //PRBS-CID dynamic signal input [4:0] tx_boundary_sel; output full_tx; // TX Phase comp. FIFO full flag output empty_tx; // TX Phase comp. FIFO empty flag output tx_clk_out; output [7:0] tx_data_tc; // 8-bit tx data from tx_ctrl to XAUI TX SM output tx_ctl_tc; // TX control/TX data bit 8 from tx_ctrl to XAUI TX SM output [19:0] pudr; // TX PCS 20-bit code group bus to TX PMA output rd_enable_sync; output refclk_b; output [19:0] txlp20b; // tx 20-bit code group bus to RX PCS for loopback output tx_pipe_clk; // TX PIPE interface clock output [9:0] encoder_testbus; // Test bus from 8B10B encoder output [9:0] tx_ctrl_testbus; // Test bus from TX FIFO output tx_pipe_soft_reset; // TX PIPE soft reset from TX FIFO output tx_pipe_electidle; // TxElecIdle output from TX FIFO // TX PIPE interface signals output txdetectrxloopback_int; //output txelecidle; txd[9] //output txcompliance; txd[10] and txd[32] output [1:0] powerdown_int; output revloopback_int; // push through TX Phase Comp FIFO output phfifo_txswing; output phfifo_txdeemph; output [2:0] phfifo_txmargin; // RX PIPE interface signals output rxpolarity_int; output polinv_rx_int; output [2:0] gray_eidleinfersel; // TX PCS CRAMs input rrev_loopbk; // CRAM - Enable dynamic Reverse, PIPE mode input rbisten_tx; // ENBIST CRAM input rforce_disp; // Acting with TXD[9, 19] forces current disparity to 1 or 0 input rib_force_disp; // Disparity force CRAM in IB mode input rforce_echar; // Force /E/ char CRAM input rforce_kchar; // Force /K/ char CRAM input rendec_tx; // Enable 8B/10B encoder CRAM input rge_xaui_tx; // GIGE Idle test enable CRAM input rdwidth_tx; // TX parallel interface data width CRAM input rtxfifo_dis; // TX FIFO disable CRAM input rcascaded_8b10b_en_tx; // Caascaded 8b/10b encoder enable CRAM input rprbsen_tx; // PRBS generator enable CRAM input [2:0] rprbs_sel; // PRBS selection CRAM input [1:0] rbist_sel; // BIST selection CRAM input [1:0] rcxpat_chnl_en; // CRPAT or CJPAT selection CRAM input renpolinv_tx; // TX Polarity inversion enable CRAM input rphfifopldentx; // TX phase comp. FIFO PLD read/write enable CRAM input rphfifoursttx; // TX phase comp. FIFO user reset enable CRAM input rfreerun_tx; // TX_CLK out free running during TX PCS reset enable CRAM input rtxwrclksel; // TX FIFO write clock selection CRAM input rtxrdclksel; // TX FIFO read clock selection CRAM input renbitrev_tx; // TX bit reversal enable CRAM input rensymswap_tx; // TX symbol swap enable CRAM input r8b10b_enc_ibm_en; // 8B10B Encoder fix enable CRAM input rtxfifo_lowlatency_en; // TX FIFO low latency enable CRAM input rpmadwidth_tx; // TX PCS to TX PMA data width selection CRAM input rpma_doublewidth_tx; // PCS/PMA double width (16/20) selection CRAM input rtx_pipe_enable; // TX PIPE enable CRAM input rcid_pattern_tx; // CID pattern to be 0 or 1 input [7:0] rcid_len_tx; // Length of CID pattern in cycles // Common PCS CRAMs input rindv_tx; // TX SM bypassing CRAM input rendec_data_sel_tx; // TX 8B10B encoder data in selection CRAM input rtxpcsbypass_en; // CRAM for enable low-latency PCS bypass mode // new signal inputs for bundling input tx_div2_sync_in_centrl; input tx_div2_sync_in_quad_up; input tx_div2_sync_in_quad_down; input wr_enable_in_centrl; input wr_enable_in_quad_up; input wr_enable_in_quad_down; input rd_enable_in_centrl; input rd_enable_in_quad_up; input rd_enable_in_quad_down; input fifo_select_in_centrl; input fifo_select_in_quad_up; input fifo_select_in_quad_down; input reset_pc_ptrs; input reset_pc_ptrs_in_centrl; input reset_pc_ptrs_in_quad_up; input reset_pc_ptrs_in_quad_down; input tx_div2_sync_in_pipe_quad_up; input tx_div2_sync_in_pipe_quad_down; input wr_enable_in_pipe_quad_up; input wr_enable_in_pipe_quad_down; input rd_enable_in_pipe_quad_up; input rd_enable_in_pipe_quad_down; input fifo_select_in_pipe_quad_up; input fifo_select_in_pipe_quad_down; input dis_pc_byte; // new MDIO inputs for bundling and auto speed input rmaster_tx; input rmaster_up_tx; input rself_sw_en_tx; input rpipeline_bypass_tx; input rphfifo_regmode_tx; // new outputs for bundling and auto speed output tx_div2_sync_out_pipe_up; output fifo_select_out_pipe_up; output wr_enable_out_pipe_up; output rd_enable_out_pipe_up; output tx_div2_sync_out_pipe_down; output fifo_select_out_pipe_down; output wr_enable_out_pipe_down; output rd_enable_out_pipe_down; // new signals in this module for bundling and auto speed wire refclk_b_raw; wire wr_clk_pos_raw; wire fifo_rd_clk_raw; wire nc_new_bundle1; wire nc_new_bundle2; wire nc_new_bundle3; wire fifo_select_out_testbus; //CRAM for TX bitslip input rtxbitslip_en; // removed // txfifo_shared_sig_in_ch0 // txfifo_shared_sig_in_q0_ch0 // rphfifo_master_sel_tx // txfifo_shared_sig_out // Wiring section wire refclk_b; wire wr_clk_pos; wire fifo_rd_clk; wire soft_reset_wclk1; wire [7:0] tx_data_tc_high; // high 8-bit tx data from tx_ctrl wire [7:0] tx_data_tc; // low 8-bit tx data from tx_ctrl wire tx_ctl_tc_high; // high tx control/tx data bit 8 from tx_ctrl wire tx_ctl_tc; // low tx control/tx data bit 8 from tx_ctrl wire rd_enable_sync; wire [1:0] tx_ctl_pre_en; wire [15:0] tx_data_pre_en; wire [1:0] tx_data_9_pre_en; wire [15:0] tx_data_sg; // 16-bit data sequence generated by bist_gen. wire [1:0] tx_control_sg; // 2-bit control sequence generated by selftest_gen. wire [1:0] tx_data_9_tc; // tx data bit 9 from tx_ctrl wire [19:0] tx_data_pg; // 20-bit tx code group generated by prbs_gen wire soft_reset_int; wire [1:0] k_det, d21_5_eq_n, d2_2_eq_n; wire [1:0] txd_extend_tc; // Extend txd by 2 bits. Used to force disparity. This will go to the encoder. // THis is input from the PLD Fabric wire [1:0] disp_out_3b; // Disparity output from encoder for testbus wire wr_enable2; wire [2:0] wptr_bin; wire rd_enable2; wire [2:0] rptr_bin; wire [15:0] tx_data_tc_temp; wire [1:0] tx_ctl_tc_temp; // Gated soft reset by scan_mode signal //assign soft_reset_int = (scan_mode) ? 1'b0 : txpcs_rst; assign soft_reset_int = txpcs_rst; // TX PIPE interface clock //assign tx_pipe_clk = wr_clk_pos; assign tx_pipe_clk = fifo_rd_clk; // Encoder testbus assign encoder_testbus = {disp_out_3b, pudr[7:0]}; // TX FIFO testbus assign tx_ctrl_testbus = {1'b0, fifo_select_out_testbus, wr_enable2, wptr_bin, rd_enable2, rptr_bin}; // Clock selection module stratixiv_hssi_tx_digi_txclk_ctl txclk_ctl_1 ( .pld_tx_clk(pld_tx_clk), .refclk_pma(refclk_pma), .txpma_local_clk(txpma_local_clk), .txrst(txpcs_rst), .scan_mode(scan_mode), .gen2ngen1(gen2ngen1), .gen2ngen1_bundle(gen2ngen1_bundle), .tx_div2_sync_centrl(tx_div2_sync_in_centrl), .tx_div2_sync_quad_up(tx_div2_sync_in_quad_up), .tx_div2_sync_quad_down(tx_div2_sync_in_quad_down), .rindv_tx(rindv_tx), .rtxwrclksel(rtxwrclksel), .rtxrdclksel(rtxrdclksel), .rdwidth_tx(rdwidth_tx), .rfreerun_tx(rfreerun_tx), .rauto_speed_ena(rauto_speed_ena), .rfreq_sel(rfreq_sel), .rtxpcsclkpwdn(rtxpcsclkpwdn), .rmaster_tx(rmaster_tx), .rmaster_up_tx(rmaster_up_tx), .rself_sw_en_tx(rself_sw_en_tx), .refclk_b(refclk_b), .wr_clk_pos(wr_clk_pos), .fifo_rd_clk(fifo_rd_clk), .tx_clk_out(tx_clk_out), .refclk_b_raw(refclk_b_raw), .wr_clk_pos_raw(wr_clk_pos_raw), .fifo_rd_clk_raw(fifo_rd_clk_raw), .tx_div2_sync_out(nc_new_bundle1) ); // TX Phase compensation FIFO module stratixiv_hssi_tx_digi_tx_ctrl tx_ctrl_1 ( .soft_reset (soft_reset_int), .fifo_wr_clk (wr_clk_pos), .fifo_rd_clk (fifo_rd_clk), .refclk_b_in (refclk_b), .scan_mode(scan_mode), .rindv_tx (rindv_tx), .p_rlpbk (1'b0), .selftest_en (rbisten_tx), .rdwidth_tx (rdwidth_tx), // S. Park 11/29/07 - Phase FIFO bypass feature removed // .txfifo_dis (rtxfifo_dis), .txfifo_dis (1'b0), .rtxfifo_urst_en(rphfifoursttx), .txfifo_urst(phfifourst_tx), .rtxfifo_lowlatency_en(rtxfifo_lowlatency_en), .rtxphfifopldctl_en(rphfifopldentx), .rtx_pipe_enable(rtx_pipe_enable), .pld_we(wrenable_tx), .pld_rd_dis(rddisable_tx), .txd ({txd[42:33],txd[31:22],txd[20:11],txd[9:0]}), .txd_extend ({txd[43],txd[32],txd[21],txd[10]}), .rforce_disp (rforce_disp), .tx_data_sg ({16'h0000,tx_data_sg}), .tx_control_sg ({2'b00,tx_control_sg}), .rxd_lpbk (40'h0000000000), .redund_ctl (4'h0), .txd_redun (40'h0000000000), .rforce_kchar (rforce_kchar), .rforce_echar (rforce_echar), .rtxpcsbypass_en (rtxpcsbypass_en), // TX PIPE signals .txdetectrxloopback (txdetectrxloopback), .powerdown (powerdown), .revloopback (revloopback), .txswing (txswing), .txdeemph (pcs_txdeemph), .txmargin (pcs_txmargin), // RX PIPE signals .rxpolarity (rxpolarity), .polinv_rx (polinv_rx), .eidleinfersel (eidleinfersel), .reset_pc_ptrs(reset_pc_ptrs), .reset_pc_ptrs_centrl(reset_pc_ptrs_in_centrl), .reset_pc_ptrs_quad_up(reset_pc_ptrs_in_quad_up), .reset_pc_ptrs_quad_down(reset_pc_ptrs_in_quad_down), .gen2ngen1(gen2ngen1), .gen2ngen1_bundle(gen2ngen1_bundle), .dis_pc_byte(dis_pc_byte), .wr_enable_centrl(wr_enable_in_centrl), .wr_enable_quad_up(wr_enable_in_quad_up), .wr_enable_quad_down(wr_enable_in_quad_down), .rd_enable_centrl(rd_enable_in_centrl), .rd_enable_quad_up(rd_enable_in_quad_up), .rd_enable_quad_down(rd_enable_in_quad_down), .fifo_select_in_centrl(fifo_select_in_centrl), .fifo_select_in_quad_up(fifo_select_in_quad_up), .fifo_select_in_quad_down(fifo_select_in_quad_down), .rauto_speed_ena(rauto_speed_ena), .rfreq_sel(rfreq_sel), .rphfifo_regmode_tx(rphfifo_regmode_tx), .rmaster_tx(rmaster_tx), .rmaster_up_tx(rmaster_up_tx), .txd_extend_tc (txd_extend_tc), .tx_data_tc (tx_data_tc_temp), .tx_ctl_tc (tx_ctl_tc_temp), .tx_data_9_tc (tx_data_9_tc), .rd_enable_sync (rd_enable_sync), .k_det (k_det), .d21_5_eq_n (d21_5_eq_n), .d2_2_eq_n (d2_2_eq_n), .wr_enable_out(nc_new_bundle2), .rd_enable_out(nc_new_bundle3), .fifo_select_out (fifo_select_out_testbus), .ph_fifo_full(full_tx), .ph_fifo_empty(empty_tx), .soft_reset_wclk1(soft_reset_wclk1), .soft_reset_rclk1(tx_pipe_soft_reset), .pipe_electric_idle(tx_pipe_electidle), // TX PIPE signals .txdetectrxloopback_int (txdetectrxloopback_int), .powerdown_int (powerdown_int), .revloopback_int (revloopback_int), .gray_eidleinfersel (gray_eidleinfersel), .phfifo_txswing (phfifo_txswing), .phfifo_txdeemph (phfifo_txdeemph), .phfifo_txmargin (phfifo_txmargin), // RX PIPE signals .rxpolarity_int (rxpolarity_int), .polinv_rx_int (polinv_rx_int), .wr_enable2(wr_enable2), .wptr_bin(wptr_bin), .rd_enable2(rd_enable2), .rptr_bin(rptr_bin) ); assign tx_data_tc_high = tx_data_tc_temp[15:8]; assign tx_data_tc = tx_data_tc_temp[7:0]; assign tx_ctl_tc_high = tx_ctl_tc_temp[1]; assign tx_ctl_tc = tx_ctl_tc_temp[0]; // BIST generator module stratixiv_hssi_tx_digi_bist_gen selftest_gen_1 ( .tx_clk(wr_clk_pos), .soft_reset(soft_reset_wclk1), .rbisten_tx(rbisten_tx), .rpmadwidth_tx(rpmadwidth_tx), .rpma_doublewidth_tx(rpma_doublewidth_tx), .rdwidth_tx(rdwidth_tx), .rbist_sel(rbist_sel), .rcxpat_chnl_sel(rcxpat_chnl_en), .bist_data_sg(tx_data_sg), .bist_ctl_sg(tx_control_sg) ); // PRBS generator module stratixiv_hssi_tx_digi_prbs_gen prbs_gen_1 ( .tx_clk(refclk_b), .soft_reset(soft_reset_int), .rprbs_en_tx(rprbsen_tx), .rpmadwidth_tx(rpmadwidth_tx), .rpma_doublewidth_tx(rpma_doublewidth_tx), .cid_en(prbs_cid_en), .rcid_len(rcid_len_tx), .rcid_pattern(rcid_pattern_tx), .rprbs_sel(rprbs_sel), .prbs_out(tx_data_pg) ); // 8B-10B Encoder module stratixiv_hssi_tx_digi_enc_chnl_top enc_chnl_top_1 ( .rst(soft_reset_int), .clk(refclk_b), .cascaded_8b10b_en(rcascaded_8b10b_en_tx), .rendec_data_sel_tx(rendec_data_sel_tx), .rrev_loopbk(rrev_loopbk), .rev_loopbk(rev_loopbk), .dwidth(rpmadwidth_tx), .doublewidth(rpma_doublewidth_tx), .endec(rendec_tx), .ge_xaui_sel(rge_xaui_tx), .rforce_disp(rforce_disp), .ib_force_disparity(rib_force_disp), .prbs_en(rprbsen_tx), .r8b10b_enc_ibm_en(r8b10b_enc_ibm_en), .rev_loop_data(rev_loop_data), .tx_ctl_ts(tx_ctl_ts), .tx_ctl_tc({tx_ctl_tc_high,tx_ctl_tc}), .tx_data_ts(tx_data_ts), .txd_extend_tc(txd_extend_tc), .tx_data_tc({tx_data_tc_high,tx_data_tc}), .tx_data_9_tc(tx_data_9_tc), .tx_data_pg(tx_data_pg), .k_det(k_det[0]), .d21_5_eq_n(d21_5_eq_n[0]), .d2_2_eq_n(d2_2_eq_n[0]), .renpolinv_tx(renpolinv_tx), .enpolinv_tx(polinv_tx), .renbitrev_tx(renbitrev_tx), .rensymswap_tx(rensymswap_tx), .rtxbitslip_en(rtxbitslip_en), .tx_boundary_sel(tx_boundary_sel), .pudr(pudr), .txlp20b(txlp20b), .tx_data_pre_en(tx_data_pre_en), .tx_data_9_pre_en(tx_data_9_pre_en), .tx_ctl_pre_en(tx_ctl_pre_en), .disp_out_3b(disp_out_3b) ); stratixiv_hssi_tx_digi_iq_pipe_tx iqp_out_up ( .refclk_b_raw(refclk_b_raw), .wr_clk_pos_raw(wr_clk_pos_raw), .fifo_rd_clk_raw(fifo_rd_clk_raw), .txrst(txpcs_rst), .soft_reset_rclk1(tx_pipe_soft_reset), .soft_reset_wclk1(soft_reset_wclk1), .tx_div2_sync_in_centrl(tx_div2_sync_in_centrl), .tx_div2_sync_in_pipe_quad_up(1'b0), .tx_div2_sync_in_pipe_quad_down(tx_div2_sync_in_pipe_quad_down), .wr_enable_in_centrl(wr_enable_in_centrl), .wr_enable_in_pipe_quad_up(1'b0), .wr_enable_in_pipe_quad_down(wr_enable_in_pipe_quad_down), .rd_enable_in_centrl(rd_enable_in_centrl), .rd_enable_in_pipe_quad_up(1'b0), .rd_enable_in_pipe_quad_down(rd_enable_in_pipe_quad_down), .fifo_select_in_centrl(fifo_select_in_centrl), .fifo_select_in_pipe_quad_up(1'b0), .fifo_select_in_pipe_quad_down(fifo_select_in_pipe_quad_down), .rmaster_tx(rmaster_tx), .rmaster_up_tx(rmaster_up_tx), .rpipeline_bypass_tx(rpipeline_bypass_tx), .rfreerun_tx(rfreerun_tx), .tx_div2_sync_out_pipe(tx_div2_sync_out_pipe_up), .fifo_select_out_pipe(fifo_select_out_pipe_up), .wr_enable_out_pipe(wr_enable_out_pipe_up), .rd_enable_out_pipe(rd_enable_out_pipe_up) ); stratixiv_hssi_tx_digi_iq_pipe_tx iqp_out_down ( .refclk_b_raw(refclk_b_raw), .wr_clk_pos_raw(wr_clk_pos_raw), .fifo_rd_clk_raw(fifo_rd_clk_raw), .txrst(txpcs_rst), .soft_reset_rclk1(tx_pipe_soft_reset), .soft_reset_wclk1(soft_reset_wclk1), .tx_div2_sync_in_centrl(tx_div2_sync_in_centrl), .tx_div2_sync_in_pipe_quad_up(tx_div2_sync_in_pipe_quad_up), .tx_div2_sync_in_pipe_quad_down(1'b0), .wr_enable_in_centrl(wr_enable_in_centrl), .wr_enable_in_pipe_quad_up(wr_enable_in_pipe_quad_up), .wr_enable_in_pipe_quad_down(1'b0), .rd_enable_in_centrl(rd_enable_in_centrl), .rd_enable_in_pipe_quad_up(rd_enable_in_pipe_quad_up), .rd_enable_in_pipe_quad_down(1'b0), .fifo_select_in_centrl(fifo_select_in_centrl), .fifo_select_in_pipe_quad_up(fifo_select_in_pipe_quad_up), .fifo_select_in_pipe_quad_down(1'b0), .rmaster_tx(rmaster_tx), .rmaster_up_tx(rmaster_up_tx), .rpipeline_bypass_tx(rpipeline_bypass_tx), .rfreerun_tx(rfreerun_tx), .tx_div2_sync_out_pipe(tx_div2_sync_out_pipe_down), .fifo_select_out_pipe(fifo_select_out_pipe_down), .wr_enable_out_pipe(wr_enable_out_pipe_down), .rd_enable_out_pipe(rd_enable_out_pipe_down) ); endmodule // digi_tx //////////////////////////////////////////////////////////////////////////////// // hssi_module: transmitter **************************************************// //////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////// // DPRIO INDEX TABLE --------------------------------------------------------// /////////////////////////////////////////////////////////////////////////////// // Table1: PCS Per Channel TX Control Register 1 for Channel 0 `define rforce_disp_TXPCS_IDX_0 0 `define rrev_loopbk_TXPCS_IDX_0 1 `define rtxrdclksel_TXPCS_IDX_0 2 `define rtxwrclksel_TXPCS_IDX_0 3 `define rfreerun_tx_TXPCS_IDX_0 4 `define rtxurstpcs_TXPCS_IDX_0 5 `define reserved_0_TB1_TXPCS_IDX_0 6 `define rphfifoursttx_TXPCS_IDX_0 7 `define rphfifopldentx_TXPCS_IDX_0 8 `define rge_xaui_tx_TXPCS_IDX_0 9 `define rdwidth_tx_TXPCS_IDX_0 10 `define rtxfifo_lowlatency_en_TXPCS_IDX_0 11 `define rib_force_disp_TXPCS_IDX_0 12 `define rtxfifo_dis_TXPCS_IDX_0 13 `define rforce_echar_TXPCS_IDX_0 14 `define rforce_kchar_TXPCS_IDX_0 15 // Table2: PCS Per Channel TX Control Register 2 for Channel 0 `define rtxpcsbypass_en_TXPCS_IDX_0 16 `define rcxpat_chnl_en_TXPCS_IDX_0 17 `define rcxpat_chnl_en_TXPCS_IDX_1 18 `define rbist_sel_TXPCS_IDX_0 19 `define rbist_sel_TXPCS_IDX_1 20 `define rbisten_tx_TXPCS_IDX_0 21 `define rprbs_sel_TXPCS_IDX_0 22 `define rprbs_sel_TXPCS_IDX_1 23 `define rprbs_sel_TXPCS_IDX_2 24 `define rprbsen_tx_TXPCS_IDX_0 25 `define renbitrev_tx_TXPCS_IDX_0 26 `define renpolinv_tx_TXPCS_IDX_0 27 `define rensymswap_tx_TXPCS_IDX_0 28 `define rcascaded_8b10b_en_tx_TXPCS_IDX_0 29 `define r8b10b_enc_ibm_en_TXPCS_IDX_0 30 `define rendec_tx_TXPCS_IDX_0 31 // Table3: PCS Per Channel TX Control Register 3 for Channel 0 `define reserved_0_TB3_TXPCS_IDX_0 32 `define rcid_len_tx_TXPCS_IDX_0 33 `define rcid_len_tx_TXPCS_IDX_1 34 `define rcid_len_tx_TXPCS_IDX_2 35 `define rcid_len_tx_TXPCS_IDX_3 36 `define rcid_len_tx_TXPCS_IDX_4 37 `define rcid_len_tx_TXPCS_IDX_5 38 `define rcid_len_tx_TXPCS_IDX_6 39 `define rcid_len_tx_TXPCS_IDX_7 40 `define rcid_pattern_tx_TXPCS_IDX_0 41 `define rtxpcsclkpwdn_TXPCS_IDX_0 42 `define rtxswing_sel_ena_TXPCS_IDX_0 43 `define rtx_elec_idle_delay_TXPCS_IDX_0 44 `define rtx_elec_idle_delay_TXPCS_IDX_1 45 `define rtx_elec_idle_delay_TXPCS_IDX_2 46 `define rtx_pipe_enable_TXPCS_IDX_0 47 // Table4: PCS Per Channel TX Control Register 4 for Channel 0 `define reserved_0_TB4_TXPCS_IDX_0 48 `define reserved_0_TB4_TXPCS_IDX_1 49 `define reserved_0_TB4_TXPCS_IDX_2 50 `define reserved_0_TB4_TXPCS_IDX_3 51 `define reserved_0_TB4_TXPCS_IDX_4 52 `define reserved_0_TB4_TXPCS_IDX_5 53 `define reserved_0_TB4_TXPCS_IDX_6 54 `define reserved_0_TB4_TXPCS_IDX_7 55 `define reserved_0_TB4_TXPCS_IDX_8 56 `define reserved_0_TB4_TXPCS_IDX_9 57 `define reserved_0_TB4_TXPCS_IDX_10 58 `define reserved_0_TB4_TXPCS_IDX_11 59 `define rtxbitslip_en_TXPCS_IDX_0 60 `define rphfifo_regmode_tx_TXPCS_IDX_0 61 `define rpipeline_bypass_tx_TXPCS_IDX_0 62 `define rself_sw_en_tx_TXPCS_IDX_0 63 // Existing `define rauto_speed_ena_TX_IDX 64 `define rendec_data_sel_tx_TX_IDX 65 `define rfreq_sel_TX_IDX 66 `define rhip_ena_TX_IDX 67 `define rindv_tx_TX_IDX 68 `define rphfifo_master_sel_tx_TX_IDX 69 `define rpma_doublewidth_tx_TX_IDX 70 `define rpmadwidth_tx_TX_IDX 71 `define rtx_cmu_sel_TX_IDX 72 `define rmaster_tx_TX_IDX 73 `define rmaster_up_tx_TX_IDX 74 `timescale 1 ps / 1 ps module stratixiv_hssi_tx_pcs ( bitslipboundaryselect, coreclk, ctrlenable, datain, datainfull, detectrxloop, digitalreset, dispval, dpriodisable, dprioin, elecidleinfersel, enrevparallellpbk, forcedisp, forcedispcompliance, //to remove forceelecidle, freezptr, hipdatain, hipdetectrxloop, hipelecidleinfersel, hipforceelecidle, hippowerdn, hiptxdeemph, hiptxmargin, invpol, iqpphfifoxnbytesel, iqpphfifoxnrdclk, iqpphfifoxnrdenable, iqpphfifoxnwrenable, localrefclk, phfifobyteserdisable, phfifoptrsreset, phfiforddisable, phfiforeset, phfifowrenable, phfifox4bytesel, phfifox4rdclk, phfifox4rdenable, phfifox4wrenable, phfifoxnbottombytesel, phfifoxnbottomrdclk, phfifoxnbottomrdenable, phfifoxnbottomwrenable, phfifoxnbytesel, phfifoxnptrsreset, phfifoxnrdclk, phfifoxnrdenable, phfifoxntopbytesel, phfifoxntoprdclk, phfifoxntoprdenable, phfifoxntopwrenable, phfifoxnwrenable, pipestatetransdone, pipetxdeemph, // RTL=txdeemph, pipetxmargin, // RTL=txmargin[2:0] pipetxswing, // RTL=txswing powerdn, prbscidenable, quadreset, rateswitch, // RTL=rate rateswitchisdone, rateswitchxndone, refclk, revparallelfdbk, xgmctrl, xgmdatain, clkout, coreclkout, dataout, dprioout, forceelecidleout, grayelecidleinferselout, hiptxclkout, iqpphfifobyteselout, iqpphfifordclkout, iqpphfifordenableout, iqpphfifowrenableout, parallelfdbkout, phfifobyteselout, phfifooverflow, phfifordclkout, phfiforddisableout, phfifordenableout, phfiforesetout, phfifounderflow, phfifowrenableout, pipeenrevparallellpbkout, pipepowerdownout, pipepowerstateout, rateswitchout, // RTL=rate_int rdenablesync, txdetectrx, xgmctrlenable, xgmdataout ); `define STRATIXIV_HSSI_TX_PCS_ALPHA_TOLOWER_WORD_LENGTH 25 parameter lpm_type = "stratixiv_hssi_tx_pcs"; parameter allow_polarity_inversion = "false"; parameter auto_spd_self_switch_enable = "false"; parameter bitslip_enable = "false"; parameter channel_bonding = "none"; // none, x8, x4 parameter channel_number = 0; parameter channel_width = 8; parameter core_clock_0ppm = "false"; parameter datapath_low_latency_mode = "false"; parameter datapath_protocol = "basic"; //replaced by protocol_hint parameter disable_ph_low_latency_mode = "false"; parameter disparity_mode = "none"; // legacy, new, none parameter dprio_config_mode = 6'h00; parameter elec_idle_delay = 6; // new in 6.0 <3-6> parameter enable_bit_reversal = "false"; parameter enable_idle_selection = "false"; parameter enable_phfifo_bypass = "false"; parameter enable_reverse_parallel_loopback = "false"; parameter enable_self_test_mode = "false"; parameter enable_symbol_swap = "false"; parameter enc_8b_10b_compatibility_mode = "true"; parameter enc_8b_10b_mode = "none"; // cascade, normal, none parameter force_echar = "false"; parameter force_kchar = "false"; parameter hip_enable = "false"; parameter iqp_bypass = "false"; parameter iqp_ph_fifo_xn_select = 9999 ; parameter logical_channel_address = 0 ; parameter ph_fifo_reg_mode = "false"; parameter ph_fifo_reset_enable = "false"; parameter ph_fifo_user_ctrl_enable = "false"; parameter ph_fifo_xn_mapping0 = "none"; parameter ph_fifo_xn_mapping1 = "none"; parameter ph_fifo_xn_mapping2 = "none"; parameter ph_fifo_xn_select = 9999 ; parameter pipe_auto_speed_nego_enable = "false"; parameter pipe_freq_scale_mode = "data width"; parameter pipe_voltage_swing_control = "false"; parameter prbs_all_one_detect = "false"; parameter prbs_cid_pattern = "false"; parameter prbs_cid_pattern_length = 0 ; parameter protocol_hint = "basic"; parameter refclk_select = "local"; // cmu_clk_divider parameter reset_clock_output_during_digital_reset = "false"; parameter self_test_mode = "incremental"; parameter use_double_data_mode = "false"; parameter use_serializer_double_data_mode = "false"; parameter wr_clk_mux_select = "core_clk"; // INT_CLK // int_clk // SIMULATION_ONLY_PARAMETERS_BEGIN parameter use_top_quad_as_mater = "true"; // NEW_PARAM todo: select top/bottom to provide phfifo pointers parameter dprio_width = 150; parameter migrated_from_prev_family = "false"; // SIMULATION_ONLY_PARAMETERS_END // LOCAL_PARAMETERS_BEGIN parameter mph_fifo_xn_mapping = (ph_fifo_xn_select == 0) ? ph_fifo_xn_mapping0 :(ph_fifo_xn_select == 1) ? ph_fifo_xn_mapping1 :(ph_fifo_xn_select == 2) ? ph_fifo_xn_mapping2 : "none"; parameter MPHFIFO_INDEX = (ph_fifo_xn_select == 0 || ph_fifo_xn_select == 1 || ph_fifo_xn_select == 2) ? ph_fifo_xn_select : 0; parameter MIQP_PHFIFO_INDEX = (ph_fifo_xn_select == 0 || ph_fifo_xn_select == 1) ? ph_fifo_xn_select : 0; parameter DPRIO_CHANNEL_INTERFACE_BIT = 4; // LOCAL_PARAMETERS_END input [4 : 0] bitslipboundaryselect; input coreclk; input [3 : 0] ctrlenable; input [39:0] datain; input [43:0] datainfull; input detectrxloop; input digitalreset; input [3 : 0] dispval; input dpriodisable; input [149 : 0] dprioin; input [2 : 0] elecidleinfersel; input enrevparallellpbk; input [3 : 0] forcedisp; //fix_width input forcedispcompliance; input forceelecidle; input freezptr; input [9 : 0] hipdatain; input hipdetectrxloop; input [2 : 0] hipelecidleinfersel; // hip_eidleinfersel of digi_chnl_hip_support input hipforceelecidle; input [1 : 0] hippowerdn; input hiptxdeemph; input [2 : 0] hiptxmargin; input invpol; input [1 : 0] iqpphfifoxnbytesel; input [1 : 0] iqpphfifoxnrdclk; input [1 : 0] iqpphfifoxnrdenable; input [1 : 0] iqpphfifoxnwrenable; input localrefclk; input phfifobyteserdisable; input phfifoptrsreset; input phfiforddisable; input phfiforeset; input phfifowrenable; input phfifox4bytesel; input phfifox4rdclk; input phfifox4rdenable; input phfifox4wrenable; input phfifoxnbottombytesel; input phfifoxnbottomrdclk; input phfifoxnbottomrdenable; input phfifoxnbottomwrenable; input [2 : 0] phfifoxnbytesel; input [2 : 0] phfifoxnptrsreset; input [2 : 0] phfifoxnrdclk; input [2 : 0] phfifoxnrdenable; input phfifoxntopbytesel; input phfifoxntoprdclk; input phfifoxntoprdenable; input phfifoxntopwrenable; input [2 : 0] phfifoxnwrenable; input pipestatetransdone; input pipetxdeemph; // RTL=txdeemph; input [2:0] pipetxmargin; // RTL=txmargin[2:0] input pipetxswing; // RTL=txswing input [1:0] powerdn; input prbscidenable; input quadreset; input rateswitch; input rateswitchisdone; input rateswitchxndone; input refclk; input [19:0] revparallelfdbk; input xgmctrl; input [7:0] xgmdatain; output clkout; output coreclkout; output [19:0] dataout; output [149 : 0] dprioout; output forceelecidleout; output [2 : 0] grayelecidleinferselout; //gray_eidleinfersel(2:0) output hiptxclkout; output iqpphfifobyteselout; output iqpphfifordclkout; output iqpphfifordenableout; output iqpphfifowrenableout; output [19:0] parallelfdbkout; output phfifooverflow; output phfifobyteselout; output phfifordclkout; output phfiforddisableout; output phfifordenableout; output phfiforesetout; output phfifounderflow; output phfifowrenableout; output pipeenrevparallellpbkout; output [1:0] pipepowerdownout; output [3:0] pipepowerstateout; output rateswitchout; output rdenablesync; output txdetectrx; output xgmctrlenable; output [7:0] xgmdataout; wire [3 : 0] tmp_ctrlenable; wire [39 : 0] tmp_datain; wire [3 : 0] tmp_dispval; wire [3 : 0] tmp_forcedisp; // --------------------------------------------------------------------------- // Initial CRAM // --------------------------------------------------------------------------- // atom level initial CRAM --------------------------------------------------- // Existing reg init_is_lane0; reg init_rauto_speed_ena; reg init_rclkcmpinsertpad; // rx only ========= pipe =========== reg init_rendec_data_sel_tx; reg init_rfreq_sel; reg init_rhip_ena; reg init_rindv_tx; reg init_rmaster_tx; reg init_rmaster_up_tx; reg init_rphfifo_master_sel_tx; reg init_rpma_doublewidth_tx; reg init_rpmadwidth_tx; reg init_rrdwidth_rx; // rx only reg init_rrx_detect_bypass; // rx only reg init_rrx_pipe_enable; // rx only reg init_rtx_cmu_sel; // added in 6.1 reg init_scan_mode; // PCS Per Channel TX Control Register 1 for Channel 0 reg init_rforce_disp; reg init_rrev_loopbk; reg init_rtxrdclksel; reg init_rtxwrclksel; reg init_rfreerun_tx; reg init_rtxurstpcs; reg init_reserved_0_TB1; reg init_rphfifoursttx; reg init_rphfifopldentx; reg init_rge_xaui_tx; reg init_rdwidth_tx; reg init_rtxfifo_lowlatency_en; reg init_rib_force_disp; reg init_rtxfifo_dis; reg init_rforce_echar; reg init_rforce_kchar; // PCS Per Channel TX Control Register 2 for Channel 0 reg init_rtxpcsbypass_en; reg [1:0] init_rcxpat_chnl_en; reg [1:0] init_rbist_sel; reg init_rbisten_tx; reg [2:0] init_rprbs_sel; reg init_rprbsen_tx; reg init_renbitrev_tx; reg init_renpolinv_tx; reg init_rensymswap_tx; reg init_rcascaded_8b10b_en_tx; reg init_r8b10b_enc_ibm_en; reg init_rendec_tx; // PCS Per Channel TX Control Register 3 for Channel 0 reg init_reserved_0_TB3; reg [7:0] init_rcid_len_tx; reg init_rcid_pattern_tx; reg init_rtxpcsclkpwdn; reg init_rtxswing_sel_ena; reg [2:0] init_rtx_elec_idle_delay; reg init_rtx_pipe_enable; // PCS Per Channel TX Control Register 4 for Channel 0 reg [11:0] init_reserved_0_TB4; reg init_rtxbitslip_en; reg init_rphfifo_regmode_tx; reg init_rpipeline_bypass_tx; reg init_rself_sw_en_tx; //////////////////////////////////////////////////////////////////////////////// // sub-block interface: pcs_reset ----------------------------------------// //////////////////////////////////////////////////////////////////////////////// wire pr_in_hard_reset; wire pr_in_clk_2_b; wire pr_in_refclk_b_in; wire pr_in_scan_mode; wire pr_in_rxpcs_rst; wire pr_in_txpcs_rst; wire pr_out_txrst_int; //////////////////////////////////////////////////////////////////////////////// // sub-block interface: chnl_hip_spt ----------------------------------------// //////////////////////////////////////////////////////////////////////////////// wire [2:0] hs_in_eidleinfersel_ch; wire [2:0] hs_in_hip_eidleinfersel_ch; wire [1:0] hs_in_hip_powerdown_ch; wire hs_in_hip_rate; wire hs_in_hip_rxpolarity; wire [9:0] hs_in_hip_txd_ch; wire hs_in_hip_txdeemph; wire hs_in_hip_txdetectrxloopback; wire hs_in_hip_txelecidle; wire [2:0] hs_in_hip_txmargin_ch; wire hs_in_pcs_phystatus; wire [8:0] hs_in_pcs_rxd_ch; wire hs_in_pcs_rxelecidle; wire [2:0] hs_in_pcs_rxstatus_ch; wire hs_in_pcs_rxvalid; wire [1:0] hs_in_powerdown_ch; wire hs_in_rate; wire hs_in_rhip_ena; wire hs_in_rxpolarity; wire [10:0] hs_in_txd_ch; wire hs_in_txdeemph; wire hs_in_txdetectrxloopback; wire [2:0] hs_in_txmargin_ch; wire hs_in_txpma_local_clk; wire hs_out_hip_phystatus; wire [8:0] hs_out_hip_rxd_ch; wire hs_out_hip_rxelecidle; wire [2:0] hs_out_hip_rxstatus_ch; wire hs_out_hip_rxvalid; wire hs_out_hip_tx_clk; wire [2:0] hs_out_pcs_eidleinfersel_ch; wire [1:0] hs_out_pcs_powerdown_ch; wire hs_out_pcs_rate; wire hs_out_pcs_rxpolarity; wire [10:0] hs_out_pcs_txd_ch; wire hs_out_pcs_txdeemph; wire hs_out_pcs_txdetectrxloopback; wire [2:0] hs_out_pcs_txmargin_ch; wire hs_out_phystatus; wire [8:0] hs_out_rxd_ch; wire hs_out_rxelecidle; wire [2:0] hs_out_rxstatus_ch; wire hs_out_rxvalid; //////////////////////////////////////////////////////////////////////////////// // sub-block interface: pipe_interface --------------------------------------// //////////////////////////////////////////////////////////////////////////////// // inputs wire pi_in_pipe_tx_clk; wire [1:0] pi_in_powerdown; wire pi_in_refclk_b; wire pi_in_refclk_b_reset_n; wire pi_in_revloopback; wire pi_in_state_transition_done; wire pi_in_tx_elec_idle_comp; wire pi_in_tx_pipe_reset_n; wire [43:0] pi_in_txd_ch; wire [43:0] pi_in_txd_ch_dprio; // new in 6.1 wire pi_in_txdetectrxloopback; wire pi_in_txelecidle; wire [43:0] pi_in_txd_ch_tmp; // before interleaving in dwidth_single PMA // outputs wire [3:0] pi_out_powerstate; // to top - both cmu and rx wire pi_out_rev_loopbk; // to TD wire pi_out_tx_elec_idle; // to tx PMA - TX sending electrical idle wire [43:0] pi_out_txd; wire pi_out_txdetectrx; // to tx PMA - RX_DET // new input in STRATIXIV - ww26.5 ===================================== // from PLD wire pi_in_txdeemph; wire [2:0] pi_in_txmargin; wire pi_in_txswing; // new output in STRATIXIV - ww26.5 ==================================== // exposed to digi_top wire pi_out_txdeemph_int; wire [2:0] pi_out_txmargin_int; wire pi_out_txswing_int; //////////////////////////////////////////////////////////////////////////////// // sub-block interface: tx digital ------------------------------------------// //////////////////////////////////////////////////////////////////////////////// // inputs wire td_in_phfifourst_tx; wire td_in_pld_tx_clk; wire td_in_polinv_tx; wire td_in_rddisable_tx; wire td_in_refclk_pma; wire [19:0] td_in_rev_loop_data; wire td_in_rev_loopbk; wire td_in_tx_ctl_ts; wire [7:0] td_in_tx_data_ts; wire [43:0] td_in_txd; wire td_in_txpcs_rst; wire td_in_txpma_local_clk; wire td_in_wrenable_tx; // new input in STRATIXIV - ww26.5 ====================================== // freeze pointer for TX/RX phase comp FIFO during freq negotiation // to tx_ctrl from rx_digi (auto_speed_neg sub-block) wire td_in_freeze_ptr; // to tx_ctrl from TX PMA local clock divider wire td_in_gen2ngen1; // to tx_ctrl from central clock divider wire td_in_gen2ngen1_bundle; // to tx_ctrl from PLD (RX polarity inversion dynamic control) // paired with polinv_tx // path: polinv_rx (pld) -> tx_digi (tx_ctrl after encoder) -> // (just a simple wire in tx_ctrl so leaving it out of tx) // rx_pipe (mux with rxpolarity) -> rx_digi (wordalign and decoder) wire td_in_polinv_rx; // to tx_ctrl from PLD // generating powerdown_int output feeding both rx_pipe and tx_pipe wire [1:0] td_in_powerdown; // to tx_ctrl from quad pcs top // generating rate_int output feeding rx_digi (auto_speed_neg) wire td_in_rate; // to tx_ctrl from quad pcs top // generating revloopback_int output feeding tx_pipe wire td_in_revloopback; // to tx_ctrl from quad pcs top (no functionality change) // path: rxpolarity (pld) -> tx_digi (tx_ctrl)-> // rx_pipe (muxing with polinv_rx) --> rx_digi wire td_in_rxpolarity; // to tx_ctrl from quad pcs top // (just a simple wire in tx_ctrl so leaving it out of tx) // generating txdetectrxloopback_int output feeding tx_pipe wire td_in_txdetectrxloopback; // new output in STRATIXIV - ww26.5 =================================== // to rx_digi muxed with rxpolarity_int wire td_out_polinv_rx_int; // to rx_pipe and tx_pipe wire [1:0] td_out_powerdown_int; // to tx_pipe wire td_out_revloopback_int; // to rx_digi (mux with polinv_rx_int) wire td_out_rxpolarity_int; // to tx_pipe wire td_out_txdetectrxloopback_int; // outputs wire td_out_empty_tx; wire [9:0] td_out_encoder_testbus; wire td_out_full_tx; wire [19:0] td_out_pudr; wire td_out_rd_enable_sync; wire td_out_refclk_b; wire td_out_tx_clk_out; wire td_out_tx_ctl_tc; wire [9:0] td_out_tx_ctrl_testbus; wire [7:0] td_out_tx_data_tc; wire td_out_tx_pipe_clk; wire td_out_tx_pipe_electidle; wire td_out_tx_pipe_soft_reset; wire [3:0] td_out_txfifo_shared_sig_out; wire [19:0] td_out_txlp20b; wire td_in_prbs_cid_en; //PRBS-CID dynamic signal wire [4:0] td_in_tx_boundary_sel; // new signal inputs for bundling wire td_in_tx_div2_sync_in_centrl; wire td_in_tx_div2_sync_in_quad_up; wire td_in_tx_div2_sync_in_quad_down; wire td_in_wr_enable_in_centrl; wire td_in_wr_enable_in_quad_up; wire td_in_wr_enable_in_quad_down; wire td_in_rd_enable_in_centrl; wire td_in_rd_enable_in_quad_up; wire td_in_rd_enable_in_quad_down; wire td_in_fifo_select_in_centrl; wire td_in_fifo_select_in_quad_up; wire td_in_fifo_select_in_quad_down; wire td_in_reset_pc_ptrs; wire td_in_reset_pc_ptrs_in_centrl; wire td_in_reset_pc_ptrs_in_quad_up; wire td_in_reset_pc_ptrs_in_quad_down; wire td_in_tx_div2_sync_in_pipe_quad_up; wire td_in_tx_div2_sync_in_pipe_quad_down; wire td_in_wr_enable_in_pipe_quad_up; wire td_in_wr_enable_in_pipe_quad_down; wire td_in_rd_enable_in_pipe_quad_up; wire td_in_rd_enable_in_pipe_quad_down; wire td_in_fifo_select_in_pipe_quad_up; wire td_in_fifo_select_in_pipe_quad_down; wire td_in_dis_pc_byte; // new outputs for bundling and auto speed wire td_out_tx_div2_sync_out_pipe; wire td_out_fifo_select_out_pipe; wire td_out_wr_enable_out_pipe; wire td_out_rd_enable_out_pipe; // push through TX Phase Comp FIFO wire td_in_txswing; wire td_in_pcs_txdeemph; wire [2:0] td_in_pcs_txmargin; // RX PIPE interface signals wire [2:0] td_in_eidleinfersel; // push through TX Phase Comp FIFO wire td_out_phfifo_txswing; wire td_out_phfifo_txdeemph; wire [2:0] td_out_phfifo_txmargin; // RX PIPE interface signals wire [2:0] td_out_gray_eidleinfersel; // new outputs for bundling and auto speed // splitting _out_pipe into _up and _down wire td_out_tx_div2_sync_out_pipe_up; wire td_out_fifo_select_out_pipe_up; wire td_out_wr_enable_out_pipe_up; wire td_out_rd_enable_out_pipe_up; wire td_out_tx_div2_sync_out_pipe_down; wire td_out_fifo_select_out_pipe_down; wire td_out_wr_enable_out_pipe_down; wire td_out_rd_enable_out_pipe_down; // --------------------------------------------------------------------------- // DPRIO input CRAM // --------------------------------------------------------------------------- // atom level DPRIO input CRAM ------------------------------------------------ // Existing wire dprioin_is_lane0; wire dprioin_rauto_speed_ena; wire dprioin_rclkcmpinsertpad; // rx only ========= pipe =========== wire dprioin_rendec_data_sel_tx; wire dprioin_rfreq_sel; wire dprioin_rhip_ena; wire dprioin_rindv_tx; wire dprioin_rmaster_tx; wire dprioin_rmaster_up_tx; wire dprioin_rphfifo_master_sel_tx; wire dprioin_rpma_doublewidth_tx; wire dprioin_rpmadwidth_tx; wire dprioin_rrdwidth_rx; // rx only wire dprioin_rrx_detect_bypass; // rx only wire dprioin_rrx_pipe_enable; // rx only wire dprioin_rtx_cmu_sel; // added in 6.1 wire dprioin_scan_mode; // PCS Per Channel TX Control Register 1 for Channel 0 wire dprioin_rforce_disp; wire dprioin_rrev_loopbk; wire dprioin_rtxrdclksel; wire dprioin_rtxwrclksel; wire dprioin_rfreerun_tx; wire dprioin_rtxurstpcs; wire dprioin_reserved_0_TB1; wire dprioin_rphfifoursttx; wire dprioin_rphfifopldentx; wire dprioin_rge_xaui_tx; wire dprioin_rdwidth_tx; wire dprioin_rtxfifo_lowlatency_en; wire dprioin_rib_force_disp; wire dprioin_rtxfifo_dis; wire dprioin_rforce_echar; wire dprioin_rforce_kchar; // PCS Per Channel TX Control Register 2 for Channel 0 wire dprioin_rtxpcsbypass_en; wire [1:0] dprioin_rcxpat_chnl_en; wire [1:0] dprioin_rbist_sel; wire dprioin_rbisten_tx; wire [2:0] dprioin_rprbs_sel; wire dprioin_rprbsen_tx; wire dprioin_renbitrev_tx; wire dprioin_renpolinv_tx; wire dprioin_rensymswap_tx; wire dprioin_rcascaded_8b10b_en_tx; wire dprioin_r8b10b_enc_ibm_en; wire dprioin_rendec_tx; // PCS Per Channel TX Control Register 3 for Channel 0 wire dprioin_reserved_0_TB3; wire [7:0] dprioin_rcid_len_tx; wire dprioin_rcid_pattern_tx; wire dprioin_rtxpcsclkpwdn; wire dprioin_rtxswing_sel_ena; wire [2:0] dprioin_rtx_elec_idle_delay; wire dprioin_rtx_pipe_enable; // PCS Per Channel TX Control Register 4 for Channel 0 wire [11:0] dprioin_reserved_0_TB4; wire dprioin_rtxbitslip_en; wire dprioin_rphfifo_regmode_tx; wire dprioin_rpipeline_bypass_tx; wire dprioin_rself_sw_en_tx; // --------------------------------------------------------------------------- // CRAM // --------------------------------------------------------------------------- // Final CRAM to pass to RTL ------------------------------------------ // Existing wire cram_is_lane0; wire cram_rauto_speed_ena; wire cram_rclkcmpinsertpad; // rx only ========= pipe =========== wire cram_rendec_data_sel_tx; wire cram_rfreq_sel; wire cram_rhip_ena; wire cram_rindv_tx; wire cram_rmaster_tx; wire cram_rmaster_up_tx; wire cram_rphfifo_master_sel_tx; wire cram_rpma_doublewidth_tx; wire cram_rpmadwidth_tx; wire cram_rrdwidth_rx; // rx only wire cram_rrx_detect_bypass; // rx only wire cram_rrx_pipe_enable; // rx only wire cram_rtx_cmu_sel; // added in 6.1 wire cram_scan_mode; // PCS Per Channel TX Control Register 1 for Channel 0 wire cram_rforce_disp; wire cram_rrev_loopbk; wire cram_rtxrdclksel; wire cram_rtxwrclksel; wire cram_rfreerun_tx; wire cram_rtxurstpcs; wire cram_reserved_0_TB1; wire cram_rphfifoursttx; wire cram_rphfifopldentx; wire cram_rge_xaui_tx; wire cram_rdwidth_tx; wire cram_rtxfifo_lowlatency_en; wire cram_rib_force_disp; wire cram_rtxfifo_dis; wire cram_rforce_echar; wire cram_rforce_kchar; // PCS Per Channel TX Control Register 2 for Channel 0 wire cram_rtxpcsbypass_en; wire [1:0] cram_rcxpat_chnl_en; wire [1:0] cram_rbist_sel; wire cram_rbisten_tx; wire [2:0] cram_rprbs_sel; wire cram_rprbsen_tx; wire cram_renbitrev_tx; wire cram_renpolinv_tx; wire cram_rensymswap_tx; wire cram_rcascaded_8b10b_en_tx; wire cram_r8b10b_enc_ibm_en; wire cram_rendec_tx; // PCS Per Channel TX Control Register 3 for Channel 0 wire cram_reserved_0_TB3; wire [7:0] cram_rcid_len_tx; wire cram_rcid_pattern_tx; wire cram_rtxpcsclkpwdn; wire cram_rtxswing_sel_ena; wire [2:0] cram_rtx_elec_idle_delay; wire cram_rtx_pipe_enable; // PCS Per Channel TX Control Register 4 for Channel 0 wire [11:0] cram_reserved_0_TB4; wire cram_rtxbitslip_en; wire cram_rphfifo_regmode_tx; wire cram_rpipeline_bypass_tx; wire cram_rself_sw_en_tx; //////////////////////////////////////////////////////////////////////////////// // Internal Variables -------------------------------------------------------// //////////////////////////////////////////////////////////////////////////////// integer i; integer j; reg rxdet_fixclk_reg; //////////////////////////////////////////////////////////////////////////////// // Function -------------------------------------------------------// //////////////////////////////////////////////////////////////////////////////// function [2:0] compute_rprbs_sel; input pma_doublewidth; input pma_width; input test_mode; reg [8*20:1] test_mode; reg [2:0] res; begin case ({pma_doublewidth, pma_width}) 2'b00 : begin if (test_mode == "prbs_8" || test_mode == "prbs8") res = 3'b000; else if (test_mode == "prbs7") res = 3'b010; else if (test_mode == "prbs23") res = 3'b100; else if (test_mode == "high frequency") res = 3'b001; else res = 3'b000; // PRBS_8 end 2'b01 : begin if (test_mode == "prbs_10" || test_mode == "prbs10") res = 3'b000; else if (test_mode == "high frequency") res = 3'b001; else if (test_mode == "low frequency") res = 3'b010; else if (test_mode == "mixed frequency") res = 3'b011; else res = 3'b000; // PRBS_10 end 2'b10 : begin if (test_mode == "prbs_7" || test_mode == "prbs7") res = 3'b000; else if (test_mode == "PRBS_23" || test_mode == "prbs_23" || test_mode == "prbs23") res = 3'b001; else if (test_mode == "high frequency") res = 3'b010; else res = 3'b000; // PRBS_7 end 2'b11 : begin if (test_mode == "prbs_7" || test_mode == "prbs7") res = 3'b000; else if (test_mode == "prbs_23" || test_mode == "prbs23") res = 3'b001; else if (test_mode == "high frequency") res = 3'b010; else if (test_mode == "low frequency") res = 3'b011; else if (test_mode == "mixed frequency") res = 3'b100; else res = 3'b000; // default end default : begin $display("Invalid pma_doublewidth and pma_width selection"); $display("Time: %0t Instance: %m", $time); end endcase compute_rprbs_sel = res; end endfunction function [8*`STRATIXIV_HSSI_TX_PCS_ALPHA_TOLOWER_WORD_LENGTH:1] alpha_tolower; input [8*`STRATIXIV_HSSI_TX_PCS_ALPHA_TOLOWER_WORD_LENGTH:1] input_string; reg [8*`STRATIXIV_HSSI_TX_PCS_ALPHA_TOLOWER_WORD_LENGTH:1] return_string; reg [8*`STRATIXIV_HSSI_TX_PCS_ALPHA_TOLOWER_WORD_LENGTH:1] reg_string; reg [8:1] tmp; reg [8:1] conv_char; integer byte_count; begin reg_string = input_string; for (byte_count = `STRATIXIV_HSSI_TX_PCS_ALPHA_TOLOWER_WORD_LENGTH; byte_count >= 1; byte_count = byte_count - 1) begin tmp = reg_string[8*`STRATIXIV_HSSI_TX_PCS_ALPHA_TOLOWER_WORD_LENGTH:(8*(`STRATIXIV_HSSI_TX_PCS_ALPHA_TOLOWER_WORD_LENGTH-1)+1)]; reg_string = reg_string << 8; if ((tmp >= 65) && (tmp <= 90)) // ASCII number of 'A' is 65, 'Z' is 90 begin conv_char = tmp + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set return_string = {return_string, conv_char}; end else return_string = {return_string, tmp}; end alpha_tolower = return_string; end endfunction //////////////////////////////////////////////////////////////////////////////// // Timing - INPUT BUFFERS ---------------------------------------------------// //////////////////////////////////////////////////////////////////////////////// wire [3:0] ctrlenable_ipd; wire [39:0] datain_ipd; wire [3:0] dispval_ipd; wire [3:0] forcedisp_ipd; wire [1:0] powerdn_ipd; wire coreclk_ipd; wire detectrxloop_ipd; wire enrevparallellpbk_ipd; wire forcedispcompliance_ipd; wire invpol_ipd; wire phfifowrenable_ipd; wire pipetxdeemph_ipd; wire [2:0] pipetxmargin_ipd; wire pipetxswing_ipd; wire rateswitch_ipd; wire refclk_ipd; wire rxrst_int_wire; wire phfiforeset_ipd; wire phfiforddisable_ipd; //ww47 new inputs wire [4 : 0] bitslipboundaryselect_in; wire forceelecidle_ipd; wire [9 : 0] hipdatain_in; wire hipdetectrxloop_in; wire hipforceelecidle_in; wire [1 : 0] hippowerdn_in; wire hiptxdeemph_in; wire [2 : 0] hiptxmargin_in; wire [1 : 0] iqpphfifoxnbytesel_in; wire [1 : 0] iqpphfifoxnrdclk_in; wire [1 : 0] iqpphfifoxnrdenable_in; wire [1 : 0] iqpphfifoxnwrenable_in; wire phfifobyteserdisable_in; wire phfifoptrsreset_in; wire [2 : 0] phfifoxnbytesel_in; wire [2 : 0] phfifoxnptrsreset_in; wire [2 : 0] phfifoxnrdclk_in; wire [2 : 0] phfifoxnrdenable_in; wire [2 : 0] phfifoxnwrenable_in; wire prbscidenable_in; wire [2:0] elecidleinfersel_in; wire [2:0] hipelecidleinfersel_in; assign refclk_ipd = refclk; assign coreclk_ipd = coreclk; assign ctrlenable_ipd = ctrlenable; assign datain_ipd = datain; assign dispval_ipd = dispval; assign forcedisp_ipd = forcedisp; assign forcedispcompliance_ipd = forcedispcompliance; assign phfifowrenable_ipd = phfifowrenable; assign detectrxloop_ipd = detectrxloop; assign forceelecidle_ipd = forceelecidle; assign powerdn_ipd = powerdn; assign pipetxdeemph_ipd = pipetxdeemph; assign pipetxmargin_ipd = pipetxmargin; assign pipetxswing_ipd = pipetxswing; assign invpol_ipd = invpol; assign phfiforddisable_ipd = phfiforddisable; assign enrevparallellpbk_ipd = enrevparallellpbk; assign phfiforeset_ipd = phfiforeset; assign rateswitch_ipd = rateswitch; assign bitslipboundaryselect_in[0] = (bitslipboundaryselect[0] === 1'b1) ? 1'b1 : 1'b0; assign bitslipboundaryselect_in[1] = (bitslipboundaryselect[1] === 1'b1) ? 1'b1 : 1'b0; assign bitslipboundaryselect_in[2] = (bitslipboundaryselect[2] === 1'b1) ? 1'b1 : 1'b0; assign bitslipboundaryselect_in[3] = (bitslipboundaryselect[3] === 1'b1) ? 1'b1 : 1'b0; assign bitslipboundaryselect_in[4] = (bitslipboundaryselect[4] === 1'b1) ? 1'b1 : 1'b0; assign hipdatain_in = hipdatain; assign hipdetectrxloop_in = hipdetectrxloop; assign hipforceelecidle_in = hipforceelecidle; assign hippowerdn_in = hippowerdn; assign hiptxdeemph_in = hiptxdeemph; assign hiptxmargin_in = hiptxmargin; assign iqpphfifoxnbytesel_in = iqpphfifoxnbytesel; assign iqpphfifoxnrdclk_in = iqpphfifoxnrdclk; assign iqpphfifoxnrdenable_in = iqpphfifoxnrdenable; assign iqpphfifoxnwrenable_in = iqpphfifoxnwrenable; assign phfifobyteserdisable_in = phfifobyteserdisable; assign phfifoptrsreset_in = phfifoptrsreset; assign phfifoxnbytesel_in = phfifoxnbytesel; assign phfifoxnptrsreset_in = phfifoxnptrsreset; assign phfifoxnrdclk_in = phfifoxnrdclk; assign phfifoxnrdenable_in = phfifoxnrdenable; assign phfifoxnwrenable_in = phfifoxnwrenable; assign prbscidenable_in = prbscidenable; assign elecidleinfersel_in[0] = (elecidleinfersel[0] === 1'b1)? 1'b1 : 1'b0; assign elecidleinfersel_in[1] = (elecidleinfersel[1] === 1'b1)? 1'b1 : 1'b0; assign elecidleinfersel_in[2] = (elecidleinfersel[2] === 1'b1)? 1'b1 : 1'b0; assign hipelecidleinfersel_in[0] = (hipelecidleinfersel[0] === 1'b1)? 1'b1 : 1'b0; assign hipelecidleinfersel_in[1] = (hipelecidleinfersel[1] === 1'b1)? 1'b1 : 1'b0; assign hipelecidleinfersel_in[2] = (hipelecidleinfersel[2] === 1'b1)? 1'b1 : 1'b0; //////////////////////////////////////////////////////////////////////////////// // TIMING -- TCO/TSU/HOLD // //////////////////////////////////////////////////////////////////////////////// specify $setuphold(posedge coreclk, ctrlenable, 0, 0); $setuphold(posedge coreclk, datain, 0, 0); $setuphold(posedge coreclk, detectrxloop, 0, 0); $setuphold(posedge coreclk, dispval, 0, 0); $setuphold(posedge coreclk, forcedisp, 0, 0); $setuphold(posedge coreclk, forcedispcompliance, 0, 0); $setuphold(posedge coreclk, phfifowrenable, 0, 0); $setuphold(posedge coreclk, forceelecidle, 0, 0); $setuphold(posedge coreclk, powerdn, 0, 0); $setuphold(posedge coreclk, pipetxdeemph, 0, 0); $setuphold(posedge coreclk, pipetxswing, 0, 0); $setuphold(posedge coreclk, pipetxmargin, 0, 0); (posedge coreclk => (phfifooverflow +: td_out_full_tx)) = (0, 0); (posedge coreclk => (phfifounderflow +: td_out_empty_tx)) = (0, 0); endspecify //////////////////////////////////////////////////////////////////////////////// // dprio outputs //////////////////////////////////////////////////////////////////////////////// wire [149:0] dprioin_in; assign dprioin_in = dprioin; // inital CRAMs from parameters - CRAM_TABLE 1 initial begin init_r8b10b_enc_ibm_en = (enc_8b_10b_compatibility_mode == "true") ? 1'b1 : 1'b0; init_rbist_sel = (self_test_mode == "incremental") ? 2'b00 : // to bist_gen (self_test_mode == "cjpat") ? 2'b01 : (self_test_mode == "crpat") ? 2'b10 : 2'b00; init_rbisten_tx = ((enable_self_test_mode == "true") && (self_test_mode == "incremental" || self_test_mode == "cjpat" || self_test_mode == "cjpat")) ? 1'b1 : 1'b0; // bist_gen init_rcascaded_8b10b_en_tx = (enc_8b_10b_mode == "cascaded") ? 1'b1 : 1'b0; init_rcxpat_chnl_en = (channel_number == 1) ? 2'b01 : // bist_gen (channel_number == 2) ? 2'b10 : (channel_number == 3) ? 2'b11 : 2'b00; init_rdwidth_tx = (use_double_data_mode == "true") ? 1'b1 : 1'b0; init_renbitrev_tx = (enable_bit_reversal == "true") ? 1'b1 : 1'b0; init_rendec_data_sel_tx = (protocol_hint == "xaui") ? 1'b0 : 1'b1; // 0=ts_; 1=tc_ init_rendec_tx = (enc_8b_10b_mode != "none") ? 1'b1 : 1'b0; init_renpolinv_tx = (allow_polarity_inversion == "true") ? 1'b1 : 1'b0; init_rensymswap_tx = (enable_symbol_swap == "true") ? 1'b1 : 1'b0; init_rforce_disp = (disparity_mode == "new") ? 1'b1 : 1'b0; init_rforce_echar = (force_echar == "true") ? 1'b1 : 1'b0; init_rforce_kchar = (force_kchar == "true") ? 1'b1 : 1'b0; init_rfreerun_tx = (reset_clock_output_during_digital_reset == "false") ? 1'b1 : 1'b0; init_rge_xaui_tx = (protocol_hint == "gige" || enable_idle_selection == "true") ? 1'b1 : 1'b0; init_rib_force_disp = (disparity_mode == "legacy") ? 1'b1 : 1'b0; init_rindv_tx = (channel_bonding == "x4" || channel_bonding == "x8" || protocol_hint == "xaui") ? 1'b0 : 1'b1; init_rphfifo_master_sel_tx = (channel_bonding == "x8") ? 1'b0 : 1'b1; init_rphfifopldentx = 1'b1; // Altera Internal Mode - Enable PLD controlled write and read ** enabled to match ASM init_rphfifoursttx = 1'b1; // Altera Internal Mode - 0 = normal operation: ** enabled for POF init_rpma_doublewidth_tx = (use_serializer_double_data_mode == "true") ? 1'b1 : 1'b0; // 1 = 16/20, 0 = 8/10 init_rpmadwidth_tx = ((enc_8b_10b_mode == "none") && ((channel_width == 8) || (channel_width == 16) || (channel_width == 32))) ? 1'b0 : 1'b1; // 0 = 8 bit, 1 = 10 bit init_rprbs_sel = compute_rprbs_sel(init_rpma_doublewidth_tx,init_rpmadwidth_tx,self_test_mode); init_rprbsen_tx = ((enable_self_test_mode == "true") && (self_test_mode != "incremental") && (self_test_mode != "cjpat") && (self_test_mode != "crpat")) ? 1'b1 : 1'b0; // prbs_gen init_rrev_loopbk = (enable_reverse_parallel_loopback == "true") ? 1'b1 : 1'b0; init_rtx_pipe_enable = (protocol_hint == "pcie" || protocol_hint == "pcie2") ? 1'b1 : 1'b0; init_rtxfifo_dis = (enable_phfifo_bypass == "true") ? 1'b1 : 1'b0; // cannot bypass init_rtxfifo_lowlatency_en = (disable_ph_low_latency_mode == "false") ? 1'b1 : 1'b0; init_rtxpcsbypass_en = (datapath_low_latency_mode == "true") ? 1'b1 : 1'b0; init_rtxrdclksel = (refclk_select == "cmu_clock_divider" || refclk_select == "cmu clock divider") ? 1'b1 : 1'b0; // TxFifo Rd clock 1=refclk_pma, 0=local_refclk_pma init_rtxswing_sel_ena = (pipe_voltage_swing_control == "true") ? 1'b1 : 1'b0; init_rtxwrclksel = (wr_clk_mux_select == "int_clk" || wr_clk_mux_select == "int clk" || wr_clk_mux_select == "internal clock") ? 1'b1 : 1'b0; // TxFifo Write clk. 1=int_clk; 0=pld_tx_clk init_rclkcmpinsertpad = 1'b1; // for rx only ====== pipe section started ======== init_rrdwidth_rx = 1'b1; // for rx only extra r in pipe interface init_rrx_detect_bypass = 1'b1; // for rx only init_rrx_pipe_enable = 1'b1; // for rx only init_rtx_elec_idle_delay = (elec_idle_delay == 0) ? 3'b011 : (elec_idle_delay - 3); // 3'b011 Engineering bits - delay numbers - on purpse seting 6 to compensate PMA model init_is_lane0 = (channel_number == 0) ? 1'b1 : 1'b0; init_scan_mode = 1'b0; // NEW init_rauto_speed_ena = (pipe_auto_speed_nego_enable == "true") ? 1'b1 : 1'b0; init_rfreq_sel = (alpha_tolower(pipe_freq_scale_mode) == "data width") ? 1'b0 : 1'b1; // default is Frequency init_rtxpcsclkpwdn = 1'b0; init_rcid_pattern_tx = (prbs_cid_pattern == "true") ? 1'b1 : 1'b0; init_rcid_len_tx = prbs_cid_pattern_length; init_rmaster_tx = (mph_fifo_xn_mapping == "central" || channel_bonding != "x8") ? 1'b1 : 1'b0; // ---------------------------------------------------------------------------- // megafuncton gets rmaster_up opposite as input mux but still in simulation // input as I connect the input (from master channel) into both in_up and // in_down. The reason I care now is due to ww12 RTL: I use the cram to mux // iqp <= (up, down) // ---------------------------------------------------------------------------- init_rmaster_up_tx = (mph_fifo_xn_mapping == "down") ? 1'b1 : 1'b0; //flip init_rself_sw_en_tx = (auto_spd_self_switch_enable == "true") ? 1'b1 : 1'b0; init_rpipeline_bypass_tx = (iqp_bypass == "true") ? 1'b1 : 1'b0; init_rphfifo_regmode_tx = (ph_fifo_reg_mode == "true") ? 1'b1 : 1'b0; init_rtxbitslip_en = (bitslip_enable == "true") ? 1'b1 : 1'b0; init_rhip_ena = (hip_enable == "true") ? 1'b1 : 1'b0; end // Set DPRIO input CRAM from dprioin - CRAM_Table 2A ------------------------- // --------------------------------------------------------------------------- // Set DPRIO CRAM input from dprioin // --------------------------------------------------------------------------- // Table 2A needs to use def'ed INDEX for PCS // Existing assign dprioin_rpma_doublewidth_tx = dprioin_in[`rpma_doublewidth_tx_TX_IDX]; assign dprioin_rpmadwidth_tx = dprioin_in[`rpmadwidth_tx_TX_IDX]; assign dprioin_rendec_data_sel_tx = dprioin_in[`rendec_data_sel_tx_TX_IDX]; assign dprioin_rindv_tx = dprioin_in[`rindv_tx_TX_IDX]; assign dprioin_rmaster_tx = dprioin_in[`rmaster_tx_TX_IDX]; assign dprioin_rmaster_up_tx = dprioin_in[`rmaster_up_tx_TX_IDX]; assign dprioin_is_lane0 = init_is_lane0; assign dprioin_rauto_speed_ena = dprioin_in[`rauto_speed_ena_TX_IDX]; assign dprioin_rclkcmpinsertpad = init_rclkcmpinsertpad; // rx only ========= pipe =========== assign dprioin_rfreq_sel = dprioin_in[`rfreq_sel_TX_IDX]; assign dprioin_rhip_ena = dprioin_in[`rhip_ena_TX_IDX]; assign dprioin_rphfifo_master_sel_tx = init_rphfifo_master_sel_tx; // obsolete cram assign dprioin_rrdwidth_rx = init_rrdwidth_rx; // rx only assign dprioin_rrx_detect_bypass = init_rrx_detect_bypass; // rx only assign dprioin_rrx_pipe_enable = init_rrx_pipe_enable; // rx only assign dprioin_rtx_cmu_sel = dprioin_in[`rtx_cmu_sel_TX_IDX]; assign dprioin_scan_mode = init_scan_mode; // PCS Per Channel TX Control Register 1 for Channel 0 assign dprioin_rforce_disp = dprioin[`rforce_disp_TXPCS_IDX_0]; assign dprioin_rrev_loopbk = dprioin[`rrev_loopbk_TXPCS_IDX_0]; assign dprioin_rtxrdclksel = dprioin[`rtxrdclksel_TXPCS_IDX_0]; assign dprioin_rtxwrclksel = dprioin[`rtxwrclksel_TXPCS_IDX_0]; assign dprioin_rfreerun_tx = dprioin[`rfreerun_tx_TXPCS_IDX_0]; assign dprioin_rtxurstpcs = dprioin[`rtxurstpcs_TXPCS_IDX_0]; assign dprioin_reserved_0_TB1 = dprioin[`reserved_0_TB1_TXPCS_IDX_0]; assign dprioin_rphfifoursttx = dprioin[`rphfifoursttx_TXPCS_IDX_0]; assign dprioin_rphfifopldentx = dprioin[`rphfifopldentx_TXPCS_IDX_0]; assign dprioin_rge_xaui_tx = dprioin[`rge_xaui_tx_TXPCS_IDX_0]; assign dprioin_rdwidth_tx = dprioin[`rdwidth_tx_TXPCS_IDX_0]; assign dprioin_rtxfifo_lowlatency_en = dprioin[`rtxfifo_lowlatency_en_TXPCS_IDX_0]; assign dprioin_rib_force_disp = dprioin[`rib_force_disp_TXPCS_IDX_0]; assign dprioin_rtxfifo_dis = dprioin[`rtxfifo_dis_TXPCS_IDX_0]; assign dprioin_rforce_echar = dprioin[`rforce_echar_TXPCS_IDX_0]; assign dprioin_rforce_kchar = dprioin[`rforce_kchar_TXPCS_IDX_0]; // PCS Per Channel TX Control Register 2 for Channel 0 assign dprioin_rtxpcsbypass_en = dprioin[`rtxpcsbypass_en_TXPCS_IDX_0]; assign dprioin_rcxpat_chnl_en = dprioin[`rcxpat_chnl_en_TXPCS_IDX_1 : `rcxpat_chnl_en_TXPCS_IDX_0]; assign dprioin_rbist_sel = dprioin[`rbist_sel_TXPCS_IDX_1 : `rbist_sel_TXPCS_IDX_0]; assign dprioin_rbisten_tx = dprioin[`rbisten_tx_TXPCS_IDX_0]; assign dprioin_rprbs_sel = dprioin[`rprbs_sel_TXPCS_IDX_2 : `rprbs_sel_TXPCS_IDX_0]; assign dprioin_rprbsen_tx = dprioin[`rprbsen_tx_TXPCS_IDX_0]; assign dprioin_renbitrev_tx = dprioin[`renbitrev_tx_TXPCS_IDX_0]; assign dprioin_renpolinv_tx = dprioin[`renpolinv_tx_TXPCS_IDX_0]; assign dprioin_rensymswap_tx = dprioin[`rensymswap_tx_TXPCS_IDX_0]; assign dprioin_rcascaded_8b10b_en_tx = dprioin[`rcascaded_8b10b_en_tx_TXPCS_IDX_0]; assign dprioin_r8b10b_enc_ibm_en = dprioin[`r8b10b_enc_ibm_en_TXPCS_IDX_0]; assign dprioin_rendec_tx = dprioin[`rendec_tx_TXPCS_IDX_0]; // PCS Per Channel TX Control Register 3 for Channel 0 assign dprioin_reserved_0_TB3 = dprioin[`reserved_0_TB3_TXPCS_IDX_0]; assign dprioin_rcid_len_tx = dprioin[`rcid_len_tx_TXPCS_IDX_7 : `rcid_len_tx_TXPCS_IDX_0]; assign dprioin_rcid_pattern_tx = dprioin[`rcid_pattern_tx_TXPCS_IDX_0]; assign dprioin_rtxpcsclkpwdn = dprioin[`rtxpcsclkpwdn_TXPCS_IDX_0]; assign dprioin_rtxswing_sel_ena = dprioin[`rtxswing_sel_ena_TXPCS_IDX_0]; assign dprioin_rtx_elec_idle_delay = dprioin[`rtx_elec_idle_delay_TXPCS_IDX_2 : `rtx_elec_idle_delay_TXPCS_IDX_0]; assign dprioin_rtx_pipe_enable = dprioin[`rtx_pipe_enable_TXPCS_IDX_0]; // PCS Per Channel TX Control Register 4 for Channel 0 assign dprioin_reserved_0_TB4 = dprioin[`reserved_0_TB4_TXPCS_IDX_11 : `reserved_0_TB4_TXPCS_IDX_0]; assign dprioin_rtxbitslip_en = dprioin[`rtxbitslip_en_TXPCS_IDX_0]; assign dprioin_rphfifo_regmode_tx = dprioin[`rphfifo_regmode_tx_TXPCS_IDX_0]; assign dprioin_rpipeline_bypass_tx = dprioin[`rpipeline_bypass_tx_TXPCS_IDX_0]; assign dprioin_rself_sw_en_tx = dprioin[`rself_sw_en_tx_TXPCS_IDX_0]; // --------------------------------------------------------------------------- // Set DPRIO output from initial CRAM // --------------------------------------------------------------------------- // Set DPRIO reg with initial parameters - CRAM_Table 2B --------------------------- // Existing assign dprioout[`rpma_doublewidth_tx_TX_IDX] = init_rpma_doublewidth_tx; assign dprioout[`rpmadwidth_tx_TX_IDX] = init_rpmadwidth_tx; assign dprioout[`rendec_data_sel_tx_TX_IDX] = init_rendec_data_sel_tx; assign dprioout[`rindv_tx_TX_IDX] = init_rindv_tx; assign dprioout[`rmaster_tx_TX_IDX] = init_rmaster_tx; assign dprioout[`rmaster_up_tx_TX_IDX] = init_rmaster_up_tx; assign dprioout[`rauto_speed_ena_TX_IDX] = init_rauto_speed_ena; assign dprioout[`rfreq_sel_TX_IDX] = init_rfreq_sel; assign dprioout[`rhip_ena_TX_IDX] = init_rhip_ena; assign dprioout[`rtx_cmu_sel_TX_IDX] = init_rtx_cmu_sel; // PCS Per Channel TX Control Register 1 for Channel 0 assign dprioout[`rforce_disp_TXPCS_IDX_0] = init_rforce_disp; assign dprioout[`rrev_loopbk_TXPCS_IDX_0] = init_rrev_loopbk; assign dprioout[`rtxrdclksel_TXPCS_IDX_0] = init_rtxrdclksel; assign dprioout[`rtxwrclksel_TXPCS_IDX_0] = init_rtxwrclksel; assign dprioout[`rfreerun_tx_TXPCS_IDX_0] = init_rfreerun_tx; assign dprioout[`rtxurstpcs_TXPCS_IDX_0] = init_rtxurstpcs; assign dprioout[`reserved_0_TB1_TXPCS_IDX_0] = init_reserved_0_TB1; assign dprioout[`rphfifoursttx_TXPCS_IDX_0] = init_rphfifoursttx; assign dprioout[`rphfifopldentx_TXPCS_IDX_0] = init_rphfifopldentx; assign dprioout[`rge_xaui_tx_TXPCS_IDX_0] = init_rge_xaui_tx; assign dprioout[`rdwidth_tx_TXPCS_IDX_0] = init_rdwidth_tx; assign dprioout[`rtxfifo_lowlatency_en_TXPCS_IDX_0] = init_rtxfifo_lowlatency_en; assign dprioout[`rib_force_disp_TXPCS_IDX_0] = init_rib_force_disp; assign dprioout[`rtxfifo_dis_TXPCS_IDX_0] = init_rtxfifo_dis; assign dprioout[`rforce_echar_TXPCS_IDX_0] = init_rforce_echar; assign dprioout[`rforce_kchar_TXPCS_IDX_0] = init_rforce_kchar; // PCS Per Channel TX Control Register 2 for Channel 0 assign dprioout[`rtxpcsbypass_en_TXPCS_IDX_0] = init_rtxpcsbypass_en; assign dprioout[`rcxpat_chnl_en_TXPCS_IDX_1 : `rcxpat_chnl_en_TXPCS_IDX_0] = init_rcxpat_chnl_en; assign dprioout[`rbist_sel_TXPCS_IDX_1 : `rbist_sel_TXPCS_IDX_0] = init_rbist_sel; assign dprioout[`rbisten_tx_TXPCS_IDX_0] = init_rbisten_tx; assign dprioout[`rprbs_sel_TXPCS_IDX_2 : `rprbs_sel_TXPCS_IDX_0] = init_rprbs_sel; assign dprioout[`rprbsen_tx_TXPCS_IDX_0] = init_rprbsen_tx; assign dprioout[`renbitrev_tx_TXPCS_IDX_0] = init_renbitrev_tx; assign dprioout[`renpolinv_tx_TXPCS_IDX_0] = init_renpolinv_tx; assign dprioout[`rensymswap_tx_TXPCS_IDX_0] = init_rensymswap_tx; assign dprioout[`rcascaded_8b10b_en_tx_TXPCS_IDX_0] = init_rcascaded_8b10b_en_tx; assign dprioout[`r8b10b_enc_ibm_en_TXPCS_IDX_0] = init_r8b10b_enc_ibm_en; assign dprioout[`rendec_tx_TXPCS_IDX_0] = init_rendec_tx; // PCS Per Channel TX Control Register 3 for Channel 0 assign dprioout[`reserved_0_TB3_TXPCS_IDX_0] = init_reserved_0_TB3; assign dprioout[`rcid_len_tx_TXPCS_IDX_7 : `rcid_len_tx_TXPCS_IDX_0] = init_rcid_len_tx; assign dprioout[`rcid_pattern_tx_TXPCS_IDX_0] = init_rcid_pattern_tx; assign dprioout[`rtxpcsclkpwdn_TXPCS_IDX_0] = init_rtxpcsclkpwdn; assign dprioout[`rtxswing_sel_ena_TXPCS_IDX_0] = init_rtxswing_sel_ena; assign dprioout[`rtx_elec_idle_delay_TXPCS_IDX_2 : `rtx_elec_idle_delay_TXPCS_IDX_0] = init_rtx_elec_idle_delay; assign dprioout[`rtx_pipe_enable_TXPCS_IDX_0] = init_rtx_pipe_enable; // PCS Per Channel TX Control Register 4 for Channel 0 assign dprioout[`reserved_0_TB4_TXPCS_IDX_11 : `reserved_0_TB4_TXPCS_IDX_0] = init_reserved_0_TB4; assign dprioout[`rtxbitslip_en_TXPCS_IDX_0] = init_rtxbitslip_en; assign dprioout[`rphfifo_regmode_tx_TXPCS_IDX_0] = init_rphfifo_regmode_tx; assign dprioout[`rpipeline_bypass_tx_TXPCS_IDX_0] = init_rpipeline_bypass_tx; assign dprioout[`rself_sw_en_tx_TXPCS_IDX_0] = init_rself_sw_en_tx; // --------------------------------------------------------------------------- // Set DPRIO CRAM // --------------------------------------------------------------------------- // select CRAMs between DPIRO vs. parameters ---------------------------------------------------------------- // Set DPRIO CRAM wire dpriodisable_in; assign dpriodisable_in = (dpriodisable === 1'b0) ? 1'b0 : 1'b1; // Existing assign cram_rpma_doublewidth_tx = (dpriodisable_in == 1'b1) ? init_rpma_doublewidth_tx : dprioin_rpma_doublewidth_tx; assign cram_rpmadwidth_tx = (dpriodisable_in == 1'b1) ? init_rpmadwidth_tx : dprioin_rpmadwidth_tx; assign cram_rendec_data_sel_tx = (dpriodisable_in == 1'b1) ? init_rendec_data_sel_tx : dprioin_rendec_data_sel_tx; assign cram_rindv_tx = (dpriodisable_in == 1'b1) ? init_rindv_tx : dprioin_rindv_tx; assign cram_rmaster_tx = (dpriodisable_in == 1'b1) ? init_rmaster_tx : dprioin_rmaster_tx; assign cram_rmaster_up_tx = (dpriodisable_in == 1'b1) ? init_rmaster_up_tx : dprioin_rmaster_up_tx; assign cram_is_lane0 = (dpriodisable_in == 1'b1) ? init_is_lane0 : dprioin_is_lane0; assign cram_rauto_speed_ena = (dpriodisable_in == 1'b1) ? init_rauto_speed_ena : dprioin_rauto_speed_ena; assign cram_rclkcmpinsertpad = (dpriodisable_in == 1'b1) ? init_rclkcmpinsertpad : dprioin_rclkcmpinsertpad; // rx only assign cram_rfreq_sel = (dpriodisable_in == 1'b1) ? init_rfreq_sel : dprioin_rfreq_sel; assign cram_rhip_ena = (dpriodisable_in == 1'b1) ? init_rhip_ena : dprioin_rhip_ena; assign cram_rphfifo_master_sel_tx = (dpriodisable_in == 1'b1) ? init_rphfifo_master_sel_tx : dprioin_rphfifo_master_sel_tx; assign cram_rrdwidth_rx = (dpriodisable_in == 1'b1) ? init_rrdwidth_rx : dprioin_rrdwidth_rx; // rx only assign cram_rrx_detect_bypass = (dpriodisable_in == 1'b1) ? init_rrx_detect_bypass : dprioin_rrx_detect_bypass; // rx only assign cram_rrx_pipe_enable = (dpriodisable_in == 1'b1) ? init_rrx_pipe_enable : dprioin_rrx_pipe_enable; // rx only assign cram_rtx_cmu_sel = (dpriodisable_in == 1'b1) ? init_rtx_cmu_sel : dprioin_rtx_cmu_sel; assign cram_scan_mode = (dpriodisable_in == 1'b1) ? init_scan_mode : dprioin_scan_mode; // PCS Per Channel TX Control Register 1 for Channel 0 assign cram_rforce_disp = (dpriodisable_in == 1'b1) ? init_rforce_disp : dprioin_rforce_disp; assign cram_rrev_loopbk = (dpriodisable_in == 1'b1) ? init_rrev_loopbk : dprioin_rrev_loopbk; assign cram_rtxrdclksel = (dpriodisable_in == 1'b1) ? init_rtxrdclksel : dprioin_rtxrdclksel; assign cram_rtxwrclksel = (dpriodisable_in == 1'b1) ? init_rtxwrclksel : dprioin_rtxwrclksel; assign cram_rfreerun_tx = (dpriodisable_in == 1'b1) ? init_rfreerun_tx : dprioin_rfreerun_tx; assign cram_rtxurstpcs = (dpriodisable_in == 1'b1) ? init_rtxurstpcs : dprioin_rtxurstpcs; assign cram_reserved_0_TB1 = (dpriodisable_in == 1'b1) ? init_reserved_0_TB1 : dprioin_reserved_0_TB1; assign cram_rphfifoursttx = (dpriodisable_in == 1'b1) ? init_rphfifoursttx : dprioin_rphfifoursttx; assign cram_rphfifopldentx = (dpriodisable_in == 1'b1) ? init_rphfifopldentx : dprioin_rphfifopldentx; assign cram_rge_xaui_tx = (dpriodisable_in == 1'b1) ? init_rge_xaui_tx : dprioin_rge_xaui_tx; assign cram_rdwidth_tx = (dpriodisable_in == 1'b1) ? init_rdwidth_tx : dprioin_rdwidth_tx; assign cram_rtxfifo_lowlatency_en = (dpriodisable_in == 1'b1) ? init_rtxfifo_lowlatency_en : dprioin_rtxfifo_lowlatency_en; assign cram_rib_force_disp = (dpriodisable_in == 1'b1) ? init_rib_force_disp : dprioin_rib_force_disp; assign cram_rtxfifo_dis = (dpriodisable_in == 1'b1) ? init_rtxfifo_dis : dprioin_rtxfifo_dis; assign cram_rforce_echar = (dpriodisable_in == 1'b1) ? init_rforce_echar : dprioin_rforce_echar; assign cram_rforce_kchar = (dpriodisable_in == 1'b1) ? init_rforce_kchar : dprioin_rforce_kchar; // PCS Per Channel TX Control Register 2 for Channel 0 assign cram_rtxpcsbypass_en = (dpriodisable_in == 1'b1) ? init_rtxpcsbypass_en : dprioin_rtxpcsbypass_en; assign cram_rcxpat_chnl_en = (dpriodisable_in == 1'b1) ? init_rcxpat_chnl_en : dprioin_rcxpat_chnl_en; assign cram_rbist_sel = (dpriodisable_in == 1'b1) ? init_rbist_sel : dprioin_rbist_sel; assign cram_rbisten_tx = (dpriodisable_in == 1'b1) ? init_rbisten_tx : dprioin_rbisten_tx; assign cram_rprbs_sel = (dpriodisable_in == 1'b1) ? init_rprbs_sel : dprioin_rprbs_sel; assign cram_rprbsen_tx = (dpriodisable_in == 1'b1) ? init_rprbsen_tx : dprioin_rprbsen_tx; assign cram_renbitrev_tx = (dpriodisable_in == 1'b1) ? init_renbitrev_tx : dprioin_renbitrev_tx; assign cram_renpolinv_tx = (dpriodisable_in == 1'b1) ? init_renpolinv_tx : dprioin_renpolinv_tx; assign cram_rensymswap_tx = (dpriodisable_in == 1'b1) ? init_rensymswap_tx : dprioin_rensymswap_tx; assign cram_rcascaded_8b10b_en_tx = (dpriodisable_in == 1'b1) ? init_rcascaded_8b10b_en_tx : dprioin_rcascaded_8b10b_en_tx; assign cram_r8b10b_enc_ibm_en = (dpriodisable_in == 1'b1) ? init_r8b10b_enc_ibm_en : dprioin_r8b10b_enc_ibm_en; assign cram_rendec_tx = (dpriodisable_in == 1'b1) ? init_rendec_tx : dprioin_rendec_tx; // PCS Per Channel TX Control Register 3 for Channel 0 assign cram_reserved_0_TB3 = (dpriodisable_in == 1'b1) ? init_reserved_0_TB3 : dprioin_reserved_0_TB3; assign cram_rcid_len_tx = (dpriodisable_in == 1'b1) ? init_rcid_len_tx : dprioin_rcid_len_tx; assign cram_rcid_pattern_tx = (dpriodisable_in == 1'b1) ? init_rcid_pattern_tx : dprioin_rcid_pattern_tx; assign cram_rtxpcsclkpwdn = (dpriodisable_in == 1'b1) ? init_rtxpcsclkpwdn : dprioin_rtxpcsclkpwdn; assign cram_rtxswing_sel_ena = (dpriodisable_in == 1'b1) ? init_rtxswing_sel_ena : dprioin_rtxswing_sel_ena; assign cram_rtx_elec_idle_delay = (dpriodisable_in == 1'b1) ? init_rtx_elec_idle_delay : dprioin_rtx_elec_idle_delay; assign cram_rtx_pipe_enable = (dpriodisable_in == 1'b1) ? init_rtx_pipe_enable : dprioin_rtx_pipe_enable; // PCS Per Channel TX Control Register 4 for Channel 0 assign cram_reserved_0_TB4 = (dpriodisable_in == 1'b1) ? init_reserved_0_TB4 : dprioin_reserved_0_TB4; assign cram_rtxbitslip_en = (dpriodisable_in == 1'b1) ? init_rtxbitslip_en : dprioin_rtxbitslip_en; assign cram_rphfifo_regmode_tx = (dpriodisable_in == 1'b1) ? init_rphfifo_regmode_tx : dprioin_rphfifo_regmode_tx; assign cram_rpipeline_bypass_tx = (dpriodisable_in == 1'b1) ? init_rpipeline_bypass_tx : dprioin_rpipeline_bypass_tx; assign cram_rself_sw_en_tx = (dpriodisable_in == 1'b1) ? init_rself_sw_en_tx : dprioin_rself_sw_en_tx; //////////////////////////////////////////////////////////////////////////////// // Connect Atom level input to appropriate RTL - PORT_IN_Table ------------- // //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////////////////////// // datain TXD mapping - datain[32/40], ctrlenable[4], forcedispacompliance, forcedisp[4], dispval[4] //////////////////////////////////////////////////////////////////////////////////////////////////// assign tmp_ctrlenable[0] = (ctrlenable_ipd[0] === 1'b1) ? 1'b1 : 1'b0; assign tmp_ctrlenable[1] = (ctrlenable_ipd[1] === 1'b1) ? 1'b1 : 1'b0; assign tmp_ctrlenable[2] = (ctrlenable_ipd[2] === 1'b1) ? 1'b1 : 1'b0; assign tmp_ctrlenable[3] = (ctrlenable_ipd[3] === 1'b1) ? 1'b1 : 1'b0; assign tmp_dispval[0] = (dispval_ipd[0] === 1'b1) ? 1'b1 : 1'b0; assign tmp_dispval[1] = (dispval_ipd[1] === 1'b1) ? 1'b1 : 1'b0; assign tmp_dispval[2] = (dispval_ipd[2] === 1'b1) ? 1'b1 : 1'b0; assign tmp_dispval[3] = (dispval_ipd[3] === 1'b1) ? 1'b1 : 1'b0; assign tmp_forcedisp[0] = (forcedisp_ipd[0] === 1'b1) ? 1'b1 : 1'b0; assign tmp_forcedisp[1] = (forcedisp_ipd[1] === 1'b1) ? 1'b1 : 1'b0; assign tmp_forcedisp[2] = (forcedisp_ipd[2] === 1'b1) ? 1'b1 : 1'b0; assign tmp_forcedisp[3] = (forcedisp_ipd[3] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[0] = (datain_ipd[0] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[1] = (datain_ipd[1] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[2] = (datain_ipd[2] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[3] = (datain_ipd[3] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[4] = (datain_ipd[4] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[5] = (datain_ipd[5] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[6] = (datain_ipd[6] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[7] = (datain_ipd[7] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[8] = (datain_ipd[8] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[9] = (datain_ipd[9] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[10] = (datain_ipd[10] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[11] = (datain_ipd[11] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[12] = (datain_ipd[12] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[13] = (datain_ipd[13] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[14] = (datain_ipd[14] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[15] = (datain_ipd[15] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[16] = (datain_ipd[16] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[17] = (datain_ipd[17] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[18] = (datain_ipd[18] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[19] = (datain_ipd[19] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[20] = (datain_ipd[20] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[21] = (datain_ipd[21] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[22] = (datain_ipd[22] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[23] = (datain_ipd[23] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[24] = (datain_ipd[24] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[25] = (datain_ipd[25] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[26] = (datain_ipd[26] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[27] = (datain_ipd[27] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[28] = (datain_ipd[28] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[29] = (datain_ipd[29] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[30] = (datain_ipd[30] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[31] = (datain_ipd[31] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[32] = (datain_ipd[32] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[33] = (datain_ipd[33] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[34] = (datain_ipd[34] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[35] = (datain_ipd[35] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[36] = (datain_ipd[36] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[37] = (datain_ipd[37] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[38] = (datain_ipd[38] === 1'b1) ? 1'b1 : 1'b0; assign tmp_datain[39] = (datain_ipd[39] === 1'b1) ? 1'b1 : 1'b0; assign pi_in_txd_ch_tmp[7:0] = tmp_datain[7:0]; assign pi_in_txd_ch_tmp[8] = (cram_rendec_tx == 1'b1) ? tmp_ctrlenable[0] : cram_rpmadwidth_tx == 1'b1 ? tmp_datain[8] : 1'bx; assign pi_in_txd_ch_tmp[9] = (cram_rendec_tx == 1'b1) ? tmp_forcedisp[0] : cram_rpmadwidth_tx == 1'b1 ? tmp_datain[9] : 1'bx; assign pi_in_txd_ch_tmp[10] = (cram_rendec_tx == 1'b1) ? tmp_dispval[0] : 1'bx; assign pi_in_txd_ch_tmp[18:11] = (cram_rendec_tx == 1'b1 || cram_rpmadwidth_tx == 1'b0) ? tmp_datain[15:8] : tmp_datain[17:10]; assign pi_in_txd_ch_tmp[19] = (cram_rendec_tx == 1'b1) ? tmp_ctrlenable[1] : cram_rpmadwidth_tx == 1'b1 ? tmp_datain[18] : 1'bx; assign pi_in_txd_ch_tmp[20] = (cram_rendec_tx == 1'b1) ? tmp_forcedisp[1] : cram_rpmadwidth_tx == 1'b1 ? tmp_datain[19] : 1'bx; assign pi_in_txd_ch_tmp[21] = (cram_rendec_tx == 1'b1) ? tmp_dispval[1] : 1'bx; assign pi_in_txd_ch_tmp[29:22] = (cram_rendec_tx == 1'b1 || cram_rpmadwidth_tx == 1'b0) ? tmp_datain[23:16] : tmp_datain[27:20]; assign pi_in_txd_ch_tmp[30] = (cram_rendec_tx == 1'b1) ? tmp_ctrlenable[2] : cram_rpmadwidth_tx == 1'b1 ? tmp_datain[28] : 1'bx; assign pi_in_txd_ch_tmp[31] = (cram_rendec_tx == 1'b1) ? tmp_forcedisp[2] : cram_rpmadwidth_tx == 1'b1 ? tmp_datain[29] : 1'bx; assign pi_in_txd_ch_tmp[32] = (cram_rendec_tx == 1'b1) ? tmp_dispval[2] : 1'bx; assign pi_in_txd_ch_tmp[40:33] = (cram_rendec_tx == 1'b1 || cram_rpmadwidth_tx == 1'b0) ? tmp_datain[31:24] : tmp_datain[37:30]; assign pi_in_txd_ch_tmp[41] = (cram_rendec_tx == 1'b1) ? tmp_ctrlenable[3] : cram_rpmadwidth_tx == 1'b1 ? tmp_datain[38] : 1'bx; assign pi_in_txd_ch_tmp[42] = (cram_rendec_tx == 1'b1) ? tmp_forcedisp[3] : cram_rpmadwidth_tx == 1'b1 ? tmp_datain[39] : 1'bx; assign pi_in_txd_ch_tmp[43] = (cram_rendec_tx == 1'b1) ? tmp_dispval[3] : 1'bx; //interleaving assign pi_in_txd_ch[10:0] = pi_in_txd_ch_tmp[10:0]; assign pi_in_txd_ch[32:22] = (cram_rdwidth_tx == 1'b1 && cram_rpma_doublewidth_tx == 1'b0) ? pi_in_txd_ch_tmp[21:11] : pi_in_txd_ch_tmp[32:22]; assign pi_in_txd_ch[21:11] = (cram_rdwidth_tx == 1'b1 && cram_rpma_doublewidth_tx == 1'b0) ? pi_in_txd_ch_tmp[32:22] : pi_in_txd_ch_tmp[21:11]; assign pi_in_txd_ch[43:33] = pi_in_txd_ch_tmp[43:33]; assign pi_in_txd_ch_dprio = ((dprio_config_mode & DPRIO_CHANNEL_INTERFACE_BIT) != 0) ? datainfull : pi_in_txd_ch; //////////////////////////////////////////////////////////////////////////////// // Connect Atom level output to appropriate RTL - PORT_OUT_Table ----------- // //////////////////////////////////////////////////////////////////////////////// assign clkout = td_out_tx_clk_out; assign dataout = td_out_pudr; assign parallelfdbkout = td_out_txlp20b; assign phfifooverflow = td_out_full_tx; assign phfifounderflow = td_out_empty_tx; assign pipepowerdownout = td_out_powerdown_int; assign pipepowerstateout = pi_out_powerstate[3:0]; assign rdenablesync = td_out_rd_enable_sync; assign txdetectrx = pi_out_txdetectrx; assign xgmctrlenable = td_out_tx_ctl_tc; assign xgmdataout = td_out_tx_data_tc; // ww47 output ---------------------------------------------------------------- assign coreclkout = coreclk_ipd; assign hiptxclkout = hs_out_hip_tx_clk; assign iqpphfifobyteselout = td_out_fifo_select_out_pipe; assign iqpphfifordclkout = td_out_tx_div2_sync_out_pipe; assign iqpphfifordenableout = td_out_rd_enable_out_pipe; assign iqpphfifowrenableout = td_out_wr_enable_out_pipe; assign phfiforddisableout = phfiforddisable_ipd; assign phfiforesetout = phfiforeset_ipd; assign phfifowrenableout = phfifowrenable_ipd; // ww12 output ---------------------------------------------------------------- assign grayelecidleinferselout = td_out_gray_eidleinfersel; assign pipeenrevparallellpbkout = pi_out_rev_loopbk; // to td and rd // q90 ww47 fix --------------------------------------------------------------- assign forceelecidleout = pi_out_tx_elec_idle; //////////////////////////////////////////////////////////////////////////////// // tx sub-block instantiation: pcs_reset -------------------------------------// //////////////////////////////////////////////////////////////////////////////// assign pr_in_hard_reset = (quadreset === 1'b1) ? 1'b1 : 1'b0; // from top assign pr_in_clk_2_b = 1'b0; // for rx side assign pr_in_refclk_b_in = td_out_refclk_b; assign pr_in_scan_mode = 1'b0; assign pr_in_rxpcs_rst = 1'b0; // for rx side assign pr_in_txpcs_rst = (digitalreset === 1'b1) ? 1'b1 : 1'b0; // from top stratixiv_hssi_pcs_reset tx_pcs_reset_1 ( .hard_reset (pr_in_hard_reset), .clk_2_b (pr_in_clk_2_b), .refclk_b_in (pr_in_refclk_b_in), .scan_mode (pr_in_scan_mode), .rxpcs_rst (pr_in_rxpcs_rst), .txpcs_rst (pr_in_txpcs_rst), .rxrst_int (rxrst_int_wire), .txrst_int (pr_out_txrst_int) ); //////////////////////////////////////////////////////////////////////////////// // tx sub-block instantiation: chnl_hip_support ------------------------------// //////////////////////////////////////////////////////////////////////////////// assign hs_in_eidleinfersel_ch = elecidleinfersel_in; assign hs_in_hip_eidleinfersel_ch = hipelecidleinfersel_in; assign hs_in_hip_powerdown_ch = hippowerdn_in; assign hs_in_hip_rate = 1'bx; assign hs_in_hip_rxpolarity = 1'bx; assign hs_in_hip_txd_ch = hipdatain_in; assign hs_in_hip_txdeemph = hiptxdeemph_in; assign hs_in_hip_txdetectrxloopback = (hipdetectrxloop_in === 1'b1) ? 1'b1 : 1'b0; assign hs_in_hip_txelecidle = hipforceelecidle_in; assign hs_in_hip_txmargin_ch = hiptxmargin_in; assign hs_in_pcs_phystatus = 1'bx; assign hs_in_pcs_rxd_ch = 9'bxxxxxxxxx; assign hs_in_pcs_rxelecidle = 1'bx; assign hs_in_pcs_rxstatus_ch = 1'bx; assign hs_in_pcs_rxvalid = 1'bx; assign hs_in_powerdown_ch = powerdn_ipd; assign hs_in_rate = 1'bx; assign hs_in_rhip_ena = cram_rhip_ena; assign hs_in_rxpolarity = 1'bx; assign hs_in_txd_ch = pi_in_txd_ch_dprio[10:0]; assign hs_in_txdeemph = pipetxdeemph_ipd; assign hs_in_txdetectrxloopback = (detectrxloop_ipd === 1'b1) ? 1'b1 : 1'b0; assign hs_in_txmargin_ch = pipetxmargin_ipd; assign hs_in_txpma_local_clk = localrefclk; stratixiv_hssi_digi_chnl_hip_spt mtx_hs( .eidleinfersel_ch ( hs_in_eidleinfersel_ch), .hip_eidleinfersel_ch (hs_in_hip_eidleinfersel_ch ), .hip_powerdown_ch (hs_in_hip_powerdown_ch ), .hip_rate (hs_in_hip_rate ), .hip_rxpolarity (hs_in_hip_rxpolarity ), .hip_txd_ch (hs_in_hip_txd_ch ), .hip_txdeemph (hs_in_hip_txdeemph ), .hip_txdetectrxloopback (hs_in_hip_txdetectrxloopback ), .hip_txelecidle (hs_in_hip_txelecidle ), .hip_txmargin_ch (hs_in_hip_txmargin_ch ), .pcs_phystatus (hs_in_pcs_phystatus ), .pcs_rxd_ch (hs_in_pcs_rxd_ch ), .pcs_rxelecidle (hs_in_pcs_rxelecidle ), .pcs_rxstatus_ch (hs_in_pcs_rxstatus_ch ), .pcs_rxvalid (hs_in_pcs_rxvalid ), .powerdown_ch (hs_in_powerdown_ch ), .rate (hs_in_rate ), .rhip_ena (hs_in_rhip_ena ), .rxpolarity (hs_in_rxpolarity ), .txd_ch (hs_in_txd_ch ), .txdeemph (hs_in_txdeemph ), .txdetectrxloopback (hs_in_txdetectrxloopback ), .txmargin_ch (hs_in_txmargin_ch ), .txpma_local_clk (hs_in_txpma_local_clk ), .hip_phystatus (hs_out_hip_phystatus ), .hip_rxd_ch (hs_out_hip_rxd_ch ), .hip_rxelecidle (hs_out_hip_rxelecidle ), .hip_rxstatus_ch (hs_out_hip_rxstatus_ch ), .hip_rxvalid (hs_out_hip_rxvalid ), .hip_tx_clk (hs_out_hip_tx_clk ), .pcs_eidleinfersel_ch (hs_out_pcs_eidleinfersel_ch ), .pcs_powerdown_ch (hs_out_pcs_powerdown_ch ), .pcs_rate (hs_out_pcs_rate ), .pcs_rxpolarity (hs_out_pcs_rxpolarity ), .pcs_txd_ch (hs_out_pcs_txd_ch ), .pcs_txdeemph (hs_out_pcs_txdeemph ), .pcs_txdetectrxloopback (hs_out_pcs_txdetectrxloopback ), .pcs_txmargin_ch (hs_out_pcs_txmargin_ch ), .phystatus (hs_out_phystatus ), .rxd_ch (hs_out_rxd_ch ), .rxelecidle (hs_out_rxelecidle ), .rxstatus_ch (hs_out_rxstatus_ch ), .rxvalid (hs_out_rxvalid ) ); //////////////////////////////////////////////////////////////////////////////// // tx sub-block instantiation: pipe_interface --------------------------------// //////////////////////////////////////////////////////////////////////////////// assign pi_in_pipe_tx_clk = (cram_rtx_pipe_enable === 1'b0) ? 1'b0 : td_out_tx_pipe_clk; assign pi_in_powerdown = td_out_powerdown_int; assign pi_in_refclk_b = (cram_rtx_pipe_enable === 1'b0) ? 1'b0 : td_out_refclk_b; assign pi_in_refclk_b_reset_n = ~pr_out_txrst_int; assign pi_in_revloopback = td_out_revloopback_int; // (enrevparallellpbk_ipd === 1'b1) ? 1'b1 : 1'b0; assign pi_in_tx_elec_idle_comp = td_out_tx_pipe_electidle; assign pi_in_tx_pipe_reset_n = ~td_out_tx_pipe_soft_reset; assign pi_in_txdetectrxloopback = td_out_txdetectrxloopback_int; assign pi_in_txelecidle = forceelecidle_ipd; assign pi_in_state_transition_done = pipestatetransdone; // new connection in ww12 assign pi_in_txdeemph = td_out_phfifo_txdeemph; assign pi_in_txmargin = td_out_phfifo_txmargin; assign pi_in_txswing = td_out_phfifo_txswing; stratixiv_hssi_tx_pipe_interface tx_pipe_interface_inst ( .clk (pi_in_pipe_tx_clk), .refclk_b (pi_in_refclk_b), .refclk_b_reset_n (pi_in_refclk_b_reset_n), .reset_n (pi_in_tx_pipe_reset_n), .rtx_pipe_enable (cram_rtx_pipe_enable), .rtx_elec_idle_delay (cram_rtx_elec_idle_delay), .txdetectrxloopback (pi_in_txdetectrxloopback), .txelecidle (pi_in_txelecidle), .powerdown (pi_in_powerdown), .txd_ch (pi_in_txd_ch_dprio), .revloopback (pi_in_revloopback), .txd (pi_out_txd), .rev_loopbk (pi_out_rev_loopbk), .tx_elec_idle_comp (pi_in_tx_elec_idle_comp), .tx_elec_idle (pi_out_tx_elec_idle), .txdetectrx (pi_out_txdetectrx), .powerstate (pi_out_powerstate), // new interfaces in STRATIXIV - ww26.5 .rtxswing_sel_ena (cram_rtxswing_sel_ena), .txdeemph (pi_in_txdeemph), .txmargin (pi_in_txmargin), .txswing (pi_in_txswing), .txdeemph_int (pi_out_txdeemph_int), .txmargin_int (pi_out_txmargin_int), .txswing_int (pi_out_txswing_int) ); //////////////////////////////////////////////////////////////////////////////// // tx sub-block instantiation: tx_digi ---------------------------------------// //////////////////////////////////////////////////////////////////////////////// assign td_in_phfifourst_tx = (phfiforeset_ipd === 1'b1) ? 1'b1 : 1'b0; assign td_in_pld_tx_clk = coreclk; // coreclk_ipd; assign td_in_polinv_tx = (invpol_ipd === 1'b1) ? 1'b1 : 1'b0; assign td_in_rddisable_tx = (phfiforddisable_ipd === 1'b1) ? 1'b1 : 1'b0; // enable by default assign td_in_refclk_pma = refclk_ipd; assign td_in_rev_loop_data = revparallelfdbk; assign td_in_rev_loopbk = pi_out_rev_loopbk; assign td_in_tx_data_ts = xgmdatain; assign td_in_tx_ctl_ts = xgmctrl; assign td_in_txd = {pi_in_txd_ch_dprio[43:11], hs_out_pcs_txd_ch};//pi_in_txd_ch_dprio; // pi_out_txd - 44 bit assign td_in_txpcs_rst = pr_out_txrst_int; assign td_in_txpma_local_clk = localrefclk; assign td_in_wrenable_tx = (phfifowrenable_ipd === 1'b0) ? 1'b0 : 1'b1; // enable by default // new input in STRATIXIV - ww26.5 -------------------------------------------------- assign td_in_gen2ngen1 = (rateswitchisdone === 1'b1) ? 1'b1 : 1'b0; //from tx_pma local clk divider assign td_in_gen2ngen1_bundle = (rateswitchxndone === 1'b1) ? 1'b1 : 1'b0; //from central clk divider assign td_in_polinv_rx = 1'b0; // leaving it out of tx as it is a simple wire in tx_ctrl assign td_in_powerdown = hs_out_pcs_powerdown_ch; assign td_in_revloopback = (enrevparallellpbk_ipd === 1'b1) ? 1'b1 : 1'b0; assign td_in_rxpolarity = 1'b0; //// leaving it out of tx as it is a simple wire in tx_ctrl assign td_in_txdetectrxloopback = hs_out_pcs_txdetectrxloopback; assign td_in_prbs_cid_en = prbscidenable_in; assign td_in_tx_boundary_sel = bitslipboundaryselect_in; // new signal inputs for bundling // temporary disabled by forcing rindv_tx = 1'b0 todo assign td_in_tx_div2_sync_in_centrl = phfifoxnrdclk_in[MPHFIFO_INDEX]; assign td_in_tx_div2_sync_in_quad_up = phfifoxnrdclk_in[MPHFIFO_INDEX]; assign td_in_tx_div2_sync_in_quad_down = phfifoxnrdclk_in[MPHFIFO_INDEX]; assign td_in_wr_enable_in_centrl = phfifoxnwrenable_in[MPHFIFO_INDEX]; assign td_in_wr_enable_in_quad_up = phfifoxnwrenable_in[MPHFIFO_INDEX]; assign td_in_wr_enable_in_quad_down = phfifoxnwrenable_in[MPHFIFO_INDEX]; assign td_in_rd_enable_in_centrl = phfifoxnrdenable_in[MPHFIFO_INDEX]; assign td_in_rd_enable_in_quad_up = phfifoxnrdenable_in[MPHFIFO_INDEX]; assign td_in_rd_enable_in_quad_down = phfifoxnrdenable_in[MPHFIFO_INDEX]; assign td_in_fifo_select_in_centrl = phfifoxnbytesel_in[MPHFIFO_INDEX]; assign td_in_fifo_select_in_quad_up = phfifoxnbytesel_in[MPHFIFO_INDEX]; assign td_in_fifo_select_in_quad_down = phfifoxnbytesel_in[MPHFIFO_INDEX]; assign td_in_reset_pc_ptrs = phfifoptrsreset_in; // from rx assign td_in_reset_pc_ptrs_in_centrl = phfifoxnptrsreset_in[MPHFIFO_INDEX]; assign td_in_reset_pc_ptrs_in_quad_up = phfifoxnptrsreset_in[MPHFIFO_INDEX]; assign td_in_reset_pc_ptrs_in_quad_down = phfifoxnptrsreset_in[MPHFIFO_INDEX]; assign td_in_tx_div2_sync_in_pipe_quad_up = iqpphfifoxnrdclk_in[MIQP_PHFIFO_INDEX]; assign td_in_tx_div2_sync_in_pipe_quad_down = iqpphfifoxnrdclk_in[MIQP_PHFIFO_INDEX]; assign td_in_wr_enable_in_pipe_quad_up = iqpphfifoxnwrenable_in[MIQP_PHFIFO_INDEX]; assign td_in_wr_enable_in_pipe_quad_down = iqpphfifoxnwrenable_in[MIQP_PHFIFO_INDEX]; assign td_in_rd_enable_in_pipe_quad_up = iqpphfifoxnrdenable_in[MIQP_PHFIFO_INDEX]; assign td_in_rd_enable_in_pipe_quad_down = iqpphfifoxnrdenable_in[MIQP_PHFIFO_INDEX]; assign td_in_fifo_select_in_pipe_quad_up = iqpphfifoxnbytesel_in[MIQP_PHFIFO_INDEX]; assign td_in_fifo_select_in_pipe_quad_down = iqpphfifoxnbytesel_in[MIQP_PHFIFO_INDEX]; assign td_in_dis_pc_byte = phfifobyteserdisable_in; // from rx // push through TX Phase Comp FIFO assign td_in_txswing = pipetxswing_ipd; assign td_in_pcs_txdeemph = hs_out_pcs_txdeemph; assign td_in_pcs_txmargin = hs_out_pcs_txmargin_ch; // RX PIPE interface signals assign td_in_eidleinfersel = hs_out_pcs_eidleinfersel_ch; assign td_out_tx_div2_sync_out_pipe = (cram_rmaster_up_tx === 1'b0) ? td_out_tx_div2_sync_out_pipe_up : td_out_tx_div2_sync_out_pipe_down; assign td_out_fifo_select_out_pipe = (cram_rmaster_up_tx === 1'b0) ? td_out_fifo_select_out_pipe_up : td_out_fifo_select_out_pipe_down; assign td_out_wr_enable_out_pipe = (cram_rmaster_up_tx === 1'b0) ? td_out_wr_enable_out_pipe_up : td_out_wr_enable_out_pipe_down; assign td_out_rd_enable_out_pipe = (cram_rmaster_up_tx === 1'b0) ? td_out_rd_enable_out_pipe_up : td_out_rd_enable_out_pipe_down; stratixiv_hssi_tx_digi digi_tx_1 ( .empty_tx (td_out_empty_tx), .encoder_testbus (td_out_encoder_testbus), .full_tx (td_out_full_tx), .phfifourst_tx (td_in_phfifourst_tx), .pld_tx_clk (td_in_pld_tx_clk), .polinv_tx (td_in_polinv_tx), .pudr (td_out_pudr), .r8b10b_enc_ibm_en (cram_r8b10b_enc_ibm_en), .rbist_sel (cram_rbist_sel), .rbisten_tx (cram_rbisten_tx), .rcascaded_8b10b_en_tx (cram_rcascaded_8b10b_en_tx), .rcxpat_chnl_en (cram_rcxpat_chnl_en), .rd_enable_sync (td_out_rd_enable_sync), .rddisable_tx (td_in_rddisable_tx), .rdwidth_tx (cram_rdwidth_tx), .refclk_b (td_out_refclk_b), .refclk_pma (td_in_refclk_pma), .renbitrev_tx (cram_renbitrev_tx), .rendec_data_sel_tx (cram_rendec_data_sel_tx), .rendec_tx (cram_rendec_tx), .renpolinv_tx (cram_renpolinv_tx), .rensymswap_tx (cram_rensymswap_tx), .rev_loop_data (td_in_rev_loop_data), .rev_loopbk (td_in_rev_loopbk), .rforce_disp (cram_rforce_disp), .rforce_echar (cram_rforce_echar), .rforce_kchar (cram_rforce_kchar), .rfreerun_tx (cram_rfreerun_tx), .rge_xaui_tx (cram_rge_xaui_tx), .rib_force_disp (cram_rib_force_disp), .rindv_tx (cram_rindv_tx), .rphfifopldentx (cram_rphfifopldentx), .rphfifoursttx (cram_rphfifoursttx), .rpma_doublewidth_tx (cram_rpma_doublewidth_tx), .rpmadwidth_tx (cram_rpmadwidth_tx), .rprbs_sel (cram_rprbs_sel), .rprbsen_tx (cram_rprbsen_tx), .rrev_loopbk (cram_rrev_loopbk), .rtx_pipe_enable (cram_rtx_pipe_enable), .rtxfifo_dis (cram_rtxfifo_dis), .rtxfifo_lowlatency_en (cram_rtxfifo_lowlatency_en), .rtxrdclksel (cram_rtxrdclksel), .rtxwrclksel (cram_rtxwrclksel), .scan_mode (cram_scan_mode), .tx_clk_out (td_out_tx_clk_out), .tx_ctl_tc (td_out_tx_ctl_tc), .tx_ctl_ts (td_in_tx_ctl_ts), .tx_ctrl_testbus (td_out_tx_ctrl_testbus), .tx_data_tc (td_out_tx_data_tc), .tx_data_ts (td_in_tx_data_ts), .tx_pipe_clk (td_out_tx_pipe_clk), .tx_pipe_electidle (td_out_tx_pipe_electidle), .tx_pipe_soft_reset (td_out_tx_pipe_soft_reset), .txd (td_in_txd), .txlp20b (td_out_txlp20b), .txpcs_rst (td_in_txpcs_rst), .txpma_local_clk (td_in_txpma_local_clk), .wrenable_tx (td_in_wrenable_tx), .gen2ngen1 (td_in_gen2ngen1), .gen2ngen1_bundle (td_in_gen2ngen1_bundle), .polinv_rx (td_in_polinv_rx), .powerdown (td_in_powerdown), .revloopback (td_in_revloopback), .rxpolarity (td_in_rxpolarity), .txdetectrxloopback (td_in_txdetectrxloopback), .rauto_speed_ena (cram_rauto_speed_ena), .rfreq_sel (cram_rfreq_sel), .rtxpcsbypass_en (cram_rtxpcsbypass_en), .rtxpcsclkpwdn (cram_rtxpcsclkpwdn), .polinv_rx_int (td_out_polinv_rx_int), .powerdown_int (td_out_powerdown_int), .revloopback_int (td_out_revloopback_int), .rxpolarity_int (td_out_rxpolarity_int), .txdetectrxloopback_int (td_out_txdetectrxloopback_int), .prbs_cid_en (td_in_prbs_cid_en), .tx_boundary_sel (td_in_tx_boundary_sel), .rcid_pattern_tx (cram_rcid_pattern_tx), .rcid_len_tx (cram_rcid_len_tx), .tx_div2_sync_in_centrl (td_in_tx_div2_sync_in_centrl), .tx_div2_sync_in_quad_up (td_in_tx_div2_sync_in_quad_up), .tx_div2_sync_in_quad_down (td_in_tx_div2_sync_in_quad_down), .wr_enable_in_centrl (td_in_wr_enable_in_centrl), .wr_enable_in_quad_up (td_in_wr_enable_in_quad_up), .wr_enable_in_quad_down (td_in_wr_enable_in_quad_down), .rd_enable_in_centrl (td_in_rd_enable_in_centrl), .rd_enable_in_quad_up (td_in_rd_enable_in_quad_up), .rd_enable_in_quad_down (td_in_rd_enable_in_quad_down), .fifo_select_in_centrl (td_in_fifo_select_in_centrl), .fifo_select_in_quad_up (td_in_fifo_select_in_quad_up), .fifo_select_in_quad_down (td_in_fifo_select_in_quad_down), .reset_pc_ptrs (td_in_reset_pc_ptrs), .reset_pc_ptrs_in_centrl (td_in_reset_pc_ptrs_in_centrl), .reset_pc_ptrs_in_quad_up (td_in_reset_pc_ptrs_in_quad_up), .reset_pc_ptrs_in_quad_down (td_in_reset_pc_ptrs_in_quad_down), .tx_div2_sync_in_pipe_quad_up (td_in_tx_div2_sync_in_pipe_quad_up), .tx_div2_sync_in_pipe_quad_down (td_in_tx_div2_sync_in_pipe_quad_down), .wr_enable_in_pipe_quad_up (td_in_wr_enable_in_pipe_quad_up), .wr_enable_in_pipe_quad_down (td_in_wr_enable_in_pipe_quad_down), .rd_enable_in_pipe_quad_up (td_in_rd_enable_in_pipe_quad_up), .rd_enable_in_pipe_quad_down (td_in_rd_enable_in_pipe_quad_down), .fifo_select_in_pipe_quad_up (td_in_fifo_select_in_pipe_quad_up), .fifo_select_in_pipe_quad_down (td_in_fifo_select_in_pipe_quad_down), .dis_pc_byte (td_in_dis_pc_byte), .rmaster_tx (cram_rmaster_tx), .rmaster_up_tx (cram_rmaster_up_tx), .rself_sw_en_tx (cram_rself_sw_en_tx), .rpipeline_bypass_tx (cram_rpipeline_bypass_tx), .rphfifo_regmode_tx (cram_rphfifo_regmode_tx), .tx_div2_sync_out_pipe_up (td_out_tx_div2_sync_out_pipe_up), .fifo_select_out_pipe_up (td_out_fifo_select_out_pipe_up), .wr_enable_out_pipe_up (td_out_wr_enable_out_pipe_up), .rd_enable_out_pipe_up (td_out_rd_enable_out_pipe_up), .tx_div2_sync_out_pipe_down (td_out_tx_div2_sync_out_pipe_down), .fifo_select_out_pipe_down (td_out_fifo_select_out_pipe_down), .wr_enable_out_pipe_down (td_out_wr_enable_out_pipe_down), .rd_enable_out_pipe_down (td_out_rd_enable_out_pipe_down), .txswing (td_in_txswing), .pcs_txdeemph (td_in_pcs_txdeemph), .pcs_txmargin (td_in_pcs_txmargin), .eidleinfersel (td_in_eidleinfersel), .phfifo_txswing (td_out_phfifo_txswing), .phfifo_txdeemph (td_out_phfifo_txdeemph), .phfifo_txmargin (td_out_phfifo_txmargin), .gray_eidleinfersel (td_out_gray_eidleinfersel), .rtxbitslip_en (cram_rtxbitslip_en) ); endmodule // stratixiigx_hssi_transmitter //Rev: 1.13 Tue Aug 12 10:38:50 PDT 2008 // `timescale 1 ps / 1 ps module stratixiv_hssi_rx_digis_ph_fifo ( // inputs rst_wclk, rst_rclk, wr_clk, rd_clk, en, lowlatency_en, we, re, din, rphfifo_regmode_rx, rindv_rx, rauto_speed_ena, reset_pc_ptrs, reset_pc_ptrs_centrl, reset_pc_ptrs_quad_up, reset_pc_ptrs_quad_down, rmaster_rx, rmaster_up_rx, // outputs data_out, ph_fifo_full, ph_fifo_empty, wptr_bin, rptr_bin, pcs_wrapback_in, rpcs_wrapback_en, scan_mode ); // ======= // inputs // ======= input rst_wclk; input rst_rclk; input wr_clk; // Write Clock input rd_clk; // Read Clock input en; // Disable FIFO or bypass - only for Altera internal debug input lowlatency_en; // low latency enable input we; // PLD dynamic write pointer enable input re; // PLD dynamic read pointer enable input [69:0] din; // 10-bit code-group bus from deskew module. input rphfifo_regmode_rx; input rindv_rx; input rmaster_rx; input rmaster_up_rx; input rauto_speed_ena; input reset_pc_ptrs; input reset_pc_ptrs_centrl; input reset_pc_ptrs_quad_up; input reset_pc_ptrs_quad_down; input [69:0] pcs_wrapback_in; input rpcs_wrapback_en; input scan_mode; // ======= // outputs // ======= output ph_fifo_full; // Indicates overflow (rd_clk) output ph_fifo_empty; // FIFO empty (rd_clk) output [69:0] data_out; // output data (rd_clk synchronous if not FIFO bypass) output [2:0] wptr_bin; // test bus output [2:0] rptr_bin; // test bus // =================== // signal declaration // =================== reg [ 7:0] wptr, rptr; reg [ 2:0] wptr_gray; reg [ 2:0] wptr_gray0; reg [ 2:0] wptr0; reg [ 2:0] wptr1; reg [ 7:0] wptr1_onehot; reg [ 7:0] rptr0_pre; reg [ 7:0] rptr0; reg [ 7:0] rptr1; reg first_rd; reg [69:0] ram_data_out; wire [69:0] ram_data_out_pre; reg [2:0] wptr_bin; // test bus reg [2:0] rptr_bin; // test bus reg ph_fifo_full, ph_fifo_empty; reg ph_fifo_empty_pre; wire rst_n; // Invert rst for new FIFO wire [3:0] fifo_cnt; reg [3:0] fifo_cnt_pre; reg [2:0] rptr1_bin; reg [2:0] wptr1_bin_rclk; wire reset_ptrs_local; reg reset_ptrs_local_sync1; reg reset_ptrs_local_sync2; // ============= // functionality // ============= assign rst_n = ~rst_wclk; // bypass assign data_out[69:0] = en ? ram_data_out : din; assign reset_ptrs_local = rauto_speed_ena & (rmaster_rx ? (rindv_rx ? reset_pc_ptrs : reset_pc_ptrs_centrl) : (rmaster_up_rx ? reset_pc_ptrs_quad_up : reset_pc_ptrs_quad_down)); // write pointer always @ (posedge rst_wclk or posedge wr_clk) begin if (rst_wclk == 1'b1) begin wptr <= #1 8'h01; end else if (rphfifo_regmode_rx) begin wptr <= #1 8'h01; end else if (reset_ptrs_local) begin wptr <= #1 8'h01; end else begin if (we == 1'b1) wptr <= #1 {wptr[6:0],wptr[7]}; end end // always @ (posedge rst_wclk or posedge wr_clk) //newly added fifo_cnt and fifo_cnt_pre logic for full/empty flag use assign fifo_cnt = (rptr1_bin == wptr1_bin_rclk) ? //((rst_rclk != 1'b1) ? ((fifo_cnt_pre==4'd1)?4'd0:4'd8) : 4'd0) : ((rst_rclk != 1'b1) ? (((fifo_cnt_pre==4'd7 || fifo_cnt_pre==4'd6||fifo_cnt_pre==4'd8))?4'd8:4'd0) : 4'd0) : ((wptr1_bin_rclk > rptr1_bin) ? (wptr1_bin_rclk - rptr1_bin) : (4'd8 - (rptr1_bin - wptr1_bin_rclk))); always @ (posedge rst_rclk or posedge rd_clk) begin if (rst_rclk == 1'b1) begin reset_ptrs_local_sync1 <= #1 1'b0; reset_ptrs_local_sync2 <= #1 1'b0; end // if (rst_rclk == 1'b1) else if (rphfifo_regmode_rx) begin reset_ptrs_local_sync1 <= #1 1'b0; reset_ptrs_local_sync2 <= #1 1'b0; end else begin reset_ptrs_local_sync1 <= #1 reset_ptrs_local; reset_ptrs_local_sync2 <= #1 reset_ptrs_local_sync1; end end // always @ (posedge rst_rclk or posedge rd_clk) //ECO for S4GX to fix metastability issue // replace the 1st FF with new flop w/o reset // replace the 2nd FF with an enhanced flop always @ (posedge rd_clk) begin if (reset_ptrs_local_sync2 || rphfifo_regmode_rx) wptr0 <= #1 3'b001; else wptr0 <= #1 wptr_gray; end // always @ (posedge rst_rclk or posedge rd_clk) always @ (posedge rst_rclk or posedge rd_clk) begin if (rst_rclk == 1'b1) wptr1 <= #1 3'b001; else if (reset_ptrs_local_sync2 || rphfifo_regmode_rx) wptr1 <= #1 3'b001; else wptr1 <= #1 wptr0; end // always @ (posedge rst_rclk or posedge rd_clk) // read pointer // full & empty always @ (posedge rst_rclk or posedge rd_clk) begin if (rst_rclk == 1'b1) begin rptr <= #1 8'h20; rptr0_pre <= #1 8'h10; rptr0 <= #1 8'h10; rptr1 <= #1 8'h10; ph_fifo_full <= #1 1'b0; ph_fifo_empty <= #1 1'b0; ph_fifo_empty_pre <= #1 1'b0; first_rd <= #1 1'b1; fifo_cnt_pre <= #1 4'b0000; // fifo_cnt previous value end // if (rst_rclk == 1'b1) else if (reset_ptrs_local_sync2 || rphfifo_regmode_rx) begin rptr <= #1 8'h20; rptr0_pre <= #1 8'h10; rptr0 <= #1 8'h10; rptr1 <= #1 8'h10; ph_fifo_full <= #1 1'b0; ph_fifo_empty <= #1 1'b0; ph_fifo_empty_pre <= #1 1'b0; first_rd <= #1 1'b1; fifo_cnt_pre <= #1 4'b0000; // fifo_cnt previous value end // if (reset_ptrs_local_sync2) else begin ph_fifo_empty <= #1 ph_fifo_empty_pre; fifo_cnt_pre <= #1 fifo_cnt; rptr0_pre <= #1 rptr; rptr0 <= #1 rptr0_pre; rptr1 <= #1 rptr0; if (first_rd == 1'b1 && re == 1'b1) first_rd <= #1 1'b0; // advance by 2 on first read in low-latency mode if (re == 1'b1) if (first_rd == 1'b1 && lowlatency_en == 1'b1) rptr <= #1 {rptr[5:0],rptr[7:6]}; else rptr <= #1 {rptr[6:0],rptr[7]}; // full condition //$if ({wptr1_onehot[6:0],wptr1_onehot[7]} == rptr1) //new full flag requirement if (({rptr1[6:0],rptr1[7]} == wptr1_onehot) && (fifo_cnt_pre==4'd7 || fifo_cnt_pre==4'd8) && (!ph_fifo_empty_pre)) ph_fifo_full <= #1 1'b1; //else if (ph_fifo_full == 1'b1 && ({rptr1[6:0],rptr1[7]} != wptr1_onehot)) //become sticky until reset //ph_fifo_full <= #1 1'b0; // empty condition //$if ({rptr1[6:0],rptr1[7]} == wptr1_onehot) //new empty flag requirement if (fifo_cnt==4'd0 && (!ph_fifo_full)) ph_fifo_empty_pre <= #1 1'b1; //else if (ph_fifo_empty_pre == 1'b1 && (rptr1 != wptr1_onehot)) // become sticky until reset //ph_fifo_empty_pre <= #1 1'b0; end // else: !if(rst_rclk == 1'b1) end // always @ (posedge rst_rclk or posedge rd_clk) /*ram8x65_syn ram8x65_syn_1 ( .rst_l (rst_n), .clk (wr_clk), .fifo_wr (wptr), .data_in (din), .fifo_re (rptr), .data_out(ram_data_out_pre) ); */ stratixiv_hssi_rx_digis_ram8x70_syn ram8x70_syn_1 ( .rst_l (rst_n), .clk (wr_clk), .fifo_wr (wptr), .data_in (din), .fifo_re (rptr), .data_out(ram_data_out_pre) ); always @ (posedge rst_rclk or posedge rd_clk) begin if (rst_rclk) begin ram_data_out <= #1 70'h000000000000000000; end else if (rphfifo_regmode_rx) begin ram_data_out <= #1 din; end else begin ram_data_out <= #1 ram_data_out_pre; end end // always @ (posedge rst_rclk or posedge rd_clk) always@(wptr) begin case(wptr) 8'h01: wptr_bin = 3'h0; 8'h02: wptr_bin = 3'h1; 8'h04: wptr_bin = 3'h2; 8'h08: wptr_bin = 3'h3; 8'h10: wptr_bin = 3'h4; 8'h20: wptr_bin = 3'h5; 8'h40: wptr_bin = 3'h6; 8'h80: wptr_bin = 3'h7; default: wptr_bin = 3'h7; endcase // case(wptr) end // always@ (wptr) always@(rptr) begin case(rptr) 8'h01: rptr_bin = 3'h0; 8'h02: rptr_bin = 3'h1; 8'h04: rptr_bin = 3'h2; 8'h08: rptr_bin = 3'h3; 8'h10: rptr_bin = 3'h4; 8'h20: rptr_bin = 3'h5; 8'h40: rptr_bin = 3'h6; 8'h80: rptr_bin = 3'h7; default: rptr_bin = 3'h7; endcase // case(rptr) end // always@ (rptr) always@(rptr1) begin case(rptr1) 8'h01: rptr1_bin = 3'h0; 8'h02: rptr1_bin = 3'h1; 8'h04: rptr1_bin = 3'h2; 8'h08: rptr1_bin = 3'h3; 8'h10: rptr1_bin = 3'h4; 8'h20: rptr1_bin = 3'h5; 8'h40: rptr1_bin = 3'h6; 8'h80: rptr1_bin = 3'h7; default: rptr1_bin = 3'h7; endcase // case(rptr1) end // always@ (rptr1) always @ (posedge rst_wclk or posedge wr_clk) begin if (rst_wclk == 1'b1) wptr_gray <= #1 3'h0; else wptr_gray <= #1 wptr_gray0; end always@(wptr) begin case(wptr) 8'h01: wptr_gray0 = 3'h0; 8'h02: wptr_gray0 = 3'h1; 8'h04: wptr_gray0 = 3'h3; 8'h08: wptr_gray0 = 3'h2; 8'h10: wptr_gray0 = 3'h6; 8'h20: wptr_gray0 = 3'h7; 8'h40: wptr_gray0 = 3'h5; 8'h80: wptr_gray0 = 3'h4; default: wptr_gray0 = 3'h0; endcase // case(wptr) end // always@ (wptr) always@(wptr1) begin case(wptr1) 3'h0: wptr1_onehot = 8'h01; 3'h1: wptr1_onehot = 8'h02; 3'h3: wptr1_onehot = 8'h04; 3'h2: wptr1_onehot = 8'h08; 3'h6: wptr1_onehot = 8'h10; 3'h7: wptr1_onehot = 8'h20; 3'h5: wptr1_onehot = 8'h40; 3'h4: wptr1_onehot = 8'h80; default: wptr1_onehot = 8'h80; endcase // case(wptr1) end // always@ (wptr1) always@(wptr1) begin case(wptr1) 3'h0: wptr1_bin_rclk = 3'h0; 3'h1: wptr1_bin_rclk = 3'h1; 3'h3: wptr1_bin_rclk = 3'h2; 3'h2: wptr1_bin_rclk = 3'h3; 3'h6: wptr1_bin_rclk = 3'h4; 3'h7: wptr1_bin_rclk = 3'h5; 3'h5: wptr1_bin_rclk = 3'h6; 3'h4: wptr1_bin_rclk = 3'h7; default: wptr1_bin_rclk = 3'h0; endcase // case(wptr1) end // always@ (wptr1) endmodule // ph_fifo_rx `timescale 1ns / 1ps module stratixiv_hssi_rx_digis_ram16x14_syn ( clk, rst_l, addr_wr, addr_rd1, addr_rd2, data_in, we, re_l, data_out1, data_out2 ); input clk; input rst_l; input [15:0] addr_wr; input [15:0] addr_rd1; input [15:0] addr_rd2; input [13:0] data_in; input we, re_l; output [13:0] data_out1; output [13:0] data_out2; parameter read_access_time = 0; parameter write_access_time = 0; parameter ram_width = 14; reg [ram_width-1:0] data_out1_i, data_out2_i; reg [ram_width-1:0] ram_array_d_0, ram_array_d_1, ram_array_d_2, ram_array_d_3, ram_array_d_4, ram_array_d_5, ram_array_d_6, ram_array_d_7, ram_array_d_8, ram_array_d_9, ram_array_d_10, ram_array_d_11, ram_array_d_12, ram_array_d_13, ram_array_d_14, ram_array_d_15, ram_array_q_0, ram_array_q_1, ram_array_q_2, ram_array_q_3, ram_array_q_4, ram_array_q_5, ram_array_q_6, ram_array_q_7, ram_array_q_8, ram_array_q_9, ram_array_q_10, ram_array_q_11, ram_array_q_12, ram_array_q_13, ram_array_q_14, ram_array_q_15; wire [ram_width-1:0] data_reg_0, data_reg_1, data_reg_2, data_reg_3, data_reg_4, data_reg_5, data_reg_6, data_reg_7, data_reg_8, data_reg_9, data_reg_10, data_reg_11, data_reg_12, data_reg_13, data_reg_14, data_reg_15; /* Modelling the read port */ /* Assuming address trigerred operation only */ //assignment assign data_reg_0 = ( addr_wr[0] == 1'b1 ) ? data_in : ram_array_q_0, data_reg_1 = ( addr_wr[1] == 1'b1 ) ? data_in : ram_array_q_1, data_reg_2 = ( addr_wr[2] == 1'b1 ) ? data_in : ram_array_q_2, data_reg_3 = ( addr_wr[3] == 1'b1 ) ? data_in : ram_array_q_3, data_reg_4 = ( addr_wr[4] == 1'b1 ) ? data_in : ram_array_q_4, data_reg_5 = ( addr_wr[5] == 1'b1 ) ? data_in : ram_array_q_5, data_reg_6 = ( addr_wr[6] == 1'b1 ) ? data_in : ram_array_q_6, data_reg_7 = ( addr_wr[7] == 1'b1 ) ? data_in : ram_array_q_7, data_reg_8 = ( addr_wr[8] == 1'b1 ) ? data_in : ram_array_q_8, data_reg_9 = ( addr_wr[9] == 1'b1 ) ? data_in : ram_array_q_9, data_reg_10 = ( addr_wr[10] == 1'b1 ) ? data_in : ram_array_q_10, data_reg_11 = ( addr_wr[11] == 1'b1 ) ? data_in : ram_array_q_11, data_reg_12 = ( addr_wr[12] == 1'b1 ) ? data_in : ram_array_q_12, data_reg_13 = ( addr_wr[13] == 1'b1 ) ? data_in : ram_array_q_13, data_reg_14 = ( addr_wr[14] == 1'b1 ) ? data_in : ram_array_q_14, data_reg_15 = ( addr_wr[15] == 1'b1 ) ? data_in : ram_array_q_15; assign #read_access_time data_out1 = re_l ? 14'b00000000000000 : data_out1_i; assign #read_access_time data_out2 = re_l ? 14'b00000000000000 : data_out2_i; always @( ram_array_q_0 or ram_array_q_1 or ram_array_q_2 or ram_array_q_3 or ram_array_q_4 or ram_array_q_5 or ram_array_q_6 or ram_array_q_7 or ram_array_q_8 or ram_array_q_9 or ram_array_q_10 or ram_array_q_11 or ram_array_q_12 or ram_array_q_13 or ram_array_q_14 or ram_array_q_15 or addr_rd1 or addr_rd2 ) begin case ( addr_rd1 ) // synopsys parallel_case full_case 16'b0000000000000001 : data_out1_i = ram_array_q_0; 16'b0000000000000010 : data_out1_i = ram_array_q_1; 16'b0000000000000100 : data_out1_i = ram_array_q_2; 16'b0000000000001000 : data_out1_i = ram_array_q_3; 16'b0000000000010000 : data_out1_i = ram_array_q_4; 16'b0000000000100000 : data_out1_i = ram_array_q_5; 16'b0000000001000000 : data_out1_i = ram_array_q_6; 16'b0000000010000000 : data_out1_i = ram_array_q_7; 16'b0000000100000000 : data_out1_i = ram_array_q_8; 16'b0000001000000000 : data_out1_i = ram_array_q_9; 16'b0000010000000000 : data_out1_i = ram_array_q_10; 16'b0000100000000000 : data_out1_i = ram_array_q_11; 16'b0001000000000000 : data_out1_i = ram_array_q_12; 16'b0010000000000000 : data_out1_i = ram_array_q_13; 16'b0100000000000000 : data_out1_i = ram_array_q_14; 16'b1000000000000000 : data_out1_i = ram_array_q_15; endcase case ( addr_rd2 ) // synopsys parallel_case full_case 16'b0000000000000001 : data_out2_i = ram_array_q_0; 16'b0000000000000010 : data_out2_i = ram_array_q_1; 16'b0000000000000100 : data_out2_i = ram_array_q_2; 16'b0000000000001000 : data_out2_i = ram_array_q_3; 16'b0000000000010000 : data_out2_i = ram_array_q_4; 16'b0000000000100000 : data_out2_i = ram_array_q_5; 16'b0000000001000000 : data_out2_i = ram_array_q_6; 16'b0000000010000000 : data_out2_i = ram_array_q_7; 16'b0000000100000000 : data_out2_i = ram_array_q_8; 16'b0000001000000000 : data_out2_i = ram_array_q_9; 16'b0000010000000000 : data_out2_i = ram_array_q_10; 16'b0000100000000000 : data_out2_i = ram_array_q_11; 16'b0001000000000000 : data_out2_i = ram_array_q_12; 16'b0010000000000000 : data_out2_i = ram_array_q_13; 16'b0100000000000000 : data_out2_i = ram_array_q_14; 16'b1000000000000000 : data_out2_i = ram_array_q_15; endcase end /* Modelling the write port */ always @(posedge clk or negedge rst_l) begin if(~rst_l) begin ram_array_q_0 <= #write_access_time 0; ram_array_q_1 <= #write_access_time 0; ram_array_q_2 <= #write_access_time 0; ram_array_q_3 <= #write_access_time 0; ram_array_q_4 <= #write_access_time 0; ram_array_q_5 <= #write_access_time 0; ram_array_q_6 <= #write_access_time 0; ram_array_q_7 <= #write_access_time 0; ram_array_q_8 <= #write_access_time 0; ram_array_q_9 <= #write_access_time 0; ram_array_q_10 <= #write_access_time 0; ram_array_q_11 <= #write_access_time 0; ram_array_q_12 <= #write_access_time 0; ram_array_q_13 <= #write_access_time 0; ram_array_q_14 <= #write_access_time 0; ram_array_q_15 <= #write_access_time 0; end else begin ram_array_q_0 <= #write_access_time ram_array_d_0; ram_array_q_1 <= #write_access_time ram_array_d_1; ram_array_q_2 <= #write_access_time ram_array_d_2; ram_array_q_3 <= #write_access_time ram_array_d_3; ram_array_q_4 <= #write_access_time ram_array_d_4; ram_array_q_5 <= #write_access_time ram_array_d_5; ram_array_q_6 <= #write_access_time ram_array_d_6; ram_array_q_7 <= #write_access_time ram_array_d_7; ram_array_q_8 <= #write_access_time ram_array_d_8; ram_array_q_9 <= #write_access_time ram_array_d_9; ram_array_q_10 <= #write_access_time ram_array_d_10; ram_array_q_11 <= #write_access_time ram_array_d_11; ram_array_q_12 <= #write_access_time ram_array_d_12; ram_array_q_13 <= #write_access_time ram_array_d_13; ram_array_q_14 <= #write_access_time ram_array_d_14; ram_array_q_15 <= #write_access_time ram_array_d_15; end end always @( we or data_reg_0 or data_reg_1 or data_reg_2 or data_reg_3 or data_reg_4 or data_reg_5 or data_reg_6 or data_reg_7 or data_reg_8 or data_reg_9 or data_reg_10 or data_reg_11 or data_reg_12 or data_reg_13 or data_reg_14 or data_reg_15 or ram_array_q_0 or ram_array_q_1 or ram_array_q_2 or ram_array_q_3 or ram_array_q_4 or ram_array_q_5 or ram_array_q_6 or ram_array_q_7 or ram_array_q_8 or ram_array_q_9 or ram_array_q_10 or ram_array_q_11 or ram_array_q_12 or ram_array_q_13 or ram_array_q_14 or ram_array_q_15 ) begin if(we) begin ram_array_d_0 <= #write_access_time data_reg_0; ram_array_d_1 <= #write_access_time data_reg_1; ram_array_d_2 <= #write_access_time data_reg_2; ram_array_d_3 <= #write_access_time data_reg_3; ram_array_d_4 <= #write_access_time data_reg_4; ram_array_d_5 <= #write_access_time data_reg_5; ram_array_d_6 <= #write_access_time data_reg_6; ram_array_d_7 <= #write_access_time data_reg_7; ram_array_d_8 <= #write_access_time data_reg_8; ram_array_d_9 <= #write_access_time data_reg_9; ram_array_d_10 <= #write_access_time data_reg_10; ram_array_d_11 <= #write_access_time data_reg_11; ram_array_d_12 <= #write_access_time data_reg_12; ram_array_d_13 <= #write_access_time data_reg_13; ram_array_d_14 <= #write_access_time data_reg_14; ram_array_d_15 <= #write_access_time data_reg_15; end else begin ram_array_d_0 <= #write_access_time ram_array_q_0; ram_array_d_1 <= #write_access_time ram_array_q_1; ram_array_d_2 <= #write_access_time ram_array_q_2; ram_array_d_3 <= #write_access_time ram_array_q_3; ram_array_d_4 <= #write_access_time ram_array_q_4; ram_array_d_5 <= #write_access_time ram_array_q_5; ram_array_d_6 <= #write_access_time ram_array_q_6; ram_array_d_7 <= #write_access_time ram_array_q_7; ram_array_d_8 <= #write_access_time ram_array_q_8; ram_array_d_9 <= #write_access_time ram_array_q_9; ram_array_d_10 <= #write_access_time ram_array_q_10; ram_array_d_11 <= #write_access_time ram_array_q_11; ram_array_d_12 <= #write_access_time ram_array_q_12; ram_array_d_13 <= #write_access_time ram_array_q_13; ram_array_d_14 <= #write_access_time ram_array_q_14; ram_array_d_15 <= #write_access_time ram_array_q_15; end end endmodule `timescale 1ps / 1ps module stratixiv_hssi_rx_digis_ram20x16_syn ( data_in, clk, fifo_wr, rst_l, fifo_re1, fifo_re2, data_out1, data_out2 ); input clk; input rst_l; input [19:0] fifo_wr; input [19:0] fifo_re1; input [19:0] fifo_re2; input [15:0] data_in; output [15:0] data_out1; output [15:0] data_out2; parameter read_access_time = 0; parameter write_access_time = 0; parameter ram_width = 16; reg [ram_width-1:0] data_out1_i, data_out2_i; reg [ram_width-1:0] ram_array_d_0, ram_array_d_1, ram_array_d_2, ram_array_d_3, ram_array_d_4, ram_array_d_5, ram_array_d_6, ram_array_d_7, ram_array_d_8, ram_array_d_9, ram_array_d_10, ram_array_d_11, ram_array_d_12, ram_array_d_13, ram_array_d_14, ram_array_d_15, ram_array_d_16, ram_array_d_17, ram_array_d_18, ram_array_d_19, ram_array_q_0, ram_array_q_1, ram_array_q_2, ram_array_q_3, ram_array_q_4, ram_array_q_5, ram_array_q_6, ram_array_q_7, ram_array_q_8, ram_array_q_9, ram_array_q_10, ram_array_q_11, ram_array_q_12, ram_array_q_13, ram_array_q_14, ram_array_q_15, ram_array_q_16, ram_array_q_17, ram_array_q_18, ram_array_q_19; wire [ram_width-1:0] data_reg_0, data_reg_1, data_reg_2, data_reg_3, data_reg_4, data_reg_5, data_reg_6, data_reg_7, data_reg_8, data_reg_9, data_reg_10, data_reg_11, data_reg_12, data_reg_13, data_reg_14, data_reg_15, data_reg_16, data_reg_17, data_reg_18, data_reg_19; wire we, re_l; assign we = 1'b1; assign re_l = 1'b0; /* Modelling the read port */ /* Assuming address trigerred operation only */ //assignment assign data_reg_0 = ( fifo_wr[0] == 1'b1 ) ? data_in : ram_array_q_0, data_reg_1 = ( fifo_wr[1] == 1'b1 ) ? data_in : ram_array_q_1, data_reg_2 = ( fifo_wr[2] == 1'b1 ) ? data_in : ram_array_q_2, data_reg_3 = ( fifo_wr[3] == 1'b1 ) ? data_in : ram_array_q_3, data_reg_4 = ( fifo_wr[4] == 1'b1 ) ? data_in : ram_array_q_4, data_reg_5 = ( fifo_wr[5] == 1'b1 ) ? data_in : ram_array_q_5, data_reg_6 = ( fifo_wr[6] == 1'b1 ) ? data_in : ram_array_q_6, data_reg_7 = ( fifo_wr[7] == 1'b1 ) ? data_in : ram_array_q_7, data_reg_8 = ( fifo_wr[8] == 1'b1 ) ? data_in : ram_array_q_8, data_reg_9 = ( fifo_wr[9] == 1'b1 ) ? data_in : ram_array_q_9, data_reg_10 = ( fifo_wr[10] == 1'b1 ) ? data_in : ram_array_q_10, data_reg_11 = ( fifo_wr[11] == 1'b1 ) ? data_in : ram_array_q_11, data_reg_12 = ( fifo_wr[12] == 1'b1 ) ? data_in : ram_array_q_12, data_reg_13 = ( fifo_wr[13] == 1'b1 ) ? data_in : ram_array_q_13, data_reg_14 = ( fifo_wr[14] == 1'b1 ) ? data_in : ram_array_q_14, data_reg_15 = ( fifo_wr[15] == 1'b1 ) ? data_in : ram_array_q_15, data_reg_16 = ( fifo_wr[16] == 1'b1 ) ? data_in : ram_array_q_16, data_reg_17 = ( fifo_wr[17] == 1'b1 ) ? data_in : ram_array_q_17, data_reg_18 = ( fifo_wr[18] == 1'b1 ) ? data_in : ram_array_q_18, data_reg_19 = ( fifo_wr[19] == 1'b1 ) ? data_in : ram_array_q_19; // 03/22/05 VC: LEDA fix: Remove delay on combinatorial statement // and changed 15'b0 to 16'd0 //assign #read_access_time data_out1 = re_l ? 15'b0 : data_out1_i; //assign #read_access_time data_out2 = re_l ? 15'b0 : data_out2_i; assign data_out1 = re_l ? 16'd0 : data_out1_i; assign data_out2 = re_l ? 16'd0 : data_out2_i; always @( ram_array_q_0 or ram_array_q_1 or ram_array_q_2 or ram_array_q_3 or ram_array_q_4 or ram_array_q_5 or ram_array_q_6 or ram_array_q_7 or ram_array_q_8 or ram_array_q_9 or ram_array_q_10 or ram_array_q_11 or ram_array_q_12 or ram_array_q_13 or ram_array_q_14 or ram_array_q_15 or ram_array_q_16 or ram_array_q_17 or ram_array_q_18 or ram_array_q_19 or fifo_re1 or fifo_re2 ) begin // 03/22/05 VC: Removed full case statement because // not all cases are listed // case ( fifo_re1 ) // synopsys parallel_case full_case case ( fifo_re1 ) // synopsys parallel_case 20'b00000000000000000001 : data_out1_i = ram_array_q_0; 20'b00000000000000000010 : data_out1_i = ram_array_q_1; 20'b00000000000000000100 : data_out1_i = ram_array_q_2; 20'b00000000000000001000 : data_out1_i = ram_array_q_3; 20'b00000000000000010000 : data_out1_i = ram_array_q_4; 20'b00000000000000100000 : data_out1_i = ram_array_q_5; 20'b00000000000001000000 : data_out1_i = ram_array_q_6; 20'b00000000000010000000 : data_out1_i = ram_array_q_7; 20'b00000000000100000000 : data_out1_i = ram_array_q_8; 20'b00000000001000000000 : data_out1_i = ram_array_q_9; 20'b00000000010000000000 : data_out1_i = ram_array_q_10; 20'b00000000100000000000 : data_out1_i = ram_array_q_11; 20'b00000001000000000000 : data_out1_i = ram_array_q_12; 20'b00000010000000000000 : data_out1_i = ram_array_q_13; 20'b00000100000000000000 : data_out1_i = ram_array_q_14; 20'b00001000000000000000 : data_out1_i = ram_array_q_15; 20'b00010000000000000000 : data_out1_i = ram_array_q_16; 20'b00100000000000000000 : data_out1_i = ram_array_q_17; 20'b01000000000000000000 : data_out1_i = ram_array_q_18; 20'b10000000000000000000 : data_out1_i = ram_array_q_19; // 03/22/05 VC: LEDA fix: Added default clause to case statement default : data_out1_i = ram_array_q_0; endcase // 03/22/05 VC: Removed full case statement because // not all cases are listed // case ( fifo_re2 ) // synopsys parallel_case full_case case ( fifo_re2 ) // synopsys parallel_case 20'b00000000000000000001 : data_out2_i = ram_array_q_0; 20'b00000000000000000010 : data_out2_i = ram_array_q_1; 20'b00000000000000000100 : data_out2_i = ram_array_q_2; 20'b00000000000000001000 : data_out2_i = ram_array_q_3; 20'b00000000000000010000 : data_out2_i = ram_array_q_4; 20'b00000000000000100000 : data_out2_i = ram_array_q_5; 20'b00000000000001000000 : data_out2_i = ram_array_q_6; 20'b00000000000010000000 : data_out2_i = ram_array_q_7; 20'b00000000000100000000 : data_out2_i = ram_array_q_8; 20'b00000000001000000000 : data_out2_i = ram_array_q_9; 20'b00000000010000000000 : data_out2_i = ram_array_q_10; 20'b00000000100000000000 : data_out2_i = ram_array_q_11; 20'b00000001000000000000 : data_out2_i = ram_array_q_12; 20'b00000010000000000000 : data_out2_i = ram_array_q_13; 20'b00000100000000000000 : data_out2_i = ram_array_q_14; 20'b00001000000000000000 : data_out2_i = ram_array_q_15; 20'b00010000000000000000 : data_out2_i = ram_array_q_16; 20'b00100000000000000000 : data_out2_i = ram_array_q_17; 20'b01000000000000000000 : data_out2_i = ram_array_q_18; 20'b10000000000000000000 : data_out2_i = ram_array_q_19; // 03/22/05 VC: LEDA fix: Added default clause to case statement default : data_out2_i = ram_array_q_0; endcase end // 03/22/05 VC: LEDA fix: Change 0 to 16'd0 /* Modelling the write port */ always @(posedge clk or negedge rst_l) begin if(~rst_l) begin ram_array_q_0 <= #write_access_time 16'd0; ram_array_q_1 <= #write_access_time 16'd0; ram_array_q_2 <= #write_access_time 16'd0; ram_array_q_3 <= #write_access_time 16'd0; ram_array_q_4 <= #write_access_time 16'd0; ram_array_q_5 <= #write_access_time 16'd0; ram_array_q_6 <= #write_access_time 16'd0; ram_array_q_7 <= #write_access_time 16'd0; ram_array_q_8 <= #write_access_time 16'd0; ram_array_q_9 <= #write_access_time 16'd0; ram_array_q_10 <= #write_access_time 16'd0; ram_array_q_11 <= #write_access_time 16'd0; ram_array_q_12 <= #write_access_time 16'd0; ram_array_q_13 <= #write_access_time 16'd0; ram_array_q_14 <= #write_access_time 16'd0; ram_array_q_15 <= #write_access_time 16'd0; ram_array_q_16 <= #write_access_time 16'd0; ram_array_q_17 <= #write_access_time 16'd0; ram_array_q_18 <= #write_access_time 16'd0; ram_array_q_19 <= #write_access_time 16'd0; end else begin ram_array_q_0 <= #write_access_time ram_array_d_0; ram_array_q_1 <= #write_access_time ram_array_d_1; ram_array_q_2 <= #write_access_time ram_array_d_2; ram_array_q_3 <= #write_access_time ram_array_d_3; ram_array_q_4 <= #write_access_time ram_array_d_4; ram_array_q_5 <= #write_access_time ram_array_d_5; ram_array_q_6 <= #write_access_time ram_array_d_6; ram_array_q_7 <= #write_access_time ram_array_d_7; ram_array_q_8 <= #write_access_time ram_array_d_8; ram_array_q_9 <= #write_access_time ram_array_d_9; ram_array_q_10 <= #write_access_time ram_array_d_10; ram_array_q_11 <= #write_access_time ram_array_d_11; ram_array_q_12 <= #write_access_time ram_array_d_12; ram_array_q_13 <= #write_access_time ram_array_d_13; ram_array_q_14 <= #write_access_time ram_array_d_14; ram_array_q_15 <= #write_access_time ram_array_d_15; ram_array_q_16 <= #write_access_time ram_array_d_16; ram_array_q_17 <= #write_access_time ram_array_d_17; ram_array_q_18 <= #write_access_time ram_array_d_18; ram_array_q_19 <= #write_access_time ram_array_d_19; end end always @( we or data_reg_0 or data_reg_1 or data_reg_2 or data_reg_3 or data_reg_4 or data_reg_5 or data_reg_6 or data_reg_7 or data_reg_8 or data_reg_9 or data_reg_10 or data_reg_11 or data_reg_12 or data_reg_13 or data_reg_14 or data_reg_15 or data_reg_16 or data_reg_17 or data_reg_18 or data_reg_19 or ram_array_q_0 or ram_array_q_1 or ram_array_q_2 or ram_array_q_3 or ram_array_q_4 or ram_array_q_5 or ram_array_q_6 or ram_array_q_7 or ram_array_q_8 or ram_array_q_9 or ram_array_q_10 or ram_array_q_11 or ram_array_q_12 or ram_array_q_13 or ram_array_q_14 or ram_array_q_15 or ram_array_q_16 or ram_array_q_17 or ram_array_q_18 or ram_array_q_19 ) begin if(we) begin ram_array_d_0 = data_reg_0; ram_array_d_1 = data_reg_1; ram_array_d_2 = data_reg_2; ram_array_d_3 = data_reg_3; ram_array_d_4 = data_reg_4; ram_array_d_5 = data_reg_5; ram_array_d_6 = data_reg_6; ram_array_d_7 = data_reg_7; ram_array_d_8 = data_reg_8; ram_array_d_9 = data_reg_9; ram_array_d_10 = data_reg_10; ram_array_d_11 = data_reg_11; ram_array_d_12 = data_reg_12; ram_array_d_13 = data_reg_13; ram_array_d_14 = data_reg_14; ram_array_d_15 = data_reg_15; ram_array_d_16 = data_reg_16; ram_array_d_17 = data_reg_17; ram_array_d_18 = data_reg_18; ram_array_d_19 = data_reg_19; end else begin ram_array_d_0 = ram_array_q_0; ram_array_d_1 = ram_array_q_1; ram_array_d_2 = ram_array_q_2; ram_array_d_3 = ram_array_q_3; ram_array_d_4 = ram_array_q_4; ram_array_d_5 = ram_array_q_5; ram_array_d_6 = ram_array_q_6; ram_array_d_7 = ram_array_q_7; ram_array_d_8 = ram_array_q_8; ram_array_d_9 = ram_array_q_9; ram_array_d_10 = ram_array_q_10; ram_array_d_11 = ram_array_q_11; ram_array_d_12 = ram_array_q_12; ram_array_d_13 = ram_array_q_13; ram_array_d_14 = ram_array_q_14; ram_array_d_15 = ram_array_q_15; ram_array_d_16 = ram_array_q_16; ram_array_d_17 = ram_array_q_17; ram_array_d_18 = ram_array_q_18; ram_array_d_19 = ram_array_q_19; end end endmodule `timescale 1 ps / 1 ps module stratixiv_hssi_rx_digis_ram8x70_syn ( rst_l, clk, fifo_wr, data_in, fifo_re, data_out ); input rst_l; input clk; input [7:0] fifo_wr; input [69:0] data_in; input [7:0] fifo_re; output [69:0] data_out; parameter read_access_time = 0; parameter write_access_time = 0; parameter ram_width = 70; reg [ram_width-1:0] data_out_i; reg [ram_width-1:0] ram_array_d_0, ram_array_d_1, ram_array_d_2, ram_array_d_3, ram_array_d_4, ram_array_d_5, ram_array_d_6, ram_array_d_7, ram_array_q_0, ram_array_q_1, ram_array_q_2, ram_array_q_3, ram_array_q_4, ram_array_q_5, ram_array_q_6, ram_array_q_7; wire [ram_width-1:0] data_reg_0, data_reg_1, data_reg_2, data_reg_3, data_reg_4, data_reg_5, data_reg_6, data_reg_7; wire we, re_l; assign we = 1'b1; assign re_l = 1'b0; /* Modelling the read port */ /* Assuming address trigerred operation only */ //assignment assign data_reg_0 = ( fifo_wr[0] == 1'b1 ) ? data_in : ram_array_q_0, data_reg_1 = ( fifo_wr[1] == 1'b1 ) ? data_in : ram_array_q_1, data_reg_2 = ( fifo_wr[2] == 1'b1 ) ? data_in : ram_array_q_2, data_reg_3 = ( fifo_wr[3] == 1'b1 ) ? data_in : ram_array_q_3, data_reg_4 = ( fifo_wr[4] == 1'b1 ) ? data_in : ram_array_q_4, data_reg_5 = ( fifo_wr[5] == 1'b1 ) ? data_in : ram_array_q_5, data_reg_6 = ( fifo_wr[6] == 1'b1 ) ? data_in : ram_array_q_6, data_reg_7 = ( fifo_wr[7] == 1'b1 ) ? data_in : ram_array_q_7; assign data_out = re_l ? 70'b0 : data_out_i; always @( ram_array_q_0 or ram_array_q_1 or ram_array_q_2 or ram_array_q_3 or ram_array_q_4 or ram_array_q_5 or ram_array_q_6 or ram_array_q_7 or fifo_re ) begin case ( fifo_re ) // synopsys parallel_case full_case 8'b00000001 : data_out_i = ram_array_q_0; 8'b00000010 : data_out_i = ram_array_q_1; 8'b00000100 : data_out_i = ram_array_q_2; 8'b00001000 : data_out_i = ram_array_q_3; 8'b00010000 : data_out_i = ram_array_q_4; 8'b00100000 : data_out_i = ram_array_q_5; 8'b01000000 : data_out_i = ram_array_q_6; 8'b10000000 : data_out_i = ram_array_q_7; default : data_out_i = ram_array_q_0; endcase end /* Modelling the write port */ always @(posedge clk or negedge rst_l) begin if(~rst_l) begin ram_array_q_0 <= #write_access_time 70'h020000000000000000; ram_array_q_1 <= #write_access_time 70'h020000000000000000; ram_array_q_2 <= #write_access_time 70'h020000000000000000; ram_array_q_3 <= #write_access_time 70'h020000000000000000; ram_array_q_4 <= #write_access_time 70'h020000000000000000; ram_array_q_5 <= #write_access_time 70'h020000000000000000; ram_array_q_6 <= #write_access_time 70'h020000000000000000; ram_array_q_7 <= #write_access_time 70'h020000000000000000; end else begin ram_array_q_0 <= #write_access_time ram_array_d_0; ram_array_q_1 <= #write_access_time ram_array_d_1; ram_array_q_2 <= #write_access_time ram_array_d_2; ram_array_q_3 <= #write_access_time ram_array_d_3; ram_array_q_4 <= #write_access_time ram_array_d_4; ram_array_q_5 <= #write_access_time ram_array_d_5; ram_array_q_6 <= #write_access_time ram_array_d_6; ram_array_q_7 <= #write_access_time ram_array_d_7; end end always @( we or data_reg_0 or data_reg_1 or data_reg_2 or data_reg_3 or data_reg_4 or data_reg_5 or data_reg_6 or data_reg_7 or ram_array_q_0 or ram_array_q_1 or ram_array_q_2 or ram_array_q_3 or ram_array_q_4 or ram_array_q_5 or ram_array_q_6 or ram_array_q_7 ) begin if(we) begin ram_array_d_0 = data_reg_0; ram_array_d_1 = data_reg_1; ram_array_d_2 = data_reg_2; ram_array_d_3 = data_reg_3; ram_array_d_4 = data_reg_4; ram_array_d_5 = data_reg_5; ram_array_d_6 = data_reg_6; ram_array_d_7 = data_reg_7; end else begin ram_array_d_0 = ram_array_q_0; ram_array_d_1 = ram_array_q_1; ram_array_d_2 = ram_array_q_2; ram_array_d_3 = ram_array_q_3; ram_array_d_4 = ram_array_q_4; ram_array_d_5 = ram_array_q_5; ram_array_d_6 = ram_array_q_6; ram_array_d_7 = ram_array_q_7; end end endmodule `timescale 1 ps / 1 ps module stratixiv_hssi_rx_digis_rxclk_gating ( select_n, clk1, clk2, clk1out_n, clk2out_n ); input select_n; input clk1; input clk2; output clk1out_n; output clk2out_n; assign clk1out_n = ~(select_n | clk1); assign clk2out_n = ~(~select_n | clk2); endmodule // rxclk_gating `timescale 1 ns /1 ps module stratixiv_hssi_rx_digi_rxclk_ctl (pld_rx_clk, rcvd_clk_pma, rcvd_clk0_pma, tx_pma_clk, refclk_pma, fref, clklow, scan_mode, gen2ngen1, gen2ngen1_bundle, rx_div2_sync_centrl, rx_div2_sync_quad_up, rx_div2_sync_quad_down, rrcvd_clk_sel, rclk_1_sel, rclk_2_sel, rrx_rd_clk_sel, rxrst, rindv_rx, rdwidth_rx, rfreerun_rx, rauto_speed_ena, rfreq_sel, rrxpcsclkpwdn, rmaster_rx, rmaster_up_rx, rself_sw_en_rx, fref_muxed, clklow_muxed, rcvd_clk, clk_1_b, clk_2_b, rx_wr_clk, rx_rd_clk, rx_clk, rcvd_clk_pma_b, clk_2_b_raw, rx_wr_clk_raw, rx_rd_clk_raw, rx_div2_sync_out ); // Clock Inputs input pld_rx_clk; // PLD clock from PLD clock trees input rcvd_clk_pma; // local recovered clock input rcvd_clk0_pma; // channel zero recovered clock input tx_pma_clk; // local TX PMA clock input refclk_pma; // Quad based clk from TXPLL input fref; input clklow; // Control Inputs input scan_mode; // Scan mode enable signal input rxrst; // This is the soft_reset for the RX_PCS // New Control Inputs input gen2ngen1; // from PMA for PCIexp Gen1/Gen2 datawidth scaling input gen2ngen1_bundle; // from PMA for PCIexp Gen1/Gen2 datawidth scaling in x4 and x8 input rx_div2_sync_centrl; // divided clock from the central channel (x2, x4 mode) input rx_div2_sync_quad_up; // divided clock from quad above (> x4 mode) input rx_div2_sync_quad_down; // divided clock from quad below (> x4 mode) // MDIO Inputs input [1:0] rrcvd_clk_sel; input [1:0] rclk_1_sel; input [1:0] rclk_2_sel; input rrx_rd_clk_sel; // Select clock for rx ph comp fifo read side input rindv_rx; // Select between XAUI mode or indiv channel mode input rdwidth_rx; // divide by 1 or 2 before feeding to FIFO write clock input rfreerun_rx; // Select whether divider is permamently enabled (free -running) or divider should be enabled / reset by RX PCS reset // New MDIO Inputs input rauto_speed_ena; // auto speed negotiation enable input rfreq_sel; // freq scaling or data width scaling input rrxpcsclkpwdn; // RX clocking power down enable input rmaster_rx; // New bundle mode MDIO, selects master quad input rmaster_up_rx; // New bundle mode MDIO, selects master quad input rself_sw_en_rx; // enables self-switch to have correct /2 clock in all quads in bundle mode // Removed Inputs // input rphfifo_master_sel_rx; // RX Phase comp. FIFO rx_div2_sync selection CRAM // input rx_div2_sync_in_ch0; // Connect from channel zero rx_div2_sync_out // input rx_div2_sync_in_q0_ch0; // Connect from channel zero rx_div2_sync_out of Master Quad // Clock Outputs with CTS output fref_muxed; output clklow_muxed; output rcvd_clk; output clk_1_b; output clk_2_b; output rx_wr_clk; // drives the rx ph comp fifo write clock tree output rx_rd_clk; // drives the rx ph comp fifo read clock tree // Clock Outputs to PLD, no CTS output rx_clk; // drives the PLD clock tree in x1 mode, logically same as rx_wr_clk output rcvd_clk_pma_b; // debug output clock to PLD // New Clock Outputs with CTS output clk_2_b_raw; // same as clk_2_b, but with no clock gating output rx_wr_clk_raw; // same as rx_wr_clk, but with no clock gating output rx_rd_clk_raw; // same as rx_rd_clk, but with no clock gating // Control Outputs output rx_div2_sync_out; // inverted /2 clock. not used w/new bundling scheme. (left for safety) reg rx_clk_2_by2; reg gen2ngen1_local_sync; reg [1:0] counter; wire rx_div2_sync; wire rx_div2_sync_out; wire rx_rst_n; wire [1:0] rrcvd_clk_sel_int; wire [1:0] rclk_1_sel_int; wire [1:0] rclk_2_sel_int; wire dynamic_div2ndiv1; wire gen2ngen1_local; wire fref_muxed; wire clklow_muxed; wire rrxpcsclkpwdn_nscan; wire rx_div2_this_quad; wire rx_div2_this_channel; wire rx_div2_other_quad; wire force_master; wire select_div1_n; wire clk1out_n; wire clk2out_n; // shawn initial begin ------ initial begin rx_clk_2_by2 = 1'b1; end // shawn initial end ------ // Old bundle logic: // Select between the local synchronization signal or the global synchronization signal //assign rx_div2_sync = rindv_rx ? rx_div2_sync_out : rx_div2_sync_in; // assign rx_div2_sync = (rphfifo_master_sel_rx == 1'b0) ? rx_div2_sync_in_q0_ch0 : // (rindv_rx == 1'b0) ? rx_div2_sync_in_ch0 : // (rauto_speed_ena & ~rfreq_sel) ? (rx_div2_sync_out | ~gen2ngen1_local_sync) : rx_div2_sync_out; always @(posedge rxrst or posedge clk_2_b_raw) begin if (rxrst) counter <= #1 2'b00; else if ((rauto_speed_ena & ~rfreq_sel & rself_sw_en_rx) & ~force_master) counter <= #1 counter + 1'b1; end assign force_master = ((counter == 2'b11) & (rauto_speed_ena & ~rfreq_sel & rself_sw_en_rx)) ? 1'b1 : 1'b0; assign rx_div2_sync = (rmaster_rx | force_master) ? rx_div2_this_quad : rx_div2_other_quad; assign rx_div2_this_quad = (rindv_rx | force_master) ? rx_div2_this_channel : rx_div2_sync_centrl; assign rx_div2_this_channel = (rauto_speed_ena & ~rfreq_sel) ? (rx_div2_sync_out | ~gen2ngen1_local_sync) : rx_div2_sync_out; assign rx_div2_other_quad = rmaster_up_rx ? rx_div2_sync_quad_up : rx_div2_sync_quad_down; assign gen2ngen1_local = (rindv_rx == 1'b0) ? gen2ngen1_bundle : gen2ngen1; always @(posedge rxrst or posedge clk_2_b_raw) begin if (rxrst) gen2ngen1_local_sync <= #1 1'b0; else gen2ngen1_local_sync <= #1 gen2ngen1_local; end assign dynamic_div2ndiv1 = rdwidth_rx | (gen2ngen1_local_sync & rauto_speed_ena & ~rfreq_sel); // Reset for Divide-by-2 FF and synchronization FF's for clock gating assign rx_rst_n = (rfreerun_rx) ? 1'b1 : ~rxrst; assign rrxpcsclkpwdn_nscan = rrxpcsclkpwdn & ~scan_mode; // clocks are assigned below in the order in which they appear in the out flowing data path // RCVD_CLK selection assign rrcvd_clk_sel_int = (scan_mode) ? 2'b01 : rrcvd_clk_sel; assign rcvd_clk = rrxpcsclkpwdn_nscan ? 1'b1 : (rrcvd_clk_sel_int == 2'b00) ? rcvd_clk_pma : (rrcvd_clk_sel_int == 2'b01) ? refclk_pma : (rrcvd_clk_sel_int == 2'b10) ? tx_pma_clk : (rrcvd_clk_sel_int == 2'b11) ? rcvd_clk_pma : rcvd_clk_pma; // CLK_1 seleciton assign rclk_1_sel_int = (scan_mode) ? 2'b01 : rclk_1_sel; assign clk_1_b = rrxpcsclkpwdn_nscan ? 1'b1 : (rclk_1_sel_int == 2'b00) ? rcvd_clk_pma : (rclk_1_sel_int == 2'b01) ? refclk_pma : (rclk_1_sel_int == 2'b10) ? tx_pma_clk : (rclk_1_sel_int == 2'b11) ? rcvd_clk0_pma : rcvd_clk_pma; // CLK_2 selection assign rclk_2_sel_int = (scan_mode) ? 2'b10 : rclk_2_sel; assign clk_2_b_raw = (rclk_2_sel_int == 2'b00) ? rcvd_clk_pma : (rclk_2_sel_int == 2'b01) ? tx_pma_clk : (rclk_2_sel_int == 2'b10) ? refclk_pma : rcvd_clk_pma; //change made for S3GX to remove pld_rx_clk from mux input //(rclk_2_sel_int == 2'b10) ? refclk_pma : //(rclk_2_sel_int == 2'b11) ? pld_rx_clk : rcvd_clk_pma; assign clk_2_b = rrxpcsclkpwdn_nscan ? 1'b1 : clk_2_b_raw; // This register is used to generate divided by two clock. Div by 2 clock starts off high after reset // No #1 on this FF as it generates a clock always @(negedge rx_rst_n or posedge clk_2_b_raw) begin if (~rx_rst_n) rx_clk_2_by2 <= 1'b1; else rx_clk_2_by2 <= rx_div2_sync; end assign rx_div2_sync_out = ~rx_clk_2_by2; // RX FIFO write clock: could be fast or divided by 2 // old code: // assign rx_wr_clk = ((rdwidth_rx == 1'b0) || scan_mode) ? clk_2_b_raw : rx_clk_2_by2; assign select_div1_n = ~(scan_mode | ~dynamic_div2ndiv1); stratixiv_hssi_rx_digis_rxclk_gating rxclk_gating ( .select_n(select_div1_n), .clk1(clk_2_b_raw), .clk2(rx_clk_2_by2), .clk1out_n(clk1out_n), .clk2out_n(clk2out_n) ); assign rx_wr_clk_raw = ~(clk1out_n | clk2out_n); assign rx_wr_clk = rrxpcsclkpwdn_nscan ? 1'b1 : rx_wr_clk_raw; // RX FIFO read clock assign rx_rd_clk_raw = (scan_mode | (rrx_rd_clk_sel == 1'b0)) ? rx_wr_clk_raw : pld_rx_clk; assign rx_rd_clk = rrxpcsclkpwdn_nscan ? 1'b1 : rx_rd_clk_raw; // RX clock out assign rx_clk = rx_wr_clk; // drives PLD clock tree // Recovered clock for debugging assign rcvd_clk_pma_b = rcvd_clk_pma; // Goes out to PLD as debug clock. This clock may or may not be routed out to PLD fabric. TBD assign fref_muxed = scan_mode ? refclk_pma : rrxpcsclkpwdn ? 1'b1 : fref; assign clklow_muxed = scan_mode ? refclk_pma : rrxpcsclkpwdn ? 1'b1 : clklow; endmodule // rxclk_ctl //IP Functional Simulation Model //VERSION_BEGIN 12.0 cbx_mgl 2012:05:31:20:09:47:SJ cbx_simgen 2012:05:31:20:08:35:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 // Copyright (C) 1991-2012 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // You may only use these simulation model output files for simulation // purposes and expressly not for synthesis or any other purposes (in which // event Altera disclaims all warranties of any kind). //synopsys translate_off //synthesis_resources = lut 74 mux21 44 oper_add 1 oper_decoder 1 oper_mux 4 `timescale 1 ps / 1 ps module stratixiv_hssi_rx_digi_auto_speed_neg ( config_sel, config_sel_centrl, config_sel_quad_down, config_sel_quad_up, cs, dis_pc_byte, gen2ngen1, pcie_switch, rate, rauto_deassert_pc_rst_cnt, rauto_pc_en_cnt, rauto_speed_ena, refclk, reset_pc_ptrs, rindv_rx, rmaster_rx, rmaster_up_rx, rphfifo_regmode_rx, rpma_done_count, rwait_for_phfifo_cnt, rxpcs_rst_int, singleorbundle, speed_change) /* synthesis synthesis_clearbox=1 */; output config_sel; input config_sel_centrl; input config_sel_quad_down; input config_sel_quad_up; output [3:0] cs; output dis_pc_byte; input gen2ngen1; output pcie_switch; input rate; input [3:0] rauto_deassert_pc_rst_cnt; input [4:0] rauto_pc_en_cnt; input rauto_speed_ena; input refclk; output reset_pc_ptrs; input rindv_rx; input rmaster_rx; input rmaster_up_rx; input rphfifo_regmode_rx; input [17:0] rpma_done_count; input [5:0] rwait_for_phfifo_cnt; input rxpcs_rst_int; input singleorbundle; output speed_change; reg n000l43; reg n000l44; reg n00ii41; reg n00ii42; reg n00il39; reg n00il40; reg n00ll37; reg n00ll38; reg n00Ol35; reg n00Ol36; reg n0i0i31; reg n0i0i32; reg n0i0O29; reg n0i0O30; reg n0i1i33; reg n0i1i34; reg n0iil27; reg n0iil28; reg n0ili25; reg n0ili26; reg n0ilO23; reg n0ilO24; reg n0iOl21; reg n0iOl22; reg n0l0i17; reg n0l0i18; reg n0l0O15; reg n0l0O16; reg n0l1i19; reg n0l1i20; reg n0lli13; reg n0lli14; reg n0lOO11; reg n0lOO12; reg n0O0i3; reg n0O0i4; reg n0O0l1; reg n0O0l2; reg n0O1i10; reg n0O1i9; reg n0O1l7; reg n0O1l8; reg n0O1O5; reg n0O1O6; reg n11l; reg n11i_clk_prev; wire wire_n11i_PRN; wire wire_n11i_ENA; reg n00i; reg n00l; reg n00O; reg n01i; reg n01l; reg n01O; reg n0ii; reg n0il; reg n0iO; reg n0li; reg n0ll; reg n0lO; reg n0Oi; reg n0Ol; reg n0OO; reg n10i; reg n10l; reg n11O; reg n1il; reg n1iO; reg n1li; reg n1Ol; reg n1OO; reg ni1i; reg ni1O; reg nll0i; reg nlOOi; reg nlOOl; reg nlOOO; wire wire_ni1l_CLRN; wire wire_n1ll_dataout; wire wire_n1lO_dataout; wire wire_n1Oi_dataout; wire wire_ni0i_dataout; wire wire_ni0l_dataout; wire wire_ni0O_dataout; wire wire_niii_dataout; wire wire_niil_dataout; wire wire_niiO_dataout; wire wire_nili_dataout; wire wire_nill_dataout; wire wire_nilO_dataout; wire wire_niOi_dataout; wire wire_niOl_dataout; wire wire_niOO_dataout; wire wire_nl0i_dataout; wire wire_nl0l_dataout; wire wire_nl0O_dataout; wire wire_nl1i_dataout; wire wire_nl1l_dataout; wire wire_nl1O_dataout; wire wire_nlii_dataout; wire wire_nlil_dataout; wire wire_nliO_dataout; wire wire_nlli_dataout; wire wire_nlll_dataout; wire wire_nllli_dataout; wire wire_nllll_dataout; wire wire_nlllO_dataout; wire wire_nllO_dataout; wire wire_nllOi_dataout; wire wire_nllOl_dataout; wire wire_nllOO_dataout; wire wire_nlO0i_dataout; wire wire_nlO0l_dataout; wire wire_nlO0O_dataout; wire wire_nlO1i_dataout; wire wire_nlO1l_dataout; wire wire_nlO1O_dataout; wire wire_nlOi_dataout; wire wire_nlOii_dataout; wire wire_nlOil_dataout; wire wire_nlOiO_dataout; wire wire_nlOli_dataout; wire [18:0] wire_nO_o; wire [15:0] wire_nllii_o; wire wire_nliOO_o; wire wire_nll1i_o; wire wire_nll1l_o; wire wire_nll1O_o; wire n000i; wire n001l; wire n001O; wire n00li; wire n00lO; wire n00Oi; wire n0i1O; wire n0l1O; wire n0lil; wire n0liO; wire n0llO; initial n000l43 = 0; always @ ( posedge refclk) n000l43 <= n000l44; event n000l43_event; initial #1 ->n000l43_event; always @(n000l43_event) n000l43 <= {1{1'b1}}; initial n000l44 = 0; always @ ( posedge refclk) n000l44 <= n000l43; initial n00ii41 = 0; always @ ( posedge refclk) n00ii41 <= n00ii42; event n00ii41_event; initial #1 ->n00ii41_event; always @(n00ii41_event) n00ii41 <= {1{1'b1}}; initial n00ii42 = 0; always @ ( posedge refclk) n00ii42 <= n00ii41; initial n00il39 = 0; always @ ( posedge refclk) n00il39 <= n00il40; event n00il39_event; initial #1 ->n00il39_event; always @(n00il39_event) n00il39 <= {1{1'b1}}; initial n00il40 = 0; always @ ( posedge refclk) n00il40 <= n00il39; initial n00ll37 = 0; always @ ( posedge refclk) n00ll37 <= n00ll38; event n00ll37_event; initial #1 ->n00ll37_event; always @(n00ll37_event) n00ll37 <= {1{1'b1}}; initial n00ll38 = 0; always @ ( posedge refclk) n00ll38 <= n00ll37; initial n00Ol35 = 0; always @ ( posedge refclk) n00Ol35 <= n00Ol36; event n00Ol35_event; initial #1 ->n00Ol35_event; always @(n00Ol35_event) n00Ol35 <= {1{1'b1}}; initial n00Ol36 = 0; always @ ( posedge refclk) n00Ol36 <= n00Ol35; initial n0i0i31 = 0; always @ ( posedge refclk) n0i0i31 <= n0i0i32; event n0i0i31_event; initial #1 ->n0i0i31_event; always @(n0i0i31_event) n0i0i31 <= {1{1'b1}}; initial n0i0i32 = 0; always @ ( posedge refclk) n0i0i32 <= n0i0i31; initial n0i0O29 = 0; always @ ( posedge refclk) n0i0O29 <= n0i0O30; event n0i0O29_event; initial #1 ->n0i0O29_event; always @(n0i0O29_event) n0i0O29 <= {1{1'b1}}; initial n0i0O30 = 0; always @ ( posedge refclk) n0i0O30 <= n0i0O29; initial n0i1i33 = 0; always @ ( posedge refclk) n0i1i33 <= n0i1i34; event n0i1i33_event; initial #1 ->n0i1i33_event; always @(n0i1i33_event) n0i1i33 <= {1{1'b1}}; initial n0i1i34 = 0; always @ ( posedge refclk) n0i1i34 <= n0i1i33; initial n0iil27 = 0; always @ ( posedge refclk) n0iil27 <= n0iil28; event n0iil27_event; initial #1 ->n0iil27_event; always @(n0iil27_event) n0iil27 <= {1{1'b1}}; initial n0iil28 = 0; always @ ( posedge refclk) n0iil28 <= n0iil27; initial n0ili25 = 0; always @ ( posedge refclk) n0ili25 <= n0ili26; event n0ili25_event; initial #1 ->n0ili25_event; always @(n0ili25_event) n0ili25 <= {1{1'b1}}; initial n0ili26 = 0; always @ ( posedge refclk) n0ili26 <= n0ili25; initial n0ilO23 = 0; always @ ( posedge refclk) n0ilO23 <= n0ilO24; event n0ilO23_event; initial #1 ->n0ilO23_event; always @(n0ilO23_event) n0ilO23 <= {1{1'b1}}; initial n0ilO24 = 0; always @ ( posedge refclk) n0ilO24 <= n0ilO23; initial n0iOl21 = 0; always @ ( posedge refclk) n0iOl21 <= n0iOl22; event n0iOl21_event; initial #1 ->n0iOl21_event; always @(n0iOl21_event) n0iOl21 <= {1{1'b1}}; initial n0iOl22 = 0; always @ ( posedge refclk) n0iOl22 <= n0iOl21; initial n0l0i17 = 0; always @ ( posedge refclk) n0l0i17 <= n0l0i18; event n0l0i17_event; initial #1 ->n0l0i17_event; always @(n0l0i17_event) n0l0i17 <= {1{1'b1}}; initial n0l0i18 = 0; always @ ( posedge refclk) n0l0i18 <= n0l0i17; initial n0l0O15 = 0; always @ ( posedge refclk) n0l0O15 <= n0l0O16; event n0l0O15_event; initial #1 ->n0l0O15_event; always @(n0l0O15_event) n0l0O15 <= {1{1'b1}}; initial n0l0O16 = 0; always @ ( posedge refclk) n0l0O16 <= n0l0O15; initial n0l1i19 = 0; always @ ( posedge refclk) n0l1i19 <= n0l1i20; event n0l1i19_event; initial #1 ->n0l1i19_event; always @(n0l1i19_event) n0l1i19 <= {1{1'b1}}; initial n0l1i20 = 0; always @ ( posedge refclk) n0l1i20 <= n0l1i19; initial n0lli13 = 0; always @ ( posedge refclk) n0lli13 <= n0lli14; event n0lli13_event; initial #1 ->n0lli13_event; always @(n0lli13_event) n0lli13 <= {1{1'b1}}; initial n0lli14 = 0; always @ ( posedge refclk) n0lli14 <= n0lli13; initial n0lOO11 = 0; always @ ( posedge refclk) n0lOO11 <= n0lOO12; event n0lOO11_event; initial #1 ->n0lOO11_event; always @(n0lOO11_event) n0lOO11 <= {1{1'b1}}; initial n0lOO12 = 0; always @ ( posedge refclk) n0lOO12 <= n0lOO11; initial n0O0i3 = 0; always @ ( posedge refclk) n0O0i3 <= n0O0i4; event n0O0i3_event; initial #1 ->n0O0i3_event; always @(n0O0i3_event) n0O0i3 <= {1{1'b1}}; initial n0O0i4 = 0; always @ ( posedge refclk) n0O0i4 <= n0O0i3; initial n0O0l1 = 0; always @ ( posedge refclk) n0O0l1 <= n0O0l2; event n0O0l1_event; initial #1 ->n0O0l1_event; always @(n0O0l1_event) n0O0l1 <= {1{1'b1}}; initial n0O0l2 = 0; always @ ( posedge refclk) n0O0l2 <= n0O0l1; initial n0O1i10 = 0; always @ ( posedge refclk) n0O1i10 <= n0O1i9; initial n0O1i9 = 0; always @ ( posedge refclk) n0O1i9 <= n0O1i10; event n0O1i9_event; initial #1 ->n0O1i9_event; always @(n0O1i9_event) n0O1i9 <= {1{1'b1}}; initial n0O1l7 = 0; always @ ( posedge refclk) n0O1l7 <= n0O1l8; event n0O1l7_event; initial #1 ->n0O1l7_event; always @(n0O1l7_event) n0O1l7 <= {1{1'b1}}; initial n0O1l8 = 0; always @ ( posedge refclk) n0O1l8 <= n0O1l7; initial n0O1O5 = 0; always @ ( posedge refclk) n0O1O5 <= n0O1O6; event n0O1O5_event; initial #1 ->n0O1O5_event; always @(n0O1O5_event) n0O1O5 <= {1{1'b1}}; initial n0O1O6 = 0; always @ ( posedge refclk) n0O1O6 <= n0O1O5; initial begin n11l = 0; end always @ (refclk or wire_n11i_PRN or rxpcs_rst_int) begin if (wire_n11i_PRN == 1'b0) begin n11l <= 1; end else if (rxpcs_rst_int == 1'b1) begin n11l <= 0; end else if (wire_n11i_ENA == 1'b1) if (refclk != n11i_clk_prev && refclk == 1'b1) begin n11l <= n1il; end n11i_clk_prev <= refclk; end assign wire_n11i_ENA = wire_nllii_o[3], wire_n11i_PRN = (n00ii42 ^ n00ii41); initial begin n00i = 0; n00l = 0; n00O = 0; n01i = 0; n01l = 0; n01O = 0; n0ii = 0; n0il = 0; n0iO = 0; n0li = 0; n0ll = 0; n0lO = 0; n0Oi = 0; n0Ol = 0; n0OO = 0; n10i = 0; n10l = 0; n11O = 0; n1il = 0; n1iO = 0; n1li = 0; n1Ol = 0; n1OO = 0; ni1i = 0; ni1O = 0; nll0i = 0; nlOOi = 0; nlOOl = 0; nlOOO = 0; end always @ ( posedge refclk or negedge wire_ni1l_CLRN) begin if (wire_ni1l_CLRN == 1'b0) begin n00i <= 0; n00l <= 0; n00O <= 0; n01i <= 0; n01l <= 0; n01O <= 0; n0ii <= 0; n0il <= 0; n0iO <= 0; n0li <= 0; n0ll <= 0; n0lO <= 0; n0Oi <= 0; n0Ol <= 0; n0OO <= 0; n10i <= 0; n10l <= 0; n11O <= 0; n1il <= 0; n1iO <= 0; n1li <= 0; n1Ol <= 0; n1OO <= 0; ni1i <= 0; ni1O <= 0; nll0i <= 0; nlOOi <= 0; nlOOl <= 0; nlOOO <= 0; end else begin n00i <= wire_nili_dataout; n00l <= wire_nill_dataout; n00O <= wire_nilO_dataout; n01i <= wire_niii_dataout; n01l <= wire_niil_dataout; n01O <= wire_niiO_dataout; n0ii <= wire_niOi_dataout; n0il <= wire_niOl_dataout; n0iO <= wire_niOO_dataout; n0li <= wire_nl1i_dataout; n0ll <= wire_nl1l_dataout; n0lO <= wire_nl1O_dataout; n0Oi <= wire_nl0i_dataout; n0Ol <= wire_nl0l_dataout; n0OO <= wire_nl0O_dataout; n10i <= gen2ngen1; n10l <= n1il; n11O <= ((n10i ^ gen2ngen1) ^ (~ (n00il40 ^ n00il39))); n1il <= n1iO; n1iO <= rate; n1li <= wire_ni0i_dataout; n1Ol <= wire_ni0l_dataout; n1OO <= wire_ni0O_dataout; ni1i <= wire_nlii_dataout; ni1O <= wire_nlil_dataout; nll0i <= wire_nliOO_o; nlOOi <= wire_nll1i_o; nlOOl <= wire_nll1l_o; nlOOO <= wire_nll1O_o; end end assign wire_ni1l_CLRN = ((n00ll38 ^ n00ll37) & (~ rxpcs_rst_int)); assign wire_n1ll_dataout = (rmaster_rx === 1'b1) ? wire_n1Oi_dataout : wire_n1lO_dataout; assign wire_n1lO_dataout = (rmaster_up_rx === 1'b1) ? config_sel_quad_up : config_sel_quad_down; assign wire_n1Oi_dataout = (rindv_rx === 1'b1) ? n11l : config_sel_centrl; and(wire_ni0i_dataout, wire_nliO_dataout, ~((~ n00lO))); and(wire_ni0l_dataout, wire_nO_o[0], ~((~ n00lO))); and(wire_ni0O_dataout, wire_nO_o[1], ~((~ n00lO))); and(wire_niii_dataout, wire_nO_o[2], ~((~ n00lO))); and(wire_niil_dataout, wire_nO_o[3], ~((~ n00lO))); and(wire_niiO_dataout, wire_nO_o[4], ~((~ n00lO))); and(wire_nili_dataout, wire_nO_o[5], ~((~ n00lO))); and(wire_nill_dataout, wire_nO_o[6], ~((~ n00lO))); and(wire_nilO_dataout, wire_nO_o[7], ~((~ n00lO))); and(wire_niOi_dataout, wire_nO_o[8], ~((~ n00lO))); and(wire_niOl_dataout, wire_nO_o[9], ~((~ n00lO))); and(wire_niOO_dataout, wire_nO_o[10], ~((~ n00lO))); and(wire_nl0i_dataout, wire_nO_o[14], ~((~ n00lO))); and(wire_nl0l_dataout, wire_nO_o[15], ~((~ n00lO))); and(wire_nl0O_dataout, wire_nO_o[16], ~((~ n00lO))); and(wire_nl1i_dataout, wire_nO_o[11], ~((~ n00lO))); and(wire_nl1l_dataout, wire_nO_o[12], ~((~ n00lO))); and(wire_nl1O_dataout, wire_nO_o[13], ~((~ n00lO))); and(wire_nlii_dataout, wire_nO_o[17], ~((~ n00lO))); and(wire_nlil_dataout, wire_nO_o[18], ~((~ n00lO))); or(wire_nliO_dataout, wire_nlli_dataout, n1li); assign wire_nlli_dataout = (wire_nllii_o[5] === 1'b1) ? (((((gen2ngen1 & n0i1O) & (n0i1i34 ^ n0i1i33)) & n1Ol) & (n00Ol36 ^ n00Ol35)) | ((~ gen2ngen1) & n00Oi)) : wire_nlll_dataout; assign wire_nlll_dataout = (wire_nllii_o[7] === 1'b1) ? ((((gen2ngen1 & (((((~ ((n1OO ^ rauto_deassert_pc_rst_cnt[0]) ^ (~ (n0l1i20 ^ n0l1i19)))) & (~ (n01i ^ rauto_deassert_pc_rst_cnt[1]))) & (~ ((n01l ^ rauto_deassert_pc_rst_cnt[2]) ^ (~ (n0iOl22 ^ n0iOl21))))) & (~ ((n01O ^ rauto_deassert_pc_rst_cnt[3]) ^ (~ (n0ilO24 ^ n0ilO23))))) & (n0ili26 ^ n0ili25))) & n1Ol) & (n0iil28 ^ n0iil27)) | ((~ gen2ngen1) & (((((~ (n1Ol ^ rauto_deassert_pc_rst_cnt[0])) & (~ ((n1OO ^ rauto_deassert_pc_rst_cnt[1]) ^ (~ (n0i0O30 ^ n0i0O29))))) & (~ (n01i ^ rauto_deassert_pc_rst_cnt[2]))) & (~ (n01l ^ rauto_deassert_pc_rst_cnt[3]))) & (n0i0i32 ^ n0i0i31)))) : wire_nllO_dataout; and(wire_nllli_dataout, nll0i, ~(n1li)); or(wire_nllll_dataout, nlOOi, n1li); and(wire_nlllO_dataout, nlOOl, ~(n1li)); assign wire_nllO_dataout = (wire_nllii_o[9] === 1'b1) ? (((((gen2ngen1 & n0lil) & (n0l0O16 ^ n0l0O15)) & n1Ol) & (n0l0i18 ^ n0l0i17)) | ((~ gen2ngen1) & n0l1O)) : wire_nlOi_dataout; or(wire_nllOi_dataout, nlOOO, n1li); and(wire_nllOl_dataout, nlOOi, ~(n1li)); assign wire_nllOO_dataout = (n1li === 1'b1) ? (~ rphfifo_regmode_rx) : nlOOl; or(wire_nlO0i_dataout, nlOOl, n11O); and(wire_nlO0l_dataout, nlOOO, ~(n11O)); and(wire_nlO0O_dataout, nlOOO, ~(n1li)); assign wire_nlO1i_dataout = (n1li === 1'b1) ? rphfifo_regmode_rx : nlOOO; or(wire_nlO1l_dataout, nll0i, n11O); and(wire_nlO1O_dataout, nlOOi, ~(n11O)); assign wire_nlOi_dataout = (wire_nllii_o[1] === 1'b1) ? ((((gen2ngen1 & n0llO) & (n0lli14 ^ n0lli13)) & n1Ol) | ((~ gen2ngen1) & n0liO)) : n1li; or(wire_nlOii_dataout, nll0i, n000i); assign wire_nlOil_dataout = (n000i === 1'b1) ? rphfifo_regmode_rx : nlOOi; and(wire_nlOiO_dataout, nlOOl, ~(n000i)); and(wire_nlOli_dataout, nlOOO, ~(n000i)); oper_add nO ( .a({ni1O, ((n0lOO12 ^ n0lOO11) & ni1i), n0OO, n0Ol, n0Oi, n0lO, n0ll, ((n0O1i10 ^ n0O1i9) & n0li), n0iO, ((n0O1l8 ^ n0O1l7) & n0il), ((n0O1O6 ^ n0O1O5) & n0ii), n00O, n00l, ((n0O0i4 ^ n0O0i3) & n00i), n01O, n01l, n01i, n1OO, ((n0O0l2 ^ n0O0l1) & n1Ol)}), .b({{18{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_nO_o)); defparam nO.sgate_representation = 0, nO.width_a = 19, nO.width_b = 19, nO.width_o = 19; oper_decoder nllii ( .i({nlOOO, nlOOl, nlOOi, nll0i}), .o(wire_nllii_o)); defparam nllii.width_i = 4, nllii.width_o = 16; oper_mux nliOO ( .data({{6{1'b0}}, wire_nllli_dataout, 1'b1, wire_nllli_dataout, 1'b1, wire_nllli_dataout, wire_nlO1l_dataout, 1'b0, 1'b1, wire_nllli_dataout, wire_nlOii_dataout}), .o(wire_nliOO_o), .sel({nlOOO, nlOOl, nlOOi, nll0i})); defparam nliOO.width_data = 16, nliOO.width_sel = 4; oper_mux nll1i ( .data({{6{1'b0}}, wire_nllll_dataout, 1'b0, wire_nllOl_dataout, 1'b1, wire_nllll_dataout, wire_nlO1O_dataout, 1'b0, 1'b1, wire_nllll_dataout, wire_nlOil_dataout}), .o(wire_nll1i_o), .sel({nlOOO, nlOOl, nlOOi, nll0i})); defparam nll1i.width_data = 16, nll1i.width_sel = 4; oper_mux nll1l ( .data({{6{1'b0}}, wire_nlllO_dataout, 1'b0, wire_nlllO_dataout, 1'b1, wire_nllOO_dataout, wire_nlO0i_dataout, 1'b1, 1'b0, wire_nlllO_dataout, wire_nlOiO_dataout}), .o(wire_nll1l_o), .sel({nlOOO, nlOOl, nlOOi, nll0i})); defparam nll1l.width_data = 16, nll1l.width_sel = 4; oper_mux nll1O ( .data({{6{1'b0}}, wire_nllOi_dataout, 1'b1, wire_nllOi_dataout, 1'b0, wire_nlO1i_dataout, wire_nlO0l_dataout, {2{1'b0}}, wire_nlO0O_dataout, wire_nlOli_dataout}), .o(wire_nll1O_o), .sel({nlOOO, nlOOl, nlOOi, nll0i})); defparam nll1O.width_data = 16, nll1O.width_sel = 4; assign config_sel = n11l, cs = {nlOOO, nlOOl, nlOOi, nll0i}, dis_pc_byte = n001O, n000i = ((((n1il ^ n10l) ^ (~ (n000l44 ^ n000l43))) & rauto_speed_ena) & singleorbundle), n001l = (((((((wire_nllii_o[15] | wire_nllii_o[14]) | wire_nllii_o[13]) | wire_nllii_o[12]) | wire_nllii_o[11]) | wire_nllii_o[10]) | wire_nllii_o[1]) | wire_nllii_o[0]), n001O = (((((wire_nllii_o[7] | wire_nllii_o[6]) | wire_nllii_o[5]) | wire_nllii_o[4]) | wire_nllii_o[2]) | wire_nllii_o[3]), n00li = 1'b1, n00lO = (((wire_nllii_o[7] | wire_nllii_o[5]) | wire_nllii_o[1]) | wire_nllii_o[9]), n00Oi = ((((((((((((((((((~ (n1Ol ^ rpma_done_count[0])) & (~ (n1OO ^ rpma_done_count[1]))) & (~ (n01i ^ rpma_done_count[2]))) & (~ (n01l ^ rpma_done_count[3]))) & (~ (n01O ^ rpma_done_count[4]))) & (~ (n00i ^ rpma_done_count[5]))) & (~ (n00l ^ rpma_done_count[6]))) & (~ (n00O ^ rpma_done_count[7]))) & (~ (n0ii ^ rpma_done_count[8]))) & (~ (n0il ^ rpma_done_count[9]))) & (~ (n0iO ^ rpma_done_count[10]))) & (~ (n0li ^ rpma_done_count[11]))) & (~ (n0ll ^ rpma_done_count[12]))) & (~ (n0lO ^ rpma_done_count[13]))) & (~ (n0Oi ^ rpma_done_count[14]))) & (~ (n0Ol ^ rpma_done_count[15]))) & (~ (n0OO ^ rpma_done_count[16]))) & (~ (ni1i ^ rpma_done_count[17]))), n0i1O = ((((((((((((((((((~ (n1OO ^ rpma_done_count[0])) & (~ (n01i ^ rpma_done_count[1]))) & (~ (n01l ^ rpma_done_count[2]))) & (~ (n01O ^ rpma_done_count[3]))) & (~ (n00i ^ rpma_done_count[4]))) & (~ (n00l ^ rpma_done_count[5]))) & (~ (n00O ^ rpma_done_count[6]))) & (~ (n0ii ^ rpma_done_count[7]))) & (~ (n0il ^ rpma_done_count[8]))) & (~ (n0iO ^ rpma_done_count[9]))) & (~ (n0li ^ rpma_done_count[10]))) & (~ (n0ll ^ rpma_done_count[11]))) & (~ (n0lO ^ rpma_done_count[12]))) & (~ (n0Oi ^ rpma_done_count[13]))) & (~ (n0Ol ^ rpma_done_count[14]))) & (~ (n0OO ^ rpma_done_count[15]))) & (~ (ni1i ^ rpma_done_count[16]))) & (~ (ni1O ^ rpma_done_count[17]))), n0l1O = (((((~ (n1Ol ^ rauto_pc_en_cnt[0])) & (~ (n1OO ^ rauto_pc_en_cnt[1]))) & (~ (n01i ^ rauto_pc_en_cnt[2]))) & (~ (n01l ^ rauto_pc_en_cnt[3]))) & (~ (n01O ^ rauto_pc_en_cnt[4]))), n0lil = (((((~ (n1OO ^ rauto_pc_en_cnt[0])) & (~ (n01i ^ rauto_pc_en_cnt[1]))) & (~ (n01l ^ rauto_pc_en_cnt[2]))) & (~ (n01O ^ rauto_pc_en_cnt[3]))) & (~ (n00i ^ rauto_pc_en_cnt[4]))), n0liO = ((((((~ (n1Ol ^ rwait_for_phfifo_cnt[0])) & (~ (n1OO ^ rwait_for_phfifo_cnt[1]))) & (~ (n01i ^ rwait_for_phfifo_cnt[2]))) & (~ (n01l ^ rwait_for_phfifo_cnt[3]))) & (~ (n01O ^ rwait_for_phfifo_cnt[4]))) & (~ (n00i ^ rwait_for_phfifo_cnt[5]))), n0llO = ((((((~ (n1OO ^ rwait_for_phfifo_cnt[0])) & (~ (n01i ^ rwait_for_phfifo_cnt[1]))) & (~ (n01l ^ rwait_for_phfifo_cnt[2]))) & (~ (n01O ^ rwait_for_phfifo_cnt[3]))) & (~ (n00i ^ rwait_for_phfifo_cnt[4]))) & (~ (n00l ^ rwait_for_phfifo_cnt[5]))), pcie_switch = wire_n1ll_dataout, reset_pc_ptrs = (((wire_nllii_o[5] | wire_nllii_o[4]) | wire_nllii_o[2]) | wire_nllii_o[3]), speed_change = (~ n001l); endmodule //stratixiv_hssi_rx_digi_auto_speed_neg //synopsys translate_on //VALID FILE //IP Functional Simulation Model //VERSION_BEGIN 12.0 cbx_mgl 2012:05:31:20:09:47:SJ cbx_simgen 2012:05:31:20:08:35:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 // Copyright (C) 1991-2012 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // You may only use these simulation model output files for simulation // purposes and expressly not for synthesis or any other purposes (in which // event Altera disclaims all warranties of any kind). //synopsys translate_off //synthesis_resources = lut 149 mux21 612 oper_add 8 oper_decoder 4 oper_mux 37 oper_selector 4 `timescale 1 ps / 1 ps module stratixiv_hssi_rx_digi_bist_ver ( bistdone, bisterr, clk_2, cur_state, err_ctl, err_data, prbs_done, prbs_err, rbist_clr_rx, rbist_sel, rbisten_rx, rcxpat_chnl_sel, rdwidth_rx, rpma_doublewidth_rx, rpmadwidth_rx, rxc, rxd, selftest_done, selftest_err, soft_reset, sync_status) /* synthesis synthesis_clearbox=1 */; output bistdone; output bisterr; input clk_2; output [4:0] cur_state; output [1:0] err_ctl; output [15:0] err_data; input prbs_done; input prbs_err; input rbist_clr_rx; input [1:0] rbist_sel; input rbisten_rx; input [1:0] rcxpat_chnl_sel; input rdwidth_rx; input rpma_doublewidth_rx; input rpmadwidth_rx; input [3:0] rxc; input [63:0] rxd; output selftest_done; output selftest_err; input soft_reset; input sync_status; reg n0li1O47; reg n0li1O48; reg n0lOOi45; reg n0lOOi46; reg n0lOOl43; reg n0lOOl44; reg n0lOOO41; reg n0lOOO42; reg n0O10i33; reg n0O10i34; reg n0O10l31; reg n0O10l32; reg n0O10O29; reg n0O10O30; reg n0O11i39; reg n0O11i40; reg n0O11l37; reg n0O11l38; reg n0O11O35; reg n0O11O36; reg n0O1ii27; reg n0O1ii28; reg n0O1Ol25; reg n0O1Ol26; reg n0Oi0O21; reg n0Oi0O22; reg n0Oi1O23; reg n0Oi1O24; reg n0OiOi19; reg n0OiOi20; reg n0OiOO17; reg n0OiOO18; reg n0Ol0i11; reg n0Ol0i12; reg n0Ol0O10; reg n0Ol0O9; reg n0Ol1i15; reg n0Ol1i16; reg n0Ol1l13; reg n0Ol1l14; reg n0Olil7; reg n0Olil8; reg n0OlOO5; reg n0OlOO6; reg n0OO0i1; reg n0OO0i2; reg n0OO1l3; reg n0OO1l4; reg ni00i; reg ni01l; reg ni1lOl; reg niiilO; reg niiiOi; reg niiiOl; reg niiiOO; reg niil0i; reg niil0l; reg niil0O; reg niil1i; reg niil1l; reg niil1O; reg niilii; reg niilil; reg niiliO; reg niilli; reg niilll; reg niillO; reg niilOi; reg niilOl; reg niiO1i; reg niiO1l; reg nll00O; reg nll0ii; wire wire_ni01O_CLRN; reg n11Oi; reg ni00l; reg ni00O; reg ni01i; reg ni0ii; reg ni0il; reg ni0iO; reg ni0li; reg ni0ll; reg ni0lO; reg ni0Oi; reg ni0Ol; reg nii1i; reg niilOO; reg niiO0l; reg niiO0O; reg niiOii; reg niiOil; reg niiOiO; reg niiOli; reg niiOll; reg niiOlO; reg niiOOi; reg niiOOl; reg niiOOO; reg nil00i; reg nil00l; reg nil00O; reg nil01i; reg nil01l; reg nil01O; reg nil10i; reg nil10l; reg nil10O; reg nil11i; reg nil11l; reg nil11O; reg nil1ii; reg nil1il; reg nil1iO; reg nil1li; reg nil1ll; reg nil1lO; reg nil1Oi; reg nil1Ol; reg nil1OO; reg nl1Oll; reg nll00l; reg nll0il; reg nll0iO; reg nll0li; reg nll0ll; reg nll0lO; reg nll0Oi; reg nll0Ol; reg nll0OO; reg nlli0i; reg nlli0l; reg nlli0O; reg nlli1i; reg nlli1l; reg nlli1O; reg nlliii; reg nlliil; reg nlliiO; reg nllili; reg nllill; reg nllilO; reg nlliOi; reg nlliOl; reg nlliOO; reg nlll0i; reg nlll1i; reg nlll1l; reg nlll1O; reg ni0OO_clk_prev; wire wire_ni0OO_CLRN; wire wire_ni0OO_PRN; reg niiO0i; reg niiO1O_clk_prev; wire wire_niiO1O_CLRN; wire wire_n000i_dataout; wire wire_n000l_dataout; wire wire_n000O_dataout; wire wire_n001i_dataout; wire wire_n001l_dataout; wire wire_n001O_dataout; wire wire_n00i_dataout; wire wire_n00ii_dataout; wire wire_n00il_dataout; wire wire_n00iO_dataout; wire wire_n00l_dataout; wire wire_n00li_dataout; wire wire_n00ll_dataout; wire wire_n00lO_dataout; wire wire_n00O_dataout; wire wire_n00Oi_dataout; wire wire_n00Ol_dataout; wire wire_n00OO_dataout; wire wire_n010i_dataout; wire wire_n010l_dataout; wire wire_n010O_dataout; wire wire_n011i_dataout; wire wire_n011l_dataout; wire wire_n011O_dataout; wire wire_n01i_dataout; wire wire_n01ii_dataout; wire wire_n01il_dataout; wire wire_n01iO_dataout; wire wire_n01l_dataout; wire wire_n01li_dataout; wire wire_n01ll_dataout; wire wire_n01lO_dataout; wire wire_n01O_dataout; wire wire_n01Oi_dataout; wire wire_n01Ol_dataout; wire wire_n01OO_dataout; wire wire_n0i_dataout; wire wire_n0i0i_dataout; wire wire_n0i0l_dataout; wire wire_n0i0O_dataout; wire wire_n0i1i_dataout; wire wire_n0i1l_dataout; wire wire_n0i1O_dataout; wire wire_n0ii_dataout; wire wire_n0iii_dataout; wire wire_n0iil_dataout; wire wire_n0iiO_dataout; wire wire_n0il_dataout; wire wire_n0ili_dataout; wire wire_n0ill_dataout; wire wire_n0ilO_dataout; wire wire_n0iO_dataout; wire wire_n0iOi_dataout; wire wire_n0iOl_dataout; wire wire_n0iOO_dataout; wire wire_n0l_dataout; wire wire_n0l0i_dataout; wire wire_n0l0l_dataout; wire wire_n0l0O_dataout; wire wire_n0l1i_dataout; wire wire_n0l1l_dataout; wire wire_n0l1O_dataout; wire wire_n0li_dataout; wire wire_n0lii_dataout; wire wire_n0lil_dataout; wire wire_n0liO_dataout; wire wire_n0lli_dataout; wire wire_n0lll_dataout; wire wire_n0llO_dataout; wire wire_n0lOi_dataout; wire wire_n0lOl_dataout; wire wire_n0lOO_dataout; wire wire_n0O_dataout; wire wire_n0O0i_dataout; wire wire_n0O0l_dataout; wire wire_n0O0O_dataout; wire wire_n0O1i_dataout; wire wire_n0O1l_dataout; wire wire_n0O1O_dataout; wire wire_n0Oi_dataout; wire wire_n0Oii_dataout; wire wire_n0Oil_dataout; wire wire_n0OiO_dataout; wire wire_n0Ol_dataout; wire wire_n0Oli_dataout; wire wire_n0Oll_dataout; wire wire_n0OlO_dataout; wire wire_n0OO_dataout; wire wire_n0OOi_dataout; wire wire_n0OOl_dataout; wire wire_n0OOO_dataout; wire wire_n100O_dataout; wire wire_n10ii_dataout; wire wire_n10il_dataout; wire wire_n10iO_dataout; wire wire_n10li_dataout; wire wire_n10ll_dataout; wire wire_n10lO_dataout; wire wire_n10Oi_dataout; wire wire_n10Ol_dataout; wire wire_n10OO_dataout; wire wire_n1i0i_dataout; wire wire_n1i0l_dataout; wire wire_n1i0O_dataout; wire wire_n1i1i_dataout; wire wire_n1i1l_dataout; wire wire_n1iii_dataout; wire wire_n1iil_dataout; wire wire_n1iiO_dataout; wire wire_n1ili_dataout; wire wire_n1ill_dataout; wire wire_n1ilO_dataout; wire wire_n1iOi_dataout; wire wire_n1iOl_dataout; wire wire_n1iOO_dataout; wire wire_n1l_dataout; wire wire_n1l0i_dataout; wire wire_n1l0l_dataout; wire wire_n1l0O_dataout; wire wire_n1l1i_dataout; wire wire_n1l1l_dataout; wire wire_n1l1O_dataout; wire wire_n1lii_dataout; wire wire_n1lil_dataout; wire wire_n1liO_dataout; wire wire_n1ll_dataout; wire wire_n1lli_dataout; wire wire_n1lll_dataout; wire wire_n1lO_dataout; wire wire_n1lOi_dataout; wire wire_n1lOl_dataout; wire wire_n1lOO_dataout; wire wire_n1O_dataout; wire wire_n1O0i_dataout; wire wire_n1O0l_dataout; wire wire_n1O0O_dataout; wire wire_n1O1i_dataout; wire wire_n1O1l_dataout; wire wire_n1O1O_dataout; wire wire_n1Oi_dataout; wire wire_n1Oii_dataout; wire wire_n1Oil_dataout; wire wire_n1OiO_dataout; wire wire_n1Ol_dataout; wire wire_n1Oli_dataout; wire wire_n1Oll_dataout; wire wire_n1OlO_dataout; wire wire_n1OO_dataout; wire wire_n1OOi_dataout; wire wire_n1OOl_dataout; wire wire_n1OOO_dataout; wire wire_ni_dataout; wire wire_ni000i_dataout; wire wire_ni000l_dataout; wire wire_ni000O_dataout; wire wire_ni001i_dataout; wire wire_ni001l_dataout; wire wire_ni001O_dataout; wire wire_ni00il_dataout; wire wire_ni00iO_dataout; wire wire_ni00ll_dataout; wire wire_ni00lO_dataout; wire wire_ni00Ol_dataout; wire wire_ni00OO_dataout; wire wire_ni010i_dataout; wire wire_ni010l_dataout; wire wire_ni010O_dataout; wire wire_ni011l_dataout; wire wire_ni011O_dataout; wire wire_ni01ii_dataout; wire wire_ni01il_dataout; wire wire_ni01li_dataout; wire wire_ni01ll_dataout; wire wire_ni01Oi_dataout; wire wire_ni01Ol_dataout; wire wire_ni0i_dataout; wire wire_ni0i0i_dataout; wire wire_ni0i0l_dataout; wire wire_ni0i1i_dataout; wire wire_ni0i1l_dataout; wire wire_ni0i1O_dataout; wire wire_ni0iii_dataout; wire wire_ni0iil_dataout; wire wire_ni0ili_dataout; wire wire_ni0ill_dataout; wire wire_ni0iOi_dataout; wire wire_ni0iOl_dataout; wire wire_ni0iOO_dataout; wire wire_ni0l_dataout; wire wire_ni0l0l_dataout; wire wire_ni0l0O_dataout; wire wire_ni0l1i_dataout; wire wire_ni0l1l_dataout; wire wire_ni0l1O_dataout; wire wire_ni0lil_dataout; wire wire_ni0liO_dataout; wire wire_ni0lli_dataout; wire wire_ni0lll_dataout; wire wire_ni0llO_dataout; wire wire_ni0lOi_dataout; wire wire_ni0lOl_dataout; wire wire_ni0lOO_dataout; wire wire_ni0O_dataout; wire wire_ni0O0i_dataout; wire wire_ni0O0l_dataout; wire wire_ni0O0O_dataout; wire wire_ni0O1i_dataout; wire wire_ni0O1l_dataout; wire wire_ni0O1O_dataout; wire wire_ni0OiO_dataout; wire wire_ni0Oli_dataout; wire wire_ni0Oll_dataout; wire wire_ni0OlO_dataout; wire wire_ni0OOi_dataout; wire wire_ni0OOl_dataout; wire wire_ni0OOO_dataout; wire wire_ni10i_dataout; wire wire_ni10l_dataout; wire wire_ni10O_dataout; wire wire_ni11i_dataout; wire wire_ni11l_dataout; wire wire_ni11O_dataout; wire wire_ni1i_dataout; wire wire_ni1ii_dataout; wire wire_ni1il_dataout; wire wire_ni1iO_dataout; wire wire_ni1l_dataout; wire wire_ni1l0i_dataout; wire wire_ni1l0l_dataout; wire wire_ni1l0O_dataout; wire wire_ni1l1i_dataout; wire wire_ni1l1l_dataout; wire wire_ni1l1O_dataout; wire wire_ni1lii_dataout; wire wire_ni1lil_dataout; wire wire_ni1liO_dataout; wire wire_ni1lli_dataout; wire wire_ni1lll_dataout; wire wire_ni1llO_dataout; wire wire_ni1lOO_dataout; wire wire_ni1O_dataout; wire wire_ni1O0i_dataout; wire wire_ni1O0l_dataout; wire wire_ni1O0O_dataout; wire wire_ni1O1i_dataout; wire wire_ni1O1l_dataout; wire wire_ni1O1O_dataout; wire wire_ni1Oii_dataout; wire wire_ni1OiO_dataout; wire wire_ni1Oli_dataout; wire wire_ni1Oll_dataout; wire wire_ni1OlO_dataout; wire wire_ni1OOl_dataout; wire wire_ni1OOO_dataout; wire wire_nii_dataout; wire wire_nii00i_dataout; wire wire_nii00l_dataout; wire wire_nii00O_dataout; wire wire_nii0i_dataout; wire wire_nii0ii_dataout; wire wire_nii0l_dataout; wire wire_nii0ll_dataout; wire wire_nii0O_dataout; wire wire_nii0Oi_dataout; wire wire_nii10i_dataout; wire wire_nii10l_dataout; wire wire_nii10O_dataout; wire wire_nii11i_dataout; wire wire_nii11l_dataout; wire wire_nii11O_dataout; wire wire_nii1ii_dataout; wire wire_nii1il_dataout; wire wire_nii1iO_dataout; wire wire_nii1l_dataout; wire wire_nii1O_dataout; wire wire_niii_dataout; wire wire_niiii_dataout; wire wire_niiil_dataout; wire wire_niiiO_dataout; wire wire_niil_dataout; wire wire_niili_dataout; wire wire_niill_dataout; wire wire_niilO_dataout; wire wire_niiO_dataout; wire wire_niiOi_dataout; wire wire_nil_dataout; wire wire_nil0ii_dataout; wire wire_nil0il_dataout; wire wire_nil0iO_dataout; wire wire_nil0li_dataout; wire wire_nil0ll_dataout; wire wire_nil0lO_dataout; wire wire_nil0Oi_dataout; wire wire_nil0Ol_dataout; wire wire_nil0OO_dataout; wire wire_nili_dataout; wire wire_nili0i_dataout; wire wire_nili0l_dataout; wire wire_nili0O_dataout; wire wire_nili1i_dataout; wire wire_nili1l_dataout; wire wire_nili1O_dataout; wire wire_niliii_dataout; wire wire_niliil_dataout; wire wire_niliiO_dataout; wire wire_nilili_dataout; wire wire_nilill_dataout; wire wire_nililO_dataout; wire wire_niliOi_dataout; wire wire_niliOl_dataout; wire wire_niliOO_dataout; wire wire_nill_dataout; wire wire_nill0i_dataout; wire wire_nill0l_dataout; wire wire_nill0O_dataout; wire wire_nill1i_dataout; wire wire_nill1l_dataout; wire wire_nill1O_dataout; wire wire_nillii_dataout; wire wire_nillil_dataout; wire wire_nilliO_dataout; wire wire_nillli_dataout; wire wire_nillll_dataout; wire wire_nilllO_dataout; wire wire_nillOi_dataout; wire wire_nillOl_dataout; wire wire_nillOO_dataout; wire wire_nilO_dataout; wire wire_nilO0i_dataout; wire wire_nilO0l_dataout; wire wire_nilO0O_dataout; wire wire_nilO1i_dataout; wire wire_nilO1l_dataout; wire wire_nilO1O_dataout; wire wire_nilOii_dataout; wire wire_nilOil_dataout; wire wire_nilOiO_dataout; wire wire_nilOli_dataout; wire wire_nilOll_dataout; wire wire_nilOlO_dataout; wire wire_nilOOi_dataout; wire wire_nilOOl_dataout; wire wire_nilOOO_dataout; wire wire_niO_dataout; wire wire_niO00i_dataout; wire wire_niO00l_dataout; wire wire_niO00O_dataout; wire wire_niO01i_dataout; wire wire_niO01l_dataout; wire wire_niO01O_dataout; wire wire_niO0ii_dataout; wire wire_niO0il_dataout; wire wire_niO0iO_dataout; wire wire_niO0li_dataout; wire wire_niO0ll_dataout; wire wire_niO0lO_dataout; wire wire_niO0Oi_dataout; wire wire_niO10i_dataout; wire wire_niO10l_dataout; wire wire_niO10O_dataout; wire wire_niO11i_dataout; wire wire_niO11l_dataout; wire wire_niO11O_dataout; wire wire_niO1ii_dataout; wire wire_niO1il_dataout; wire wire_niO1iO_dataout; wire wire_niO1li_dataout; wire wire_niO1ll_dataout; wire wire_niO1lO_dataout; wire wire_niO1Oi_dataout; wire wire_niO1Ol_dataout; wire wire_niO1OO_dataout; wire wire_niOi_dataout; wire wire_niOi0i_dataout; wire wire_niOi0l_dataout; wire wire_niOi0O_dataout; wire wire_niOi1l_dataout; wire wire_niOi1O_dataout; wire wire_niOiii_dataout; wire wire_niOiil_dataout; wire wire_niOiiO_dataout; wire wire_niOili_dataout; wire wire_niOill_dataout; wire wire_niOilO_dataout; wire wire_niOiOi_dataout; wire wire_niOiOl_dataout; wire wire_niOiOO_dataout; wire wire_niOl_dataout; wire wire_niOl1i_dataout; wire wire_niOl1l_dataout; wire wire_niOO_dataout; wire wire_nl_dataout; wire wire_nl000l_dataout; wire wire_nl000O_dataout; wire wire_nl001i_dataout; wire wire_nl001l_dataout; wire wire_nl001O_dataout; wire wire_nl00ii_dataout; wire wire_nl00il_dataout; wire wire_nl00iO_dataout; wire wire_nl00li_dataout; wire wire_nl00ll_dataout; wire wire_nl00lO_dataout; wire wire_nl00Oi_dataout; wire wire_nl00Ol_dataout; wire wire_nl00OO_dataout; wire wire_nl01il_dataout; wire wire_nl01iO_dataout; wire wire_nl01li_dataout; wire wire_nl01ll_dataout; wire wire_nl01lO_dataout; wire wire_nl01Oi_dataout; wire wire_nl01Ol_dataout; wire wire_nl01OO_dataout; wire wire_nl0i_dataout; wire wire_nl0i0i_dataout; wire wire_nl0i0l_dataout; wire wire_nl0i0O_dataout; wire wire_nl0i1i_dataout; wire wire_nl0i1l_dataout; wire wire_nl0i1O_dataout; wire wire_nl0iii_dataout; wire wire_nl0iil_dataout; wire wire_nl0iiO_dataout; wire wire_nl0ili_dataout; wire wire_nl0ill_dataout; wire wire_nl0ilO_dataout; wire wire_nl0iOl_dataout; wire wire_nl0iOO_dataout; wire wire_nl0l_dataout; wire wire_nl0l0i_dataout; wire wire_nl0l0l_dataout; wire wire_nl0l0O_dataout; wire wire_nl0l1i_dataout; wire wire_nl0l1l_dataout; wire wire_nl0l1O_dataout; wire wire_nl0lii_dataout; wire wire_nl0lil_dataout; wire wire_nl0liO_dataout; wire wire_nl0lli_dataout; wire wire_nl0lll_dataout; wire wire_nl0llO_dataout; wire wire_nl0lOi_dataout; wire wire_nl0lOl_dataout; wire wire_nl0lOO_dataout; wire wire_nl0O_dataout; wire wire_nl0O0i_dataout; wire wire_nl0O0l_dataout; wire wire_nl0O0O_dataout; wire wire_nl0O1i_dataout; wire wire_nl0O1l_dataout; wire wire_nl0O1O_dataout; wire wire_nl0Oii_dataout; wire wire_nl0Oil_dataout; wire wire_nl0OiO_dataout; wire wire_nl0Oli_dataout; wire wire_nl0Oll_dataout; wire wire_nl0OlO_dataout; wire wire_nl0OOi_dataout; wire wire_nl0OOl_dataout; wire wire_nl0OOO_dataout; wire wire_nl1i_dataout; wire wire_nl1l_dataout; wire wire_nl1O_dataout; wire wire_nl1Oii_dataout; wire wire_nl1Oil_dataout; wire wire_nl1Oli_dataout; wire wire_nl1OlO_dataout; wire wire_nl1OOi_dataout; wire wire_nl1OOl_dataout; wire wire_nl1OOO_dataout; wire wire_nli_dataout; wire wire_nli00i_dataout; wire wire_nli00l_dataout; wire wire_nli00O_dataout; wire wire_nli01i_dataout; wire wire_nli01l_dataout; wire wire_nli01O_dataout; wire wire_nli0ii_dataout; wire wire_nli0il_dataout; wire wire_nli0iO_dataout; wire wire_nli0li_dataout; wire wire_nli0ll_dataout; wire wire_nli0lO_dataout; wire wire_nli0Oi_dataout; wire wire_nli0Ol_dataout; wire wire_nli0OO_dataout; wire wire_nli10i_dataout; wire wire_nli10l_dataout; wire wire_nli10O_dataout; wire wire_nli11i_dataout; wire wire_nli11l_dataout; wire wire_nli11O_dataout; wire wire_nli1ii_dataout; wire wire_nli1il_dataout; wire wire_nli1iO_dataout; wire wire_nli1li_dataout; wire wire_nli1ll_dataout; wire wire_nli1lO_dataout; wire wire_nli1Oi_dataout; wire wire_nli1Ol_dataout; wire wire_nli1OO_dataout; wire wire_nlii_dataout; wire wire_nlii0i_dataout; wire wire_nlii0l_dataout; wire wire_nlii0O_dataout; wire wire_nlii1i_dataout; wire wire_nlii1l_dataout; wire wire_nlii1O_dataout; wire wire_nliiii_dataout; wire wire_nliiil_dataout; wire wire_nliiiO_dataout; wire wire_nliill_dataout; wire wire_nliilO_dataout; wire wire_nliiOi_dataout; wire wire_nliiOl_dataout; wire wire_nliiOO_dataout; wire wire_nlil_dataout; wire wire_nlil0i_dataout; wire wire_nlil0l_dataout; wire wire_nlil0O_dataout; wire wire_nlil1i_dataout; wire wire_nlil1l_dataout; wire wire_nlil1O_dataout; wire wire_nlilii_dataout; wire wire_nlilil_dataout; wire wire_nliliO_dataout; wire wire_nlilli_dataout; wire wire_nlilll_dataout; wire wire_nlillO_dataout; wire wire_nlilOi_dataout; wire wire_nlilOl_dataout; wire wire_nlilOO_dataout; wire wire_nliO_dataout; wire wire_nliO0i_dataout; wire wire_nliO0l_dataout; wire wire_nliO0O_dataout; wire wire_nliO1i_dataout; wire wire_nliO1l_dataout; wire wire_nliO1O_dataout; wire wire_nliOii_dataout; wire wire_nliOil_dataout; wire wire_nliOiO_dataout; wire wire_nliOli_dataout; wire wire_nliOll_dataout; wire wire_nliOlO_dataout; wire wire_nliOOi_dataout; wire wire_nliOOl_dataout; wire wire_nliOOO_dataout; wire wire_nll10i_dataout; wire wire_nll10l_dataout; wire wire_nll10O_dataout; wire wire_nll11i_dataout; wire wire_nll11O_dataout; wire wire_nll1ii_dataout; wire wire_nll1il_dataout; wire wire_nll1iO_dataout; wire wire_nll1li_dataout; wire wire_nll1ll_dataout; wire wire_nll1lO_dataout; wire wire_nll1Oi_dataout; wire wire_nll1Ol_dataout; wire wire_nlli_dataout; wire wire_nlll_dataout; wire wire_nlll0l_dataout; wire wire_nlll0O_dataout; wire wire_nlllii_dataout; wire wire_nlllil_dataout; wire wire_nllliO_dataout; wire wire_nlllli_dataout; wire wire_nlllll_dataout; wire wire_nllllO_dataout; wire wire_nlllOi_dataout; wire wire_nlllOl_dataout; wire wire_nlllOO_dataout; wire wire_nllO_dataout; wire wire_nllO0l_dataout; wire wire_nllO0O_dataout; wire wire_nllO1i_dataout; wire wire_nllO1l_dataout; wire wire_nllO1O_dataout; wire wire_nllOii_dataout; wire wire_nllOiO_dataout; wire wire_nllOli_dataout; wire wire_nllOll_dataout; wire wire_nllOlO_dataout; wire wire_nllOOi_dataout; wire wire_nllOOl_dataout; wire wire_nllOOO_dataout; wire wire_nlO00i_dataout; wire wire_nlO00l_dataout; wire wire_nlO01i_dataout; wire wire_nlO01l_dataout; wire wire_nlO01O_dataout; wire wire_nlO10i_dataout; wire wire_nlO10l_dataout; wire wire_nlO10O_dataout; wire wire_nlO11i_dataout; wire wire_nlO11O_dataout; wire wire_nlO1ii_dataout; wire wire_nlO1il_dataout; wire wire_nlO1iO_dataout; wire wire_nlO1li_dataout; wire wire_nlO1ll_dataout; wire wire_nlO1lO_dataout; wire wire_nlO1Oi_dataout; wire wire_nlO1Ol_dataout; wire wire_nlO1OO_dataout; wire wire_nlOi_dataout; wire wire_nlOl_dataout; wire wire_nlOO_dataout; wire wire_nO_dataout; wire [4:0] wire_niiOl_o; wire [6:0] wire_niO0Ol_o; wire [6:0] wire_niO0OO_o; wire [8:0] wire_niOi1i_o; wire [5:0] wire_nllO0i_o; wire [2:0] wire_nllOil_o; wire [8:0] wire_nlO00O_o; wire [3:0] wire_nlO11l_o; wire [31:0] wire_n11li_o; wire [15:0] wire_ni1iii_o; wire [15:0] wire_nii0Ol_o; wire [15:0] wire_nl1OiO_o; wire wire_n100i_o; wire wire_n100l_o; wire wire_n101i_o; wire wire_n101l_o; wire wire_n101O_o; wire wire_n11Ol_o; wire wire_n11OO_o; wire wire_ni1iil_o; wire wire_ni1iiO_o; wire wire_ni1ili_o; wire wire_ni1ill_o; wire wire_ni1ilO_o; wire wire_ni1iOi_o; wire wire_ni1iOl_o; wire wire_ni1iOO_o; wire wire_nii0iO_o; wire wire_nii0li_o; wire wire_nii0lO_o; wire wire_nii0OO_o; wire wire_niii0i_o; wire wire_niii0l_o; wire wire_niii0O_o; wire wire_niii1i_o; wire wire_niii1l_o; wire wire_niii1O_o; wire wire_niiiii_o; wire wire_niiiil_o; wire wire_niiiiO_o; wire wire_niiili_o; wire wire_niiill_o; wire wire_nl010i_o; wire wire_nl010l_o; wire wire_nl010O_o; wire wire_nl011i_o; wire wire_nl011l_o; wire wire_nl011O_o; wire wire_nl01ii_o; wire wire_n11ii_o; wire wire_n11il_o; wire wire_n11ll_o; wire wire_ni1i0l_o; wire n0iO0i; wire n0iO0l; wire n0iO0O; wire n0iO1i; wire n0iO1l; wire n0iO1O; wire n0iOii; wire n0iOil; wire n0iOiO; wire n0iOli; wire n0iOll; wire n0iOlO; wire n0iOOi; wire n0iOOl; wire n0iOOO; wire n0l00i; wire n0l00l; wire n0l00O; wire n0l01i; wire n0l01l; wire n0l01O; wire n0l0ii; wire n0l0il; wire n0l0iO; wire n0l0li; wire n0l0ll; wire n0l0lO; wire n0l0Oi; wire n0l0Ol; wire n0l0OO; wire n0l10i; wire n0l10l; wire n0l10O; wire n0l11i; wire n0l11l; wire n0l11O; wire n0l1ii; wire n0l1il; wire n0l1iO; wire n0l1li; wire n0l1ll; wire n0l1lO; wire n0l1Oi; wire n0l1Ol; wire n0l1OO; wire n0li0i; wire n0li0l; wire n0li0O; wire n0li1i; wire n0li1l; wire n0liii; wire n0liil; wire n0liiO; wire n0lili; wire n0lill; wire n0lilO; wire n0liOi; wire n0liOl; wire n0liOO; wire n0ll0i; wire n0ll0l; wire n0ll0O; wire n0ll1i; wire n0ll1l; wire n0ll1O; wire n0llii; wire n0llil; wire n0lliO; wire n0llli; wire n0llll; wire n0lllO; wire n0llOi; wire n0llOl; wire n0llOO; wire n0lO0i; wire n0lO0l; wire n0lO0O; wire n0lO1i; wire n0lO1l; wire n0lO1O; wire n0lOii; wire n0lOil; wire n0lOiO; wire n0lOli; wire n0lOll; wire n0lOlO; wire n0O00i; wire n0O00l; wire n0O00O; wire n0O01i; wire n0O01l; wire n0O01O; wire n0O0ii; wire n0O0il; wire n0O0iO; wire n0O0li; wire n0O0ll; wire n0O0lO; wire n0O0Oi; wire n0O0Ol; wire n0O0OO; wire n0O1il; wire n0O1iO; wire n0O1li; wire n0O1ll; wire n0O1lO; wire n0O1Oi; wire n0Oi0l; wire n0Oi1i; wire n0Oi1l; wire n0Oiil; wire n0OiiO; wire n0Oili; wire n0Oill; wire n0OilO; wire n0OiOl; wire n0Olli; wire n0Olll; wire n0OllO; wire n0OlOi; wire n0OlOl; initial n0li1O47 = 0; always @ ( posedge clk_2) n0li1O47 <= n0li1O48; event n0li1O47_event; initial #1 ->n0li1O47_event; always @(n0li1O47_event) n0li1O47 <= {1{1'b1}}; initial n0li1O48 = 0; always @ ( posedge clk_2) n0li1O48 <= n0li1O47; initial n0lOOi45 = 0; always @ ( posedge clk_2) n0lOOi45 <= n0lOOi46; event n0lOOi45_event; initial #1 ->n0lOOi45_event; always @(n0lOOi45_event) n0lOOi45 <= {1{1'b1}}; initial n0lOOi46 = 0; always @ ( posedge clk_2) n0lOOi46 <= n0lOOi45; initial n0lOOl43 = 0; always @ ( posedge clk_2) n0lOOl43 <= n0lOOl44; event n0lOOl43_event; initial #1 ->n0lOOl43_event; always @(n0lOOl43_event) n0lOOl43 <= {1{1'b1}}; initial n0lOOl44 = 0; always @ ( posedge clk_2) n0lOOl44 <= n0lOOl43; initial n0lOOO41 = 0; always @ ( posedge clk_2) n0lOOO41 <= n0lOOO42; event n0lOOO41_event; initial #1 ->n0lOOO41_event; always @(n0lOOO41_event) n0lOOO41 <= {1{1'b1}}; initial n0lOOO42 = 0; always @ ( posedge clk_2) n0lOOO42 <= n0lOOO41; initial n0O10i33 = 0; always @ ( posedge clk_2) n0O10i33 <= n0O10i34; event n0O10i33_event; initial #1 ->n0O10i33_event; always @(n0O10i33_event) n0O10i33 <= {1{1'b1}}; initial n0O10i34 = 0; always @ ( posedge clk_2) n0O10i34 <= n0O10i33; initial n0O10l31 = 0; always @ ( posedge clk_2) n0O10l31 <= n0O10l32; event n0O10l31_event; initial #1 ->n0O10l31_event; always @(n0O10l31_event) n0O10l31 <= {1{1'b1}}; initial n0O10l32 = 0; always @ ( posedge clk_2) n0O10l32 <= n0O10l31; initial n0O10O29 = 0; always @ ( posedge clk_2) n0O10O29 <= n0O10O30; event n0O10O29_event; initial #1 ->n0O10O29_event; always @(n0O10O29_event) n0O10O29 <= {1{1'b1}}; initial n0O10O30 = 0; always @ ( posedge clk_2) n0O10O30 <= n0O10O29; initial n0O11i39 = 0; always @ ( posedge clk_2) n0O11i39 <= n0O11i40; event n0O11i39_event; initial #1 ->n0O11i39_event; always @(n0O11i39_event) n0O11i39 <= {1{1'b1}}; initial n0O11i40 = 0; always @ ( posedge clk_2) n0O11i40 <= n0O11i39; initial n0O11l37 = 0; always @ ( posedge clk_2) n0O11l37 <= n0O11l38; event n0O11l37_event; initial #1 ->n0O11l37_event; always @(n0O11l37_event) n0O11l37 <= {1{1'b1}}; initial n0O11l38 = 0; always @ ( posedge clk_2) n0O11l38 <= n0O11l37; initial n0O11O35 = 0; always @ ( posedge clk_2) n0O11O35 <= n0O11O36; event n0O11O35_event; initial #1 ->n0O11O35_event; always @(n0O11O35_event) n0O11O35 <= {1{1'b1}}; initial n0O11O36 = 0; always @ ( posedge clk_2) n0O11O36 <= n0O11O35; initial n0O1ii27 = 0; always @ ( posedge clk_2) n0O1ii27 <= n0O1ii28; event n0O1ii27_event; initial #1 ->n0O1ii27_event; always @(n0O1ii27_event) n0O1ii27 <= {1{1'b1}}; initial n0O1ii28 = 0; always @ ( posedge clk_2) n0O1ii28 <= n0O1ii27; initial n0O1Ol25 = 0; always @ ( posedge clk_2) n0O1Ol25 <= n0O1Ol26; event n0O1Ol25_event; initial #1 ->n0O1Ol25_event; always @(n0O1Ol25_event) n0O1Ol25 <= {1{1'b1}}; initial n0O1Ol26 = 0; always @ ( posedge clk_2) n0O1Ol26 <= n0O1Ol25; initial n0Oi0O21 = 0; always @ ( posedge clk_2) n0Oi0O21 <= n0Oi0O22; event n0Oi0O21_event; initial #1 ->n0Oi0O21_event; always @(n0Oi0O21_event) n0Oi0O21 <= {1{1'b1}}; initial n0Oi0O22 = 0; always @ ( posedge clk_2) n0Oi0O22 <= n0Oi0O21; initial n0Oi1O23 = 0; always @ ( posedge clk_2) n0Oi1O23 <= n0Oi1O24; event n0Oi1O23_event; initial #1 ->n0Oi1O23_event; always @(n0Oi1O23_event) n0Oi1O23 <= {1{1'b1}}; initial n0Oi1O24 = 0; always @ ( posedge clk_2) n0Oi1O24 <= n0Oi1O23; initial n0OiOi19 = 0; always @ ( posedge clk_2) n0OiOi19 <= n0OiOi20; event n0OiOi19_event; initial #1 ->n0OiOi19_event; always @(n0OiOi19_event) n0OiOi19 <= {1{1'b1}}; initial n0OiOi20 = 0; always @ ( posedge clk_2) n0OiOi20 <= n0OiOi19; initial n0OiOO17 = 0; always @ ( posedge clk_2) n0OiOO17 <= n0OiOO18; event n0OiOO17_event; initial #1 ->n0OiOO17_event; always @(n0OiOO17_event) n0OiOO17 <= {1{1'b1}}; initial n0OiOO18 = 0; always @ ( posedge clk_2) n0OiOO18 <= n0OiOO17; initial n0Ol0i11 = 0; always @ ( posedge clk_2) n0Ol0i11 <= n0Ol0i12; event n0Ol0i11_event; initial #1 ->n0Ol0i11_event; always @(n0Ol0i11_event) n0Ol0i11 <= {1{1'b1}}; initial n0Ol0i12 = 0; always @ ( posedge clk_2) n0Ol0i12 <= n0Ol0i11; initial n0Ol0O10 = 0; always @ ( posedge clk_2) n0Ol0O10 <= n0Ol0O9; initial n0Ol0O9 = 0; always @ ( posedge clk_2) n0Ol0O9 <= n0Ol0O10; event n0Ol0O9_event; initial #1 ->n0Ol0O9_event; always @(n0Ol0O9_event) n0Ol0O9 <= {1{1'b1}}; initial n0Ol1i15 = 0; always @ ( posedge clk_2) n0Ol1i15 <= n0Ol1i16; event n0Ol1i15_event; initial #1 ->n0Ol1i15_event; always @(n0Ol1i15_event) n0Ol1i15 <= {1{1'b1}}; initial n0Ol1i16 = 0; always @ ( posedge clk_2) n0Ol1i16 <= n0Ol1i15; initial n0Ol1l13 = 0; always @ ( posedge clk_2) n0Ol1l13 <= n0Ol1l14; event n0Ol1l13_event; initial #1 ->n0Ol1l13_event; always @(n0Ol1l13_event) n0Ol1l13 <= {1{1'b1}}; initial n0Ol1l14 = 0; always @ ( posedge clk_2) n0Ol1l14 <= n0Ol1l13; initial n0Olil7 = 0; always @ ( posedge clk_2) n0Olil7 <= n0Olil8; event n0Olil7_event; initial #1 ->n0Olil7_event; always @(n0Olil7_event) n0Olil7 <= {1{1'b1}}; initial n0Olil8 = 0; always @ ( posedge clk_2) n0Olil8 <= n0Olil7; initial n0OlOO5 = 0; always @ ( posedge clk_2) n0OlOO5 <= n0OlOO6; event n0OlOO5_event; initial #1 ->n0OlOO5_event; always @(n0OlOO5_event) n0OlOO5 <= {1{1'b1}}; initial n0OlOO6 = 0; always @ ( posedge clk_2) n0OlOO6 <= n0OlOO5; initial n0OO0i1 = 0; always @ ( posedge clk_2) n0OO0i1 <= n0OO0i2; event n0OO0i1_event; initial #1 ->n0OO0i1_event; always @(n0OO0i1_event) n0OO0i1 <= {1{1'b1}}; initial n0OO0i2 = 0; always @ ( posedge clk_2) n0OO0i2 <= n0OO0i1; initial n0OO1l3 = 0; always @ ( posedge clk_2) n0OO1l3 <= n0OO1l4; event n0OO1l3_event; initial #1 ->n0OO1l3_event; always @(n0OO1l3_event) n0OO1l3 <= {1{1'b1}}; initial n0OO1l4 = 0; always @ ( posedge clk_2) n0OO1l4 <= n0OO1l3; initial begin ni00i = 0; ni01l = 0; ni1lOl = 0; niiilO = 0; niiiOi = 0; niiiOl = 0; niiiOO = 0; niil0i = 0; niil0l = 0; niil0O = 0; niil1i = 0; niil1l = 0; niil1O = 0; niilii = 0; niilil = 0; niiliO = 0; niilli = 0; niilll = 0; niillO = 0; niilOi = 0; niilOl = 0; niiO1i = 0; niiO1l = 0; nll00O = 0; nll0ii = 0; end always @ ( posedge clk_2 or negedge wire_ni01O_CLRN) begin if (wire_ni01O_CLRN == 1'b0) begin ni00i <= 0; ni01l <= 0; ni1lOl <= 0; niiilO <= 0; niiiOi <= 0; niiiOl <= 0; niiiOO <= 0; niil0i <= 0; niil0l <= 0; niil0O <= 0; niil1i <= 0; niil1l <= 0; niil1O <= 0; niilii <= 0; niilil <= 0; niiliO <= 0; niilli <= 0; niilll <= 0; niillO <= 0; niilOi <= 0; niilOl <= 0; niiO1i <= 0; niiO1l <= 0; nll00O <= 0; nll0ii <= 0; end else begin ni00i <= wire_nii1O_dataout; ni01l <= wire_nii1l_dataout; ni1lOl <= wire_nil0ii_dataout; niiilO <= wire_nil0il_dataout; niiiOi <= wire_nil0iO_dataout; niiiOl <= wire_nil0li_dataout; niiiOO <= wire_nil0ll_dataout; niil0i <= wire_nil0OO_dataout; niil0l <= wire_nili1i_dataout; niil0O <= wire_nili1l_dataout; niil1i <= wire_nil0lO_dataout; niil1l <= wire_nil0Oi_dataout; niil1O <= wire_nil0Ol_dataout; niilii <= wire_nili1O_dataout; niilil <= wire_nili0i_dataout; niiliO <= wire_nili0l_dataout; niilli <= wire_nili0O_dataout; niilll <= wire_niliii_dataout; niillO <= wire_niliil_dataout; niilOi <= wire_niliiO_dataout; niilOl <= wire_nilili_dataout; niiO1i <= wire_nilill_dataout; niiO1l <= wire_nililO_dataout; nll00O <= wire_nlll0l_dataout; nll0ii <= wire_nlll0O_dataout; end end assign wire_ni01O_CLRN = ((n0OiOi20 ^ n0OiOi19) & (~ soft_reset)); initial begin n11Oi = 0; ni00l = 0; ni00O = 0; ni01i = 0; ni0ii = 0; ni0il = 0; ni0iO = 0; ni0li = 0; ni0ll = 0; ni0lO = 0; ni0Oi = 0; ni0Ol = 0; nii1i = 0; niilOO = 0; niiO0l = 0; niiO0O = 0; niiOii = 0; niiOil = 0; niiOiO = 0; niiOli = 0; niiOll = 0; niiOlO = 0; niiOOi = 0; niiOOl = 0; niiOOO = 0; nil00i = 0; nil00l = 0; nil00O = 0; nil01i = 0; nil01l = 0; nil01O = 0; nil10i = 0; nil10l = 0; nil10O = 0; nil11i = 0; nil11l = 0; nil11O = 0; nil1ii = 0; nil1il = 0; nil1iO = 0; nil1li = 0; nil1ll = 0; nil1lO = 0; nil1Oi = 0; nil1Ol = 0; nil1OO = 0; nl1Oll = 0; nll00l = 0; nll0il = 0; nll0iO = 0; nll0li = 0; nll0ll = 0; nll0lO = 0; nll0Oi = 0; nll0Ol = 0; nll0OO = 0; nlli0i = 0; nlli0l = 0; nlli0O = 0; nlli1i = 0; nlli1l = 0; nlli1O = 0; nlliii = 0; nlliil = 0; nlliiO = 0; nllili = 0; nllill = 0; nllilO = 0; nlliOi = 0; nlliOl = 0; nlliOO = 0; nlll0i = 0; nlll1i = 0; nlll1l = 0; nlll1O = 0; end always @ (clk_2 or wire_ni0OO_PRN or wire_ni0OO_CLRN) begin if (wire_ni0OO_PRN == 1'b0) begin n11Oi <= 1; ni00l <= 1; ni00O <= 1; ni01i <= 1; ni0ii <= 1; ni0il <= 1; ni0iO <= 1; ni0li <= 1; ni0ll <= 1; ni0lO <= 1; ni0Oi <= 1; ni0Ol <= 1; nii1i <= 1; niilOO <= 1; niiO0l <= 1; niiO0O <= 1; niiOii <= 1; niiOil <= 1; niiOiO <= 1; niiOli <= 1; niiOll <= 1; niiOlO <= 1; niiOOi <= 1; niiOOl <= 1; niiOOO <= 1; nil00i <= 1; nil00l <= 1; nil00O <= 1; nil01i <= 1; nil01l <= 1; nil01O <= 1; nil10i <= 1; nil10l <= 1; nil10O <= 1; nil11i <= 1; nil11l <= 1; nil11O <= 1; nil1ii <= 1; nil1il <= 1; nil1iO <= 1; nil1li <= 1; nil1ll <= 1; nil1lO <= 1; nil1Oi <= 1; nil1Ol <= 1; nil1OO <= 1; nl1Oll <= 1; nll00l <= 1; nll0il <= 1; nll0iO <= 1; nll0li <= 1; nll0ll <= 1; nll0lO <= 1; nll0Oi <= 1; nll0Ol <= 1; nll0OO <= 1; nlli0i <= 1; nlli0l <= 1; nlli0O <= 1; nlli1i <= 1; nlli1l <= 1; nlli1O <= 1; nlliii <= 1; nlliil <= 1; nlliiO <= 1; nllili <= 1; nllill <= 1; nllilO <= 1; nlliOi <= 1; nlliOl <= 1; nlliOO <= 1; nlll0i <= 1; nlll1i <= 1; nlll1l <= 1; nlll1O <= 1; end else if (wire_ni0OO_CLRN == 1'b0) begin n11Oi <= 0; ni00l <= 0; ni00O <= 0; ni01i <= 0; ni0ii <= 0; ni0il <= 0; ni0iO <= 0; ni0li <= 0; ni0ll <= 0; ni0lO <= 0; ni0Oi <= 0; ni0Ol <= 0; nii1i <= 0; niilOO <= 0; niiO0l <= 0; niiO0O <= 0; niiOii <= 0; niiOil <= 0; niiOiO <= 0; niiOli <= 0; niiOll <= 0; niiOlO <= 0; niiOOi <= 0; niiOOl <= 0; niiOOO <= 0; nil00i <= 0; nil00l <= 0; nil00O <= 0; nil01i <= 0; nil01l <= 0; nil01O <= 0; nil10i <= 0; nil10l <= 0; nil10O <= 0; nil11i <= 0; nil11l <= 0; nil11O <= 0; nil1ii <= 0; nil1il <= 0; nil1iO <= 0; nil1li <= 0; nil1ll <= 0; nil1lO <= 0; nil1Oi <= 0; nil1Ol <= 0; nil1OO <= 0; nl1Oll <= 0; nll00l <= 0; nll0il <= 0; nll0iO <= 0; nll0li <= 0; nll0ll <= 0; nll0lO <= 0; nll0Oi <= 0; nll0Ol <= 0; nll0OO <= 0; nlli0i <= 0; nlli0l <= 0; nlli0O <= 0; nlli1i <= 0; nlli1l <= 0; nlli1O <= 0; nlliii <= 0; nlliil <= 0; nlliiO <= 0; nllili <= 0; nllill <= 0; nllilO <= 0; nlliOi <= 0; nlliOl <= 0; nlliOO <= 0; nlll0i <= 0; nlll1i <= 0; nlll1l <= 0; nlll1O <= 0; end else if (rbist_clr_rx == 1'b0) if (clk_2 != ni0OO_clk_prev && clk_2 == 1'b1) begin n11Oi <= ni01i; ni00l <= wire_n11ll_o; ni00O <= wire_nii0i_dataout; ni01i <= sync_status; ni0ii <= wire_nii0l_dataout; ni0il <= wire_nii0O_dataout; ni0iO <= wire_niiii_dataout; ni0li <= wire_niiil_dataout; ni0ll <= wire_n101i_o; ni0lO <= wire_n101l_o; ni0Oi <= wire_n101O_o; ni0Ol <= wire_n100i_o; nii1i <= wire_n100l_o; niilOO <= wire_ni1iiO_o; niiO0l <= wire_niO1Oi_dataout; niiO0O <= wire_niO1Ol_dataout; niiOii <= wire_niO1OO_dataout; niiOil <= wire_niO01i_dataout; niiOiO <= wire_niO01l_dataout; niiOli <= wire_niO01O_dataout; niiOll <= wire_niO00i_dataout; niiOlO <= wire_niO10i_dataout; niiOOi <= wire_niO10l_dataout; niiOOl <= wire_niO10O_dataout; niiOOO <= wire_niO1ii_dataout; nil00i <= wire_ni1iOi_o; nil00l <= wire_ni1iOl_o; nil00O <= wire_ni1iOO_o; nil01i <= nil00l; nil01l <= nil00O; nil01O <= wire_ni1ilO_o; nil10i <= wire_niO1ll_dataout; nil10l <= wire_niO00l_dataout; nil10O <= wire_niO00O_dataout; nil11i <= wire_niO1il_dataout; nil11l <= wire_niO1iO_dataout; nil11O <= wire_niO1li_dataout; nil1ii <= wire_niO0ii_dataout; nil1il <= wire_niO0il_dataout; nil1iO <= wire_niO0iO_dataout; nil1li <= wire_niO0li_dataout; nil1ll <= wire_niO0ll_dataout; nil1lO <= wire_niO0lO_dataout; nil1Oi <= wire_niO0Oi_dataout; nil1Ol <= nil01O; nil1OO <= nil00i; nl1Oll <= nll00l; nll00l <= sync_status; nll0il <= wire_nl011i_o; nll0iO <= wire_nlllii_dataout; nll0li <= wire_nlllil_dataout; nll0ll <= wire_nllliO_dataout; nll0lO <= wire_nlllli_dataout; nll0Oi <= wire_nlllll_dataout; nll0Ol <= wire_nllllO_dataout; nll0OO <= wire_nllO0l_dataout; nlli0i <= wire_nllOli_dataout; nlli0l <= wire_nllOll_dataout; nlli0O <= wire_nllOlO_dataout; nlli1i <= wire_nllO0O_dataout; nlli1l <= wire_nllOii_dataout; nlli1O <= wire_nllOiO_dataout; nlliii <= wire_nlO11O_dataout; nlliil <= wire_nlO10i_dataout; nlliiO <= wire_nlO10l_dataout; nllili <= wire_nlO10O_dataout; nllill <= wire_nlO1ii_dataout; nllilO <= wire_nlO1il_dataout; nlliOi <= wire_nlO1iO_dataout; nlliOl <= wire_nlO1li_dataout; nlliOO <= wire_nlO1ll_dataout; nlll0i <= wire_nl01ii_o; nlll1i <= wire_nl010i_o; nlll1l <= wire_nl010l_o; nlll1O <= wire_nl010O_o; end ni0OO_clk_prev <= clk_2; end assign wire_ni0OO_CLRN = ((n0Ol1i16 ^ n0Ol1i15) & (~ soft_reset)), wire_ni0OO_PRN = (n0OiOO18 ^ n0OiOO17); initial begin niiO0i = 0; end always @ (clk_2 or soft_reset or wire_niiO1O_CLRN) begin if (soft_reset == 1'b1) begin niiO0i <= 1; end else if (wire_niiO1O_CLRN == 1'b0) begin niiO0i <= 0; end else if (rbist_clr_rx == 1'b0) if (clk_2 != niiO1O_clk_prev && clk_2 == 1'b1) begin niiO0i <= wire_niO1lO_dataout; end niiO1O_clk_prev <= clk_2; end assign wire_niiO1O_CLRN = (n0li1O48 ^ n0li1O47); event niiO0i_event; initial #1 ->niiO0i_event; always @(niiO0i_event) niiO0i <= 1; or(wire_n000i_dataout, ni01l, (~ n0O01O)); or(wire_n000l_dataout, ni00i, (~ n0O01O)); or(wire_n000O_dataout, wire_n00lO_dataout, (~ n0O01O)); or(wire_n001i_dataout, nii1i, n0Oi1i); and(wire_n001l_dataout, wire_n00ll_dataout, ~((~ n0O01O))); and(wire_n001O_dataout, wire_n0i1l_dataout, ~((~ n0O01O))); assign wire_n00i_dataout = (n0Olll === 1'b1) ? nlll0i : wire_n0iO_dataout; and(wire_n00ii_dataout, wire_n00Oi_dataout, ~((~ n0O01O))); or(wire_n00il_dataout, wire_n00Ol_dataout, (~ n0O01O)); and(wire_n00iO_dataout, wire_n00OO_dataout, ~((~ n0O01O))); and(wire_n00l_dataout, wire_n0li_dataout, ~(n0Olll)); or(wire_n00li_dataout, wire_n0i1i_dataout, (~ n0O01O)); and(wire_n00ll_dataout, (~ n0O00i), n0OlOi); or(wire_n00lO_dataout, wire_n1Oii_dataout, ~(n0OlOi)); and(wire_n00O_dataout, ni0ll, n0OllO); or(wire_n00Oi_dataout, wire_n1Oil_dataout, ~(n0OlOi)); or(wire_n00Ol_dataout, wire_n1OiO_dataout, ~(n0OlOi)); or(wire_n00OO_dataout, wire_n1Oli_dataout, ~(n0OlOi)); and(wire_n010i_dataout, wire_n01iO_dataout, ~(n0OiiO)); and(wire_n010l_dataout, wire_n01li_dataout, ~(n0OiiO)); or(wire_n010O_dataout, wire_n01ll_dataout, n0OiiO); or(wire_n011i_dataout, wire_n010O_dataout, n0Oill); or(wire_n011l_dataout, wire_n01ii_dataout, n0OiiO); and(wire_n011O_dataout, wire_n01il_dataout, ~(n0OiiO)); assign wire_n01i_dataout = (n0Olll === 1'b1) ? nlll1i : wire_n00O_dataout; and(wire_n01ii_dataout, wire_n01lO_dataout, ~(n0Oiil)); or(wire_n01il_dataout, wire_n01Oi_dataout, n0Oiil); and(wire_n01iO_dataout, wire_n01Ol_dataout, ~(n0Oiil)); assign wire_n01l_dataout = (n0Olll === 1'b1) ? nlll1l : wire_n0ii_dataout; and(wire_n01li_dataout, wire_n01OO_dataout, ~(n0Oiil)); or(wire_n01ll_dataout, wire_n001i_dataout, n0Oiil); or(wire_n01lO_dataout, ni0ll, n0Oi1i); assign wire_n01O_dataout = (n0Olll === 1'b1) ? nlll1O : wire_n0il_dataout; or(wire_n01Oi_dataout, ni0lO, n0Oi1i); and(wire_n01Ol_dataout, ni0Oi, ~(n0Oi1i)); and(wire_n01OO_dataout, ni0Ol, ~(n0Oi1i)); assign wire_n0i_dataout = (n0OlOl === 1'b1) ? rxd[33] : rxd[17]; or(wire_n0i0i_dataout, ni00i, (~ n0O00l)); or(wire_n0i0l_dataout, ni01l, (~ n0O00O)); or(wire_n0i0O_dataout, ni00i, (~ n0O00O)); and(wire_n0i1i_dataout, wire_n1Oll_dataout, n0OlOi); and(wire_n0i1l_dataout, n0O00i, n0OlOi); or(wire_n0i1O_dataout, ni01l, (~ n0O00l)); and(wire_n0ii_dataout, ni0lO, n0OllO); or(wire_n0iii_dataout, (~ n0OlOi), (~ n0O00O)); and(wire_n0iil_dataout, n0OlOi, ~((~ n0O00O))); or(wire_n0iiO_dataout, ni01l, (~ n0O0ii)); and(wire_n0il_dataout, ni0Oi, n0OllO); or(wire_n0ili_dataout, ni00i, (~ n0O0ii)); or(wire_n0ill_dataout, ni01l, (~ n0O0il)); or(wire_n0ilO_dataout, ni00i, (~ n0O0il)); and(wire_n0iO_dataout, ni0Ol, n0OllO); or(wire_n0iOi_dataout, (~ n0OlOi), (~ n0O0il)); and(wire_n0iOl_dataout, (~ n0OlOi), ~((~ n0O0il))); or(wire_n0iOO_dataout, n0OlOi, (~ n0O0il)); assign wire_n0l_dataout = (n0OlOl === 1'b1) ? rxd[34] : rxd[18]; or(wire_n0l0i_dataout, ni00i, (~ n0O0li)); or(wire_n0l0l_dataout, (~ n0OlOi), (~ n0O0li)); and(wire_n0l0O_dataout, n0OlOi, ~((~ n0O0li))); or(wire_n0l1i_dataout, ni01l, (~ n0O0iO)); or(wire_n0l1l_dataout, ni00i, (~ n0O0iO)); or(wire_n0l1O_dataout, ni01l, (~ n0O0li)); and(wire_n0li_dataout, nii1i, n0OllO); or(wire_n0lii_dataout, ni01l, (~ n0O0ll)); or(wire_n0lil_dataout, ni00i, (~ n0O0ll)); or(wire_n0liO_dataout, ni01l, (~ n0O0lO)); or(wire_n0lli_dataout, ni00i, (~ n0O0lO)); and(wire_n0lll_dataout, (~ n0OlOi), ~((~ n0O0lO))); or(wire_n0llO_dataout, (~ n0OlOi), (~ n0O0lO)); and(wire_n0lOi_dataout, n0OlOi, ~((~ n0O0lO))); or(wire_n0lOl_dataout, ni01l, (~ n0O0Oi)); or(wire_n0lOO_dataout, ni00i, (~ n0O0Oi)); assign wire_n0O_dataout = (n0OlOl === 1'b1) ? rxd[35] : rxd[19]; and(wire_n0O0i_dataout, n0OlOi, ~((~ n0O0Ol))); and(wire_n0O0l_dataout, ni0ll, ~((~ n0Oi1i))); and(wire_n0O0O_dataout, ni0lO, ~((~ n0Oi1i))); or(wire_n0O1i_dataout, ni01l, (~ n0O0Ol)); or(wire_n0O1l_dataout, ni00i, (~ n0O0Ol)); or(wire_n0O1O_dataout, (~ n0OlOi), (~ n0O0Ol)); and(wire_n0Oi_dataout, ni1lOl, n0Olli); or(wire_n0Oii_dataout, ni0Oi, (~ n0Oi1i)); and(wire_n0Oil_dataout, ni0Ol, ~((~ n0Oi1i))); and(wire_n0OiO_dataout, nii1i, ~((~ n0Oi1i))); and(wire_n0Ol_dataout, niiilO, n0Olli); and(wire_n0Oli_dataout, wire_n0OOO_dataout, ~(n0Oili)); assign wire_n0Oll_dataout = (n0Oili === 1'b1) ? (~ n0OlOi) : wire_ni11i_dataout; assign wire_n0OlO_dataout = (n0Oili === 1'b1) ? n0OlOi : wire_ni11l_dataout; and(wire_n0OO_dataout, niiiOi, n0Olli); and(wire_n0OOi_dataout, wire_ni11O_dataout, ~(n0Oili)); and(wire_n0OOl_dataout, wire_ni10i_dataout, ~(n0Oili)); and(wire_n0OOO_dataout, wire_ni10l_dataout, ~(n0Oi1l)); and(wire_n100O_dataout, ni00i, ~((~ wire_ni_dataout))); and(wire_n10ii_dataout, ni01l, ~((~ wire_ni_dataout))); and(wire_n10il_dataout, ni0ll, ~((~ wire_ni_dataout))); and(wire_n10iO_dataout, ni0lO, ~((~ wire_ni_dataout))); and(wire_n10li_dataout, ni0Oi, ~((~ wire_ni_dataout))); and(wire_n10ll_dataout, ni0Ol, ~((~ wire_ni_dataout))); and(wire_n10lO_dataout, nii1i, ~((~ wire_ni_dataout))); or(wire_n10Oi_dataout, ni00l, ~(n0O1il)); or(wire_n10Ol_dataout, wire_n1i1l_dataout, n0O1il); or(wire_n10OO_dataout, ni00i, n0O1il); or(wire_n1i0i_dataout, ni00l, ~((~ n0O1li))); or(wire_n1i0l_dataout, wire_n1i1l_dataout, (~ n0O1li)); or(wire_n1i0O_dataout, ni00i, (~ n0O1li)); or(wire_n1i1i_dataout, ni00l, n0O1il); or(wire_n1i1l_dataout, ni01l, ni00l); or(wire_n1iii_dataout, ni00l, (~ n0O1li)); or(wire_n1iil_dataout, ni00l, ~((~ n0O1ll))); or(wire_n1iiO_dataout, wire_n1i1l_dataout, (~ n0O1ll)); or(wire_n1ili_dataout, ni00i, (~ n0O1ll)); or(wire_n1ill_dataout, ni00l, (~ n0O1ll)); or(wire_n1ilO_dataout, ni00l, ~((~ n0O1lO))); or(wire_n1iOi_dataout, wire_n1i1l_dataout, (~ n0O1lO)); or(wire_n1iOl_dataout, ni00i, (~ n0O1lO)); or(wire_n1iOO_dataout, ni00l, (~ n0O1lO)); assign wire_n1l_dataout = (n0OlOl === 1'b1) ? rxc[2] : rxc[1]; or(wire_n1l0i_dataout, (~ n0O01i), n0OlOi); or(wire_n1l0l_dataout, wire_n1lll_dataout, ~(n0OlOi)); or(wire_n1l0O_dataout, ni01l, (~ n0O01i)); assign wire_n1l1i_dataout = (n0OlOi === 1'b1) ? wire_n1lil_dataout : ni00l; assign wire_n1l1l_dataout = (n0OlOi === 1'b1) ? wire_n1liO_dataout : wire_n1l0O_dataout; assign wire_n1l1O_dataout = (n0OlOi === 1'b1) ? wire_n1lli_dataout : wire_n1lii_dataout; or(wire_n1lii_dataout, ni00i, (~ n0O01i)); or(wire_n1lil_dataout, ni00l, ~(n0O1Oi)); or(wire_n1liO_dataout, wire_n1i1l_dataout, n0O1Oi); assign wire_n1ll_dataout = (n0Olli === 1'b1) ? nil01O : wire_n01i_dataout; or(wire_n1lli_dataout, ni00i, n0O1Oi); or(wire_n1lll_dataout, ni00l, n0O1Oi); assign wire_n1lO_dataout = (n0Olli === 1'b1) ? nil00i : wire_n01l_dataout; and(wire_n1lOi_dataout, (~ n0O00i), ~((~ n0O01l))); and(wire_n1lOl_dataout, n0O00i, ~((~ n0O01l))); or(wire_n1lOO_dataout, ni01l, (~ n0O01l)); assign wire_n1O_dataout = (n0OlOl === 1'b1) ? rxd[32] : rxd[16]; or(wire_n1O0i_dataout, wire_n1OiO_dataout, (~ n0O01l)); and(wire_n1O0l_dataout, wire_n1Oli_dataout, ~((~ n0O01l))); or(wire_n1O0O_dataout, wire_n1Oll_dataout, (~ n0O01l)); or(wire_n1O1i_dataout, ni00i, (~ n0O01l)); or(wire_n1O1l_dataout, wire_n1Oii_dataout, (~ n0O01l)); and(wire_n1O1O_dataout, wire_n1Oil_dataout, ~((~ n0O01l))); assign wire_n1Oi_dataout = (n0Olli === 1'b1) ? nil00l : wire_n01O_dataout; and(wire_n1Oii_dataout, wire_n1OlO_dataout, n0O00i); and(wire_n1Oil_dataout, wire_n1OOi_dataout, n0O00i); or(wire_n1OiO_dataout, wire_n1OOl_dataout, ~(n0O00i)); assign wire_n1Ol_dataout = (n0Olli === 1'b1) ? nil00O : wire_n00i_dataout; and(wire_n1Oli_dataout, wire_n1OOO_dataout, n0O00i); and(wire_n1Oll_dataout, wire_n011i_dataout, n0O00i); and(wire_n1OlO_dataout, wire_n011l_dataout, ~(n0Oill)); and(wire_n1OO_dataout, wire_n00l_dataout, ~(n0Olli)); and(wire_n1OOi_dataout, wire_n011O_dataout, ~(n0Oill)); and(wire_n1OOl_dataout, wire_n010i_dataout, ~(n0Oill)); and(wire_n1OOO_dataout, wire_n010l_dataout, ~(n0Oill)); and(wire_ni_dataout, rbisten_rx, (((~ rbist_sel[0]) & rbist_sel[1]) & (n0OO1l4 ^ n0OO1l3))); assign wire_ni000i_dataout = (n0OlOi === 1'b1) ? n0l11O : n0l11i; or(wire_ni000l_dataout, niiO1i, n0l11i); or(wire_ni000O_dataout, niiO1l, n0l11i); assign wire_ni001i_dataout = (n0OlOi === 1'b1) ? wire_ni00il_dataout : wire_ni000l_dataout; assign wire_ni001l_dataout = (n0OlOi === 1'b1) ? wire_ni00iO_dataout : wire_ni000O_dataout; or(wire_ni001O_dataout, n0l11i, n0OlOi); or(wire_ni00il_dataout, niiO1i, n0l11O); or(wire_ni00iO_dataout, niiO1l, n0l11O); or(wire_ni00ll_dataout, niiO1i, n0l10l); or(wire_ni00lO_dataout, niiO1l, n0l10l); assign wire_ni00Ol_dataout = (n0OlOi === 1'b1) ? wire_ni0iii_dataout : wire_ni0i0i_dataout; assign wire_ni00OO_dataout = (n0OlOi === 1'b1) ? wire_ni0iil_dataout : wire_ni0i0l_dataout; or(wire_ni010i_dataout, n0iOli, n0OlOi); assign wire_ni010l_dataout = (n0OlOi === 1'b1) ? (~ n0iOlO) : (~ n0iOli); assign wire_ni010O_dataout = (n0OlOi === 1'b1) ? n0iOlO : n0iOli; assign wire_ni011l_dataout = (n0OlOi === 1'b1) ? wire_ni01li_dataout : wire_ni01ii_dataout; assign wire_ni011O_dataout = (n0OlOi === 1'b1) ? wire_ni01ll_dataout : wire_ni01il_dataout; or(wire_ni01ii_dataout, niiO1i, n0iOli); or(wire_ni01il_dataout, niiO1l, n0iOli); or(wire_ni01li_dataout, niiO1i, n0iOlO); or(wire_ni01ll_dataout, niiO1l, n0iOlO); or(wire_ni01Oi_dataout, niiO1i, n0iOOl); or(wire_ni01Ol_dataout, niiO1l, n0iOOl); and(wire_ni0i_dataout, niil1l, n0Olli); or(wire_ni0i0i_dataout, niiO1i, n0l1ii); or(wire_ni0i0l_dataout, niiO1l, n0l1ii); or(wire_ni0i1i_dataout, n0l1ii, n0OlOi); assign wire_ni0i1l_dataout = (n0OlOi === 1'b1) ? (~ n0l1iO) : (~ n0l1ii); assign wire_ni0i1O_dataout = (n0OlOi === 1'b1) ? n0l1iO : n0l1ii; or(wire_ni0iii_dataout, niiO1i, n0l1iO); or(wire_ni0iil_dataout, niiO1l, n0l1iO); or(wire_ni0ili_dataout, niiO1i, n0l1ll); or(wire_ni0ill_dataout, niiO1l, n0l1ll); assign wire_ni0iOi_dataout = (n0OlOi === 1'b1) ? wire_ni0l0l_dataout : wire_ni0l1l_dataout; assign wire_ni0iOl_dataout = (n0OlOi === 1'b1) ? wire_ni0l0O_dataout : wire_ni0l1O_dataout; or(wire_ni0iOO_dataout, n0l1Oi, n0OlOi); and(wire_ni0l_dataout, niil1O, n0Olli); or(wire_ni0l0l_dataout, niiO1i, n0l01i); or(wire_ni0l0O_dataout, niiO1l, n0l01i); assign wire_ni0l1i_dataout = (n0OlOi === 1'b1) ? n0l01i : n0l1Oi; or(wire_ni0l1l_dataout, niiO1i, n0l1Oi); or(wire_ni0l1O_dataout, niiO1l, n0l1Oi); or(wire_ni0lil_dataout, niiO1i, n0l0ii); or(wire_ni0liO_dataout, niiO1l, n0l0ii); or(wire_ni0lli_dataout, wire_ni0lOl_dataout, n0l0ii); and(wire_ni0lll_dataout, wire_ni0lOO_dataout, ~(n0l0ii)); or(wire_ni0llO_dataout, wire_ni0O1i_dataout, n0l0ii); or(wire_ni0lOi_dataout, wire_ni0O1l_dataout, n0l0ii); or(wire_ni0lOl_dataout, wire_ni0O1O_dataout, n0l00l); or(wire_ni0lOO_dataout, wire_ni0O0i_dataout, n0l00l); and(wire_ni0O_dataout, niil0i, n0Olli); or(wire_ni0O0i_dataout, nil00i, n0l00i); and(wire_ni0O0l_dataout, nil00l, ~(n0l00i)); and(wire_ni0O0O_dataout, nil00O, ~(n0l00i)); and(wire_ni0O1i_dataout, wire_ni0O0l_dataout, ~(n0l00l)); and(wire_ni0O1l_dataout, wire_ni0O0O_dataout, ~(n0l00l)); or(wire_ni0O1O_dataout, nil01O, n0l00i); or(wire_ni0OiO_dataout, wire_nii11i_dataout, n0l0Ol); or(wire_ni0Oli_dataout, niiO1i, n0l0Ol); or(wire_ni0Oll_dataout, niiO1l, n0l0Ol); or(wire_ni0OlO_dataout, wire_nii11l_dataout, n0l0Ol); and(wire_ni0OOi_dataout, wire_nii11O_dataout, ~(n0l0Ol)); or(wire_ni0OOl_dataout, wire_nii10i_dataout, n0l0Ol); or(wire_ni0OOO_dataout, wire_nii10l_dataout, n0l0Ol); and(wire_ni10i_dataout, wire_ni1iO_dataout, ~(n0Oi1l)); assign wire_ni10l_dataout = (n0O0OO === 1'b1) ? (~ n0OlOi) : ni0ll; assign wire_ni10O_dataout = (n0O0OO === 1'b1) ? (~ n0OlOi) : ni0lO; assign wire_ni11i_dataout = (n0Oi1l === 1'b1) ? (~ n0OlOi) : wire_ni10O_dataout; assign wire_ni11l_dataout = (n0Oi1l === 1'b1) ? n0OlOi : wire_ni1ii_dataout; and(wire_ni11O_dataout, wire_ni1il_dataout, ~(n0Oi1l)); and(wire_ni1i_dataout, niiiOl, n0Olli); assign wire_ni1ii_dataout = (n0O0OO === 1'b1) ? n0OlOi : ni0Oi; and(wire_ni1il_dataout, ni0Ol, ~(n0O0OO)); and(wire_ni1iO_dataout, nii1i, ~(n0O0OO)); and(wire_ni1l_dataout, niiiOO, n0Olli); and(wire_ni1l0i_dataout, nil01O, ~((~ wire_nO_dataout))); and(wire_ni1l0l_dataout, nil00i, ~((~ wire_nO_dataout))); and(wire_ni1l0O_dataout, nil00l, ~((~ wire_nO_dataout))); and(wire_ni1l1i_dataout, niilOO, ~((~ wire_nO_dataout))); and(wire_ni1l1l_dataout, niiO1i, ~((~ wire_nO_dataout))); and(wire_ni1l1O_dataout, niiO1l, ~((~ wire_nO_dataout))); and(wire_ni1lii_dataout, nil00O, ~((~ wire_nO_dataout))); or(wire_ni1lil_dataout, niilOO, ~(n0iO1l)); or(wire_ni1liO_dataout, niiO1i, n0iO1l); or(wire_ni1lli_dataout, wire_ni1llO_dataout, n0iO1l); or(wire_ni1lll_dataout, niilOO, n0iO1l); or(wire_ni1llO_dataout, niiO1l, niilOO); assign wire_ni1lOO_dataout = (n0OlOi === 1'b1) ? wire_ni1OiO_dataout : niilOO; and(wire_ni1O_dataout, niil1i, n0Olli); or(wire_ni1O0i_dataout, n0iO0i, n0OlOi); or(wire_ni1O0l_dataout, wire_ni1OlO_dataout, ~(n0OlOi)); or(wire_ni1O0O_dataout, niiO1i, n0iO0i); assign wire_ni1O1i_dataout = (n0OlOi === 1'b1) ? n0iO0O : n0iO0i; assign wire_ni1O1l_dataout = (n0OlOi === 1'b1) ? wire_ni1Oli_dataout : wire_ni1O0O_dataout; assign wire_ni1O1O_dataout = (n0OlOi === 1'b1) ? wire_ni1Oll_dataout : wire_ni1Oii_dataout; or(wire_ni1Oii_dataout, niiO1l, n0iO0i); or(wire_ni1OiO_dataout, niilOO, ~(n0iO0O)); or(wire_ni1Oli_dataout, niiO1i, n0iO0O); or(wire_ni1Oll_dataout, wire_ni1llO_dataout, n0iO0O); or(wire_ni1OlO_dataout, niilOO, n0iO0O); or(wire_ni1OOl_dataout, niiO1i, n0iOil); or(wire_ni1OOO_dataout, niiO1l, n0iOil); assign wire_nii_dataout = (n0OlOl === 1'b1) ? rxd[36] : rxd[20]; or(wire_nii00i_dataout, nil01O, n0li1l); and(wire_nii00l_dataout, nil00i, ~(n0li1l)); and(wire_nii00O_dataout, nil00l, ~(n0li1l)); assign wire_nii0i_dataout = (wire_n11ii_o === 1'b1) ? wire_niiOl_o[0] : wire_niiiO_dataout; and(wire_nii0ii_dataout, nil00O, ~(n0li1l)); assign wire_nii0l_dataout = (wire_n11ii_o === 1'b1) ? wire_niiOl_o[1] : wire_niili_dataout; or(wire_nii0ll_dataout, wire_niOi0i_dataout, ~(wire_nii0Ol_o[2])); assign wire_nii0O_dataout = (wire_n11ii_o === 1'b1) ? wire_niiOl_o[2] : wire_niill_dataout; or(wire_nii0Oi_dataout, wire_niOi0O_dataout, ~(wire_nii0Ol_o[2])); and(wire_nii10i_dataout, wire_nii1il_dataout, ~(n0l0ll)); and(wire_nii10l_dataout, wire_nii1iO_dataout, ~(n0l0ll)); and(wire_nii10O_dataout, nil01O, ~(n0l0iO)); and(wire_nii11i_dataout, (~ n0l0iO), ~(n0l0ll)); and(wire_nii11l_dataout, wire_nii10O_dataout, ~(n0l0ll)); or(wire_nii11O_dataout, wire_nii1ii_dataout, n0l0ll); or(wire_nii1ii_dataout, nil00i, n0l0iO); and(wire_nii1il_dataout, nil00l, ~(n0l0iO)); and(wire_nii1iO_dataout, nil00O, ~(n0l0iO)); and(wire_nii1l_dataout, wire_n11OO_o, ~(rbist_clr_rx)); and(wire_nii1O_dataout, wire_n11Ol_o, ~(rbist_clr_rx)); and(wire_niii_dataout, niil0l, n0Olli); assign wire_niiii_dataout = (wire_n11ii_o === 1'b1) ? wire_niiOl_o[3] : wire_niilO_dataout; assign wire_niiil_dataout = (wire_n11ii_o === 1'b1) ? wire_niiOl_o[4] : wire_niiOi_dataout; and(wire_niiiO_dataout, ni00O, ~(wire_n11il_o)); and(wire_niil_dataout, niil0O, n0Olli); and(wire_niili_dataout, ni0ii, ~(wire_n11il_o)); and(wire_niill_dataout, ni0il, ~(wire_n11il_o)); and(wire_niilO_dataout, ni0iO, ~(wire_n11il_o)); and(wire_niiO_dataout, niilii, n0Olli); and(wire_niiOi_dataout, ni0li, ~(wire_n11il_o)); assign wire_nil_dataout = (n0OlOl === 1'b1) ? rxd[37] : rxd[21]; and(wire_nil0ii_dataout, wire_niliOi_dataout, ~(rbist_clr_rx)); and(wire_nil0il_dataout, wire_niliOl_dataout, ~(rbist_clr_rx)); and(wire_nil0iO_dataout, wire_niliOO_dataout, ~(rbist_clr_rx)); and(wire_nil0li_dataout, wire_nill1i_dataout, ~(rbist_clr_rx)); and(wire_nil0ll_dataout, wire_nill1l_dataout, ~(rbist_clr_rx)); and(wire_nil0lO_dataout, wire_nill1O_dataout, ~(rbist_clr_rx)); and(wire_nil0Oi_dataout, wire_nill0i_dataout, ~(rbist_clr_rx)); and(wire_nil0Ol_dataout, wire_nill0l_dataout, ~(rbist_clr_rx)); and(wire_nil0OO_dataout, wire_nill0O_dataout, ~(rbist_clr_rx)); and(wire_nili_dataout, niilil, n0Olli); and(wire_nili0i_dataout, wire_nillli_dataout, ~(rbist_clr_rx)); and(wire_nili0l_dataout, wire_nillll_dataout, ~(rbist_clr_rx)); and(wire_nili0O_dataout, wire_nilllO_dataout, ~(rbist_clr_rx)); and(wire_nili1i_dataout, wire_nillii_dataout, ~(rbist_clr_rx)); and(wire_nili1l_dataout, wire_nillil_dataout, ~(rbist_clr_rx)); and(wire_nili1O_dataout, wire_nilliO_dataout, ~(rbist_clr_rx)); and(wire_niliii_dataout, wire_nillOi_dataout, ~(rbist_clr_rx)); and(wire_niliil_dataout, wire_nillOl_dataout, ~(rbist_clr_rx)); and(wire_niliiO_dataout, wire_nillOO_dataout, ~(rbist_clr_rx)); and(wire_nilili_dataout, wire_ni1iil_o, ~(rbist_clr_rx)); and(wire_nilill_dataout, wire_ni1ili_o, ~(rbist_clr_rx)); and(wire_nililO_dataout, wire_ni1ill_o, ~(rbist_clr_rx)); and(wire_niliOi_dataout, wire_nilO1i_dataout, ~((~ wire_nO_dataout))); and(wire_niliOl_dataout, wire_nilO1l_dataout, ~((~ wire_nO_dataout))); and(wire_niliOO_dataout, wire_nilO1O_dataout, ~((~ wire_nO_dataout))); and(wire_nill_dataout, niiliO, n0Olli); and(wire_nill0i_dataout, wire_nilOii_dataout, ~((~ wire_nO_dataout))); and(wire_nill0l_dataout, wire_nilOil_dataout, ~((~ wire_nO_dataout))); and(wire_nill0O_dataout, wire_nilOiO_dataout, ~((~ wire_nO_dataout))); and(wire_nill1i_dataout, wire_nilO0i_dataout, ~((~ wire_nO_dataout))); and(wire_nill1l_dataout, wire_nilO0l_dataout, ~((~ wire_nO_dataout))); and(wire_nill1O_dataout, wire_nilO0O_dataout, ~((~ wire_nO_dataout))); and(wire_nillii_dataout, wire_nilOli_dataout, ~((~ wire_nO_dataout))); and(wire_nillil_dataout, wire_nilOll_dataout, ~((~ wire_nO_dataout))); and(wire_nilliO_dataout, wire_nilOlO_dataout, ~((~ wire_nO_dataout))); and(wire_nillli_dataout, wire_nilOOi_dataout, ~((~ wire_nO_dataout))); and(wire_nillll_dataout, wire_nilOOl_dataout, ~((~ wire_nO_dataout))); and(wire_nilllO_dataout, wire_nilOOO_dataout, ~((~ wire_nO_dataout))); and(wire_nillOi_dataout, wire_niO11i_dataout, ~((~ wire_nO_dataout))); and(wire_nillOl_dataout, wire_niO11l_dataout, ~((~ wire_nO_dataout))); and(wire_nillOO_dataout, wire_niO11O_dataout, ~((~ wire_nO_dataout))); and(wire_nilO_dataout, niilli, n0Olli); assign wire_nilO0i_dataout = (niilOl === 1'b1) ? wire_nii0lO_o : niiiOl; assign wire_nilO0l_dataout = (niilOl === 1'b1) ? wire_nii0Oi_dataout : niiiOO; assign wire_nilO0O_dataout = (niilOl === 1'b1) ? wire_nii0OO_o : niil1i; assign wire_nilO1i_dataout = (niilOl === 1'b1) ? wire_nii0iO_o : ni1lOl; assign wire_nilO1l_dataout = (niilOl === 1'b1) ? wire_nii0li_o : niiilO; assign wire_nilO1O_dataout = (niilOl === 1'b1) ? wire_nii0ll_dataout : niiiOi; assign wire_nilOii_dataout = (niilOl === 1'b1) ? wire_niii1i_o : niil1l; assign wire_nilOil_dataout = (niilOl === 1'b1) ? wire_niii1l_o : niil1O; assign wire_nilOiO_dataout = (niilOl === 1'b1) ? wire_niii1O_o : niil0i; assign wire_nilOli_dataout = (niilOl === 1'b1) ? wire_niii0i_o : niil0l; assign wire_nilOll_dataout = (niilOl === 1'b1) ? wire_niii0l_o : niil0O; assign wire_nilOlO_dataout = (niilOl === 1'b1) ? wire_niii0O_o : niilii; assign wire_nilOOi_dataout = (niilOl === 1'b1) ? wire_niiiii_o : niilil; assign wire_nilOOl_dataout = (niilOl === 1'b1) ? wire_niiiil_o : niiliO; assign wire_nilOOO_dataout = (niilOl === 1'b1) ? wire_niiiiO_o : niilli; assign wire_niO_dataout = (n0OlOl === 1'b1) ? rxd[38] : rxd[22]; and(wire_niO00i_dataout, wire_niO0OO_o[6], wire_ni1i0l_o); and(wire_niO00l_dataout, wire_niOi1i_o[0], wire_ni1i0l_o); and(wire_niO00O_dataout, wire_niOi1i_o[1], wire_ni1i0l_o); and(wire_niO01i_dataout, wire_niO0OO_o[3], wire_ni1i0l_o); and(wire_niO01l_dataout, wire_niO0OO_o[4], wire_ni1i0l_o); and(wire_niO01O_dataout, wire_niO0OO_o[5], wire_ni1i0l_o); and(wire_niO0ii_dataout, wire_niOi1i_o[2], wire_ni1i0l_o); and(wire_niO0il_dataout, wire_niOi1i_o[3], wire_ni1i0l_o); and(wire_niO0iO_dataout, wire_niOi1i_o[4], wire_ni1i0l_o); and(wire_niO0li_dataout, wire_niOi1i_o[5], wire_ni1i0l_o); and(wire_niO0ll_dataout, wire_niOi1i_o[6], wire_ni1i0l_o); and(wire_niO0lO_dataout, wire_niOi1i_o[7], wire_ni1i0l_o); and(wire_niO0Oi_dataout, wire_niOi1i_o[8], wire_ni1i0l_o); and(wire_niO10i_dataout, niiOlO, wire_ni1i0l_o); and(wire_niO10l_dataout, wire_niO0Ol_o[0], wire_ni1i0l_o); and(wire_niO10O_dataout, wire_niO0Ol_o[1], wire_ni1i0l_o); assign wire_niO11i_dataout = (niilOl === 1'b1) ? wire_niiili_o : niilll; assign wire_niO11l_dataout = (niilOl === 1'b1) ? (~ wire_nii0Ol_o[2]) : niillO; assign wire_niO11O_dataout = (niilOl === 1'b1) ? wire_niiill_o : niilOi; and(wire_niO1ii_dataout, wire_niO0Ol_o[2], wire_ni1i0l_o); and(wire_niO1il_dataout, wire_niO0Ol_o[3], wire_ni1i0l_o); and(wire_niO1iO_dataout, wire_niO0Ol_o[4], wire_ni1i0l_o); and(wire_niO1li_dataout, wire_niO0Ol_o[5], wire_ni1i0l_o); and(wire_niO1ll_dataout, wire_niO0Ol_o[6], wire_ni1i0l_o); or(wire_niO1lO_dataout, niiO0i, ~(wire_ni1i0l_o)); and(wire_niO1Oi_dataout, wire_niO0OO_o[0], wire_ni1i0l_o); and(wire_niO1Ol_dataout, wire_niO0OO_o[1], wire_ni1i0l_o); and(wire_niO1OO_dataout, wire_niO0OO_o[2], wire_ni1i0l_o); and(wire_niOi_dataout, niilll, n0Olli); assign wire_niOi0i_dataout = (n0OlOi === 1'b1) ? niiOOl : nil1ii; assign wire_niOi0l_dataout = (n0OlOi === 1'b1) ? niiOOO : nil1il; assign wire_niOi0O_dataout = (n0OlOi === 1'b1) ? nil11i : nil1iO; assign wire_niOi1l_dataout = (n0OlOi === 1'b1) ? niiOlO : nil10l; assign wire_niOi1O_dataout = (n0OlOi === 1'b1) ? niiOOi : nil10O; assign wire_niOiii_dataout = (n0OlOi === 1'b1) ? nil11l : nil1li; assign wire_niOiil_dataout = (n0OlOi === 1'b1) ? nil11O : nil1ll; assign wire_niOiiO_dataout = (n0OlOi === 1'b1) ? nil10i : nil1lO; and(wire_niOili_dataout, niiO0i, n0OlOi); and(wire_niOill_dataout, niiO0l, n0OlOi); and(wire_niOilO_dataout, niiO0O, n0OlOi); and(wire_niOiOi_dataout, niiOii, n0OlOi); and(wire_niOiOl_dataout, niiOil, n0OlOi); and(wire_niOiOO_dataout, niiOiO, n0OlOi); and(wire_niOl_dataout, niillO, n0Olli); and(wire_niOl1i_dataout, niiOli, n0OlOi); and(wire_niOl1l_dataout, niiOll, n0OlOi); and(wire_niOO_dataout, niilOi, n0Olli); and(wire_nl_dataout, rbisten_rx, (rbist_sel[0] & (~ rbist_sel[1]))); or(wire_nl000l_dataout, nll0il, ~((~ n0li0O))); or(wire_nl000O_dataout, wire_nl001O_dataout, (~ n0li0O)); or(wire_nl001i_dataout, nll0ii, n0li0i); or(wire_nl001l_dataout, nll0il, n0li0i); or(wire_nl001O_dataout, nll00O, nll0il); or(wire_nl00ii_dataout, nll0ii, (~ n0li0O)); or(wire_nl00il_dataout, nll0il, (~ n0li0O)); or(wire_nl00iO_dataout, nll0il, ~((~ n0liii))); or(wire_nl00li_dataout, wire_nl001O_dataout, (~ n0liii)); or(wire_nl00ll_dataout, nll0ii, (~ n0liii)); or(wire_nl00lO_dataout, nll0il, (~ n0liii)); or(wire_nl00Oi_dataout, nll0il, ~((~ n0liil))); or(wire_nl00Ol_dataout, wire_nl001O_dataout, (~ n0liil)); or(wire_nl00OO_dataout, nll0ii, (~ n0liil)); and(wire_nl01il_dataout, nll0ii, ~((~ wire_nl_dataout))); and(wire_nl01iO_dataout, nll00O, ~((~ wire_nl_dataout))); and(wire_nl01li_dataout, nlll1i, ~((~ wire_nl_dataout))); and(wire_nl01ll_dataout, nlll1l, ~((~ wire_nl_dataout))); and(wire_nl01lO_dataout, nlll1O, ~((~ wire_nl_dataout))); and(wire_nl01Oi_dataout, nlll0i, ~((~ wire_nl_dataout))); or(wire_nl01Ol_dataout, nll0il, ~(n0li0i)); or(wire_nl01OO_dataout, wire_nl001O_dataout, n0li0i); assign wire_nl0i_dataout = (n0Olll === 1'b1) ? nll00O : wire_nl0O_dataout; assign wire_nl0i0i_dataout = (n0OlOi === 1'b1) ? wire_nl0ill_dataout : wire_nl0iil_dataout; or(wire_nl0i0l_dataout, (~ n0lili), n0OlOi); or(wire_nl0i0O_dataout, wire_nl0ilO_dataout, ~(n0OlOi)); or(wire_nl0i1i_dataout, nll0il, (~ n0liil)); assign wire_nl0i1l_dataout = (n0OlOi === 1'b1) ? wire_nl0iiO_dataout : nll0il; assign wire_nl0i1O_dataout = (n0OlOi === 1'b1) ? wire_nl0ili_dataout : wire_nl0iii_dataout; or(wire_nl0iii_dataout, nll00O, (~ n0lili)); or(wire_nl0iil_dataout, nll0ii, (~ n0lili)); or(wire_nl0iiO_dataout, nll0il, ~(n0liiO)); or(wire_nl0ili_dataout, wire_nl001O_dataout, n0liiO); or(wire_nl0ill_dataout, nll0ii, n0liiO); or(wire_nl0ilO_dataout, nll0il, n0liiO); and(wire_nl0iOl_dataout, wire_nl0l0O_dataout, ~((~ n0lill))); and(wire_nl0iOO_dataout, wire_nl0l0l_dataout, ~((~ n0lill))); and(wire_nl0l_dataout, ni00i, n0OllO); or(wire_nl0l0i_dataout, wire_nl0l0O_dataout, (~ n0lill)); assign wire_nl0l0l_dataout = (n0OlOi === 1'b1) ? n0lilO : n0liOi; assign wire_nl0l0O_dataout = (n0OlOi === 1'b1) ? (~ n0lilO) : (~ n0liOi); or(wire_nl0l1i_dataout, nll00O, (~ n0lill)); or(wire_nl0l1l_dataout, nll0ii, (~ n0lill)); or(wire_nl0l1O_dataout, wire_nl0l0l_dataout, (~ n0lill)); or(wire_nl0lii_dataout, nll00O, (~ n0liOl)); or(wire_nl0lil_dataout, nll0ii, (~ n0liOl)); and(wire_nl0liO_dataout, n0OlOi, ~((~ n0liOO))); or(wire_nl0lli_dataout, nll00O, (~ n0liOO)); or(wire_nl0lll_dataout, nll0ii, (~ n0liOO)); or(wire_nl0llO_dataout, wire_nl0O1i_dataout, (~ n0liOO)); or(wire_nl0lOi_dataout, wire_nl0O1l_dataout, (~ n0liOO)); or(wire_nl0lOl_dataout, wire_nl0O1O_dataout, (~ n0liOO)); or(wire_nl0lOO_dataout, wire_nl0O0i_dataout, (~ n0liOO)); and(wire_nl0O_dataout, ni01l, n0OllO); and(wire_nl0O0i_dataout, wire_nl0Oil_dataout, n0OlOi); or(wire_nl0O0l_dataout, wire_nl0OiO_dataout, n0ll1i); and(wire_nl0O0O_dataout, wire_nl0Oli_dataout, ~(n0ll1i)); and(wire_nl0O1i_dataout, wire_nl0O0l_dataout, n0OlOi); or(wire_nl0O1l_dataout, wire_nl0O0O_dataout, ~(n0OlOi)); or(wire_nl0O1O_dataout, wire_nl0Oii_dataout, ~(n0OlOi)); or(wire_nl0Oii_dataout, wire_nl0Oll_dataout, n0ll1i); and(wire_nl0Oil_dataout, wire_nl0OlO_dataout, ~(n0ll1i)); or(wire_nl0OiO_dataout, wire_nl0OOi_dataout, ~(n0ll1l)); or(wire_nl0Oli_dataout, wire_nl0OOl_dataout, ~(n0ll1l)); or(wire_nl0Oll_dataout, wire_nl0OOO_dataout, ~(n0ll1l)); and(wire_nl0OlO_dataout, wire_nli11i_dataout, n0ll1l); and(wire_nl0OOi_dataout, wire_nli11l_dataout, ~(n0lOiO)); or(wire_nl0OOl_dataout, wire_nli11O_dataout, n0lOiO); and(wire_nl0OOO_dataout, wire_nli10i_dataout, ~(n0lOiO)); assign wire_nl1i_dataout = (n0Olli === 1'b1) ? niiO1i : wire_nl1O_dataout; assign wire_nl1l_dataout = (n0Olli === 1'b1) ? niiO1l : wire_nl0i_dataout; assign wire_nl1O_dataout = (n0Olll === 1'b1) ? nll0ii : wire_nl0l_dataout; and(wire_nl1Oii_dataout, wire_nliill_dataout, wire_nl1OiO_o[5]); and(wire_nl1Oil_dataout, n0llil, wire_nl1OiO_o[5]); and(wire_nl1Oli_dataout, wire_nli1Ol_dataout, wire_nl1OiO_o[6]); and(wire_nl1OlO_dataout, wire_nli1OO_dataout, wire_nl1OiO_o[6]); and(wire_nl1OOi_dataout, wire_nl0liO_dataout, wire_nl1OiO_o[7]); and(wire_nl1OOl_dataout, wire_nl0iOl_dataout, wire_nl1OiO_o[8]); and(wire_nl1OOO_dataout, wire_nl0iOO_dataout, wire_nl1OiO_o[8]); assign wire_nli_dataout = (n0OlOl === 1'b1) ? rxd[39] : rxd[23]; or(wire_nli00i_dataout, wire_nli0li_dataout, (~ n0ll1O)); or(wire_nli00l_dataout, wire_nli0ll_dataout, (~ n0ll1O)); or(wire_nli00O_dataout, wire_nli0lO_dataout, (~ n0ll1O)); or(wire_nli01i_dataout, nll00O, (~ n0ll1O)); or(wire_nli01l_dataout, nll0ii, (~ n0ll1O)); or(wire_nli01O_dataout, wire_nli0iO_dataout, (~ n0ll1O)); or(wire_nli0ii_dataout, (~ n0ll0i), ~(n0OlOi)); and(wire_nli0il_dataout, n0ll0i, n0OlOi); assign wire_nli0iO_dataout = (n0OlOi === 1'b1) ? n0ll0i : wire_nli0Oi_dataout; assign wire_nli0li_dataout = (n0OlOi === 1'b1) ? (~ n0ll0i) : wire_nli0Ol_dataout; assign wire_nli0ll_dataout = (n0OlOi === 1'b1) ? (~ n0ll0i) : wire_nli0OO_dataout; assign wire_nli0lO_dataout = (n0OlOi === 1'b1) ? n0ll0i : wire_nlii1i_dataout; or(wire_nli0Oi_dataout, wire_nlii1l_dataout, n0llii); and(wire_nli0Ol_dataout, wire_nlii1O_dataout, ~(n0llii)); and(wire_nli0OO_dataout, wire_nlii0i_dataout, ~(n0llii)); and(wire_nli10i_dataout, wire_nli1il_dataout, ~(n0lO1l)); or(wire_nli10l_dataout, wire_nli1iO_dataout, n0lO1l); and(wire_nli10O_dataout, wire_nli1li_dataout, ~(n0lO1i)); or(wire_nli11i_dataout, wire_nli10l_dataout, n0lOiO); or(wire_nli11l_dataout, wire_nli10O_dataout, n0lO1l); or(wire_nli11O_dataout, wire_nli1ii_dataout, n0lO1l); and(wire_nli1ii_dataout, wire_nli1ll_dataout, ~(n0lO1i)); or(wire_nli1il_dataout, wire_nli1lO_dataout, n0lO1i); or(wire_nli1iO_dataout, wire_nli1Oi_dataout, n0lO1i); or(wire_nli1li_dataout, nlll1i, n0lO0i); and(wire_nli1ll_dataout, nlll1l, ~(n0lO0i)); or(wire_nli1lO_dataout, nlll1O, n0lO0i); or(wire_nli1Oi_dataout, nlll0i, n0lO0i); and(wire_nli1Ol_dataout, wire_nli0ii_dataout, ~((~ n0ll1O))); and(wire_nli1OO_dataout, wire_nli0il_dataout, ~((~ n0ll1O))); and(wire_nlii_dataout, wire_n1l_dataout, n0OlOi); or(wire_nlii0i_dataout, wire_nliiil_dataout, n0ll0l); and(wire_nlii0l_dataout, wire_nliiiO_dataout, ~(n0ll0l)); or(wire_nlii0O_dataout, wire_nl0OOi_dataout, ~(n0ll0O)); or(wire_nlii1i_dataout, wire_nlii0l_dataout, n0llii); or(wire_nlii1l_dataout, wire_nlii0O_dataout, n0ll0l); and(wire_nlii1O_dataout, wire_nliiii_dataout, ~(n0ll0l)); or(wire_nliiii_dataout, wire_nl0OOl_dataout, ~(n0ll0O)); or(wire_nliiil_dataout, wire_nl0OOO_dataout, ~(n0ll0O)); and(wire_nliiiO_dataout, wire_nli11i_dataout, n0ll0O); and(wire_nliill_dataout, wire_nlil1i_dataout, ~((~ n0llil))); or(wire_nliilO_dataout, nll00O, (~ n0llil)); or(wire_nliiOi_dataout, nll0ii, (~ n0llil)); or(wire_nliiOl_dataout, wire_nlil1l_dataout, (~ n0llil)); or(wire_nliiOO_dataout, wire_nlil1O_dataout, (~ n0llil)); and(wire_nlil_dataout, wire_n1O_dataout, n0OlOi); assign wire_nlil0i_dataout = (n0OlOi === 1'b1) ? wire_nlilli_dataout : wire_nlilii_dataout; assign wire_nlil0l_dataout = (n0OlOi === 1'b1) ? wire_nlilll_dataout : wire_nlilil_dataout; assign wire_nlil0O_dataout = (n0OlOi === 1'b1) ? wire_nlillO_dataout : wire_nliliO_dataout; assign wire_nlil1i_dataout = (n0lOiO === 1'b1) ? wire_nlilOi_dataout : wire_nlil0i_dataout; assign wire_nlil1l_dataout = (n0lOiO === 1'b1) ? wire_nlilOl_dataout : wire_nlil0l_dataout; assign wire_nlil1O_dataout = (n0lOiO === 1'b1) ? wire_nlilOO_dataout : wire_nlil0O_dataout; and(wire_nlilii_dataout, n0lliO, ~(n0llll)); and(wire_nlilil_dataout, (~ n0lliO), ~(n0llll)); or(wire_nliliO_dataout, n0lliO, n0llll); and(wire_nlilli_dataout, n0llll, ~(n0llli)); and(wire_nlilll_dataout, (~ n0llll), ~(n0llli)); or(wire_nlillO_dataout, n0llll, n0llli); assign wire_nlilOi_dataout = (n0OlOi === 1'b1) ? wire_nliO0i_dataout : wire_nliO1i_dataout; assign wire_nlilOl_dataout = (n0OlOi === 1'b1) ? wire_nliO0l_dataout : wire_nliO1l_dataout; assign wire_nlilOO_dataout = (n0OlOi === 1'b1) ? wire_nliO0O_dataout : wire_nliO1O_dataout; and(wire_nliO_dataout, wire_n0i_dataout, n0OlOi); and(wire_nliO0i_dataout, n0llOl, ~(n0llOi)); and(wire_nliO0l_dataout, (~ n0llOl), ~(n0llOi)); or(wire_nliO0O_dataout, n0llOl, n0llOi); and(wire_nliO1i_dataout, n0lllO, ~(n0llOl)); and(wire_nliO1l_dataout, (~ n0lllO), ~(n0llOl)); or(wire_nliO1O_dataout, n0lllO, n0llOl); or(wire_nliOii_dataout, nll00O, (~ n0llOO)); or(wire_nliOil_dataout, nll0ii, (~ n0llOO)); and(wire_nliOiO_dataout, wire_nliOOi_dataout, ~(n0lOiO)); and(wire_nliOli_dataout, wire_nliOOl_dataout, ~(n0lOiO)); or(wire_nliOll_dataout, wire_nliOOO_dataout, n0lOiO); and(wire_nliOlO_dataout, wire_nll11i_dataout, ~(n0lOiO)); or(wire_nliOOi_dataout, nlll1i, n0lOii); and(wire_nliOOl_dataout, nlll1l, ~(n0lOii)); or(wire_nliOOO_dataout, nlll1O, n0lOii); assign wire_nll10i_dataout = (n0lOil === 1'b1) ? (~ n0OlOi) : wire_nll1il_dataout; assign wire_nll10l_dataout = (n0lOil === 1'b1) ? n0OlOi : wire_nll1iO_dataout; and(wire_nll10O_dataout, wire_nll1li_dataout, ~(n0lOil)); and(wire_nll11i_dataout, nlll0i, ~(n0lOii)); and(wire_nll11O_dataout, wire_nll1ii_dataout, ~(n0lOil)); assign wire_nll1ii_dataout = (n0lO0l === 1'b1) ? n0OlOi : wire_nll1ll_dataout; assign wire_nll1il_dataout = (n0lO0l === 1'b1) ? (~ n0OlOi) : wire_nll1lO_dataout; assign wire_nll1iO_dataout = (n0lO0l === 1'b1) ? n0OlOi : wire_nll1Oi_dataout; and(wire_nll1li_dataout, wire_nll1Ol_dataout, ~(n0lO0l)); or(wire_nll1ll_dataout, nlll1i, n0lO1O); assign wire_nll1lO_dataout = (n0lO1O === 1'b1) ? (~ n0OlOi) : nlll1l; assign wire_nll1Oi_dataout = (n0lO1O === 1'b1) ? n0OlOi : nlll1O; and(wire_nll1Ol_dataout, nlll0i, ~(n0lO1O)); and(wire_nlli_dataout, wire_n0l_dataout, n0OlOi); and(wire_nlll_dataout, wire_n0O_dataout, n0OlOi); and(wire_nlll0l_dataout, wire_nl011O_o, ~(rbist_clr_rx)); and(wire_nlll0O_dataout, wire_nl011l_o, ~(rbist_clr_rx)); assign wire_nlllii_dataout = (wire_nl1OOl_dataout === 1'b1) ? wire_nllO0i_o[0] : wire_nlllOi_dataout; assign wire_nlllil_dataout = (wire_nl1OOl_dataout === 1'b1) ? wire_nllO0i_o[1] : wire_nlllOl_dataout; assign wire_nllliO_dataout = (wire_nl1OOl_dataout === 1'b1) ? wire_nllO0i_o[2] : wire_nlllOO_dataout; assign wire_nlllli_dataout = (wire_nl1OOl_dataout === 1'b1) ? wire_nllO0i_o[3] : wire_nllO1i_dataout; assign wire_nlllll_dataout = (wire_nl1OOl_dataout === 1'b1) ? wire_nllO0i_o[4] : wire_nllO1l_dataout; assign wire_nllllO_dataout = (wire_nl1OOl_dataout === 1'b1) ? wire_nllO0i_o[5] : wire_nllO1O_dataout; and(wire_nlllOi_dataout, nll0iO, ~(wire_nl1OOO_dataout)); and(wire_nlllOl_dataout, nll0li, ~(wire_nl1OOO_dataout)); and(wire_nlllOO_dataout, nll0ll, ~(wire_nl1OOO_dataout)); and(wire_nllO_dataout, wire_nii_dataout, n0OlOi); assign wire_nllO0l_dataout = (wire_nl1OOi_dataout === 1'b1) ? wire_nllOil_o[0] : nll0OO; assign wire_nllO0O_dataout = (wire_nl1OOi_dataout === 1'b1) ? wire_nllOil_o[1] : nlli1i; and(wire_nllO1i_dataout, nll0lO, ~(wire_nl1OOO_dataout)); and(wire_nllO1l_dataout, nll0Oi, ~(wire_nl1OOO_dataout)); and(wire_nllO1O_dataout, nll0Ol, ~(wire_nl1OOO_dataout)); assign wire_nllOii_dataout = (wire_nl1OOi_dataout === 1'b1) ? wire_nllOil_o[2] : nlli1l; and(wire_nllOiO_dataout, wire_nllOOi_dataout, ~(wire_nl1OlO_dataout)); and(wire_nllOli_dataout, wire_nllOOl_dataout, ~(wire_nl1OlO_dataout)); and(wire_nllOll_dataout, wire_nllOOO_dataout, ~(wire_nl1OlO_dataout)); and(wire_nllOlO_dataout, wire_nlO11i_dataout, ~(wire_nl1OlO_dataout)); assign wire_nllOOi_dataout = (wire_nl1Oli_dataout === 1'b1) ? wire_nlO11l_o[0] : nlli1O; assign wire_nllOOl_dataout = (wire_nl1Oli_dataout === 1'b1) ? wire_nlO11l_o[1] : nlli0i; assign wire_nllOOO_dataout = (wire_nl1Oli_dataout === 1'b1) ? wire_nlO11l_o[2] : nlli0l; assign wire_nlO00i_dataout = (wire_nl1Oil_dataout === 1'b1) ? wire_nlO00O_o[7] : nlliOl; assign wire_nlO00l_dataout = (wire_nl1Oil_dataout === 1'b1) ? wire_nlO00O_o[8] : nlliOO; assign wire_nlO01i_dataout = (wire_nl1Oil_dataout === 1'b1) ? wire_nlO00O_o[4] : nllill; assign wire_nlO01l_dataout = (wire_nl1Oil_dataout === 1'b1) ? wire_nlO00O_o[5] : nllilO; assign wire_nlO01O_dataout = (wire_nl1Oil_dataout === 1'b1) ? wire_nlO00O_o[6] : nlliOi; and(wire_nlO10i_dataout, wire_nlO1Oi_dataout, ~(wire_nl1Oii_dataout)); and(wire_nlO10l_dataout, wire_nlO1Ol_dataout, ~(wire_nl1Oii_dataout)); and(wire_nlO10O_dataout, wire_nlO1OO_dataout, ~(wire_nl1Oii_dataout)); assign wire_nlO11i_dataout = (wire_nl1Oli_dataout === 1'b1) ? wire_nlO11l_o[3] : nlli0O; and(wire_nlO11O_dataout, wire_nlO1lO_dataout, ~(wire_nl1Oii_dataout)); and(wire_nlO1ii_dataout, wire_nlO01i_dataout, ~(wire_nl1Oii_dataout)); and(wire_nlO1il_dataout, wire_nlO01l_dataout, ~(wire_nl1Oii_dataout)); and(wire_nlO1iO_dataout, wire_nlO01O_dataout, ~(wire_nl1Oii_dataout)); and(wire_nlO1li_dataout, wire_nlO00i_dataout, ~(wire_nl1Oii_dataout)); and(wire_nlO1ll_dataout, wire_nlO00l_dataout, ~(wire_nl1Oii_dataout)); assign wire_nlO1lO_dataout = (wire_nl1Oil_dataout === 1'b1) ? wire_nlO00O_o[0] : nlliii; assign wire_nlO1Oi_dataout = (wire_nl1Oil_dataout === 1'b1) ? wire_nlO00O_o[1] : nlliil; assign wire_nlO1Ol_dataout = (wire_nl1Oil_dataout === 1'b1) ? wire_nlO00O_o[2] : nlliiO; assign wire_nlO1OO_dataout = (wire_nl1Oil_dataout === 1'b1) ? wire_nlO00O_o[3] : nllili; and(wire_nlOi_dataout, wire_nil_dataout, n0OlOi); and(wire_nlOl_dataout, wire_niO_dataout, n0OlOi); and(wire_nlOO_dataout, wire_nli_dataout, n0OlOi); and(wire_nO_dataout, rbisten_rx, (((~ rbist_sel[0]) & (~ rbist_sel[1])) & (n0OO0i2 ^ n0OO0i1))); oper_add niiOl ( .a({ni0li, ni0iO, ni0il, ni0ii, ni00O}), .b({{4{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_niiOl_o)); defparam niiOl.sgate_representation = 0, niiOl.width_a = 5, niiOl.width_b = 5, niiOl.width_o = 5; oper_add niO0Ol ( .a({nil10i, nil11O, nil11l, nil11i, niiOOO, niiOOl, niiOOi}), .b({{6{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_niO0Ol_o)); defparam niO0Ol.sgate_representation = 0, niO0Ol.width_a = 7, niO0Ol.width_b = 7, niO0Ol.width_o = 7; oper_add niO0OO ( .a({niiOll, niiOli, niiOiO, niiOil, niiOii, niiO0O, niiO0l}), .b({{6{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_niO0OO_o)); defparam niO0OO.sgate_representation = 0, niO0OO.width_a = 7, niO0OO.width_b = 7, niO0OO.width_o = 7; oper_add niOi1i ( .a({nil1Oi, nil1lO, nil1ll, nil1li, nil1iO, nil1il, nil1ii, nil10O, nil10l}), .b({{8{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_niOi1i_o)); defparam niOi1i.sgate_representation = 0, niOi1i.width_a = 9, niOi1i.width_b = 9, niOi1i.width_o = 9; oper_add nllO0i ( .a({nll0Ol, nll0Oi, nll0lO, nll0ll, nll0li, nll0iO}), .b({{5{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_nllO0i_o)); defparam nllO0i.sgate_representation = 0, nllO0i.width_a = 6, nllO0i.width_b = 6, nllO0i.width_o = 6; oper_add nllOil ( .a({nlli1l, nlli1i, nll0OO}), .b({{2{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_nllOil_o)); defparam nllOil.sgate_representation = 0, nllOil.width_a = 3, nllOil.width_b = 3, nllOil.width_o = 3; oper_add nlO00O ( .a({nlliOO, nlliOl, nlliOi, nllilO, nllill, nllili, nlliiO, nlliil, nlliii}), .b({{8{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_nlO00O_o)); defparam nlO00O.sgate_representation = 0, nlO00O.width_a = 9, nlO00O.width_b = 9, nlO00O.width_o = 9; oper_add nlO11l ( .a({nlli0O, nlli0l, nlli0i, nlli1O}), .b({{3{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_nlO11l_o)); defparam nlO11l.sgate_representation = 0, nlO11l.width_a = 4, nlO11l.width_b = 4, nlO11l.width_o = 4; oper_decoder n11li ( .i({nii1i, ni0Ol, ni0Oi, ni0lO, ni0ll}), .o(wire_n11li_o)); defparam n11li.width_i = 5, n11li.width_o = 32; oper_decoder ni1iii ( .i({nil00O, nil00l, nil00i, nil01O}), .o(wire_ni1iii_o)); defparam ni1iii.width_i = 4, ni1iii.width_o = 16; oper_decoder nii0Ol ( .i({nil01l, nil01i, nil1OO, nil1Ol}), .o(wire_nii0Ol_o)); defparam nii0Ol.width_i = 4, nii0Ol.width_o = 16; oper_decoder nl1OiO ( .i({nlll0i, nlll1O, nlll1l, nlll1i}), .o(wire_nl1OiO_o)); defparam nl1OiO.width_i = 4, nl1OiO.width_o = 16; oper_mux n100i ( .data({{10{1'b0}}, wire_n10ll_dataout, {5{1'b0}}, wire_n1O0l_dataout, wire_n00iO_dataout, n0O00l, n0O00O, ((n0O11l38 ^ n0O11l37) & n0O0ii), n0O0il, n0O0iO, n0O0li, n0O0ll, wire_n0lOi_dataout, {3{1'b0}}, wire_n0Oil_dataout, wire_n0OOi_dataout, 1'b0}), .o(wire_n100i_o), .sel({nii1i, ni0Ol, ni0Oi, ni0lO, ni0ll})); defparam n100i.width_data = 32, n100i.width_sel = 5; oper_mux n100l ( .data({{10{1'b0}}, wire_n10lO_dataout, ((n0O11O36 ^ n0O11O35) & wire_n1i1i_dataout), wire_n1iii_dataout, wire_n1ill_dataout, ((n0O10i34 ^ n0O10i33) & wire_n1iOO_dataout), wire_n1l0l_dataout, wire_n1O0O_dataout, wire_n00li_dataout, (~ n0O00l), (~ n0O00O), (~ n0O0ii), ((n0O10l32 ^ n0O10l31) & (~ n0O0il)), ((n0O10O30 ^ n0O10O29) & (~ n0O0iO)), (~ n0O0li), (~ n0O0ll), (~ n0O0lO), (~ n0O0Oi), (~ n0O0Ol), 1'b0, wire_n0OiO_dataout, wire_n0OOl_dataout, 1'b0}), .o(wire_n100l_o), .sel({((n0O1ii28 ^ n0O1ii27) & nii1i), ni0Ol, ni0Oi, ni0lO, ni0ll})); defparam n100l.width_data = 32, n100l.width_sel = 5; oper_mux n101i ( .data({{10{1'b0}}, wire_n10il_dataout, {4{1'b1}}, wire_n1l0i_dataout, wire_n1O1l_dataout, wire_n000O_dataout, (~ n0O00l), wire_n0iii_dataout, (~ n0O0ii), wire_n0iOi_dataout, (~ n0O0iO), wire_n0l0l_dataout, (~ n0O0ll), wire_n0llO_dataout, (~ n0O0Oi), wire_n0O1O_dataout, 1'b0, wire_n0O0l_dataout, wire_n0Oli_dataout, (wire_ni_dataout & n11Oi)}), .o(wire_n101i_o), .sel({nii1i, ni0Ol, ni0Oi, ni0lO, ni0ll})); defparam n101i.width_data = 32, n101i.width_sel = 5; oper_mux n101l ( .data({{10{1'b0}}, wire_n10iO_dataout, {5{1'b0}}, wire_n1O1O_dataout, wire_n00ii_dataout, n0O00l, wire_n0iil_dataout, 1'b0, wire_n0iOl_dataout, n0O0iO, wire_n0l0O_dataout, 1'b0, wire_n0lll_dataout, n0O0Oi, wire_n0O0i_dataout, 1'b0, wire_n0O0O_dataout, wire_n0Oll_dataout, 1'b0}), .o(wire_n101l_o), .sel({nii1i, ni0Ol, ni0Oi, ((n0lOOi46 ^ n0lOOi45) & ni0lO), ni0ll})); defparam n101l.width_data = 32, n101l.width_sel = 5; oper_mux n101O ( .data({{10{1'b0}}, ((n0lOOl44 ^ n0lOOl43) & wire_n10li_dataout), wire_n1i1i_dataout, wire_n1iii_dataout, ((n0lOOO42 ^ n0lOOO41) & wire_n1ill_dataout), wire_n1iOO_dataout, wire_n1l0l_dataout, wire_n1O0i_dataout, ((n0O11i40 ^ n0O11i39) & wire_n00il_dataout), {3{1'b1}}, wire_n0iOO_dataout, (~ n0O0iO), (~ n0O0li), (~ n0O0ll), wire_n0llO_dataout, {3{1'b1}}, wire_n0Oii_dataout, wire_n0OlO_dataout, 1'b0}), .o(wire_n101O_o), .sel({nii1i, ni0Ol, ni0Oi, ni0lO, ni0ll})); defparam n101O.width_data = 32, n101O.width_sel = 5; oper_mux n11Ol ( .data({{10{ni00i}}, wire_n100O_dataout, wire_n10OO_dataout, wire_n1i0O_dataout, wire_n1ili_dataout, wire_n1iOl_dataout, wire_n1l1O_dataout, wire_n1O1i_dataout, wire_n000l_dataout, wire_n0i0i_dataout, wire_n0i0O_dataout, wire_n0ili_dataout, wire_n0ilO_dataout, wire_n0l1l_dataout, wire_n0l0i_dataout, wire_n0lil_dataout, wire_n0lli_dataout, wire_n0lOO_dataout, wire_n0O1l_dataout, {4{ni00i}}}), .o(wire_n11Ol_o), .sel({nii1i, ni0Ol, ni0Oi, ni0lO, ni0ll})); defparam n11Ol.width_data = 32, n11Ol.width_sel = 5; oper_mux n11OO ( .data({{10{ni01l}}, wire_n10ii_dataout, wire_n10Ol_dataout, wire_n1i0l_dataout, wire_n1iiO_dataout, wire_n1iOi_dataout, wire_n1l1l_dataout, wire_n1lOO_dataout, wire_n000i_dataout, wire_n0i1O_dataout, wire_n0i0l_dataout, wire_n0iiO_dataout, wire_n0ill_dataout, wire_n0l1i_dataout, wire_n0l1O_dataout, wire_n0lii_dataout, wire_n0liO_dataout, wire_n0lOl_dataout, wire_n0O1i_dataout, {4{ni01l}}}), .o(wire_n11OO_o), .sel({nii1i, ni0Ol, ni0Oi, ni0lO, ni0ll})); defparam n11OO.width_data = 32, n11OO.width_sel = 5; oper_mux ni1iil ( .data({{3{1'b0}}, n0iO1l, wire_ni1O1i_dataout, n0iOil, wire_ni010O_dataout, n0iOOl, wire_ni000i_dataout, 1'b0, wire_ni0i1O_dataout, n0l1ll, wire_ni0l1i_dataout, n0l0ii, n0l0Ol, 1'b0}), .o(wire_ni1iil_o), .sel({nil00O, nil00l, nil00i, nil01O})); defparam ni1iil.width_data = 16, ni1iil.width_sel = 4; oper_mux ni1iiO ( .data({{2{niilOO}}, wire_ni1l1i_dataout, wire_ni1lil_dataout, wire_ni1lOO_dataout, {11{niilOO}}}), .o(wire_ni1iiO_o), .sel({nil00O, nil00l, nil00i, nil01O})); defparam ni1iiO.width_data = 16, ni1iiO.width_sel = 4; oper_mux ni1ili ( .data({{2{niiO1i}}, wire_ni1l1l_dataout, wire_ni1liO_dataout, wire_ni1O1l_dataout, wire_ni1OOl_dataout, wire_ni011l_dataout, wire_ni01Oi_dataout, wire_ni001i_dataout, wire_ni00ll_dataout, wire_ni00Ol_dataout, wire_ni0ili_dataout, wire_ni0iOi_dataout, wire_ni0lil_dataout, wire_ni0Oli_dataout, niiO1i}), .o(wire_ni1ili_o), .sel({nil00O, nil00l, nil00i, nil01O})); defparam ni1ili.width_data = 16, ni1ili.width_sel = 4; oper_mux ni1ill ( .data({{2{niiO1l}}, wire_ni1l1O_dataout, wire_ni1lli_dataout, wire_ni1O1O_dataout, wire_ni1OOO_dataout, wire_ni011O_dataout, wire_ni01Ol_dataout, wire_ni001l_dataout, wire_ni00lO_dataout, wire_ni00OO_dataout, wire_ni0ill_dataout, wire_ni0iOl_dataout, wire_ni0liO_dataout, wire_ni0Oll_dataout, niiO1l}), .o(wire_ni1ill_o), .sel({nil00O, nil00l, nil00i, nil01O})); defparam ni1ill.width_data = 16, ni1ill.width_sel = 4; oper_mux ni1ilO ( .data({{2{1'b0}}, wire_ni1l0i_dataout, 1'b1, wire_ni1O0i_dataout, 1'b1, wire_ni010i_dataout, 1'b1, wire_ni001O_dataout, 1'b1, wire_ni0i1i_dataout, 1'b1, wire_ni0iOO_dataout, wire_ni0lli_dataout, wire_ni0OlO_dataout, wire_nii00i_dataout}), .o(wire_ni1ilO_o), .sel({nil00O, nil00l, nil00i, nil01O})); defparam ni1ilO.width_data = 16, ni1ilO.width_sel = 4; oper_mux ni1iOi ( .data({{2{1'b0}}, wire_ni1l0l_dataout, {2{1'b0}}, (~ n0iOil), wire_ni010l_dataout, {2{1'b0}}, (~ n0l10l), wire_ni0i1l_dataout, {2{1'b0}}, wire_ni0lll_dataout, wire_ni0OOi_dataout, wire_nii00l_dataout}), .o(wire_ni1iOi_o), .sel({nil00O, nil00l, nil00i, nil01O})); defparam ni1iOi.width_data = 16, ni1iOi.width_sel = 4; oper_mux ni1iOl ( .data({{2{1'b0}}, wire_ni1l0O_dataout, wire_ni1lll_dataout, wire_ni1O0l_dataout, n0iOil, wire_ni010O_dataout, n0iOOl, wire_ni000i_dataout, {4{1'b1}}, wire_ni0llO_dataout, wire_ni0OOl_dataout, wire_nii00O_dataout}), .o(wire_ni1iOl_o), .sel({nil00O, nil00l, nil00i, nil01O})); defparam ni1iOl.width_data = 16, ni1iOl.width_sel = 4; oper_mux ni1iOO ( .data({{2{1'b0}}, wire_ni1lii_dataout, wire_ni1lll_dataout, wire_ni1O0l_dataout, {4{1'b1}}, n0l10l, wire_ni0i1O_dataout, n0l1ll, wire_ni0l1i_dataout, wire_ni0lOi_dataout, wire_ni0OOO_dataout, wire_nii0ii_dataout}), .o(wire_ni1iOO_o), .sel({nil00O, nil00l, nil00i, nil01O})); defparam ni1iOO.width_data = 16, ni1iOO.width_sel = 4; oper_mux nii0iO ( .data({{4{1'b1}}, 1'b0, 1'b1, {7{1'b0}}, wire_niOi1l_dataout, {2{1'b1}}}), .o(wire_nii0iO_o), .sel({nil01l, nil01i, nil1OO, nil1Ol})); defparam nii0iO.width_data = 16, nii0iO.width_sel = 4; oper_mux nii0li ( .data({{3{1'b1}}, 1'b0, {2{1'b1}}, {7{1'b0}}, wire_niOi1O_dataout, {2{1'b1}}}), .o(wire_nii0li_o), .sel({nil01l, nil01i, nil1OO, nil1Ol})); defparam nii0li.width_data = 16, nii0li.width_sel = 4; oper_mux nii0lO ( .data({{5{1'b1}}, 1'b0, {7{1'b1}}, wire_niOi0l_dataout, {2{1'b1}}}), .o(wire_nii0lO_o), .sel({nil01l, nil01i, nil1OO, nil1Ol})); defparam nii0lO.width_data = 16, nii0lO.width_sel = 4; oper_mux nii0OO ( .data({{7{1'b1}}, {2{1'b0}}, 1'b1, 1'b0, 1'b1, 1'b0, wire_niOiii_dataout, {2{1'b1}}}), .o(wire_nii0OO_o), .sel({nil01l, nil01i, nil1OO, nil1Ol})); defparam nii0OO.width_data = 16, nii0OO.width_sel = 4; oper_mux niii0i ( .data({{3{n0OlOi}}, {3{1'b0}}, n0OlOi, {6{1'b0}}, wire_niOill_dataout, {2{n0OlOi}}}), .o(wire_niii0i_o), .sel({nil01l, nil01i, nil1OO, nil1Ol})); defparam niii0i.width_data = 16, niii0i.width_sel = 4; oper_mux niii0l ( .data({{3{n0OlOi}}, 1'b0, n0OlOi, 1'b0, n0OlOi, 1'b0, n0OlOi, 1'b0, n0OlOi, 1'b0, n0OlOi, wire_niOilO_dataout, {2{n0OlOi}}}), .o(wire_niii0l_o), .sel({nil01l, nil01i, nil1OO, nil1Ol})); defparam niii0l.width_data = 16, niii0l.width_sel = 4; oper_mux niii0O ( .data({{3{n0OlOi}}, 1'b0, n0OlOi, {3{1'b0}}, n0OlOi, 1'b0, n0OlOi, 1'b0, n0OlOi, wire_niOiOi_dataout, {2{n0OlOi}}}), .o(wire_niii0O_o), .sel({nil01l, nil01i, nil1OO, nil1Ol})); defparam niii0O.width_data = 16, niii0O.width_sel = 4; oper_mux niii1i ( .data({{8{1'b1}}, 1'b0, {2{1'b1}}, {2{1'b0}}, wire_niOiil_dataout, {2{1'b1}}}), .o(wire_niii1i_o), .sel({nil01l, nil01i, nil1OO, nil1Ol})); defparam niii1i.width_data = 16, niii1i.width_sel = 4; oper_mux niii1l ( .data({{9{1'b1}}, {4{1'b0}}, wire_niOiiO_dataout, {2{1'b1}}}), .o(wire_niii1l_o), .sel({nil01l, nil01i, nil1OO, nil1Ol})); defparam niii1l.width_data = 16, niii1l.width_sel = 4; oper_mux niii1O ( .data({{3{n0OlOi}}, 1'b0, n0OlOi, 1'b0, n0OlOi, {6{1'b0}}, wire_niOili_dataout, {2{n0OlOi}}}), .o(wire_niii1O_o), .sel({nil01l, nil01i, nil1OO, nil1Ol})); defparam niii1O.width_data = 16, niii1O.width_sel = 4; oper_mux niiiii ( .data({{3{n0OlOi}}, 1'b0, n0OlOi, 1'b0, n0OlOi, 1'b0, n0OlOi, 1'b0, n0OlOi, 1'b0, n0OlOi, wire_niOiOl_dataout, {2{n0OlOi}}}), .o(wire_niiiii_o), .sel({nil01l, nil01i, nil1OO, nil1Ol})); defparam niiiii.width_data = 16, niiiii.width_sel = 4; oper_mux niiiil ( .data({{3{n0OlOi}}, 1'b0, n0OlOi, 1'b0, n0OlOi, {3{1'b0}}, n0OlOi, 1'b0, n0OlOi, wire_niOiOO_dataout, {2{n0OlOi}}}), .o(wire_niiiil_o), .sel({nil01l, nil01i, nil1OO, nil1Ol})); defparam niiiil.width_data = 16, niiiil.width_sel = 4; oper_mux niiiiO ( .data({{3{n0OlOi}}, 1'b0, n0OlOi, 1'b0, n0OlOi, 1'b0, n0OlOi, 1'b0, n0OlOi, {2{1'b0}}, wire_niOl1i_dataout, {2{n0OlOi}}}), .o(wire_niiiiO_o), .sel({nil01l, nil01i, nil1OO, nil1Ol})); defparam niiiiO.width_data = 16, niiiiO.width_sel = 4; oper_mux niiili ( .data({{3{n0OlOi}}, 1'b0, n0OlOi, 1'b0, n0OlOi, 1'b0, n0OlOi, {4{1'b0}}, wire_niOl1l_dataout, {2{n0OlOi}}}), .o(wire_niiili_o), .sel({nil01l, nil01i, nil1OO, nil1Ol})); defparam niiili.width_data = 16, niiili.width_sel = 4; oper_mux niiill ( .data({{3{n0OlOi}}, 1'b0, n0OlOi, 1'b0, n0OlOi, 1'b0, n0OlOi, 1'b0, n0OlOi, 1'b0, n0OlOi, 1'b0, {2{n0OlOi}}}), .o(wire_niiill_o), .sel({nil01l, nil01i, nil1OO, nil1Ol})); defparam niiill.width_data = 16, niiill.width_sel = 4; oper_mux nl010i ( .data({wire_nl01li_dataout, {4{1'b1}}, wire_nl0i0l_dataout, (~ n0liOl), wire_nl0l1O_dataout, wire_nl0llO_dataout, wire_nli01O_dataout, wire_nliiOl_dataout, {2{1'b1}}, wire_nliOiO_dataout, wire_nll11O_dataout, (wire_nl_dataout & nl1Oll)}), .o(wire_nl010i_o), .sel({nlll0i, nlll1O, nlll1l, nlll1i})); defparam nl010i.width_data = 16, nl010i.width_sel = 4; oper_mux nl010l ( .data({wire_nl01ll_dataout, wire_nl001l_dataout, wire_nl00il_dataout, wire_nl00lO_dataout, wire_nl0i1i_dataout, wire_nl0i0O_dataout, (~ n0liOl), wire_nl0l1O_dataout, wire_nl0lOi_dataout, wire_nli00i_dataout, wire_nliiOO_dataout, (~ n0llOO), 1'b0, wire_nliOli_dataout, wire_nll10i_dataout, 1'b0}), .o(wire_nl010l_o), .sel({nlll0i, nlll1O, nlll1l, nlll1i})); defparam nl010l.width_data = 16, nl010l.width_sel = 4; oper_mux nl010O ( .data({wire_nl01lO_dataout, wire_nl001l_dataout, wire_nl00il_dataout, wire_nl00lO_dataout, wire_nl0i1i_dataout, wire_nl0i0O_dataout, (~ n0liOl), wire_nl0l1O_dataout, wire_nl0lOl_dataout, wire_nli00l_dataout, {3{1'b1}}, wire_nliOll_dataout, wire_nll10l_dataout, 1'b0}), .o(wire_nl010O_o), .sel({nlll0i, nlll1O, nlll1l, nlll1i})); defparam nl010O.width_data = 16, nl010O.width_sel = 4; oper_mux nl011i ( .data({nll0il, wire_nl01Ol_dataout, wire_nl000l_dataout, wire_nl00iO_dataout, wire_nl00Oi_dataout, wire_nl0i1l_dataout, {10{nll0il}}}), .o(wire_nl011i_o), .sel({nlll0i, nlll1O, nlll1l, nlll1i})); defparam nl011i.width_data = 16, nl011i.width_sel = 4; oper_mux nl011l ( .data({wire_nl01il_dataout, wire_nl001i_dataout, wire_nl00ii_dataout, wire_nl00ll_dataout, wire_nl00OO_dataout, wire_nl0i0i_dataout, wire_nl0lil_dataout, wire_nl0l1l_dataout, wire_nl0lll_dataout, wire_nli01l_dataout, wire_nliiOi_dataout, wire_nliOil_dataout, {4{nll0ii}}}), .o(wire_nl011l_o), .sel({nlll0i, nlll1O, nlll1l, nlll1i})); defparam nl011l.width_data = 16, nl011l.width_sel = 4; oper_mux nl011O ( .data({wire_nl01iO_dataout, wire_nl01OO_dataout, wire_nl000O_dataout, wire_nl00li_dataout, wire_nl00Ol_dataout, wire_nl0i1O_dataout, wire_nl0lii_dataout, wire_nl0l1i_dataout, wire_nl0lli_dataout, wire_nli01i_dataout, wire_nliilO_dataout, wire_nliOii_dataout, {4{nll00O}}}), .o(wire_nl011O_o), .sel({nlll0i, nlll1O, nlll1l, nlll1i})); defparam nl011O.width_data = 16, nl011O.width_sel = 4; oper_mux nl01ii ( .data({wire_nl01Oi_dataout, wire_nl001l_dataout, wire_nl00il_dataout, wire_nl00lO_dataout, wire_nl0i1i_dataout, wire_nl0i0O_dataout, 1'b1, wire_nl0l0i_dataout, wire_nl0lOO_dataout, wire_nli00O_dataout, (~ n0llil), (~ n0llOO), 1'b0, wire_nliOlO_dataout, wire_nll10O_dataout, 1'b0}), .o(wire_nl01ii_o), .sel({nlll0i, nlll1O, nlll1l, nlll1i})); defparam nl01ii.width_data = 16, nl01ii.width_sel = 4; oper_selector n11ii ( .data({1'b0, wire_n1lOi_dataout, wire_n001l_dataout}), .o(wire_n11ii_o), .sel({n0lOll, wire_n11li_o[15:14]})); defparam n11ii.width_data = 3, n11ii.width_sel = 3; oper_selector n11il ( .data({1'b0, wire_n1lOl_dataout, wire_n001O_dataout}), .o(wire_n11il_o), .sel({n0lOll, wire_n11li_o[15:14]})); defparam n11il.width_data = 3, n11il.width_sel = 3; oper_selector n11ll ( .data({ni00l, wire_n10Oi_dataout, wire_n1i0i_dataout, wire_n1iil_dataout, wire_n1ilO_dataout, wire_n1l1i_dataout}), .o(wire_n11ll_o), .sel({n0lOlO, wire_n11li_o[20:16]})); defparam n11ll.width_data = 6, n11ll.width_sel = 6; oper_selector ni1i0l ( .data({1'b0, 1'b1, wire_ni0OiO_dataout}), .o(wire_ni1i0l_o), .sel({n0iO1i, wire_ni1iii_o[2:1]})); defparam ni1i0l.width_data = 3, ni1i0l.width_sel = 3; assign bistdone = ((wire_nl1l_dataout | prbs_done) | (~ (n0Ol0O10 ^ n0Ol0O9))), bisterr = ((wire_nl1i_dataout | prbs_err) | (~ (n0Olil8 ^ n0Olil7))), cur_state = {wire_n1OO_dataout, wire_n1Ol_dataout, wire_n1Oi_dataout, wire_n1lO_dataout, wire_n1ll_dataout}, err_ctl = {wire_niOO_dataout, wire_niOl_dataout}, err_data = {wire_niOi_dataout, wire_nilO_dataout, wire_nill_dataout, wire_nili_dataout, wire_niiO_dataout, wire_niil_dataout, wire_niii_dataout, wire_ni0O_dataout, wire_ni0l_dataout, wire_ni0i_dataout, wire_ni1O_dataout, wire_ni1l_dataout, wire_ni1i_dataout, wire_n0OO_dataout, wire_n0Ol_dataout, wire_n0Oi_dataout}, n0iO0i = ((~ n0iO0l) | (~ n0l1Ol)), n0iO0l = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & (~ rxd[0])) & rxd[1]) & rxd[2]) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]), n0iO0O = ((~ n0iOii) | (~ n0l01l)), n0iO1i = (((((((((((((wire_ni1iii_o[15] | wire_ni1iii_o[14]) | wire_ni1iii_o[13]) | wire_ni1iii_o[12]) | wire_ni1iii_o[11]) | wire_ni1iii_o[10]) | wire_ni1iii_o[9]) | wire_ni1iii_o[8]) | wire_ni1iii_o[7]) | wire_ni1iii_o[6]) | wire_ni1iii_o[5]) | wire_ni1iii_o[4]) | wire_ni1iii_o[3]) | wire_ni1iii_o[0]), n0iO1l = ((~ n0iO1O) | (~ n0l1Ol)), n0iO1O = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & rxd[0]) & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]), n0iOii = (((((((((((((((wire_nlOO_dataout & wire_nlOl_dataout) & wire_nlOi_dataout) & wire_nllO_dataout) & wire_nlll_dataout) & wire_nlli_dataout) & (~ wire_nliO_dataout)) & wire_nlil_dataout) & (~ rxd[0])) & rxd[1]) & rxd[2]) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]), n0iOil = ((~ n0iOiO) | (~ n0l1Ol)), n0iOiO = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & rxd[0]) & rxd[1]) & rxd[2]) & (~ rxd[3])) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]), n0iOli = ((~ n0iOll) | (~ n0l1Ol)), n0iOll = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & (~ rxd[0])) & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]), n0iOlO = ((~ n0iOOi) | (~ n0l01l)), n0iOOi = (((((((((((((((wire_nlOO_dataout & wire_nlOl_dataout) & wire_nlOi_dataout) & wire_nllO_dataout) & (~ wire_nlll_dataout)) & wire_nlli_dataout) & wire_nliO_dataout) & wire_nlil_dataout) & (~ rxd[0])) & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]), n0iOOl = ((~ n0iOOO) | (~ n0l1Ol)), n0iOOO = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & (~ rxd[0])) & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & (~ rxd[5])) & rxd[6]) & rxd[7]), n0l00i = (((((((nil1lO & nil1ll) & nil1li) & nil1iO) & nil1il) & nil1ii) & nil10O) & nil10l), n0l00l = (n0OlOi & n0l00O), n0l00O = (((((((niiOll & niiOli) & niiOiO) & niiOil) & niiOii) & niiO0O) & niiO0l) & niiO0i), n0l01i = ((~ n0l01O) | (~ n0l01l)), n0l01l = (wire_nlii_dataout & rxc[0]), n0l01O = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & wire_nlOi_dataout) & wire_nllO_dataout) & wire_nlll_dataout) & wire_nlli_dataout) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & (~ rxd[0])) & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & (~ rxd[5])) & (~ rxd[6])) & (~ rxd[7])), n0l0ii = ((~ n0l0il) | (~ ((~ wire_nlii_dataout) & (~ rxc[0])))), n0l0il = ((((((((((((((((~ (rxd[0] ^ wire_niOi1l_dataout)) & (~ (rxd[1] ^ wire_niOi1O_dataout))) & (~ (rxd[2] ^ wire_niOi0i_dataout))) & (~ (rxd[3] ^ wire_niOi0l_dataout))) & (~ (rxd[4] ^ wire_niOi0O_dataout))) & (~ (rxd[5] ^ wire_niOiii_dataout))) & (~ (rxd[6] ^ wire_niOiil_dataout))) & (~ (rxd[7] ^ wire_niOiiO_dataout))) & (~ (wire_nlil_dataout ^ wire_niOili_dataout))) & (~ (wire_nliO_dataout ^ wire_niOill_dataout))) & (~ (wire_nlli_dataout ^ wire_niOilO_dataout))) & (~ (wire_nlll_dataout ^ wire_niOiOi_dataout))) & (~ (wire_nllO_dataout ^ wire_niOiOl_dataout))) & (~ (wire_nlOi_dataout ^ wire_niOiOO_dataout))) & (~ (wire_nlOl_dataout ^ wire_niOl1i_dataout))) & (~ (wire_nlOO_dataout ^ wire_niOl1l_dataout))), n0l0iO = ((~ n0OlOi) & (rxc[0] & n0l0li)), n0l0li = (((((((rxd[0] & rxd[1]) & (~ rxd[2])) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]), n0l0ll = (n0OlOi & ((wire_nlii_dataout & n0l0Oi) & (rxc[0] & n0l0lO))), n0l0lO = ((((((((~ rxd[0]) & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & rxd[5]) & (~ rxd[6])) & rxd[7]), n0l0Oi = (((((((wire_nlOO_dataout & wire_nlOl_dataout) & wire_nlOi_dataout) & wire_nllO_dataout) & wire_nlll_dataout) & (~ wire_nlli_dataout)) & wire_nliO_dataout) & wire_nlil_dataout), n0l0Ol = (((~ n0OlOi) & n0li1i) | (n0OlOi & n0l0OO)), n0l0OO = ((((((((nil1Oi & (~ nil1lO)) & (~ nil1ll)) & (~ nil1li)) & (~ nil1iO)) & (~ nil1il)) & (~ nil1ii)) & (~ nil10O)) & (~ nil10l)), n0l10i = (((((((((((((((wire_nlOO_dataout & wire_nlOl_dataout) & (~ wire_nlOi_dataout)) & wire_nllO_dataout) & wire_nlll_dataout) & wire_nlli_dataout) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & (~ rxd[0])) & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & (~ rxd[5])) & (~ rxd[6])) & rxd[7]), n0l10l = ((~ n0l10O) | (~ n0l1Ol)), n0l10O = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & (~ rxd[0])) & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & (~ rxd[7])), n0l11i = ((~ n0l11l) | (~ n0l1Ol)), n0l11l = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & (~ rxd[0])) & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & (~ rxd[5])) & (~ rxd[6])) & rxd[7]), n0l11O = ((~ n0l10i) | (~ n0l01l)), n0l1ii = ((~ n0l1il) | (~ n0l1Ol)), n0l1il = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & (~ rxd[0])) & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & (~ rxd[5])) & rxd[6]) & (~ rxd[7])), n0l1iO = ((~ n0l1li) | (~ n0l01l)), n0l1li = ((((((((((((((((~ wire_nlOO_dataout) & wire_nlOl_dataout) & wire_nlOi_dataout) & wire_nllO_dataout) & wire_nlll_dataout) & wire_nlli_dataout) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & (~ rxd[0])) & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & (~ rxd[5])) & rxd[6]) & (~ rxd[7])), n0l1ll = ((~ n0l1lO) | (~ n0l1Ol)), n0l1lO = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & (~ rxd[0])) & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & rxd[5]) & (~ rxd[6])) & (~ rxd[7])), n0l1Oi = ((~ n0l1OO) | (~ n0l1Ol)), n0l1Ol = ((~ wire_nlii_dataout) & rxc[0]), n0l1OO = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & (~ rxd[0])) & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & (~ rxd[5])) & (~ rxd[6])) & (~ rxd[7])), n0li0i = ((~ rxc[0]) | (~ n0li0l)), n0li0l = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & rxd[0]) & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]), n0li0O = ((((((((((((((((~ wire_nlOl_dataout) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & rxd[0]) & rxd[1]) & (~ rxd[2])) & rxd[3]) & (~ rxd[4])) & rxd[5]) & (~ rxd[6])) & rxd[7]) & (~ (n0OlOi ^ wire_nlli_dataout))) & (~ (n0OlOi ^ wire_nlll_dataout))) & (~ (n0OlOi ^ wire_nllO_dataout))) & (~ (n0OlOi ^ wire_nlOi_dataout))) & (~ (n0OlOi ^ wire_nlOO_dataout))), n0li1i = ((((((((nil1Oi & (~ nil1lO)) & (~ nil1ll)) & nil1li) & (~ nil1iO)) & (~ nil1il)) & (~ nil1ii)) & (~ nil10O)) & nil10l), n0li1l = (wire_nO_dataout & rxd[10]), n0liii = ((((((((((((((((~ wire_nlOl_dataout) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & (~ rxd[0])) & rxd[1]) & rxd[2]) & rxd[3]) & rxd[4]) & (~ rxd[5])) & (~ rxd[6])) & (~ rxd[7])) & (~ (n0OlOi ^ wire_nlli_dataout))) & (~ (n0OlOi ^ wire_nlll_dataout))) & (~ (n0OlOi ^ wire_nllO_dataout))) & (~ (n0OlOi ^ wire_nlOi_dataout))) & (~ (n0OlOi ^ wire_nlOO_dataout))), n0liil = ((((((((((((((((~ wire_nlOl_dataout) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & rxd[0]) & rxd[1]) & rxd[2]) & rxd[3]) & rxd[4]) & (~ rxd[5])) & (~ rxd[6])) & rxd[7]) & (~ (n0OlOi ^ wire_nlli_dataout))) & (~ (n0OlOi ^ wire_nlll_dataout))) & (~ (n0OlOi ^ wire_nllO_dataout))) & (~ (n0OlOi ^ wire_nlOi_dataout))) & (~ (n0OlOi ^ wire_nlOO_dataout))), n0liiO = ((~ n0lili) | (~ (wire_nlii_dataout & (~ rxc[0])))), n0lili = ((((((((((((((((~ wire_nliO_dataout) & rxd[0]) & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & rxd[5]) & (~ rxd[6])) & rxd[7]) & (~ (n0OlOi ^ wire_nlil_dataout))) & (~ (n0OlOi ^ wire_nlli_dataout))) & (~ (n0OlOi ^ wire_nlll_dataout))) & (~ (n0OlOi ^ wire_nllO_dataout))) & (~ (n0OlOi ^ wire_nlOi_dataout))) & (~ (n0OlOi ^ wire_nlOl_dataout))) & (~ (n0OlOi ^ wire_nlOO_dataout))), n0lill = ((((((((((((((((~ wire_nlOl_dataout) & (~ wire_nlll_dataout)) & (~ wire_nliO_dataout)) & rxd[0]) & (~ rxd[1])) & rxd[2]) & (~ rxd[3])) & rxd[4]) & rxd[5]) & (~ rxd[6])) & rxd[7]) & (~ (n0OlOi ^ wire_nlil_dataout))) & (~ (n0OlOi ^ wire_nlli_dataout))) & (~ (n0OlOi ^ wire_nllO_dataout))) & (~ (n0OlOi ^ wire_nlOi_dataout))) & (~ (n0OlOi ^ wire_nlOO_dataout))), n0lilO = ((((((~ nll0Ol) & nll0Oi) & (~ nll0lO)) & (~ nll0ll)) & nll0li) & nll0iO), n0liOi = (((((nll0Ol & (~ nll0Oi)) & (~ nll0lO)) & nll0ll) & nll0li) & nll0iO), n0liOl = ((((((((((((((((~ wire_nlOl_dataout) & (~ wire_nllO_dataout)) & (~ wire_nlli_dataout)) & rxd[5]) & rxd[7]) & (~ ((~ n0OlOi) ^ rxd[0]))) & (~ ((~ n0OlOi) ^ rxd[1]))) & (~ (n0OlOi ^ rxd[2]))) & (~ ((~ n0OlOi) ^ rxd[3]))) & (~ (n0OlOi ^ rxd[4]))) & (~ (n0OlOi ^ rxd[6]))) & (~ (n0OlOi ^ wire_nlil_dataout))) & (~ (n0OlOi ^ wire_nliO_dataout))) & (~ (n0OlOi ^ wire_nlll_dataout))) & (~ (n0OlOi ^ wire_nlOi_dataout))) & (~ (n0OlOi ^ wire_nlOO_dataout))), n0liOO = ((((((((((((((((~ wire_nlll_dataout) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & rxd[0]) & rxd[1]) & (~ rxd[2])) & rxd[3]) & (~ rxd[4])) & rxd[5]) & rxd[6]) & rxd[7]) & (~ (n0OlOi ^ wire_nlli_dataout))) & (~ (n0OlOi ^ wire_nllO_dataout))) & (~ (n0OlOi ^ wire_nlOi_dataout))) & (~ (n0OlOi ^ wire_nlOl_dataout))) & (~ (n0OlOi ^ wire_nlOO_dataout))), n0ll0i = ((((~ nlli0O) & (~ nlli0l)) & nlli0i) & (~ nlli1O)), n0ll0l = ((((~ nlli0O) & nlli0l) & nlli0i) & nlli1O), n0ll0O = (((nlli0O & nlli0l) & nlli0i) & nlli1O), n0ll1i = (((~ nlli1l) & nlli1i) & nll0OO), n0ll1l = ((nlli1l & nlli1i) & nll0OO), n0ll1O = ((((((((((((((((~ wire_nllO_dataout) & (~ wire_nlli_dataout)) & (~ rxd[0])) & (~ rxd[1])) & rxd[2]) & (~ rxd[3])) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]) & (~ (n0OlOi ^ wire_nlil_dataout))) & (~ (n0OlOi ^ wire_nliO_dataout))) & (~ (n0OlOi ^ wire_nlll_dataout))) & (~ (n0OlOi ^ wire_nlOi_dataout))) & (~ (n0OlOi ^ wire_nlOl_dataout))) & (~ (n0OlOi ^ wire_nlOO_dataout))), n0llii = (((((~ nlli0O) & (~ nlli0l)) & nlli0i) & nlli1O) | (((nlli0O & (~ nlli0l)) & nlli0i) & nlli1O)), n0llil = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlil_dataout)) & (~ rxd[0])) & rxd[1]) & rxd[2]) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & (~ rxd[7])) & (~ (n0OlOi ^ wire_nliO_dataout))) & (~ (n0OlOi ^ wire_nlli_dataout))) & (~ (n0OlOi ^ wire_nlll_dataout))) & (~ (n0OlOi ^ wire_nllO_dataout))) & (~ (n0OlOi ^ wire_nlOi_dataout))) & (~ (n0OlOi ^ wire_nlOl_dataout))), n0lliO = ((((((((nlliOO & (~ nlliOl)) & (~ nlliOi)) & (~ nllilO)) & (~ nllill)) & (~ nllili)) & nlliiO) & nlliil) & nlliii), n0llli = (((((((((~ nlliOO) & (~ nlliOl)) & nlliOi) & (~ nllilO)) & (~ nllill)) & (~ nllili)) & (~ nlliiO)) & (~ nlliil)) & nlliii), n0llll = (((((((((~ nlliOO) & nlliOl) & (~ nlliOi)) & (~ nllilO)) & (~ nllill)) & (~ nllili)) & (~ nlliiO)) & nlliil) & nlliii), n0lllO = ((((((((nlliOO & (~ nlliOl)) & (~ nlliOi)) & (~ nllilO)) & (~ nllill)) & (~ nllili)) & nlliiO) & nlliil) & (~ nlliii)), n0llOi = (((((((((~ nlliOO) & (~ nlliOl)) & nlliOi) & (~ nllilO)) & (~ nllill)) & (~ nllili)) & (~ nlliiO)) & (~ nlliil)) & (~ nlliii)), n0llOl = (((((((((~ nlliOO) & nlliOl) & (~ nlliOi)) & (~ nllilO)) & (~ nllill)) & (~ nllili)) & (~ nlliiO)) & nlliil) & (~ nlliii)), n0llOO = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlil_dataout)) & rxd[0]) & rxd[1]) & (~ rxd[2])) & rxd[3]) & (~ rxd[4])) & (~ rxd[5])) & (~ rxd[6])) & (~ rxd[7])) & (~ (n0OlOi ^ wire_nliO_dataout))) & (~ (n0OlOi ^ wire_nlli_dataout))) & (~ (n0OlOi ^ wire_nlll_dataout))) & (~ (n0OlOi ^ wire_nllO_dataout))) & (~ (n0OlOi ^ wire_nlOi_dataout))) & (~ (n0OlOi ^ wire_nlOl_dataout))), n0lO0i = (rcxpat_chnl_sel[0] & rcxpat_chnl_sel[1]), n0lO0l = (n0lOii & n0lO0O), n0lO0O = (((((((rxd[0] & (~ rxd[1])) & rxd[2]) & (~ rxd[3])) & rxd[4]) & (~ rxd[5])) & rxd[6]) & (~ rxd[7])), n0lO1i = ((~ rcxpat_chnl_sel[0]) & rcxpat_chnl_sel[1]), n0lO1l = (rcxpat_chnl_sel[0] & (~ rcxpat_chnl_sel[1])), n0lO1O = (n0lO0O & n0lO0i), n0lOii = (n0lO1l | n0lO1i), n0lOil = (rxc[0] & (n0lOli & n0lOiO)), n0lOiO = ((~ rcxpat_chnl_sel[0]) & (~ rcxpat_chnl_sel[1])), n0lOli = (((((((rxd[0] & rxd[1]) & (~ rxd[2])) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]), n0lOll = (((((((((((((((((((((((((((((wire_n11li_o[31] | wire_n11li_o[30]) | wire_n11li_o[29]) | wire_n11li_o[28]) | wire_n11li_o[27]) | wire_n11li_o[26]) | wire_n11li_o[25]) | wire_n11li_o[24]) | wire_n11li_o[23]) | wire_n11li_o[22]) | wire_n11li_o[21]) | wire_n11li_o[20]) | wire_n11li_o[19]) | wire_n11li_o[18]) | wire_n11li_o[17]) | wire_n11li_o[16]) | wire_n11li_o[13]) | wire_n11li_o[12]) | wire_n11li_o[11]) | wire_n11li_o[10]) | wire_n11li_o[9]) | wire_n11li_o[8]) | wire_n11li_o[7]) | wire_n11li_o[6]) | wire_n11li_o[5]) | wire_n11li_o[4]) | wire_n11li_o[3]) | wire_n11li_o[2]) | wire_n11li_o[1]) | wire_n11li_o[0]), n0lOlO = ((((((((((((((((((((((((((wire_n11li_o[31] | wire_n11li_o[30]) | wire_n11li_o[29]) | wire_n11li_o[28]) | wire_n11li_o[27]) | wire_n11li_o[26]) | wire_n11li_o[25]) | wire_n11li_o[24]) | wire_n11li_o[23]) | wire_n11li_o[22]) | wire_n11li_o[21]) | wire_n11li_o[15]) | wire_n11li_o[14]) | wire_n11li_o[13]) | wire_n11li_o[12]) | wire_n11li_o[11]) | wire_n11li_o[10]) | wire_n11li_o[9]) | wire_n11li_o[8]) | wire_n11li_o[7]) | wire_n11li_o[6]) | wire_n11li_o[5]) | wire_n11li_o[4]) | wire_n11li_o[3]) | wire_n11li_o[2]) | wire_n11li_o[1]) | wire_n11li_o[0]), n0O00i = ((((ni0li & ni0iO) & ni0il) & ni0ii) & (~ ni00O)), n0O00l = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & rxd[0]) & rxd[1]) & (~ rxd[2])) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]), n0O00O = ((((((((((((((((~ wire_nlli_dataout) & (~ rxd[0])) & rxd[1]) & rxd[2]) & rxd[3]) & rxd[4]) & (~ rxd[5])) & rxd[6]) & (~ rxd[7])) & (~ (n0OlOi ^ wire_nlil_dataout))) & (~ (n0OlOi ^ wire_nliO_dataout))) & (~ (n0OlOi ^ wire_nlll_dataout))) & (~ (n0OlOi ^ wire_nllO_dataout))) & (~ (n0OlOi ^ wire_nlOi_dataout))) & (~ (n0OlOi ^ wire_nlOl_dataout))) & (~ (n0OlOi ^ wire_nlOO_dataout))), n0O01i = ((((((((((((((((~ wire_nliO_dataout) & (~ rxd[0])) & (~ rxd[1])) & (~ rxd[2])) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]) & (~ (n0OlOi ^ wire_nlil_dataout))) & (~ (n0OlOi ^ wire_nlli_dataout))) & (~ (n0OlOi ^ wire_nlll_dataout))) & (~ (n0OlOi ^ wire_nllO_dataout))) & (~ (n0OlOi ^ wire_nlOi_dataout))) & (~ (n0OlOi ^ wire_nlOl_dataout))) & (~ (n0OlOi ^ wire_nlOO_dataout))), n0O01l = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & rxd[0]) & (~ rxd[1])) & (~ rxd[2])) & rxd[3]) & rxd[4]) & (~ rxd[5])) & rxd[6]) & (~ rxd[7])), n0O01O = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOi_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & rxd[0]) & (~ rxd[1])) & rxd[2]) & (~ rxd[3])) & rxd[4]) & rxd[5]) & (~ rxd[6])) & (~ rxd[7])) & (~ (n0OlOi ^ wire_nlil_dataout))) & (~ (n0OlOi ^ wire_nlll_dataout))) & (~ (n0OlOi ^ wire_nllO_dataout))) & (~ (n0OlOi ^ wire_nlOl_dataout))), n0O0ii = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & (~ rxd[0])) & (~ rxd[1])) & rxd[2]) & (~ rxd[3])) & rxd[4]) & (~ rxd[5])) & (~ rxd[6])) & (~ rxd[7])), n0O0il = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & rxd[0]) & rxd[1]) & (~ rxd[2])) & (~ rxd[3])) & rxd[4]) & rxd[5]) & (~ rxd[6])) & rxd[7]) & (~ (n0OlOi ^ wire_nlli_dataout))) & (~ (n0OlOi ^ wire_nllO_dataout))), n0O0iO = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & rxd[0]) & rxd[1]) & rxd[2]) & rxd[3]) & (~ rxd[4])) & (~ rxd[5])) & (~ rxd[6])) & rxd[7]), n0O0li = ((((((((((((((((~ wire_nlOl_dataout) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & rxd[0]) & rxd[1]) & (~ rxd[2])) & rxd[3]) & (~ rxd[4])) & rxd[5]) & rxd[6]) & (~ rxd[7])) & (~ (n0OlOi ^ wire_nlil_dataout))) & (~ (n0OlOi ^ wire_nliO_dataout))) & (~ (n0OlOi ^ wire_nlli_dataout))) & (~ (n0OlOi ^ wire_nlll_dataout))) & (~ (n0OlOi ^ wire_nlOO_dataout))), n0O0ll = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & rxd[0]) & rxd[1]) & rxd[2]) & (~ rxd[3])) & (~ rxd[4])) & (~ rxd[5])) & rxd[6]) & (~ rxd[7])), n0O0lO = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & rxd[0]) & rxd[1]) & (~ rxd[2])) & (~ rxd[3])) & (~ rxd[4])) & rxd[5]) & (~ rxd[6])) & (~ rxd[7])) & (~ (n0OlOi ^ wire_nlil_dataout))) & (~ (n0OlOi ^ wire_nliO_dataout))) & (~ (n0OlOi ^ wire_nlli_dataout))) & (~ (n0OlOi ^ wire_nlOl_dataout))), n0O0Oi = ((((((((((((((((~ wire_nlOO_dataout) & (~ wire_nlOl_dataout)) & (~ wire_nlOi_dataout)) & (~ wire_nllO_dataout)) & (~ wire_nlll_dataout)) & (~ wire_nlli_dataout)) & (~ wire_nliO_dataout)) & (~ wire_nlil_dataout)) & rxd[0]) & rxd[1]) & rxd[2]) & (~ rxd[3])) & rxd[4]) & (~ rxd[5])) & rxd[6]) & rxd[7]), n0O0Ol = ((((((((((((((((~ wire_nlOi_dataout) & (~ wire_nlll_dataout)) & (~ rxd[0])) & rxd[1]) & rxd[2]) & rxd[3]) & rxd[4]) & rxd[5]) & (~ rxd[6])) & rxd[7]) & (~ (n0OlOi ^ wire_nlil_dataout))) & (~ (n0OlOi ^ wire_nliO_dataout))) & (~ (n0OlOi ^ wire_nlli_dataout))) & (~ (n0OlOi ^ wire_nllO_dataout))) & (~ (n0OlOi ^ wire_nlOl_dataout))) & (~ (n0OlOi ^ wire_nlOO_dataout))), n0O0OO = (n0Oi0l & n0Oi1i), n0O1il = ((~ rxc[0]) | (~ n0O1iO)), n0O1iO = (((((((rxd[0] & (~ rxd[1])) & rxd[2]) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]), n0O1li = (((((((rxd[0] & (~ rxd[1])) & (~ rxd[2])) & rxd[3]) & rxd[4]) & (~ rxd[5])) & rxd[6]) & (~ rxd[7])), n0O1ll = (((((((rxd[0] & (~ rxd[1])) & rxd[2]) & (~ rxd[3])) & (~ rxd[4])) & (~ rxd[5])) & (~ rxd[6])) & (~ rxd[7])), n0O1lO = (((((((rxd[0] & (~ rxd[1])) & (~ rxd[2])) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & (~ rxd[7])), n0O1Oi = (((~ n0O01i) | (~ (wire_nlii_dataout & (~ rxc[0])))) | (~ (n0O1Ol26 ^ n0O1Ol25))), n0Oi0l = (((((((rxd[0] & (~ rxd[1])) & rxd[2]) & (~ rxd[3])) & rxd[4]) & (~ rxd[5])) & rxd[6]) & (~ rxd[7])), n0Oi1i = (rcxpat_chnl_sel[0] & rcxpat_chnl_sel[1]), n0Oi1l = ((((n0OiiO | n0Oiil) | (~ (n0Oi0O22 ^ n0Oi0O21))) & n0Oi0l) & (n0Oi1O24 ^ n0Oi1O23)), n0Oiil = ((~ rcxpat_chnl_sel[0]) & rcxpat_chnl_sel[1]), n0OiiO = (rcxpat_chnl_sel[0] & (~ rcxpat_chnl_sel[1])), n0Oili = (rxc[0] & (n0OilO & n0Oill)), n0Oill = ((~ rcxpat_chnl_sel[0]) & (~ rcxpat_chnl_sel[1])), n0OilO = (((((((rxd[0] & rxd[1]) & (~ rxd[2])) & rxd[3]) & rxd[4]) & rxd[5]) & rxd[6]) & rxd[7]), n0OiOl = 1'b1, n0Olli = (((~ rbist_sel[0]) & (~ rbist_sel[1])) & (n0Ol0i12 ^ n0Ol0i11)), n0Olll = (rbist_sel[0] & (~ rbist_sel[1])), n0OllO = (((~ rbist_sel[0]) & rbist_sel[1]) & (n0Ol1l14 ^ n0Ol1l13)), n0OlOi = (n0OlOl | (rpmadwidth_rx & rpma_doublewidth_rx)), n0OlOl = (((rpmadwidth_rx & (~ rpma_doublewidth_rx)) & rdwidth_rx) & (n0OlOO6 ^ n0OlOO5)), selftest_done = wire_nl1l_dataout, selftest_err = wire_nl1i_dataout; endmodule //stratixiv_hssi_rx_digi_bist_ver //synopsys translate_on //VALID FILE //IP Functional Simulation Model //VERSION_BEGIN 12.0 cbx_mgl 2012:05:31:20:09:47:SJ cbx_simgen 2012:05:31:20:08:35:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 // Copyright (C) 1991-2012 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // You may only use these simulation model output files for simulation // purposes and expressly not for synthesis or any other purposes (in which // event Altera disclaims all warranties of any kind). //synopsys translate_off //synthesis_resources = lut 98 mux21 49 oper_add 3 oper_selector 7 `timescale 1 ps / 1 ps module stratixiv_hssi_rx_digi_cdr_ctrl ( adata, adata_valid, early_eios, eidle_exit, eiosdetect_int, gen2ngen1, gen2ngen1_bundle, inferred_rxvalid, ltr, pipe_loopbk, pld_ltr, rcdr_ctrl_en, rcid_en, rcvd_clk, rindv_rx, rmask_count, rrxvalid_mask, rwait_count, rxpcs_reset_int, sigdet) /* synthesis synthesis_clearbox=1 */; input [9:0] adata; input adata_valid; output early_eios; output eidle_exit; output eiosdetect_int; input gen2ngen1; input gen2ngen1_bundle; output inferred_rxvalid; output ltr; input pipe_loopbk; input pld_ltr; input rcdr_ctrl_en; input rcid_en; input rcvd_clk; input rindv_rx; input [9:0] rmask_count; input rrxvalid_mask; input [7:0] rwait_count; input rxpcs_reset_int; input sigdet; reg n0l0O43; reg n0l0O44; reg n0l1i45; reg n0l1i46; reg n0lli41; reg n0lli42; reg n0lOO39; reg n0lOO40; reg n0O0i35; reg n0O0i36; reg n0O0l33; reg n0O0l34; reg n0O0O31; reg n0O0O32; reg n0O1l37; reg n0O1l38; reg n0OiO29; reg n0OiO30; reg n0Oll27; reg n0Oll28; reg n0OOi25; reg n0OOi26; reg n0OOO23; reg n0OOO24; reg ni01i3; reg ni01i4; reg ni01O1; reg ni01O2; reg ni10i19; reg ni10i20; reg ni10l17; reg ni10l18; reg ni11O21; reg ni11O22; reg ni1ii15; reg ni1ii16; reg ni1iO13; reg ni1iO14; reg ni1lO11; reg ni1lO12; reg ni1Oi10; reg ni1Oi9; reg ni1Ol7; reg ni1Ol8; reg ni1OO5; reg ni1OO6; reg n10O; reg n11O; reg n1ii; reg n1il; reg n1iO; reg n1li; reg n1ll; reg n1lO; reg n1Oi; reg n1Ol; reg n1OO; reg ni0li; reg ni0Oi; reg nii0i; reg nii0O; reg niili; reg niOOO; reg nl; reg nl0il; reg nl0iO; reg nl0li; reg nl0ll; reg nl0lO; reg nl0Oi; reg nl0Ol; reg nl0OO; reg nl10O; reg nl11i; reg nl11l; reg nl11O; reg nl1ii; reg nl1il; reg nl1iO; reg nl1li; reg nl1ll; reg nli0O; reg nli1i; reg nll0l; reg nll0O; reg nll1l; reg nllii; reg nllil; reg nlliO; reg nllli; reg nllll; reg nlllO; reg nlO; wire wire_ni_CLRN; reg nilil; reg nilii_clk_prev; wire wire_nilii_PRN; wire wire_nilii_ENA; reg niiii; reg niiil; reg niiiO; reg nl10l; reg nl10i_clk_prev; wire wire_nl10i_CLRN; wire wire_n00i_dataout; wire wire_n00l_dataout; wire wire_n00O_dataout; wire wire_n01i_dataout; wire wire_n01l_dataout; wire wire_n01O_dataout; wire wire_n0ii_dataout; wire wire_n0il_dataout; wire wire_n0iO_dataout; wire wire_n0li_dataout; wire wire_n10i_dataout; wire wire_n10l_dataout; wire wire_ni0ll_dataout; wire wire_nii1i_dataout; wire wire_nil0l_dataout; wire wire_nil1l_dataout; wire wire_nilOi_dataout; wire wire_nilOl_dataout; wire wire_niO1i_dataout; wire wire_niO1l_dataout; wire wire_niOii_dataout; wire wire_niOil_dataout; wire wire_niOiO_dataout; wire wire_niOli_dataout; wire wire_niOll_dataout; wire wire_nl00i_dataout; wire wire_nl00l_dataout; wire wire_nl00O_dataout; wire wire_nl01i_dataout; wire wire_nl01l_dataout; wire wire_nl01O_dataout; wire wire_nl1lO_dataout; wire wire_nl1Oi_dataout; wire wire_nl1Ol_dataout; wire wire_nl1OO_dataout; wire wire_nli1l_dataout; wire wire_nli1O_dataout; wire wire_nliii_dataout; wire wire_nll0i_dataout; wire wire_nll1O_dataout; wire wire_nllOi_dataout; wire wire_nllOl_dataout; wire wire_nllOO_dataout; wire wire_nlO0i_dataout; wire wire_nlO0l_dataout; wire wire_nlO1i_dataout; wire wire_nlO1l_dataout; wire wire_nlO1O_dataout; wire wire_nO_dataout; wire [9:0] wire_n0ll_o; wire [4:0] wire_nl0ii_o; wire [7:0] wire_nlO0O_o; wire wire_niill_o; wire wire_niiOi_o; wire wire_niiOO_o; wire wire_nil1i_o; wire wire_nil1O_o; wire wire_niliO_o; wire wire_nilli_o; wire n0ilO; wire n0iOi; wire n0iOl; wire n0iOO; wire n0l0i; wire n0l0l; wire n0l1l; wire n0l1O; wire n0lil; wire n0liO; wire n0llO; wire n0lOi; wire n0lOl; wire n0Oil; wire ni01l; wire ni11l; wire ni1ll; initial n0l0O43 = 0; always @ ( posedge rcvd_clk) n0l0O43 <= n0l0O44; event n0l0O43_event; initial #1 ->n0l0O43_event; always @(n0l0O43_event) n0l0O43 <= {1{1'b1}}; initial n0l0O44 = 0; always @ ( posedge rcvd_clk) n0l0O44 <= n0l0O43; initial n0l1i45 = 0; always @ ( posedge rcvd_clk) n0l1i45 <= n0l1i46; event n0l1i45_event; initial #1 ->n0l1i45_event; always @(n0l1i45_event) n0l1i45 <= {1{1'b1}}; initial n0l1i46 = 0; always @ ( posedge rcvd_clk) n0l1i46 <= n0l1i45; initial n0lli41 = 0; always @ ( posedge rcvd_clk) n0lli41 <= n0lli42; event n0lli41_event; initial #1 ->n0lli41_event; always @(n0lli41_event) n0lli41 <= {1{1'b1}}; initial n0lli42 = 0; always @ ( posedge rcvd_clk) n0lli42 <= n0lli41; initial n0lOO39 = 0; always @ ( posedge rcvd_clk) n0lOO39 <= n0lOO40; event n0lOO39_event; initial #1 ->n0lOO39_event; always @(n0lOO39_event) n0lOO39 <= {1{1'b1}}; initial n0lOO40 = 0; always @ ( posedge rcvd_clk) n0lOO40 <= n0lOO39; initial n0O0i35 = 0; always @ ( posedge rcvd_clk) n0O0i35 <= n0O0i36; event n0O0i35_event; initial #1 ->n0O0i35_event; always @(n0O0i35_event) n0O0i35 <= {1{1'b1}}; initial n0O0i36 = 0; always @ ( posedge rcvd_clk) n0O0i36 <= n0O0i35; initial n0O0l33 = 0; always @ ( posedge rcvd_clk) n0O0l33 <= n0O0l34; event n0O0l33_event; initial #1 ->n0O0l33_event; always @(n0O0l33_event) n0O0l33 <= {1{1'b1}}; initial n0O0l34 = 0; always @ ( posedge rcvd_clk) n0O0l34 <= n0O0l33; initial n0O0O31 = 0; always @ ( posedge rcvd_clk) n0O0O31 <= n0O0O32; event n0O0O31_event; initial #1 ->n0O0O31_event; always @(n0O0O31_event) n0O0O31 <= {1{1'b1}}; initial n0O0O32 = 0; always @ ( posedge rcvd_clk) n0O0O32 <= n0O0O31; initial n0O1l37 = 0; always @ ( posedge rcvd_clk) n0O1l37 <= n0O1l38; event n0O1l37_event; initial #1 ->n0O1l37_event; always @(n0O1l37_event) n0O1l37 <= {1{1'b1}}; initial n0O1l38 = 0; always @ ( posedge rcvd_clk) n0O1l38 <= n0O1l37; initial n0OiO29 = 0; always @ ( posedge rcvd_clk) n0OiO29 <= n0OiO30; event n0OiO29_event; initial #1 ->n0OiO29_event; always @(n0OiO29_event) n0OiO29 <= {1{1'b1}}; initial n0OiO30 = 0; always @ ( posedge rcvd_clk) n0OiO30 <= n0OiO29; initial n0Oll27 = 0; always @ ( posedge rcvd_clk) n0Oll27 <= n0Oll28; event n0Oll27_event; initial #1 ->n0Oll27_event; always @(n0Oll27_event) n0Oll27 <= {1{1'b1}}; initial n0Oll28 = 0; always @ ( posedge rcvd_clk) n0Oll28 <= n0Oll27; initial n0OOi25 = 0; always @ ( posedge rcvd_clk) n0OOi25 <= n0OOi26; event n0OOi25_event; initial #1 ->n0OOi25_event; always @(n0OOi25_event) n0OOi25 <= {1{1'b1}}; initial n0OOi26 = 0; always @ ( posedge rcvd_clk) n0OOi26 <= n0OOi25; initial n0OOO23 = 0; always @ ( posedge rcvd_clk) n0OOO23 <= n0OOO24; event n0OOO23_event; initial #1 ->n0OOO23_event; always @(n0OOO23_event) n0OOO23 <= {1{1'b1}}; initial n0OOO24 = 0; always @ ( posedge rcvd_clk) n0OOO24 <= n0OOO23; initial ni01i3 = 0; always @ ( posedge rcvd_clk) ni01i3 <= ni01i4; event ni01i3_event; initial #1 ->ni01i3_event; always @(ni01i3_event) ni01i3 <= {1{1'b1}}; initial ni01i4 = 0; always @ ( posedge rcvd_clk) ni01i4 <= ni01i3; initial ni01O1 = 0; always @ ( posedge rcvd_clk) ni01O1 <= ni01O2; event ni01O1_event; initial #1 ->ni01O1_event; always @(ni01O1_event) ni01O1 <= {1{1'b1}}; initial ni01O2 = 0; always @ ( posedge rcvd_clk) ni01O2 <= ni01O1; initial ni10i19 = 0; always @ ( posedge rcvd_clk) ni10i19 <= ni10i20; event ni10i19_event; initial #1 ->ni10i19_event; always @(ni10i19_event) ni10i19 <= {1{1'b1}}; initial ni10i20 = 0; always @ ( posedge rcvd_clk) ni10i20 <= ni10i19; initial ni10l17 = 0; always @ ( posedge rcvd_clk) ni10l17 <= ni10l18; event ni10l17_event; initial #1 ->ni10l17_event; always @(ni10l17_event) ni10l17 <= {1{1'b1}}; initial ni10l18 = 0; always @ ( posedge rcvd_clk) ni10l18 <= ni10l17; initial ni11O21 = 0; always @ ( posedge rcvd_clk) ni11O21 <= ni11O22; event ni11O21_event; initial #1 ->ni11O21_event; always @(ni11O21_event) ni11O21 <= {1{1'b1}}; initial ni11O22 = 0; always @ ( posedge rcvd_clk) ni11O22 <= ni11O21; initial ni1ii15 = 0; always @ ( posedge rcvd_clk) ni1ii15 <= ni1ii16; event ni1ii15_event; initial #1 ->ni1ii15_event; always @(ni1ii15_event) ni1ii15 <= {1{1'b1}}; initial ni1ii16 = 0; always @ ( posedge rcvd_clk) ni1ii16 <= ni1ii15; initial ni1iO13 = 0; always @ ( posedge rcvd_clk) ni1iO13 <= ni1iO14; event ni1iO13_event; initial #1 ->ni1iO13_event; always @(ni1iO13_event) ni1iO13 <= {1{1'b1}}; initial ni1iO14 = 0; always @ ( posedge rcvd_clk) ni1iO14 <= ni1iO13; initial ni1lO11 = 0; always @ ( posedge rcvd_clk) ni1lO11 <= ni1lO12; event ni1lO11_event; initial #1 ->ni1lO11_event; always @(ni1lO11_event) ni1lO11 <= {1{1'b1}}; initial ni1lO12 = 0; always @ ( posedge rcvd_clk) ni1lO12 <= ni1lO11; initial ni1Oi10 = 0; always @ ( posedge rcvd_clk) ni1Oi10 <= ni1Oi9; initial ni1Oi9 = 0; always @ ( posedge rcvd_clk) ni1Oi9 <= ni1Oi10; event ni1Oi9_event; initial #1 ->ni1Oi9_event; always @(ni1Oi9_event) ni1Oi9 <= {1{1'b1}}; initial ni1Ol7 = 0; always @ ( posedge rcvd_clk) ni1Ol7 <= ni1Ol8; event ni1Ol7_event; initial #1 ->ni1Ol7_event; always @(ni1Ol7_event) ni1Ol7 <= {1{1'b1}}; initial ni1Ol8 = 0; always @ ( posedge rcvd_clk) ni1Ol8 <= ni1Ol7; initial ni1OO5 = 0; always @ ( posedge rcvd_clk) ni1OO5 <= ni1OO6; event ni1OO5_event; initial #1 ->ni1OO5_event; always @(ni1OO5_event) ni1OO5 <= {1{1'b1}}; initial ni1OO6 = 0; always @ ( posedge rcvd_clk) ni1OO6 <= ni1OO5; initial begin n10O = 0; n11O = 0; n1ii = 0; n1il = 0; n1iO = 0; n1li = 0; n1ll = 0; n1lO = 0; n1Oi = 0; n1Ol = 0; n1OO = 0; ni0li = 0; ni0Oi = 0; nii0i = 0; nii0O = 0; niili = 0; niOOO = 0; nl = 0; nl0il = 0; nl0iO = 0; nl0li = 0; nl0ll = 0; nl0lO = 0; nl0Oi = 0; nl0Ol = 0; nl0OO = 0; nl10O = 0; nl11i = 0; nl11l = 0; nl11O = 0; nl1ii = 0; nl1il = 0; nl1iO = 0; nl1li = 0; nl1ll = 0; nli0O = 0; nli1i = 0; nll0l = 0; nll0O = 0; nll1l = 0; nllii = 0; nllil = 0; nlliO = 0; nllli = 0; nllll = 0; nlllO = 0; nlO = 0; end always @ ( posedge rcvd_clk or negedge wire_ni_CLRN) begin if (wire_ni_CLRN == 1'b0) begin n10O <= 0; n11O <= 0; n1ii <= 0; n1il <= 0; n1iO <= 0; n1li <= 0; n1ll <= 0; n1lO <= 0; n1Oi <= 0; n1Ol <= 0; n1OO <= 0; ni0li <= 0; ni0Oi <= 0; nii0i <= 0; nii0O <= 0; niili <= 0; niOOO <= 0; nl <= 0; nl0il <= 0; nl0iO <= 0; nl0li <= 0; nl0ll <= 0; nl0lO <= 0; nl0Oi <= 0; nl0Ol <= 0; nl0OO <= 0; nl10O <= 0; nl11i <= 0; nl11l <= 0; nl11O <= 0; nl1ii <= 0; nl1il <= 0; nl1iO <= 0; nl1li <= 0; nl1ll <= 0; nli0O <= 0; nli1i <= 0; nll0l <= 0; nll0O <= 0; nll1l <= 0; nllii <= 0; nllil <= 0; nlliO <= 0; nllli <= 0; nllll <= 0; nlllO <= 0; nlO <= 0; end else begin n10O <= wire_n10i_dataout; n11O <= wire_n01i_dataout; n1ii <= wire_n01l_dataout; n1il <= wire_n01O_dataout; n1iO <= wire_n00i_dataout; n1li <= wire_n00l_dataout; n1ll <= wire_n00O_dataout; n1lO <= wire_n0ii_dataout; n1Oi <= wire_n0il_dataout; n1Ol <= wire_n0iO_dataout; n1OO <= wire_n0li_dataout; ni0li <= wire_ni0ll_dataout; ni0Oi <= ni0li; nii0i <= nii0O; nii0O <= wire_nil0l_dataout; niili <= wire_niill_o; niOOO <= wire_niiOi_o; nl <= wire_nO_dataout; nl0il <= pipe_loopbk; nl0iO <= nl0li; nl0li <= nl0ll; nl0ll <= nl0lO; nl0lO <= nl0Oi; nl0Oi <= nl0Ol; nl0Ol <= nl0OO; nl0OO <= sigdet; nl10O <= wire_nl1lO_dataout; nl11i <= wire_niiOO_o; nl11l <= wire_nil1i_o; nl11O <= wire_nil1l_dataout; nl1ii <= wire_nl1Oi_dataout; nl1il <= wire_nl1Ol_dataout; nl1iO <= wire_nl1OO_dataout; nl1li <= wire_nl01i_dataout; nl1ll <= nl0il; nli0O <= wire_niliO_o; nli1i <= wire_nilli_o; nll0l <= wire_nll1O_dataout; nll0O <= wire_nllOl_dataout; nll1l <= wire_nllOi_dataout; nllii <= wire_nllOO_dataout; nllil <= wire_nlO1i_dataout; nlliO <= wire_nlO1l_dataout; nllli <= wire_nlO1O_dataout; nllll <= wire_nlO0i_dataout; nlllO <= wire_nlO0l_dataout; nlO <= nl; end end assign wire_ni_CLRN = ((ni01O2 ^ ni01O1) & (~ rxpcs_reset_int)); initial begin nilil = 0; end always @ (rcvd_clk or wire_nilii_PRN or rxpcs_reset_int) begin if (wire_nilii_PRN == 1'b0) begin nilil <= 1; end else if (rxpcs_reset_int == 1'b1) begin nilil <= 0; end else if (wire_nilii_ENA == 1'b1) if (rcvd_clk != nilii_clk_prev && rcvd_clk == 1'b1) begin nilil <= ni01l; end nilii_clk_prev <= rcvd_clk; end assign wire_nilii_ENA = (nl0li & (~ nl0iO)), wire_nilii_PRN = (n0l1i46 ^ n0l1i45); initial begin niiii = 0; niiil = 0; niiiO = 0; nl10l = 0; end always @ (rcvd_clk or rxpcs_reset_int or wire_nl10i_CLRN) begin if (rxpcs_reset_int == 1'b1) begin niiii <= 1; niiil <= 1; niiiO <= 1; nl10l <= 1; end else if (wire_nl10i_CLRN == 1'b0) begin niiii <= 0; niiil <= 0; niiiO <= 0; nl10l <= 0; end else if (rcvd_clk != nl10i_clk_prev && rcvd_clk == 1'b1) begin niiii <= niiil; niiil <= niiiO; niiiO <= (~ (nl11i | niOOO)); nl10l <= wire_nil1O_o; end nl10i_clk_prev <= rcvd_clk; end assign wire_nl10i_CLRN = (n0O0i36 ^ n0O0i35); event niiii_event; event niiil_event; event niiiO_event; event nl10l_event; initial #1 ->niiii_event; initial #1 ->niiil_event; initial #1 ->niiiO_event; initial #1 ->nl10l_event; always @(niiii_event) niiii <= 1; always @(niiil_event) niiil <= 1; always @(niiiO_event) niiiO <= 1; always @(nl10l_event) nl10l <= 1; and(wire_n00i_dataout, wire_n0ll_o[3], ~((~ niOOO))); and(wire_n00l_dataout, wire_n0ll_o[4], ~((~ niOOO))); and(wire_n00O_dataout, wire_n0ll_o[5], ~((~ niOOO))); and(wire_n01i_dataout, wire_n0ll_o[0], ~((~ niOOO))); and(wire_n01l_dataout, wire_n0ll_o[1], ~((~ niOOO))); and(wire_n01O_dataout, wire_n0ll_o[2], ~((~ niOOO))); and(wire_n0ii_dataout, wire_n0ll_o[6], ~((~ niOOO))); and(wire_n0il_dataout, wire_n0ll_o[7], ~((~ niOOO))); and(wire_n0iO_dataout, wire_n0ll_o[8], ~((~ niOOO))); and(wire_n0li_dataout, wire_n0ll_o[9], ~((~ niOOO))); and(wire_n10i_dataout, wire_n10l_dataout, ~((~ niOOO))); or(wire_n10l_dataout, n10O, ni1ll); and(wire_ni0ll_dataout, adata_valid, (n0iOi | n0ilO)); and(wire_nii1i_dataout, adata_valid, (n0iOO | n0iOl)); and(wire_nil0l_dataout, wire_nii1i_dataout, (nl11O | nl11l)); and(wire_nil1l_dataout, wire_niOil_dataout, nl10l); and(wire_nilOi_dataout, (~ n10O), ~(n0liO)); and(wire_nilOl_dataout, n10O, ~(n0liO)); and(wire_niO1i_dataout, (~ n0l0l), ~(n0lil)); and(wire_niO1l_dataout, n0l0l, ~(n0lil)); and(wire_niOii_dataout, wire_niOli_dataout, ~(n0lOl)); and(wire_niOil_dataout, n0llO, ~(n0lOl)); and(wire_niOiO_dataout, wire_niOll_dataout, ~(n0lOl)); and(wire_niOli_dataout, n0lOi, ~(n0llO)); and(wire_niOll_dataout, (~ n0lOi), ~(n0llO)); assign wire_nl00i_dataout = (niili === 1'b1) ? wire_nl0ii_o[2] : nl1il; assign wire_nl00l_dataout = (niili === 1'b1) ? wire_nl0ii_o[3] : nl1iO; assign wire_nl00O_dataout = (niili === 1'b1) ? wire_nl0ii_o[4] : nl1li; and(wire_nl01i_dataout, wire_nl00O_dataout, ~((~ niili))); assign wire_nl01l_dataout = (niili === 1'b1) ? wire_nl0ii_o[0] : nl10O; assign wire_nl01O_dataout = (niili === 1'b1) ? wire_nl0ii_o[1] : nl1ii; and(wire_nl1lO_dataout, wire_nl01l_dataout, ~((~ niili))); and(wire_nl1Oi_dataout, wire_nl01O_dataout, ~((~ niili))); and(wire_nl1Ol_dataout, wire_nl00i_dataout, ~((~ niili))); and(wire_nl1OO_dataout, wire_nl00l_dataout, ~((~ niili))); or(wire_nli1l_dataout, niiii, ~(rrxvalid_mask)); and(wire_nli1O_dataout, nli1i, ((rcid_en & (~ n0Oil)) & (n0O0O32 ^ n0O0O31))); assign wire_nliii_dataout = (rcdr_ctrl_en === 1'b1) ? nli0O : pld_ltr; or(wire_nll0i_dataout, nll0l, ni11l); and(wire_nll1O_dataout, wire_nll0i_dataout, ~((~ nl11i))); and(wire_nllOi_dataout, wire_nlO0O_o[0], ~((~ nl11i))); and(wire_nllOl_dataout, wire_nlO0O_o[1], ~((~ nl11i))); and(wire_nllOO_dataout, wire_nlO0O_o[2], ~((~ nl11i))); and(wire_nlO0i_dataout, wire_nlO0O_o[6], ~((~ nl11i))); and(wire_nlO0l_dataout, wire_nlO0O_o[7], ~((~ nl11i))); and(wire_nlO1i_dataout, wire_nlO0O_o[3], ~((~ nl11i))); and(wire_nlO1l_dataout, wire_nlO0O_o[4], ~((~ nl11i))); and(wire_nlO1O_dataout, wire_nlO0O_o[5], ~((~ nl11i))); assign wire_nO_dataout = (rindv_rx === 1'b1) ? gen2ngen1 : gen2ngen1_bundle; oper_add n0ll ( .a({((ni1lO12 ^ ni1lO11) & n1OO), n1Ol, ((ni1Oi10 ^ ni1Oi9) & n1Oi), ((ni1Ol8 ^ ni1Ol7) & n1lO), n1ll, n1li, ((ni1OO6 ^ ni1OO5) & n1iO), n1il, n1ii, ((ni01i4 ^ ni01i3) & n11O)}), .b({{9{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_n0ll_o)); defparam n0ll.sgate_representation = 0, n0ll.width_a = 10, n0ll.width_b = 10, n0ll.width_o = 10; oper_add nl0ii ( .a({nl1li, nl1iO, nl1il, nl1ii, ((n0O0l34 ^ n0O0l33) & nl10O)}), .b({{4{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_nl0ii_o)); defparam nl0ii.sgate_representation = 0, nl0ii.width_a = 5, nl0ii.width_b = 5, nl0ii.width_o = 5; oper_add nlO0O ( .a({nlllO, nllll, nllli, nlliO, ((ni11O22 ^ ni11O21) & nllil), ((ni10i20 ^ ni10i19) & nllii), nll0O, nll1l}), .b({{7{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_nlO0O_o)); defparam nlO0O.sgate_representation = 0, nlO0O.width_a = 8, nlO0O.width_b = 8, nlO0O.width_o = 8; oper_selector niill ( .data({1'b0, {2{wire_niO1l_dataout}}, (~ n0l1l)}), .o(wire_niill_o), .sel({((nl10l | nl11i) | niOOO), nl11O, nl11l, niili})); defparam niill.width_data = 4, niill.width_sel = 4; oper_selector niiOi ( .data({1'b0, n0l0i, wire_nilOi_dataout}), .o(wire_niiOi_o), .sel({(((nl10l | nl11O) | nl11l) | niili), nl11i, niOOO})); defparam niiOi.width_data = 3, niiOi.width_sel = 3; oper_selector niiOO ( .data({n0lOl, {2{n0lil}}, (~ n0l0i), n0liO, n0l1l}), .o(wire_niiOO_o), .sel({nl10l, nl11O, nl11l, nl11i, niOOO, niili})); defparam niiOO.width_data = 6, niiOO.width_sel = 6; oper_selector nil1i ( .data({wire_niOii_dataout, wire_niO1i_dataout, 1'b0}), .o(wire_nil1i_o), .sel({nl10l, nl11O, n0l1O})); defparam nil1i.width_data = 3, nil1i.width_sel = 3; oper_selector nil1O ( .data({wire_niOiO_dataout, 1'b0, wire_niO1i_dataout, wire_nilOl_dataout}), .o(wire_nil1O_o), .sel({nl10l, ((nl11O | nl11i) | niili), nl11l, niOOO})); defparam nil1O.width_data = 4, nil1O.width_sel = 4; oper_selector niliO ( .data({n0lOl, {2{n0lil}}, (~ n0l0i), n0liO, n0l1l}), .o(wire_niliO_o), .sel({nl10l, nl11O, nl11l, nl11i, niOOO, niili})); defparam niliO.width_data = 6, niliO.width_sel = 6; oper_selector nilli ( .data({(n0llO | n0lOi), wire_niO1i_dataout, 1'b0}), .o(wire_nilli_o), .sel({nl10l, nl11O, n0l1O})); defparam nilli.width_data = 3, nilli.width_sel = 3; assign early_eios = wire_nli1O_dataout, eidle_exit = niOOO, eiosdetect_int = nii0i, inferred_rxvalid = wire_nli1l_dataout, ltr = wire_nliii_dataout, n0ilO = (((((((((adata[0] & adata[1]) & (~ adata[2])) & (~ adata[3])) & (~ adata[4])) & (~ adata[5])) & (~ adata[6])) & adata[7]) & (~ adata[8])) & adata[9]), n0iOi = ((((((((((~ adata[0]) & (~ adata[1])) & adata[2]) & adata[3]) & adata[4]) & adata[5]) & adata[6]) & (~ adata[7])) & adata[8]) & (~ adata[9])), n0iOl = (((((((((adata[0] & adata[1]) & (~ adata[2])) & (~ adata[3])) & (~ adata[4])) & (~ adata[5])) & adata[6]) & adata[7]) & (~ adata[8])) & (~ adata[9])), n0iOO = ((((((((((~ adata[0]) & (~ adata[1])) & adata[2]) & adata[3]) & adata[4]) & adata[5]) & (~ adata[6])) & (~ adata[7])) & adata[8]) & adata[9]), n0l0i = (nl0iO & nll0l), n0l0l = ((wire_nii1i_dataout & n0Oil) & (n0l0O44 ^ n0l0O43)), n0l1l = ((((nl1li & nl1iO) & nl1il) & (~ nl1ii)) & nl10O), n0l1O = (((nl11l | nl11i) | niOOO) | niili), n0lil = (n0liO | (wire_nii1i_dataout & (~ nl1ll))), n0liO = (((~ nlO) & (~ nl0iO)) & (n0lli42 ^ n0lli41)), n0llO = (wire_nii1i_dataout & ni0li), n0lOi = (wire_nii1i_dataout & ni0Oi), n0lOl = (((~ nlO) & (((~ nl0iO) & nilil) & (n0O1l38 ^ n0O1l37))) & (n0lOO40 ^ n0lOO39)), n0Oil = (nlO & nl1ll), ni01l = 1'b1, ni11l = ((((((((~ ((rwait_count[0] ^ nll1l) ^ (~ (n0OOO24 ^ n0OOO23)))) & (~ (rwait_count[1] ^ nll0O))) & (~ ((rwait_count[2] ^ nllii) ^ (~ (n0OOi26 ^ n0OOi25))))) & (~ (rwait_count[3] ^ nllil))) & (~ ((rwait_count[4] ^ nlliO) ^ (~ (n0Oll28 ^ n0Oll27))))) & (~ (rwait_count[5] ^ nllli))) & (~ (rwait_count[6] ^ nllll))) & (~ ((rwait_count[7] ^ nlllO) ^ (~ (n0OiO30 ^ n0OiO29))))), ni1ll = ((((((((((~ (rmask_count[0] ^ n11O)) & (~ (rmask_count[1] ^ n1ii))) & (~ (rmask_count[2] ^ n1il))) & (~ ((rmask_count[3] ^ n1iO) ^ (~ (ni1iO14 ^ ni1iO13))))) & (~ (rmask_count[4] ^ n1li))) & (~ (rmask_count[5] ^ n1ll))) & (~ ((rmask_count[6] ^ n1lO) ^ (~ (ni1ii16 ^ ni1ii15))))) & (~ ((rmask_count[7] ^ n1Oi) ^ (~ (ni10l18 ^ ni10l17))))) & (~ (rmask_count[8] ^ n1Ol))) & (~ (rmask_count[9] ^ n1OO))); endmodule //stratixiv_hssi_rx_digi_cdr_ctrl //synopsys translate_on //VALID FILE //IP Functional Simulation Model //VERSION_BEGIN 12.0 cbx_mgl 2012:05:31:20:09:47:SJ cbx_simgen 2012:05:31:20:08:35:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 // Copyright (C) 1991-2012 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // You may only use these simulation model output files for simulation // purposes and expressly not for synthesis or any other purposes (in which // event Altera disclaims all warranties of any kind). //synopsys translate_off //synthesis_resources = lut 529 mux21 1169 oper_add 22 oper_decoder 15 oper_less_than 18 oper_mux 4 stratixiv_hssi_rx_digis_ram20x16_syn 2 `timescale 1 ps / 1 ps module stratixiv_hssi_rx_digi_comp_chnl_top ( align_status, align_status_sync, align_status_sync_0, align_status_sync_2, audi, audi_pre, cg_comp_rd_d_ch0, cg_comp_rd_d_ch1, cg_comp_rd_d_ch2, cg_comp_rd_d_ch3, cg_comp_rd_d_out, cg_comp_wr_ch0, cg_comp_wr_ch1, cg_comp_wr_ch2, cg_comp_wr_ch3, cg_comp_wr_out, clk_1, clk_2, cmpfifourst, comp_curr_st, cudi, cudi_valid, del_cond_met_0, del_cond_met_out, dskwclksel, fifo_cnt, fifo_ovr_0, fifo_ovr_out, fifo_rd_in_comp_0, fifo_rd_in_comp_2, fifo_rd_out_comp, gen2ngen1, gen2ngen1_bundle, hard_reset, inferred_rxvalid, insert_incomplete_0, insert_incomplete_out, is_lane0, latency_comp_0, latency_comp_out, rauto_speed_ena, rclkcmpinsertpad, rclkcmpsq1n, rclkcmpsq1p, rclkcmpsqmd, rcmpfifourst, rdel_threshold, rdenable, rdfifo_almost_empty, rdfifo_almost_full, rdfifo_empty, rdfifo_full, rdwidth_rx, rempty_threshold, rev_loop_data, rfreq_sel, rfull_threshold, rgenericfifo, rindv_rx, rins_threshold, rmatchen, rrx_pipe_enable, rskpsetbased, rstart_threshold, rtruebac2bac, rwa_6g_en, scan_mode, skpos_det, soft_reset, sudi, sudi_pre, sync_status, wrenable) /* synthesis synthesis_clearbox=1 */; input align_status; output align_status_sync; input align_status_sync_0; input align_status_sync_2; input [13:0] audi; input [13:0] audi_pre; input cg_comp_rd_d_ch0; input cg_comp_rd_d_ch1; input cg_comp_rd_d_ch2; input cg_comp_rd_d_ch3; output cg_comp_rd_d_out; input cg_comp_wr_ch0; input cg_comp_wr_ch1; input cg_comp_wr_ch2; input cg_comp_wr_ch3; output cg_comp_wr_out; input clk_1; input clk_2; input cmpfifourst; output [1:0] comp_curr_st; output [31:0] cudi; output cudi_valid; input del_cond_met_0; output del_cond_met_out; input [1:0] dskwclksel; output [4:0] fifo_cnt; input fifo_ovr_0; output fifo_ovr_out; input fifo_rd_in_comp_0; input fifo_rd_in_comp_2; output fifo_rd_out_comp; input gen2ngen1; input gen2ngen1_bundle; input hard_reset; input inferred_rxvalid; input insert_incomplete_0; output insert_incomplete_out; input is_lane0; input latency_comp_0; output latency_comp_out; input rauto_speed_ena; input rclkcmpinsertpad; input [19:0] rclkcmpsq1n; input [19:0] rclkcmpsq1p; input rclkcmpsqmd; input rcmpfifourst; input [4:0] rdel_threshold; input rdenable; output rdfifo_almost_empty; output rdfifo_almost_full; output rdfifo_empty; output rdfifo_full; input rdwidth_rx; input [2:0] rempty_threshold; output [19:0] rev_loop_data; input rfreq_sel; input [4:0] rfull_threshold; input rgenericfifo; input rindv_rx; input [4:0] rins_threshold; input rmatchen; input rrx_pipe_enable; input rskpsetbased; input [2:0] rstart_threshold; input rtruebac2bac; input rwa_6g_en; input scan_mode; output skpos_det; input soft_reset; input [27:0] sudi; input [13:0] sudi_pre; input sync_status; input wrenable; reg nli0O0O61; reg nli0O0O62; reg nliil1i59; reg nliil1i60; reg nliil1l57; reg nliil1l58; reg nliiOOi55; reg nliiOOi56; reg nliiOOl53; reg nliiOOl54; reg nliiOOO51; reg nliiOOO52; reg nlil01l49; reg nlil01l50; reg nlil0li47; reg nlil0li48; reg nlil0Ol45; reg nlil0Ol46; reg nlili0l43; reg nlili0l44; reg nlilill41; reg nlilill42; reg nlililO39; reg nlililO40; reg nliliOi37; reg nliliOi38; reg nliliOl35; reg nliliOl36; reg nliliOO33; reg nliliOO34; reg nlill0l25; reg nlill0l26; reg nlill1i31; reg nlill1i32; reg nlill1l29; reg nlill1l30; reg nlill1O27; reg nlill1O28; reg nlilliO23; reg nlilliO24; reg nlillll21; reg nlillll22; reg nlilO0O15; reg nlilO0O16; reg nlilO1i19; reg nlilO1i20; reg nlilO1O17; reg nlilO1O18; reg nlilOli13; reg nlilOli14; reg nlilOlO11; reg nlilOlO12; reg nlilOOl10; reg nlilOOl9; reg nlilOOO7; reg nlilOOO8; reg nliO10i3; reg nliO10i4; reg nliO11l5; reg nliO11l6; reg nliO1iO1; reg nliO1iO2; reg n0111i; reg n0111l; reg n1000i; reg n1000l; reg n1000O; reg n1001i; reg n1001l; reg n1001O; reg n100ii; reg n100il; reg n100li; reg n100ll; reg n100lO; reg n100Oi; reg n100Ol; reg n100OO; reg n101Ol; reg n101OO; reg n10i0i; reg n10i0l; reg n10i0O; reg n10i1i; reg n10i1l; reg n10i1O; reg n10iii; reg n10iil; reg n10iiO; reg n10ili; reg n10ill; reg n10ilO; reg n10iOl; reg n10iOO; reg n10l0i; reg n10l0l; reg n10l0O; reg n10l1i; reg n10l1l; reg n10l1O; reg n10lii; reg n10lil; reg n10liO; reg n10lli; reg n10lll; reg n10llO; reg n10lOi; reg n10lOl; reg n10lOO; reg n10O1i; reg n10O1l; reg n10O1O; reg n110iO; reg n110li; reg n110ll; reg n110lO; reg n11iil; reg n11iiO; reg n11ili; reg n11ill; reg n11ilO; reg n11iOi; reg n11iOl; reg n11iOO; reg n11O0i; reg n11O0l; reg n11O0O; reg n11O1i; reg n11O1l; reg n11O1O; reg n1l; reg n1liil; reg n1liiO; reg n1lili; reg n1ll1i; reg n1ll1l; reg n1O00i; reg n1O00l; reg n1O01l; reg n1O01O; reg ni0OOi; reg ni0OOl; reg ni0OOO; reg nii00i; reg nii00l; reg nii00O; reg nii01i; reg nii01l; reg nii01O; reg nii0ii; reg nii0il; reg nii0iO; reg nii0ll; reg nii0Ol; reg nii0OO; reg nii10i; reg nii10l; reg nii10O; reg nii11i; reg nii11l; reg nii11O; reg nii1ii; reg nii1il; reg nii1iO; reg nii1li; reg nii1ll; reg nii1lO; reg nii1Oi; reg nii1Ol; reg nii1OO; reg niii1i; reg niOlOl; reg niOlOO; reg niOO0i; reg niOO0l; reg niOO0O; reg niOO1i; reg niOO1l; reg niOO1O; reg niOOii; reg niOOil; reg niOOli; reg niOOll; reg niOOlO; reg niOOOi; reg niOOOl; reg niOOOO; reg nl100i; reg nl100l; reg nl100O; reg nl101i; reg nl101l; reg nl101O; reg nl10ii; reg nl10il; reg nl10iO; reg nl10li; reg nl10ll; reg nl10lO; reg nl10Oi; reg nl10Ol; reg nl10OO; reg nl110i; reg nl110l; reg nl110O; reg nl111i; reg nl111l; reg nl111O; reg nl11ii; reg nl11il; reg nl11iO; reg nl11li; reg nl11ll; reg nl11lO; reg nl11OO; reg nl1i0i; reg nl1i1i; reg nl1i1l; reg nl1i1O; reg nli0il; reg nli0Ol; reg nli0OO; reg nli1ll; reg nli1lO; reg nli1Oi; reg nli1Ol; reg nlii0i; reg nlii0l; reg nlii0O; reg nlii1i; reg nlii1l; reg nliilO; reg nliiOi; reg nlil0i; reg nlil0l; reg nlil0O; reg nlil1O; reg nlilOl; reg nliO01l; reg nliO01O; reg nliO1i; reg nlll; reg nlO00OO; reg nlOi1iO; reg nlOiO0i; reg nlOiO0l; reg nlOiO0O; reg nlOiO1O; reg nlOiOii; reg nlOl0OO; reg nlOli0i; reg nlOli0l; reg nlOli0O; reg nlOli1i; reg nlOli1l; reg nlOli1O; reg nlOliii; reg nlOliil; reg nlOliiO; reg nlOlili; reg nlOlilO; reg nlOliOO; reg nlOll1i; reg nlOll1l; reg n1i_clk_prev; wire wire_n1i_CLRN; wire wire_n1i_PRN; reg n0l0iO; reg ni11ll; reg ni11lO; reg ni11Ol; reg nlliiOO; reg nllil1i; reg nllil1l; reg nlllO0l; reg ni11Oi_clk_prev; wire wire_ni11Oi_CLRN; wire wire_ni11Oi_PRN; reg n0111O; reg n0l00l; reg n0l00O; reg n0l0ii; reg n0l0il; reg n0l0li; reg n0l0ll; reg n0l0lO; reg n0l0Oi; reg n0l0Ol; reg n0l0OO; reg n0li0i; reg n0li0l; reg n0li0O; reg n0li1i; reg n0li1l; reg n0li1O; reg n0liii; reg n0liil; reg n0liiO; reg n0lili; reg n0lill; reg n0lilO; reg n0liOi; reg n0liOl; reg n0O0ll; reg n0O0lO; reg n0O0Oi; reg n0O0Ol; reg n0O0OO; reg n0Oiil; reg n0OiOl; reg n0OiOO; reg n0Ol0i; reg n0Ol0l; reg n0Ol0O; reg n0Ol1l; reg n0Ol1O; reg n0OO1O; reg n0OOli; reg n0OOll; reg n1O; reg ni000i; reg ni000l; reg ni00il; reg ni00iO; reg ni00Oi; reg ni101i; reg ni101l; reg ni110i; reg ni110l; reg ni111i; reg ni111l; reg ni111O; reg ni11OO; reg ni1i0i; reg ni1i0l; reg ni1i0O; reg ni1i1l; reg ni1i1O; reg ni1llO; reg ni1O0i; reg ni1O0l; reg ni1O0O; reg ni1O1l; reg ni1O1O; reg nil; reg nliO00i; reg nliO1l; reg nlli00O; reg nlli0Oi; reg nlli0Ol; reg nlli1ii; reg nlli1il; reg nlli1iO; reg nlli1li; reg nlli1ll; reg nllii0l; reg nllii0O; reg nllii1O; reg nlliiii; reg nlliiil; reg nlliiiO; reg nlliiO; reg nllil0i; reg nllil0l; reg nllil1O; reg nllili; reg nllill; reg nllilO; reg nlliOi; reg nlliOl; reg nlliOO; reg nlll0i; reg nlll0l; reg nlll0O; reg nlll10l; reg nlll10O; reg nlll1i; reg nlll1ii; reg nlll1il; reg nlll1iO; reg nlll1l; reg nlll1li; reg nlll1O; reg nlllii; reg nlllil; reg nllliO; reg nllll0O; reg nlllli; reg nllllii; reg nlllliO; reg nlllll; reg nllllli; reg nllllO; reg nlllO0i; reg nlllO0O; reg nlllO1i; reg nlllO1l; reg nlllO1O; reg nlllOi; reg nlllOii; reg nlllOil; reg nlllOiO; reg nlllOl; reg nlllOli; reg nlllOll; reg nlllOlO; reg nlllOO; reg nlllOOi; reg nlllOOl; reg nlllOOO; reg nllO0i; reg nllO0l; reg nllO10i; reg nllO10l; reg nllO10O; reg nllO11i; reg nllO11l; reg nllO11O; reg nllO1i; reg nllO1ii; reg nllO1il; reg nllO1iO; reg nllO1l; reg nllO1li; reg nllO1O; reg nllOOi; reg nllOOl; reg nlO00ii; reg nlO00li; reg nlO00ll; reg nlO00lO; reg nlO00Oi; reg nlO00Ol; reg nlO011i; reg nlO011l; reg nlO01l; reg nlO01O; reg nlO10li; reg nlO10ll; reg nlO10lO; reg nlO10Oi; reg nlO1i0O; reg nlO1Oii; reg nlO1OiO; reg nlO1OOi; reg nlO1OOl; reg nlO1OOO; wire wire_nii_CLRN; reg ni00Ol; reg ni0liO; reg ni0lli; reg ni0lll; reg ni0llO; reg ni0lOi; reg ni0lOl; reg ni0lOO; reg ni0O0i; reg ni0O0l; reg ni0O0O; reg ni0O1i; reg ni0O1l; reg ni0O1O; reg ni0Oii; reg ni0Oil; reg ni0OiO; reg ni0Oli; reg ni0Oll; reg ni0OlO; reg nii0li; reg nii0Oi; wire wire_nii0lO_CLRN; reg n0Oi1i; reg n0Oi1l; reg niiOlO; reg niiOOi; reg niiOOO; reg nlli10i; reg nlli10l; reg nlli10O; reg nlO10Ol; reg nlO10OO; reg niiOOl_clk_prev; wire wire_niiOOl_CLRN; wire wire_niiOOl_PRN; reg nl0l; reg nO; reg nl_clk_prev; wire wire_nl_CLRN; reg n100iO; reg n10iOi; reg niOOiO; reg nl11Ol; reg n0l00i; reg n0l01l; reg n0l01O; reg n1O00O; reg n1O0ii; reg nli01l; reg nli1OO; reg nlli11i; reg nlli11l; reg nlli11O; wire wire_nli01i_PRN; reg nl0O; reg nlli; reg nlOiOil; reg nlOiOli; reg nlOiOll; reg nlOiOlO; reg nlOiOOi; reg nlOiOOl; reg nlOiOOO; reg nlOl00i; reg nlOl00l; reg nlOl00O; reg nlOl01i; reg nlOl01l; reg nlOl01O; reg nlOl0ii; reg nlOl0il; reg nlOl0iO; reg nlOl0li; reg nlOl0ll; reg nlOl0lO; reg nlOl0Oi; reg nlOl0Ol; reg nlOl10i; reg nlOl10l; reg nlOl10O; reg nlOl11i; reg nlOl11l; reg nlOl11O; reg nlOl1ii; reg nlOl1il; reg nlOl1iO; reg nlOl1li; reg nlOl1ll; reg nlOl1lO; reg nlOl1Oi; reg nlOl1Ol; reg nlOl1OO; reg nlOlill; reg nlOliOl; reg nlOliOi_clk_prev; wire wire_nlOliOi_PRN; wire wire_n00i_dataout; wire wire_n00l_dataout; wire wire_n00O_dataout; wire wire_n0110i_dataout; wire wire_n0110l_dataout; wire wire_n0110O_dataout; wire wire_n01i_dataout; wire wire_n01l_dataout; wire wire_n01O_dataout; wire wire_n0ii_dataout; wire wire_n0il_dataout; wire wire_n0iO_dataout; wire wire_n0li_dataout; wire wire_n0liOO_dataout; wire wire_n0ll_dataout; wire wire_n0ll0i_dataout; wire wire_n0ll0l_dataout; wire wire_n0ll0O_dataout; wire wire_n0ll1i_dataout; wire wire_n0ll1l_dataout; wire wire_n0ll1O_dataout; wire wire_n0llii_dataout; wire wire_n0llil_dataout; wire wire_n0lliO_dataout; wire wire_n0llli_dataout; wire wire_n0llll_dataout; wire wire_n0lllO_dataout; wire wire_n0llOi_dataout; wire wire_n0llOl_dataout; wire wire_n0llOO_dataout; wire wire_n0lO_dataout; wire wire_n0lO0i_dataout; wire wire_n0lO0l_dataout; wire wire_n0lO0O_dataout; wire wire_n0lO1i_dataout; wire wire_n0lO1l_dataout; wire wire_n0lO1O_dataout; wire wire_n0lOii_dataout; wire wire_n0lOil_dataout; wire wire_n0lOiO_dataout; wire wire_n0lOli_dataout; wire wire_n0lOll_dataout; wire wire_n0lOlO_dataout; wire wire_n0lOOi_dataout; wire wire_n0lOOl_dataout; wire wire_n0lOOO_dataout; wire wire_n0O00i_dataout; wire wire_n0O00l_dataout; wire wire_n0O00O_dataout; wire wire_n0O01i_dataout; wire wire_n0O01l_dataout; wire wire_n0O01O_dataout; wire wire_n0O0ii_dataout; wire wire_n0O0il_dataout; wire wire_n0O0iO_dataout; wire wire_n0O10i_dataout; wire wire_n0O10l_dataout; wire wire_n0O10O_dataout; wire wire_n0O11i_dataout; wire wire_n0O11l_dataout; wire wire_n0O11O_dataout; wire wire_n0O1ii_dataout; wire wire_n0O1il_dataout; wire wire_n0O1iO_dataout; wire wire_n0O1li_dataout; wire wire_n0O1ll_dataout; wire wire_n0O1lO_dataout; wire wire_n0O1Oi_dataout; wire wire_n0O1Ol_dataout; wire wire_n0O1OO_dataout; wire wire_n0Oi_dataout; wire wire_n0Oi0i_dataout; wire wire_n0Oi0l_dataout; wire wire_n0Oi0O_dataout; wire wire_n0Oi1O_dataout; wire wire_n0Oiii_dataout; wire wire_n0OiiO_dataout; wire wire_n0Oili_dataout; wire wire_n0Oill_dataout; wire wire_n0OilO_dataout; wire wire_n0OiOi_dataout; wire wire_n0Ol_dataout; wire wire_n0Olii_dataout; wire wire_n0Olil_dataout; wire wire_n0OliO_dataout; wire wire_n0Olli_dataout; wire wire_n0Olll_dataout; wire wire_n0OO_dataout; wire wire_n0OO0i_dataout; wire wire_n0OO0l_dataout; wire wire_n0OOii_dataout; wire wire_n1011i_dataout; wire wire_n1011l_dataout; wire wire_n1011O_dataout; wire wire_n101iO_dataout; wire wire_n101li_dataout; wire wire_n101ll_dataout; wire wire_n10i_dataout; wire wire_n10l_dataout; wire wire_n10O_dataout; wire wire_n10O0i_dataout; wire wire_n10O0l_dataout; wire wire_n10O0O_dataout; wire wire_n10Oii_dataout; wire wire_n10Oil_dataout; wire wire_n10OiO_dataout; wire wire_n10Oli_dataout; wire wire_n10Oll_dataout; wire wire_n10OlO_dataout; wire wire_n10OOi_dataout; wire wire_n10OOl_dataout; wire wire_n10OOO_dataout; wire wire_n1100i_dataout; wire wire_n1100l_dataout; wire wire_n1100O_dataout; wire wire_n1101i_dataout; wire wire_n110Oi_dataout; wire wire_n110Ol_dataout; wire wire_n1110i_dataout; wire wire_n1110l_dataout; wire wire_n1110O_dataout; wire wire_n1111i_dataout; wire wire_n1111l_dataout; wire wire_n1111O_dataout; wire wire_n111ii_dataout; wire wire_n111il_dataout; wire wire_n111iO_dataout; wire wire_n111li_dataout; wire wire_n111ll_dataout; wire wire_n111lO_dataout; wire wire_n111Oi_dataout; wire wire_n111Ol_dataout; wire wire_n111OO_dataout; wire wire_n11i_dataout; wire wire_n11l_dataout; wire wire_n11l0i_dataout; wire wire_n11l0l_dataout; wire wire_n11l0O_dataout; wire wire_n11l1i_dataout; wire wire_n11l1l_dataout; wire wire_n11l1O_dataout; wire wire_n11lii_dataout; wire wire_n11lil_dataout; wire wire_n11liO_dataout; wire wire_n11lli_dataout; wire wire_n11lll_dataout; wire wire_n11llO_dataout; wire wire_n11lOi_dataout; wire wire_n11lOl_dataout; wire wire_n11lOO_dataout; wire wire_n11O_dataout; wire wire_n11Oii_dataout; wire wire_n11Oil_dataout; wire wire_n11OiO_dataout; wire wire_n11Oli_dataout; wire wire_n11Oll_dataout; wire wire_n11OlO_dataout; wire wire_n11OOi_dataout; wire wire_n11OOl_dataout; wire wire_n11OOO_dataout; wire wire_n1i00i_dataout; wire wire_n1i00l_dataout; wire wire_n1i00O_dataout; wire wire_n1i01i_dataout; wire wire_n1i01l_dataout; wire wire_n1i01O_dataout; wire wire_n1i0ii_dataout; wire wire_n1i0il_dataout; wire wire_n1i0iO_dataout; wire wire_n1i0li_dataout; wire wire_n1i0ll_dataout; wire wire_n1i0lO_dataout; wire wire_n1i0Oi_dataout; wire wire_n1i0Ol_dataout; wire wire_n1i0OO_dataout; wire wire_n1i10i_dataout; wire wire_n1i10l_dataout; wire wire_n1i10O_dataout; wire wire_n1i11i_dataout; wire wire_n1i11l_dataout; wire wire_n1i11O_dataout; wire wire_n1i1ii_dataout; wire wire_n1i1il_dataout; wire wire_n1i1iO_dataout; wire wire_n1i1li_dataout; wire wire_n1i1ll_dataout; wire wire_n1i1lO_dataout; wire wire_n1i1Oi_dataout; wire wire_n1i1Ol_dataout; wire wire_n1i1OO_dataout; wire wire_n1ii_dataout; wire wire_n1ii0i_dataout; wire wire_n1ii0l_dataout; wire wire_n1ii0O_dataout; wire wire_n1ii1i_dataout; wire wire_n1ii1l_dataout; wire wire_n1ii1O_dataout; wire wire_n1iiii_dataout; wire wire_n1iiil_dataout; wire wire_n1iiiO_dataout; wire wire_n1iili_dataout; wire wire_n1iill_dataout; wire wire_n1iilO_dataout; wire wire_n1iiOi_dataout; wire wire_n1iiOl_dataout; wire wire_n1iiOO_dataout; wire wire_n1il_dataout; wire wire_n1il0i_dataout; wire wire_n1il0l_dataout; wire wire_n1il0O_dataout; wire wire_n1il1i_dataout; wire wire_n1il1l_dataout; wire wire_n1il1O_dataout; wire wire_n1ilii_dataout; wire wire_n1ilil_dataout; wire wire_n1iliO_dataout; wire wire_n1illi_dataout; wire wire_n1illl_dataout; wire wire_n1illO_dataout; wire wire_n1ilOi_dataout; wire wire_n1ilOl_dataout; wire wire_n1ilOO_dataout; wire wire_n1iO_dataout; wire wire_n1iO0i_dataout; wire wire_n1iO0l_dataout; wire wire_n1iO0O_dataout; wire wire_n1iO1i_dataout; wire wire_n1iO1l_dataout; wire wire_n1iO1O_dataout; wire wire_n1iOii_dataout; wire wire_n1iOil_dataout; wire wire_n1iOiO_dataout; wire wire_n1iOli_dataout; wire wire_n1iOll_dataout; wire wire_n1iOlO_dataout; wire wire_n1iOOi_dataout; wire wire_n1iOOl_dataout; wire wire_n1iOOO_dataout; wire wire_n1l0ii_dataout; wire wire_n1l0il_dataout; wire wire_n1l0iO_dataout; wire wire_n1l0li_dataout; wire wire_n1l0ll_dataout; wire wire_n1l10i_dataout; wire wire_n1l10l_dataout; wire wire_n1l10O_dataout; wire wire_n1l11i_dataout; wire wire_n1l11l_dataout; wire wire_n1l11O_dataout; wire wire_n1l1ii_dataout; wire wire_n1l1il_dataout; wire wire_n1l1iO_dataout; wire wire_n1l1li_dataout; wire wire_n1l1ll_dataout; wire wire_n1l1lO_dataout; wire wire_n1l1Oi_dataout; wire wire_n1li_dataout; wire wire_n1li0i_dataout; wire wire_n1li1O_dataout; wire wire_n1lill_dataout; wire wire_n1lilO_dataout; wire wire_n1liOi_dataout; wire wire_n1ll_dataout; wire wire_n1lO_dataout; wire wire_n1O0il_dataout; wire wire_n1O0iO_dataout; wire wire_n1O0li_dataout; wire wire_n1O0ll_dataout; wire wire_n1O0lO_dataout; wire wire_n1O0Oi_dataout; wire wire_n1O0Ol_dataout; wire wire_n1O0OO_dataout; wire wire_n1O1ll_dataout; wire wire_n1O1lO_dataout; wire wire_n1Oi_dataout; wire wire_n1Oi1i_dataout; wire wire_n1Oi1l_dataout; wire wire_n1Oi1O_dataout; wire wire_n1Oiil_dataout; wire wire_n1OiOi_dataout; wire wire_n1OiOl_dataout; wire wire_n1OiOO_dataout; wire wire_n1Ol_dataout; wire wire_n1Ol0i_dataout; wire wire_n1Ol0l_dataout; wire wire_n1Ol0O_dataout; wire wire_n1Ol1i_dataout; wire wire_n1Ol1l_dataout; wire wire_n1Ol1O_dataout; wire wire_n1Olii_dataout; wire wire_n1Olli_dataout; wire wire_n1Olll_dataout; wire wire_n1OlOl_dataout; wire wire_n1OlOO_dataout; wire wire_n1OO_dataout; wire wire_n1OO0i_dataout; wire wire_n1OO0l_dataout; wire wire_n1OO0O_dataout; wire wire_n1OO1i_dataout; wire wire_n1OO1l_dataout; wire wire_n1OO1O_dataout; wire wire_n1OOii_dataout; wire wire_n1OOil_dataout; wire wire_ni_dataout; wire wire_ni000O_dataout; wire wire_ni00ii_dataout; wire wire_ni00li_dataout; wire wire_ni00ll_dataout; wire wire_ni00OO_dataout; wire wire_ni010i_dataout; wire wire_ni010l_dataout; wire wire_ni010O_dataout; wire wire_ni011i_dataout; wire wire_ni011l_dataout; wire wire_ni011O_dataout; wire wire_ni0i_dataout; wire wire_ni0iiO_dataout; wire wire_ni0ili_dataout; wire wire_ni0l_dataout; wire wire_ni0O_dataout; wire wire_ni100i_dataout; wire wire_ni100l_dataout; wire wire_ni100O_dataout; wire wire_ni101O_dataout; wire wire_ni10ii_dataout; wire wire_ni10il_dataout; wire wire_ni10iO_dataout; wire wire_ni10lO_dataout; wire wire_ni110O_dataout; wire wire_ni11ii_dataout; wire wire_ni11il_dataout; wire wire_ni11iO_dataout; wire wire_ni11li_dataout; wire wire_ni1i_dataout; wire wire_ni1iii_dataout; wire wire_ni1iil_dataout; wire wire_ni1iiO_dataout; wire wire_ni1ili_dataout; wire wire_ni1ill_dataout; wire wire_ni1ilO_dataout; wire wire_ni1iOi_dataout; wire wire_ni1iOl_dataout; wire wire_ni1iOO_dataout; wire wire_ni1l_dataout; wire wire_ni1l0i_dataout; wire wire_ni1l0l_dataout; wire wire_ni1l0O_dataout; wire wire_ni1l1i_dataout; wire wire_ni1l1l_dataout; wire wire_ni1l1O_dataout; wire wire_ni1lOi_dataout; wire wire_ni1O_dataout; wire wire_ni1Oii_dataout; wire wire_ni1Oil_dataout; wire wire_ni1OiO_dataout; wire wire_ni1Oli_dataout; wire wire_ni1Oll_dataout; wire wire_ni1OlO_dataout; wire wire_ni1OOi_dataout; wire wire_ni1OOl_dataout; wire wire_ni1OOO_dataout; wire wire_niii_dataout; wire wire_niii0i_dataout; wire wire_niii0l_dataout; wire wire_niii0O_dataout; wire wire_niii1l_dataout; wire wire_niii1O_dataout; wire wire_niiiii_dataout; wire wire_niiiil_dataout; wire wire_niiiiO_dataout; wire wire_niiili_dataout; wire wire_niiill_dataout; wire wire_niiilO_dataout; wire wire_niiiOi_dataout; wire wire_niiiOl_dataout; wire wire_niiiOO_dataout; wire wire_niil_dataout; wire wire_niil0i_dataout; wire wire_niil0l_dataout; wire wire_niil0O_dataout; wire wire_niil1i_dataout; wire wire_niil1l_dataout; wire wire_niil1O_dataout; wire wire_niilii_dataout; wire wire_niilil_dataout; wire wire_niiliO_dataout; wire wire_niilli_dataout; wire wire_niilll_dataout; wire wire_niillO_dataout; wire wire_niilOi_dataout; wire wire_niilOl_dataout; wire wire_niilOO_dataout; wire wire_niiO_dataout; wire wire_niiO0i_dataout; wire wire_niiO0l_dataout; wire wire_niiO0O_dataout; wire wire_niiO1i_dataout; wire wire_niiO1l_dataout; wire wire_niiO1O_dataout; wire wire_niiOi_dataout; wire wire_niiOii_dataout; wire wire_niiOil_dataout; wire wire_niiOiO_dataout; wire wire_niiOl_dataout; wire wire_niiOli_dataout; wire wire_niiOll_dataout; wire wire_niiOO_dataout; wire wire_nil00i_dataout; wire wire_nil00l_dataout; wire wire_nil00O_dataout; wire wire_nil01i_dataout; wire wire_nil01l_dataout; wire wire_nil01O_dataout; wire wire_nil0i_dataout; wire wire_nil0ii_dataout; wire wire_nil0il_dataout; wire wire_nil0iO_dataout; wire wire_nil0l_dataout; wire wire_nil0li_dataout; wire wire_nil0ll_dataout; wire wire_nil0lO_dataout; wire wire_nil0O_dataout; wire wire_nil0Oi_dataout; wire wire_nil0Ol_dataout; wire wire_nil0OO_dataout; wire wire_nil10i_dataout; wire wire_nil10l_dataout; wire wire_nil10O_dataout; wire wire_nil11i_dataout; wire wire_nil11l_dataout; wire wire_nil11O_dataout; wire wire_nil1i_dataout; wire wire_nil1ii_dataout; wire wire_nil1il_dataout; wire wire_nil1iO_dataout; wire wire_nil1l_dataout; wire wire_nil1li_dataout; wire wire_nil1ll_dataout; wire wire_nil1lO_dataout; wire wire_nil1O_dataout; wire wire_nil1Oi_dataout; wire wire_nil1Ol_dataout; wire wire_nil1OO_dataout; wire wire_nili_dataout; wire wire_nili0i_dataout; wire wire_nili0l_dataout; wire wire_nili0O_dataout; wire wire_nili1i_dataout; wire wire_nili1l_dataout; wire wire_nili1O_dataout; wire wire_nilii_dataout; wire wire_niliii_dataout; wire wire_niliil_dataout; wire wire_niliiO_dataout; wire wire_nilil_dataout; wire wire_nilili_dataout; wire wire_nilill_dataout; wire wire_nililO_dataout; wire wire_niliO_dataout; wire wire_niliOi_dataout; wire wire_niliOl_dataout; wire wire_niliOO_dataout; wire wire_nill_dataout; wire wire_nill0i_dataout; wire wire_nill0l_dataout; wire wire_nill0O_dataout; wire wire_nill1i_dataout; wire wire_nill1l_dataout; wire wire_nill1O_dataout; wire wire_nilli_dataout; wire wire_nillii_dataout; wire wire_nillil_dataout; wire wire_nilliO_dataout; wire wire_nilll_dataout; wire wire_nillli_dataout; wire wire_nillll_dataout; wire wire_nilllO_dataout; wire wire_nillO_dataout; wire wire_nillOi_dataout; wire wire_nillOl_dataout; wire wire_nillOO_dataout; wire wire_nilO_dataout; wire wire_nilO0i_dataout; wire wire_nilO0l_dataout; wire wire_nilO0O_dataout; wire wire_nilO1i_dataout; wire wire_nilO1l_dataout; wire wire_nilO1O_dataout; wire wire_nilOi_dataout; wire wire_nilOii_dataout; wire wire_nilOil_dataout; wire wire_nilOiO_dataout; wire wire_nilOl_dataout; wire wire_nilOli_dataout; wire wire_nilOll_dataout; wire wire_nilOlO_dataout; wire wire_nilOO_dataout; wire wire_nilOOi_dataout; wire wire_nilOOl_dataout; wire wire_nilOOO_dataout; wire wire_niO_dataout; wire wire_niO00i_dataout; wire wire_niO00l_dataout; wire wire_niO00O_dataout; wire wire_niO01i_dataout; wire wire_niO01l_dataout; wire wire_niO01O_dataout; wire wire_niO0i_dataout; wire wire_niO0ii_dataout; wire wire_niO0il_dataout; wire wire_niO0iO_dataout; wire wire_niO0l_dataout; wire wire_niO0li_dataout; wire wire_niO0ll_dataout; wire wire_niO0lO_dataout; wire wire_niO0O_dataout; wire wire_niO0Oi_dataout; wire wire_niO0Ol_dataout; wire wire_niO0OO_dataout; wire wire_niO10i_dataout; wire wire_niO10l_dataout; wire wire_niO10O_dataout; wire wire_niO11i_dataout; wire wire_niO11l_dataout; wire wire_niO11O_dataout; wire wire_niO1i_dataout; wire wire_niO1ii_dataout; wire wire_niO1il_dataout; wire wire_niO1iO_dataout; wire wire_niO1l_dataout; wire wire_niO1li_dataout; wire wire_niO1ll_dataout; wire wire_niO1lO_dataout; wire wire_niO1O_dataout; wire wire_niO1Oi_dataout; wire wire_niO1Ol_dataout; wire wire_niO1OO_dataout; wire wire_niOi_dataout; wire wire_niOi0i_dataout; wire wire_niOi0l_dataout; wire wire_niOi0O_dataout; wire wire_niOi1i_dataout; wire wire_niOi1l_dataout; wire wire_niOi1O_dataout; wire wire_niOii_dataout; wire wire_niOiii_dataout; wire wire_niOiil_dataout; wire wire_niOiiO_dataout; wire wire_niOil_dataout; wire wire_niOili_dataout; wire wire_niOill_dataout; wire wire_niOilO_dataout; wire wire_niOiO_dataout; wire wire_niOiOi_dataout; wire wire_niOiOl_dataout; wire wire_niOiOO_dataout; wire wire_niOl_dataout; wire wire_niOl0i_dataout; wire wire_niOl0l_dataout; wire wire_niOl0O_dataout; wire wire_niOl1i_dataout; wire wire_niOl1l_dataout; wire wire_niOl1O_dataout; wire wire_niOli_dataout; wire wire_niOlii_dataout; wire wire_niOlil_dataout; wire wire_niOll_dataout; wire wire_niOllO_dataout; wire wire_niOlO_dataout; wire wire_niOlOi_dataout; wire wire_niOO_dataout; wire wire_niOOi_dataout; wire wire_niOOl_dataout; wire wire_niOOO_dataout; wire wire_nl000i_dataout; wire wire_nl000l_dataout; wire wire_nl000O_dataout; wire wire_nl001i_dataout; wire wire_nl001l_dataout; wire wire_nl001O_dataout; wire wire_nl00i_dataout; wire wire_nl00ii_dataout; wire wire_nl00il_dataout; wire wire_nl00iO_dataout; wire wire_nl00l_dataout; wire wire_nl00li_dataout; wire wire_nl00ll_dataout; wire wire_nl00lO_dataout; wire wire_nl00O_dataout; wire wire_nl00Oi_dataout; wire wire_nl00Ol_dataout; wire wire_nl00OO_dataout; wire wire_nl010i_dataout; wire wire_nl010l_dataout; wire wire_nl010O_dataout; wire wire_nl011i_dataout; wire wire_nl011l_dataout; wire wire_nl011O_dataout; wire wire_nl01i_dataout; wire wire_nl01ii_dataout; wire wire_nl01il_dataout; wire wire_nl01iO_dataout; wire wire_nl01l_dataout; wire wire_nl01li_dataout; wire wire_nl01ll_dataout; wire wire_nl01lO_dataout; wire wire_nl01O_dataout; wire wire_nl01Oi_dataout; wire wire_nl01Ol_dataout; wire wire_nl01OO_dataout; wire wire_nl0i_dataout; wire wire_nl0i0i_dataout; wire wire_nl0i0l_dataout; wire wire_nl0i0O_dataout; wire wire_nl0i1i_dataout; wire wire_nl0i1l_dataout; wire wire_nl0i1O_dataout; wire wire_nl0ii_dataout; wire wire_nl0iii_dataout; wire wire_nl0iil_dataout; wire wire_nl0iiO_dataout; wire wire_nl0il_dataout; wire wire_nl0ili_dataout; wire wire_nl0ill_dataout; wire wire_nl0ilO_dataout; wire wire_nl0iO_dataout; wire wire_nl0iOi_dataout; wire wire_nl0iOl_dataout; wire wire_nl0iOO_dataout; wire wire_nl0l0i_dataout; wire wire_nl0l0l_dataout; wire wire_nl0l0O_dataout; wire wire_nl0l1i_dataout; wire wire_nl0l1l_dataout; wire wire_nl0l1O_dataout; wire wire_nl0li_dataout; wire wire_nl0lii_dataout; wire wire_nl0lil_dataout; wire wire_nl0liO_dataout; wire wire_nl0ll_dataout; wire wire_nl0lli_dataout; wire wire_nl0lll_dataout; wire wire_nl0llO_dataout; wire wire_nl0lO_dataout; wire wire_nl0lOi_dataout; wire wire_nl0lOl_dataout; wire wire_nl0Oi_dataout; wire wire_nl0Oil_dataout; wire wire_nl0OiO_dataout; wire wire_nl0Ol_dataout; wire wire_nl0Oli_dataout; wire wire_nl0Oll_dataout; wire wire_nl0OlO_dataout; wire wire_nl0OO_dataout; wire wire_nl10i_dataout; wire wire_nl10l_dataout; wire wire_nl10O_dataout; wire wire_nl11i_dataout; wire wire_nl11l_dataout; wire wire_nl11O_dataout; wire wire_nl1i_dataout; wire wire_nl1i0l_dataout; wire wire_nl1i0O_dataout; wire wire_nl1ii_dataout; wire wire_nl1iii_dataout; wire wire_nl1iil_dataout; wire wire_nl1iiO_dataout; wire wire_nl1il_dataout; wire wire_nl1ili_dataout; wire wire_nl1ill_dataout; wire wire_nl1ilO_dataout; wire wire_nl1iO_dataout; wire wire_nl1iOi_dataout; wire wire_nl1iOl_dataout; wire wire_nl1iOO_dataout; wire wire_nl1l_dataout; wire wire_nl1l0i_dataout; wire wire_nl1l0l_dataout; wire wire_nl1l0O_dataout; wire wire_nl1l1i_dataout; wire wire_nl1l1l_dataout; wire wire_nl1l1O_dataout; wire wire_nl1li_dataout; wire wire_nl1lii_dataout; wire wire_nl1lil_dataout; wire wire_nl1liO_dataout; wire wire_nl1ll_dataout; wire wire_nl1lli_dataout; wire wire_nl1lll_dataout; wire wire_nl1llO_dataout; wire wire_nl1lO_dataout; wire wire_nl1lOi_dataout; wire wire_nl1lOl_dataout; wire wire_nl1lOO_dataout; wire wire_nl1O_dataout; wire wire_nl1O0i_dataout; wire wire_nl1O0l_dataout; wire wire_nl1O0O_dataout; wire wire_nl1O1i_dataout; wire wire_nl1O1l_dataout; wire wire_nl1O1O_dataout; wire wire_nl1Oi_dataout; wire wire_nl1Oii_dataout; wire wire_nl1Oil_dataout; wire wire_nl1OiO_dataout; wire wire_nl1Ol_dataout; wire wire_nl1Oli_dataout; wire wire_nl1Oll_dataout; wire wire_nl1OlO_dataout; wire wire_nl1OO_dataout; wire wire_nl1OOi_dataout; wire wire_nl1OOl_dataout; wire wire_nl1OOO_dataout; wire wire_nli_dataout; wire wire_nli00i_dataout; wire wire_nli00l_dataout; wire wire_nli00O_dataout; wire wire_nli01O_dataout; wire wire_nli0i_dataout; wire wire_nli0ii_dataout; wire wire_nli0iO_dataout; wire wire_nli0l_dataout; wire wire_nli0li_dataout; wire wire_nli0ll_dataout; wire wire_nli0lO_dataout; wire wire_nli0O_dataout; wire wire_nli0Oi_dataout; wire wire_nli1i_dataout; wire wire_nli1l_dataout; wire wire_nli1O_dataout; wire wire_nliii_dataout; wire wire_nliiii_dataout; wire wire_nliiil_dataout; wire wire_nliiiO_dataout; wire wire_nliil_dataout; wire wire_nliiO_dataout; wire wire_nliiOO_dataout; wire wire_nlil_dataout; wire wire_nlili_dataout; wire wire_nlilii_dataout; wire wire_nlilil_dataout; wire wire_nlill_dataout; wire wire_nlilO_dataout; wire wire_nlilOO_dataout; wire wire_nliO00l_dataout; wire wire_nliO00O_dataout; wire wire_nliO0i_dataout; wire wire_nliO0ii_dataout; wire wire_nliO0l_dataout; wire wire_nliO0O_dataout; wire wire_nliO1O_dataout; wire wire_nliOi_dataout; wire wire_nliOl_dataout; wire wire_nliOlO_dataout; wire wire_nliOO_dataout; wire wire_nliOOi_dataout; wire wire_nliOOO_dataout; wire wire_nll_dataout; wire wire_nll00i_dataout; wire wire_nll00l_dataout; wire wire_nll00O_dataout; wire wire_nll01i_dataout; wire wire_nll01l_dataout; wire wire_nll01O_dataout; wire wire_nll0i_dataout; wire wire_nll0ii_dataout; wire wire_nll0il_dataout; wire wire_nll0iO_dataout; wire wire_nll0l_dataout; wire wire_nll0li_dataout; wire wire_nll0ll_dataout; wire wire_nll0lO_dataout; wire wire_nll0O_dataout; wire wire_nll0Oi_dataout; wire wire_nll0Ol_dataout; wire wire_nll0OO_dataout; wire wire_nll10i_dataout; wire wire_nll10l_dataout; wire wire_nll10O_dataout; wire wire_nll11i_dataout; wire wire_nll11l_dataout; wire wire_nll11O_dataout; wire wire_nll1i_dataout; wire wire_nll1ii_dataout; wire wire_nll1il_dataout; wire wire_nll1iO_dataout; wire wire_nll1l_dataout; wire wire_nll1li_dataout; wire wire_nll1ll_dataout; wire wire_nll1lO_dataout; wire wire_nll1O_dataout; wire wire_nll1Oi_dataout; wire wire_nll1Ol_dataout; wire wire_nll1OO_dataout; wire wire_nlli01i_dataout; wire wire_nlli0li_dataout; wire wire_nlli1i_dataout; wire wire_nlli1l_dataout; wire wire_nlli1lO_dataout; wire wire_nlli1Oi_dataout; wire wire_nlli1Ol_dataout; wire wire_nlli1OO_dataout; wire wire_nllii_dataout; wire wire_nllii0i_dataout; wire wire_nlliili_dataout; wire wire_nlliill_dataout; wire wire_nlliilO_dataout; wire wire_nlliiOi_dataout; wire wire_nlliiOl_dataout; wire wire_nllil_dataout; wire wire_nllil0O_dataout; wire wire_nllilii_dataout; wire wire_nllilil_dataout; wire wire_nlliliO_dataout; wire wire_nllilli_dataout; wire wire_nllilll_dataout; wire wire_nllillO_dataout; wire wire_nllilOO_dataout; wire wire_nlliO_dataout; wire wire_nlll00i_dataout; wire wire_nlll00l_dataout; wire wire_nlll00O_dataout; wire wire_nlll01i_dataout; wire wire_nlll01l_dataout; wire wire_nlll01O_dataout; wire wire_nlll0ii_dataout; wire wire_nlll0il_dataout; wire wire_nlll0iO_dataout; wire wire_nlll0li_dataout; wire wire_nlll0ll_dataout; wire wire_nlll0lO_dataout; wire wire_nlll0Oi_dataout; wire wire_nlll0Ol_dataout; wire wire_nlll0OO_dataout; wire wire_nlll1ll_dataout; wire wire_nlll1lO_dataout; wire wire_nlll1Oi_dataout; wire wire_nlll1Ol_dataout; wire wire_nlll1OO_dataout; wire wire_nllli_dataout; wire wire_nllli0i_dataout; wire wire_nllli0l_dataout; wire wire_nllli0O_dataout; wire wire_nllli1i_dataout; wire wire_nllli1l_dataout; wire wire_nllli1O_dataout; wire wire_nllll_dataout; wire wire_nllllll_dataout; wire wire_nlllllO_dataout; wire wire_nlllO_dataout; wire wire_nllO_dataout; wire wire_nllO00i_dataout; wire wire_nllO00l_dataout; wire wire_nllO00O_dataout; wire wire_nllO01i_dataout; wire wire_nllO01l_dataout; wire wire_nllO01O_dataout; wire wire_nllO0ii_dataout; wire wire_nllO0il_dataout; wire wire_nllO0iO_dataout; wire wire_nllO0li_dataout; wire wire_nllO0ll_dataout; wire wire_nllO0lO_dataout; wire wire_nllO0Oi_dataout; wire wire_nllO0Ol_dataout; wire wire_nllO0OO_dataout; wire wire_nllO1ll_dataout; wire wire_nllO1lO_dataout; wire wire_nllO1Oi_dataout; wire wire_nllO1Ol_dataout; wire wire_nllO1OO_dataout; wire wire_nllOi_dataout; wire wire_nllOi0i_dataout; wire wire_nllOi0l_dataout; wire wire_nllOi0O_dataout; wire wire_nllOi1i_dataout; wire wire_nllOi1l_dataout; wire wire_nllOi1O_dataout; wire wire_nllOiii_dataout; wire wire_nllOiil_dataout; wire wire_nllOiiO_dataout; wire wire_nllOili_dataout; wire wire_nllOill_dataout; wire wire_nllOilO_dataout; wire wire_nllOiOi_dataout; wire wire_nllOiOl_dataout; wire wire_nllOiOO_dataout; wire wire_nllOl_dataout; wire wire_nllOl0i_dataout; wire wire_nllOl0l_dataout; wire wire_nllOl0O_dataout; wire wire_nllOl1i_dataout; wire wire_nllOl1l_dataout; wire wire_nllOl1O_dataout; wire wire_nllOlii_dataout; wire wire_nllOlil_dataout; wire wire_nllOliO_dataout; wire wire_nllOlli_dataout; wire wire_nllOlll_dataout; wire wire_nllOllO_dataout; wire wire_nllOlOi_dataout; wire wire_nllOlOl_dataout; wire wire_nllOlOO_dataout; wire wire_nllOO_dataout; wire wire_nllOO0i_dataout; wire wire_nllOO0l_dataout; wire wire_nllOO0O_dataout; wire wire_nllOO1i_dataout; wire wire_nllOO1l_dataout; wire wire_nllOO1O_dataout; wire wire_nllOOii_dataout; wire wire_nllOOil_dataout; wire wire_nllOOiO_dataout; wire wire_nllOOli_dataout; wire wire_nllOOll_dataout; wire wire_nllOOlO_dataout; wire wire_nllOOOi_dataout; wire wire_nllOOOl_dataout; wire wire_nllOOOO_dataout; wire wire_nlO_dataout; wire wire_nlO001i_dataout; wire wire_nlO001l_dataout; wire wire_nlO00il_dataout; wire wire_nlO010i_dataout; wire wire_nlO010l_dataout; wire wire_nlO010O_dataout; wire wire_nlO011O_dataout; wire wire_nlO01ii_dataout; wire wire_nlO01il_dataout; wire wire_nlO01iO_dataout; wire wire_nlO01li_dataout; wire wire_nlO01ll_dataout; wire wire_nlO01lO_dataout; wire wire_nlO01Oi_dataout; wire wire_nlO01Ol_dataout; wire wire_nlO01OO_dataout; wire wire_nlO0i_dataout; wire wire_nlO0i0l_dataout; wire wire_nlO0i1i_dataout; wire wire_nlO0i1O_dataout; wire wire_nlO0iiO_dataout; wire wire_nlO0l_dataout; wire wire_nlO0l1O_dataout; wire wire_nlO0lOi_dataout; wire wire_nlO0lOl_dataout; wire wire_nlO0lOO_dataout; wire wire_nlO0O_dataout; wire wire_nlO0O0i_dataout; wire wire_nlO0O0l_dataout; wire wire_nlO0O0O_dataout; wire wire_nlO0O1i_dataout; wire wire_nlO0O1l_dataout; wire wire_nlO0O1O_dataout; wire wire_nlO0Oii_dataout; wire wire_nlO0Oil_dataout; wire wire_nlO0OiO_dataout; wire wire_nlO0Oli_dataout; wire wire_nlO0Oll_dataout; wire wire_nlO0OlO_dataout; wire wire_nlO100i_dataout; wire wire_nlO100l_dataout; wire wire_nlO100O_dataout; wire wire_nlO10i_dataout; wire wire_nlO10ii_dataout; wire wire_nlO10il_dataout; wire wire_nlO10l_dataout; wire wire_nlO10O_dataout; wire wire_nlO110i_dataout; wire wire_nlO110l_dataout; wire wire_nlO110O_dataout; wire wire_nlO111i_dataout; wire wire_nlO111l_dataout; wire wire_nlO111O_dataout; wire wire_nlO11ii_dataout; wire wire_nlO11il_dataout; wire wire_nlO11iO_dataout; wire wire_nlO11li_dataout; wire wire_nlO11ll_dataout; wire wire_nlO11lO_dataout; wire wire_nlO11Oi_dataout; wire wire_nlO11Ol_dataout; wire wire_nlO11OO_dataout; wire wire_nlO1i_dataout; wire wire_nlO1i0i_dataout; wire wire_nlO1i0l_dataout; wire wire_nlO1i1i_dataout; wire wire_nlO1i1l_dataout; wire wire_nlO1i1O_dataout; wire wire_nlO1ii_dataout; wire wire_nlO1iii_dataout; wire wire_nlO1iil_dataout; wire wire_nlO1iiO_dataout; wire wire_nlO1il_dataout; wire wire_nlO1ili_dataout; wire wire_nlO1ill_dataout; wire wire_nlO1iO_dataout; wire wire_nlO1l_dataout; wire wire_nlO1li_dataout; wire wire_nlO1ll_dataout; wire wire_nlO1lO_dataout; wire wire_nlO1O_dataout; wire wire_nlO1Oi_dataout; wire wire_nlO1Oil_dataout; wire wire_nlO1Oli_dataout; wire wire_nlO1Oll_dataout; wire wire_nlO1OO_dataout; wire wire_nlOi00i_dataout; wire wire_nlOi00l_dataout; wire wire_nlOi00O_dataout; wire wire_nlOi01i_dataout; wire wire_nlOi01l_dataout; wire wire_nlOi01O_dataout; wire wire_nlOi0ii_dataout; wire wire_nlOi0il_dataout; wire wire_nlOi0iO_dataout; wire wire_nlOi0li_dataout; wire wire_nlOi0ll_dataout; wire wire_nlOi0lO_dataout; wire wire_nlOi0Oi_dataout; wire wire_nlOi0Ol_dataout; wire wire_nlOi0OO_dataout; wire wire_nlOi10i_dataout; wire wire_nlOi10l_dataout; wire wire_nlOi10O_dataout; wire wire_nlOi11i_dataout; wire wire_nlOi11l_dataout; wire wire_nlOi11O_dataout; wire wire_nlOi1il_dataout; wire wire_nlOi1li_dataout; wire wire_nlOi1ll_dataout; wire wire_nlOi1lO_dataout; wire wire_nlOi1Oi_dataout; wire wire_nlOi1Ol_dataout; wire wire_nlOi1OO_dataout; wire wire_nlOii_dataout; wire wire_nlOii0i_dataout; wire wire_nlOii0l_dataout; wire wire_nlOii0O_dataout; wire wire_nlOii1i_dataout; wire wire_nlOii1l_dataout; wire wire_nlOii1O_dataout; wire wire_nlOiiii_dataout; wire wire_nlOiiil_dataout; wire wire_nlOiiiO_dataout; wire wire_nlOiili_dataout; wire wire_nlOiill_dataout; wire wire_nlOiilO_dataout; wire wire_nlOiiOi_dataout; wire wire_nlOiiOl_dataout; wire wire_nlOiiOO_dataout; wire wire_nlOil_dataout; wire wire_nlOil0i_dataout; wire wire_nlOil0l_dataout; wire wire_nlOil0O_dataout; wire wire_nlOil1i_dataout; wire wire_nlOil1l_dataout; wire wire_nlOil1O_dataout; wire wire_nlOilii_dataout; wire wire_nlOilil_dataout; wire wire_nlOiliO_dataout; wire wire_nlOiO_dataout; wire wire_nlOli_dataout; wire wire_nlOll_dataout; wire wire_nlOll0i_dataout; wire wire_nlOll0l_dataout; wire wire_nlOll0O_dataout; wire wire_nlOll1O_dataout; wire wire_nlOllii_dataout; wire wire_nlOllil_dataout; wire wire_nlOlliO_dataout; wire wire_nlOllli_dataout; wire wire_nlOllll_dataout; wire wire_nlOlllO_dataout; wire wire_nlOllOi_dataout; wire wire_nlOllOl_dataout; wire wire_nlOllOO_dataout; wire wire_nlOlO_dataout; wire wire_nlOlO0i_dataout; wire wire_nlOlO0l_dataout; wire wire_nlOlO0O_dataout; wire wire_nlOlO1i_dataout; wire wire_nlOlO1l_dataout; wire wire_nlOlO1O_dataout; wire wire_nlOlOii_dataout; wire wire_nlOlOil_dataout; wire wire_nlOlOiO_dataout; wire wire_nlOlOli_dataout; wire wire_nlOlOll_dataout; wire wire_nlOlOlO_dataout; wire wire_nlOlOOi_dataout; wire wire_nlOlOOl_dataout; wire wire_nlOlOOO_dataout; wire wire_nlOO00i_dataout; wire wire_nlOO00l_dataout; wire wire_nlOO00O_dataout; wire wire_nlOO01i_dataout; wire wire_nlOO01l_dataout; wire wire_nlOO01O_dataout; wire wire_nlOO0ii_dataout; wire wire_nlOO0il_dataout; wire wire_nlOO0iO_dataout; wire wire_nlOO0li_dataout; wire wire_nlOO0ll_dataout; wire wire_nlOO0lO_dataout; wire wire_nlOO0Oi_dataout; wire wire_nlOO0Ol_dataout; wire wire_nlOO0OO_dataout; wire wire_nlOO10i_dataout; wire wire_nlOO10l_dataout; wire wire_nlOO10O_dataout; wire wire_nlOO11i_dataout; wire wire_nlOO11l_dataout; wire wire_nlOO11O_dataout; wire wire_nlOO1ii_dataout; wire wire_nlOO1il_dataout; wire wire_nlOO1iO_dataout; wire wire_nlOO1li_dataout; wire wire_nlOO1ll_dataout; wire wire_nlOO1lO_dataout; wire wire_nlOO1Oi_dataout; wire wire_nlOO1Ol_dataout; wire wire_nlOO1OO_dataout; wire wire_nlOOi_dataout; wire wire_nlOOi0i_dataout; wire wire_nlOOi0l_dataout; wire wire_nlOOi0O_dataout; wire wire_nlOOi1i_dataout; wire wire_nlOOi1l_dataout; wire wire_nlOOi1O_dataout; wire wire_nlOOiii_dataout; wire wire_nlOOiil_dataout; wire wire_nlOOiiO_dataout; wire wire_nlOOili_dataout; wire wire_nlOOill_dataout; wire wire_nlOOilO_dataout; wire wire_nlOOiOi_dataout; wire wire_nlOOiOl_dataout; wire wire_nlOOiOO_dataout; wire wire_nlOOl_dataout; wire wire_nlOOl0i_dataout; wire wire_nlOOl0l_dataout; wire wire_nlOOl0O_dataout; wire wire_nlOOl1i_dataout; wire wire_nlOOl1l_dataout; wire wire_nlOOl1O_dataout; wire wire_nlOOlii_dataout; wire wire_nlOOlil_dataout; wire wire_nlOOliO_dataout; wire wire_nlOOlli_dataout; wire wire_nlOOlll_dataout; wire wire_nlOOllO_dataout; wire wire_nlOOlOi_dataout; wire wire_nlOOlOO_dataout; wire wire_nlOOO_dataout; wire wire_nlOOO0i_dataout; wire wire_nlOOO0l_dataout; wire wire_nlOOO0O_dataout; wire wire_nlOOO1i_dataout; wire wire_nlOOO1l_dataout; wire wire_nlOOO1O_dataout; wire wire_nlOOOii_dataout; wire wire_nlOOOil_dataout; wire wire_nlOOOiO_dataout; wire wire_nlOOOli_dataout; wire wire_nlOOOll_dataout; wire wire_nlOOOlO_dataout; wire wire_nlOOOOi_dataout; wire wire_nlOOOOl_dataout; wire wire_nlOOOOO_dataout; wire [4:0] wire_n0O0li_o; wire [6:0] wire_n0OOOO_o; wire [2:0] wire_n1010i_o; wire [4:0] wire_n1l0lO_o; wire [6:0] wire_n1O1OO_o; wire [5:0] wire_ni01ii_o; wire [4:0] wire_ni01il_o; wire [5:0] wire_ni1lii_o; wire [5:0] wire_ni1lil_o; wire [5:0] wire_ni1liO_o; wire [4:0] wire_nl0OOi_o; wire [6:0] wire_nli1iO_o; wire [5:0] wire_nllliii_o; wire [4:0] wire_nllliil_o; wire [3:0] wire_nllliOl_o; wire [4:0] wire_nllll1i_o; wire [5:0] wire_nlO000i_o; wire [5:0] wire_nlO000l_o; wire [5:0] wire_nlO001O_o; wire [6:0] wire_nlO0lli_o; wire [5:0] wire_nlO101i_o; wire [4:0] wire_nlO10iO_o; wire [15:0] wire_n011iO_o; wire [3:0] wire_n011ll_o; wire [31:0] wire_n011Oi_o; wire [31:0] wire_n0OO1l_o; wire [31:0] wire_n1l00O_o; wire [15:0] wire_n1l01l_o; wire [15:0] wire_n1l1OO_o; wire [3:0] wire_n1OliO_o; wire [15:0] wire_nl0O1i_o; wire [15:0] wire_nl0O1O_o; wire [31:0] wire_nl0Oii_o; wire [31:0] wire_nliO01i_o; wire [15:0] wire_nliO1lO_o; wire [3:0] wire_nliO1Ol_o; wire [31:0] wire_nlli01O_o; wire wire_n11iii_o; wire wire_n1O01i_o; wire wire_n1O10l_o; wire wire_n1O11l_o; wire wire_n1OllO_o; wire wire_n1OlOi_o; wire wire_n1OOlO_o; wire wire_n1OOOi_o; wire wire_ni1i1i_o; wire wire_ni1lli_o; wire wire_nli1li_o; wire wire_nlilOi_o; wire wire_nlli0iO_o; wire wire_nllOii_o; wire wire_nllOil_o; wire wire_nllOiO_o; wire wire_nllOli_o; wire wire_nlO000O_o; wire wire_nllOOO_o; wire wire_nlO11i_o; wire wire_nlO11l_o; wire wire_nlO11O_o; wire [15:0] wire_nllOll_data_out1; wire [15:0] wire_nllOll_data_out2; wire [15:0] wire_nllOlO_data_out1; wire [15:0] wire_nllOlO_data_out2; wire nli00ll; wire nli00lO; wire nli00Oi; wire nli00Ol; wire nli00OO; wire nli0i0i; wire nli0i0l; wire nli0i0O; wire nli0i1i; wire nli0i1l; wire nli0i1O; wire nli0iii; wire nli0iil; wire nli0iiO; wire nli0ili; wire nli0ill; wire nli0ilO; wire nli0iOi; wire nli0iOl; wire nli0iOO; wire nli0l0i; wire nli0l0l; wire nli0l0O; wire nli0l1i; wire nli0l1l; wire nli0l1O; wire nli0lii; wire nli0lil; wire nli0liO; wire nli0lli; wire nli0lll; wire nli0llO; wire nli0lOi; wire nli0lOl; wire nli0lOO; wire nli0O0i; wire nli0O0l; wire nli0O1i; wire nli0O1l; wire nli0O1O; wire nli0Oii; wire nli0Oil; wire nli0OiO; wire nli0Oli; wire nli0Oll; wire nli0OlO; wire nli0OOi; wire nli0OOl; wire nli0OOO; wire nlii00i; wire nlii00l; wire nlii00O; wire nlii01i; wire nlii01l; wire nlii01O; wire nlii0ii; wire nlii0il; wire nlii0iO; wire nlii0li; wire nlii0ll; wire nlii0lO; wire nlii0Oi; wire nlii0Ol; wire nlii0OO; wire nlii10i; wire nlii10l; wire nlii10O; wire nlii11i; wire nlii11l; wire nlii11O; wire nlii1ii; wire nlii1il; wire nlii1iO; wire nlii1li; wire nlii1ll; wire nlii1lO; wire nlii1Oi; wire nlii1Ol; wire nlii1OO; wire nliii0i; wire nliii0l; wire nliii0O; wire nliii1i; wire nliii1l; wire nliii1O; wire nliiiii; wire nliiiil; wire nliiiiO; wire nliiili; wire nliiill; wire nliiilO; wire nliiiOi; wire nliiiOl; wire nliiiOO; wire nliil0i; wire nliil0l; wire nliil0O; wire nliil1O; wire nliilii; wire nliilil; wire nliiliO; wire nliilli; wire nliilll; wire nliillO; wire nliilOi; wire nliilOl; wire nliilOO; wire nliiO0i; wire nliiO0l; wire nliiO0O; wire nliiO1i; wire nliiO1l; wire nliiO1O; wire nliiOii; wire nliiOil; wire nliiOiO; wire nliiOli; wire nliiOll; wire nliiOlO; wire nlil00i; wire nlil00l; wire nlil00O; wire nlil01i; wire nlil01O; wire nlil0ii; wire nlil0il; wire nlil0iO; wire nlil0lO; wire nlil0Oi; wire nlil10i; wire nlil10l; wire nlil10O; wire nlil11i; wire nlil11l; wire nlil11O; wire nlil1ii; wire nlil1il; wire nlil1iO; wire nlil1li; wire nlil1ll; wire nlil1lO; wire nlil1Oi; wire nlil1Ol; wire nlil1OO; wire nlili0i; wire nlili1i; wire nlili1l; wire nlili1O; wire nliliii; wire nliliil; wire nliliiO; wire nlilili; wire nlill0O; wire nlillii; wire nlillil; wire nlillOi; wire nlillOl; wire nlillOO; wire nlilO0l; wire nlilOil; wire nlilOiO; wire nliO10l; wire nliO11i; wire nliO1il; initial nli0O0O61 = 0; always @ ( posedge clk_2) nli0O0O61 <= nli0O0O62; event nli0O0O61_event; initial #1 ->nli0O0O61_event; always @(nli0O0O61_event) nli0O0O61 <= {1{1'b1}}; initial nli0O0O62 = 0; always @ ( posedge clk_2) nli0O0O62 <= nli0O0O61; initial nliil1i59 = 0; always @ ( posedge clk_2) nliil1i59 <= nliil1i60; event nliil1i59_event; initial #1 ->nliil1i59_event; always @(nliil1i59_event) nliil1i59 <= {1{1'b1}}; initial nliil1i60 = 0; always @ ( posedge clk_2) nliil1i60 <= nliil1i59; initial nliil1l57 = 0; always @ ( posedge clk_2) nliil1l57 <= nliil1l58; event nliil1l57_event; initial #1 ->nliil1l57_event; always @(nliil1l57_event) nliil1l57 <= {1{1'b1}}; initial nliil1l58 = 0; always @ ( posedge clk_2) nliil1l58 <= nliil1l57; initial nliiOOi55 = 0; always @ ( posedge clk_2) nliiOOi55 <= nliiOOi56; event nliiOOi55_event; initial #1 ->nliiOOi55_event; always @(nliiOOi55_event) nliiOOi55 <= {1{1'b1}}; initial nliiOOi56 = 0; always @ ( posedge clk_2) nliiOOi56 <= nliiOOi55; initial nliiOOl53 = 0; always @ ( posedge clk_2) nliiOOl53 <= nliiOOl54; event nliiOOl53_event; initial #1 ->nliiOOl53_event; always @(nliiOOl53_event) nliiOOl53 <= {1{1'b1}}; initial nliiOOl54 = 0; always @ ( posedge clk_2) nliiOOl54 <= nliiOOl53; initial nliiOOO51 = 0; always @ ( posedge clk_2) nliiOOO51 <= nliiOOO52; event nliiOOO51_event; initial #1 ->nliiOOO51_event; always @(nliiOOO51_event) nliiOOO51 <= {1{1'b1}}; initial nliiOOO52 = 0; always @ ( posedge clk_2) nliiOOO52 <= nliiOOO51; initial nlil01l49 = 0; always @ ( posedge clk_2) nlil01l49 <= nlil01l50; event nlil01l49_event; initial #1 ->nlil01l49_event; always @(nlil01l49_event) nlil01l49 <= {1{1'b1}}; initial nlil01l50 = 0; always @ ( posedge clk_2) nlil01l50 <= nlil01l49; initial nlil0li47 = 0; always @ ( posedge clk_2) nlil0li47 <= nlil0li48; event nlil0li47_event; initial #1 ->nlil0li47_event; always @(nlil0li47_event) nlil0li47 <= {1{1'b1}}; initial nlil0li48 = 0; always @ ( posedge clk_2) nlil0li48 <= nlil0li47; initial nlil0Ol45 = 0; always @ ( posedge clk_2) nlil0Ol45 <= nlil0Ol46; event nlil0Ol45_event; initial #1 ->nlil0Ol45_event; always @(nlil0Ol45_event) nlil0Ol45 <= {1{1'b1}}; initial nlil0Ol46 = 0; always @ ( posedge clk_2) nlil0Ol46 <= nlil0Ol45; initial nlili0l43 = 0; always @ ( posedge clk_2) nlili0l43 <= nlili0l44; event nlili0l43_event; initial #1 ->nlili0l43_event; always @(nlili0l43_event) nlili0l43 <= {1{1'b1}}; initial nlili0l44 = 0; always @ ( posedge clk_2) nlili0l44 <= nlili0l43; initial nlilill41 = 0; always @ ( posedge clk_2) nlilill41 <= nlilill42; event nlilill41_event; initial #1 ->nlilill41_event; always @(nlilill41_event) nlilill41 <= {1{1'b1}}; initial nlilill42 = 0; always @ ( posedge clk_2) nlilill42 <= nlilill41; initial nlililO39 = 0; always @ ( posedge clk_2) nlililO39 <= nlililO40; event nlililO39_event; initial #1 ->nlililO39_event; always @(nlililO39_event) nlililO39 <= {1{1'b1}}; initial nlililO40 = 0; always @ ( posedge clk_2) nlililO40 <= nlililO39; initial nliliOi37 = 0; always @ ( posedge clk_2) nliliOi37 <= nliliOi38; event nliliOi37_event; initial #1 ->nliliOi37_event; always @(nliliOi37_event) nliliOi37 <= {1{1'b1}}; initial nliliOi38 = 0; always @ ( posedge clk_2) nliliOi38 <= nliliOi37; initial nliliOl35 = 0; always @ ( posedge clk_2) nliliOl35 <= nliliOl36; event nliliOl35_event; initial #1 ->nliliOl35_event; always @(nliliOl35_event) nliliOl35 <= {1{1'b1}}; initial nliliOl36 = 0; always @ ( posedge clk_2) nliliOl36 <= nliliOl35; initial nliliOO33 = 0; always @ ( posedge clk_2) nliliOO33 <= nliliOO34; event nliliOO33_event; initial #1 ->nliliOO33_event; always @(nliliOO33_event) nliliOO33 <= {1{1'b1}}; initial nliliOO34 = 0; always @ ( posedge clk_2) nliliOO34 <= nliliOO33; initial nlill0l25 = 0; always @ ( posedge clk_2) nlill0l25 <= nlill0l26; event nlill0l25_event; initial #1 ->nlill0l25_event; always @(nlill0l25_event) nlill0l25 <= {1{1'b1}}; initial nlill0l26 = 0; always @ ( posedge clk_2) nlill0l26 <= nlill0l25; initial nlill1i31 = 0; always @ ( posedge clk_2) nlill1i31 <= nlill1i32; event nlill1i31_event; initial #1 ->nlill1i31_event; always @(nlill1i31_event) nlill1i31 <= {1{1'b1}}; initial nlill1i32 = 0; always @ ( posedge clk_2) nlill1i32 <= nlill1i31; initial nlill1l29 = 0; always @ ( posedge clk_2) nlill1l29 <= nlill1l30; event nlill1l29_event; initial #1 ->nlill1l29_event; always @(nlill1l29_event) nlill1l29 <= {1{1'b1}}; initial nlill1l30 = 0; always @ ( posedge clk_2) nlill1l30 <= nlill1l29; initial nlill1O27 = 0; always @ ( posedge clk_2) nlill1O27 <= nlill1O28; event nlill1O27_event; initial #1 ->nlill1O27_event; always @(nlill1O27_event) nlill1O27 <= {1{1'b1}}; initial nlill1O28 = 0; always @ ( posedge clk_2) nlill1O28 <= nlill1O27; initial nlilliO23 = 0; always @ ( posedge clk_2) nlilliO23 <= nlilliO24; event nlilliO23_event; initial #1 ->nlilliO23_event; always @(nlilliO23_event) nlilliO23 <= {1{1'b1}}; initial nlilliO24 = 0; always @ ( posedge clk_2) nlilliO24 <= nlilliO23; initial nlillll21 = 0; always @ ( posedge clk_2) nlillll21 <= nlillll22; event nlillll21_event; initial #1 ->nlillll21_event; always @(nlillll21_event) nlillll21 <= {1{1'b1}}; initial nlillll22 = 0; always @ ( posedge clk_2) nlillll22 <= nlillll21; initial nlilO0O15 = 0; always @ ( posedge clk_2) nlilO0O15 <= nlilO0O16; event nlilO0O15_event; initial #1 ->nlilO0O15_event; always @(nlilO0O15_event) nlilO0O15 <= {1{1'b1}}; initial nlilO0O16 = 0; always @ ( posedge clk_2) nlilO0O16 <= nlilO0O15; initial nlilO1i19 = 0; always @ ( posedge clk_2) nlilO1i19 <= nlilO1i20; event nlilO1i19_event; initial #1 ->nlilO1i19_event; always @(nlilO1i19_event) nlilO1i19 <= {1{1'b1}}; initial nlilO1i20 = 0; always @ ( posedge clk_2) nlilO1i20 <= nlilO1i19; initial nlilO1O17 = 0; always @ ( posedge clk_2) nlilO1O17 <= nlilO1O18; event nlilO1O17_event; initial #1 ->nlilO1O17_event; always @(nlilO1O17_event) nlilO1O17 <= {1{1'b1}}; initial nlilO1O18 = 0; always @ ( posedge clk_2) nlilO1O18 <= nlilO1O17; initial nlilOli13 = 0; always @ ( posedge clk_2) nlilOli13 <= nlilOli14; event nlilOli13_event; initial #1 ->nlilOli13_event; always @(nlilOli13_event) nlilOli13 <= {1{1'b1}}; initial nlilOli14 = 0; always @ ( posedge clk_2) nlilOli14 <= nlilOli13; initial nlilOlO11 = 0; always @ ( posedge clk_2) nlilOlO11 <= nlilOlO12; event nlilOlO11_event; initial #1 ->nlilOlO11_event; always @(nlilOlO11_event) nlilOlO11 <= {1{1'b1}}; initial nlilOlO12 = 0; always @ ( posedge clk_2) nlilOlO12 <= nlilOlO11; initial nlilOOl10 = 0; always @ ( posedge clk_2) nlilOOl10 <= nlilOOl9; initial nlilOOl9 = 0; always @ ( posedge clk_2) nlilOOl9 <= nlilOOl10; event nlilOOl9_event; initial #1 ->nlilOOl9_event; always @(nlilOOl9_event) nlilOOl9 <= {1{1'b1}}; initial nlilOOO7 = 0; always @ ( posedge clk_2) nlilOOO7 <= nlilOOO8; event nlilOOO7_event; initial #1 ->nlilOOO7_event; always @(nlilOOO7_event) nlilOOO7 <= {1{1'b1}}; initial nlilOOO8 = 0; always @ ( posedge clk_2) nlilOOO8 <= nlilOOO7; initial nliO10i3 = 0; always @ ( posedge clk_2) nliO10i3 <= nliO10i4; event nliO10i3_event; initial #1 ->nliO10i3_event; always @(nliO10i3_event) nliO10i3 <= {1{1'b1}}; initial nliO10i4 = 0; always @ ( posedge clk_2) nliO10i4 <= nliO10i3; initial nliO11l5 = 0; always @ ( posedge clk_2) nliO11l5 <= nliO11l6; event nliO11l5_event; initial #1 ->nliO11l5_event; always @(nliO11l5_event) nliO11l5 <= {1{1'b1}}; initial nliO11l6 = 0; always @ ( posedge clk_2) nliO11l6 <= nliO11l5; initial nliO1iO1 = 0; always @ ( posedge clk_2) nliO1iO1 <= nliO1iO2; event nliO1iO1_event; initial #1 ->nliO1iO1_event; always @(nliO1iO1_event) nliO1iO1 <= {1{1'b1}}; initial nliO1iO2 = 0; always @ ( posedge clk_2) nliO1iO2 <= nliO1iO1; initial begin n0111i = 0; n0111l = 0; n1000i = 0; n1000l = 0; n1000O = 0; n1001i = 0; n1001l = 0; n1001O = 0; n100ii = 0; n100il = 0; n100li = 0; n100ll = 0; n100lO = 0; n100Oi = 0; n100Ol = 0; n100OO = 0; n101Ol = 0; n101OO = 0; n10i0i = 0; n10i0l = 0; n10i0O = 0; n10i1i = 0; n10i1l = 0; n10i1O = 0; n10iii = 0; n10iil = 0; n10iiO = 0; n10ili = 0; n10ill = 0; n10ilO = 0; n10iOl = 0; n10iOO = 0; n10l0i = 0; n10l0l = 0; n10l0O = 0; n10l1i = 0; n10l1l = 0; n10l1O = 0; n10lii = 0; n10lil = 0; n10liO = 0; n10lli = 0; n10lll = 0; n10llO = 0; n10lOi = 0; n10lOl = 0; n10lOO = 0; n10O1i = 0; n10O1l = 0; n10O1O = 0; n110iO = 0; n110li = 0; n110ll = 0; n110lO = 0; n11iil = 0; n11iiO = 0; n11ili = 0; n11ill = 0; n11ilO = 0; n11iOi = 0; n11iOl = 0; n11iOO = 0; n11O0i = 0; n11O0l = 0; n11O0O = 0; n11O1i = 0; n11O1l = 0; n11O1O = 0; n1l = 0; n1liil = 0; n1liiO = 0; n1lili = 0; n1ll1i = 0; n1ll1l = 0; n1O00i = 0; n1O00l = 0; n1O01l = 0; n1O01O = 0; ni0OOi = 0; ni0OOl = 0; ni0OOO = 0; nii00i = 0; nii00l = 0; nii00O = 0; nii01i = 0; nii01l = 0; nii01O = 0; nii0ii = 0; nii0il = 0; nii0iO = 0; nii0ll = 0; nii0Ol = 0; nii0OO = 0; nii10i = 0; nii10l = 0; nii10O = 0; nii11i = 0; nii11l = 0; nii11O = 0; nii1ii = 0; nii1il = 0; nii1iO = 0; nii1li = 0; nii1ll = 0; nii1lO = 0; nii1Oi = 0; nii1Ol = 0; nii1OO = 0; niii1i = 0; niOlOl = 0; niOlOO = 0; niOO0i = 0; niOO0l = 0; niOO0O = 0; niOO1i = 0; niOO1l = 0; niOO1O = 0; niOOii = 0; niOOil = 0; niOOli = 0; niOOll = 0; niOOlO = 0; niOOOi = 0; niOOOl = 0; niOOOO = 0; nl100i = 0; nl100l = 0; nl100O = 0; nl101i = 0; nl101l = 0; nl101O = 0; nl10ii = 0; nl10il = 0; nl10iO = 0; nl10li = 0; nl10ll = 0; nl10lO = 0; nl10Oi = 0; nl10Ol = 0; nl10OO = 0; nl110i = 0; nl110l = 0; nl110O = 0; nl111i = 0; nl111l = 0; nl111O = 0; nl11ii = 0; nl11il = 0; nl11iO = 0; nl11li = 0; nl11ll = 0; nl11lO = 0; nl11OO = 0; nl1i0i = 0; nl1i1i = 0; nl1i1l = 0; nl1i1O = 0; nli0il = 0; nli0Ol = 0; nli0OO = 0; nli1ll = 0; nli1lO = 0; nli1Oi = 0; nli1Ol = 0; nlii0i = 0; nlii0l = 0; nlii0O = 0; nlii1i = 0; nlii1l = 0; nliilO = 0; nliiOi = 0; nlil0i = 0; nlil0l = 0; nlil0O = 0; nlil1O = 0; nlilOl = 0; nliO01l = 0; nliO01O = 0; nliO1i = 0; nlll = 0; nlO00OO = 0; nlOi1iO = 0; nlOiO0i = 0; nlOiO0l = 0; nlOiO0O = 0; nlOiO1O = 0; nlOiOii = 0; nlOl0OO = 0; nlOli0i = 0; nlOli0l = 0; nlOli0O = 0; nlOli1i = 0; nlOli1l = 0; nlOli1O = 0; nlOliii = 0; nlOliil = 0; nlOliiO = 0; nlOlili = 0; nlOlilO = 0; nlOliOO = 0; nlOll1i = 0; nlOll1l = 0; end always @ (clk_2 or wire_n1i_PRN or wire_n1i_CLRN) begin if (wire_n1i_PRN == 1'b0) begin n0111i <= 1; n0111l <= 1; n1000i <= 1; n1000l <= 1; n1000O <= 1; n1001i <= 1; n1001l <= 1; n1001O <= 1; n100ii <= 1; n100il <= 1; n100li <= 1; n100ll <= 1; n100lO <= 1; n100Oi <= 1; n100Ol <= 1; n100OO <= 1; n101Ol <= 1; n101OO <= 1; n10i0i <= 1; n10i0l <= 1; n10i0O <= 1; n10i1i <= 1; n10i1l <= 1; n10i1O <= 1; n10iii <= 1; n10iil <= 1; n10iiO <= 1; n10ili <= 1; n10ill <= 1; n10ilO <= 1; n10iOl <= 1; n10iOO <= 1; n10l0i <= 1; n10l0l <= 1; n10l0O <= 1; n10l1i <= 1; n10l1l <= 1; n10l1O <= 1; n10lii <= 1; n10lil <= 1; n10liO <= 1; n10lli <= 1; n10lll <= 1; n10llO <= 1; n10lOi <= 1; n10lOl <= 1; n10lOO <= 1; n10O1i <= 1; n10O1l <= 1; n10O1O <= 1; n110iO <= 1; n110li <= 1; n110ll <= 1; n110lO <= 1; n11iil <= 1; n11iiO <= 1; n11ili <= 1; n11ill <= 1; n11ilO <= 1; n11iOi <= 1; n11iOl <= 1; n11iOO <= 1; n11O0i <= 1; n11O0l <= 1; n11O0O <= 1; n11O1i <= 1; n11O1l <= 1; n11O1O <= 1; n1l <= 1; n1liil <= 1; n1liiO <= 1; n1lili <= 1; n1ll1i <= 1; n1ll1l <= 1; n1O00i <= 1; n1O00l <= 1; n1O01l <= 1; n1O01O <= 1; ni0OOi <= 1; ni0OOl <= 1; ni0OOO <= 1; nii00i <= 1; nii00l <= 1; nii00O <= 1; nii01i <= 1; nii01l <= 1; nii01O <= 1; nii0ii <= 1; nii0il <= 1; nii0iO <= 1; nii0ll <= 1; nii0Ol <= 1; nii0OO <= 1; nii10i <= 1; nii10l <= 1; nii10O <= 1; nii11i <= 1; nii11l <= 1; nii11O <= 1; nii1ii <= 1; nii1il <= 1; nii1iO <= 1; nii1li <= 1; nii1ll <= 1; nii1lO <= 1; nii1Oi <= 1; nii1Ol <= 1; nii1OO <= 1; niii1i <= 1; niOlOl <= 1; niOlOO <= 1; niOO0i <= 1; niOO0l <= 1; niOO0O <= 1; niOO1i <= 1; niOO1l <= 1; niOO1O <= 1; niOOii <= 1; niOOil <= 1; niOOli <= 1; niOOll <= 1; niOOlO <= 1; niOOOi <= 1; niOOOl <= 1; niOOOO <= 1; nl100i <= 1; nl100l <= 1; nl100O <= 1; nl101i <= 1; nl101l <= 1; nl101O <= 1; nl10ii <= 1; nl10il <= 1; nl10iO <= 1; nl10li <= 1; nl10ll <= 1; nl10lO <= 1; nl10Oi <= 1; nl10Ol <= 1; nl10OO <= 1; nl110i <= 1; nl110l <= 1; nl110O <= 1; nl111i <= 1; nl111l <= 1; nl111O <= 1; nl11ii <= 1; nl11il <= 1; nl11iO <= 1; nl11li <= 1; nl11ll <= 1; nl11lO <= 1; nl11OO <= 1; nl1i0i <= 1; nl1i1i <= 1; nl1i1l <= 1; nl1i1O <= 1; nli0il <= 1; nli0Ol <= 1; nli0OO <= 1; nli1ll <= 1; nli1lO <= 1; nli1Oi <= 1; nli1Ol <= 1; nlii0i <= 1; nlii0l <= 1; nlii0O <= 1; nlii1i <= 1; nlii1l <= 1; nliilO <= 1; nliiOi <= 1; nlil0i <= 1; nlil0l <= 1; nlil0O <= 1; nlil1O <= 1; nlilOl <= 1; nliO01l <= 1; nliO01O <= 1; nliO1i <= 1; nlll <= 1; nlO00OO <= 1; nlOi1iO <= 1; nlOiO0i <= 1; nlOiO0l <= 1; nlOiO0O <= 1; nlOiO1O <= 1; nlOiOii <= 1; nlOl0OO <= 1; nlOli0i <= 1; nlOli0l <= 1; nlOli0O <= 1; nlOli1i <= 1; nlOli1l <= 1; nlOli1O <= 1; nlOliii <= 1; nlOliil <= 1; nlOliiO <= 1; nlOlili <= 1; nlOlilO <= 1; nlOliOO <= 1; nlOll1i <= 1; nlOll1l <= 1; end else if (wire_n1i_CLRN == 1'b0) begin n0111i <= 0; n0111l <= 0; n1000i <= 0; n1000l <= 0; n1000O <= 0; n1001i <= 0; n1001l <= 0; n1001O <= 0; n100ii <= 0; n100il <= 0; n100li <= 0; n100ll <= 0; n100lO <= 0; n100Oi <= 0; n100Ol <= 0; n100OO <= 0; n101Ol <= 0; n101OO <= 0; n10i0i <= 0; n10i0l <= 0; n10i0O <= 0; n10i1i <= 0; n10i1l <= 0; n10i1O <= 0; n10iii <= 0; n10iil <= 0; n10iiO <= 0; n10ili <= 0; n10ill <= 0; n10ilO <= 0; n10iOl <= 0; n10iOO <= 0; n10l0i <= 0; n10l0l <= 0; n10l0O <= 0; n10l1i <= 0; n10l1l <= 0; n10l1O <= 0; n10lii <= 0; n10lil <= 0; n10liO <= 0; n10lli <= 0; n10lll <= 0; n10llO <= 0; n10lOi <= 0; n10lOl <= 0; n10lOO <= 0; n10O1i <= 0; n10O1l <= 0; n10O1O <= 0; n110iO <= 0; n110li <= 0; n110ll <= 0; n110lO <= 0; n11iil <= 0; n11iiO <= 0; n11ili <= 0; n11ill <= 0; n11ilO <= 0; n11iOi <= 0; n11iOl <= 0; n11iOO <= 0; n11O0i <= 0; n11O0l <= 0; n11O0O <= 0; n11O1i <= 0; n11O1l <= 0; n11O1O <= 0; n1l <= 0; n1liil <= 0; n1liiO <= 0; n1lili <= 0; n1ll1i <= 0; n1ll1l <= 0; n1O00i <= 0; n1O00l <= 0; n1O01l <= 0; n1O01O <= 0; ni0OOi <= 0; ni0OOl <= 0; ni0OOO <= 0; nii00i <= 0; nii00l <= 0; nii00O <= 0; nii01i <= 0; nii01l <= 0; nii01O <= 0; nii0ii <= 0; nii0il <= 0; nii0iO <= 0; nii0ll <= 0; nii0Ol <= 0; nii0OO <= 0; nii10i <= 0; nii10l <= 0; nii10O <= 0; nii11i <= 0; nii11l <= 0; nii11O <= 0; nii1ii <= 0; nii1il <= 0; nii1iO <= 0; nii1li <= 0; nii1ll <= 0; nii1lO <= 0; nii1Oi <= 0; nii1Ol <= 0; nii1OO <= 0; niii1i <= 0; niOlOl <= 0; niOlOO <= 0; niOO0i <= 0; niOO0l <= 0; niOO0O <= 0; niOO1i <= 0; niOO1l <= 0; niOO1O <= 0; niOOii <= 0; niOOil <= 0; niOOli <= 0; niOOll <= 0; niOOlO <= 0; niOOOi <= 0; niOOOl <= 0; niOOOO <= 0; nl100i <= 0; nl100l <= 0; nl100O <= 0; nl101i <= 0; nl101l <= 0; nl101O <= 0; nl10ii <= 0; nl10il <= 0; nl10iO <= 0; nl10li <= 0; nl10ll <= 0; nl10lO <= 0; nl10Oi <= 0; nl10Ol <= 0; nl10OO <= 0; nl110i <= 0; nl110l <= 0; nl110O <= 0; nl111i <= 0; nl111l <= 0; nl111O <= 0; nl11ii <= 0; nl11il <= 0; nl11iO <= 0; nl11li <= 0; nl11ll <= 0; nl11lO <= 0; nl11OO <= 0; nl1i0i <= 0; nl1i1i <= 0; nl1i1l <= 0; nl1i1O <= 0; nli0il <= 0; nli0Ol <= 0; nli0OO <= 0; nli1ll <= 0; nli1lO <= 0; nli1Oi <= 0; nli1Ol <= 0; nlii0i <= 0; nlii0l <= 0; nlii0O <= 0; nlii1i <= 0; nlii1l <= 0; nliilO <= 0; nliiOi <= 0; nlil0i <= 0; nlil0l <= 0; nlil0O <= 0; nlil1O <= 0; nlilOl <= 0; nliO01l <= 0; nliO01O <= 0; nliO1i <= 0; nlll <= 0; nlO00OO <= 0; nlOi1iO <= 0; nlOiO0i <= 0; nlOiO0l <= 0; nlOiO0O <= 0; nlOiO1O <= 0; nlOiOii <= 0; nlOl0OO <= 0; nlOli0i <= 0; nlOli0l <= 0; nlOli0O <= 0; nlOli1i <= 0; nlOli1l <= 0; nlOli1O <= 0; nlOliii <= 0; nlOliil <= 0; nlOliiO <= 0; nlOlili <= 0; nlOlilO <= 0; nlOliOO <= 0; nlOll1i <= 0; nlOll1l <= 0; end else if (clk_2 != n1i_clk_prev && clk_2 == 1'b1) begin n0111i <= wire_n0110i_dataout; n0111l <= wire_n0110l_dataout; n1000i <= wire_n10Oli_dataout; n1000l <= wire_n10Oll_dataout; n1000O <= wire_n10OlO_dataout; n1001i <= wire_n10Oii_dataout; n1001l <= wire_n10Oil_dataout; n1001O <= wire_n10OiO_dataout; n100ii <= wire_n10OOi_dataout; n100il <= wire_n10OOl_dataout; n100li <= wire_n1i11i_dataout; n100ll <= wire_n1i11l_dataout; n100lO <= wire_n1i11O_dataout; n100Oi <= wire_n1i10i_dataout; n100Ol <= wire_n1i10l_dataout; n100OO <= wire_n1i10O_dataout; n101Ol <= wire_n10O0l_dataout; n101OO <= wire_n10O0O_dataout; n10i0i <= wire_n1i1li_dataout; n10i0l <= wire_n1i1ll_dataout; n10i0O <= wire_n1i1lO_dataout; n10i1i <= wire_n1i1ii_dataout; n10i1l <= wire_n1i1il_dataout; n10i1O <= wire_n1i1iO_dataout; n10iii <= wire_n1i1Oi_dataout; n10iil <= wire_n1i1Ol_dataout; n10iiO <= wire_n1i1OO_dataout; n10ili <= wire_n1i01i_dataout; n10ill <= wire_n1i01l_dataout; n10ilO <= wire_n1i01O_dataout; n10iOl <= wire_n1i00l_dataout; n10iOO <= wire_n1i00O_dataout; n10l0i <= wire_n1i0li_dataout; n10l0l <= wire_n1i0ll_dataout; n10l0O <= wire_n1i0lO_dataout; n10l1i <= wire_n1i0ii_dataout; n10l1l <= wire_n1i0il_dataout; n10l1O <= wire_n1i0iO_dataout; n10lii <= wire_n1i0Oi_dataout; n10lil <= wire_n1i0Ol_dataout; n10liO <= wire_n1i0OO_dataout; n10lli <= wire_n1ii1i_dataout; n10lll <= wire_n1ii1l_dataout; n10llO <= wire_n1ii1O_dataout; n10lOi <= wire_n1ii0i_dataout; n10lOl <= wire_n1ii0l_dataout; n10lOO <= wire_n1ii0O_dataout; n10O1i <= wire_n1iiii_dataout; n10O1l <= wire_n1iiil_dataout; n10O1O <= wire_n1lill_dataout; n110iO <= n110ll; n110li <= wire_n110Oi_dataout; n110ll <= wire_n110Ol_dataout; n110lO <= wire_n11l1i_dataout; n11iil <= wire_n11l1l_dataout; n11iiO <= wire_n11l1O_dataout; n11ili <= wire_n11l0i_dataout; n11ill <= wire_n11l0l_dataout; n11ilO <= wire_n11l0O_dataout; n11iOi <= wire_n11lii_dataout; n11iOl <= wire_n11lil_dataout; n11iOO <= wire_n101iO_dataout; n11O0i <= wire_n11Oil_dataout; n11O0l <= wire_n11OiO_dataout; n11O0O <= wire_n10O0i_dataout; n11O1i <= wire_n101ll_dataout; n11O1l <= wire_n101li_dataout; n11O1O <= wire_n11Oii_dataout; n1l <= wire_niO_dataout; n1liil <= wire_n1lilO_dataout; n1liiO <= wire_n1liOi_dataout; n1lili <= n1ll1i; n1ll1i <= ((~ rgenericfifo) & nlO1Oii); n1ll1l <= wire_n1O0il_dataout; n1O00i <= wire_n1O0ll_dataout; n1O00l <= wire_n1O0lO_dataout; n1O01l <= wire_n1O0iO_dataout; n1O01O <= wire_n1O0li_dataout; ni0OOi <= wire_niii1l_dataout; ni0OOl <= wire_niii1O_dataout; ni0OOO <= wire_niii0i_dataout; nii00i <= wire_niilil_dataout; nii00l <= wire_niiliO_dataout; nii00O <= wire_niilli_dataout; nii01i <= wire_niil0l_dataout; nii01l <= wire_niil0O_dataout; nii01O <= wire_niilii_dataout; nii0ii <= wire_niilll_dataout; nii0il <= wire_niillO_dataout; nii0iO <= wire_niilOi_dataout; nii0ll <= wire_niilOl_dataout; nii0Ol <= wire_niilOO_dataout; nii0OO <= wire_niiO1i_dataout; nii10i <= wire_niiiil_dataout; nii10l <= wire_niiiiO_dataout; nii10O <= wire_niiili_dataout; nii11i <= wire_niii0l_dataout; nii11l <= wire_niii0O_dataout; nii11O <= wire_niiiii_dataout; nii1ii <= wire_niiill_dataout; nii1il <= wire_niiilO_dataout; nii1iO <= wire_niiiOi_dataout; nii1li <= wire_niiiOl_dataout; nii1ll <= wire_niiiOO_dataout; nii1lO <= wire_niil1i_dataout; nii1Oi <= wire_niil1l_dataout; nii1Ol <= wire_niil1O_dataout; nii1OO <= wire_niil0i_dataout; niii1i <= wire_nl1i0l_dataout; niOlOl <= wire_nl1i0O_dataout; niOlOO <= wire_nl1iii_dataout; niOO0i <= wire_nl1ill_dataout; niOO0l <= wire_nl1ilO_dataout; niOO0O <= wire_nl1iOi_dataout; niOO1i <= wire_nl1iil_dataout; niOO1l <= wire_nl1iiO_dataout; niOO1O <= wire_nl1ili_dataout; niOOii <= wire_nl1iOl_dataout; niOOil <= wire_nl1iOO_dataout; niOOli <= wire_nl1l1l_dataout; niOOll <= wire_nl1l1O_dataout; niOOlO <= wire_nl1l0i_dataout; niOOOi <= wire_nl1l0l_dataout; niOOOl <= wire_nl1l0O_dataout; niOOOO <= wire_nl1lii_dataout; nl100i <= wire_nl1Oli_dataout; nl100l <= wire_nl1Oll_dataout; nl100O <= wire_nl1OlO_dataout; nl101i <= wire_nl1Oii_dataout; nl101l <= wire_nl1Oil_dataout; nl101O <= wire_nl1OiO_dataout; nl10ii <= wire_nl1OOi_dataout; nl10il <= wire_nl1OOl_dataout; nl10iO <= wire_nl1OOO_dataout; nl10li <= wire_nl011i_dataout; nl10ll <= wire_nl011l_dataout; nl10lO <= wire_nl011O_dataout; nl10Oi <= wire_nl010i_dataout; nl10Ol <= wire_nl010l_dataout; nl10OO <= wire_nl010O_dataout; nl110i <= wire_nl1lll_dataout; nl110l <= wire_nl1llO_dataout; nl110O <= wire_nl1lOi_dataout; nl111i <= wire_nl1lil_dataout; nl111l <= wire_nl1liO_dataout; nl111O <= wire_nl1lli_dataout; nl11ii <= wire_nl1lOl_dataout; nl11il <= wire_nl1lOO_dataout; nl11iO <= wire_nl1O1i_dataout; nl11li <= wire_nl1O1l_dataout; nl11ll <= wire_nl1O1O_dataout; nl11lO <= wire_nl1O0i_dataout; nl11OO <= wire_nl1O0O_dataout; nl1i0i <= wire_nli01O_dataout; nl1i1i <= wire_nl01ii_dataout; nl1i1l <= wire_nl01il_dataout; nl1i1O <= wire_nl01iO_dataout; nli0il <= nli0Ol; nli0Ol <= (rgenericfifo & rdenable); nli0OO <= nlii1i; nli1ll <= wire_nli00i_dataout; nli1lO <= wire_nli00l_dataout; nli1Oi <= wire_nli00O_dataout; nli1Ol <= wire_nli0ii_dataout; nlii0i <= wire_nliiil_dataout; nlii0l <= wire_nliiiO_dataout; nlii0O <= nliilO; nlii1i <= sync_status; nlii1l <= wire_nliiii_dataout; nliilO <= ((~ rgenericfifo) & n0Ol0O); nliiOi <= nlil1O; nlil0i <= wire_nlilii_dataout; nlil0l <= wire_nlilil_dataout; nlil0O <= wire_nlilOO_dataout; nlil1O <= nlil0l; nlilOl <= wire_nliO0i_dataout; nliO01l <= wire_nliO00l_dataout; nliO01O <= wire_nliO00O_dataout; nliO1i <= wire_nliO1O_dataout; nlll <= n1l; nlO00OO <= wire_nlOi1li_dataout; nlOi1iO <= nlOiO1O; nlOiO0i <= nlOiO0l; nlOiO0l <= sync_status; nlOiO0O <= nlOiOii; nlOiO1O <= (rgenericfifo & rdenable); nlOiOii <= align_status; nlOl0OO <= wire_nlOll1O_dataout; nlOli0i <= wire_nlOllii_dataout; nlOli0l <= wire_nlOllil_dataout; nlOli0O <= wire_nlOlliO_dataout; nlOli1i <= wire_nlOll0i_dataout; nlOli1l <= wire_nlOll0l_dataout; nlOli1O <= wire_nlOll0O_dataout; nlOliii <= wire_nlOllli_dataout; nlOliil <= wire_nlOllll_dataout; nlOliiO <= wire_nlOlllO_dataout; nlOlili <= wire_nlOllOi_dataout; nlOlilO <= wire_nlOllOl_dataout; nlOliOO <= wire_nlOllOO_dataout; nlOll1i <= wire_nlOlO1i_dataout; nlOll1l <= n110iO; end n1i_clk_prev <= clk_2; end assign wire_n1i_CLRN = ((nlilOOO8 ^ nlilOOO7) & (~ nliO1il)), wire_n1i_PRN = (nlilOOl10 ^ nlilOOl9); initial begin n0l0iO = 0; ni11ll = 0; ni11lO = 0; ni11Ol = 0; nlliiOO = 0; nllil1i = 0; nllil1l = 0; nlllO0l = 0; end always @ (clk_1 or wire_ni11Oi_PRN or wire_ni11Oi_CLRN) begin if (wire_ni11Oi_PRN == 1'b0) begin n0l0iO <= 1; ni11ll <= 1; ni11lO <= 1; ni11Ol <= 1; nlliiOO <= 1; nllil1i <= 1; nllil1l <= 1; nlllO0l <= 1; end else if (wire_ni11Oi_CLRN == 1'b0) begin n0l0iO <= 0; ni11ll <= 0; ni11lO <= 0; ni11Ol <= 0; nlliiOO <= 0; nllil1i <= 0; nllil1l <= 0; nlllO0l <= 0; end else if (clk_1 != ni11Oi_clk_prev && clk_1 == 1'b1) begin n0l0iO <= wire_n0ll0l_dataout; ni11ll <= wire_ni100i_dataout; ni11lO <= wire_ni100l_dataout; ni11Ol <= wire_ni100O_dataout; nlliiOO <= wire_nllilii_dataout; nllil1i <= wire_nllilil_dataout; nllil1l <= wire_nlliliO_dataout; nlllO0l <= wire_nllO01i_dataout; end ni11Oi_clk_prev <= clk_1; end assign wire_ni11Oi_CLRN = (nliil1l58 ^ nliil1l57), wire_ni11Oi_PRN = ((nliil1i60 ^ nliil1i59) & (~ wire_nl0i_dataout)); event n0l0iO_event; event ni11ll_event; event ni11lO_event; event ni11Ol_event; event nlliiOO_event; event nllil1i_event; event nllil1l_event; event nlllO0l_event; initial #1 ->n0l0iO_event; initial #1 ->ni11ll_event; initial #1 ->ni11lO_event; initial #1 ->ni11Ol_event; initial #1 ->nlliiOO_event; initial #1 ->nllil1i_event; initial #1 ->nllil1l_event; initial #1 ->nlllO0l_event; always @(n0l0iO_event) n0l0iO <= 1; always @(ni11ll_event) ni11ll <= 1; always @(ni11lO_event) ni11lO <= 1; always @(ni11Ol_event) ni11Ol <= 1; always @(nlliiOO_event) nlliiOO <= 1; always @(nllil1i_event) nllil1i <= 1; always @(nllil1l_event) nllil1l <= 1; always @(nlllO0l_event) nlllO0l <= 1; initial begin n0111O = 0; n0l00l = 0; n0l00O = 0; n0l0ii = 0; n0l0il = 0; n0l0li = 0; n0l0ll = 0; n0l0lO = 0; n0l0Oi = 0; n0l0Ol = 0; n0l0OO = 0; n0li0i = 0; n0li0l = 0; n0li0O = 0; n0li1i = 0; n0li1l = 0; n0li1O = 0; n0liii = 0; n0liil = 0; n0liiO = 0; n0lili = 0; n0lill = 0; n0lilO = 0; n0liOi = 0; n0liOl = 0; n0O0ll = 0; n0O0lO = 0; n0O0Oi = 0; n0O0Ol = 0; n0O0OO = 0; n0Oiil = 0; n0OiOl = 0; n0OiOO = 0; n0Ol0i = 0; n0Ol0l = 0; n0Ol0O = 0; n0Ol1l = 0; n0Ol1O = 0; n0OO1O = 0; n0OOli = 0; n0OOll = 0; n1O = 0; ni000i = 0; ni000l = 0; ni00il = 0; ni00iO = 0; ni00Oi = 0; ni101i = 0; ni101l = 0; ni110i = 0; ni110l = 0; ni111i = 0; ni111l = 0; ni111O = 0; ni11OO = 0; ni1i0i = 0; ni1i0l = 0; ni1i0O = 0; ni1i1l = 0; ni1i1O = 0; ni1llO = 0; ni1O0i = 0; ni1O0l = 0; ni1O0O = 0; ni1O1l = 0; ni1O1O = 0; nil = 0; nliO00i = 0; nliO1l = 0; nlli00O = 0; nlli0Oi = 0; nlli0Ol = 0; nlli1ii = 0; nlli1il = 0; nlli1iO = 0; nlli1li = 0; nlli1ll = 0; nllii0l = 0; nllii0O = 0; nllii1O = 0; nlliiii = 0; nlliiil = 0; nlliiiO = 0; nlliiO = 0; nllil0i = 0; nllil0l = 0; nllil1O = 0; nllili = 0; nllill = 0; nllilO = 0; nlliOi = 0; nlliOl = 0; nlliOO = 0; nlll0i = 0; nlll0l = 0; nlll0O = 0; nlll10l = 0; nlll10O = 0; nlll1i = 0; nlll1ii = 0; nlll1il = 0; nlll1iO = 0; nlll1l = 0; nlll1li = 0; nlll1O = 0; nlllii = 0; nlllil = 0; nllliO = 0; nllll0O = 0; nlllli = 0; nllllii = 0; nlllliO = 0; nlllll = 0; nllllli = 0; nllllO = 0; nlllO0i = 0; nlllO0O = 0; nlllO1i = 0; nlllO1l = 0; nlllO1O = 0; nlllOi = 0; nlllOii = 0; nlllOil = 0; nlllOiO = 0; nlllOl = 0; nlllOli = 0; nlllOll = 0; nlllOlO = 0; nlllOO = 0; nlllOOi = 0; nlllOOl = 0; nlllOOO = 0; nllO0i = 0; nllO0l = 0; nllO10i = 0; nllO10l = 0; nllO10O = 0; nllO11i = 0; nllO11l = 0; nllO11O = 0; nllO1i = 0; nllO1ii = 0; nllO1il = 0; nllO1iO = 0; nllO1l = 0; nllO1li = 0; nllO1O = 0; nllOOi = 0; nllOOl = 0; nlO00ii = 0; nlO00li = 0; nlO00ll = 0; nlO00lO = 0; nlO00Oi = 0; nlO00Ol = 0; nlO011i = 0; nlO011l = 0; nlO01l = 0; nlO01O = 0; nlO10li = 0; nlO10ll = 0; nlO10lO = 0; nlO10Oi = 0; nlO1i0O = 0; nlO1Oii = 0; nlO1OiO = 0; nlO1OOi = 0; nlO1OOl = 0; nlO1OOO = 0; end always @ ( posedge clk_1 or negedge wire_nii_CLRN) begin if (wire_nii_CLRN == 1'b0) begin n0111O <= 0; n0l00l <= 0; n0l00O <= 0; n0l0ii <= 0; n0l0il <= 0; n0l0li <= 0; n0l0ll <= 0; n0l0lO <= 0; n0l0Oi <= 0; n0l0Ol <= 0; n0l0OO <= 0; n0li0i <= 0; n0li0l <= 0; n0li0O <= 0; n0li1i <= 0; n0li1l <= 0; n0li1O <= 0; n0liii <= 0; n0liil <= 0; n0liiO <= 0; n0lili <= 0; n0lill <= 0; n0lilO <= 0; n0liOi <= 0; n0liOl <= 0; n0O0ll <= 0; n0O0lO <= 0; n0O0Oi <= 0; n0O0Ol <= 0; n0O0OO <= 0; n0Oiil <= 0; n0OiOl <= 0; n0OiOO <= 0; n0Ol0i <= 0; n0Ol0l <= 0; n0Ol0O <= 0; n0Ol1l <= 0; n0Ol1O <= 0; n0OO1O <= 0; n0OOli <= 0; n0OOll <= 0; n1O <= 0; ni000i <= 0; ni000l <= 0; ni00il <= 0; ni00iO <= 0; ni00Oi <= 0; ni101i <= 0; ni101l <= 0; ni110i <= 0; ni110l <= 0; ni111i <= 0; ni111l <= 0; ni111O <= 0; ni11OO <= 0; ni1i0i <= 0; ni1i0l <= 0; ni1i0O <= 0; ni1i1l <= 0; ni1i1O <= 0; ni1llO <= 0; ni1O0i <= 0; ni1O0l <= 0; ni1O0O <= 0; ni1O1l <= 0; ni1O1O <= 0; nil <= 0; nliO00i <= 0; nliO1l <= 0; nlli00O <= 0; nlli0Oi <= 0; nlli0Ol <= 0; nlli1ii <= 0; nlli1il <= 0; nlli1iO <= 0; nlli1li <= 0; nlli1ll <= 0; nllii0l <= 0; nllii0O <= 0; nllii1O <= 0; nlliiii <= 0; nlliiil <= 0; nlliiiO <= 0; nlliiO <= 0; nllil0i <= 0; nllil0l <= 0; nllil1O <= 0; nllili <= 0; nllill <= 0; nllilO <= 0; nlliOi <= 0; nlliOl <= 0; nlliOO <= 0; nlll0i <= 0; nlll0l <= 0; nlll0O <= 0; nlll10l <= 0; nlll10O <= 0; nlll1i <= 0; nlll1ii <= 0; nlll1il <= 0; nlll1iO <= 0; nlll1l <= 0; nlll1li <= 0; nlll1O <= 0; nlllii <= 0; nlllil <= 0; nllliO <= 0; nllll0O <= 0; nlllli <= 0; nllllii <= 0; nlllliO <= 0; nlllll <= 0; nllllli <= 0; nllllO <= 0; nlllO0i <= 0; nlllO0O <= 0; nlllO1i <= 0; nlllO1l <= 0; nlllO1O <= 0; nlllOi <= 0; nlllOii <= 0; nlllOil <= 0; nlllOiO <= 0; nlllOl <= 0; nlllOli <= 0; nlllOll <= 0; nlllOlO <= 0; nlllOO <= 0; nlllOOi <= 0; nlllOOl <= 0; nlllOOO <= 0; nllO0i <= 0; nllO0l <= 0; nllO10i <= 0; nllO10l <= 0; nllO10O <= 0; nllO11i <= 0; nllO11l <= 0; nllO11O <= 0; nllO1i <= 0; nllO1ii <= 0; nllO1il <= 0; nllO1iO <= 0; nllO1l <= 0; nllO1li <= 0; nllO1O <= 0; nllOOi <= 0; nllOOl <= 0; nlO00ii <= 0; nlO00li <= 0; nlO00ll <= 0; nlO00lO <= 0; nlO00Oi <= 0; nlO00Ol <= 0; nlO011i <= 0; nlO011l <= 0; nlO01l <= 0; nlO01O <= 0; nlO10li <= 0; nlO10ll <= 0; nlO10lO <= 0; nlO10Oi <= 0; nlO1i0O <= 0; nlO1Oii <= 0; nlO1OiO <= 0; nlO1OOi <= 0; nlO1OOl <= 0; nlO1OOO <= 0; end else begin n0111O <= wire_n0110O_dataout; n0l00l <= wire_n0ll1i_dataout; n0l00O <= wire_n0ll1l_dataout; n0l0ii <= wire_n0ll1O_dataout; n0l0il <= wire_n0ll0i_dataout; n0l0li <= wire_n0ll0O_dataout; n0l0ll <= wire_n0llii_dataout; n0l0lO <= wire_n0llil_dataout; n0l0Oi <= wire_n0lliO_dataout; n0l0Ol <= wire_n0llli_dataout; n0l0OO <= wire_n0llll_dataout; n0li0i <= wire_n0llOO_dataout; n0li0l <= wire_n0lO1i_dataout; n0li0O <= wire_n0lO1l_dataout; n0li1i <= wire_n0lllO_dataout; n0li1l <= wire_n0llOi_dataout; n0li1O <= wire_n0llOl_dataout; n0liii <= wire_n0lO1O_dataout; n0liil <= wire_n0lO0i_dataout; n0liiO <= wire_n0lO0l_dataout; n0lili <= wire_n0lO0O_dataout; n0lill <= wire_n0lOii_dataout; n0lilO <= wire_n0lOil_dataout; n0liOi <= wire_n0lOiO_dataout; n0liOl <= wire_n0Oi1O_dataout; n0O0ll <= wire_n0liOO_dataout; n0O0lO <= wire_n0Oi0i_dataout; n0O0Oi <= wire_n0Oi0l_dataout; n0O0Ol <= wire_n0Oi0O_dataout; n0O0OO <= wire_n0Oiii_dataout; n0Oiil <= n0OiOl; n0OiOl <= (rgenericfifo & wrenable); n0OiOO <= wire_n0Olii_dataout; n0Ol0i <= wire_n0Olli_dataout; n0Ol0l <= wire_n0Olll_dataout; n0Ol0O <= wire_n0OO0i_dataout; n0Ol1l <= wire_n0Olil_dataout; n0Ol1O <= wire_n0OliO_dataout; n0OO1O <= n0OOli; n0OOli <= nliiO0O; n0OOll <= wire_ni110O_dataout; n1O <= nil; ni000i <= wire_ni00ii_dataout; ni000l <= wire_ni00li_dataout; ni00il <= wire_ni00ll_dataout; ni00iO <= wire_ni00OO_dataout; ni00Oi <= wire_ni0iiO_dataout; ni101i <= wire_ni10il_dataout; ni101l <= wire_ni1iii_dataout; ni110i <= wire_ni11li_dataout; ni110l <= wire_ni101O_dataout; ni111i <= wire_ni11ii_dataout; ni111l <= wire_ni11il_dataout; ni111O <= wire_ni11iO_dataout; ni11OO <= wire_ni10ii_dataout; ni1i0i <= wire_ni1ili_dataout; ni1i0l <= wire_ni1ill_dataout; ni1i0O <= wire_ni1lOi_dataout; ni1i1l <= wire_ni1iil_dataout; ni1i1O <= wire_ni1iiO_dataout; ni1llO <= wire_ni1Oii_dataout; ni1O0i <= wire_ni1Oli_dataout; ni1O0l <= wire_ni1Oll_dataout; ni1O0O <= wire_ni000O_dataout; ni1O1l <= wire_ni1Oil_dataout; ni1O1O <= wire_ni1OiO_dataout; nil <= wire_niO_dataout; nliO00i <= wire_nliO0ii_dataout; nliO1l <= sudi[0]; nlli00O <= wire_nlli1lO_dataout; nlli0Oi <= nli0l0i; nlli0Ol <= wire_nllii0i_dataout; nlli1ii <= wire_nlli1Oi_dataout; nlli1il <= wire_nlli1Ol_dataout; nlli1iO <= wire_nlli1OO_dataout; nlli1li <= wire_nlli01i_dataout; nlli1ll <= nlli0Oi; nllii0l <= wire_nlliill_dataout; nllii0O <= wire_nlliilO_dataout; nllii1O <= wire_nlliili_dataout; nlliiii <= wire_nlliiOi_dataout; nlliiil <= wire_nlliiOl_dataout; nlliiiO <= wire_nllil0O_dataout; nlliiO <= sudi[1]; nllil0i <= wire_nllilll_dataout; nllil0l <= wire_nlll1ll_dataout; nllil1O <= wire_nllilli_dataout; nllili <= sudi[2]; nllill <= sudi[3]; nllilO <= sudi[4]; nlliOi <= sudi[5]; nlliOl <= sudi[6]; nlliOO <= sudi[7]; nlll0i <= sudi[11]; nlll0l <= sudi[12]; nlll0O <= sudi[13]; nlll10l <= wire_nlll1lO_dataout; nlll10O <= wire_nlll1Oi_dataout; nlll1i <= sudi[8]; nlll1ii <= wire_nlll1Ol_dataout; nlll1il <= wire_nlll1OO_dataout; nlll1iO <= wire_nlll01i_dataout; nlll1l <= sudi[9]; nlll1li <= nllll0O; nlll1O <= sudi[10]; nlllii <= sudi[14]; nlllil <= sudi[15]; nllliO <= sudi[16]; nllll0O <= (rgenericfifo & wrenable); nlllli <= sudi[17]; nllllii <= wire_nllllll_dataout; nlllliO <= wire_nlllllO_dataout; nlllll <= sudi[18]; nllllli <= wire_nllO1ll_dataout; nllllO <= sudi[19]; nlllO0i <= wire_nllO1OO_dataout; nlllO0O <= wire_nllO01l_dataout; nlllO1i <= wire_nllO1lO_dataout; nlllO1l <= wire_nllO1Oi_dataout; nlllO1O <= wire_nllO1Ol_dataout; nlllOi <= sudi[20]; nlllOii <= wire_nllO01O_dataout; nlllOil <= wire_nllO00i_dataout; nlllOiO <= wire_nllO00l_dataout; nlllOl <= sudi[21]; nlllOli <= wire_nllO00O_dataout; nlllOll <= wire_nllO0ii_dataout; nlllOlO <= wire_nllO0il_dataout; nlllOO <= sudi[22]; nlllOOi <= wire_nllO0iO_dataout; nlllOOl <= wire_nllO0li_dataout; nlllOOO <= wire_nllO0ll_dataout; nllO0i <= sudi[26]; nllO0l <= sudi[27]; nllO10i <= wire_nllO0OO_dataout; nllO10l <= wire_nllOi1i_dataout; nllO10O <= wire_nllOi1l_dataout; nllO11i <= wire_nllO0lO_dataout; nllO11l <= wire_nllO0Oi_dataout; nllO11O <= wire_nllO0Ol_dataout; nllO1i <= sudi[23]; nllO1ii <= wire_nllOi1O_dataout; nllO1il <= wire_nllOi0i_dataout; nllO1iO <= wire_nllOi0l_dataout; nllO1l <= sudi[24]; nllO1li <= wire_nlO1i1i_dataout; nllO1O <= sudi[25]; nllOOi <= wire_nlO11i_o; nllOOl <= wire_nlO11l_o; nlO00ii <= (rclkcmpsqmd & (wire_nlOi10l_dataout & (((nlillil | nlO00Oi) | nlO00lO) | nlO00ll))); nlO00li <= wire_nlO0i1i_dataout; nlO00ll <= wire_nlO0i1O_dataout; nlO00lO <= wire_nlO0i0l_dataout; nlO00Oi <= wire_nlO0iiO_dataout; nlO00Ol <= wire_nlO0l1O_dataout; nlO011i <= wire_nlO01ii_dataout; nlO011l <= wire_nlO00il_dataout; nlO01l <= wire_nlO11O_o; nlO01O <= wire_nllOOO_o; nlO10li <= wire_nlO1i1l_dataout; nlO10ll <= wire_nlO1i1O_dataout; nlO10lO <= wire_nlO1i0i_dataout; nlO10Oi <= wire_nlO1i0l_dataout; nlO1i0O <= wire_nlO1Oil_dataout; nlO1Oii <= wire_nlO1Oli_dataout; nlO1OiO <= wire_nlO011O_dataout; nlO1OOi <= wire_nlO010i_dataout; nlO1OOl <= wire_nlO010l_dataout; nlO1OOO <= wire_nlO010O_dataout; end end assign wire_nii_CLRN = ((nliO10i4 ^ nliO10i3) & (~ wire_nl0i_dataout)); initial begin ni00Ol = 0; ni0liO = 0; ni0lli = 0; ni0lll = 0; ni0llO = 0; ni0lOi = 0; ni0lOl = 0; ni0lOO = 0; ni0O0i = 0; ni0O0l = 0; ni0O0O = 0; ni0O1i = 0; ni0O1l = 0; ni0O1O = 0; ni0Oii = 0; ni0Oil = 0; ni0OiO = 0; ni0Oli = 0; ni0Oll = 0; ni0OlO = 0; nii0li = 0; nii0Oi = 0; end always @ ( posedge clk_2 or negedge wire_nii0lO_CLRN) begin if (wire_nii0lO_CLRN == 1'b0) begin ni00Ol <= 0; ni0liO <= 0; ni0lli <= 0; ni0lll <= 0; ni0llO <= 0; ni0lOi <= 0; ni0lOl <= 0; ni0lOO <= 0; ni0O0i <= 0; ni0O0l <= 0; ni0O0O <= 0; ni0O1i <= 0; ni0O1l <= 0; ni0O1O <= 0; ni0Oii <= 0; ni0Oil <= 0; ni0OiO <= 0; ni0Oli <= 0; ni0Oll <= 0; ni0OlO <= 0; nii0li <= 0; nii0Oi <= 0; end else if (nlil0l == 1'b0) begin ni00Ol <= wire_niiO1l_dataout; ni0liO <= wire_niiO1O_dataout; ni0lli <= wire_niiO0i_dataout; ni0lll <= wire_niiO0l_dataout; ni0llO <= wire_niiO0O_dataout; ni0lOi <= wire_niiOii_dataout; ni0lOl <= wire_niiOil_dataout; ni0lOO <= wire_niiOiO_dataout; ni0O0i <= wire_nil11l_dataout; ni0O0l <= wire_nil11O_dataout; ni0O0O <= wire_nil10i_dataout; ni0O1i <= wire_niiOli_dataout; ni0O1l <= wire_niiOll_dataout; ni0O1O <= wire_nil11i_dataout; ni0Oii <= wire_nil10l_dataout; ni0Oil <= wire_nil10O_dataout; ni0OiO <= wire_nil1ii_dataout; ni0Oli <= wire_nil1il_dataout; ni0Oll <= wire_nil1iO_dataout; ni0OlO <= wire_nil1li_dataout; nii0li <= wire_niliil_dataout; nii0Oi <= wire_nilili_dataout; end end assign wire_nii0lO_CLRN = ((nliiOOi56 ^ nliiOOi55) & (~ nliO1il)); initial begin n0Oi1i = 0; n0Oi1l = 0; niiOlO = 0; niiOOi = 0; niiOOO = 0; nlli10i = 0; nlli10l = 0; nlli10O = 0; nlO10Ol = 0; nlO10OO = 0; end always @ (clk_1 or wire_niiOOl_PRN or wire_niiOOl_CLRN) begin if (wire_niiOOl_PRN == 1'b0) begin n0Oi1i <= 1; n0Oi1l <= 1; niiOlO <= 1; niiOOi <= 1; niiOOO <= 1; nlli10i <= 1; nlli10l <= 1; nlli10O <= 1; nlO10Ol <= 1; nlO10OO <= 1; end else if (wire_niiOOl_CLRN == 1'b0) begin n0Oi1i <= 0; n0Oi1l <= 0; niiOlO <= 0; niiOOi <= 0; niiOOO <= 0; nlli10i <= 0; nlli10l <= 0; nlli10O <= 0; nlO10Ol <= 0; nlO10OO <= 0; end else if (clk_1 != niiOOl_clk_prev && clk_1 == 1'b1) begin n0Oi1i <= wire_n0Oili_dataout; n0Oi1l <= wire_n0OiiO_dataout; niiOlO <= wire_n0Oill_dataout; niiOOi <= wire_n0OilO_dataout; niiOOO <= wire_n0OiOi_dataout; nlli10i <= wire_nlO1ill_dataout; nlli10l <= wire_nlO1ili_dataout; nlli10O <= wire_nlO1iiO_dataout; nlO10Ol <= wire_nlO1iil_dataout; nlO10OO <= wire_nlO1iii_dataout; end niiOOl_clk_prev <= clk_1; end assign wire_niiOOl_CLRN = (nliiOOO52 ^ nliiOOO51), wire_niiOOl_PRN = (nliiOOl54 ^ nliiOOl53); initial begin nl0l = 0; nO = 0; end always @ (clk_1 or nliO1il or wire_nl_CLRN) begin if (nliO1il == 1'b1) begin nl0l <= 1; nO <= 1; end else if (wire_nl_CLRN == 1'b0) begin nl0l <= 0; nO <= 0; end else if (clk_1 != nl_clk_prev && clk_1 == 1'b1) begin nl0l <= nlilOil; nO <= nl0l; end nl_clk_prev <= clk_1; end assign wire_nl_CLRN = (nliO1iO2 ^ nliO1iO1); event nl0l_event; event nO_event; initial #1 ->nl0l_event; initial #1 ->nO_event; always @(nl0l_event) nl0l <= 1; always @(nO_event) nO <= 1; initial begin n100iO = 0; n10iOi = 0; niOOiO = 0; nl11Ol = 0; end always @ ( posedge clk_2 or posedge nliO1il) begin if (nliO1il == 1'b1) begin n100iO <= 1; n10iOi <= 1; niOOiO <= 1; nl11Ol <= 1; end else begin n100iO <= wire_n10OOO_dataout; n10iOi <= wire_n1i00i_dataout; niOOiO <= wire_nl1l1i_dataout; nl11Ol <= wire_nl1O0l_dataout; end end event n100iO_event; event n10iOi_event; event niOOiO_event; event nl11Ol_event; initial #1 ->n100iO_event; initial #1 ->n10iOi_event; initial #1 ->niOOiO_event; initial #1 ->nl11Ol_event; always @(n100iO_event) n100iO <= 1; always @(n10iOi_event) n10iOi <= 1; always @(niOOiO_event) niOOiO <= 1; always @(nl11Ol_event) nl11Ol <= 1; initial begin n0l00i = 0; n0l01l = 0; n0l01O = 0; n1O00O = 0; n1O0ii = 0; nli01l = 0; nli1OO = 0; nlli11i = 0; nlli11l = 0; nlli11O = 0; end always @ ( posedge clk_2 or negedge wire_nli01i_PRN) begin if (wire_nli01i_PRN == 1'b0) begin n0l00i <= 1; n0l01l <= 1; n0l01O <= 1; n1O00O <= 1; n1O0ii <= 1; nli01l <= 1; nli1OO <= 1; nlli11i <= 1; nlli11l <= 1; nlli11O <= 1; end else begin n0l00i <= wire_nli0ll_dataout; n0l01l <= wire_nli0Oi_dataout; n0l01O <= wire_nli0lO_dataout; n1O00O <= wire_n1O0Ol_dataout; n1O0ii <= wire_n1O0Oi_dataout; nli01l <= wire_nli0iO_dataout; nli1OO <= wire_nli0li_dataout; nlli11i <= wire_n1Oi1l_dataout; nlli11l <= wire_n1Oi1i_dataout; nlli11O <= wire_n1O0OO_dataout; end end assign wire_nli01i_PRN = (nlil01l50 ^ nlil01l49); initial begin nl0O = 0; nlli = 0; end always @ ( posedge clk_2 or posedge hard_reset) begin if (hard_reset == 1'b1) begin nl0O <= 1; nlli <= 1; end else begin nl0O <= wire_nllO_dataout; nlli <= nl0O; end end event nl0O_event; event nlli_event; initial #1 ->nl0O_event; initial #1 ->nlli_event; always @(nl0O_event) nl0O <= 1; always @(nlli_event) nlli <= 1; initial begin nlOiOil = 0; nlOiOli = 0; nlOiOll = 0; nlOiOlO = 0; nlOiOOi = 0; nlOiOOl = 0; nlOiOOO = 0; nlOl00i = 0; nlOl00l = 0; nlOl00O = 0; nlOl01i = 0; nlOl01l = 0; nlOl01O = 0; nlOl0ii = 0; nlOl0il = 0; nlOl0iO = 0; nlOl0li = 0; nlOl0ll = 0; nlOl0lO = 0; nlOl0Oi = 0; nlOl0Ol = 0; nlOl10i = 0; nlOl10l = 0; nlOl10O = 0; nlOl11i = 0; nlOl11l = 0; nlOl11O = 0; nlOl1ii = 0; nlOl1il = 0; nlOl1iO = 0; nlOl1li = 0; nlOl1ll = 0; nlOl1lO = 0; nlOl1Oi = 0; nlOl1Ol = 0; nlOl1OO = 0; nlOlill = 0; nlOliOl = 0; end always @ (clk_2 or wire_nlOliOi_PRN or nliO1il) begin if (wire_nlOliOi_PRN == 1'b0) begin nlOiOil <= 1; nlOiOli <= 1; nlOiOll <= 1; nlOiOlO <= 1; nlOiOOi <= 1; nlOiOOl <= 1; nlOiOOO <= 1; nlOl00i <= 1; nlOl00l <= 1; nlOl00O <= 1; nlOl01i <= 1; nlOl01l <= 1; nlOl01O <= 1; nlOl0ii <= 1; nlOl0il <= 1; nlOl0iO <= 1; nlOl0li <= 1; nlOl0ll <= 1; nlOl0lO <= 1; nlOl0Oi <= 1; nlOl0Ol <= 1; nlOl10i <= 1; nlOl10l <= 1; nlOl10O <= 1; nlOl11i <= 1; nlOl11l <= 1; nlOl11O <= 1; nlOl1ii <= 1; nlOl1il <= 1; nlOl1iO <= 1; nlOl1li <= 1; nlOl1ll <= 1; nlOl1lO <= 1; nlOl1Oi <= 1; nlOl1Ol <= 1; nlOl1OO <= 1; nlOlill <= 1; nlOliOl <= 1; end else if (nliO1il == 1'b1) begin nlOiOil <= 0; nlOiOli <= 0; nlOiOll <= 0; nlOiOlO <= 0; nlOiOOi <= 0; nlOiOOl <= 0; nlOiOOO <= 0; nlOl00i <= 0; nlOl00l <= 0; nlOl00O <= 0; nlOl01i <= 0; nlOl01l <= 0; nlOl01O <= 0; nlOl0ii <= 0; nlOl0il <= 0; nlOl0iO <= 0; nlOl0li <= 0; nlOl0ll <= 0; nlOl0lO <= 0; nlOl0Oi <= 0; nlOl0Ol <= 0; nlOl10i <= 0; nlOl10l <= 0; nlOl10O <= 0; nlOl11i <= 0; nlOl11l <= 0; nlOl11O <= 0; nlOl1ii <= 0; nlOl1il <= 0; nlOl1iO <= 0; nlOl1li <= 0; nlOl1ll <= 0; nlOl1lO <= 0; nlOl1Oi <= 0; nlOl1Ol <= 0; nlOl1OO <= 0; nlOlill <= 0; nlOliOl <= 0; end else if (nlii1Oi == 1'b0) if (clk_2 != nlOliOi_clk_prev && clk_2 == 1'b1) begin nlOiOil <= wire_nlOlOOl_dataout; nlOiOli <= wire_nlOlOOO_dataout; nlOiOll <= wire_nlOO11i_dataout; nlOiOlO <= wire_nlOO11l_dataout; nlOiOOi <= wire_nlOO11O_dataout; nlOiOOl <= wire_nlOO10i_dataout; nlOiOOO <= wire_nlOO10l_dataout; nlOl00i <= wire_nlOlO1O_dataout; nlOl00l <= wire_nlOlO0i_dataout; nlOl00O <= wire_nlOlO0l_dataout; nlOl01i <= wire_nlOO00O_dataout; nlOl01l <= wire_nlOO0ii_dataout; nlOl01O <= wire_nlOlO1l_dataout; nlOl0ii <= wire_nlOlO0O_dataout; nlOl0il <= wire_nlOlOii_dataout; nlOl0iO <= wire_nlOlOil_dataout; nlOl0li <= wire_nlOlOiO_dataout; nlOl0ll <= wire_nlOlOli_dataout; nlOl0lO <= wire_nlOlOll_dataout; nlOl0Oi <= wire_nlOlOlO_dataout; nlOl0Ol <= wire_nlOlOOi_dataout; nlOl10i <= wire_nlOO1iO_dataout; nlOl10l <= wire_nlOO1li_dataout; nlOl10O <= wire_nlOO1ll_dataout; nlOl11i <= wire_nlOO10O_dataout; nlOl11l <= wire_nlOO1ii_dataout; nlOl11O <= wire_nlOO1il_dataout; nlOl1ii <= wire_nlOO1lO_dataout; nlOl1il <= wire_nlOO1Oi_dataout; nlOl1iO <= wire_nlOO1Ol_dataout; nlOl1li <= wire_nlOO1OO_dataout; nlOl1ll <= wire_nlOO01i_dataout; nlOl1lO <= wire_nlOO01l_dataout; nlOl1Oi <= wire_nlOO01O_dataout; nlOl1Ol <= wire_nlOO00i_dataout; nlOl1OO <= wire_nlOO00l_dataout; nlOlill <= wire_nlOOi0i_dataout; nlOliOl <= wire_nlOOi0O_dataout; end nlOliOi_clk_prev <= clk_2; end assign wire_nlOliOi_PRN = (nli0O0O62 ^ nli0O0O61); assign wire_n00i_dataout = (rwa_6g_en === 1'b1) ? wire_nll1il_dataout : wire_nlOi01O_dataout; assign wire_n00l_dataout = (rwa_6g_en === 1'b1) ? wire_nll1iO_dataout : wire_nlOi00i_dataout; assign wire_n00O_dataout = (rwa_6g_en === 1'b1) ? wire_nll1li_dataout : wire_nlOi00l_dataout; and(wire_n0110i_dataout, n0111l, ~((~ nlil00O))); and(wire_n0110l_dataout, n0111O, ~((~ nlil00O))); and(wire_n0110O_dataout, wire_nlilOi_o, (rgenericfifo | wire_nliOOi_dataout)); assign wire_n01i_dataout = (rwa_6g_en === 1'b1) ? wire_nll10l_dataout : wire_nlOi1OO_dataout; assign wire_n01l_dataout = (rwa_6g_en === 1'b1) ? wire_nll10O_dataout : wire_nlOi01i_dataout; assign wire_n01O_dataout = (rwa_6g_en === 1'b1) ? wire_nll1ii_dataout : wire_nlOi01l_dataout; assign wire_n0ii_dataout = (rwa_6g_en === 1'b1) ? wire_nll1ll_dataout : wire_nlOi00O_dataout; assign wire_n0il_dataout = (rwa_6g_en === 1'b1) ? wire_nll1lO_dataout : wire_nlOi0ii_dataout; assign wire_n0iO_dataout = (rwa_6g_en === 1'b1) ? wire_nll1Oi_dataout : wire_nlOi0il_dataout; assign wire_n0li_dataout = (rwa_6g_en === 1'b1) ? wire_nll1Ol_dataout : wire_nlOi0iO_dataout; and(wire_n0liOO_dataout, wire_n0lOli_dataout, ~(nliiO1i)); assign wire_n0ll_dataout = (rwa_6g_en === 1'b1) ? wire_nll1OO_dataout : wire_nlOi0li_dataout; and(wire_n0ll0i_dataout, wire_n0lOOl_dataout, ~(nliiO1i)); or(wire_n0ll0l_dataout, wire_n0lOOO_dataout, nliiO1i); and(wire_n0ll0O_dataout, wire_n0O11i_dataout, ~(nliiO1i)); and(wire_n0ll1i_dataout, wire_n0lOll_dataout, ~(nliiO1i)); and(wire_n0ll1l_dataout, wire_n0lOlO_dataout, ~(nliiO1i)); and(wire_n0ll1O_dataout, wire_n0lOOi_dataout, ~(nliiO1i)); and(wire_n0llii_dataout, wire_n0O11l_dataout, ~(nliiO1i)); and(wire_n0llil_dataout, wire_n0O11O_dataout, ~(nliiO1i)); and(wire_n0lliO_dataout, wire_n0O10i_dataout, ~(nliiO1i)); and(wire_n0llli_dataout, wire_n0O10l_dataout, ~(nliiO1i)); and(wire_n0llll_dataout, wire_n0O10O_dataout, ~(nliiO1i)); and(wire_n0lllO_dataout, wire_n0O1ii_dataout, ~(nliiO1i)); and(wire_n0llOi_dataout, wire_n0O1il_dataout, ~(nliiO1i)); and(wire_n0llOl_dataout, wire_n0O1iO_dataout, ~(nliiO1i)); and(wire_n0llOO_dataout, wire_n0O1li_dataout, ~(nliiO1i)); assign wire_n0lO_dataout = (rwa_6g_en === 1'b1) ? wire_nll01i_dataout : wire_nlOi0ll_dataout; and(wire_n0lO0i_dataout, wire_n0O1Ol_dataout, ~(nliiO1i)); and(wire_n0lO0l_dataout, wire_n0O1OO_dataout, ~(nliiO1i)); and(wire_n0lO0O_dataout, wire_n0O01i_dataout, ~(nliiO1i)); and(wire_n0lO1i_dataout, wire_n0O1ll_dataout, ~(nliiO1i)); and(wire_n0lO1l_dataout, wire_n0O1lO_dataout, ~(nliiO1i)); and(wire_n0lO1O_dataout, wire_n0O1Oi_dataout, ~(nliiO1i)); and(wire_n0lOii_dataout, wire_n0O01l_dataout, ~(nliiO1i)); and(wire_n0lOil_dataout, wire_n0O01O_dataout, ~(nliiO1i)); and(wire_n0lOiO_dataout, wire_n0O00i_dataout, ~(nliiO1i)); assign wire_n0lOli_dataout = (nliilOl === 1'b1) ? wire_n0O00l_dataout : n0O0ll; assign wire_n0lOll_dataout = (nliilOl === 1'b1) ? wire_n0O00O_dataout : n0l00l; assign wire_n0lOlO_dataout = (nliilOl === 1'b1) ? wire_n0O0ii_dataout : n0l00O; assign wire_n0lOOi_dataout = (nliilOl === 1'b1) ? wire_n0O0il_dataout : n0l0ii; assign wire_n0lOOl_dataout = (nliilOl === 1'b1) ? wire_n0O0iO_dataout : n0l0il; assign wire_n0lOOO_dataout = (nliilOl === 1'b1) ? n0liOi : n0l0iO; assign wire_n0O00i_dataout = (nliilOl === 1'b1) ? n0lilO : n0liOi; and(wire_n0O00l_dataout, wire_n0O0li_o[0], ~(nliii0O)); and(wire_n0O00O_dataout, wire_n0O0li_o[1], ~(nliii0O)); assign wire_n0O01i_dataout = (nliilOl === 1'b1) ? n0liiO : n0lili; assign wire_n0O01l_dataout = (nliilOl === 1'b1) ? n0lili : n0lill; assign wire_n0O01O_dataout = (nliilOl === 1'b1) ? n0lill : n0lilO; and(wire_n0O0ii_dataout, wire_n0O0li_o[2], ~(nliii0O)); and(wire_n0O0il_dataout, wire_n0O0li_o[3], ~(nliii0O)); and(wire_n0O0iO_dataout, wire_n0O0li_o[4], ~(nliii0O)); assign wire_n0O10i_dataout = (nliilOl === 1'b1) ? n0l0lO : n0l0Oi; assign wire_n0O10l_dataout = (nliilOl === 1'b1) ? n0l0Oi : n0l0Ol; assign wire_n0O10O_dataout = (nliilOl === 1'b1) ? n0l0Ol : n0l0OO; assign wire_n0O11i_dataout = (nliilOl === 1'b1) ? n0l0iO : n0l0li; assign wire_n0O11l_dataout = (nliilOl === 1'b1) ? n0l0li : n0l0ll; assign wire_n0O11O_dataout = (nliilOl === 1'b1) ? n0l0ll : n0l0lO; assign wire_n0O1ii_dataout = (nliilOl === 1'b1) ? n0l0OO : n0li1i; assign wire_n0O1il_dataout = (nliilOl === 1'b1) ? n0li1i : n0li1l; assign wire_n0O1iO_dataout = (nliilOl === 1'b1) ? n0li1l : n0li1O; assign wire_n0O1li_dataout = (nliilOl === 1'b1) ? n0li1O : n0li0i; assign wire_n0O1ll_dataout = (nliilOl === 1'b1) ? n0li0i : n0li0l; assign wire_n0O1lO_dataout = (nliilOl === 1'b1) ? n0li0l : n0li0O; assign wire_n0O1Oi_dataout = (nliilOl === 1'b1) ? n0li0O : n0liii; assign wire_n0O1Ol_dataout = (nliilOl === 1'b1) ? n0liii : n0liil; assign wire_n0O1OO_dataout = (nliilOl === 1'b1) ? n0liil : n0liiO; and(wire_n0Oi_dataout, wire_nll01l_dataout, rwa_6g_en); and(wire_n0Oi0i_dataout, n0Oi1i, ~(nliiO1i)); and(wire_n0Oi0l_dataout, niiOlO, ~(nliiO1i)); and(wire_n0Oi0O_dataout, niiOOi, ~(nliiO1i)); and(wire_n0Oi1O_dataout, n0Oi1l, ~(nliiO1i)); and(wire_n0Oiii_dataout, niiOOO, ~(nliiO1i)); and(wire_n0OiiO_dataout, niii1i, ~(nliiO1i)); and(wire_n0Oili_dataout, niOlOl, ~(nliiO1i)); and(wire_n0Oill_dataout, niOlOO, ~(nliiO1i)); and(wire_n0OilO_dataout, niOO1i, ~(nliiO1i)); and(wire_n0OiOi_dataout, niOO1l, ~(nliiO1i)); and(wire_n0Ol_dataout, wire_nll01O_dataout, rwa_6g_en); and(wire_n0Olii_dataout, nliiiii, ~(nliiO1i)); and(wire_n0Olil_dataout, nliiiil, ~(nliiO1i)); and(wire_n0OliO_dataout, nliiiiO, ~(nliiO1i)); and(wire_n0Olli_dataout, nliiili, ~(nliiO1i)); and(wire_n0Olll_dataout, nliiill, ~(nliiO1i)); and(wire_n0OO_dataout, wire_nll00i_dataout, rwa_6g_en); and(wire_n0OO0i_dataout, wire_n0OO0l_dataout, wire_nliOOi_dataout); or(wire_n0OO0l_dataout, n0Ol0O, ((~ n0Ol0O) & nliiilO)); assign wire_n0OOii_dataout = (nliO11i === 1'b1) ? (nliiiOi | n0OO1O) : nliiiOi; and(wire_n1011i_dataout, wire_n1010i_o[0], nli0OOi); and(wire_n1011l_dataout, wire_n1010i_o[1], nli0OOi); and(wire_n1011O_dataout, wire_n1010i_o[2], nli0OOi); and(wire_n101iO_dataout, n11O1l, wire_nlOi11i_dataout); and(wire_n101li_dataout, (rclkcmpsqmd & (nlii1li & (~ n11O1l))), wire_nlOi11i_dataout); and(wire_n101ll_dataout, nlii1li, wire_nlOi11i_dataout); assign wire_n10i_dataout = (rwa_6g_en === 1'b1) ? nl10OO : n10lOl; assign wire_n10l_dataout = (rwa_6g_en === 1'b1) ? nl1i1i : n10lOO; assign wire_n10O_dataout = (rwa_6g_en === 1'b1) ? nl1i1l : n10O1i; and(wire_n10O0i_dataout, wire_n1iiiO_dataout, ~(nlii00O)); and(wire_n10O0l_dataout, wire_n1iili_dataout, ~(nlii00O)); and(wire_n10O0O_dataout, wire_n1iill_dataout, ~(nlii00O)); and(wire_n10Oii_dataout, wire_n1iilO_dataout, ~(nlii00O)); and(wire_n10Oil_dataout, wire_n1iiOi_dataout, ~(nlii00O)); and(wire_n10OiO_dataout, wire_n1iiOl_dataout, ~(nlii00O)); and(wire_n10Oli_dataout, wire_n1iiOO_dataout, ~(nlii00O)); and(wire_n10Oll_dataout, wire_n1il1i_dataout, ~(nlii00O)); and(wire_n10OlO_dataout, wire_n1il1l_dataout, ~(nlii00O)); and(wire_n10OOi_dataout, wire_n1il1O_dataout, ~(nlii00O)); and(wire_n10OOl_dataout, wire_n1il0i_dataout, ~(nlii00O)); or(wire_n10OOO_dataout, wire_n1il0l_dataout, nlii00O); assign wire_n1100i_dataout = (rclkcmpinsertpad === 1'b1) ? (~ nlOliOl) : nlOliOl; assign wire_n1100l_dataout = (rclkcmpinsertpad === 1'b1) ? nlOliOl : (~ nlOliOl); assign wire_n1100O_dataout = (nlilOiO === 1'b1) ? (nli0OiO | nlOll1l) : nli0OiO; or(wire_n1101i_dataout, nlOll1i, nlii1li); and(wire_n110Oi_dataout, nliO01l, ~(nlii00O)); and(wire_n110Ol_dataout, ((((n1lili & nliO01l) & (~ n110li)) & (rskpsetbased | nli0Oll)) & (~ nli0Oli)), ~(nlii00O)); assign wire_n1110i_dataout = (nlii1li === 1'b1) ? nlOiOlO : nlOli1O; assign wire_n1110l_dataout = (nlii1li === 1'b1) ? nlOiOOi : nlOli0i; assign wire_n1110O_dataout = (nlii1li === 1'b1) ? nlOiOOl : nlOli0l; assign wire_n1111i_dataout = (nlii1li === 1'b1) ? nlOiOil : nlOl0OO; assign wire_n1111l_dataout = (nlii1li === 1'b1) ? nlOiOli : nlOli1i; assign wire_n1111O_dataout = (nlii1li === 1'b1) ? nlOiOll : nlOli1l; assign wire_n111ii_dataout = (nlii1li === 1'b1) ? nlOiOOO : nlOli0O; assign wire_n111il_dataout = (nlii1li === 1'b1) ? nlOl11i : nlOliii; assign wire_n111iO_dataout = (nlii1li === 1'b1) ? nlOl11l : nlOliil; assign wire_n111li_dataout = (nlii1li === 1'b1) ? nlOl11O : nlOliiO; and(wire_n111ll_dataout, nlOlili, ~(nlii1li)); assign wire_n111lO_dataout = (nlii1li === 1'b1) ? nlOl10i : nlOlill; and(wire_n111Oi_dataout, nlOlilO, ~(nlii1li)); assign wire_n111Ol_dataout = (nlii1li === 1'b1) ? nlOl10l : nlOliOl; and(wire_n111OO_dataout, nlOliOO, ~(nlii1li)); assign wire_n11i_dataout = (rwa_6g_en === 1'b1) ? nl10lO : n10lll; assign wire_n11l_dataout = (rwa_6g_en === 1'b1) ? nl10Oi : n10llO; and(wire_n11l0i_dataout, wire_n11lll_dataout, ~(nlii00O)); and(wire_n11l0l_dataout, wire_n11llO_dataout, ~(nlii00O)); and(wire_n11l0O_dataout, wire_n11lOi_dataout, ~(nlii00O)); and(wire_n11l1i_dataout, nlii1li, ~(nlii00O)); and(wire_n11l1l_dataout, wire_n11liO_dataout, ~(nlii00O)); and(wire_n11l1O_dataout, wire_n11lli_dataout, ~(nlii00O)); and(wire_n11lii_dataout, wire_n11lOl_dataout, ~(nlii00O)); and(wire_n11lil_dataout, wire_n11lOO_dataout, ~(nlii00O)); and(wire_n11liO_dataout, n110lO, ~(nlii1li)); and(wire_n11lli_dataout, n11iil, ~(nlii1li)); and(wire_n11lll_dataout, n11iiO, ~(nlii1li)); and(wire_n11llO_dataout, n11ili, ~(nlii1li)); and(wire_n11lOi_dataout, n11ill, ~(nlii1li)); and(wire_n11lOl_dataout, n11ilO, ~(nlii1li)); and(wire_n11lOO_dataout, n11iOi, ~(nlii1li)); assign wire_n11O_dataout = (rwa_6g_en === 1'b1) ? nl10Ol : n10lOi; and(wire_n11Oii_dataout, wire_n11Oli_dataout, wire_nlOi11i_dataout); and(wire_n11Oil_dataout, wire_n11Oll_dataout, wire_nlOi11i_dataout); and(wire_n11OiO_dataout, wire_n11OlO_dataout, wire_nlOi11i_dataout); or(wire_n11Oli_dataout, wire_n11OOi_dataout, nli0OOO); and(wire_n11Oll_dataout, wire_n11OOl_dataout, ~(nli0OOO)); and(wire_n11OlO_dataout, wire_n11OOO_dataout, ~(nli0OOO)); assign wire_n11OOi_dataout = (nli0OOl === 1'b1) ? wire_n1010i_o[0] : wire_n1011i_dataout; assign wire_n11OOl_dataout = (nli0OOl === 1'b1) ? wire_n1010i_o[1] : wire_n1011l_dataout; assign wire_n11OOO_dataout = (nli0OOl === 1'b1) ? wire_n1010i_o[2] : wire_n1011O_dataout; or(wire_n1i00i_dataout, wire_n1iOiO_dataout, nlii00O); and(wire_n1i00l_dataout, wire_n1iOli_dataout, ~(nlii00O)); and(wire_n1i00O_dataout, wire_n1iOll_dataout, ~(nlii00O)); and(wire_n1i01i_dataout, wire_n1iO0O_dataout, ~(nlii00O)); and(wire_n1i01l_dataout, wire_n1iOii_dataout, ~(nlii00O)); and(wire_n1i01O_dataout, wire_n1iOil_dataout, ~(nlii00O)); and(wire_n1i0ii_dataout, wire_n1iOlO_dataout, ~(nlii00O)); and(wire_n1i0il_dataout, wire_n1iOOi_dataout, ~(nlii00O)); and(wire_n1i0iO_dataout, wire_n1iOOl_dataout, ~(nlii00O)); and(wire_n1i0li_dataout, wire_n1iOOO_dataout, ~(nlii00O)); and(wire_n1i0ll_dataout, wire_n1l11i_dataout, ~(nlii00O)); and(wire_n1i0lO_dataout, wire_n1l11l_dataout, ~(nlii00O)); and(wire_n1i0Oi_dataout, wire_n1l11O_dataout, ~(nlii00O)); and(wire_n1i0Ol_dataout, wire_n1l10i_dataout, ~(nlii00O)); and(wire_n1i0OO_dataout, wire_n1l10l_dataout, ~(nlii00O)); and(wire_n1i10i_dataout, wire_n1iliO_dataout, ~(nlii00O)); and(wire_n1i10l_dataout, wire_n1illi_dataout, ~(nlii00O)); and(wire_n1i10O_dataout, wire_n1illl_dataout, ~(nlii00O)); and(wire_n1i11i_dataout, wire_n1il0O_dataout, ~(nlii00O)); and(wire_n1i11l_dataout, wire_n1ilii_dataout, ~(nlii00O)); and(wire_n1i11O_dataout, wire_n1ilil_dataout, ~(nlii00O)); and(wire_n1i1ii_dataout, wire_n1illO_dataout, ~(nlii00O)); and(wire_n1i1il_dataout, wire_n1ilOi_dataout, ~(nlii00O)); and(wire_n1i1iO_dataout, wire_n1ilOl_dataout, ~(nlii00O)); and(wire_n1i1li_dataout, wire_n1ilOO_dataout, ~(nlii00O)); and(wire_n1i1ll_dataout, wire_n1iO1i_dataout, ~(nlii00O)); and(wire_n1i1lO_dataout, wire_n1iO1l_dataout, ~(nlii00O)); and(wire_n1i1Oi_dataout, wire_n1iO1O_dataout, ~(nlii00O)); and(wire_n1i1Ol_dataout, wire_n1iO0i_dataout, ~(nlii00O)); and(wire_n1i1OO_dataout, wire_n1iO0l_dataout, ~(nlii00O)); assign wire_n1ii_dataout = (rwa_6g_en === 1'b1) ? nl1i1O : n10O1l; and(wire_n1ii0i_dataout, wire_n1l1iO_dataout, ~(nlii00O)); and(wire_n1ii0l_dataout, wire_n1l1li_dataout, ~(nlii00O)); and(wire_n1ii0O_dataout, wire_n1l1ll_dataout, ~(nlii00O)); and(wire_n1ii1i_dataout, wire_n1l10O_dataout, ~(nlii00O)); and(wire_n1ii1l_dataout, wire_n1l1ii_dataout, ~(nlii00O)); and(wire_n1ii1O_dataout, wire_n1l1il_dataout, ~(nlii00O)); and(wire_n1iiii_dataout, wire_n1l1lO_dataout, ~(nlii00O)); and(wire_n1iiil_dataout, wire_n1l1Oi_dataout, ~(nlii00O)); assign wire_n1iiiO_dataout = (nlii10l === 1'b1) ? nlii11i : n11O0O; assign wire_n1iili_dataout = (nlii10l === 1'b1) ? (((wire_n1l01l_o[4] | wire_n1l01l_o[3]) | wire_n1l01l_o[2]) | wire_n1l01l_o[1]) : n101Ol; assign wire_n1iill_dataout = (nlii10l === 1'b1) ? nlii11l : n101OO; assign wire_n1iilO_dataout = (nlii10l === 1'b1) ? nlii11O : n1001i; assign wire_n1iiOi_dataout = (nlii10l === 1'b1) ? (((wire_n1l00O_o[18] | wire_n1l00O_o[17]) | wire_n1l00O_o[16]) | wire_n1l00O_o[15]) : n1001l; assign wire_n1iiOl_dataout = (nlii10l === 1'b1) ? wire_n1l0ii_dataout : n1001O; assign wire_n1iiOO_dataout = (nlii10l === 1'b1) ? wire_n1l0il_dataout : n1000i; assign wire_n1il_dataout = (rwa_6g_en === 1'b1) ? wire_ni1i1i_o : wire_nlli0iO_o; assign wire_n1il0i_dataout = (nlii10l === 1'b1) ? n10ilO : n100il; assign wire_n1il0l_dataout = (nlii10l === 1'b1) ? n100il : n100iO; assign wire_n1il0O_dataout = (nlii10l === 1'b1) ? n100iO : n100li; assign wire_n1il1i_dataout = (nlii10l === 1'b1) ? wire_n1l0iO_dataout : n1000l; assign wire_n1il1l_dataout = (nlii10l === 1'b1) ? wire_n1l0li_dataout : n1000O; assign wire_n1il1O_dataout = (nlii10l === 1'b1) ? wire_n1l0ll_dataout : n100ii; assign wire_n1ilii_dataout = (nlii10l === 1'b1) ? n100li : n100ll; assign wire_n1ilil_dataout = (nlii10l === 1'b1) ? n100ll : n100lO; assign wire_n1iliO_dataout = (nlii10l === 1'b1) ? n100lO : n100Oi; assign wire_n1illi_dataout = (nlii10l === 1'b1) ? n100Oi : n100Ol; assign wire_n1illl_dataout = (nlii10l === 1'b1) ? n100Ol : n100OO; assign wire_n1illO_dataout = (nlii10l === 1'b1) ? n100OO : n10i1i; assign wire_n1ilOi_dataout = (nlii10l === 1'b1) ? n10i1i : n10i1l; assign wire_n1ilOl_dataout = (nlii10l === 1'b1) ? n10i1l : n10i1O; assign wire_n1ilOO_dataout = (nlii10l === 1'b1) ? n10i1O : n10i0i; assign wire_n1iO_dataout = (rwa_6g_en === 1'b1) ? wire_nllOiO_o : wire_n1OllO_o; assign wire_n1iO0i_dataout = (nlii10l === 1'b1) ? n10iii : n10iil; assign wire_n1iO0l_dataout = (nlii10l === 1'b1) ? n10iil : n10iiO; assign wire_n1iO0O_dataout = (nlii10l === 1'b1) ? n10iiO : n10ili; assign wire_n1iO1i_dataout = (nlii10l === 1'b1) ? n10i0i : n10i0l; assign wire_n1iO1l_dataout = (nlii10l === 1'b1) ? n10i0l : n10i0O; assign wire_n1iO1O_dataout = (nlii10l === 1'b1) ? n10i0O : n10iii; assign wire_n1iOii_dataout = (nlii10l === 1'b1) ? n10ili : n10ill; assign wire_n1iOil_dataout = (nlii10l === 1'b1) ? n10ill : n10ilO; assign wire_n1iOiO_dataout = (nlii10l === 1'b1) ? n10O1l : n10iOi; assign wire_n1iOli_dataout = (nlii10l === 1'b1) ? n10iOi : n10iOl; assign wire_n1iOll_dataout = (nlii10l === 1'b1) ? n10iOl : n10iOO; assign wire_n1iOlO_dataout = (nlii10l === 1'b1) ? n10iOO : n10l1i; assign wire_n1iOOi_dataout = (nlii10l === 1'b1) ? n10l1i : n10l1l; assign wire_n1iOOl_dataout = (nlii10l === 1'b1) ? n10l1l : n10l1O; assign wire_n1iOOO_dataout = (nlii10l === 1'b1) ? n10l1O : n10l0i; and(wire_n1l0ii_dataout, wire_n1l0lO_o[0], ~(nlii10i)); and(wire_n1l0il_dataout, wire_n1l0lO_o[1], ~(nlii10i)); and(wire_n1l0iO_dataout, wire_n1l0lO_o[2], ~(nlii10i)); and(wire_n1l0li_dataout, wire_n1l0lO_o[3], ~(nlii10i)); and(wire_n1l0ll_dataout, wire_n1l0lO_o[4], ~(nlii10i)); assign wire_n1l10i_dataout = (nlii10l === 1'b1) ? n10lii : n10lil; assign wire_n1l10l_dataout = (nlii10l === 1'b1) ? n10lil : n10liO; assign wire_n1l10O_dataout = (nlii10l === 1'b1) ? n10liO : n10lli; assign wire_n1l11i_dataout = (nlii10l === 1'b1) ? n10l0i : n10l0l; assign wire_n1l11l_dataout = (nlii10l === 1'b1) ? n10l0l : n10l0O; assign wire_n1l11O_dataout = (nlii10l === 1'b1) ? n10l0O : n10lii; assign wire_n1l1ii_dataout = (nlii10l === 1'b1) ? n10lli : n10lll; assign wire_n1l1il_dataout = (nlii10l === 1'b1) ? n10lll : n10llO; assign wire_n1l1iO_dataout = (nlii10l === 1'b1) ? n10llO : n10lOi; assign wire_n1l1li_dataout = (nlii10l === 1'b1) ? n10lOi : n10lOl; assign wire_n1l1ll_dataout = (nlii10l === 1'b1) ? n10lOl : n10lOO; assign wire_n1l1lO_dataout = (nlii10l === 1'b1) ? n10lOO : n10O1i; assign wire_n1l1Oi_dataout = (nlii10l === 1'b1) ? n10O1i : n10O1l; assign wire_n1li_dataout = (rwa_6g_en === 1'b1) ? wire_nllOli_o : wire_n1OlOi_o; assign wire_n1li0i_dataout = (nlii10O === 1'b1) ? fifo_rd_in_comp_2 : n1lili; assign wire_n1li1O_dataout = (nlii1ii === 1'b1) ? fifo_rd_in_comp_0 : wire_n1li0i_dataout; and(wire_n1lill_dataout, (((~ rgenericfifo) & n1lili) | nlii1iO), ~(nlii00O)); and(wire_n1lilO_dataout, n1liiO, ~(nlii00O)); and(wire_n1liOi_dataout, nllOOi, ~(nlii00O)); assign wire_n1ll_dataout = (rwa_6g_en === 1'b1) ? (wire_nllOil_o & wire_nllOii_o) : ((wire_n1OOOi_o & wire_n1OOlO_o) & (nlilO0O16 ^ nlilO0O15)); assign wire_n1lO_dataout = (rwa_6g_en === 1'b1) ? wire_nll11i_dataout : wire_nlOi1ll_dataout; and(wire_n1O0il_dataout, n1O0ii, ~(nlii00O)); and(wire_n1O0iO_dataout, n1O00O, ~(nlii00O)); and(wire_n1O0li_dataout, nlli11O, ~(nlii00O)); and(wire_n1O0ll_dataout, nlli11l, ~(nlii00O)); and(wire_n1O0lO_dataout, nlli11i, ~(nlii00O)); and(wire_n1O0Oi_dataout, nlli00O, ~(nlii00O)); and(wire_n1O0Ol_dataout, nlli1ii, ~(nlii00O)); and(wire_n1O0OO_dataout, nlli1il, ~(nlii00O)); assign wire_n1O1ll_dataout = (nlilO0l === 1'b1) ? insert_incomplete_0 : n1liil; assign wire_n1O1lO_dataout = (nlilO0l === 1'b1) ? latency_comp_0 : (~ nlillii); assign wire_n1Oi_dataout = (rwa_6g_en === 1'b1) ? wire_nll11l_dataout : wire_nlOi1lO_dataout; and(wire_n1Oi1i_dataout, nlli1iO, ~(nlii00O)); and(wire_n1Oi1l_dataout, nlli1li, ~(nlii00O)); or(wire_n1Oi1O_dataout, (rskpsetbased & (nlii0li | nlii0iO)), ((~ rskpsetbased) & (nlii0il | nlii0ii))); assign wire_n1Oiil_dataout = (rskpsetbased === 1'b1) ? (nlii0lO | nlii0ll) : (nlii0Ol | nlii0Oi); assign wire_n1OiOi_dataout = (nliii1O === 1'b1) ? rclkcmpsq1n[0] : rclkcmpsq1n[10]; assign wire_n1OiOl_dataout = (nliii1O === 1'b1) ? rclkcmpsq1n[1] : rclkcmpsq1n[11]; assign wire_n1OiOO_dataout = (nliii1O === 1'b1) ? rclkcmpsq1n[2] : rclkcmpsq1n[12]; assign wire_n1Ol_dataout = (rwa_6g_en === 1'b1) ? wire_nll11O_dataout : wire_nlOi1Oi_dataout; assign wire_n1Ol0i_dataout = (nliii1O === 1'b1) ? rclkcmpsq1n[6] : rclkcmpsq1n[16]; assign wire_n1Ol0l_dataout = (nliii1O === 1'b1) ? rclkcmpsq1n[7] : rclkcmpsq1n[17]; assign wire_n1Ol0O_dataout = (nliii1O === 1'b1) ? rclkcmpsq1n[8] : rclkcmpsq1n[18]; assign wire_n1Ol1i_dataout = (nliii1O === 1'b1) ? rclkcmpsq1n[3] : rclkcmpsq1n[13]; assign wire_n1Ol1l_dataout = (nliii1O === 1'b1) ? rclkcmpsq1n[4] : rclkcmpsq1n[14]; assign wire_n1Ol1O_dataout = (nliii1O === 1'b1) ? rclkcmpsq1n[5] : rclkcmpsq1n[15]; assign wire_n1Olii_dataout = (nliii1O === 1'b1) ? rclkcmpsq1n[9] : rclkcmpsq1n[19]; assign wire_n1Olli_dataout = (nlilO0l === 1'b1) ? fifo_ovr_0 : nlO01O; assign wire_n1Olll_dataout = (nlilO0l === 1'b1) ? del_cond_met_0 : wire_n1OllO_o; assign wire_n1OlOl_dataout = (nliii0i === 1'b1) ? rclkcmpsq1p[10] : rclkcmpsq1p[0]; assign wire_n1OlOO_dataout = (nliii0i === 1'b1) ? rclkcmpsq1p[11] : rclkcmpsq1p[1]; assign wire_n1OO_dataout = (rwa_6g_en === 1'b1) ? wire_nll10i_dataout : wire_nlOi1Ol_dataout; assign wire_n1OO0i_dataout = (nliii0i === 1'b1) ? rclkcmpsq1p[15] : rclkcmpsq1p[5]; assign wire_n1OO0l_dataout = (nliii0i === 1'b1) ? rclkcmpsq1p[16] : rclkcmpsq1p[6]; assign wire_n1OO0O_dataout = (nliii0i === 1'b1) ? rclkcmpsq1p[17] : rclkcmpsq1p[7]; assign wire_n1OO1i_dataout = (nliii0i === 1'b1) ? rclkcmpsq1p[12] : rclkcmpsq1p[2]; assign wire_n1OO1l_dataout = (nliii0i === 1'b1) ? rclkcmpsq1p[13] : rclkcmpsq1p[3]; assign wire_n1OO1O_dataout = (nliii0i === 1'b1) ? rclkcmpsq1p[14] : rclkcmpsq1p[4]; assign wire_n1OOii_dataout = (nliii0i === 1'b1) ? rclkcmpsq1p[18] : rclkcmpsq1p[8]; assign wire_n1OOil_dataout = (nliii0i === 1'b1) ? rclkcmpsq1p[19] : rclkcmpsq1p[9]; assign wire_ni_dataout = (rwa_6g_en === 1'b1) ? ni101i : nllil0i; and(wire_ni000O_dataout, nliiO0O, ~(nliiO1i)); and(wire_ni00ii_dataout, nliiO0O, ~(nliiO1i)); and(wire_ni00li_dataout, (nliiOii & (nliiO1O | nliiO1l)), wire_nliOOi_dataout); and(wire_ni00ll_dataout, (nliiO0l | nliiO0i), wire_nliOOi_dataout); or(wire_ni00OO_dataout, ((nliiOli & (nliiOii & (wire_nliOOi_dataout & ni000l))) & (~ nliiO0O)), (rtruebac2bac & (nliiOli & (nliiOii & (wire_nliOOi_dataout & ni00iO))))); assign wire_ni010i_dataout = ((~ nliilll) === 1'b1) ? wire_ni01ii_o[3] : ni1O1O; assign wire_ni010l_dataout = ((~ nliilll) === 1'b1) ? wire_ni01ii_o[4] : ni1O0i; assign wire_ni010O_dataout = ((~ nliilll) === 1'b1) ? wire_ni01ii_o[5] : ni1O0l; assign wire_ni011i_dataout = (nliillO === 1'b1) ? wire_ni01il_o[4] : wire_ni010O_dataout; assign wire_ni011l_dataout = ((~ nliilll) === 1'b1) ? wire_ni01ii_o[1] : ni1llO; assign wire_ni011O_dataout = ((~ nliilll) === 1'b1) ? wire_ni01ii_o[2] : ni1O1l; and(wire_ni0i_dataout, wire_nll0il_dataout, rwa_6g_en); or(wire_ni0iiO_dataout, wire_ni0ili_dataout, (rtruebac2bac & (nliiOii & (nliiOli & (wire_nliOOi_dataout & ni00Oi))))); and(wire_ni0ili_dataout, ((nliiOli & nliiOii) & (~ nliiO0O)), (wire_nliOOi_dataout & ni00il)); and(wire_ni0l_dataout, wire_nll0iO_dataout, rwa_6g_en); and(wire_ni0O_dataout, wire_nll0li_dataout, rwa_6g_en); or(wire_ni100i_dataout, ni11lO, nliiO1i); or(wire_ni100l_dataout, wire_nllOli_o, nliiO1i); or(wire_ni100O_dataout, wire_ni10iO_dataout, nliiO1i); and(wire_ni101O_dataout, ni11OO, ~(nliiO1i)); and(wire_ni10ii_dataout, wire_nllOiO_o, ~(nliiO1i)); and(wire_ni10il_dataout, wire_ni10lO_dataout, ~(nliiO1i)); assign wire_ni10iO_dataout = (nliO11i === 1'b1) ? (nliil1O | ni11ll) : nliil1O; assign wire_ni10lO_dataout = (nliO11i === 1'b1) ? (nliil0i | ni110l) : nliil0i; and(wire_ni110O_dataout, ni101l, ~(nliiO1i)); and(wire_ni11ii_dataout, ni1i1l, ~(nliiO1i)); and(wire_ni11il_dataout, ni1i1O, ~(nliiO1i)); and(wire_ni11iO_dataout, ni1i0i, ~(nliiO1i)); and(wire_ni11li_dataout, ni1i0l, ~(nliiO1i)); and(wire_ni1i_dataout, wire_nll00l_dataout, rwa_6g_en); and(wire_ni1iii_dataout, wire_ni1ilO_dataout, ~(nliiO1i)); and(wire_ni1iil_dataout, wire_ni1iOi_dataout, ~(nliiO1i)); and(wire_ni1iiO_dataout, wire_ni1iOl_dataout, ~(nliiO1i)); and(wire_ni1ili_dataout, wire_ni1iOO_dataout, ~(nliiO1i)); and(wire_ni1ill_dataout, wire_ni1l1i_dataout, ~(nliiO1i)); and(wire_ni1ilO_dataout, wire_ni1l1l_dataout, ~(nliil0l)); and(wire_ni1iOi_dataout, wire_ni1l1O_dataout, ~(nliil0l)); assign wire_ni1iOl_dataout = (nliil0l === 1'b1) ? n0Ol0O : wire_ni1l0i_dataout; and(wire_ni1iOO_dataout, wire_ni1l0l_dataout, ~(nliil0l)); and(wire_ni1l_dataout, wire_nll00O_dataout, rwa_6g_en); assign wire_ni1l0i_dataout = (wire_ni1lli_o === 1'b1) ? wire_ni1liO_o[3] : wire_ni1lii_o[3]; assign wire_ni1l0l_dataout = (wire_ni1lli_o === 1'b1) ? wire_ni1liO_o[4] : wire_ni1lii_o[4]; assign wire_ni1l0O_dataout = (wire_ni1lli_o === 1'b1) ? wire_ni1liO_o[5] : wire_ni1lii_o[5]; assign wire_ni1l1i_dataout = (nliil0l === 1'b1) ? n0Ol0O : wire_ni1l0O_dataout; assign wire_ni1l1l_dataout = (wire_ni1lli_o === 1'b1) ? wire_ni1liO_o[1] : wire_ni1lii_o[1]; assign wire_ni1l1O_dataout = (wire_ni1lli_o === 1'b1) ? wire_ni1liO_o[2] : wire_ni1lii_o[2]; and(wire_ni1lOi_dataout, nliilli, ~(nliiO1i)); and(wire_ni1O_dataout, wire_nll0ii_dataout, rwa_6g_en); and(wire_ni1Oii_dataout, wire_ni1OlO_dataout, ~(nliiO1i)); and(wire_ni1Oil_dataout, wire_ni1OOi_dataout, ~(nliiO1i)); and(wire_ni1OiO_dataout, wire_ni1OOl_dataout, ~(nliiO1i)); and(wire_ni1Oli_dataout, wire_ni1OOO_dataout, ~(nliiO1i)); and(wire_ni1Oll_dataout, wire_ni011i_dataout, ~(nliiO1i)); assign wire_ni1OlO_dataout = (nliillO === 1'b1) ? wire_ni01il_o[0] : wire_ni011l_dataout; assign wire_ni1OOi_dataout = (nliillO === 1'b1) ? wire_ni01il_o[1] : wire_ni011O_dataout; assign wire_ni1OOl_dataout = (nliillO === 1'b1) ? wire_ni01il_o[2] : wire_ni010i_dataout; assign wire_ni1OOO_dataout = (nliillO === 1'b1) ? wire_ni01il_o[3] : wire_ni010l_dataout; and(wire_niii_dataout, wire_nll0ll_dataout, rwa_6g_en); assign wire_niii0i_dataout = (nlil0l === 1'b1) ? (~ nii0Oi) : wire_nil1Oi_dataout; assign wire_niii0l_dataout = (nlil0l === 1'b1) ? wire_niOlOi_dataout : wire_nil1Ol_dataout; assign wire_niii0O_dataout = (nlil0l === 1'b1) ? (~ nii0Oi) : wire_nil1OO_dataout; assign wire_niii1l_dataout = (nlil0l === 1'b1) ? wire_niOllO_dataout : wire_nil1ll_dataout; assign wire_niii1O_dataout = (nlil0l === 1'b1) ? (~ nii0Oi) : wire_nil1lO_dataout; assign wire_niiiii_dataout = (nlil0l === 1'b1) ? nii0Oi : wire_nil01i_dataout; assign wire_niiiil_dataout = (nlil0l === 1'b1) ? (~ nii0Oi) : wire_nil01l_dataout; assign wire_niiiiO_dataout = (nlil0l === 1'b1) ? nii0Oi : wire_nil01O_dataout; assign wire_niiili_dataout = (nlil0l === 1'b1) ? nii0Oi : wire_nil00i_dataout; assign wire_niiill_dataout = (nlil0l === 1'b1) ? nii0Oi : wire_nil00l_dataout; and(wire_niiilO_dataout, wire_nil00O_dataout, ~(nlil0l)); assign wire_niiiOi_dataout = (nlil0l === 1'b1) ? nii0li : wire_nil0ii_dataout; and(wire_niiiOl_dataout, wire_nil0il_dataout, ~(nlil0l)); assign wire_niiiOO_dataout = (nlil0l === 1'b1) ? nii0Oi : wire_nil0iO_dataout; and(wire_niil_dataout, wire_nll0lO_dataout, rwa_6g_en); assign wire_niil0i_dataout = (nlil0l === 1'b1) ? (~ nii0Oi) : wire_nil0Oi_dataout; assign wire_niil0l_dataout = (nlil0l === 1'b1) ? (~ nii0Oi) : wire_nil0Ol_dataout; assign wire_niil0O_dataout = (nlil0l === 1'b1) ? wire_niOlOi_dataout : wire_nil0OO_dataout; and(wire_niil1i_dataout, wire_nil0li_dataout, ~(nlil0l)); or(wire_niil1l_dataout, wire_nil0ll_dataout, nlil0l); assign wire_niil1O_dataout = (nlil0l === 1'b1) ? wire_niOllO_dataout : wire_nil0lO_dataout; assign wire_niilii_dataout = (nlil0l === 1'b1) ? (~ nii0Oi) : wire_nili1i_dataout; assign wire_niilil_dataout = (nlil0l === 1'b1) ? nii0Oi : wire_nili1l_dataout; assign wire_niiliO_dataout = (nlil0l === 1'b1) ? (~ nii0Oi) : wire_nili1O_dataout; assign wire_niilli_dataout = (nlil0l === 1'b1) ? nii0Oi : wire_nili0i_dataout; assign wire_niilll_dataout = (nlil0l === 1'b1) ? nii0Oi : wire_nili0l_dataout; assign wire_niillO_dataout = (nlil0l === 1'b1) ? nii0Oi : wire_nili0O_dataout; and(wire_niilOi_dataout, wire_niliii_dataout, ~(nlil0l)); and(wire_niilOl_dataout, wire_niliiO_dataout, ~(nlil0l)); and(wire_niilOO_dataout, wire_nilill_dataout, ~(nlil0l)); and(wire_niiO_dataout, wire_nll0Oi_dataout, rwa_6g_en); assign wire_niiO0i_dataout = (nlil10O === 1'b1) ? wire_nllOll_data_out2[2] : ni0lli; assign wire_niiO0l_dataout = (nlil10O === 1'b1) ? wire_nllOll_data_out2[3] : ni0lll; assign wire_niiO0O_dataout = (nlil10O === 1'b1) ? wire_nllOll_data_out2[4] : ni0llO; or(wire_niiO1i_dataout, wire_nililO_dataout, nlil0l); assign wire_niiO1l_dataout = (nlil10O === 1'b1) ? wire_nllOll_data_out2[0] : ni00Ol; assign wire_niiO1O_dataout = (nlil10O === 1'b1) ? wire_nllOll_data_out2[1] : ni0liO; assign wire_niiOi_dataout = (rwa_6g_en === 1'b1) ? wire_nliOOO_dataout : wire_nlOi1il_dataout; assign wire_niiOii_dataout = (nlil10O === 1'b1) ? wire_nllOll_data_out2[5] : ni0lOi; assign wire_niiOil_dataout = (nlil10O === 1'b1) ? wire_nllOll_data_out2[6] : ni0lOl; assign wire_niiOiO_dataout = (nlil10O === 1'b1) ? wire_nllOll_data_out2[7] : ni0lOO; assign wire_niiOl_dataout = (rwa_6g_en === 1'b1) ? wire_nll11i_dataout : wire_nlOi1ll_dataout; assign wire_niiOli_dataout = (nlil10O === 1'b1) ? wire_nllOll_data_out2[8] : ni0O1i; assign wire_niiOll_dataout = (nlil10O === 1'b1) ? wire_nllOll_data_out2[9] : ni0O1l; assign wire_niiOO_dataout = (rwa_6g_en === 1'b1) ? wire_nll11l_dataout : wire_nlOi1lO_dataout; assign wire_nil00i_dataout = (nlil10O === 1'b1) ? wire_nllOll_data_out1[8] : wire_nill0O_dataout; assign wire_nil00l_dataout = (nlil10O === 1'b1) ? wire_nllOll_data_out1[9] : wire_nillii_dataout; assign wire_nil00O_dataout = (nlil10O === 1'b1) ? wire_nllOll_data_out1[10] : wire_nillil_dataout; assign wire_nil01i_dataout = (nlil10O === 1'b1) ? wire_nllOll_data_out1[5] : wire_nill1O_dataout; assign wire_nil01l_dataout = (nlil10O === 1'b1) ? wire_nllOll_data_out1[6] : wire_nill0i_dataout; assign wire_nil01O_dataout = (nlil10O === 1'b1) ? wire_nllOll_data_out1[7] : wire_nill0l_dataout; assign wire_nil0i_dataout = (rwa_6g_en === 1'b1) ? wire_nll10O_dataout : wire_nlOi01i_dataout; assign wire_nil0ii_dataout = (nlil10O === 1'b1) ? wire_nllOll_data_out1[11] : wire_nilliO_dataout; assign wire_nil0il_dataout = (nlil10O === 1'b1) ? wire_nllOll_data_out1[12] : wire_nillli_dataout; assign wire_nil0iO_dataout = (nlil10O === 1'b1) ? wire_nllOll_data_out1[13] : wire_nillll_dataout; assign wire_nil0l_dataout = (rwa_6g_en === 1'b1) ? wire_nll1ii_dataout : wire_nlOi01l_dataout; and(wire_nil0li_dataout, wire_nllOll_data_out1[14], nlil10O); or(wire_nil0ll_dataout, wire_nllOll_data_out1[15], ~(nlil10O)); assign wire_nil0lO_dataout = (nlil10O === 1'b1) ? wire_nllOlO_data_out1[0] : wire_nilllO_dataout; assign wire_nil0O_dataout = (rwa_6g_en === 1'b1) ? wire_nll1il_dataout : wire_nlOi01O_dataout; assign wire_nil0Oi_dataout = (nlil10O === 1'b1) ? wire_nllOlO_data_out1[1] : wire_nillOi_dataout; assign wire_nil0Ol_dataout = (nlil10O === 1'b1) ? wire_nllOlO_data_out1[2] : wire_nillOl_dataout; assign wire_nil0OO_dataout = (nlil10O === 1'b1) ? wire_nllOlO_data_out1[3] : wire_nillOO_dataout; assign wire_nil10i_dataout = (nlil10O === 1'b1) ? wire_nllOlO_data_out2[3] : ni0O0O; assign wire_nil10l_dataout = (nlil10O === 1'b1) ? wire_nllOlO_data_out2[4] : ni0Oii; assign wire_nil10O_dataout = (nlil10O === 1'b1) ? wire_nllOlO_data_out2[5] : ni0Oil; assign wire_nil11i_dataout = (nlil10O === 1'b1) ? wire_nllOlO_data_out2[0] : ni0O1O; assign wire_nil11l_dataout = (nlil10O === 1'b1) ? wire_nllOlO_data_out2[1] : ni0O0i; assign wire_nil11O_dataout = (nlil10O === 1'b1) ? wire_nllOlO_data_out2[2] : ni0O0l; assign wire_nil1i_dataout = (rwa_6g_en === 1'b1) ? wire_nll11O_dataout : wire_nlOi1Oi_dataout; assign wire_nil1ii_dataout = (nlil10O === 1'b1) ? wire_nllOlO_data_out2[6] : ni0OiO; assign wire_nil1il_dataout = (nlil10O === 1'b1) ? wire_nllOlO_data_out2[7] : ni0Oli; assign wire_nil1iO_dataout = (nlil10O === 1'b1) ? wire_nllOlO_data_out2[8] : ni0Oll; assign wire_nil1l_dataout = (rwa_6g_en === 1'b1) ? wire_nll10i_dataout : wire_nlOi1Ol_dataout; assign wire_nil1li_dataout = (nlil10O === 1'b1) ? wire_nllOlO_data_out2[9] : ni0OlO; assign wire_nil1ll_dataout = (nlil10O === 1'b1) ? wire_nllOll_data_out1[0] : wire_niliOi_dataout; assign wire_nil1lO_dataout = (nlil10O === 1'b1) ? wire_nllOll_data_out1[1] : wire_niliOl_dataout; assign wire_nil1O_dataout = (rwa_6g_en === 1'b1) ? wire_nll10l_dataout : wire_nlOi1OO_dataout; assign wire_nil1Oi_dataout = (nlil10O === 1'b1) ? wire_nllOll_data_out1[2] : wire_niliOO_dataout; assign wire_nil1Ol_dataout = (nlil10O === 1'b1) ? wire_nllOll_data_out1[3] : wire_nill1i_dataout; assign wire_nil1OO_dataout = (nlil10O === 1'b1) ? wire_nllOll_data_out1[4] : wire_nill1l_dataout; and(wire_nili_dataout, wire_nll0Ol_dataout, rwa_6g_en); assign wire_nili0i_dataout = (nlil10O === 1'b1) ? wire_nllOlO_data_out1[7] : wire_nilO0i_dataout; assign wire_nili0l_dataout = (nlil10O === 1'b1) ? wire_nllOlO_data_out1[8] : wire_nilO0l_dataout; assign wire_nili0O_dataout = (nlil10O === 1'b1) ? wire_nllOlO_data_out1[9] : wire_nilO0O_dataout; assign wire_nili1i_dataout = (nlil10O === 1'b1) ? wire_nllOlO_data_out1[4] : wire_nilO1i_dataout; assign wire_nili1l_dataout = (nlil10O === 1'b1) ? wire_nllOlO_data_out1[5] : wire_nilO1l_dataout; assign wire_nili1O_dataout = (nlil10O === 1'b1) ? wire_nllOlO_data_out1[6] : wire_nilO1O_dataout; assign wire_nilii_dataout = (rwa_6g_en === 1'b1) ? wire_nll1iO_dataout : wire_nlOi00i_dataout; assign wire_niliii_dataout = (nlil10O === 1'b1) ? wire_nllOlO_data_out1[10] : wire_nilOii_dataout; assign wire_niliil_dataout = (nlil10O === 1'b1) ? wire_nllOlO_data_out1[11] : nii0li; assign wire_niliiO_dataout = (nlil10O === 1'b1) ? wire_nllOlO_data_out1[12] : wire_nilOil_dataout; assign wire_nilil_dataout = (rwa_6g_en === 1'b1) ? wire_nll1li_dataout : wire_nlOi00l_dataout; assign wire_nilili_dataout = (nlil10O === 1'b1) ? wire_nllOlO_data_out1[13] : nii0Oi; and(wire_nilill_dataout, wire_nllOlO_data_out1[14], nlil10O); or(wire_nililO_dataout, wire_nllOlO_data_out1[15], ~(nlil10O)); and(wire_niliO_dataout, wire_nll01l_dataout, rwa_6g_en); assign wire_niliOi_dataout = (nlil10l === 1'b1) ? ni0OOi : wire_nilOiO_dataout; assign wire_niliOl_dataout = (nlil10l === 1'b1) ? ni0OOl : wire_nilOli_dataout; assign wire_niliOO_dataout = (nlil10l === 1'b1) ? ni0OOO : wire_nilOll_dataout; and(wire_nill_dataout, wire_nll0OO_dataout, rwa_6g_en); assign wire_nill0i_dataout = (nlil10l === 1'b1) ? nii10i : wire_nilOOO_dataout; assign wire_nill0l_dataout = (nlil10l === 1'b1) ? nii10l : wire_niO11i_dataout; assign wire_nill0O_dataout = (nlil10l === 1'b1) ? nii10O : wire_niO11l_dataout; assign wire_nill1i_dataout = (nlil10l === 1'b1) ? nii11i : wire_nilOlO_dataout; assign wire_nill1l_dataout = (nlil10l === 1'b1) ? nii11l : wire_nilOOi_dataout; assign wire_nill1O_dataout = (nlil10l === 1'b1) ? nii11O : wire_nilOOl_dataout; and(wire_nilli_dataout, wire_nll01O_dataout, rwa_6g_en); assign wire_nillii_dataout = (nlil10l === 1'b1) ? nii1ii : wire_niO11O_dataout; and(wire_nillil_dataout, nii1il, nlil10l); assign wire_nilliO_dataout = (nlil10l === 1'b1) ? nii1iO : nii0li; and(wire_nilll_dataout, wire_nll00i_dataout, rwa_6g_en); and(wire_nillli_dataout, nii1li, nlil10l); assign wire_nillll_dataout = (nlil10l === 1'b1) ? nii1ll : nii0Oi; assign wire_nilllO_dataout = (nlil10l === 1'b1) ? nii1Ol : wire_niO0iO_dataout; and(wire_nillO_dataout, wire_nll00l_dataout, rwa_6g_en); assign wire_nillOi_dataout = (nlil10l === 1'b1) ? nii1OO : wire_niO0li_dataout; assign wire_nillOl_dataout = (nlil10l === 1'b1) ? nii01i : wire_niO0ll_dataout; assign wire_nillOO_dataout = (nlil10l === 1'b1) ? nii01l : wire_niO0lO_dataout; and(wire_nilO_dataout, wire_nlli1i_dataout, rwa_6g_en); assign wire_nilO0i_dataout = (nlil10l === 1'b1) ? nii00O : wire_niOi1i_dataout; assign wire_nilO0l_dataout = (nlil10l === 1'b1) ? nii0ii : wire_niOi1l_dataout; assign wire_nilO0O_dataout = (nlil10l === 1'b1) ? nii0il : wire_niOi1O_dataout; assign wire_nilO1i_dataout = (nlil10l === 1'b1) ? nii01O : wire_niO0Oi_dataout; assign wire_nilO1l_dataout = (nlil10l === 1'b1) ? nii00i : wire_niO0Ol_dataout; assign wire_nilO1O_dataout = (nlil10l === 1'b1) ? nii00l : wire_niO0OO_dataout; and(wire_nilOi_dataout, wire_nll00O_dataout, rwa_6g_en); and(wire_nilOii_dataout, nii0iO, nlil10l); and(wire_nilOil_dataout, nii0ll, nlil10l); assign wire_nilOiO_dataout = (nii0Oi === 1'b1) ? wire_niO1Ol_dataout : wire_niO10i_dataout; and(wire_nilOl_dataout, wire_nll0ii_dataout, rwa_6g_en); assign wire_nilOli_dataout = (nii0Oi === 1'b1) ? wire_niO1OO_dataout : wire_niO10l_dataout; assign wire_nilOll_dataout = (nii0Oi === 1'b1) ? wire_niO01i_dataout : wire_niO10O_dataout; assign wire_nilOlO_dataout = (nii0Oi === 1'b1) ? wire_niO01l_dataout : wire_niO1ii_dataout; and(wire_nilOO_dataout, wire_nll0il_dataout, rwa_6g_en); assign wire_nilOOi_dataout = (nii0Oi === 1'b1) ? wire_niO01O_dataout : wire_niO1il_dataout; assign wire_nilOOl_dataout = (nii0Oi === 1'b1) ? wire_niO00i_dataout : wire_niO1iO_dataout; assign wire_nilOOO_dataout = (nii0Oi === 1'b1) ? wire_niO00l_dataout : wire_niO1li_dataout; assign wire_niO_dataout = (rindv_rx === 1'b1) ? gen2ngen1 : gen2ngen1_bundle; or(wire_niO00i_dataout, rclkcmpsq1p[15], nlil11l); and(wire_niO00l_dataout, rclkcmpsq1p[16], ~(nlil11l)); or(wire_niO00O_dataout, rclkcmpsq1p[17], nlil11l); and(wire_niO01i_dataout, rclkcmpsq1p[12], ~(nlil11l)); assign wire_niO01l_dataout = (nlil11l === 1'b1) ? rclkcmpinsertpad : rclkcmpsq1p[13]; and(wire_niO01O_dataout, rclkcmpsq1p[14], ~(nlil11l)); assign wire_niO0i_dataout = (rwa_6g_en === 1'b1) ? nliO1l : wire_nlOiiOi_dataout; or(wire_niO0ii_dataout, rclkcmpsq1p[18], nlil11l); or(wire_niO0il_dataout, rclkcmpsq1p[19], nlil11l); assign wire_niO0iO_dataout = (nii0Oi === 1'b1) ? wire_niOiOl_dataout : wire_niOi0i_dataout; assign wire_niO0l_dataout = (rwa_6g_en === 1'b1) ? nlliiO : wire_nlOiiOl_dataout; assign wire_niO0li_dataout = (nii0Oi === 1'b1) ? wire_niOiOO_dataout : wire_niOi0l_dataout; assign wire_niO0ll_dataout = (nii0Oi === 1'b1) ? wire_niOl1i_dataout : wire_niOi0O_dataout; assign wire_niO0lO_dataout = (nii0Oi === 1'b1) ? wire_niOl1l_dataout : wire_niOiii_dataout; assign wire_niO0O_dataout = (rwa_6g_en === 1'b1) ? nllili : wire_nlOiiOO_dataout; assign wire_niO0Oi_dataout = (nii0Oi === 1'b1) ? wire_niOl1O_dataout : wire_niOiil_dataout; assign wire_niO0Ol_dataout = (nii0Oi === 1'b1) ? wire_niOl0i_dataout : wire_niOiiO_dataout; assign wire_niO0OO_dataout = (nii0Oi === 1'b1) ? wire_niOl0l_dataout : wire_niOili_dataout; assign wire_niO10i_dataout = (nlil11i === 1'b1) ? rclkcmpinsertpad : rclkcmpsq1n[10]; or(wire_niO10l_dataout, rclkcmpsq1n[11], nlil11i); or(wire_niO10O_dataout, rclkcmpsq1n[12], nlil11i); assign wire_niO11i_dataout = (nii0Oi === 1'b1) ? wire_niO00O_dataout : wire_niO1ll_dataout; assign wire_niO11l_dataout = (nii0Oi === 1'b1) ? wire_niO0ii_dataout : wire_niO1lO_dataout; assign wire_niO11O_dataout = (nii0Oi === 1'b1) ? wire_niO0il_dataout : wire_niO1Oi_dataout; and(wire_niO1i_dataout, wire_nll0iO_dataout, rwa_6g_en); assign wire_niO1ii_dataout = (nlil11i === 1'b1) ? (~ rclkcmpinsertpad) : rclkcmpsq1n[13]; or(wire_niO1il_dataout, rclkcmpsq1n[14], nlil11i); and(wire_niO1iO_dataout, rclkcmpsq1n[15], ~(nlil11i)); and(wire_niO1l_dataout, wire_nll0li_dataout, rwa_6g_en); or(wire_niO1li_dataout, rclkcmpsq1n[16], nlil11i); and(wire_niO1ll_dataout, rclkcmpsq1n[17], ~(nlil11i)); and(wire_niO1lO_dataout, rclkcmpsq1n[18], ~(nlil11i)); and(wire_niO1O_dataout, wire_nll0ll_dataout, rwa_6g_en); and(wire_niO1Oi_dataout, rclkcmpsq1n[19], ~(nlil11i)); assign wire_niO1Ol_dataout = (nlil11l === 1'b1) ? (~ rclkcmpinsertpad) : rclkcmpsq1p[10]; and(wire_niO1OO_dataout, rclkcmpsq1p[11], ~(nlil11l)); and(wire_niOi_dataout, wire_nlli1l_dataout, rwa_6g_en); assign wire_niOi0i_dataout = (nlil11O === 1'b1) ? rclkcmpinsertpad : rclkcmpsq1n[10]; or(wire_niOi0l_dataout, rclkcmpsq1n[11], nlil11O); or(wire_niOi0O_dataout, rclkcmpsq1n[12], nlil11O); assign wire_niOi1i_dataout = (nii0Oi === 1'b1) ? wire_niOl0O_dataout : wire_niOill_dataout; assign wire_niOi1l_dataout = (nii0Oi === 1'b1) ? wire_niOlii_dataout : wire_niOilO_dataout; assign wire_niOi1O_dataout = (nii0Oi === 1'b1) ? wire_niOlil_dataout : wire_niOiOi_dataout; assign wire_niOii_dataout = (rwa_6g_en === 1'b1) ? nllill : wire_nlOil1i_dataout; assign wire_niOiii_dataout = (nlil11O === 1'b1) ? (~ rclkcmpinsertpad) : rclkcmpsq1n[13]; or(wire_niOiil_dataout, rclkcmpsq1n[14], nlil11O); and(wire_niOiiO_dataout, rclkcmpsq1n[15], ~(nlil11O)); assign wire_niOil_dataout = (rwa_6g_en === 1'b1) ? nllilO : wire_nlOil1l_dataout; or(wire_niOili_dataout, rclkcmpsq1n[16], nlil11O); and(wire_niOill_dataout, rclkcmpsq1n[17], ~(nlil11O)); and(wire_niOilO_dataout, rclkcmpsq1n[18], ~(nlil11O)); assign wire_niOiO_dataout = (rwa_6g_en === 1'b1) ? nlliOi : wire_nlOil1O_dataout; and(wire_niOiOi_dataout, rclkcmpsq1n[19], ~(nlil11O)); assign wire_niOiOl_dataout = (nlil10i === 1'b1) ? (~ rclkcmpinsertpad) : rclkcmpsq1p[10]; and(wire_niOiOO_dataout, rclkcmpsq1p[11], ~(nlil10i)); assign wire_niOl_dataout = (rwa_6g_en === 1'b1) ? ni101l : nlO1OiO; or(wire_niOl0i_dataout, rclkcmpsq1p[15], nlil10i); and(wire_niOl0l_dataout, rclkcmpsq1p[16], ~(nlil10i)); or(wire_niOl0O_dataout, rclkcmpsq1p[17], nlil10i); and(wire_niOl1i_dataout, rclkcmpsq1p[12], ~(nlil10i)); assign wire_niOl1l_dataout = (nlil10i === 1'b1) ? rclkcmpinsertpad : rclkcmpsq1p[13]; and(wire_niOl1O_dataout, rclkcmpsq1p[14], ~(nlil10i)); assign wire_niOli_dataout = (rwa_6g_en === 1'b1) ? nlliOl : wire_nlOil0i_dataout; or(wire_niOlii_dataout, rclkcmpsq1p[18], nlil10i); or(wire_niOlil_dataout, rclkcmpsq1p[19], nlil10i); assign wire_niOll_dataout = (rwa_6g_en === 1'b1) ? nlliOO : wire_nlOil0l_dataout; assign wire_niOllO_dataout = (rclkcmpinsertpad === 1'b1) ? (~ nii0Oi) : nii0Oi; assign wire_niOlO_dataout = (rwa_6g_en === 1'b1) ? nlll1i : wire_nlOil0O_dataout; assign wire_niOlOi_dataout = (rclkcmpinsertpad === 1'b1) ? nii0Oi : (~ nii0Oi); assign wire_niOO_dataout = (rwa_6g_en === 1'b1) ? ni1i1l : nlO1OOi; assign wire_niOOi_dataout = (rwa_6g_en === 1'b1) ? nlll1l : wire_nlOilii_dataout; assign wire_niOOl_dataout = (rwa_6g_en === 1'b1) ? nlll1O : wire_nlO0Oli_dataout; assign wire_niOOO_dataout = (rwa_6g_en === 1'b1) ? nlll0i : wire_nlO0Oll_dataout; assign wire_nl000i_dataout = (nlil1ll === 1'b1) ? wire_nl0OlO_dataout : niOOii; assign wire_nl000l_dataout = (nlil1ll === 1'b1) ? nl11lO : niOOil; assign wire_nl000O_dataout = (nlil1ll === 1'b1) ? niOOil : niOOiO; assign wire_nl001i_dataout = (nlil1ll === 1'b1) ? wire_nl0OiO_dataout : niOO0i; assign wire_nl001l_dataout = (nlil1ll === 1'b1) ? wire_nl0Oli_dataout : niOO0l; assign wire_nl001O_dataout = (nlil1ll === 1'b1) ? wire_nl0Oll_dataout : niOO0O; and(wire_nl00i_dataout, (nlillOO | ni1O0O), rwa_6g_en); assign wire_nl00ii_dataout = (nlil1ll === 1'b1) ? niOOiO : niOOli; assign wire_nl00il_dataout = (nlil1ll === 1'b1) ? niOOli : niOOll; assign wire_nl00iO_dataout = (nlil1ll === 1'b1) ? niOOll : niOOlO; and(wire_nl00l_dataout, ni000i, rwa_6g_en); assign wire_nl00li_dataout = (nlil1ll === 1'b1) ? niOOlO : niOOOi; assign wire_nl00ll_dataout = (nlil1ll === 1'b1) ? niOOOi : niOOOl; assign wire_nl00lO_dataout = (nlil1ll === 1'b1) ? niOOOl : niOOOO; assign wire_nl00O_dataout = (rwa_6g_en === 1'b1) ? wire_nliOOi_dataout : wire_nlOi10l_dataout; assign wire_nl00Oi_dataout = (nlil1ll === 1'b1) ? niOOOO : nl111i; assign wire_nl00Ol_dataout = (nlil1ll === 1'b1) ? nl111i : nl111l; assign wire_nl00OO_dataout = (nlil1ll === 1'b1) ? nl111l : nl111O; and(wire_nl010i_dataout, wire_nl0liO_dataout, ~(nlil00l)); and(wire_nl010l_dataout, wire_nl0lli_dataout, ~(nlil00l)); and(wire_nl010O_dataout, wire_nl0lll_dataout, ~(nlil00l)); and(wire_nl011i_dataout, wire_nl0l0O_dataout, ~(nlil00l)); and(wire_nl011l_dataout, wire_nl0lii_dataout, ~(nlil00l)); and(wire_nl011O_dataout, wire_nl0lil_dataout, ~(nlil00l)); and(wire_nl01i_dataout, nllO1O, rwa_6g_en); and(wire_nl01ii_dataout, wire_nl0llO_dataout, ~(nlil00l)); and(wire_nl01il_dataout, wire_nl0lOi_dataout, ~(nlil00l)); and(wire_nl01iO_dataout, wire_nl0lOl_dataout, ~(nlil00l)); and(wire_nl01l_dataout, nllO0i, rwa_6g_en); assign wire_nl01li_dataout = (nlil1ll === 1'b1) ? nlil1ii : niii1i; assign wire_nl01ll_dataout = (nlil1ll === 1'b1) ? (((wire_nl0O1O_o[4] | wire_nl0O1O_o[3]) | wire_nl0O1O_o[2]) | wire_nl0O1O_o[1]) : niOlOl; assign wire_nl01lO_dataout = (nlil1ll === 1'b1) ? nlil1il : niOlOO; and(wire_nl01O_dataout, nllO0l, rwa_6g_en); assign wire_nl01Oi_dataout = (nlil1ll === 1'b1) ? nlil1iO : niOO1i; assign wire_nl01Ol_dataout = (nlil1ll === 1'b1) ? (((wire_nl0Oii_o[18] | wire_nl0Oii_o[17]) | wire_nl0Oii_o[16]) | wire_nl0Oii_o[15]) : niOO1l; assign wire_nl01OO_dataout = (nlil1ll === 1'b1) ? wire_nl0Oil_dataout : niOO1O; and(wire_nl0i_dataout, nO, ~(scan_mode)); assign wire_nl0i0i_dataout = (nlil1ll === 1'b1) ? nl110O : nl11ii; assign wire_nl0i0l_dataout = (nlil1ll === 1'b1) ? nl11ii : nl11il; assign wire_nl0i0O_dataout = (nlil1ll === 1'b1) ? nl11il : nl11iO; assign wire_nl0i1i_dataout = (nlil1ll === 1'b1) ? nl111O : nl110i; assign wire_nl0i1l_dataout = (nlil1ll === 1'b1) ? nl110i : nl110l; assign wire_nl0i1O_dataout = (nlil1ll === 1'b1) ? nl110l : nl110O; assign wire_nl0ii_dataout = (rwa_6g_en === 1'b1) ? (rmatchen & (~ rgenericfifo)) : (((~ rgenericfifo) & ((((~ dskwclksel[1]) & rmatchen) | nlilO0l) | (~ (nlilO1O18 ^ nlilO1O17)))) & (nlilO1i20 ^ nlilO1i19)); assign wire_nl0iii_dataout = (nlil1ll === 1'b1) ? nl11iO : nl11li; assign wire_nl0iil_dataout = (nlil1ll === 1'b1) ? nl11li : nl11ll; assign wire_nl0iiO_dataout = (nlil1ll === 1'b1) ? nl11ll : nl11lO; assign wire_nl0il_dataout = (rwa_6g_en === 1'b1) ? n0l0iO : nlllO0l; assign wire_nl0ili_dataout = (nlil1ll === 1'b1) ? nl1i1O : nl11Ol; assign wire_nl0ill_dataout = (nlil1ll === 1'b1) ? nl11Ol : nl11OO; assign wire_nl0ilO_dataout = (nlil1ll === 1'b1) ? nl11OO : nl101i; assign wire_nl0iO_dataout = (rwa_6g_en === 1'b1) ? n0l0li : nlllO0O; assign wire_nl0iOi_dataout = (nlil1ll === 1'b1) ? nl101i : nl101l; assign wire_nl0iOl_dataout = (nlil1ll === 1'b1) ? nl101l : nl101O; assign wire_nl0iOO_dataout = (nlil1ll === 1'b1) ? nl101O : nl100i; assign wire_nl0l0i_dataout = (nlil1ll === 1'b1) ? nl10ii : nl10il; assign wire_nl0l0l_dataout = (nlil1ll === 1'b1) ? nl10il : nl10iO; assign wire_nl0l0O_dataout = (nlil1ll === 1'b1) ? nl10iO : nl10li; assign wire_nl0l1i_dataout = (nlil1ll === 1'b1) ? nl100i : nl100l; assign wire_nl0l1l_dataout = (nlil1ll === 1'b1) ? nl100l : nl100O; assign wire_nl0l1O_dataout = (nlil1ll === 1'b1) ? nl100O : nl10ii; assign wire_nl0li_dataout = (rwa_6g_en === 1'b1) ? n0l0ll : nlllOii; assign wire_nl0lii_dataout = (nlil1ll === 1'b1) ? nl10li : nl10ll; assign wire_nl0lil_dataout = (nlil1ll === 1'b1) ? nl10ll : nl10lO; assign wire_nl0liO_dataout = (nlil1ll === 1'b1) ? nl10lO : nl10Oi; assign wire_nl0ll_dataout = (rwa_6g_en === 1'b1) ? n0l0lO : nlllOil; assign wire_nl0lli_dataout = (nlil1ll === 1'b1) ? nl10Oi : nl10Ol; assign wire_nl0lll_dataout = (nlil1ll === 1'b1) ? nl10Ol : nl10OO; assign wire_nl0llO_dataout = (nlil1ll === 1'b1) ? nl10OO : nl1i1i; assign wire_nl0lO_dataout = (rwa_6g_en === 1'b1) ? n0l0Oi : nlllOiO; assign wire_nl0lOi_dataout = (nlil1ll === 1'b1) ? nl1i1i : nl1i1l; assign wire_nl0lOl_dataout = (nlil1ll === 1'b1) ? nl1i1l : nl1i1O; assign wire_nl0Oi_dataout = (rwa_6g_en === 1'b1) ? n0l0Ol : nlllOli; and(wire_nl0Oil_dataout, wire_nl0OOi_o[0], ~(nlil1li)); and(wire_nl0OiO_dataout, wire_nl0OOi_o[1], ~(nlil1li)); assign wire_nl0Ol_dataout = (rwa_6g_en === 1'b1) ? n0l0OO : nlllOll; and(wire_nl0Oli_dataout, wire_nl0OOi_o[2], ~(nlil1li)); and(wire_nl0Oll_dataout, wire_nl0OOi_o[3], ~(nlil1li)); and(wire_nl0OlO_dataout, wire_nl0OOi_o[4], ~(nlil1li)); assign wire_nl0OO_dataout = (rwa_6g_en === 1'b1) ? n0li1i : nlllOlO; assign wire_nl10i_dataout = (rwa_6g_en === 1'b1) ? ni000i : nlllliO; and(wire_nl10l_dataout, nlllii, rwa_6g_en); and(wire_nl10O_dataout, nlllil, rwa_6g_en); assign wire_nl11i_dataout = (rwa_6g_en === 1'b1) ? nlll0l : wire_nlO0OlO_dataout; assign wire_nl11l_dataout = (rwa_6g_en === 1'b1) ? nlll0O : wire_nlOiliO_dataout; assign wire_nl11O_dataout = (rwa_6g_en === 1'b1) ? ((nlillOO | ni1O0O) | (~ (nlilliO24 ^ nlilliO23))) : (((nllllii | nlillOl) | nlillOi) | (~ (nlillll22 ^ nlillll21))); assign wire_nl1i_dataout = (rwa_6g_en === 1'b1) ? ni1i1O : nlO1OOl; and(wire_nl1i0l_dataout, wire_nl01li_dataout, ~(nlil00l)); and(wire_nl1i0O_dataout, wire_nl01ll_dataout, ~(nlil00l)); and(wire_nl1ii_dataout, nllliO, rwa_6g_en); and(wire_nl1iii_dataout, wire_nl01lO_dataout, ~(nlil00l)); and(wire_nl1iil_dataout, wire_nl01Oi_dataout, ~(nlil00l)); and(wire_nl1iiO_dataout, wire_nl01Ol_dataout, ~(nlil00l)); and(wire_nl1il_dataout, nlllli, rwa_6g_en); and(wire_nl1ili_dataout, wire_nl01OO_dataout, ~(nlil00l)); and(wire_nl1ill_dataout, wire_nl001i_dataout, ~(nlil00l)); and(wire_nl1ilO_dataout, wire_nl001l_dataout, ~(nlil00l)); and(wire_nl1iO_dataout, nlllll, rwa_6g_en); and(wire_nl1iOi_dataout, wire_nl001O_dataout, ~(nlil00l)); and(wire_nl1iOl_dataout, wire_nl000i_dataout, ~(nlil00l)); and(wire_nl1iOO_dataout, wire_nl000l_dataout, ~(nlil00l)); assign wire_nl1l_dataout = (rwa_6g_en === 1'b1) ? ni1i0i : nlO1OOO; and(wire_nl1l0i_dataout, wire_nl00iO_dataout, ~(nlil00l)); and(wire_nl1l0l_dataout, wire_nl00li_dataout, ~(nlil00l)); and(wire_nl1l0O_dataout, wire_nl00ll_dataout, ~(nlil00l)); or(wire_nl1l1i_dataout, wire_nl000O_dataout, nlil00l); and(wire_nl1l1l_dataout, wire_nl00ii_dataout, ~(nlil00l)); and(wire_nl1l1O_dataout, wire_nl00il_dataout, ~(nlil00l)); and(wire_nl1li_dataout, nllllO, rwa_6g_en); and(wire_nl1lii_dataout, wire_nl00lO_dataout, ~(nlil00l)); and(wire_nl1lil_dataout, wire_nl00Oi_dataout, ~(nlil00l)); and(wire_nl1liO_dataout, wire_nl00Ol_dataout, ~(nlil00l)); and(wire_nl1ll_dataout, nlllOi, rwa_6g_en); and(wire_nl1lli_dataout, wire_nl00OO_dataout, ~(nlil00l)); and(wire_nl1lll_dataout, wire_nl0i1i_dataout, ~(nlil00l)); and(wire_nl1llO_dataout, wire_nl0i1l_dataout, ~(nlil00l)); and(wire_nl1lO_dataout, nlllOl, rwa_6g_en); and(wire_nl1lOi_dataout, wire_nl0i1O_dataout, ~(nlil00l)); and(wire_nl1lOl_dataout, wire_nl0i0i_dataout, ~(nlil00l)); and(wire_nl1lOO_dataout, wire_nl0i0l_dataout, ~(nlil00l)); assign wire_nl1O_dataout = (rwa_6g_en === 1'b1) ? ni1i0l : nlO011i; and(wire_nl1O0i_dataout, wire_nl0iiO_dataout, ~(nlil00l)); or(wire_nl1O0l_dataout, wire_nl0ili_dataout, nlil00l); and(wire_nl1O0O_dataout, wire_nl0ill_dataout, ~(nlil00l)); and(wire_nl1O1i_dataout, wire_nl0i0O_dataout, ~(nlil00l)); and(wire_nl1O1l_dataout, wire_nl0iii_dataout, ~(nlil00l)); and(wire_nl1O1O_dataout, wire_nl0iil_dataout, ~(nlil00l)); and(wire_nl1Oi_dataout, nlllOO, rwa_6g_en); and(wire_nl1Oii_dataout, wire_nl0ilO_dataout, ~(nlil00l)); and(wire_nl1Oil_dataout, wire_nl0iOi_dataout, ~(nlil00l)); and(wire_nl1OiO_dataout, wire_nl0iOl_dataout, ~(nlil00l)); and(wire_nl1Ol_dataout, nllO1i, rwa_6g_en); and(wire_nl1Oli_dataout, wire_nl0iOO_dataout, ~(nlil00l)); and(wire_nl1Oll_dataout, wire_nl0l1i_dataout, ~(nlil00l)); and(wire_nl1OlO_dataout, wire_nl0l1l_dataout, ~(nlil00l)); and(wire_nl1OO_dataout, nllO1l, rwa_6g_en); and(wire_nl1OOi_dataout, wire_nl0l1O_dataout, ~(nlil00l)); and(wire_nl1OOl_dataout, wire_nl0l0i_dataout, ~(nlil00l)); and(wire_nl1OOO_dataout, wire_nl0l0l_dataout, ~(nlil00l)); assign wire_nli_dataout = (rwa_6g_en === 1'b1) ? wire_nliiOO_dataout : wire_n1100O_dataout; and(wire_nli00i_dataout, nli1OO, ~(nlil00l)); and(wire_nli00l_dataout, n0l00i, ~(nlil00l)); and(wire_nli00O_dataout, n0l01O, ~(nlil00l)); and(wire_nli01O_dataout, nli01l, ~(nlil00l)); assign wire_nli0i_dataout = (rwa_6g_en === 1'b1) ? n0li0l : nllO11i; and(wire_nli0ii_dataout, n0l01l, ~(nlil00l)); and(wire_nli0iO_dataout, n0OiOO, ~(nlil00l)); assign wire_nli0l_dataout = (rwa_6g_en === 1'b1) ? n0li0O : nllO11l; and(wire_nli0li_dataout, n0Ol1l, ~(nlil00l)); and(wire_nli0ll_dataout, n0Ol1O, ~(nlil00l)); and(wire_nli0lO_dataout, n0Ol0i, ~(nlil00l)); assign wire_nli0O_dataout = (rwa_6g_en === 1'b1) ? n0liii : nllO11O; and(wire_nli0Oi_dataout, n0Ol0l, ~(nlil00l)); assign wire_nli1i_dataout = (rwa_6g_en === 1'b1) ? n0li1l : nlllOOi; assign wire_nli1l_dataout = (rwa_6g_en === 1'b1) ? n0li1O : nlllOOl; assign wire_nli1O_dataout = (rwa_6g_en === 1'b1) ? n0li0i : nlllOOO; assign wire_nliii_dataout = (rwa_6g_en === 1'b1) ? n0liil : nllO10i; and(wire_nliiii_dataout, (((~ rgenericfifo) & nlii0O) | nlil01O), ~(nlil00l)); and(wire_nliiil_dataout, nlii0l, ~(nlil00l)); and(wire_nliiiO_dataout, nllOOi, ~(nlil00l)); assign wire_nliil_dataout = (rwa_6g_en === 1'b1) ? n0liiO : nllO10l; assign wire_nliiO_dataout = (rwa_6g_en === 1'b1) ? n0lili : nllO10O; assign wire_nliiOO_dataout = (nlilOiO === 1'b1) ? (nlil00i | nliiOi) : nlil00i; and(wire_nlil_dataout, nlli, ~(scan_mode)); assign wire_nlili_dataout = (rwa_6g_en === 1'b1) ? n0lill : nllO1ii; and(wire_nlilii_dataout, n0111i, ~(nlil00l)); and(wire_nlilil_dataout, ((nlii0O & n0111i) & (~ nlil0i)), ~(nlil00l)); assign wire_nlill_dataout = (rwa_6g_en === 1'b1) ? n0lilO : nllO1il; assign wire_nlilO_dataout = (rwa_6g_en === 1'b1) ? n0liOi : nllO1iO; and(wire_nlilOO_dataout, (nlil0il | nlil0ii), wire_nliOlO_dataout); and(wire_nliO00l_dataout, nliO01O, ~((~ nli0OlO))); and(wire_nliO00O_dataout, nliO00i, ~((~ nli0OlO))); and(wire_nliO0i_dataout, nlil0iO, wire_nliOlO_dataout); and(wire_nliO0ii_dataout, wire_n11iii_o, (rgenericfifo | wire_nlOi10l_dataout)); assign wire_nliO0l_dataout = ((((~ nlilOl) & nlil0O) & (~ nliliii)) === 1'b1) ? ((nlil0Oi | nlil0lO) | (~ (nlil0li48 ^ nlil0li47))) : wire_nliO0O_dataout; or(wire_nliO0O_dataout, (rtruebac2bac & (((~ nliliil) & nliliii) & (nlili0l44 ^ nlili0l43))), ((nlili0i | nlili1O) & ((nlili1l | nlili1i) | (~ (nlil0Ol46 ^ nlil0Ol45))))); and(wire_nliO1O_dataout, wire_nliO0l_dataout, wire_nliOlO_dataout); assign wire_nliOi_dataout = (rwa_6g_en === 1'b1) ? niOOil : n100il; assign wire_nliOl_dataout = (rwa_6g_en === 1'b1) ? niOOiO : n100iO; and(wire_nliOlO_dataout, nli0OO, ~(nliliiO)); assign wire_nliOO_dataout = (rwa_6g_en === 1'b1) ? niOOli : n100li; and(wire_nliOOi_dataout, sync_status, ~(nliliiO)); assign wire_nliOOO_dataout = (nlilili === 1'b1) ? nlii1l : sync_status; assign wire_nll_dataout = (rwa_6g_en === 1'b1) ? ni11Ol : nllil1l; assign wire_nll00i_dataout = (nlilili === 1'b1) ? nii01i : sudi[16]; assign wire_nll00l_dataout = (nlilili === 1'b1) ? nii01l : sudi[17]; assign wire_nll00O_dataout = (nlilili === 1'b1) ? nii01O : sudi[18]; and(wire_nll01i_dataout, nii1Oi, nlilili); assign wire_nll01l_dataout = (nlilili === 1'b1) ? nii1Ol : sudi[14]; assign wire_nll01O_dataout = (nlilili === 1'b1) ? nii1OO : sudi[15]; assign wire_nll0i_dataout = (rwa_6g_en === 1'b1) ? niOOOl : n100Ol; assign wire_nll0ii_dataout = (nlilili === 1'b1) ? nii00i : sudi[19]; assign wire_nll0il_dataout = (nlilili === 1'b1) ? nii00l : sudi[20]; assign wire_nll0iO_dataout = (nlilili === 1'b1) ? nii00O : sudi[21]; assign wire_nll0l_dataout = (rwa_6g_en === 1'b1) ? niOOOO : n100OO; assign wire_nll0li_dataout = (nlilili === 1'b1) ? nii0ii : sudi[22]; assign wire_nll0ll_dataout = (nlilili === 1'b1) ? nii0il : sudi[23]; assign wire_nll0lO_dataout = (nlilili === 1'b1) ? nii0iO : sudi[24]; assign wire_nll0O_dataout = (rwa_6g_en === 1'b1) ? nl111i : n10i1i; assign wire_nll0Oi_dataout = (nlilili === 1'b1) ? nii0li : sudi[25]; assign wire_nll0Ol_dataout = (nlilili === 1'b1) ? nii0ll : sudi[26]; assign wire_nll0OO_dataout = (nlilili === 1'b1) ? nii0Oi : sudi[27]; assign wire_nll10i_dataout = (nlilili === 1'b1) ? nii11i : sudi[3]; assign wire_nll10l_dataout = (nlilili === 1'b1) ? nii11l : sudi[4]; assign wire_nll10O_dataout = (nlilili === 1'b1) ? nii11O : sudi[5]; assign wire_nll11i_dataout = (nlilili === 1'b1) ? ni0OOi : sudi[0]; assign wire_nll11l_dataout = (nlilili === 1'b1) ? ni0OOl : sudi[1]; assign wire_nll11O_dataout = (nlilili === 1'b1) ? ni0OOO : sudi[2]; assign wire_nll1i_dataout = (rwa_6g_en === 1'b1) ? niOOll : n100ll; assign wire_nll1ii_dataout = (nlilili === 1'b1) ? nii10i : sudi[6]; assign wire_nll1il_dataout = (nlilili === 1'b1) ? nii10l : sudi[7]; assign wire_nll1iO_dataout = (nlilili === 1'b1) ? nii10O : sudi[8]; assign wire_nll1l_dataout = (rwa_6g_en === 1'b1) ? niOOlO : n100lO; assign wire_nll1li_dataout = (nlilili === 1'b1) ? nii1ii : sudi[9]; assign wire_nll1ll_dataout = (nlilili === 1'b1) ? nii1il : sudi[10]; assign wire_nll1lO_dataout = (nlilili === 1'b1) ? nii1iO : sudi[11]; assign wire_nll1O_dataout = (rwa_6g_en === 1'b1) ? niOOOi : n100Oi; assign wire_nll1Oi_dataout = (nlilili === 1'b1) ? nii1li : sudi[12]; assign wire_nll1Ol_dataout = (nlilili === 1'b1) ? nii1ll : sudi[13]; and(wire_nll1OO_dataout, nii1lO, nlilili); and(wire_nlli01i_dataout, nli0i1i, ~(nli0lii)); assign wire_nlli0li_dataout = (nliO11i === 1'b1) ? (nli0i1l | nlli1ll) : nli0i1l; and(wire_nlli1i_dataout, nii0Ol, nlilili); and(wire_nlli1l_dataout, nii0OO, nlilili); and(wire_nlli1lO_dataout, nli00lO, ~(nli0lii)); and(wire_nlli1Oi_dataout, nli00Oi, ~(nli0lii)); and(wire_nlli1Ol_dataout, nli00Ol, ~(nli0lii)); and(wire_nlli1OO_dataout, nli00OO, ~(nli0lii)); assign wire_nllii_dataout = (rwa_6g_en === 1'b1) ? nl111l : n10i1l; and(wire_nllii0i_dataout, nli0l0l, ~(nli0lii)); and(wire_nlliili_dataout, nlO1OiO, ~(nli0lii)); and(wire_nlliill_dataout, nlO1OOi, ~(nli0lii)); and(wire_nlliilO_dataout, nlO1OOl, ~(nli0lii)); and(wire_nlliiOi_dataout, nlO1OOO, ~(nli0lii)); and(wire_nlliiOl_dataout, nlO011i, ~(nli0lii)); assign wire_nllil_dataout = (rwa_6g_en === 1'b1) ? nl111O : n10i1O; and(wire_nllil0O_dataout, nllil1O, ~(nli0lii)); or(wire_nllilii_dataout, nllil1i, nli0lii); or(wire_nllilil_dataout, wire_n1OlOi_o, nli0lii); or(wire_nlliliO_dataout, wire_nllillO_dataout, nli0lii); and(wire_nllilli_dataout, wire_n1OllO_o, ~(nli0lii)); and(wire_nllilll_dataout, wire_nllilOO_dataout, ~(nli0lii)); assign wire_nllillO_dataout = (nliO11i === 1'b1) ? (nli0i0i | nlliiOO) : nli0i0i; assign wire_nllilOO_dataout = (nliO11i === 1'b1) ? (nli0i0l | nlliiiO) : nli0i0l; assign wire_nlliO_dataout = (rwa_6g_en === 1'b1) ? nl110i : n10i0i; assign wire_nlll00i_dataout = (nli0ili === 1'b1) ? wire_nllll1i_o[2] : wire_nlll0iO_dataout; assign wire_nlll00l_dataout = (nli0ili === 1'b1) ? wire_nllll1i_o[3] : wire_nlll0li_dataout; assign wire_nlll00O_dataout = (nli0ili === 1'b1) ? wire_nllll1i_o[4] : wire_nlll0ll_dataout; and(wire_nlll01i_dataout, wire_nlll00O_dataout, ~(nli0lii)); assign wire_nlll01l_dataout = (nli0ili === 1'b1) ? wire_nllll1i_o[0] : wire_nlll0ii_dataout; assign wire_nlll01O_dataout = (nli0ili === 1'b1) ? wire_nllll1i_o[1] : wire_nlll0il_dataout; assign wire_nlll0ii_dataout = (nli0iiO === 1'b1) ? nlll10l : wire_nlll0lO_dataout; assign wire_nlll0il_dataout = (nli0iiO === 1'b1) ? wire_nllliOl_o[0] : wire_nlll0Oi_dataout; assign wire_nlll0iO_dataout = (nli0iiO === 1'b1) ? wire_nllliOl_o[1] : wire_nlll0Ol_dataout; assign wire_nlll0li_dataout = (nli0iiO === 1'b1) ? wire_nllliOl_o[2] : wire_nlll0OO_dataout; assign wire_nlll0ll_dataout = (nli0iiO === 1'b1) ? wire_nllliOl_o[3] : wire_nllli1i_dataout; assign wire_nlll0lO_dataout = (nli0iil === 1'b1) ? wire_nllliil_o[0] : wire_nllli1l_dataout; assign wire_nlll0Oi_dataout = (nli0iil === 1'b1) ? wire_nllliil_o[1] : wire_nllli1O_dataout; assign wire_nlll0Ol_dataout = (nli0iil === 1'b1) ? wire_nllliil_o[2] : wire_nllli0i_dataout; assign wire_nlll0OO_dataout = (nli0iil === 1'b1) ? wire_nllliil_o[3] : wire_nllli0l_dataout; and(wire_nlll1ll_dataout, nlillOl, ~(nli0lii)); and(wire_nlll1lO_dataout, wire_nlll01l_dataout, ~(nli0lii)); and(wire_nlll1Oi_dataout, wire_nlll01O_dataout, ~(nli0lii)); and(wire_nlll1Ol_dataout, wire_nlll00i_dataout, ~(nli0lii)); and(wire_nlll1OO_dataout, wire_nlll00l_dataout, ~(nli0lii)); assign wire_nllli_dataout = (rwa_6g_en === 1'b1) ? nl110l : n10i0l; assign wire_nllli0i_dataout = ((~ nli0iii) === 1'b1) ? wire_nllliii_o[3] : nlll1ii; assign wire_nllli0l_dataout = ((~ nli0iii) === 1'b1) ? wire_nllliii_o[4] : nlll1il; assign wire_nllli0O_dataout = ((~ nli0iii) === 1'b1) ? wire_nllliii_o[5] : nlll1iO; assign wire_nllli1i_dataout = (nli0iil === 1'b1) ? wire_nllliil_o[4] : wire_nllli0O_dataout; assign wire_nllli1l_dataout = ((~ nli0iii) === 1'b1) ? wire_nllliii_o[1] : nlll10l; assign wire_nllli1O_dataout = ((~ nli0iii) === 1'b1) ? wire_nllliii_o[2] : nlll10O; assign wire_nllll_dataout = (rwa_6g_en === 1'b1) ? nl110O : n10i0O; and(wire_nllllll_dataout, nli0ilO, ~(nli0lii)); and(wire_nlllllO_dataout, nli0ilO, ~(nli0lii)); assign wire_nlllO_dataout = (rwa_6g_en === 1'b1) ? nl11ii : n10iii; and(wire_nllO_dataout, cmpfifourst, rcmpfifourst); and(wire_nllO00i_dataout, wire_nllOiOl_dataout, ~(nli0lii)); and(wire_nllO00l_dataout, wire_nllOiOO_dataout, ~(nli0lii)); and(wire_nllO00O_dataout, wire_nllOl1i_dataout, ~(nli0lii)); or(wire_nllO01i_dataout, wire_nllOill_dataout, nli0lii); and(wire_nllO01l_dataout, wire_nllOilO_dataout, ~(nli0lii)); and(wire_nllO01O_dataout, wire_nllOiOi_dataout, ~(nli0lii)); and(wire_nllO0ii_dataout, wire_nllOl1l_dataout, ~(nli0lii)); and(wire_nllO0il_dataout, wire_nllOl1O_dataout, ~(nli0lii)); and(wire_nllO0iO_dataout, wire_nllOl0i_dataout, ~(nli0lii)); and(wire_nllO0li_dataout, wire_nllOl0l_dataout, ~(nli0lii)); and(wire_nllO0ll_dataout, wire_nllOl0O_dataout, ~(nli0lii)); and(wire_nllO0lO_dataout, wire_nllOlii_dataout, ~(nli0lii)); and(wire_nllO0Oi_dataout, wire_nllOlil_dataout, ~(nli0lii)); and(wire_nllO0Ol_dataout, wire_nllOliO_dataout, ~(nli0lii)); and(wire_nllO0OO_dataout, wire_nllOlli_dataout, ~(nli0lii)); and(wire_nllO1ll_dataout, wire_nllOi0O_dataout, ~(nli0lii)); and(wire_nllO1lO_dataout, wire_nllOiii_dataout, ~(nli0lii)); and(wire_nllO1Oi_dataout, wire_nllOiil_dataout, ~(nli0lii)); and(wire_nllO1Ol_dataout, wire_nllOiiO_dataout, ~(nli0lii)); and(wire_nllO1OO_dataout, wire_nllOili_dataout, ~(nli0lii)); assign wire_nllOi_dataout = (rwa_6g_en === 1'b1) ? nl11il : n10iil; and(wire_nllOi0i_dataout, wire_nllOlOl_dataout, ~(nli0lii)); and(wire_nllOi0l_dataout, wire_nllOlOO_dataout, ~(nli0lii)); assign wire_nllOi0O_dataout = (nli0iOi === 1'b1) ? wire_nlO100i_dataout : wire_nllOO1i_dataout; and(wire_nllOi1i_dataout, wire_nllOlll_dataout, ~(nli0lii)); and(wire_nllOi1l_dataout, wire_nllOllO_dataout, ~(nli0lii)); and(wire_nllOi1O_dataout, wire_nllOlOi_dataout, ~(nli0lii)); assign wire_nllOiii_dataout = (nli0iOi === 1'b1) ? wire_nlO100l_dataout : wire_nllOO1l_dataout; assign wire_nllOiil_dataout = (nli0iOi === 1'b1) ? wire_nlO100O_dataout : wire_nllOO1O_dataout; assign wire_nllOiiO_dataout = (nli0iOi === 1'b1) ? wire_nlO10ii_dataout : wire_nllOO0i_dataout; assign wire_nllOili_dataout = (nli0iOi === 1'b1) ? wire_nlO10il_dataout : wire_nllOO0l_dataout; assign wire_nllOill_dataout = (nli0iOi === 1'b1) ? nllO1iO : wire_nllOO0O_dataout; assign wire_nllOilO_dataout = (nli0iOi === 1'b1) ? nlllO0l : wire_nllOOii_dataout; assign wire_nllOiOi_dataout = (nli0iOi === 1'b1) ? nlllO0O : wire_nllOOil_dataout; assign wire_nllOiOl_dataout = (nli0iOi === 1'b1) ? nlllOii : wire_nllOOiO_dataout; assign wire_nllOiOO_dataout = (nli0iOi === 1'b1) ? nlllOil : wire_nllOOli_dataout; assign wire_nllOl_dataout = (rwa_6g_en === 1'b1) ? nl11iO : n10iiO; assign wire_nllOl0i_dataout = (nli0iOi === 1'b1) ? nlllOlO : wire_nllOOOl_dataout; assign wire_nllOl0l_dataout = (nli0iOi === 1'b1) ? nlllOOi : wire_nllOOOO_dataout; assign wire_nllOl0O_dataout = (nli0iOi === 1'b1) ? nlllOOl : wire_nlO111i_dataout; assign wire_nllOl1i_dataout = (nli0iOi === 1'b1) ? nlllOiO : wire_nllOOll_dataout; assign wire_nllOl1l_dataout = (nli0iOi === 1'b1) ? nlllOli : wire_nllOOlO_dataout; assign wire_nllOl1O_dataout = (nli0iOi === 1'b1) ? nlllOll : wire_nllOOOi_dataout; assign wire_nllOlii_dataout = (nli0iOi === 1'b1) ? nlllOOO : wire_nlO111l_dataout; assign wire_nllOlil_dataout = (nli0iOi === 1'b1) ? nllO11i : wire_nlO111O_dataout; assign wire_nllOliO_dataout = (nli0iOi === 1'b1) ? nllO11l : wire_nlO110i_dataout; assign wire_nllOlli_dataout = (nli0iOi === 1'b1) ? nllO11O : wire_nlO110l_dataout; assign wire_nllOlll_dataout = (nli0iOi === 1'b1) ? nllO10i : wire_nlO110O_dataout; assign wire_nllOllO_dataout = (nli0iOi === 1'b1) ? nllO10l : wire_nlO11ii_dataout; assign wire_nllOlOi_dataout = (nli0iOi === 1'b1) ? nllO10O : wire_nlO11il_dataout; assign wire_nllOlOl_dataout = (nli0iOi === 1'b1) ? nllO1ii : wire_nlO11iO_dataout; assign wire_nllOlOO_dataout = (nli0iOi === 1'b1) ? nllO1il : wire_nlO11li_dataout; assign wire_nllOO_dataout = (rwa_6g_en === 1'b1) ? nl11li : n10ili; assign wire_nllOO0i_dataout = (nli0iOO === 1'b1) ? wire_nlO11Ol_dataout : nlllO1O; assign wire_nllOO0l_dataout = (nli0iOO === 1'b1) ? wire_nlO11OO_dataout : nlllO0i; assign wire_nllOO0O_dataout = (nli0iOO === 1'b1) ? nlllO0O : nlllO0l; assign wire_nllOO1i_dataout = (nli0iOO === 1'b1) ? wire_nlO11ll_dataout : nllllli; assign wire_nllOO1l_dataout = (nli0iOO === 1'b1) ? wire_nlO11lO_dataout : nlllO1i; assign wire_nllOO1O_dataout = (nli0iOO === 1'b1) ? wire_nlO11Oi_dataout : nlllO1l; assign wire_nllOOii_dataout = (nli0iOO === 1'b1) ? nlllOii : nlllO0O; assign wire_nllOOil_dataout = (nli0iOO === 1'b1) ? nlllOil : nlllOii; assign wire_nllOOiO_dataout = (nli0iOO === 1'b1) ? nlllOiO : nlllOil; assign wire_nllOOli_dataout = (nli0iOO === 1'b1) ? nlllOli : nlllOiO; assign wire_nllOOll_dataout = (nli0iOO === 1'b1) ? nlllOll : nlllOli; assign wire_nllOOlO_dataout = (nli0iOO === 1'b1) ? nlllOlO : nlllOll; assign wire_nllOOOi_dataout = (nli0iOO === 1'b1) ? nlllOOi : nlllOlO; assign wire_nllOOOl_dataout = (nli0iOO === 1'b1) ? nlllOOl : nlllOOi; assign wire_nllOOOO_dataout = (nli0iOO === 1'b1) ? nlllOOO : nlllOOl; assign wire_nlO_dataout = (rwa_6g_en === 1'b1) ? wire_n0OOii_dataout : wire_nlli0li_dataout; assign wire_nlO001i_dataout = (wire_nlO000O_o === 1'b1) ? wire_nlO000l_o[4] : wire_nlO001O_o[4]; assign wire_nlO001l_dataout = (wire_nlO000O_o === 1'b1) ? wire_nlO000l_o[5] : wire_nlO001O_o[5]; and(wire_nlO00il_dataout, (nli0lOl | nli0lOi), (wire_nlOi10l_dataout & nliii0i)); and(wire_nlO010i_dataout, wire_nlO01iO_dataout, ~(nli0lii)); and(wire_nlO010l_dataout, wire_nlO01li_dataout, ~(nli0lii)); and(wire_nlO010O_dataout, wire_nlO01ll_dataout, ~(nli0lii)); and(wire_nlO011O_dataout, wire_nlO01il_dataout, ~(nli0lii)); and(wire_nlO01ii_dataout, wire_nlO01lO_dataout, ~(nli0lii)); and(wire_nlO01il_dataout, wire_nlO01Oi_dataout, ~(nli0lil)); and(wire_nlO01iO_dataout, wire_nlO01Ol_dataout, ~(nli0lil)); assign wire_nlO01li_dataout = (nli0lil === 1'b1) ? nlO1Oii : wire_nlO01OO_dataout; and(wire_nlO01ll_dataout, wire_nlO001i_dataout, ~(nli0lil)); assign wire_nlO01lO_dataout = (nli0lil === 1'b1) ? nlO1Oii : wire_nlO001l_dataout; assign wire_nlO01Oi_dataout = (wire_nlO000O_o === 1'b1) ? wire_nlO000l_o[1] : wire_nlO001O_o[1]; assign wire_nlO01Ol_dataout = (wire_nlO000O_o === 1'b1) ? wire_nlO000l_o[2] : wire_nlO001O_o[2]; assign wire_nlO01OO_dataout = (wire_nlO000O_o === 1'b1) ? wire_nlO000l_o[3] : wire_nlO001O_o[3]; assign wire_nlO0i_dataout = (rwa_6g_en === 1'b1) ? nl11OO : n10iOl; and(wire_nlO0i0l_dataout, nli0lOO, (wire_nlOi10l_dataout & nlO00Oi)); and(wire_nlO0i1i_dataout, nli0lOO, (wire_nlOi10l_dataout & nlO00ll)); and(wire_nlO0i1O_dataout, nli0lOO, (wire_nlOi10l_dataout & nlO00lO)); and(wire_nlO0iiO_dataout, nlii0OO, (wire_nlOi10l_dataout & (((~ rclkcmpsqmd) & nlillil) | nlO00ii))); assign wire_nlO0l_dataout = (rwa_6g_en === 1'b1) ? nl101i : n10iOO; and(wire_nlO0l1O_dataout, nlii0OO, (wire_nlOi10l_dataout & (nli0O1i | (~ nliii0i)))); assign wire_nlO0lOi_dataout = (dskwclksel[1] === 1'b1) ? audi_pre[0] : sudi_pre[0]; assign wire_nlO0lOl_dataout = (dskwclksel[1] === 1'b1) ? audi_pre[1] : sudi_pre[1]; assign wire_nlO0lOO_dataout = (dskwclksel[1] === 1'b1) ? audi_pre[2] : sudi_pre[2]; assign wire_nlO0O_dataout = (rwa_6g_en === 1'b1) ? nl101l : n10l1i; assign wire_nlO0O0i_dataout = (dskwclksel[1] === 1'b1) ? audi_pre[6] : sudi_pre[6]; assign wire_nlO0O0l_dataout = (dskwclksel[1] === 1'b1) ? audi_pre[7] : sudi_pre[7]; assign wire_nlO0O0O_dataout = (dskwclksel[1] === 1'b1) ? audi_pre[8] : sudi_pre[8]; assign wire_nlO0O1i_dataout = (dskwclksel[1] === 1'b1) ? audi_pre[3] : sudi_pre[3]; assign wire_nlO0O1l_dataout = (dskwclksel[1] === 1'b1) ? audi_pre[4] : sudi_pre[4]; assign wire_nlO0O1O_dataout = (dskwclksel[1] === 1'b1) ? audi_pre[5] : sudi_pre[5]; assign wire_nlO0Oii_dataout = (dskwclksel[1] === 1'b1) ? audi_pre[9] : sudi_pre[9]; assign wire_nlO0Oil_dataout = (dskwclksel[1] === 1'b1) ? audi_pre[10] : sudi_pre[10]; assign wire_nlO0OiO_dataout = (dskwclksel[1] === 1'b1) ? audi_pre[12] : sudi_pre[12]; assign wire_nlO0Oli_dataout = (dskwclksel[1] === 1'b1) ? audi[10] : sudi[10]; assign wire_nlO0Oll_dataout = (dskwclksel[1] === 1'b1) ? audi[11] : (sudi[11] & inferred_rxvalid); assign wire_nlO0OlO_dataout = (dskwclksel[1] === 1'b1) ? audi[12] : sudi[12]; and(wire_nlO100i_dataout, wire_nlO10iO_o[0], ~(nli0l1l)); and(wire_nlO100l_dataout, wire_nlO10iO_o[1], ~(nli0l1l)); and(wire_nlO100O_dataout, wire_nlO10iO_o[2], ~(nli0l1l)); and(wire_nlO10i_dataout, wire_n1ll_dataout, ~((~ wire_nl00O_dataout))); and(wire_nlO10ii_dataout, wire_nlO10iO_o[3], ~(nli0l1l)); and(wire_nlO10il_dataout, wire_nlO10iO_o[4], ~(nli0l1l)); and(wire_nlO10l_dataout, wire_nlO1ii_dataout, ~((~ wire_nl00O_dataout))); and(wire_nlO10O_dataout, wire_nlO1il_dataout, ~((~ wire_nl00O_dataout))); assign wire_nlO110i_dataout = (nli0iOO === 1'b1) ? nllO10i : nllO11O; assign wire_nlO110l_dataout = (nli0iOO === 1'b1) ? nllO10l : nllO10i; assign wire_nlO110O_dataout = (nli0iOO === 1'b1) ? nllO10O : nllO10l; assign wire_nlO111i_dataout = (nli0iOO === 1'b1) ? nllO11i : nlllOOO; assign wire_nlO111l_dataout = (nli0iOO === 1'b1) ? nllO11l : nllO11i; assign wire_nlO111O_dataout = (nli0iOO === 1'b1) ? nllO11O : nllO11l; assign wire_nlO11ii_dataout = (nli0iOO === 1'b1) ? nllO1ii : nllO10O; assign wire_nlO11il_dataout = (nli0iOO === 1'b1) ? nllO1il : nllO1ii; assign wire_nlO11iO_dataout = (nli0iOO === 1'b1) ? nllO1iO : nllO1il; assign wire_nlO11li_dataout = (nli0iOO === 1'b1) ? nlllO0l : nllO1iO; or(wire_nlO11ll_dataout, wire_nlO101i_o[1], nli0iOl); or(wire_nlO11lO_dataout, wire_nlO101i_o[2], nli0iOl); and(wire_nlO11Oi_dataout, wire_nlO101i_o[3], ~(nli0iOl)); and(wire_nlO11Ol_dataout, wire_nlO101i_o[4], ~(nli0iOl)); or(wire_nlO11OO_dataout, wire_nlO101i_o[5], nli0iOl); assign wire_nlO1i_dataout = (rwa_6g_en === 1'b1) ? nl11ll : n10ill; and(wire_nlO1i0i_dataout, nlli10l, ~(nli0lii)); and(wire_nlO1i0l_dataout, nlli10i, ~(nli0lii)); and(wire_nlO1i1i_dataout, nlO10OO, ~(nli0lii)); and(wire_nlO1i1l_dataout, nlO10Ol, ~(nli0lii)); and(wire_nlO1i1O_dataout, nlli10O, ~(nli0lii)); and(wire_nlO1ii_dataout, nllOOi, ~(wire_n1ll_dataout)); and(wire_nlO1iii_dataout, n11O0O, ~(nli0lii)); and(wire_nlO1iil_dataout, n101Ol, ~(nli0lii)); and(wire_nlO1iiO_dataout, n101OO, ~(nli0lii)); and(wire_nlO1il_dataout, nlO01O, ~(wire_n1ll_dataout)); and(wire_nlO1ili_dataout, n1001i, ~(nli0lii)); and(wire_nlO1ill_dataout, n1001l, ~(nli0lii)); assign wire_nlO1iO_dataout = ((~ wire_nl00O_dataout) === 1'b1) ? nlO01O : wire_nlO1lO_dataout; assign wire_nlO1l_dataout = (rwa_6g_en === 1'b1) ? nl11lO : n10ilO; assign wire_nlO1li_dataout = ((~ wire_nl00O_dataout) === 1'b1) ? nllOOi : wire_nlO1Oi_dataout; and(wire_nlO1ll_dataout, (~ nlill0O), ~((~ wire_nl00O_dataout))); assign wire_nlO1lO_dataout = (nlill0O === 1'b1) ? wire_n1iO_dataout : nlO01O; assign wire_nlO1O_dataout = (rwa_6g_en === 1'b1) ? nl11Ol : n10iOi; assign wire_nlO1Oi_dataout = (nlill0O === 1'b1) ? wire_n1li_dataout : nllOOi; and(wire_nlO1Oil_dataout, nlillOi, wire_nlOi10l_dataout); and(wire_nlO1Oli_dataout, wire_nlO1Oll_dataout, wire_nlOi10l_dataout); or(wire_nlO1Oll_dataout, nlO1Oii, ((~ nlO1Oii) & nli0l0O)); and(wire_nlO1OO_dataout, wire_n1il_dataout, wire_nl00O_dataout); assign wire_nlOi00i_dataout = (nli0Oli === 1'b1) ? nlOliil : wire_nlOii0l_dataout; assign wire_nlOi00l_dataout = (nli0Oli === 1'b1) ? nlOliiO : wire_nlOii0O_dataout; assign wire_nlOi00O_dataout = (nli0Oli === 1'b1) ? nlOlili : wire_nlOiiii_dataout; assign wire_nlOi01i_dataout = (nli0Oli === 1'b1) ? nlOli0l : wire_nlOii1l_dataout; assign wire_nlOi01l_dataout = (nli0Oli === 1'b1) ? nlOli0O : wire_nlOii1O_dataout; assign wire_nlOi01O_dataout = (nli0Oli === 1'b1) ? nlOliii : wire_nlOii0i_dataout; assign wire_nlOi0ii_dataout = (nli0Oli === 1'b1) ? nlOlill : wire_nlOiiil_dataout; assign wire_nlOi0il_dataout = (nli0Oli === 1'b1) ? nlOlilO : wire_nlOiiiO_dataout; assign wire_nlOi0iO_dataout = (nli0Oli === 1'b1) ? nlOliOl : wire_nlOiili_dataout; and(wire_nlOi0li_dataout, wire_nlOiill_dataout, ~(nli0Oli)); or(wire_nlOi0ll_dataout, wire_nlOiilO_dataout, nli0Oli); assign wire_nlOi0lO_dataout = (nli0O0l === 1'b1) ? nlOl0OO : wire_nlOiiOi_dataout; assign wire_nlOi0Oi_dataout = (nli0O0l === 1'b1) ? nlOli1i : wire_nlOiiOl_dataout; assign wire_nlOi0Ol_dataout = (nli0O0l === 1'b1) ? nlOli1l : wire_nlOiiOO_dataout; assign wire_nlOi0OO_dataout = (nli0O0l === 1'b1) ? nlOli1O : wire_nlOil1i_dataout; assign wire_nlOi10i_dataout = (dskwclksel[1] === 1'b1) ? nlOiO0O : nlOiO0i; and(wire_nlOi10l_dataout, wire_nlOi10O_dataout, ~(nli0O0i)); assign wire_nlOi10O_dataout = (dskwclksel[1] === 1'b1) ? align_status : sync_status; and(wire_nlOi11i_dataout, wire_nlOi11l_dataout, ~(nli0O0i)); assign wire_nlOi11l_dataout = (nlii1ii === 1'b1) ? align_status_sync_0 : wire_nlOi11O_dataout; assign wire_nlOi11O_dataout = (nlii10O === 1'b1) ? align_status_sync_2 : wire_nlOi10i_dataout; assign wire_nlOi1il_dataout = (nli0O0l === 1'b1) ? n10O1O : wire_nlOi10O_dataout; and(wire_nlOi1li_dataout, nli0Oli, wire_nlOi11i_dataout); assign wire_nlOi1ll_dataout = (nli0Oli === 1'b1) ? nlOl0OO : wire_nlOi0lO_dataout; assign wire_nlOi1lO_dataout = (nli0Oli === 1'b1) ? nlOli1i : wire_nlOi0Oi_dataout; assign wire_nlOi1Oi_dataout = (nli0Oli === 1'b1) ? nlOli1l : wire_nlOi0Ol_dataout; assign wire_nlOi1Ol_dataout = (nli0Oli === 1'b1) ? nlOli1O : wire_nlOi0OO_dataout; assign wire_nlOi1OO_dataout = (nli0Oli === 1'b1) ? nlOli0i : wire_nlOii1i_dataout; assign wire_nlOii_dataout = (rwa_6g_en === 1'b1) ? nl101O : n10l1l; assign wire_nlOii0i_dataout = (nli0O0l === 1'b1) ? nlOliii : wire_nlOil0l_dataout; assign wire_nlOii0l_dataout = (nli0O0l === 1'b1) ? nlOliil : wire_nlOil0O_dataout; assign wire_nlOii0O_dataout = (nli0O0l === 1'b1) ? nlOliiO : wire_nlOilii_dataout; assign wire_nlOii1i_dataout = (nli0O0l === 1'b1) ? nlOli0i : wire_nlOil1l_dataout; assign wire_nlOii1l_dataout = (nli0O0l === 1'b1) ? nlOli0l : wire_nlOil1O_dataout; assign wire_nlOii1O_dataout = (nli0O0l === 1'b1) ? nlOli0O : wire_nlOil0i_dataout; assign wire_nlOiiii_dataout = (nli0O0l === 1'b1) ? nlOlili : wire_nlO0Oli_dataout; assign wire_nlOiiil_dataout = (nli0O0l === 1'b1) ? nlOlill : wire_nlOilil_dataout; assign wire_nlOiiiO_dataout = (nli0O0l === 1'b1) ? nlOlilO : wire_nlO0OlO_dataout; assign wire_nlOiili_dataout = (nli0O0l === 1'b1) ? nlOliOl : wire_nlOiliO_dataout; and(wire_nlOiill_dataout, nlOliOO, nli0O0l); and(wire_nlOiilO_dataout, nlOll1i, nli0O0l); assign wire_nlOiiOi_dataout = (dskwclksel[1] === 1'b1) ? audi[0] : sudi[0]; assign wire_nlOiiOl_dataout = (dskwclksel[1] === 1'b1) ? audi[1] : sudi[1]; assign wire_nlOiiOO_dataout = (dskwclksel[1] === 1'b1) ? audi[2] : sudi[2]; assign wire_nlOil_dataout = (rwa_6g_en === 1'b1) ? nl100i : n10l1O; assign wire_nlOil0i_dataout = (dskwclksel[1] === 1'b1) ? audi[6] : sudi[6]; assign wire_nlOil0l_dataout = (dskwclksel[1] === 1'b1) ? audi[7] : sudi[7]; assign wire_nlOil0O_dataout = (dskwclksel[1] === 1'b1) ? audi[8] : sudi[8]; assign wire_nlOil1i_dataout = (dskwclksel[1] === 1'b1) ? audi[3] : sudi[3]; assign wire_nlOil1l_dataout = (dskwclksel[1] === 1'b1) ? audi[4] : sudi[4]; assign wire_nlOil1O_dataout = (dskwclksel[1] === 1'b1) ? audi[5] : sudi[5]; assign wire_nlOilii_dataout = (dskwclksel[1] === 1'b1) ? audi[9] : sudi[9]; assign wire_nlOilil_dataout = (dskwclksel[1] === 1'b1) ? audi[11] : sudi[11]; assign wire_nlOiliO_dataout = (dskwclksel[1] === 1'b1) ? audi[13] : sudi[13]; assign wire_nlOiO_dataout = (rwa_6g_en === 1'b1) ? nl100l : n10l0i; assign wire_nlOli_dataout = (rwa_6g_en === 1'b1) ? nl100O : n10l0l; assign wire_nlOll_dataout = (rwa_6g_en === 1'b1) ? nl10ii : n10l0O; assign wire_nlOll0i_dataout = (nlii1Oi === 1'b1) ? (~ nlOliOl) : wire_nlOO0iO_dataout; assign wire_nlOll0l_dataout = (nlii1Oi === 1'b1) ? (~ nlOliOl) : wire_nlOO0li_dataout; assign wire_nlOll0O_dataout = (nlii1Oi === 1'b1) ? wire_n1100l_dataout : wire_nlOO0ll_dataout; assign wire_nlOll1O_dataout = (nlii1Oi === 1'b1) ? wire_n1100i_dataout : wire_nlOO0il_dataout; assign wire_nlOllii_dataout = (nlii1Oi === 1'b1) ? (~ nlOliOl) : wire_nlOO0lO_dataout; assign wire_nlOllil_dataout = (nlii1Oi === 1'b1) ? nlOliOl : wire_nlOO0Oi_dataout; assign wire_nlOlliO_dataout = (nlii1Oi === 1'b1) ? (~ nlOliOl) : wire_nlOO0Ol_dataout; assign wire_nlOllli_dataout = (nlii1Oi === 1'b1) ? nlOliOl : wire_nlOO0OO_dataout; assign wire_nlOllll_dataout = (nlii1Oi === 1'b1) ? nlOliOl : wire_nlOOi1i_dataout; assign wire_nlOlllO_dataout = (nlii1Oi === 1'b1) ? nlOliOl : wire_nlOOi1l_dataout; and(wire_nlOllOi_dataout, wire_nlOOi1O_dataout, ~(nlii1Oi)); and(wire_nlOllOl_dataout, wire_nlOOi0l_dataout, ~(nlii1Oi)); and(wire_nlOllOO_dataout, wire_nlOOiii_dataout, ~(nlii1Oi)); assign wire_nlOlO_dataout = (rwa_6g_en === 1'b1) ? nl10il : n10lii; assign wire_nlOlO0i_dataout = (nli0Oil === 1'b1) ? wire_nllOll_data_out2[2] : nlOl00l; assign wire_nlOlO0l_dataout = (nli0Oil === 1'b1) ? wire_nllOll_data_out2[3] : nlOl00O; assign wire_nlOlO0O_dataout = (nli0Oil === 1'b1) ? wire_nllOll_data_out2[4] : nlOl0ii; or(wire_nlOlO1i_dataout, wire_nlOOiil_dataout, nlii1Oi); assign wire_nlOlO1l_dataout = (nli0Oil === 1'b1) ? wire_nllOll_data_out2[0] : nlOl01O; assign wire_nlOlO1O_dataout = (nli0Oil === 1'b1) ? wire_nllOll_data_out2[1] : nlOl00i; assign wire_nlOlOii_dataout = (nli0Oil === 1'b1) ? wire_nllOll_data_out2[5] : nlOl0il; assign wire_nlOlOil_dataout = (nli0Oil === 1'b1) ? wire_nllOll_data_out2[6] : nlOl0iO; assign wire_nlOlOiO_dataout = (nli0Oil === 1'b1) ? wire_nllOll_data_out2[7] : nlOl0li; assign wire_nlOlOli_dataout = (nli0Oil === 1'b1) ? wire_nllOll_data_out2[8] : nlOl0ll; assign wire_nlOlOll_dataout = (nli0Oil === 1'b1) ? wire_nllOll_data_out2[9] : nlOl0lO; assign wire_nlOlOlO_dataout = (nli0Oil === 1'b1) ? wire_nllOll_data_out2[11] : nlOl0Oi; assign wire_nlOlOOi_dataout = (nli0Oil === 1'b1) ? wire_nllOll_data_out2[13] : nlOl0Ol; assign wire_nlOlOOl_dataout = (nli0Oil === 1'b1) ? nlOl10O : nlOiOil; assign wire_nlOlOOO_dataout = (nli0Oil === 1'b1) ? nlOl1ii : nlOiOli; assign wire_nlOO00i_dataout = (nli0Oil === 1'b1) ? nlOl0ll : nlOl1Ol; assign wire_nlOO00l_dataout = (nli0Oil === 1'b1) ? nlOl0lO : nlOl1OO; assign wire_nlOO00O_dataout = (nli0Oil === 1'b1) ? nlOl0Oi : nlOl01i; assign wire_nlOO01i_dataout = (nli0Oil === 1'b1) ? nlOl0il : nlOl1ll; assign wire_nlOO01l_dataout = (nli0Oil === 1'b1) ? nlOl0iO : nlOl1lO; assign wire_nlOO01O_dataout = (nli0Oil === 1'b1) ? nlOl0li : nlOl1Oi; assign wire_nlOO0ii_dataout = (nli0Oil === 1'b1) ? nlOl0Ol : nlOl01l; assign wire_nlOO0il_dataout = (nli0Oil === 1'b1) ? wire_nllOll_data_out1[0] : wire_nlOOiiO_dataout; assign wire_nlOO0iO_dataout = (nli0Oil === 1'b1) ? wire_nllOll_data_out1[1] : wire_nlOOili_dataout; assign wire_nlOO0li_dataout = (nli0Oil === 1'b1) ? wire_nllOll_data_out1[2] : wire_nlOOill_dataout; assign wire_nlOO0ll_dataout = (nli0Oil === 1'b1) ? wire_nllOll_data_out1[3] : wire_nlOOilO_dataout; assign wire_nlOO0lO_dataout = (nli0Oil === 1'b1) ? wire_nllOll_data_out1[4] : wire_nlOOiOi_dataout; assign wire_nlOO0Oi_dataout = (nli0Oil === 1'b1) ? wire_nllOll_data_out1[5] : wire_nlOOiOl_dataout; assign wire_nlOO0Ol_dataout = (nli0Oil === 1'b1) ? wire_nllOll_data_out1[6] : wire_nlOOiOO_dataout; assign wire_nlOO0OO_dataout = (nli0Oil === 1'b1) ? wire_nllOll_data_out1[7] : wire_nlOOl1i_dataout; assign wire_nlOO10i_dataout = (nli0Oil === 1'b1) ? nlOl1ll : nlOiOOl; assign wire_nlOO10l_dataout = (nli0Oil === 1'b1) ? nlOl1lO : nlOiOOO; assign wire_nlOO10O_dataout = (nli0Oil === 1'b1) ? nlOl1Oi : nlOl11i; assign wire_nlOO11i_dataout = (nli0Oil === 1'b1) ? nlOl1il : nlOiOll; assign wire_nlOO11l_dataout = (nli0Oil === 1'b1) ? nlOl1iO : nlOiOlO; assign wire_nlOO11O_dataout = (nli0Oil === 1'b1) ? nlOl1li : nlOiOOi; assign wire_nlOO1ii_dataout = (nli0Oil === 1'b1) ? nlOl1Ol : nlOl11l; assign wire_nlOO1il_dataout = (nli0Oil === 1'b1) ? nlOl1OO : nlOl11O; assign wire_nlOO1iO_dataout = (nli0Oil === 1'b1) ? nlOl01i : nlOl10i; assign wire_nlOO1li_dataout = (nli0Oil === 1'b1) ? nlOl01l : nlOl10l; assign wire_nlOO1ll_dataout = (nli0Oil === 1'b1) ? nlOl01O : nlOl10O; assign wire_nlOO1lO_dataout = (nli0Oil === 1'b1) ? nlOl00i : nlOl1ii; assign wire_nlOO1Oi_dataout = (nli0Oil === 1'b1) ? nlOl00l : nlOl1il; assign wire_nlOO1Ol_dataout = (nli0Oil === 1'b1) ? nlOl00O : nlOl1iO; assign wire_nlOO1OO_dataout = (nli0Oil === 1'b1) ? nlOl0ii : nlOl1li; assign wire_nlOOi_dataout = (rwa_6g_en === 1'b1) ? nl10iO : n10lil; assign wire_nlOOi0i_dataout = (nli0Oil === 1'b1) ? wire_nllOll_data_out1[11] : wire_nlOOl0l_dataout; assign wire_nlOOi0l_dataout = (nli0Oil === 1'b1) ? wire_nllOll_data_out1[12] : wire_nlOOl0O_dataout; assign wire_nlOOi0O_dataout = (nli0Oil === 1'b1) ? wire_nllOll_data_out1[13] : wire_nlOOlii_dataout; assign wire_nlOOi1i_dataout = (nli0Oil === 1'b1) ? wire_nllOll_data_out1[8] : wire_nlOOl1l_dataout; assign wire_nlOOi1l_dataout = (nli0Oil === 1'b1) ? wire_nllOll_data_out1[9] : wire_nlOOl1O_dataout; assign wire_nlOOi1O_dataout = (nli0Oil === 1'b1) ? wire_nllOll_data_out1[10] : wire_nlOOl0i_dataout; assign wire_nlOOiii_dataout = (nli0Oil === 1'b1) ? wire_nllOll_data_out1[14] : wire_nlOOlil_dataout; assign wire_nlOOiil_dataout = (nli0Oil === 1'b1) ? wire_nllOll_data_out1[15] : wire_nlOOliO_dataout; assign wire_nlOOiiO_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlOOlOO_dataout : nlOl0OO; assign wire_nlOOili_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlOOO1i_dataout : nlOli1i; assign wire_nlOOill_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlOOO1l_dataout : nlOli1l; assign wire_nlOOilO_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlOOO1O_dataout : nlOli1O; assign wire_nlOOiOi_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlOOO0i_dataout : nlOli0i; assign wire_nlOOiOl_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlOOO0l_dataout : nlOli0l; assign wire_nlOOiOO_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlOOO0O_dataout : nlOli0O; assign wire_nlOOl_dataout = (rwa_6g_en === 1'b1) ? nl10li : n10liO; assign wire_nlOOl0i_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlOOOli_dataout : wire_nlOOlli_dataout; assign wire_nlOOl0l_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlOOOll_dataout : nlOlill; assign wire_nlOOl0O_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlOOOlO_dataout : wire_nlOOlll_dataout; assign wire_nlOOl1i_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlOOOii_dataout : nlOliii; assign wire_nlOOl1l_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlOOOil_dataout : nlOliil; assign wire_nlOOl1O_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlOOOiO_dataout : nlOliiO; assign wire_nlOOlii_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlOOOOi_dataout : nlOliOl; and(wire_nlOOlil_dataout, wire_nlOOOOl_dataout, rclkcmpsqmd); assign wire_nlOOliO_dataout = (rclkcmpsqmd === 1'b1) ? wire_nlOOOOO_dataout : (~ rrx_pipe_enable); and(wire_nlOOlli_dataout, wire_nlOOllO_dataout, ~(rrx_pipe_enable)); and(wire_nlOOlll_dataout, wire_nlOOlOi_dataout, ~(rrx_pipe_enable)); and(wire_nlOOllO_dataout, nlOlili, nli0Oii); and(wire_nlOOlOi_dataout, nlOlilO, nli0Oii); assign wire_nlOOlOO_dataout = (n11O1l === 1'b1) ? nlOl10O : wire_n1111i_dataout; assign wire_nlOOO_dataout = (rwa_6g_en === 1'b1) ? nl10ll : n10lli; assign wire_nlOOO0i_dataout = (n11O1l === 1'b1) ? nlOl1li : wire_n1110l_dataout; assign wire_nlOOO0l_dataout = (n11O1l === 1'b1) ? nlOl1ll : wire_n1110O_dataout; assign wire_nlOOO0O_dataout = (n11O1l === 1'b1) ? nlOl1lO : wire_n111ii_dataout; assign wire_nlOOO1i_dataout = (n11O1l === 1'b1) ? nlOl1ii : wire_n1111l_dataout; assign wire_nlOOO1l_dataout = (n11O1l === 1'b1) ? nlOl1il : wire_n1111O_dataout; assign wire_nlOOO1O_dataout = (n11O1l === 1'b1) ? nlOl1iO : wire_n1110i_dataout; assign wire_nlOOOii_dataout = (n11O1l === 1'b1) ? nlOl1Oi : wire_n111il_dataout; assign wire_nlOOOil_dataout = (n11O1l === 1'b1) ? nlOl1Ol : wire_n111iO_dataout; assign wire_nlOOOiO_dataout = (n11O1l === 1'b1) ? nlOl1OO : wire_n111li_dataout; and(wire_nlOOOli_dataout, wire_n111ll_dataout, ~(n11O1l)); assign wire_nlOOOll_dataout = (n11O1l === 1'b1) ? nlOl01i : wire_n111lO_dataout; and(wire_nlOOOlO_dataout, wire_n111Oi_dataout, ~(n11O1l)); assign wire_nlOOOOi_dataout = (n11O1l === 1'b1) ? nlOl01l : wire_n111Ol_dataout; and(wire_nlOOOOl_dataout, wire_n111OO_dataout, ~(n11O1l)); or(wire_nlOOOOO_dataout, wire_n1101i_dataout, n11O1l); oper_add n0O0li ( .a({n0l0il, n0l0ii, n0l00O, n0l00l, n0O0ll}), .b({{4{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_n0O0li_o)); defparam n0O0li.sgate_representation = 0, n0O0li.width_a = 5, n0O0li.width_b = 5, n0O0li.width_o = 5; oper_add n0OOOO ( .a({1'b0, rfull_threshold[4:0], 1'b1}), .b({1'b0, {4{1'b1}}, 1'b0, 1'b1}), .cin(1'b0), .cout(), .o(wire_n0OOOO_o)); defparam n0OOOO.sgate_representation = 0, n0OOOO.width_a = 7, n0OOOO.width_b = 7, n0OOOO.width_o = 7; oper_add n1010i ( .a({n11O0l, n11O0i, n11O1O}), .b({{2{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_n1010i_o)); defparam n1010i.sgate_representation = 0, n1010i.width_a = 3, n1010i.width_b = 3, n1010i.width_o = 3; oper_add n1l0lO ( .a({n100ii, n1000O, n1000l, n1000i, n1001O}), .b({{4{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_n1l0lO_o)); defparam n1l0lO.sgate_representation = 0, n1l0lO.width_a = 5, n1l0lO.width_b = 5, n1l0lO.width_o = 5; oper_add n1O1OO ( .a({1'b0, rins_threshold[4:0], 1'b1}), .b({1'b0, {4{1'b1}}, 1'b0, 1'b1}), .cin(1'b0), .cout(), .o(wire_n1O1OO_o)); defparam n1O1OO.sgate_representation = 0, n1O1OO.width_a = 7, n1O1OO.width_b = 7, n1O1OO.width_o = 7; oper_add ni01ii ( .a({ni1O0l, ni1O0i, ni1O1O, ni1O1l, ni1llO, 1'b1}), .b({{4{1'b1}}, 1'b0, 1'b1}), .cin(1'b0), .cout(), .o(wire_ni01ii_o)); defparam ni01ii.sgate_representation = 0, ni01ii.width_a = 6, ni01ii.width_b = 6, ni01ii.width_o = 6; oper_add ni01il ( .a({ni1O0l, ni1O0i, ni1O1O, ni1O1l, ni1llO}), .b({{4{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_ni01il_o)); defparam ni01il.sgate_representation = 0, ni01il.width_a = 5, ni01il.width_b = 5, ni01il.width_o = 5; oper_add ni1lii ( .a({(~ wire_ni1lil_o[5]), (~ wire_ni1lil_o[4]), (~ wire_ni1lil_o[3]), (~ wire_ni1lil_o[2]), (~ wire_ni1lil_o[1]), 1'b1}), .b({1'b1, 1'b0, 1'b1, {2{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_ni1lii_o)); defparam ni1lii.sgate_representation = 0, ni1lii.width_a = 6, ni1lii.width_b = 6, ni1lii.width_o = 6; oper_add ni1lil ( .a({n0O0OO, nliil0O, nliilii, nliilil, nliiliO, 1'b1}), .b({(~ n0l0il), (~ n0l0ii), (~ n0l00O), (~ n0l00l), (~ n0O0ll), 1'b1}), .cin(1'b0), .cout(), .o(wire_ni1lil_o)); defparam ni1lil.sgate_representation = 0, ni1lil.width_a = 6, ni1lil.width_b = 6, ni1lil.width_o = 6; oper_add ni1liO ( .a({n0l0il, n0l0ii, n0l00O, n0l00l, n0O0ll, 1'b1}), .b({(~ n0O0OO), (~ nliil0O), (~ nliilii), (~ nliilil), (~ nliiliO), 1'b1}), .cin(1'b0), .cout(), .o(wire_ni1liO_o)); defparam ni1liO.sgate_representation = 0, ni1liO.width_a = 6, ni1liO.width_b = 6, ni1liO.width_o = 6; oper_add nl0OOi ( .a({niOOii, niOO0O, niOO0l, niOO0i, niOO1O}), .b({{4{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_nl0OOi_o)); defparam nl0OOi.sgate_representation = 0, nl0OOi.width_a = 5, nl0OOi.width_b = 5, nl0OOi.width_o = 5; oper_add nli1iO ( .a({1'b0, rins_threshold[4:0], 1'b1}), .b({1'b0, {4{1'b1}}, 1'b0, 1'b1}), .cin(1'b0), .cout(), .o(wire_nli1iO_o)); defparam nli1iO.sgate_representation = 0, nli1iO.width_a = 7, nli1iO.width_b = 7, nli1iO.width_o = 7; oper_add nllliii ( .a({nlll1iO, nlll1il, nlll1ii, nlll10O, nlll10l, 1'b1}), .b({{4{1'b1}}, 1'b0, 1'b1}), .cin(1'b0), .cout(), .o(wire_nllliii_o)); defparam nllliii.sgate_representation = 0, nllliii.width_a = 6, nllliii.width_b = 6, nllliii.width_o = 6; oper_add nllliil ( .a({nlll1iO, nlll1il, nlll1ii, nlll10O, nlll10l}), .b({{4{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_nllliil_o)); defparam nllliil.sgate_representation = 0, nllliil.width_a = 5, nllliil.width_b = 5, nllliil.width_o = 5; oper_add nllliOl ( .a({nlll1iO, nlll1il, nlll1ii, nlll10O}), .b({{3{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_nllliOl_o)); defparam nllliOl.sgate_representation = 0, nllliOl.width_a = 4, nllliOl.width_b = 4, nllliOl.width_o = 4; oper_add nllll1i ( .a({nlll1iO, nlll1il, nlll1ii, nlll10O, nlll10l}), .b({{3{1'b0}}, {2{1'b1}}}), .cin(1'b0), .cout(), .o(wire_nllll1i_o)); defparam nllll1i.sgate_representation = 0, nllll1i.width_a = 5, nllll1i.width_b = 5, nllll1i.width_o = 5; oper_add nlO000i ( .a({nlO10Oi, nli0liO, nli0lli, nli0lll, nli0llO, 1'b1}), .b({(~ nlllO0i), (~ nlllO1O), (~ nlllO1l), (~ nlllO1i), (~ nllllli), 1'b1}), .cin(1'b0), .cout(), .o(wire_nlO000i_o)); defparam nlO000i.sgate_representation = 0, nlO000i.width_a = 6, nlO000i.width_b = 6, nlO000i.width_o = 6; oper_add nlO000l ( .a({nlllO0i, nlllO1O, nlllO1l, nlllO1i, nllllli, 1'b1}), .b({(~ nlO10Oi), (~ nli0liO), (~ nli0lli), (~ nli0lll), (~ nli0llO), 1'b1}), .cin(1'b0), .cout(), .o(wire_nlO000l_o)); defparam nlO000l.sgate_representation = 0, nlO000l.width_a = 6, nlO000l.width_b = 6, nlO000l.width_o = 6; oper_add nlO001O ( .a({(~ wire_nlO000i_o[5]), (~ wire_nlO000i_o[4]), (~ wire_nlO000i_o[3]), (~ wire_nlO000i_o[2]), (~ wire_nlO000i_o[1]), 1'b1}), .b({1'b1, 1'b0, 1'b1, {2{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_nlO001O_o)); defparam nlO001O.sgate_representation = 0, nlO001O.width_a = 6, nlO001O.width_b = 6, nlO001O.width_o = 6; oper_add nlO0lli ( .a({1'b0, rfull_threshold[4:0], 1'b1}), .b({1'b0, {4{1'b1}}, 1'b0, 1'b1}), .cin(1'b0), .cout(), .o(wire_nlO0lli_o)); defparam nlO0lli.sgate_representation = 0, nlO0lli.width_a = 7, nlO0lli.width_b = 7, nlO0lli.width_o = 7; oper_add nlO101i ( .a({nlllO0i, nlllO1O, nlllO1l, nlllO1i, nllllli, 1'b1}), .b({{4{1'b1}}, 1'b0, 1'b1}), .cin(1'b0), .cout(), .o(wire_nlO101i_o)); defparam nlO101i.sgate_representation = 0, nlO101i.width_a = 6, nlO101i.width_b = 6, nlO101i.width_o = 6; oper_add nlO10iO ( .a({nlllO0i, nlllO1O, nlllO1l, nlllO1i, nllllli}), .b({{4{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_nlO10iO_o)); defparam nlO10iO.sgate_representation = 0, nlO10iO.width_a = 5, nlO10iO.width_b = 5, nlO10iO.width_o = 5; oper_decoder n011iO ( .i({nli1Ol, nli1Oi, nli1lO, nli1ll}), .o(wire_n011iO_o)); defparam n011iO.width_i = 4, n011iO.width_o = 16; oper_decoder n011ll ( .i({nli1Ol, nli1Oi}), .o(wire_n011ll_o)); defparam n011ll.width_i = 2, n011ll.width_o = 4; oper_decoder n011Oi ( .i({nli1Ol, nli1Oi, nli1lO, nli1ll, nl1i0i}), .o(wire_n011Oi_o)); defparam n011Oi.width_i = 5, n011Oi.width_o = 32; oper_decoder n0OO1l ( .i({wire_ni1l1i_dataout, wire_ni1iOO_dataout, wire_ni1iOl_dataout, wire_ni1iOi_dataout, wire_ni1ilO_dataout}), .o(wire_n0OO1l_o)); defparam n0OO1l.width_i = 5, n0OO1l.width_o = 32; oper_decoder n1l00O ( .i({n100ii, n1000O, n1000l, n1000i, n1001O}), .o(wire_n1l00O_o)); defparam n1l00O.width_i = 5, n1l00O.width_o = 32; oper_decoder n1l01l ( .i({n100ii, n1000l, n1000i, n1001O}), .o(wire_n1l01l_o)); defparam n1l01l.width_i = 4, n1l01l.width_o = 16; oper_decoder n1l1OO ( .i({n100ii, n1000O, n1000l, n1000i}), .o(wire_n1l1OO_o)); defparam n1l1OO.width_i = 4, n1l1OO.width_o = 16; oper_decoder n1OliO ( .i({rskpsetbased, rclkcmpsqmd}), .o(wire_n1OliO_o)); defparam n1OliO.width_i = 2, n1OliO.width_o = 4; oper_decoder nl0O1i ( .i({niOOii, niOO0O, niOO0l, niOO0i}), .o(wire_nl0O1i_o)); defparam nl0O1i.width_i = 4, nl0O1i.width_o = 16; oper_decoder nl0O1O ( .i({niOOii, niOO0l, niOO0i, niOO1O}), .o(wire_nl0O1O_o)); defparam nl0O1O.width_i = 4, nl0O1O.width_o = 16; oper_decoder nl0Oii ( .i({niOOii, niOO0O, niOO0l, niOO0i, niOO1O}), .o(wire_nl0Oii_o)); defparam nl0Oii.width_i = 5, nl0Oii.width_o = 32; oper_decoder nliO01i ( .i({n1O00l, n1O00i, n1O01O, n1O01l, n1ll1l}), .o(wire_nliO01i_o)); defparam nliO01i.width_i = 5, nliO01i.width_o = 32; oper_decoder nliO1lO ( .i({n1O00l, n1O00i, n1O01O, n1O01l}), .o(wire_nliO1lO_o)); defparam nliO1lO.width_i = 4, nliO1lO.width_o = 16; oper_decoder nliO1Ol ( .i({n1O00l, n1O00i}), .o(wire_nliO1Ol_o)); defparam nliO1Ol.width_i = 2, nliO1Ol.width_o = 4; oper_decoder nlli01O ( .i({wire_nlO01lO_dataout, wire_nlO01ll_dataout, wire_nlO01li_dataout, wire_nlO01iO_dataout, wire_nlO01il_dataout}), .o(wire_nlli01O_o)); defparam nlli01O.width_i = 5, nlli01O.width_o = 32; oper_less_than n11iii ( .a({nlO011i, nlO1OOO, nlO1OOl, nlO1OOi, nlO1OiO}), .b({{2{1'b0}}, rempty_threshold[2:0]}), .cin(1'b0), .o(wire_n11iii_o)); defparam n11iii.sgate_representation = 0, n11iii.width_a = 5, n11iii.width_b = 5; oper_less_than n1O01i ( .a({rins_threshold[4:0]}), .b({nlii01l, wire_nliO1Ol_o[1], nlii01O, nlii00i, nlii00l}), .cin(1'b1), .o(wire_n1O01i_o)); defparam n1O01i.sgate_representation = 0, n1O01i.width_a = 5, n1O01i.width_b = 5; oper_less_than n1O10l ( .a({3{1'b0}}), .b({n11O0l, n11O0i, n11O1O}), .cin(1'b0), .o(wire_n1O10l_o)); defparam n1O10l.sgate_representation = 0, n1O10l.width_a = 3, n1O10l.width_b = 3; oper_less_than n1O11l ( .a({n11O0l, n11O0i, n11O1O}), .b({1'b1, 1'b0, 1'b1}), .cin(1'b0), .o(wire_n1O11l_o)); defparam n1O11l.sgate_representation = 0, n1O11l.width_a = 3, n1O11l.width_b = 3; oper_less_than n1OllO ( .a({rdel_threshold[4:0]}), .b({nlO011i, nlO1OOO, nlO1OOl, nlO1OOi, nlO1OiO}), .cin(1'b0), .o(wire_n1OllO_o)); defparam n1OllO.sgate_representation = 0, n1OllO.width_a = 5, n1OllO.width_b = 5; oper_less_than n1OlOi ( .a({nlO011i, nlO1OOO, nlO1OOl, nlO1OOi, nlO1OiO}), .b({rins_threshold[4:0]}), .cin(1'b0), .o(wire_n1OlOi_o)); defparam n1OlOi.sgate_representation = 0, n1OlOi.width_a = 5, n1OlOi.width_b = 5; oper_less_than n1OOlO ( .a({nlO011i, nlO1OOO, nlO1OOl, nlO1OOi, nlO1OiO}), .b({rdel_threshold[4:0]}), .cin(1'b1), .o(wire_n1OOlO_o)); defparam n1OOlO.sgate_representation = 0, n1OOlO.width_a = 5, n1OOlO.width_b = 5; oper_less_than n1OOOi ( .a({rins_threshold[4:0]}), .b({nlO011i, nlO1OOO, nlO1OOl, nlO1OOi, nlO1OiO}), .cin(1'b1), .o(wire_n1OOOi_o)); defparam n1OOOi.sgate_representation = 0, n1OOOi.width_a = 5, n1OOOi.width_b = 5; oper_less_than ni1i1i ( .a({5{1'b0}}), .b({n0O0OO, nliil0O, nliilii, nliilil, nliiliO}), .cin(1'b0), .o(wire_ni1i1i_o)); defparam ni1i1i.sgate_representation = 0, ni1i1i.width_a = 5, ni1i1i.width_b = 5; oper_less_than ni1lli ( .a({n0O0OO, nliil0O, nliilii, nliilil, nliiliO}), .b({n0l0il, n0l0ii, n0l00O, n0l00l, n0O0ll}), .cin(1'b0), .o(wire_ni1lli_o)); defparam ni1lli.sgate_representation = 0, ni1lli.width_a = 5, ni1lli.width_b = 5; oper_less_than nli1li ( .a({rins_threshold[4:0]}), .b({nlil1Oi, wire_n011ll_o[1], nlil1Ol, nlil1OO, nlil01i}), .cin(1'b1), .o(wire_nli1li_o)); defparam nli1li.sgate_representation = 0, nli1li.width_a = 5, nli1li.width_b = 5; oper_less_than nlilOi ( .a({ni1i0l, ni1i0i, ni1i1O, ni1i1l, ni101l}), .b({{2{1'b0}}, rempty_threshold[2:0]}), .cin(1'b0), .o(wire_nlilOi_o)); defparam nlilOi.sgate_representation = 0, nlilOi.width_a = 5, nlilOi.width_b = 5; oper_less_than nlli0iO ( .a({5{1'b0}}), .b({nlO10Oi, nli0liO, nli0lli, nli0lll, nli0llO}), .cin(1'b0), .o(wire_nlli0iO_o)); defparam nlli0iO.sgate_representation = 0, nlli0iO.width_a = 5, nlli0iO.width_b = 5; oper_less_than nllOii ( .a({((nlililO40 ^ nlililO39) & ni1i0l), ni1i0i, ni1i1O, ni1i1l, ni101l}), .b({rdel_threshold[4], ((nlilill42 ^ nlilill41) & rdel_threshold[3]), rdel_threshold[2:0]}), .cin(1'b1), .o(wire_nllOii_o)); defparam nllOii.sgate_representation = 0, nllOii.width_a = 5, nllOii.width_b = 5; oper_less_than nllOil ( .a({rins_threshold[4:0]}), .b({ni1i0l, ni1i0i, ni1i1O, ni1i1l, ni101l}), .cin(1'b1), .o(wire_nllOil_o)); defparam nllOil.sgate_representation = 0, nllOil.width_a = 5, nllOil.width_b = 5; oper_less_than nllOiO ( .a({rdel_threshold[4:0]}), .b({ni1i0l, ni1i0i, ni1i1O, ((nliliOi38 ^ nliliOi37) & ni1i1l), ni101l}), .cin(1'b0), .o(wire_nllOiO_o)); defparam nllOiO.sgate_representation = 0, nllOiO.width_a = 5, nllOiO.width_b = 5; oper_less_than nllOli ( .a({ni1i0l, ni1i0i, ((nliliOl36 ^ nliliOl35) & ni1i1O), ni1i1l, ni101l}), .b({rins_threshold[4:0]}), .cin(1'b0), .o(wire_nllOli_o)); defparam nllOli.sgate_representation = 0, nllOli.width_a = 5, nllOli.width_b = 5; oper_less_than nlO000O ( .a({nlO10Oi, nli0liO, nli0lli, nli0lll, nli0llO}), .b({nlllO0i, nlllO1O, nlllO1l, nlllO1i, nllllli}), .cin(1'b0), .o(wire_nlO000O_o)); defparam nlO000O.sgate_representation = 0, nlO000O.width_a = 5, nlO000O.width_b = 5; oper_mux nllOOO ( .data({((nliliOO34 ^ nliliOO33) & wire_nlO1iO_dataout), wire_nlO10O_dataout, {2{nlO01O}}}), .o(wire_nllOOO_o), .sel({nlO01l, nllOOl})); defparam nllOOO.width_data = 4, nllOOO.width_sel = 2; oper_mux nlO11i ( .data({wire_nlO1li_dataout, ((nlill1i32 ^ nlill1i31) & wire_nlO10l_dataout), ((nlill1l30 ^ nlill1l29) & nllOOi), nllOOi}), .o(wire_nlO11i_o), .sel({nlO01l, nllOOl})); defparam nlO11i.width_data = 4, nlO11i.width_sel = 2; oper_mux nlO11l ( .data({wire_nlO1ll_dataout, wire_nlO10i_dataout, wire_nl00O_dataout, ((wire_nl0ii_dataout & wire_nl00O_dataout) & (nlill1O28 ^ nlill1O27))}), .o(wire_nlO11l_o), .sel({nlO01l, nllOOl})); defparam nlO11l.width_data = 4, nlO11l.width_sel = 2; oper_mux nlO11O ( .data({{2{wire_nl00O_dataout}}, wire_nlO1OO_dataout, 1'b0}), .o(wire_nlO11O_o), .sel({nlO01l, ((nlill0l26 ^ nlill0l25) & nllOOl)})); defparam nlO11O.width_data = 4, nlO11O.width_sel = 2; stratixiv_hssi_rx_digis_ram20x16_syn nllOll ( .clk(clk_1), .data_in({wire_nl10i_dataout, wire_nl11O_dataout, wire_nl11l_dataout, wire_nl11i_dataout, wire_niOOO_dataout, wire_niOOl_dataout, wire_niOOi_dataout, wire_niOlO_dataout, wire_niOll_dataout, wire_niOli_dataout, wire_niOiO_dataout, wire_niOil_dataout, wire_niOii_dataout, wire_niO0O_dataout, wire_niO0l_dataout, wire_niO0i_dataout}), .data_out1(wire_nllOll_data_out1), .data_out2(wire_nllOll_data_out2), .fifo_re1({wire_n1ii_dataout, wire_n10O_dataout, wire_n10l_dataout, wire_n10i_dataout, wire_n11O_dataout, wire_n11l_dataout, wire_n11i_dataout, wire_nlOOO_dataout, wire_nlOOl_dataout, wire_nlOOi_dataout, wire_nlOlO_dataout, wire_nlOll_dataout, wire_nlOli_dataout, wire_nlOiO_dataout, wire_nlOil_dataout, wire_nlOii_dataout, wire_nlO0O_dataout, wire_nlO0l_dataout, wire_nlO0i_dataout, wire_nlO1O_dataout}), .fifo_re2({wire_nlO1l_dataout, wire_nlO1i_dataout, wire_nllOO_dataout, wire_nllOl_dataout, wire_nllOi_dataout, wire_nlllO_dataout, wire_nllll_dataout, wire_nllli_dataout, wire_nlliO_dataout, wire_nllil_dataout, wire_nllii_dataout, wire_nll0O_dataout, wire_nll0l_dataout, wire_nll0i_dataout, wire_nll1O_dataout, wire_nll1l_dataout, wire_nll1i_dataout, wire_nliOO_dataout, wire_nliOl_dataout, wire_nliOi_dataout}), .fifo_wr({wire_nlilO_dataout, wire_nlill_dataout, wire_nlili_dataout, wire_nliiO_dataout, wire_nliil_dataout, wire_nliii_dataout, wire_nli0O_dataout, wire_nli0l_dataout, wire_nli0i_dataout, wire_nli1O_dataout, wire_nli1l_dataout, wire_nli1i_dataout, wire_nl0OO_dataout, wire_nl0Ol_dataout, wire_nl0Oi_dataout, wire_nl0lO_dataout, wire_nl0ll_dataout, wire_nl0li_dataout, wire_nl0iO_dataout, wire_nl0il_dataout}), .rst_l((~ wire_nl0i_dataout))); defparam nllOll.ram_width = 16, nllOll.read_access_time = 0, nllOll.write_access_time = 0; stratixiv_hssi_rx_digis_ram20x16_syn nllOlO ( .clk(clk_1), .data_in({wire_nl00l_dataout, wire_nl00i_dataout, wire_nl01O_dataout, wire_nl01l_dataout, wire_nl01i_dataout, wire_nl1OO_dataout, wire_nl1Ol_dataout, wire_nl1Oi_dataout, wire_nl1lO_dataout, wire_nl1ll_dataout, wire_nl1li_dataout, wire_nl1iO_dataout, wire_nl1il_dataout, wire_nl1ii_dataout, wire_nl10O_dataout, wire_nl10l_dataout}), .data_out1(wire_nllOlO_data_out1), .data_out2(wire_nllOlO_data_out2), .fifo_re1({wire_n1ii_dataout, wire_n10O_dataout, wire_n10l_dataout, wire_n10i_dataout, wire_n11O_dataout, wire_n11l_dataout, wire_n11i_dataout, wire_nlOOO_dataout, wire_nlOOl_dataout, wire_nlOOi_dataout, wire_nlOlO_dataout, wire_nlOll_dataout, wire_nlOli_dataout, wire_nlOiO_dataout, wire_nlOil_dataout, wire_nlOii_dataout, wire_nlO0O_dataout, wire_nlO0l_dataout, wire_nlO0i_dataout, wire_nlO1O_dataout}), .fifo_re2({wire_nlO1l_dataout, wire_nlO1i_dataout, wire_nllOO_dataout, wire_nllOl_dataout, wire_nllOi_dataout, wire_nlllO_dataout, wire_nllll_dataout, wire_nllli_dataout, wire_nlliO_dataout, wire_nllil_dataout, wire_nllii_dataout, wire_nll0O_dataout, wire_nll0l_dataout, wire_nll0i_dataout, wire_nll1O_dataout, wire_nll1l_dataout, wire_nll1i_dataout, wire_nliOO_dataout, wire_nliOl_dataout, wire_nliOi_dataout}), .fifo_wr({wire_nlilO_dataout, wire_nlill_dataout, wire_nlili_dataout, wire_nliiO_dataout, wire_nliil_dataout, wire_nliii_dataout, wire_nli0O_dataout, wire_nli0l_dataout, wire_nli0i_dataout, wire_nli1O_dataout, wire_nli1l_dataout, wire_nli1i_dataout, wire_nl0OO_dataout, wire_nl0Ol_dataout, wire_nl0Oi_dataout, wire_nl0lO_dataout, wire_nl0ll_dataout, wire_nl0li_dataout, wire_nl0iO_dataout, wire_nl0il_dataout}), .rst_l((~ wire_nl0i_dataout))); defparam nllOlO.ram_width = 16, nllOlO.read_access_time = 0, nllOlO.write_access_time = 0; assign align_status_sync = nlOiO0O, cg_comp_rd_d_out = wire_n1Oiil_dataout, cg_comp_wr_out = nlillil, comp_curr_st = {nlO01l, nllOOl}, cudi = {wire_niOi_dataout, wire_nilO_dataout, wire_nill_dataout, wire_nili_dataout, wire_niiO_dataout, wire_niil_dataout, wire_niii_dataout, wire_ni0O_dataout, wire_ni0l_dataout, wire_ni0i_dataout, wire_ni1O_dataout, wire_ni1l_dataout, wire_ni1i_dataout, wire_n0OO_dataout, wire_n0Ol_dataout, wire_n0Oi_dataout, wire_n0lO_dataout, wire_n0ll_dataout, wire_n0li_dataout, wire_n0iO_dataout, wire_n0il_dataout, wire_n0ii_dataout, wire_n00O_dataout, wire_n00l_dataout, wire_n00i_dataout, wire_n01O_dataout, wire_n01l_dataout, wire_n01i_dataout, wire_n1OO_dataout, wire_n1Ol_dataout, wire_n1Oi_dataout, wire_n1lO_dataout}, cudi_valid = wire_niiOi_dataout, del_cond_met_out = wire_n1OllO_o, fifo_cnt = {wire_nl1O_dataout, wire_nl1l_dataout, wire_nl1i_dataout, wire_niOO_dataout, wire_niOl_dataout}, fifo_ovr_out = nlO01O, fifo_rd_out_comp = n1lili, insert_incomplete_out = n1liil, latency_comp_out = (~ nlillii), nli00ll = (nlO10lO ^ nlO10li), nli00lO = (((((((((wire_nlli01O_o[18] | wire_nlli01O_o[17]) | wire_nlli01O_o[14]) | wire_nlli01O_o[13]) | wire_nlli01O_o[10]) | wire_nlli01O_o[9]) | wire_nlli01O_o[6]) | wire_nlli01O_o[5]) | wire_nlli01O_o[2]) | wire_nlli01O_o[1]), nli00Oi = ((((((((((wire_nlli01O_o[20] | wire_nlli01O_o[19]) | wire_nlli01O_o[12]) | wire_nlli01O_o[11]) | wire_nlli01O_o[4]) | wire_nlli01O_o[3]) | wire_nlli01O_o[18]) | wire_nlli01O_o[13]) | wire_nlli01O_o[10]) | wire_nlli01O_o[5]) | wire_nlli01O_o[2]), nli00Ol = ((((((((wire_nlli01O_o[20] | wire_nlli01O_o[11]) | wire_nlli01O_o[8]) | wire_nlli01O_o[7]) | wire_nlli01O_o[4]) | wire_nlli01O_o[10]) | wire_nlli01O_o[9]) | wire_nlli01O_o[6]) | wire_nlli01O_o[5]), nli00OO = ((((((((((((wire_nlli01O_o[20] | wire_nlli01O_o[19]) | wire_nlli01O_o[16]) | wire_nlli01O_o[15]) | wire_nlli01O_o[12]) | wire_nlli01O_o[11]) | wire_nlli01O_o[8]) | wire_nlli01O_o[18]) | wire_nlli01O_o[17]) | wire_nlli01O_o[14]) | wire_nlli01O_o[13]) | wire_nlli01O_o[10]) | wire_nlli01O_o[9]), nli0i0i = (wire_n1OlOi_o | nllil1i), nli0i0l = (wire_n1OllO_o | nllil1O), nli0i0O = ((((nlll1iO | nlll1il) | nlll1ii) | nlll10O) | nlll10l), nli0i1i = ((((wire_nlli01O_o[20] | wire_nlli01O_o[19]) | wire_nlli01O_o[16]) | wire_nlli01O_o[18]) | wire_nlli01O_o[17]), nli0i1l = (nli0l0i | nlli0Oi), nli0i1O = (((((wire_nlO0lli_o[6] & (~ (wire_nlO0lli_o[1] ^ nllii1O))) & (~ (wire_nlO0lli_o[2] ^ nllii0l))) & (~ (wire_nlO0lli_o[3] ^ nllii0O))) & (~ (wire_nlO0lli_o[4] ^ nlliiii))) & (~ (wire_nlO0lli_o[5] ^ nlliiil))), nli0iii = (((((~ nlll1iO) & (~ nlll1il)) & (~ nlll1ii)) & (~ nlll10O)) & (~ nlll10l)), nli0iil = (((~ rclkcmpsqmd) & (((~ rgenericfifo) & nli0l1O) | (rgenericfifo & (~ nlll1li)))) & nli0ill), nli0iiO = (nli0l1i & nli0ill), nli0ili = ((rclkcmpsqmd & (nli0l1O & (nlillOl | nllil0l))) & nli0ill), nli0ill = ((~ rskpsetbased) | (~ nli0l0i)), nli0ilO = ((rskpsetbased | ((~ rskpsetbased) & (~ nli0l1O))) & nli0l0i), nli0iOi = (((~ rgenericfifo) & (~ nli0l1O)) | (rgenericfifo & nlll1li)), nli0iOl = (((((~ nlllO0i) & (~ nlllO1O)) & (~ nlllO1l)) & (~ nlllO1i)) & (~ nllllli)), nli0iOO = ((~ rgenericfifo) & nli0l1i), nli0l0i = (((~ nli0l0l) & (nli0O1O & nli0i1O)) & (~ nlli0Ol)), nli0l0l = ((((~ rskpsetbased) & (wire_n1Olll_dataout & (wire_n1Olli_dataout & (nlillil & (((~ nlilO0l) | nliii0i) | (cg_comp_wr_ch3 & (cg_comp_wr_ch2 & (cg_comp_wr_ch0 & cg_comp_wr_ch1)))))))) | nlO1i0O) | (wire_n1OllO_o & (((rskpsetbased & (rtruebac2bac & (nlO00Oi | (nlO00lO | (nlO00ll | nlO00li))))) | ((~ rrx_pipe_enable) & (rskpsetbased & ((~ rtruebac2bac) & nlO00Oi)))) & nlO01O))), nli0l0O = (((((~ nlO011i) & (~ nlO1OOO)) & (~ (rstart_threshold[0] ^ nlO1OiO))) & (~ (rstart_threshold[1] ^ nlO1OOi))) & (~ (rstart_threshold[2] ^ nlO1OOl))), nli0l1i = (rclkcmpsqmd & nli0l1O), nli0l1l = ((((nlllO0i & (~ nlllO1O)) & (~ nlllO1l)) & nlllO1i) & nllllli), nli0l1O = (nli0l0l | (rskpsetbased & nli0l0i)), nli0lii = ((~ rgenericfifo) & (~ wire_nlOi10l_dataout)), nli0lil = (((((~ (nllllli ^ nli0llO)) & (~ (nlllO1i ^ nli0lll))) & (~ (nlllO1l ^ nli0lli))) & (~ (nlllO1O ^ nli0liO))) & (~ (nlO10Oi ^ nlllO0i))), nli0liO = ((~ nlO10Oi) & nlO10lO), nli0lli = ((~ nlO10Oi) & (nlO10lO ^ nlO10ll)), nli0lll = (nlO10Oi ^ (nlO10ll ^ nli00ll)), nli0llO = (nlO10Oi ^ (nli00ll ^ (nlO10ll ^ nllO1li))), nli0lOi = ((((((((((~ (rclkcmpsq1n[0] ^ wire_nlO0lOi_dataout)) & (~ (rclkcmpsq1n[1] ^ wire_nlO0lOl_dataout))) & (~ (rclkcmpsq1n[2] ^ wire_nlO0lOO_dataout))) & (~ (rclkcmpsq1n[3] ^ wire_nlO0O1i_dataout))) & (~ (rclkcmpsq1n[4] ^ wire_nlO0O1l_dataout))) & (~ (rclkcmpsq1n[5] ^ wire_nlO0O1O_dataout))) & (~ (rclkcmpsq1n[6] ^ wire_nlO0O0i_dataout))) & (~ (rclkcmpsq1n[7] ^ wire_nlO0O0l_dataout))) & (~ (rclkcmpsq1n[8] ^ wire_nlO0O0O_dataout))) & (~ (rclkcmpsq1n[9] ^ wire_nlO0Oii_dataout))), nli0lOl = ((((((((((~ (rclkcmpsq1p[0] ^ wire_nlO0lOi_dataout)) & (~ (rclkcmpsq1p[1] ^ wire_nlO0lOl_dataout))) & (~ (rclkcmpsq1p[2] ^ wire_nlO0lOO_dataout))) & (~ (rclkcmpsq1p[3] ^ wire_nlO0O1i_dataout))) & (~ (rclkcmpsq1p[4] ^ wire_nlO0O1l_dataout))) & (~ (rclkcmpsq1p[5] ^ wire_nlO0O1O_dataout))) & (~ (rclkcmpsq1p[6] ^ wire_nlO0O0i_dataout))) & (~ (rclkcmpsq1p[7] ^ wire_nlO0O0l_dataout))) & (~ (rclkcmpsq1p[8] ^ wire_nlO0O0O_dataout))) & (~ (rclkcmpsq1p[9] ^ wire_nlO0Oii_dataout))), nli0lOO = (nlii0OO & ((~ rclkcmpsqmd) | nlO00ii)), nli0O0i = ((~ rmatchen) | rgenericfifo), nli0O0l = (rmatchen | rgenericfifo), nli0O1i = ((~ wire_nlO0OlO_dataout) & ((~ wire_nlO0Oli_dataout) & nlO011l)), nli0O1l = (((((wire_nlO0lli_o[6] & (~ (wire_nlO0lli_o[1] ^ nllii1O))) & (~ (wire_nlO0lli_o[2] ^ nllii0l))) & (~ (wire_nlO0lli_o[3] ^ nllii0O))) & (~ (wire_nlO0lli_o[4] ^ nlliiii))) & (~ (wire_nlO0lli_o[5] ^ nlliiil))), nli0O1O = (((((~ (rfull_threshold[0] ^ nlO1OiO)) & (~ (rfull_threshold[1] ^ nlO1OOi))) & (~ (rfull_threshold[2] ^ nlO1OOl))) & (~ (rfull_threshold[3] ^ nlO1OOO))) & (~ (rfull_threshold[4] ^ nlO011i))), nli0Oii = (rgenericfifo & (~ nlOi1iO)), nli0Oil = (((~ rgenericfifo) & (~ nlii1li)) | nlOi1iO), nli0OiO = (n110ll | n110iO), nli0Oli = ((~ n110iO) & ((~ n110ll) & (n1liil & ((~ nlillii) & (wire_n1Oiil_dataout & (wire_n1Oi1O_dataout & (rmatchen & rrx_pipe_enable))))))), nli0Oll = ((((((((~ n11iOl) & (~ n11iOi)) & (~ n11ilO)) & (~ n11ill)) & (~ n11ili)) & (~ n11iiO)) & (~ n11iil)) & (~ n110lO)), nli0OlO = (rgenericfifo | wire_nlOi11i_dataout), nli0OOi = (wire_n1O11l_o & (wire_n1Oiil_dataout & (~ (((~ n11O0l) & (~ n11O0i)) & (~ n11O1O))))), nli0OOl = (wire_n1O11l_o & nlii1Ol), nli0OOO = (wire_n1Oiil_dataout & wire_n1Oi1O_dataout), nlii00i = ((((wire_nliO1lO_o[13] | wire_nliO1lO_o[7]) | wire_nliO1lO_o[4]) | wire_nliO1lO_o[2]) | wire_nliO1lO_o[1]), nlii00l = (((((((((wire_nliO01i_o[26] | wire_nliO01i_o[25]) | wire_nliO01i_o[11]) | wire_nliO01i_o[8]) | wire_nliO01i_o[7]) | wire_nliO01i_o[4]) | wire_nliO01i_o[14]) | wire_nliO01i_o[13]) | wire_nliO01i_o[2]) | wire_nliO01i_o[1]), nlii00O = ((~ rgenericfifo) & (~ wire_nlOi11i_dataout)), nlii01i = (((((wire_n1O1OO_o[6] & (~ (wire_n1O1OO_o[1] ^ nlii00l))) & (~ (wire_n1O1OO_o[2] ^ nlii00i))) & (~ (wire_n1O1OO_o[3] ^ nlii01O))) & (~ (wire_n1O1OO_o[4] ^ wire_nliO1Ol_o[1]))) & (~ (wire_n1O1OO_o[5] ^ nlii01l))), nlii01l = ((((wire_nliO01i_o[30] | wire_nliO01i_o[27]) | wire_nliO01i_o[26]) | wire_nliO01i_o[25]) | wire_nliO01i_o[24]), nlii01O = ((((((((wire_nliO01i_o[30] | wire_nliO01i_o[11]) | wire_nliO01i_o[10]) | wire_nliO01i_o[9]) | wire_nliO01i_o[8]) | wire_nliO01i_o[7]) | wire_nliO01i_o[6]) | wire_nliO01i_o[5]) | wire_nliO01i_o[4]), nlii0ii = ((((((((((~ (rclkcmpsq1n[0] ^ nlOl01O)) & (~ (rclkcmpsq1n[1] ^ nlOl00i))) & (~ (rclkcmpsq1n[2] ^ nlOl00l))) & (~ (rclkcmpsq1n[3] ^ nlOl00O))) & (~ (rclkcmpsq1n[4] ^ nlOl0ii))) & (~ (rclkcmpsq1n[5] ^ nlOl0il))) & (~ (rclkcmpsq1n[6] ^ nlOl0iO))) & (~ (rclkcmpsq1n[7] ^ nlOl0li))) & (~ (rclkcmpsq1n[8] ^ nlOl0ll))) & (~ (rclkcmpsq1n[9] ^ nlOl0lO))), nlii0il = ((((((((((~ (rclkcmpsq1p[0] ^ nlOl01O)) & (~ (rclkcmpsq1p[1] ^ nlOl00i))) & (~ (rclkcmpsq1p[2] ^ nlOl00l))) & (~ (rclkcmpsq1p[3] ^ nlOl00O))) & (~ (rclkcmpsq1p[4] ^ nlOl0ii))) & (~ (rclkcmpsq1p[5] ^ nlOl0il))) & (~ (rclkcmpsq1p[6] ^ nlOl0iO))) & (~ (rclkcmpsq1p[7] ^ nlOl0li))) & (~ (rclkcmpsq1p[8] ^ nlOl0ll))) & (~ (rclkcmpsq1p[9] ^ nlOl0lO))), nlii0iO = ((((((((((~ (rclkcmpsq1n[0] ^ nlOl10O)) & (~ (rclkcmpsq1n[1] ^ nlOl1ii))) & (~ (rclkcmpsq1n[2] ^ nlOl1il))) & (~ (rclkcmpsq1n[3] ^ nlOl1iO))) & (~ (rclkcmpsq1n[4] ^ nlOl1li))) & (~ (rclkcmpsq1n[5] ^ nlOl1ll))) & (~ (rclkcmpsq1n[6] ^ nlOl1lO))) & (~ (rclkcmpsq1n[7] ^ nlOl1Oi))) & (~ (rclkcmpsq1n[8] ^ nlOl1Ol))) & (~ (rclkcmpsq1n[9] ^ nlOl1OO))), nlii0li = ((((((((((~ (rclkcmpsq1p[0] ^ nlOl10O)) & (~ (rclkcmpsq1p[1] ^ nlOl1ii))) & (~ (rclkcmpsq1p[2] ^ nlOl1il))) & (~ (rclkcmpsq1p[3] ^ nlOl1iO))) & (~ (rclkcmpsq1p[4] ^ nlOl1li))) & (~ (rclkcmpsq1p[5] ^ nlOl1ll))) & (~ (rclkcmpsq1p[6] ^ nlOl1lO))) & (~ (rclkcmpsq1p[7] ^ nlOl1Oi))) & (~ (rclkcmpsq1p[8] ^ nlOl1Ol))) & (~ (rclkcmpsq1p[9] ^ nlOl1OO))), nlii0ll = ((((((((((~ (wire_n1OiOi_dataout ^ nlOl01O)) & (~ (wire_n1OiOl_dataout ^ nlOl00i))) & (~ (wire_n1OiOO_dataout ^ nlOl00l))) & (~ (wire_n1Ol1i_dataout ^ nlOl00O))) & (~ (wire_n1Ol1l_dataout ^ nlOl0ii))) & (~ (wire_n1Ol1O_dataout ^ nlOl0il))) & (~ (wire_n1Ol0i_dataout ^ nlOl0iO))) & (~ (wire_n1Ol0l_dataout ^ nlOl0li))) & (~ (wire_n1Ol0O_dataout ^ nlOl0ll))) & (~ (wire_n1Olii_dataout ^ nlOl0lO))), nlii0lO = ((((((((((~ (wire_n1OlOl_dataout ^ nlOl01O)) & (~ (wire_n1OlOO_dataout ^ nlOl00i))) & (~ (wire_n1OO1i_dataout ^ nlOl00l))) & (~ (wire_n1OO1l_dataout ^ nlOl00O))) & (~ (wire_n1OO1O_dataout ^ nlOl0ii))) & (~ (wire_n1OO0i_dataout ^ nlOl0il))) & (~ (wire_n1OO0l_dataout ^ nlOl0iO))) & (~ (wire_n1OO0O_dataout ^ nlOl0li))) & (~ (wire_n1OOii_dataout ^ nlOl0ll))) & (~ (wire_n1OOil_dataout ^ nlOl0lO))), nlii0Oi = ((((((((((~ (wire_n1OiOi_dataout ^ nlOl10O)) & (~ (wire_n1OiOl_dataout ^ nlOl1ii))) & (~ (wire_n1OiOO_dataout ^ nlOl1il))) & (~ (wire_n1Ol1i_dataout ^ nlOl1iO))) & (~ (wire_n1Ol1l_dataout ^ nlOl1li))) & (~ (wire_n1Ol1O_dataout ^ nlOl1ll))) & (~ (wire_n1Ol0i_dataout ^ nlOl1lO))) & (~ (wire_n1Ol0l_dataout ^ nlOl1Oi))) & (~ (wire_n1Ol0O_dataout ^ nlOl1Ol))) & (~ (wire_n1Olii_dataout ^ nlOl1OO))), nlii0Ol = ((((((((((~ (wire_n1OlOl_dataout ^ nlOl10O)) & (~ (wire_n1OlOO_dataout ^ nlOl1ii))) & (~ (wire_n1OO1i_dataout ^ nlOl1il))) & (~ (wire_n1OO1l_dataout ^ nlOl1iO))) & (~ (wire_n1OO1O_dataout ^ nlOl1li))) & (~ (wire_n1OO0i_dataout ^ nlOl1ll))) & (~ (wire_n1OO0l_dataout ^ nlOl1lO))) & (~ (wire_n1OO0O_dataout ^ nlOl1Oi))) & (~ (wire_n1OOii_dataout ^ nlOl1Ol))) & (~ (wire_n1OOil_dataout ^ nlOl1OO))), nlii0OO = (nliii1l | nliii1i), nlii10i = ((((n100ii & (~ n1000O)) & (~ n1000l)) & n1000i) & n1001O), nlii10l = (((~ rgenericfifo) & ((~ nlii1li) & wire_n1li1O_dataout)) | nlii1iO), nlii10O = (dskwclksel[0] & nlii1il), nlii11i = ((((wire_n1l1OO_o[8] | wire_n1l1OO_o[6]) | wire_n1l1OO_o[4]) | wire_n1l1OO_o[2]) | wire_n1l1OO_o[0]), nlii11l = (((((((wire_n1l00O_o[10] | wire_n1l00O_o[9]) | wire_n1l00O_o[8]) | wire_n1l00O_o[7]) | wire_n1l00O_o[6]) | wire_n1l00O_o[5]) | wire_n1l00O_o[4]) | wire_n1l00O_o[3]), nlii11O = (((((((((wire_n1l00O_o[16] | wire_n1l00O_o[15]) | wire_n1l00O_o[14]) | wire_n1l00O_o[13]) | wire_n1l00O_o[12]) | wire_n1l00O_o[11]) | wire_n1l00O_o[10]) | wire_n1l00O_o[9]) | wire_n1l00O_o[8]) | wire_n1l00O_o[7]), nlii1ii = ((~ dskwclksel[0]) & nlii1il), nlii1il = ((~ is_lane0) & nlilO0l), nlii1iO = (rgenericfifo & nlOi1iO), nlii1li = ((((~ nlilO0l) | (cg_comp_rd_d_ch3 & (cg_comp_rd_d_ch2 & (cg_comp_rd_d_ch0 & cg_comp_rd_d_ch1)))) & (wire_n1Oiil_dataout & (wire_n1O1ll_dataout & ((~ rskpsetbased) & (((~ rclkcmpsqmd) & wire_n1O1lO_dataout) & nlii1OO))))) | ((((((rclkcmpsqmd & (~ nlillii)) & (rtruebac2bac | ((~ rtruebac2bac) & (~ n11iOO)))) & n1liil) & ((nlii0Ol & nlii1lO) | (nlii0Oi & nlii1ll))) | n11O1l) | (nlii1Ol | (nlii1Oi | nlO00OO)))), nlii1ll = ((((((((((~ (rclkcmpsq1n[0] ^ nlOiOil)) & (~ (rclkcmpsq1n[1] ^ nlOiOli))) & (~ (rclkcmpsq1n[2] ^ nlOiOll))) & (~ (rclkcmpsq1n[3] ^ nlOiOlO))) & (~ (rclkcmpsq1n[4] ^ nlOiOOi))) & (~ (rclkcmpsq1n[5] ^ nlOiOOl))) & (~ (rclkcmpsq1n[6] ^ nlOiOOO))) & (~ (rclkcmpsq1n[7] ^ nlOl11i))) & (~ (rclkcmpsq1n[8] ^ nlOl11l))) & (~ (rclkcmpsq1n[9] ^ nlOl11O))), nlii1lO = ((((((((((~ (rclkcmpsq1p[0] ^ nlOiOil)) & (~ (rclkcmpsq1p[1] ^ nlOiOli))) & (~ (rclkcmpsq1p[2] ^ nlOiOll))) & (~ (rclkcmpsq1p[3] ^ nlOiOlO))) & (~ (rclkcmpsq1p[4] ^ nlOiOOi))) & (~ (rclkcmpsq1p[5] ^ nlOiOOl))) & (~ (rclkcmpsq1p[6] ^ nlOiOOO))) & (~ (rclkcmpsq1p[7] ^ nlOl11i))) & (~ (rclkcmpsq1p[8] ^ nlOl11l))) & (~ (rclkcmpsq1p[9] ^ nlOl11O))), nlii1Oi = (rskpsetbased & n110ll), nlii1Ol = (((~ wire_n1Oiil_dataout) & (((rskpsetbased & ((~ rrx_pipe_enable) & (((~ rclkcmpsqmd) & (~ nlillii)) & nlii1OO))) & n1liil) & wire_n1O10l_o)) & wire_n1O11l_o), nlii1OO = (rtruebac2bac | ((~ rtruebac2bac) & (~ n11O1i))), nliii0i = (rskpsetbased | rclkcmpsqmd), nliii0l = (n0O0Ol ^ n0O0lO), nliii0O = ((((n0O0ll & n0l0il) & (~ n0l0ii)) & (~ n0l00O)) & n0l00l), nliii1i = ((((((((((~ (wire_n1OiOi_dataout ^ wire_nlO0lOi_dataout)) & (~ (wire_n1OiOl_dataout ^ wire_nlO0lOl_dataout))) & (~ (wire_n1OiOO_dataout ^ wire_nlO0lOO_dataout))) & (~ (wire_n1Ol1i_dataout ^ wire_nlO0O1i_dataout))) & (~ (wire_n1Ol1l_dataout ^ wire_nlO0O1l_dataout))) & (~ (wire_n1Ol1O_dataout ^ wire_nlO0O1O_dataout))) & (~ (wire_n1Ol0i_dataout ^ wire_nlO0O0i_dataout))) & (~ (wire_n1Ol0l_dataout ^ wire_nlO0O0l_dataout))) & (~ (wire_n1Ol0O_dataout ^ wire_nlO0O0O_dataout))) & (~ (wire_n1Olii_dataout ^ wire_nlO0Oii_dataout))), nliii1l = ((((((((((~ (wire_n1OlOl_dataout ^ wire_nlO0lOi_dataout)) & (~ (wire_n1OlOO_dataout ^ wire_nlO0lOl_dataout))) & (~ (wire_n1OO1i_dataout ^ wire_nlO0lOO_dataout))) & (~ (wire_n1OO1l_dataout ^ wire_nlO0O1i_dataout))) & (~ (wire_n1OO1O_dataout ^ wire_nlO0O1l_dataout))) & (~ (wire_n1OO0i_dataout ^ wire_nlO0O1O_dataout))) & (~ (wire_n1OO0l_dataout ^ wire_nlO0O0i_dataout))) & (~ (wire_n1OO0O_dataout ^ wire_nlO0O0l_dataout))) & (~ (wire_n1OOii_dataout ^ wire_nlO0O0O_dataout))) & (~ (wire_n1OOil_dataout ^ wire_nlO0Oii_dataout))), nliii1O = (wire_n1OliO_o[3] | wire_n1OliO_o[0]), nliiiii = (((((((((wire_n0OO1l_o[18] | wire_n0OO1l_o[17]) | wire_n0OO1l_o[14]) | wire_n0OO1l_o[13]) | wire_n0OO1l_o[10]) | wire_n0OO1l_o[9]) | wire_n0OO1l_o[6]) | wire_n0OO1l_o[5]) | wire_n0OO1l_o[2]) | wire_n0OO1l_o[1]), nliiiil = ((((((((((wire_n0OO1l_o[20] | wire_n0OO1l_o[19]) | wire_n0OO1l_o[18]) | wire_n0OO1l_o[13]) | wire_n0OO1l_o[12]) | wire_n0OO1l_o[11]) | wire_n0OO1l_o[10]) | wire_n0OO1l_o[5]) | wire_n0OO1l_o[4]) | wire_n0OO1l_o[3]) | wire_n0OO1l_o[2]), nliiiiO = ((((((((wire_n0OO1l_o[20] | wire_n0OO1l_o[11]) | wire_n0OO1l_o[10]) | wire_n0OO1l_o[9]) | wire_n0OO1l_o[8]) | wire_n0OO1l_o[7]) | wire_n0OO1l_o[6]) | wire_n0OO1l_o[5]) | wire_n0OO1l_o[4]), nliiili = ((((((((((((wire_n0OO1l_o[20] | wire_n0OO1l_o[19]) | wire_n0OO1l_o[18]) | wire_n0OO1l_o[17]) | wire_n0OO1l_o[16]) | wire_n0OO1l_o[15]) | wire_n0OO1l_o[14]) | wire_n0OO1l_o[13]) | wire_n0OO1l_o[12]) | wire_n0OO1l_o[11]) | wire_n0OO1l_o[10]) | wire_n0OO1l_o[9]) | wire_n0OO1l_o[8]), nliiill = ((((wire_n0OO1l_o[20] | wire_n0OO1l_o[19]) | wire_n0OO1l_o[18]) | wire_n0OO1l_o[17]) | wire_n0OO1l_o[16]), nliiilO = (((((~ ni1i0l) & (~ ni1i0i)) & (~ (rstart_threshold[0] ^ ni101l))) & (~ (rstart_threshold[1] ^ ni1i1l))) & (~ (rstart_threshold[2] ^ ni1i1O))), nliiiOi = (nliiO0O | n0OOli), nliiiOl = (((((wire_n0OOOO_o[6] & (~ (wire_n0OOOO_o[1] ^ n0OOll))) & (~ (ni111i ^ wire_n0OOOO_o[2]))) & (~ (ni111l ^ wire_n0OOOO_o[3]))) & (~ (ni111O ^ wire_n0OOOO_o[4]))) & (~ (ni110i ^ wire_n0OOOO_o[5]))), nliiiOO = (((((~ (rfull_threshold[0] ^ ni101l)) & (~ (rfull_threshold[1] ^ ni1i1l))) & (~ (rfull_threshold[2] ^ ni1i1O))) & (~ (rfull_threshold[3] ^ ni1i0i))) & (~ (rfull_threshold[4] ^ ni1i0l))), nliil0i = (wire_nllOiO_o | ni11OO), nliil0l = (((((~ (n0O0ll ^ nliiliO)) & (~ (n0l00l ^ nliilil))) & (~ (n0l00O ^ nliilii))) & (~ (n0l0ii ^ nliil0O))) & (~ (n0O0OO ^ n0l0il))), nliil0O = ((~ n0O0OO) & n0O0Ol), nliil1O = (wire_nllOli_o | ni11lO), nliilii = ((~ n0O0OO) & (n0O0Ol ^ n0O0Oi)), nliilil = (n0O0OO ^ (n0O0Oi ^ nliii0l)), nliiliO = (n0O0OO ^ (nliii0l ^ (n0O0Oi ^ n0liOl))), nliilli = (wire_nllOiO_o & ((ni00Oi | ni00iO) & nlO01O)), nliilll = (((((~ ni1O0l) & (~ ni1O0i)) & (~ ni1O1O)) & (~ ni1O1l)) & (~ ni1llO)), nliillO = ((((~ rgenericfifo) & nliilOO) | (rgenericfifo & (~ n0Oiil))) & (~ nliiO0O)), nliilOi = ((((ni1O0l | ni1O0i) | ni1O1O) | ni1O1l) | ni1llO), nliilOl = (((~ rgenericfifo) & (~ nliilOO)) | (rgenericfifo & n0Oiil)), nliilOO = (nliilli | nliiO0O), nliiO0i = ((((((((((~ (sudi[14] ^ rclkcmpsq1n[0])) & (~ (sudi[15] ^ rclkcmpsq1n[1]))) & (~ (sudi[16] ^ rclkcmpsq1n[2]))) & (~ (sudi[17] ^ rclkcmpsq1n[3]))) & (~ (sudi[18] ^ rclkcmpsq1n[4]))) & (~ (sudi[19] ^ rclkcmpsq1n[5]))) & (~ (sudi[20] ^ rclkcmpsq1n[6]))) & (~ (sudi[21] ^ rclkcmpsq1n[7]))) & (~ (sudi[22] ^ rclkcmpsq1n[8]))) & (~ (sudi[23] ^ rclkcmpsq1n[9]))), nliiO0l = ((((((((((~ (sudi[14] ^ rclkcmpsq1p[0])) & (~ (sudi[15] ^ rclkcmpsq1p[1]))) & (~ (sudi[16] ^ rclkcmpsq1p[2]))) & (~ (sudi[17] ^ rclkcmpsq1p[3]))) & (~ (sudi[18] ^ rclkcmpsq1p[4]))) & (~ (sudi[19] ^ rclkcmpsq1p[5]))) & (~ (sudi[20] ^ rclkcmpsq1p[6]))) & (~ (sudi[21] ^ rclkcmpsq1p[7]))) & (~ (sudi[22] ^ rclkcmpsq1p[8]))) & (~ (sudi[23] ^ rclkcmpsq1p[9]))), nliiO0O = ((~ ni1i0O) & ((~ nliilli) & (nliiiOO & nliiiOl))), nliiO1i = ((~ rgenericfifo) & (~ wire_nliOOi_dataout)), nliiO1l = ((((((((((~ (sudi[0] ^ rclkcmpsq1n[0])) & (~ (sudi[1] ^ rclkcmpsq1n[1]))) & (~ (sudi[2] ^ rclkcmpsq1n[2]))) & (~ (sudi[3] ^ rclkcmpsq1n[3]))) & (~ (sudi[4] ^ rclkcmpsq1n[4]))) & (~ (sudi[5] ^ rclkcmpsq1n[5]))) & (~ (sudi[6] ^ rclkcmpsq1n[6]))) & (~ (sudi[7] ^ rclkcmpsq1n[7]))) & (~ (sudi[8] ^ rclkcmpsq1n[8]))) & (~ (sudi[9] ^ rclkcmpsq1n[9]))), nliiO1O = ((((((((((~ (sudi[0] ^ rclkcmpsq1p[0])) & (~ (sudi[1] ^ rclkcmpsq1p[1]))) & (~ (sudi[2] ^ rclkcmpsq1p[2]))) & (~ (sudi[3] ^ rclkcmpsq1p[3]))) & (~ (sudi[4] ^ rclkcmpsq1p[4]))) & (~ (sudi[5] ^ rclkcmpsq1p[5]))) & (~ (sudi[6] ^ rclkcmpsq1p[6]))) & (~ (sudi[7] ^ rclkcmpsq1p[7]))) & (~ (sudi[8] ^ rclkcmpsq1p[8]))) & (~ (sudi[9] ^ rclkcmpsq1p[9]))), nliiOii = (nliiOiO | nliiOil), nliiOil = ((((((((((~ (sudi[14] ^ rclkcmpsq1n[10])) & (~ (sudi[15] ^ rclkcmpsq1n[11]))) & (~ (sudi[16] ^ rclkcmpsq1n[12]))) & (~ (sudi[17] ^ rclkcmpsq1n[13]))) & (~ (sudi[18] ^ rclkcmpsq1n[14]))) & (~ (sudi[19] ^ rclkcmpsq1n[15]))) & (~ (sudi[20] ^ rclkcmpsq1n[16]))) & (~ (sudi[21] ^ rclkcmpsq1n[17]))) & (~ (sudi[22] ^ rclkcmpsq1n[18]))) & (~ (sudi[23] ^ rclkcmpsq1n[19]))), nliiOiO = ((((((((((~ (sudi[14] ^ rclkcmpsq1p[10])) & (~ (sudi[15] ^ rclkcmpsq1p[11]))) & (~ (sudi[16] ^ rclkcmpsq1p[12]))) & (~ (sudi[17] ^ rclkcmpsq1p[13]))) & (~ (sudi[18] ^ rclkcmpsq1p[14]))) & (~ (sudi[19] ^ rclkcmpsq1p[15]))) & (~ (sudi[20] ^ rclkcmpsq1p[16]))) & (~ (sudi[21] ^ rclkcmpsq1p[17]))) & (~ (sudi[22] ^ rclkcmpsq1p[18]))) & (~ (sudi[23] ^ rclkcmpsq1p[19]))), nliiOli = (nliiOlO | nliiOll), nliiOll = ((((((((((~ (sudi[0] ^ rclkcmpsq1n[10])) & (~ (sudi[1] ^ rclkcmpsq1n[11]))) & (~ (sudi[2] ^ rclkcmpsq1n[12]))) & (~ (sudi[3] ^ rclkcmpsq1n[13]))) & (~ (sudi[4] ^ rclkcmpsq1n[14]))) & (~ (sudi[5] ^ rclkcmpsq1n[15]))) & (~ (sudi[6] ^ rclkcmpsq1n[16]))) & (~ (sudi[7] ^ rclkcmpsq1n[17]))) & (~ (sudi[8] ^ rclkcmpsq1n[18]))) & (~ (sudi[9] ^ rclkcmpsq1n[19]))), nliiOlO = ((((((((((~ (sudi[0] ^ rclkcmpsq1p[10])) & (~ (sudi[1] ^ rclkcmpsq1p[11]))) & (~ (sudi[2] ^ rclkcmpsq1p[12]))) & (~ (sudi[3] ^ rclkcmpsq1p[13]))) & (~ (sudi[4] ^ rclkcmpsq1p[14]))) & (~ (sudi[5] ^ rclkcmpsq1p[15]))) & (~ (sudi[6] ^ rclkcmpsq1p[16]))) & (~ (sudi[7] ^ rclkcmpsq1p[17]))) & (~ (sudi[8] ^ rclkcmpsq1p[18]))) & (~ (sudi[9] ^ rclkcmpsq1p[19]))), nlil00i = (nlil0l | nlil1O), nlil00l = ((~ rgenericfifo) & (~ wire_nliOlO_dataout)), nlil00O = (rgenericfifo | wire_nliOlO_dataout), nlil01i = (((((((((wire_n011Oi_o[26] | wire_n011Oi_o[25]) | wire_n011Oi_o[11]) | wire_n011Oi_o[8]) | wire_n011Oi_o[7]) | wire_n011Oi_o[4]) | wire_n011Oi_o[14]) | wire_n011Oi_o[13]) | wire_n011Oi_o[2]) | wire_n011Oi_o[1]), nlil01O = (rgenericfifo & nli0il), nlil0ii = ((((((((((~ (rclkcmpsq1n[0] ^ wire_nllOlO_data_out2[0])) & (~ (rclkcmpsq1n[1] ^ wire_nllOlO_data_out2[1]))) & (~ (rclkcmpsq1n[2] ^ wire_nllOlO_data_out2[2]))) & (~ (rclkcmpsq1n[3] ^ wire_nllOlO_data_out2[3]))) & (~ (rclkcmpsq1n[4] ^ wire_nllOlO_data_out2[4]))) & (~ (rclkcmpsq1n[5] ^ wire_nllOlO_data_out2[5]))) & (~ (rclkcmpsq1n[6] ^ wire_nllOlO_data_out2[6]))) & (~ (rclkcmpsq1n[7] ^ wire_nllOlO_data_out2[7]))) & (~ (rclkcmpsq1n[8] ^ wire_nllOlO_data_out2[8]))) & (~ (rclkcmpsq1n[9] ^ wire_nllOlO_data_out2[9]))), nlil0il = ((((((((((~ (rclkcmpsq1p[0] ^ wire_nllOlO_data_out2[0])) & (~ (rclkcmpsq1p[1] ^ wire_nllOlO_data_out2[1]))) & (~ (rclkcmpsq1p[2] ^ wire_nllOlO_data_out2[2]))) & (~ (rclkcmpsq1p[3] ^ wire_nllOlO_data_out2[3]))) & (~ (rclkcmpsq1p[4] ^ wire_nllOlO_data_out2[4]))) & (~ (rclkcmpsq1p[5] ^ wire_nllOlO_data_out2[5]))) & (~ (rclkcmpsq1p[6] ^ wire_nllOlO_data_out2[6]))) & (~ (rclkcmpsq1p[7] ^ wire_nllOlO_data_out2[7]))) & (~ (rclkcmpsq1p[8] ^ wire_nllOlO_data_out2[8]))) & (~ (rclkcmpsq1p[9] ^ wire_nllOlO_data_out2[9]))), nlil0iO = (nlil0l | nliliii), nlil0lO = ((((((((((~ (rclkcmpsq1n[10] ^ wire_nllOll_data_out2[0])) & (~ (rclkcmpsq1n[11] ^ wire_nllOll_data_out2[1]))) & (~ (rclkcmpsq1n[12] ^ wire_nllOll_data_out2[2]))) & (~ (rclkcmpsq1n[13] ^ wire_nllOll_data_out2[3]))) & (~ (rclkcmpsq1n[14] ^ wire_nllOll_data_out2[4]))) & (~ (rclkcmpsq1n[15] ^ wire_nllOll_data_out2[5]))) & (~ (rclkcmpsq1n[16] ^ wire_nllOll_data_out2[6]))) & (~ (rclkcmpsq1n[17] ^ wire_nllOll_data_out2[7]))) & (~ (rclkcmpsq1n[18] ^ wire_nllOll_data_out2[8]))) & (~ (rclkcmpsq1n[19] ^ wire_nllOll_data_out2[9]))), nlil0Oi = ((((((((((~ (rclkcmpsq1p[10] ^ wire_nllOll_data_out2[0])) & (~ (rclkcmpsq1p[11] ^ wire_nllOll_data_out2[1]))) & (~ (rclkcmpsq1p[12] ^ wire_nllOll_data_out2[2]))) & (~ (rclkcmpsq1p[13] ^ wire_nllOll_data_out2[3]))) & (~ (rclkcmpsq1p[14] ^ wire_nllOll_data_out2[4]))) & (~ (rclkcmpsq1p[15] ^ wire_nllOll_data_out2[5]))) & (~ (rclkcmpsq1p[16] ^ wire_nllOll_data_out2[6]))) & (~ (rclkcmpsq1p[17] ^ wire_nllOll_data_out2[7]))) & (~ (rclkcmpsq1p[18] ^ wire_nllOll_data_out2[8]))) & (~ (rclkcmpsq1p[19] ^ wire_nllOll_data_out2[9]))), nlil10i = (((((((((nii0il & nii0ii) & nii00O) & (~ nii00l)) & nii00i) & (~ nii01O)) & (~ nii01i)) & (~ nii1OO)) & (~ ((~ rclkcmpinsertpad) ^ nii1Ol))) & (~ (rclkcmpinsertpad ^ nii01l))), nlil10l = (rgenericfifo & (~ nli0il)), nlil10O = (nli0il | ((~ rgenericfifo) & (~ nlil0iO))), nlil11i = ((((((((((~ nii1ii) & (~ nii10O)) & (~ nii10l)) & nii10i) & (~ nii11O)) & nii11l) & ni0OOO) & ni0OOl) & (~ (rclkcmpinsertpad ^ ni0OOi))) & (~ ((~ rclkcmpinsertpad) ^ nii11i))), nlil11l = (((((((((nii1ii & nii10O) & nii10l) & (~ nii10i)) & nii11O) & (~ nii11l)) & (~ ni0OOO)) & (~ ni0OOl)) & (~ ((~ rclkcmpinsertpad) ^ ni0OOi))) & (~ (rclkcmpinsertpad ^ nii11i))), nlil11O = ((((((((((~ nii0il) & (~ nii0ii)) & (~ nii00O)) & nii00l) & (~ nii00i)) & nii01O) & nii01i) & nii1OO) & (~ (rclkcmpinsertpad ^ nii1Ol))) & (~ ((~ rclkcmpinsertpad) ^ nii01l))), nlil1ii = ((((wire_nl0O1i_o[8] | wire_nl0O1i_o[6]) | wire_nl0O1i_o[4]) | wire_nl0O1i_o[2]) | wire_nl0O1i_o[0]), nlil1il = (((((((wire_nl0Oii_o[10] | wire_nl0Oii_o[9]) | wire_nl0Oii_o[8]) | wire_nl0Oii_o[7]) | wire_nl0Oii_o[6]) | wire_nl0Oii_o[5]) | wire_nl0Oii_o[4]) | wire_nl0Oii_o[3]), nlil1iO = (((((((((wire_nl0Oii_o[16] | wire_nl0Oii_o[15]) | wire_nl0Oii_o[14]) | wire_nl0Oii_o[13]) | wire_nl0Oii_o[12]) | wire_nl0Oii_o[11]) | wire_nl0Oii_o[10]) | wire_nl0Oii_o[9]) | wire_nl0Oii_o[8]) | wire_nl0Oii_o[7]), nlil1li = ((((niOOii & (~ niOO0O)) & (~ niOO0l)) & niOO0i) & niOO1O), nlil1ll = (((~ rgenericfifo) & (nlii0O & (~ nlil0iO))) | nlil01O), nlil1lO = (((((wire_nli1iO_o[6] & (~ (wire_nli1iO_o[1] ^ nlil01i))) & (~ (wire_nli1iO_o[2] ^ nlil1OO))) & (~ (wire_nli1iO_o[3] ^ nlil1Ol))) & (~ (wire_nli1iO_o[4] ^ wire_n011ll_o[1]))) & (~ (wire_nli1iO_o[5] ^ nlil1Oi))), nlil1Oi = ((((wire_n011Oi_o[30] | wire_n011Oi_o[27]) | wire_n011Oi_o[26]) | wire_n011Oi_o[25]) | wire_n011Oi_o[24]), nlil1Ol = ((((((((wire_n011Oi_o[30] | wire_n011Oi_o[11]) | wire_n011Oi_o[10]) | wire_n011Oi_o[9]) | wire_n011Oi_o[8]) | wire_n011Oi_o[7]) | wire_n011Oi_o[6]) | wire_n011Oi_o[5]) | wire_n011Oi_o[4]), nlil1OO = ((((wire_n011iO_o[13] | wire_n011iO_o[7]) | wire_n011iO_o[4]) | wire_n011iO_o[2]) | wire_n011iO_o[1]), nlili0i = ((((((((((~ (rclkcmpsq1p[10] ^ ni0O1O)) & (~ (rclkcmpsq1p[11] ^ ni0O0i))) & (~ (rclkcmpsq1p[12] ^ ni0O0l))) & (~ (rclkcmpsq1p[13] ^ ni0O0O))) & (~ (rclkcmpsq1p[14] ^ ni0Oii))) & (~ (rclkcmpsq1p[15] ^ ni0Oil))) & (~ (rclkcmpsq1p[16] ^ ni0OiO))) & (~ (rclkcmpsq1p[17] ^ ni0Oli))) & (~ (rclkcmpsq1p[18] ^ ni0Oll))) & (~ (rclkcmpsq1p[19] ^ ni0OlO))), nlili1i = ((((((((((~ (rclkcmpsq1n[0] ^ ni00Ol)) & (~ (rclkcmpsq1n[1] ^ ni0liO))) & (~ (rclkcmpsq1n[2] ^ ni0lli))) & (~ (rclkcmpsq1n[3] ^ ni0lll))) & (~ (rclkcmpsq1n[4] ^ ni0llO))) & (~ (rclkcmpsq1n[5] ^ ni0lOi))) & (~ (rclkcmpsq1n[6] ^ ni0lOl))) & (~ (rclkcmpsq1n[7] ^ ni0lOO))) & (~ (rclkcmpsq1n[8] ^ ni0O1i))) & (~ (rclkcmpsq1n[9] ^ ni0O1l))), nlili1l = ((((((((((~ (rclkcmpsq1p[0] ^ ni00Ol)) & (~ (rclkcmpsq1p[1] ^ ni0liO))) & (~ (rclkcmpsq1p[2] ^ ni0lli))) & (~ (rclkcmpsq1p[3] ^ ni0lll))) & (~ (rclkcmpsq1p[4] ^ ni0llO))) & (~ (rclkcmpsq1p[5] ^ ni0lOi))) & (~ (rclkcmpsq1p[6] ^ ni0lOl))) & (~ (rclkcmpsq1p[7] ^ ni0lOO))) & (~ (rclkcmpsq1p[8] ^ ni0O1i))) & (~ (rclkcmpsq1p[9] ^ ni0O1l))), nlili1O = ((((((((((~ (rclkcmpsq1n[10] ^ ni0O1O)) & (~ (rclkcmpsq1n[11] ^ ni0O0i))) & (~ (rclkcmpsq1n[12] ^ ni0O0l))) & (~ (rclkcmpsq1n[13] ^ ni0O0O))) & (~ (rclkcmpsq1n[14] ^ ni0Oii))) & (~ (rclkcmpsq1n[15] ^ ni0Oil))) & (~ (rclkcmpsq1n[16] ^ ni0OiO))) & (~ (rclkcmpsq1n[17] ^ ni0Oli))) & (~ (rclkcmpsq1n[18] ^ ni0Oll))) & (~ (rclkcmpsq1n[19] ^ ni0OlO))), nliliii = (nliO1i & (nlii0i & (~ nliliil))), nliliil = (wire_nli1li_o | (nlilOl & nlil1lO)), nliliiO = ((~ rmatchen) | rgenericfifo), nlilili = (rmatchen | rgenericfifo), nlill0O = (wire_n1li_dataout | wire_n1iO_dataout), nlillii = (wire_n1O01i_o | (n11O1i & nlii01i)), nlillil = (((~ wire_nlO0OlO_dataout) & ((~ wire_nlO0Oli_dataout) & nlO00Ol)) & (~ (nli0O1O & nli0O1l))), nlillOi = ((wire_n1OllO_o & (nli0O1i & (((~ wire_nlO0OiO_dataout) & ((~ wire_nlO0Oil_dataout) & (rrx_pipe_enable & nlii0OO))) & nlO01O))) & ((~ nli0l0i) & (~ nlli0Oi))), nlillOl = ((((~ rrx_pipe_enable) & nli0ill) & nli0iOi) & nli0i0O), nlillOO = ((nliilOl & (~ nliiO0O)) & nliilOi), nlilO0l = (dskwclksel[1] & rmatchen), nlilOil = 1'b0, nlilOiO = (((((rauto_speed_ena & (~ rfreq_sel)) & (nlilOlO12 ^ nlilOlO11)) & nlll) | rdwidth_rx) | (~ (nlilOli14 ^ nlilOli13))), nliO10l = 1'b1, nliO11i = ((((rauto_speed_ena & (~ rfreq_sel)) & (nliO11l6 ^ nliO11l5)) & n1O) | rdwidth_rx), nliO1il = (wire_nlil_dataout | soft_reset), rdfifo_almost_empty = wire_nll_dataout, rdfifo_almost_full = wire_ni_dataout, rdfifo_empty = wire_nli_dataout, rdfifo_full = wire_nlO_dataout, rev_loop_data = {wire_niO1O_dataout, wire_niO1l_dataout, wire_niO1i_dataout, wire_nilOO_dataout, wire_nilOl_dataout, wire_nilOi_dataout, wire_nillO_dataout, wire_nilll_dataout, wire_nilli_dataout, wire_niliO_dataout, wire_nilil_dataout, wire_nilii_dataout, wire_nil0O_dataout, wire_nil0l_dataout, wire_nil0i_dataout, wire_nil1O_dataout, wire_nil1l_dataout, wire_nil1i_dataout, wire_niiOO_dataout, wire_niiOl_dataout}, skpos_det = nlillil; endmodule //stratixiv_hssi_rx_digi_comp_chnl_top //synopsys translate_on //VALID FILE //Rev: 1.37 Fri May 23 09:56:18 PDT 2008 `timescale 1 ps / 1 ps module stratixiv_hssi_rx_digi_rx_ctrl ( // inputs //hard_reset, soft_reset, clk_2, rx_wr_clk, rx_rd_clk, scan_mode, rrxfifo_dis, //is_lane0, rindv_rx, rendec_data_sel_rx, rwa_6g_en, rrxfifo_lowlatency_en, //indv_tx, endec_rx, //endec_tx, rinvalid_code_err_only, rrx_pipe_enable, rpmadatawidth, //renpolinv, rdwidth, rautoinsdis, rbytorden, rbytord_2sym_en, rbytordpat, rbytordpadval, rbytordplden, bytordplden, rsync_comp_size, rsync_comp_pat, rsync_comp_porn, rsync_sm_dis, //phfifo_wren_rx, //phfifo_rden_rx, rclkcmpinsertpad, rbytord_6g_mask_en, rbytord_s2gx, invalid_code_delay, sigdetni, dec_data_valid_pre, dec_data_valid, rx_data_rs, rx_control_rs, rx_data_dt, rx_control_dt, tenb_data, sync_resync_pre, sync_resync_delay, disp_err_delay, disp_val_delay, //rgenericfifo, //rdfifo_full, ovr_undflow, rrxfifo_urst_en, rxfifo_urst, rrxphfifopldctl_en, pld_wr_dis, pld_re, rrxpcsbypass_en, //PIPE Status signals phystatus_int, rxvalid_int, rxstatus_int, powerdown, // New inputs for new bundling scheme and new PCIE features like autospeed reset_pc_ptrs, reset_pc_ptrs_centrl, reset_pc_ptrs_quad_up, reset_pc_ptrs_quad_down, gen2ngen1, gen2ngen1_bundle, dis_pc_byte, wr_enable_centrl, wr_enable_quad_up, wr_enable_quad_down, rd_enable_centrl, rd_enable_quad_up, rd_enable_quad_down, rx_we_in_centrl, rx_we_in_quad_up, rx_we_in_quad_down, // New MDIO for new bundling scheme and new PCIE features like autospeed rauto_speed_ena, rfreq_sel, rphfifo_regmode_rx, rmaster_rx, rmaster_up_rx, // outputs rxd, rxd_9, rxd_19, rxc, running_disp, signal_detect_out, rxd_lpbk, rx_we_out, //full, ph_fifo_empty, ph_fifo_full, wr_enable_out, rd_enable_out, bytord_valid_out, soft_reset_rclk1, soft_reset_wclk1, // PIPE status signals phystatus, rxvalid, rxstatus, pipe_data, // test bus // rx_we_out, // testbus[8], re-used wr_enable2, // testbus[7] wptr_bin, // testbus[6:4] rd_enable2, // testbus[3] rptr_bin, // testbus[2:0] pcs_wrapback_in, rpcs_wrapback_en ); // ======= // inputs // ======= input [1:0] rbytorden; // enable byte ordering block // 00: disable byte ordering on sync_status (auto byte ordering) // 01: 8-bit match, auto byte ordering or pld control byte ordering // 10: 9-bit match, auto byte ordering or pld control byte ordering // 11: 10-bit match, auto byte ordering or pld control byte ordering input rbytord_2sym_en; // enable 2 symbol longer byte ordering input [19:0] rbytordpat; // searched byte ordering pattern for byte ordering block, // upper bits[19:10] is shared with // rsync_comp_pat[39:32] input [9:0] rbytordpadval; // Padded pattern for byte ordering block input rbytordplden; // enable byteordpld - dynamic signal input bytordplden; // byteordpld - dynamic signal. Positive Edge of // this signal triggers new byte ordering input rautoinsdis; // disable automatic insertion of 8'h9c when invalid data //input hard_reset; // From MDIO_REG.V Complex function of NPOR, ENTEST etc., input soft_reset; input clk_2; input rx_rd_clk; // This replaces PLD_RX_CLK input rx_wr_clk; // divided by 1 or 2 write clock. input scan_mode; // scan enable input rrxfifo_dis; // (CRAM = 1) bypass phase comp fifo //input is_lane0; // ch0 input rindv_rx; // For non P_LPBK mode input rendec_data_sel_rx; // RX 8B10B decoder data out selection CRAM (1: indv; 0: sel SM) input rwa_6g_en; // decoder cascaded enable, indicating it is 6G or 3G input rrxfifo_lowlatency_en; // low latency enable //input indv_tx; // For P_LPBK mode input endec_rx; // Enable 8B/10B decoder for non P_LPBK mode //input endec_tx; // Enable 8B/10B encoder for P_LPBK mode input rinvalid_code_err_only; // treat only invalid code as errors input rrx_pipe_enable; // PIPE mode: treat 19C replacement as invalid code //input renpolinv; // Enable polarity inversion CRAM input rdwidth; input rpmadatawidth; input [2:0] rsync_comp_size; input [39:0] rsync_comp_pat; input rsync_comp_porn; input rsync_sm_dis; input rclkcmpinsertpad; // CRAM for PCI-E PAD value selection if an error occurs input rbytord_6g_mask_en; //CRAM to enabled upper byte of 6G DW B.O. to be masked out input rbytord_s2gx; //CRAM to enable byte ordering to behave like S2GX byte ordering input [1:0] invalid_code_delay; input sigdetni; // from PMA directly input [1:0] dec_data_valid_pre; // decoded data valid 1 cycle ahead, for 3G BO enable input [1:0] dec_data_valid; // decoded data valid input [7:0] rx_data_rs; // data from rcv_sm input rx_control_rs; // control bits from rcv_sm input [15:0] rx_data_dt; // data from 8b10b decoder input [1:0] rx_control_dt; // control bits from 8b10b decoder input [19:0] tenb_data; // pre-decoded data input [1:0] sync_resync_pre; // sync_resync flag 1 cycle ahead, for A1A1A2A2 3G BO input [1:0] sync_resync_delay; // sync_resync flag input [1:0] disp_err_delay; // RD error flag input [1:0] disp_val_delay; // RD value flag //input rgenericfifo; // Select genericfifo mode //input rdfifo_full; // from comp_fifo input [3:0] ovr_undflow; // from dec_chnl_top // rx_we_out // Connect from channel zero rx_we_out input rrxfifo_urst_en; // Enable rxfifo_urst input rxfifo_urst; // User reset exclusive to rx_ctrl & below input rrxphfifopldctl_en; // CRAM to enable PLD controlled write/read enable input pld_wr_dis; // PLD write disable input pld_re; // PLD read eanble input rrxpcsbypass_en; // CRAM for enable low-latency PCS bypass mode // PIPE status input input phystatus_int; input rxvalid_int; input [2:0] rxstatus_int; input [1:0] powerdown; // New Inputs for new bundling scheme and new PCIE features like autospeed input reset_pc_ptrs; input reset_pc_ptrs_centrl; input reset_pc_ptrs_quad_up; input reset_pc_ptrs_quad_down; input gen2ngen1; input gen2ngen1_bundle; input dis_pc_byte; input wr_enable_centrl; input wr_enable_quad_up; input wr_enable_quad_down; input rd_enable_centrl; input rd_enable_quad_up; input rd_enable_quad_down; input rx_we_in_centrl; input rx_we_in_quad_up; input rx_we_in_quad_down; // New MDIO for new bundling scheme and new PCIE features like autospeed input rauto_speed_ena; input rfreq_sel; input rphfifo_regmode_rx; input rmaster_rx; input rmaster_up_rx; input [69:0] pcs_wrapback_in; input rpcs_wrapback_en; // ======= // outputs // ======= output [63:0] rxd; output [1:0] rxd_9; output [1:0] rxd_19; output [3:0] rxc; output [1:0] running_disp; // Only used in XAUI receive state machine , only bit[0] is used output signal_detect_out;// To control pin/bit output [39:0] rxd_lpbk; output rx_we_out; // connect channel zero rx_we_out 05/15/02 VC //output full; // Mux between rdfifo_full and ovr_undflow output ph_fifo_full; // phase comp. FIFO full flag output ph_fifo_empty; // phase comp. FIFO empty flag output wr_enable_out; output rd_enable_out; output bytord_valid_out; // byte ordering valid flag output soft_reset_rclk1; // reset output for PIPE interface module output soft_reset_wclk1; // PIPE output phystatus; output rxvalid; output [2:0] rxstatus; output [63:0] pipe_data; // ======== // test bus // ======== output wr_enable2; output rd_enable2; output [2:0] wptr_bin; output [2:0] rptr_bin; // ==================== // signal declarations // ==================== parameter delay = 0; // ensure hold time between // deserializer and fifo for RTL simulation wire [39:0] rxd_lpbk; wire [63:0] rxd; wire [1:0] rxd_9; wire [3:0] rxc; wire [1:0] running_disp; reg [1:0] sync_resync_d; reg [1:0] disp_err_d; reg [1:0] disp_val_d; // reset signals wire rrxfifo_urst_en; wire local_soft_reset; // OR of local & global resets. wire local_soft_reset_low; // Inverted soft reset for active low fifo reset reg soft_reset_wclk0; reg soft_reset_wclk1_b4scan; wire soft_reset_wclk1; // reset for fifo_wr_clk reg soft_reset_rclk0; reg soft_reset_rclk1_b4scan; wire soft_reset_rclk1; // reset for pld_rx_clk // flags reg [1:0] sync_resync_delay_1; reg [1:0] sync_resync_delay_2; reg [1:0] disp_err_delay_1; reg [1:0] disp_err_delay_2; reg [1:0] disp_val_delay_1; reg [1:0] disp_val_delay_2; reg [3:0] ovr_undflow_d; // pre-register value reg [3:0] ovr_undflow0; // delayed overflow/underflow flags in XAUI reg [3:0] ovr_undflow1; // delayed overflow/underflow flags in XAUI // pattern detection signals reg [1:0] pattern_det_1_latch; reg [1:0] pattern_det_int; reg [1:0] pattern_det_int_delay_1; reg [1:0] pattern_det_int_delay_2; reg pd_16bit_high; reg pd_20bit_high; reg pd_32bit_low; reg pd_40bit_low; reg pd_32bit_high0; reg pd_32bit_high1; reg pd_40bit_high0; reg pd_40bit_high1; reg [1:0] pattern_det_d; reg [1:0] pattern_det_2_latch;// Detection of second A1 for A1A1A2A2 reg [1:0] pattern_det_3_latch;// Detection of first A2 for A1A1A2A2 // byte de-serializer signals reg [31:0] data_lt_0_sync; reg [31:0] data_lt_0; reg [31:0] data_lt_1; wire [31:0] data_lt_0_sync_aftermux; reg [19:0] rx_data_int; reg rx_we_out; // Channel zero output should all channel rx_we_in of rx_ctrl // PMA signal detect output to PLD wire signal_detect_out; // fifo IO reg [63:0] fifo_data_in; wire [63:0] fifo_data_out; // Data out from the fifo reg rd_enable0; reg rd_enable0p5; reg rd_enable1; reg rd_enable2; reg pld_wr_dis0; reg pld_wr_dis1; reg pld_wr_dis2; reg pld_wr_dis_edge; reg wr_enable0; reg wr_enable0p5; reg wr_enable1; reg wr_enable2; reg rxfifo_en_clk2_0; reg rxfifo_en_clk2_1; reg wr_enable_clk2; // byte ordering signals wire [63:0] din0; reg [63:0] din1; reg [47:0] din1_d; reg [63:0] din2; reg bytordpaten0; reg bytordpaten1; reg bytordpaten2; reg bytordpaten3; wire [1:0] bytordpaten4; reg [1:0] bytordpaten5; reg bytord_valid; reg [3:0] bytordpat_det; reg [3:0] bytordpat_det0; wire bytord_valid0; wire bytord_valid_fifoout; // debug signals wire [2:0] wptr_bin; wire [2:0] rptr_bin; // misc. wire din_6g; wire [1:0] false_rd_error; reg [1:0] dec_data_valid_d0_int; wire [1:0] dec_data_valid_d0; // PIPE wire [4:0] pipe_status_in; wire [4:0] pipe_status_out; wire phystatus; wire phystatus_sync; wire rxvalid; wire [2:0] rxstatus; wire [63:0] pipe_data; wire decode_p2; reg decode_p2_reg; reg decode_p2_reg1; reg phystatus_out_reg; reg phystatus_out_reg1; reg phystatus_gap_filler; reg wa_lock_achieved; reg wa_lock_achieved_s2gx; wire rdwidth_or_auto; wire gen2ngen1_int; reg gen2ngen1_reg; reg gen2ngen1_sync; reg bytord_valid0_d1; //ML 11-19-07 reg bytord_valid0_d2; //ML 01-17-08 //------------------------------------------ // Used for 3G SYNC SM Enabled cases only // K.Kankipati 02/29/2008 //------------------------------------------ wire din_3g_sync_sm_en; assign din_3g_sync_sm_en = ~din_6g & ~rsync_sm_dis ; // signal detect is taken directly from PMA and only buffered here assign signal_detect_out = sigdetni; //--------- always @ (posedge rx_rd_clk or posedge soft_reset_rclk1) begin if (soft_reset_rclk1) begin decode_p2_reg <= #1 1'b0; decode_p2_reg1 <= #1 1'b0; end else begin decode_p2_reg <= #1 decode_p2; decode_p2_reg1 <= #1 decode_p2_reg; end end always @ (posedge rx_rd_clk or posedge soft_reset_rclk1) begin if (soft_reset_rclk1) begin phystatus_out_reg <= #1 1'b0; phystatus_out_reg1 <= #1 1'b0; phystatus_gap_filler <= #1 1'b1; end else begin phystatus_out_reg <= #1 pipe_status_out[0]; phystatus_out_reg1 <= #1 phystatus_out_reg; if ((phystatus_gap_filler == 1'b1) && phystatus_out_reg && ~phystatus_out_reg1) phystatus_gap_filler <= #1 1'b0; end end // ============= // functionality // ============= assign din_6g = rwa_6g_en; assign local_soft_reset = soft_reset | (rrxfifo_urst_en && rxfifo_urst) ; // delay underflow/overflow flags by 2 clks if RX SM is used. This aligns flags and data //assign ovr_undflow_d = (rendec_data_sel_rx)? ovr_undflow : ovr_undflow1; // Error Replacement condition // XAUI or GiGE: RD Error Or Invalid Code // Else: Invalid Code Only assign running_disp = (rinvalid_code_err_only)? invalid_code_delay : disp_err_delay | invalid_code_delay; // bypass FIFO assign rxd = (rrxfifo_dis)? din2[63:0] : fifo_data_out[63:0]; // bypass FIFO assign rxc = (rrxfifo_dis)? {din2[56], din2[40], din2[24], din2[8]} : {fifo_data_out[56], fifo_data_out[40], fifo_data_out[24], fifo_data_out[8]}; // 8b 10b control bits // bypass FIFO assign rxd_9 = (rrxfifo_dis)? {din2[25], din2[9]} : {fifo_data_out[25], fifo_data_out[9]}; // bypass FIFO assign rxd_19 = (rrxfifo_dis)? {din2[57], din2[41]} : {fifo_data_out[57], fifo_data_out[41]}; // bypass FIFO assign bytord_valid_out = (rrxfifo_dis)? bytord_valid0 : bytord_valid_fifoout; // bypass FIFO assign pipe_status_in = {rxstatus_int,rxvalid_int, phystatus_int}; //assign phystatus_sync = (rrxfifo_dis)? pipe_status_in[0]: pipe_status_out[0] | phystatus_gap_filler; assign phystatus = (rrxfifo_dis)? pipe_status_in[0]: pipe_status_out[0]; //assign phystatus = (~decode_p2 && decode_p2_reg1)? 1'b1: phystatus_sync; //assign decode_p2 = (powerdown == 2'b11)? 1'b1: 1'b0; assign rxvalid = (rrxfifo_dis)? pipe_status_in[1]: pipe_status_out[1]; assign rxstatus = (rrxfifo_dis)? pipe_status_in[4:2]: pipe_status_out[4:2]; assign pipe_data = din2; assign wr_enable_out = wr_enable1; assign rd_enable_out = rd_enable1; // pattern detection[0] // In A1A2 mode, tenB_data[8] is A1A2_SIZE always @ (rwa_6g_en or rpmadatawidth or rsync_comp_size or tenb_data or rsync_comp_pat or pattern_det_1_latch or pattern_det_3_latch or pd_16bit_high or pd_20bit_high or pd_32bit_high1 or pd_40bit_high1 or rsync_comp_porn) begin casex ({rwa_6g_en, rpmadatawidth,rsync_comp_size, tenb_data[8]}) // 6G 7-bit pattern detection 6'b11000x: pattern_det_int[0] = (tenb_data[6:0] == rsync_comp_pat[6:0]) || (rsync_comp_porn && (tenb_data[6:0] == ~rsync_comp_pat[6:0])); // 6G 8-bit pattern detection 6'b10001x: pattern_det_int[0] = (tenb_data[7:0] == rsync_comp_pat[7:0]) || (rsync_comp_porn && (tenb_data[7:0] == ~rsync_comp_pat[7:0])); // 6G 10-bit pattern detection 6'b11010x: pattern_det_int[0] = (tenb_data[9:0] == rsync_comp_pat[9:0]) || (rsync_comp_porn && (tenb_data[9:0] == ~rsync_comp_pat[9:0])); // 6G 16-bit pattern detection 6'b10011x: pattern_det_int[0] = ((tenb_data[ 7:0] == rsync_comp_pat[15:8]) || (rsync_comp_porn && (tenb_data[ 7:0] == ~rsync_comp_pat[15:8]))) && pd_16bit_high; // 6G 20-bit pattern detection 6'b11100x: pattern_det_int[0] = ((tenb_data[9:0] == rsync_comp_pat[19:10]) || (rsync_comp_porn && (tenb_data[9:0] == ~rsync_comp_pat[19:10]))) && pd_20bit_high; // 6G 32-bit pattern detection 6'b10101x: pattern_det_int[0] = ((tenb_data[ 7:0] == rsync_comp_pat[31:24]) || (rsync_comp_porn && (tenb_data[ 7:0] == ~rsync_comp_pat[ 31:24]))) && pd_32bit_high1; // 6G 40-bit pattern detection 6'b11110x: pattern_det_int[0] = ((tenb_data[ 9:0] == rsync_comp_pat[39:30]) || (rsync_comp_porn && (tenb_data[ 9:0] == ~rsync_comp_pat[ 39:30]))) && pd_40bit_high1; // 3G 7-bit 6'b01000x: pattern_det_int[0] = (tenb_data[6:0] == rsync_comp_pat[6:0]) || (tenb_data[6:0] == ~rsync_comp_pat[6:0]); // 3G 10-bit 6'b01010x: pattern_det_int[0] = (tenb_data[9:0] == rsync_comp_pat[9:0]) || (tenb_data[9:0] == ~rsync_comp_pat[9:0]); // 3G 16/32-bit default: if (tenb_data[8]) pattern_det_int[0] = (tenb_data[7:0] == rsync_comp_pat[15:8]) && pattern_det_3_latch[0]; else pattern_det_int[0] = (tenb_data[7:0] == rsync_comp_pat[15:8]) && pattern_det_1_latch[0]; endcase end // pattern detection[1] // In A1A2 mode, tenB_data[18] is A1A2_SIZE always @ (rwa_6g_en or rpmadatawidth or rsync_comp_size or tenb_data or rsync_comp_pat or pattern_det_1_latch or pattern_det_3_latch or pd_32bit_low or pd_40bit_low or rsync_comp_porn) begin casex ({rwa_6g_en, rpmadatawidth,rsync_comp_size, tenb_data[18]}) // 6G 7-bit pattern detection 6'b11000x: pattern_det_int[1] = (tenb_data[16:10] == rsync_comp_pat[6:0]) || (rsync_comp_porn && (tenb_data[16:10] == ~rsync_comp_pat[6:0])); // 6G 8-bit pattern detection 6'b10001x: pattern_det_int[1] = (tenb_data[17:10] == rsync_comp_pat[7:0]) || (rsync_comp_porn && (tenb_data[17:10] == ~rsync_comp_pat[7:0])); // 6G 10-bit pattern detection 6'b11010x: pattern_det_int[1] = (tenb_data[19:10] == rsync_comp_pat[9:0]) || (rsync_comp_porn && (tenb_data[19:10] == ~rsync_comp_pat[9:0])); // 6G 16-bit pattern detection 6'b10011x: pattern_det_int[1] = ({tenb_data[17:10],tenb_data[7:0]} == rsync_comp_pat[15:0]) || (rsync_comp_porn && ((tenb_data[ 7: 0] == rsync_comp_pat[ 7:0]) | (tenb_data[ 7: 0] == ~rsync_comp_pat[ 7:0])) && ((tenb_data[17:10] == rsync_comp_pat[15:8]) | (tenb_data[17:10] == ~rsync_comp_pat[15:8]))); // 6G 20-bit pattern detection 6'b11100x: pattern_det_int[1] = (tenb_data[19:0] == rsync_comp_pat[19:0]) || (rsync_comp_porn && ((tenb_data[ 9: 0] == rsync_comp_pat[ 9: 0]) | (tenb_data[ 9: 0] == ~rsync_comp_pat[ 9: 0])) && ((tenb_data[19:10] == rsync_comp_pat[19:10]) | (tenb_data[19:10] == ~rsync_comp_pat[19:10]))); // 6G 32-bit pattern detection 6'b10101x: pattern_det_int[1] = (({tenb_data[17:10],tenb_data[7:0]} == rsync_comp_pat[31:16]) || (rsync_comp_porn && ((tenb_data[ 7: 0] == rsync_comp_pat[23:16]) | (tenb_data[ 7: 0] == ~rsync_comp_pat[23:16])) && ((tenb_data[17:10] == rsync_comp_pat[31:24]) | (tenb_data[17:10] == ~rsync_comp_pat[31:24])))) && pd_32bit_low; // 6G 40-bit pattern detection 6'b11110x: pattern_det_int[1] = ((tenb_data[19:0] == rsync_comp_pat[39:20]) || (rsync_comp_porn && ((tenb_data[ 9: 0] == rsync_comp_pat[29:20]) | (tenb_data[ 9: 0] == ~rsync_comp_pat[29:20])) && ((tenb_data[19:10] == rsync_comp_pat[39:30]) | (tenb_data[19:10] == ~rsync_comp_pat[39:30])))) && pd_40bit_low; // 3G 7-bit pattern detection 6'b01000x: pattern_det_int[1] = (tenb_data[16:10] == rsync_comp_pat[6:0]) || (tenb_data[16:10] == ~rsync_comp_pat[6:0]); // 3G 10-bit pattern detection 6'b01010x: pattern_det_int[1] = (tenb_data[19:10] == rsync_comp_pat[9:0]) || (tenb_data[19:10] == ~rsync_comp_pat[9:0]); // 3G 16/32-bit pattern detection default: if (tenb_data[18]) pattern_det_int[1] = (tenb_data[17:10] == rsync_comp_pat[15:8]) && pattern_det_3_latch[1]; else pattern_det_int[1] = (tenb_data[17:10] == rsync_comp_pat[15:8]) && pattern_det_1_latch[1]; endcase end assign rxd_lpbk = {fifo_data_out[57:48], fifo_data_out[41:32], fifo_data_out[25:16], fifo_data_out[9:0]}; // the first cycle sync_status goes high: // if RD error occurs but not invalid code, it is false RD error because // it is between last un-aligned code and the first aligned code // need to ignore it, else error replacement will replace the first aligned code assign false_rd_error[0] = din_6g && ~rinvalid_code_err_only && ~invalid_code_delay[0] && disp_err_delay[0] && sync_resync_delay[0] && ~sync_resync_delay_1[0]; assign false_rd_error[1] = din_6g && ~rinvalid_code_err_only && ~invalid_code_delay[1] && disp_err_delay[1] && sync_resync_delay[1] && ~sync_resync_delay_1[1]; always @ (endec_rx or rendec_data_sel_rx or rx_data_rs or rx_data_dt or tenb_data or rx_control_rs or rx_control_dt or dec_data_valid_d0 or running_disp or sync_resync_delay or sync_resync_pre or disp_err_delay or disp_val_delay or rsync_sm_dis or pattern_det_int or rautoinsdis or rclkcmpinsertpad or sync_resync_delay_2 or disp_err_delay_2 or disp_val_delay_2 or pattern_det_int_delay_2 or ovr_undflow or ovr_undflow1 or false_rd_error or rrx_pipe_enable or din_3g_sync_sm_en ) begin if (endec_rx) // decoded 8b10b code begin if (rendec_data_sel_rx) // select decoder dout begin //------------------------------------------------------------------------- //sync_resync_d pulled ahead by one clock cycle for 3G SYNC SM enabled cases //K.Kankipati 02/29/2008 //------------------------------------------------------------------------- sync_resync_d = din_3g_sync_sm_en ?sync_resync_pre:sync_resync_delay; //sync_resync_d = sync_resync_delay; disp_err_d = disp_err_delay; disp_val_d = disp_val_delay; ovr_undflow_d = ovr_undflow; // Begin Low byte processing if (dec_data_valid_d0[0] == 1'b0) // initial data begin //rx_data_int[9] = (rsync_sm_dis)? running_disp[0] : 1'b0; // Not error // LMC: 03/26/08 PIPE modes: when 19c replacement occurs, treat as invalid code error // rx_data_int[9] = running_disp[0]; // keep error flag, recommended by PIPE, XAUI/GIGE are ok if(!rsync_sm_dis && !rautoinsdis) // Non-PIPE or PIPE, both use 19C as filler cell begin // LMC: 03/26/08 PIPE modes: when 19c replacement occurs, treat as invalid code error and stuff with EDB instead // rx_data_int[8:0] = 9'h19C; // 9'h19C = /Q/ pattern_det_d[0] = 1'b0; // Not idle // LMC: 03/26/08 PIPE modes: when 19c replacement occurs, treat as invalid code error if (rrx_pipe_enable) begin rx_data_int[9] = 1'b1; rx_data_int[8:0] = 9'h1FE; // 9'h1FE = EDB end else begin rx_data_int[9] = running_disp[0]; // keep error flag rx_data_int[8:0] = 9'h19C; // 9'h19C = /Q/ end end else begin rx_data_int[8:0] = {rx_control_dt[0], rx_data_dt[7:0]}; pattern_det_d[0] = pattern_det_int[0]; // LMC: 04/04/08 For non PIPE modes keep rxd[9] as running_disp rx_data_int[9] = running_disp[0]; // keep error flag end end else // valid data begin rx_data_int[9] = running_disp[0]; pattern_det_d[0] = pattern_det_int[0]; //SYNC SM enabled and error happens if (dec_data_valid_d0[0] && !rautoinsdis && ~rsync_sm_dis && running_disp[0] && ~false_rd_error[0]) // Non-PIPE or PIPE, diff. running_disp rx_data_int[8:0] = (rclkcmpinsertpad)? 9'b111110111 : 9'b111111110; // PCI-E Pad value : PCI-E EDB/other protocols 9'h1FE /E/ else rx_data_int[8:0] = {rx_control_dt[0], rx_data_dt[7:0]}; end // Begin High byte processing if (dec_data_valid_d0[1] == 1'b0) begin //rx_data_int[19] = (rsync_sm_dis)? running_disp[1] : 1'b0; // Not error // LMC: 03/26/08 PIPE modes: when 19c replacement occurs, treat as invalid code error // rx_data_int[19] = running_disp[1]; // keep error flag, recommended by PIPE, XAUI/GIGE are ok if(!rsync_sm_dis && !rautoinsdis) // Non-PIPE or PIPE, both use 19C as filler cell begin // LMC: 03/26/08 PIPE modes: when 19c replacement occurs, treat as invalid code error and stuff with EDB instead // rx_data_int[18:10] = 9'h19C; // 9'h19C = /Q/ pattern_det_d[1] = 1'b0; // Not idle // LMC: 03/26/08 PIPE modes: when 19c replacement occurs, treat as invalid code error if (rrx_pipe_enable) begin rx_data_int[19] = 1'b1; rx_data_int[18:10] = 9'h1FE; // 9'h1FE = EDB end else begin rx_data_int[19] = running_disp[1]; // keep error flag rx_data_int[18:10] = 9'h19C; // 9'h19C = /Q/ end end else begin rx_data_int[18:10] = {rx_control_dt[1], rx_data_dt[15:8]}; pattern_det_d[1] = pattern_det_int[1]; // LMC: 04/04/08 For non PIPE modes keep rxd[9] as running_disp rx_data_int[19] = running_disp[1]; // keep error flag end end else // valid data begin rx_data_int[19] = running_disp[1]; pattern_det_d[1] = pattern_det_int[1]; //SYNC SM enabled and error happens if (dec_data_valid_d0[1] && !rautoinsdis && ~rsync_sm_dis && running_disp[1] && ~false_rd_error[1]) // Non-PIPE or PIPE, diff. running_disp rx_data_int[18:10] = (rclkcmpinsertpad)? 9'b111110111 : 9'b111111110; // PCI-E Pad value : PCI-E EDB/other protocols 9'h1FE = /E/ else rx_data_int[18:10] = {rx_control_dt[1], rx_data_dt[15:8]}; end end else // if (rendec_data_sel_rx) begin // XAUI related sync_resync_d = sync_resync_delay_2; disp_err_d = disp_err_delay_2; disp_val_d = disp_val_delay_2; rx_data_int[8:0] = {rx_control_rs, rx_data_rs[7:0]}; rx_data_int[9] = rx_control_rs & ~(|(rx_data_rs[7:0]^8'hfe)); // /E/ rx_data_int[18:10] = {rx_control_dt[1], rx_data_dt[15:8]}; // same as indv_rx == 1'b1 rx_data_int[19] = running_disp[1]; // same as indv_rx == 1'b1 pattern_det_d = pattern_det_int_delay_2; ovr_undflow_d = ovr_undflow1; end end else // if (endec_rx) // non 8B10B begin //------------------------------------------------------------------------- //sync_resync_d pulled ahead by one clock cycle for 3G SYNC SM enabled cases //K.Kankipati 02/29/2008 //------------------------------------------------------------------------- sync_resync_d = din_3g_sync_sm_en ?sync_resync_pre:sync_resync_delay; //sync_resync_d = sync_resync_delay; disp_err_d = disp_err_delay; disp_val_d = disp_val_delay; rx_data_int = tenb_data; ovr_undflow_d = ovr_undflow; if (!dec_data_valid_d0[0] && !rsync_sm_dis) pattern_det_d[0] = 1'b0; else pattern_det_d[0] = pattern_det_int[0]; if (!dec_data_valid_d0[1] && !rsync_sm_dis) pattern_det_d[1] = 1'b0; else pattern_det_d[1] = pattern_det_int[1]; end end // 3G BO enable fix: 3G sync SM does not output to sync_status or late // 1: // if it is A1A2 type or rsync_sm_dis == 1'b0 (resync_sync, on time), // extend resync_sync until reset // 2: // if it is A1A1A2A2 type (resync_sync, 1 cycle late for BO), // use resync_sync_pre (on time), and extend it until reset // 3: // else (8b10b code), sync_resync_delay is 2 cycles late // use dec_data_valid_pre (2 cycles ahead, on time) reg bo_3g_en; reg bo_3g_en_lt_1; reg bo_3g_en_lt_0; reg bo_3g_en_lt_0_sync; wire bo_en; assign bo_en = (din_6g)? (sync_resync_delay[0] | sync_resync_delay[1]) : // 6G (rsync_sm_dis==1'b0)? dec_data_valid_pre[0] : // 3G sync_sm enabled, advance sync_status 2 clks (rpmadatawidth==1'b0)? sync_resync_pre[0] : // A1A2 or A1A1A2A2, advance resync_sync by 1 clk sync_resync_delay[0]; // other resync_sync, right cycle reg bo_en_d1,bo_en_d2,bo_en_d3,bo_en_d4,bo_en_d5; //always @(posedge rx_wr_clk or posedge soft_reset_wclk1) always @(posedge soft_reset or posedge clk_2) begin if (soft_reset) begin bo_en_d1 <= #1 1'b0; bo_en_d2 <= #1 1'b0; bo_en_d3 <= #1 1'b0; bo_en_d4 <= #1 1'b0; bo_en_d5 <= #1 1'b0; wa_lock_achieved <= #1 1'b0; wa_lock_achieved_s2gx <= #1 1'b0; end else begin bo_en_d1 <= #1 bo_en; bo_en_d2 <= #1 bo_en_d1; bo_en_d3 <= #1 bo_en_d2; bo_en_d4 <= #1 bo_en_d3; bo_en_d5 <= #1 bo_en_d4; if (rbytordplden) begin // Modified by NM on 08/08/08 if ((bytordpaten2 == 1'b1) && (bytordpaten3 == 1'b0)) begin wa_lock_achieved <= #1 1'b1; end else if (bytord_valid0_d1 && !bytord_valid0_d2) //11-19-07 ML changed from bytord_valid_out to (!bytord_valid0 && bytord_valid0_d1) begin wa_lock_achieved <= #1 1'b0; wa_lock_achieved_s2gx <= #1 1'b1; //Assert to signal to design that in s2gx like behavior, do not want to BO again end end else begin //wa_lock_achieved signal is necessary because rcomp_pat is not necessarily equal to rbytordpat if (bo_en == 1'b1 && bo_en_d1 == 1'b0) //Wait until syncstatus/resync_sync asserts begin //signal that occasion with wa_lock_achieved wa_lock_achieved <= #1 1'b1; end else if (bytord_valid0_d1 && !bytord_valid0_d2) //11-19-07 ML changed from bytord_valid_out to (!bytord_valid0 && bytord_valid0_d1) begin wa_lock_achieved <= #1 1'b0; //De-assert this signal once byte ordering has been done wa_lock_achieved_s2gx <= #1 1'b1; //Assert to signal to design that in s2gx like behavior, do not want to BO again end end end end // always @ (posedge soft_reset or posedge clk_2) assign gen2ngen1_int = rindv_rx? gen2ngen1: gen2ngen1_bundle; //************************************ // Synchronization of gen2ngen1 //************************************ always @ (posedge clk_2 or posedge soft_reset) begin if(soft_reset) begin gen2ngen1_reg <= 1'b0; gen2ngen1_sync <= 1'b0; end else begin gen2ngen1_reg <= gen2ngen1_int; gen2ngen1_sync <= gen2ngen1_reg; end end // always @ (posedge clk_2 or posedge soft_reset) assign rdwidth_or_auto = (rdwidth | (rauto_speed_ena & ~rfreq_sel & gen2ngen1_sync)); // Data pipe for xgmii always @(posedge soft_reset or posedge clk_2) begin if (soft_reset) begin data_lt_1 <= #1 32'h00000000; data_lt_0 <= #1 32'h00000000; data_lt_0_sync <= #1 32'h00000000; sync_resync_delay_1 <= #1 2'b00; sync_resync_delay_2 <= #1 2'b00; disp_err_delay_1 <= #1 2'b00; disp_err_delay_2 <= #1 2'b00; disp_val_delay_1 <= #1 2'b00; disp_val_delay_2 <= #1 2'b00; pattern_det_1_latch <= #1 2'b00; // For first A1 match pattern_det_2_latch <= #1 2'b00; // For second A1 match pattern_det_3_latch <= #1 2'b00; // for first A2 match pattern_det_int_delay_1 <= #1 2'b00; pattern_det_int_delay_2 <= #1 2'b00; pd_16bit_high <= #1 1'b0; pd_20bit_high <= #1 1'b0; pd_32bit_low <= #1 1'b0; pd_40bit_low <= #1 1'b0; pd_32bit_high0 <= #1 1'b0; pd_32bit_high1 <= #1 1'b0; pd_40bit_high0 <= #1 1'b0; pd_40bit_high1 <= #1 1'b0; ovr_undflow0 <= #1 4'h0; ovr_undflow1 <= #1 4'h0; bo_3g_en <= #1 1'h0; bo_3g_en_lt_1 <= #1 1'b0; bo_3g_en_lt_0 <= #1 1'b0; bo_3g_en_lt_0_sync <= #1 1'b0; dec_data_valid_d0_int <= #1 2'h0; end else begin //------------------------------------------------------------------------- //sync_resync_d pulled ahead by one clock cycle for 3G SYNC SM enabled cases //K.Kankipati 02/29/2008 //------------------------------------------------------------------------- sync_resync_delay_1 <= #1 (din_3g_sync_sm_en) ?sync_resync_pre:sync_resync_delay; //sync_resync_delay_1 <= #1 sync_resync_delay; sync_resync_delay_2 <= #1 sync_resync_delay_1; disp_err_delay_1 <= #1 disp_err_delay; disp_err_delay_2 <= #1 disp_err_delay_1; disp_val_delay_1 <= #1 disp_val_delay; disp_val_delay_2 <= #1 disp_val_delay_1; ovr_undflow0 <= #1 ovr_undflow; ovr_undflow1 <= #1 ovr_undflow0; dec_data_valid_d0_int <= #1 dec_data_valid; if (bo_3g_en == 1'b0) bo_3g_en <= #1 bo_en; // 6G P.D. on 16-bit pd_16bit_high <= #1 (tenb_data[17:10] == rsync_comp_pat[7:0]) || (rsync_comp_porn && (tenb_data[17:10] == ~rsync_comp_pat[ 7:0])); // 6G P.D. on 20-bit pd_20bit_high <= #1 (tenb_data[19:10] == rsync_comp_pat[9:0]) || (rsync_comp_porn && (tenb_data[19:10] == ~rsync_comp_pat[ 9:0])); // 6G P.D. on 32-bit pd_32bit_low <= #1 ({tenb_data[17:10],tenb_data[7:0]} == rsync_comp_pat[15:0]) || (rsync_comp_porn && ((tenb_data[ 7: 0] == rsync_comp_pat[ 7:0]) | (tenb_data[ 7: 0] == ~rsync_comp_pat[ 7:0])) && ((tenb_data[17:10] == rsync_comp_pat[15:8]) | (tenb_data[17:10] == ~rsync_comp_pat[15:8]))); pd_32bit_high0 <= #1 (tenb_data[17:10] == rsync_comp_pat[ 7:0]) | (rsync_comp_porn && (tenb_data[17:10] == ~rsync_comp_pat[ 7:0])); pd_32bit_high1 <= #1 (({tenb_data[17:10],tenb_data[7:0]} == rsync_comp_pat[23:8]) | (rsync_comp_porn && ((tenb_data[17:10] == rsync_comp_pat[23:16]) | (tenb_data[17:10] ==~rsync_comp_pat[23:16])) && ((tenb_data[ 7: 0] == rsync_comp_pat[15: 8]) | (tenb_data[ 7: 0] ==~rsync_comp_pat[15: 8])))) && pd_32bit_high0; // 6G P.D. on 40-bit pd_40bit_low <= #1 (tenb_data[19:0] == rsync_comp_pat[19:0]) || (rsync_comp_porn && ((tenb_data[ 9: 0] == rsync_comp_pat[ 9: 0]) | (tenb_data[ 9: 0] == ~rsync_comp_pat[ 9: 0])) && ((tenb_data[19:10] == rsync_comp_pat[19:10]) | (tenb_data[19:10] == ~rsync_comp_pat[19:10]))); pd_40bit_high0 <= #1 (tenb_data[19:10] == rsync_comp_pat[ 9:0]) | (rsync_comp_porn && (tenb_data[19:10] == ~rsync_comp_pat[ 9:0])); pd_40bit_high1 <= #1 ((tenb_data[19:0] == rsync_comp_pat[29:10]) | (rsync_comp_porn && ((tenb_data[19:10] == rsync_comp_pat[29:20]) | (tenb_data[19:10] ==~rsync_comp_pat[29:20])) && ((tenb_data[ 9: 0] == rsync_comp_pat[19:10]) | (tenb_data[ 9: 0] ==~rsync_comp_pat[19:10])))) && pd_40bit_high0; // 3G P.D. on A1A2/A1A1A2A2 pattern_det_1_latch[0] <= #1 (tenb_data[7:0] == rsync_comp_pat[7:0]); pattern_det_2_latch[0] <= #1 (pattern_det_1_latch[0]) & (tenb_data[7:0] == rsync_comp_pat[7:0]); pattern_det_3_latch[0] <= #1 (pattern_det_2_latch[0]) & (tenb_data[7:0] == rsync_comp_pat[15:8]); pattern_det_1_latch[1] <= #1 (tenb_data[17:10] == rsync_comp_pat[7:0]); pattern_det_2_latch[1] <= #1 (pattern_det_1_latch[1]) & (tenb_data[17:10] == rsync_comp_pat[7:0]); pattern_det_3_latch[1] <= #1 (pattern_det_2_latch[1]) & (tenb_data[17:10] == rsync_comp_pat[15:8]); pattern_det_int_delay_1 <= #1 pattern_det_int; pattern_det_int_delay_2 <= #1 pattern_det_int_delay_1; if (rdwidth_or_auto && !rx_we_out) begin data_lt_1[7:0] <= #1 rx_data_int[7:0]; data_lt_1[8] <= #1 rx_data_int[8]; data_lt_1[9] <= #1 rx_data_int[9]; data_lt_1[10] <= #1 sync_resync_d[0]; data_lt_1[11] <= #1 disp_err_d[0]; data_lt_1[12] <= #1 pattern_det_d[0]; data_lt_1[13] <= #1 ovr_undflow_d[0]; data_lt_1[14] <= #1 ovr_undflow_d[1]; data_lt_1[15] <= #1 disp_val_d[0]; data_lt_1[23:16]<= #1 rx_data_int[17:10]; data_lt_1[24] <= #1 rx_data_int[18]; data_lt_1[25] <= #1 rx_data_int[19]; data_lt_1[26] <= #1 sync_resync_d[1]; data_lt_1[27] <= #1 disp_err_d[1]; data_lt_1[28] <= #1 pattern_det_d[1]; data_lt_1[29] <= #1 ovr_undflow_d[2]; data_lt_1[30] <= #1 ovr_undflow_d[3]; data_lt_1[31] <= #1 disp_val_d[1]; bo_3g_en_lt_1 <= #1 bo_en | bo_3g_en; end if (rdwidth_or_auto & rx_we_out) begin data_lt_0[7:0] <= #1 rx_data_int[7:0]; data_lt_0[8] <= #1 rx_data_int[8]; data_lt_0[9] <= #1 rx_data_int[9]; data_lt_0[10] <= #1 sync_resync_d[0]; data_lt_0[11] <= #1 disp_err_d[0]; data_lt_0[12] <= #1 pattern_det_d[0]; data_lt_0[13] <= #1 ovr_undflow_d[0]; data_lt_0[14] <= #1 ovr_undflow_d[1]; data_lt_0[15] <= #1 disp_val_d[0]; data_lt_0[23:16]<= #1 rx_data_int[17:10]; data_lt_0[24] <= #1 rx_data_int[18]; data_lt_0[25] <= #1 rx_data_int[19]; data_lt_0[26] <= #1 sync_resync_d[1]; data_lt_0[27] <= #1 disp_err_d[1]; data_lt_0[28] <= #1 pattern_det_d[1]; data_lt_0[29] <= #1 ovr_undflow_d[2]; data_lt_0[30] <= #1 ovr_undflow_d[3]; data_lt_0[31] <= #1 disp_val_d[1]; bo_3g_en_lt_0 <= #1 bo_en | bo_3g_en; end if (!rdwidth_or_auto) begin data_lt_0_sync[7:0] <= #1 rx_data_int[7:0]; data_lt_0_sync[8] <= #1 rx_data_int[8]; data_lt_0_sync[9] <= #1 rx_data_int[9]; data_lt_0_sync[10] <= #1 sync_resync_d[0]; data_lt_0_sync[11] <= #1 disp_err_d[0]; data_lt_0_sync[12] <= #1 pattern_det_d[0]; data_lt_0_sync[13] <= #1 ovr_undflow_d[0]; data_lt_0_sync[14] <= #1 ovr_undflow_d[1]; data_lt_0_sync[15] <= #1 disp_val_d[0]; data_lt_0_sync[23:16]<= #1 rx_data_int[17:10]; data_lt_0_sync[24] <= #1 rx_data_int[18]; data_lt_0_sync[25] <= #1 rx_data_int[19]; data_lt_0_sync[26] <= #1 sync_resync_d[1]; data_lt_0_sync[27] <= #1 disp_err_d[1]; data_lt_0_sync[28] <= #1 pattern_det_d[1]; data_lt_0_sync[29] <= #1 ovr_undflow_d[2]; data_lt_0_sync[30] <= #1 ovr_undflow_d[3]; data_lt_0_sync[31] <= #1 disp_val_d[1]; bo_3g_en_lt_0_sync <= #1 bo_en | bo_3g_en; end else begin data_lt_0_sync <= #1 data_lt_0; bo_3g_en_lt_0_sync <= #1 bo_3g_en_lt_0; end end end //-------------------------------------------------------- //K.Kankipati 02/22/2008 //dec_data_valid_d0 behavior changed only for 3G-10 bit SYNC SM enabled //dec_data_valid_d0 is not a registered version of dec_data_valid //this has been done in comjucntion with pulling sync_status ahead by //one cycle.since sync_status ia head by one cycle we need not use // the delayed version of sync_status // changed (~din_6g & ~rsync_sm_dis) to din_3g_sync_sm_en //-------------------------------------------------------- //assign dec_data_valid_d0 = (~din_6g & ~rsync_sm_dis) ?dec_data_valid:dec_data_valid_d0_int; assign dec_data_valid_d0 = din_3g_sync_sm_en ?dec_data_valid:dec_data_valid_d0_int; //new assign data_lt_0_sync_aftermux = (rrxpcsbypass_en&(!rdwidth))? ({3'd0,pattern_det_d[1],2'd0,rx_data_int[19:10],3'd0,pattern_det_d[1],2'd0,rx_data_int[9:0]}) : data_lt_0_sync; //end new assign local_soft_reset_low = ~local_soft_reset; //assign rxfifo_en = (rrxfifo_urst_en)? ~rxfifo_urst : 1'b1; // generate rx_wr_clk reset always@(posedge local_soft_reset or posedge rx_wr_clk) begin if (local_soft_reset) begin soft_reset_wclk0 <= #1 1'b1; soft_reset_wclk1_b4scan <= #1 1'b1; end else begin soft_reset_wclk0 <= #1 1'b0; soft_reset_wclk1_b4scan <= #1 soft_reset_wclk0; end end assign soft_reset_wclk1 = (scan_mode)? 1'b0 : soft_reset_wclk1_b4scan; // generate pld_rx_clk reset always@(posedge local_soft_reset or posedge rx_rd_clk) begin if (local_soft_reset) begin soft_reset_rclk0 <= #1 1'b1; soft_reset_rclk1_b4scan <= #1 1'b1; end else begin soft_reset_rclk0 <= #1 1'b0; soft_reset_rclk1_b4scan <= #1 soft_reset_rclk0; end end assign soft_reset_rclk1 = (scan_mode)? 1'b0 : soft_reset_rclk1_b4scan; reg [1:0] bo_3g_start; // write enable, fifo data in always @(posedge rx_wr_clk or posedge soft_reset_wclk1) begin if (soft_reset_wclk1) begin fifo_data_in <= #1 64'h0000000000000000; bo_3g_start <= #1 2'h0; pld_wr_dis0 <= #1 1'b0; pld_wr_dis1 <= #1 1'b0; pld_wr_dis2 <= #1 1'b0; pld_wr_dis_edge <= #1 1'b0; wr_enable0 <= #1 1'b0; wr_enable0p5 <= #1 1'b0; wr_enable1 <= #1 1'b0; wr_enable2 <= #1 1'b0; end else begin // add one unit delay to help VCS to order the sampling // sequence between clk_2 and rx_wr_clk //%fifo_data_in <= #1 {data_lt_1, data_lt_0_sync}; fifo_data_in <= #1 {data_lt_1, data_lt_0_sync_aftermux}; bo_3g_start <= #1 {bo_3g_en_lt_1, bo_3g_en_lt_0_sync}; pld_wr_dis0 <= #1 pld_wr_dis; pld_wr_dis1 <= #1 pld_wr_dis0; pld_wr_dis2 <= #1 pld_wr_dis1; pld_wr_dis_edge <= #1 (pld_wr_dis2 != pld_wr_dis1); //wr_enable0 <= rxfifo_en; //wr_enable0 <= 1'b1; wr_enable0 <= #1 ~(rauto_speed_ena & dis_pc_byte); wr_enable0p5 <= #1 wr_enable0; wr_enable1 <= #1 (rrxphfifopldctl_en)? (wr_enable0p5 & !pld_wr_dis_edge) : wr_enable0p5; wr_enable2 <= #1 rmaster_rx ? (rindv_rx ? wr_enable1 : wr_enable_centrl) : (rmaster_up_rx ? wr_enable_quad_up : wr_enable_quad_down); end end // read enable always @(posedge rx_rd_clk or posedge soft_reset_rclk1) begin if (soft_reset_rclk1 == 1'b1) begin rd_enable0 <= #1 1'b0; rd_enable0p5 <= #1 1'b0; rd_enable1 <= #1 1'b0; rd_enable2 <= #1 1'b0; end else begin //rd_enable0 <= rxfifo_en; //rd_enable0 <= 1'b1; rd_enable0 <= #1 ~(rauto_speed_ena & dis_pc_byte); rd_enable0p5 <= #1 rd_enable0; rd_enable1 <= #1 (rrxphfifopldctl_en)? (rd_enable0p5 && pld_re) : rd_enable0p5; rd_enable2 <= #1 rmaster_rx ? (rindv_rx ? rd_enable1 : rd_enable_centrl) : (rmaster_up_rx ? rd_enable_quad_up : rd_enable_quad_down); end end // byte ordering function //assign bytordpaten4 = (rbytorden==2'b00)? 1'b0 : (rbytordplden)? bytordpaten3 : //(din_6g)? (sync_resync_delay[1] | sync_resync_delay[0]) : dec_data_valid[0]; //assign bo_en_rising_detected = (bo_en == 1'b1 && bo_en_d1 == 1'b0) ? 1'b1: //(bo_en_d1 == 1'b1 && bo_en_d2 == 1'b0) ? 1'b1: 1'b0; wire bo_en_rising_detected; wire bo_en_rising_detected_d1; wire bo_en_rising_detected_d2; //ML 11/16/07 Added condition below to hold bo_en_rising_detected one clk_2 cycle longer so that bytordpaten4 will equal 2'b00 and //reset bytord_det0 and retrigger byte ordering. assign bo_en_rising_detected = ((bo_en_d1 == 1'b1 && bo_en_d2 == 1'b0) || (bo_en_d2 == 1'b1 && bo_en_d3 == 1'b0)) ? 1'b1: 1'b0; assign bo_en_rising_detected_d1 = ((bo_en_d2 == 1'b1 && bo_en_d3 == 1'b0) || (bo_en_d3 == 1'b1 && bo_en_d4 == 1'b0)) ? 1'b1: 1'b0; assign bo_en_rising_detected_d2 = ((bo_en_d3 == 1'b1 && bo_en_d4 == 1'b0) || (bo_en_d4 == 1'b1 && bo_en_d5 == 1'b0)) ? 1'b1: 1'b0; assign bytordpaten4 = (bo_en_rising_detected && din_6g == 1'b0 && rbytord_s2gx == 1'b0)? 2'b00: (bo_en_rising_detected_d1 && din_6g == 1'b0 && rbytord_s2gx == 1'b0)? {2'b00}: (bo_en_rising_detected_d2 && din_6g == 1'b0 && rbytord_s2gx == 1'b0)? {bo_3g_start[1],1'b0}: (rbytorden==2'b00)? 2'b00 : (rbytordplden)? {bytordpaten3,bytordpaten3} : (din_6g)? {fifo_data_in[58] | fifo_data_in[42], fifo_data_in[26] | fifo_data_in[10]} : bo_3g_start; /* assign bytordpaten4 = (bo_en_rising_detected && din_6g == 1'b0 && rbytord_s2gx == 1'b0)? 2'b00: (rbytorden==2'b00)? 2'b00 : (rbytordplden)? {bytordpaten3,bytordpaten3} : (din_6g)? {fifo_data_in[58] | fifo_data_in[42], fifo_data_in[26] | fifo_data_in[10]} : bo_3g_start; */ /*assign bytordpaten4 = (rbytorden==2'b00)? 2'b00 : (rbytordplden)? {bytordpaten3,bytordpaten3} : (din_6g)? {fifo_data_in[58] | fifo_data_in[42], fifo_data_in[26] | fifo_data_in[10]} : bo_3g_start; */ reg bytordpat_det_lsb; //%assign din0 = fifo_data_in; assign din0 = (rrxpcsbypass_en)? {data_lt_1, data_lt_0_sync_aftermux} : fifo_data_in; always @(posedge soft_reset_wclk1 or posedge rx_wr_clk) begin if (soft_reset_wclk1) begin bytordpaten0 <= #1 1'b0; bytordpaten1 <= #1 1'b0; bytordpaten2 <= #1 1'b0; bytordpaten3 <= #1 1'b0; bytordpaten5 <= #1 2'h0; //din0 <= 64'h0000000000000000; din1 <= #1 64'h0000000000000000; din1_d <= #1 48'h000000000000; bytord_valid <= #1 1'b0; bytordpat_det0 <= #1 4'h0; //bytord_16bit_high <= 1'b0; bytordpat_det_lsb <= #1 1'b0; bytord_valid0_d1 <= #1 1'b0; bytord_valid0_d2 <= #1 1'b0; //Added 01-25-08 end else begin //din0 <= fifo_data_in; din1 <= #1 din0; din1_d <= #1 din1[63:16]; bytordpaten5 <= #1 bytordpaten4; if (bytordpat_det0 == 4'h0) // only lock to the first pattern detected bytordpat_det0 <= #1 bytordpat_det; else if (bytordpaten4 == 2'b00) bytordpat_det0 <= #1 4'h0; //bytordpaten0 <= (rbytorden==2'b00)? 1'b0 : // (rbytordplden)? bytordplden : sync_resync_delay[0]; bytordpaten0 <= #1 bytordplden; bytordpaten1 <= #1 bytordpaten0; bytordpaten2 <= #1 bytordpaten1; if (bytordpaten1 == 1'b1 && bytordpaten2 == 1'b0) // rising edge of byte ordering cmd bytordpaten3 <= #1 1'b0; else if (bytordpaten3 == 1'b0 && bytordpaten2 == 1'b1) // enable after rising edge bytordpaten3 <= #1 1'b1; if (bytord_valid == 1'b1) //bytord_valid signal asserts for one PLD cycle only bytord_valid <= #1 1'b0; else if (bytordpaten4 == 2'b00) //reset bytord_valid flag if B.O. block is disabled bytord_valid <= #1 1'b0; else if (|bytordpat_det && !bytordpat_det[0]) //bytord_valid signal asserts if syncstatus/resync_sync was asserted //before 11-16-07 ML change: bytord_valid <= #1 (rbytord_s2gx)? 1'b1: (wa_lock_achieved)? 1'b1: 1'b0; //11-16-07 ML, changed assertion of bytord_valid for s2gx-like behavior to be conditional on additional conditions: //1) BO pattern must not have been found in the lower lane (since bytord_valid0 takes care of this) //2) WA must not have been achieved already. If it has been achieved again, do not assert bytord_valid flag // For non s2gx behavior, gate signal with !rbytord_s2gx //bytord_valid <= #1 (rbytord_s2gx && wa_lock_achieved && !wa_lock_achieved_s2gx && !bytordpat_det[0])? 1'b1: (wa_lock_achieved && !rbytord_s2gx)? 1'b1: 1'b0; // bytord_valid <= #1 (rbytord_s2gx && wa_lock_achieved && !wa_lock_achieved_s2gx && !bytordpat_det[0] && !din_6g)? 1'b1: (wa_lock_achieved && !bytordpat_det[0])? 1'b1: 1'b0; bytord_valid <= #1 din_6g? (wa_lock_achieved? 1'b1:1'b0): (rbytord_s2gx? (rbytordplden? (wa_lock_achieved? 1'b1:1'b0): (wa_lock_achieved_s2gx? 1'b0:(wa_lock_achieved? 1'b1:1'b0))):(wa_lock_achieved? 1'b1:1'b0)); else bytord_valid <= #1 1'b0; bytordpat_det_lsb <= #1 bytordpat_det[0]; bytord_valid0_d1 <= #1 bytord_valid0; //used for wa_lock_achieved de-assertion bytord_valid0_d2 <= #1 bytord_valid0_d1; //Added 01-25-08. used for wa_lock_achieved de-assertion end end // byte ordering pattern detection always@(bytordpaten4 or bytordpaten5 or din_6g or rbytord_2sym_en or din0 or din1 or rbytordpat or rsync_comp_pat or rbytorden or rdwidth or rbytordplden or rbytord_6g_mask_en) begin if (bytordpaten4==2'b00) bytordpat_det = 4'h0; else begin case ({rbytord_2sym_en, rbytorden}) 3'b001 : // 3G/6G 8-bit match begin bytordpat_det[3] = (din_6g)? (rdwidth==1'b0)? 1'b0 : (((din0[39:32] != rbytordpat[7:0]) | ~rbytordplden) && (din0[55:48] == rbytordpat[7:0]) && bytordpaten4[1]) : 1'b0; bytordpat_det[2] = (din_6g)? (rdwidth==1'b0)? 1'b0 : (((din0[23:16] != rbytordpat[7:0]) | ~rbytordplden) && (din0[39:32] == rbytordpat[7:0]) && bytordpaten4[1]) : (((din0[ 7: 0] != rbytordpat[7:0]) | ~rbytordplden) && (din0[39:32] == rbytordpat[7:0]) && bytordpaten4[1]) ; bytordpat_det[1] = (din_6g)? (((din0[ 7: 0] != rbytordpat[7:0]) | ~rbytordplden) && (din0[23:16] == rbytordpat[7:0]) && bytordpaten4[0]) : 1'b0; bytordpat_det[0] = (din_6g)? (((din1[55:48] != rbytordpat[7:0]) | ~rbytordplden) && (din0[ 7: 0] == rbytordpat[7:0]) && bytordpaten4[0]) : (((din1[39:32] != rbytordpat[7:0]) | ~rbytordplden) && (din0[ 7: 0] == rbytordpat[7:0]) && bytordpaten4[0]); end 3'b010: // 3G/6G 9-bit match begin bytordpat_det[3] = (din_6g)? (rdwidth==1'b0)? 1'b0 : (((din0[40:32] != rbytordpat[8:0]) | ~rbytordplden) && (din0[56:48] == rbytordpat[8:0]) && bytordpaten4[1]) : 1'b0; bytordpat_det[2] = (din_6g)? (rdwidth==1'b0)? 1'b0 : (((din0[24:16] != rbytordpat[8:0]) | ~rbytordplden) && (din0[40:32] == rbytordpat[8:0]) && bytordpaten4[1]) : (((din0[ 8: 0] != rbytordpat[8:0]) | ~rbytordplden) && (din0[40:32] == rbytordpat[8:0]) && bytordpaten4[1]); bytordpat_det[1] = (din_6g)? (((din0[ 8: 0] != rbytordpat[8:0]) | ~rbytordplden) && (din0[24:16] == rbytordpat[8:0]) && bytordpaten4[0]) : 1'b0; bytordpat_det[0] = (din_6g)? (((din1[56:48] != rbytordpat[8:0]) | ~rbytordplden) && (din0[ 8: 0] == rbytordpat[8:0]) && bytordpaten4[0]) : (((din1[40:32] != rbytordpat[8:0]) | ~rbytordplden) && (din0[ 8: 0] == rbytordpat[8:0]) && bytordpaten4[0]); end 3'b011: // 3G/6G 10-bit match begin bytordpat_det[3] = (din_6g)? (rdwidth==1'b0)? 1'b0 : ((((din0[41:32] != rbytordpat[9:0]) && (din0[41:32] !=~rbytordpat[9:0])) | ~rbytordplden) && ((din0[57:48] == rbytordpat[9:0]) | (din0[57:48] ==~rbytordpat[9:0])) && bytordpaten4[1]) : 1'b0; bytordpat_det[2] = (din_6g)? (rdwidth==1'b0)? 1'b0 : ((((din0[25:16] != rbytordpat[9:0]) && (din0[25:16] !=~rbytordpat[9:0])) | ~rbytordplden) && ((din0[41:32] == rbytordpat[9:0]) | (din0[41:32] ==~rbytordpat[9:0])) && bytordpaten4[1]) : ((((din0[ 9: 0] != rbytordpat[9:0]) && (din0[ 9: 0] !=~rbytordpat[9:0])) | ~rbytordplden) && ((din0[41:32] == rbytordpat[9:0]) | (din0[41:32] ==~rbytordpat[9:0])) && bytordpaten4[1]); bytordpat_det[1] = (din_6g)? ((((din0[ 9: 0] != rbytordpat[9:0]) && (din0[ 9: 0] !=~rbytordpat[9:0])) | ~rbytordplden) && ((din0[25:16] == rbytordpat[9:0]) | (din0[25:16] ==~rbytordpat[9:0])) && bytordpaten4[0]) : 1'b0; bytordpat_det[0] = (din_6g)? ((((din1[57:48] != rbytordpat[9:0]) && (din1[57:48] !=~rbytordpat[9:0])) | ~rbytordplden) && ((din0[ 9: 0] == rbytordpat[9:0]) | (din0[ 9: 0] ==~rbytordpat[9:0])) && bytordpaten4[0]) : ((((din1[41:32] != rbytordpat[9:0]) && (din1[41:32] !=~rbytordpat[9:0])) | ~rbytordplden) && ((din0[ 9: 0] == rbytordpat[9:0]) | (din0[ 9: 0] ==~rbytordpat[9:0])) && bytordpaten4[0]); end 3'b101: // 3G/6G 2 8-bit symbol match, rsync_comp_pat[39:32] is used as rbytordpat[17:10] begin // fix 2 symbol BO for back 2 back patterns and only the 2nd pattern is "sync-status"ed high // this does not occur in 6G because 6G WA always flags the 1st pattern, there is no pattern preceeding // in 3G Sonet, this is not a problem because A1A2 does not occur back to back; // however, the enable signal (sync_sta/resync_sync) goes high on first A2, so advance bytordpaten5 by 1 symbol time // in 3G 10-bit, this may occur. Add sync_status of the 2nd symbol as a condition bytordpat_det[3] = (din_6g)? (rdwidth==1'b0)? 1'b0 : ((din1[55:48] == rbytordpat[7:0]) && ((rbytord_6g_mask_en)? 1'b1 : (din0[7:0] == rbytordpat[17:10]))) : 1'b0; bytordpat_det[2] = (din_6g)? (rdwidth==1'b0)? 1'b0 : ((din1[39:32] == rbytordpat[7:0]) && ((rbytord_6g_mask_en)? 1'b1 : (din1[55:48] == rbytordpat[17:10]))) : ((din1[39:32] == rbytordpat[7:0]) && (din0[7:0] == rbytordpat[17:10]) && bytordpaten4[0]); // advance bytordpaten 1 symbol time, because sync_staus goes high on first A2, not on last A1 bytordpat_det[1] = (din_6g)? (rdwidth==1'b1)? ((din1[23:16] == rbytordpat[7:0]) && ((rbytord_6g_mask_en)? 1'b1 : (din1[39:32] == rbytordpat[17:10]))) : ((din1[23:16] == rbytordpat[7:0]) && ((rbytord_6g_mask_en)? 1'b1 : (din0[7:0] == rbytordpat[17:10]))) : 1'b0; bytordpat_det[0] = (din_6g)? ((din1[ 7: 0] == rbytordpat[7:0]) && ((rbytord_6g_mask_en)? 1'b1 : (din1[23:16] == rbytordpat[17:10]))) : ((din1[ 7: 0] == rbytordpat[7:0]) && (din1[39:32] == rbytordpat[17:10]) && bytordpaten5[1]) ; // advance bytordpaten 1 symbol time, because sync_staus goes high on first A2, not on last A1 end 3'b110: // 3G/6G 2 9-bit symbol match, {rsync_comp_pat[39:32],rbytordpat[9]} is used as rbytordpat[18:10] begin // fix 2 symbol BO for back 2 back patterns and only the 2nd pattern is "sync-status"ed high // this does not occur in 6G because 6G WA always flags the 1st pattern, there is no pattern preceeding // in 3G Sonet, this is not a problem because A1A2 does not occur back to back; // in 3G 10-bit, this may occur. Add sync_status of the 2nd symbol as a condition. sync_status goes high the same cycle in 7/10-bit WA. no need to advance bytordpaten bytordpat_det[3] = (din_6g)? (rdwidth==1'b0)? 1'b0 : ((din1[56:48] == rbytordpat[8:0]) && ((rbytord_6g_mask_en)? 1'b1 : (din0[8:0] == rbytordpat[18:10]))) : 1'b0; bytordpat_det[2] = (din_6g)? (rdwidth==1'b0)? 1'b0 : ((din1[40:32] == rbytordpat[8:0]) && ((rbytord_6g_mask_en)? 1'b1 : (din1[56:48] == rbytordpat[18:10]))) : ((din1[40:32] == rbytordpat[8:0]) && (din0[8:0] == rbytordpat[18:10]) && bytordpaten5[1]); // advance bytordpaten 1 symbol time, because sync_staus goes high on first A2, not on last A1 bytordpat_det[1] = (din_6g)? (rdwidth==1'b1)? ((din1[24:16] == rbytordpat[8:0]) && ((rbytord_6g_mask_en)? 1'b1 : (din1[40:32] == rbytordpat[18:10]))) : ((din1[24:16] == rbytordpat[8:0]) && ((rbytord_6g_mask_en)? 1'b1 : (din0[8:0] == rbytordpat[18:10]))) : 1'b0; bytordpat_det[0] = (din_6g)? ((din1[ 8: 0] == rbytordpat[8:0]) && ((rbytord_6g_mask_en)? 1'b1 : (din1[24:16] == rbytordpat[18:10]))) : ((din1[ 8: 0] == rbytordpat[8:0]) && (din1[40:32] == rbytordpat[18:10]) && bytordpaten5[0]) ; // advance bytordpaten 1 symbol time, because sync_staus goes high on first A2, not on last A1 end 3'b111: // 3G/6G 2 10-bit symbol match, {rsync_comp_pat[39:32],rbytordpat[9]} is used as rbytordpat[18:10] begin bytordpat_det[3] = (din_6g)? (rdwidth==1'b0)? 1'b0 : (((din1[57:48] == rbytordpat[9:0]) | (din1[57:48] == ~rbytordpat[9:0])) && ((rbytord_6g_mask_en)? 1'b1 : ((din0[9:0] == rbytordpat[19:10]) | (din0[9:0] == ~rbytordpat[19:10]))) && bytordpaten4[1]) : 1'b0; bytordpat_det[2] = (din_6g)? (rdwidth==1'b0)? 1'b0 : ((((din1[41:32] == rbytordpat[9:0]) | (din1[41:32] == ~rbytordpat[9:0])) && ((rbytord_6g_mask_en)? 1'b1 : ((din1[57:48] == rbytordpat[19:10])| (din1[57:48] == ~rbytordpat[19:10])))) && bytordpaten4[1]) : (((din1[41:32] == rbytordpat[9:0]) | (din1[41:32] == ~rbytordpat[9:0])) && ((din0[9:0] == rbytordpat[19:10]) | (din0[9:0] == ~rbytordpat[19:10])) && bytordpaten5[1]); // advance bytordpaten 1 symbol time, because sync_staus goes high on first A2, not on last A1 bytordpat_det[1] = (din_6g)? (rdwidth==1'b1)? ((((din1[25:16] == rbytordpat[9:0]) | (din1[25:16] == ~rbytordpat[9:0])) && ((rbytord_6g_mask_en)? 1'b1 : ((din1[41:32] == rbytordpat[19:10]) | (din1[41:32] == ~rbytordpat[19:10])))) && bytordpaten4[0]) : ((((din1[25:16] == rbytordpat[9:0]) | (din1[25:16] == ~rbytordpat[9:0])) && ((rbytord_6g_mask_en)? 1'b1 : ((din0[9:0] == rbytordpat[19:10]) | (din0[9:0] == ~rbytordpat[19:10])))) && bytordpaten4[0]) : 1'b0; bytordpat_det[0] = (din_6g)? ((((din1[ 9: 0] == rbytordpat[9:0]) | (din1[ 9: 0] == ~rbytordpat[9:0])) && ((rbytord_6g_mask_en)? 1'b1 : (din1[25:16] == rbytordpat[19:10]) | ((din1[25:16] == ~rbytordpat[19:10])))) && bytordpaten4[0]) : (((din1[ 9: 0] == rbytordpat[9:0] ) | (din1[ 9: 0] == ~rbytordpat[9:0] )) && ((din1[41:32] == rbytordpat[19:10]) | (din1[41:32] == ~rbytordpat[19:10])) && bytordpaten5[0]) ; // advance bytordpaten 1 symbol time, because sync_staus goes high on first A2, not on last A1 end default: begin bytordpat_det[3] = 1'b0; bytordpat_det[2] = 1'b0; bytordpat_det[1] = 1'b0; bytordpat_det[0] = 1'b0; end endcase end // else begin end // byte ordering data selection always @(din_6g or rdwidth or rbytord_2sym_en or bytordpat_det0 or bytordpat_det or rbytordpadval or din0 or din1 or din1_d) begin case({din_6g,rdwidth,rbytord_2sym_en}) 3'b110 : // 6G 4 symbols per sample, 1 symbol byte ordering if (bytordpat_det0 == 4'h0) casex(bytordpat_det[3:0]) 4'bxx10: din2 = {5'h00,din0[10],rbytordpadval,5'h00,din0[10],rbytordpadval,5'h00,din0[10],rbytordpadval,din0[15:0]}; 4'bx100: din2 = {5'h00,din0[26],rbytordpadval,5'h00,din0[26],rbytordpadval,din0[31:0]}; 4'b1000: din2 = {5'h00,din0[42],rbytordpadval,din0[47:0]}; default: din2 = din0; endcase else casex(bytordpat_det0[3:0]) 4'bxx10: din2 = {din0[15:0],din1[63:16]}; 4'bx100: din2 = {din0[31:0],din1[63:32]}; 4'b1000: din2 = {din0[47:0],din1[63:48]}; default: din2 = din0; endcase 3'b111 : // 6G 4 symbols per sample, 2 symbol byte ordering if (bytordpat_det0 == 4'h0) casex(bytordpat_det[3:0]) 4'bxx10: din2 = {5'h00,din1[10],rbytordpadval,5'h00,din1[10],rbytordpadval,5'h00,din1[10],rbytordpadval,din1[15:0]}; 4'bx100: din2 = {5'h00,din1[26],rbytordpadval,5'h00,din1[26],rbytordpadval,din1[31:0]}; 4'b1000: din2 = {5'h00,din1[42],rbytordpadval,din1[47:0]}; default: din2 = din1; endcase else casex(bytordpat_det0[3:0]) 4'bxx10: din2 = {din1[15:0],din1_d[47: 0]}; // din1_d[47: 0] is [63:16] 4'bx100: din2 = {din1[31:0],din1_d[47:16]}; // din1_d[47:16] is [63:32] 4'b1000: din2 = {din1[47:0],din1_d[47:32]}; // din1_d[47:32] is [63:48] default: din2 = din1; endcase 3'b100: // 6G 2 symbols per sample, 1 symbol byte ordering if (bytordpat_det0[1:0] == 2'h0) casex(bytordpat_det[1:0]) 2'b10: din2 = {16'h0000,16'h0000,5'h00,din0[10],rbytordpadval,din0[15:0]}; default: din2 = din0; endcase else casex(bytordpat_det0[1:0]) 2'b10: din2 = {32'h0, din0[15:0],din1[31:16]}; default: din2 = din0; endcase 3'b101: // 6G 2 symbols per sample, 2 symbol byte ordering if (bytordpat_det0[1:0] == 2'h0) casex(bytordpat_det[1:0]) 2'b10: din2 = {16'h0000,16'h0000,5'h00,din1[10],rbytordpadval,din1[15:0]}; default: din2 = din1; endcase else casex(bytordpat_det0[1:0]) 2'b10: din2 = {32'h0, din1[15:0],din1_d[15: 0]}; // din1_d[15:0] is [31:16] default: din2 = din1; endcase 3'b010: // 3G 2 symbols per sample, 1 symbol byte ordering if (bytordpat_det0[3:0] == 4'h0) casex(bytordpat_det[3:0]) 4'bx100: din2 = {16'h0000,5'h00,din0[10],rbytordpadval,16'h0000,din0[15:0]}; default: din2 = din0; endcase else casex(bytordpat_det0[3:0]) 4'bx100: din2 = {din0[31:0],din1[63:32]}; // din1_d[47:16] is [63:32] default: din2 = din0; endcase 3'b011: // 3G 2 symbols per sample, 2 symbol byte ordering if (bytordpat_det0[3:0] == 4'h0) casex(bytordpat_det[3:0]) 4'bx100: din2 = {16'h0000,5'h00,din1[10],rbytordpadval,16'h0000,din1[15:0]}; default: din2 = din1; endcase else casex(bytordpat_det0[3:0]) 4'bx100: din2 = {din1[31:0],din1_d[47:16]}; // din1_d[47:16] is [63:32] default: din2 = din1; endcase default: // 3G single-width din2 = din0; endcase end // if B.O. pattern is in the LSB, no change, but bytord_valid flag should be advanced by 1 clk // to be aligned with data //bytordvalid0 signal will now also assert for only one cycle so that bytord_flag will follow its behavior //this one cycle assertion is for both syncstatus and resync_sync cases, and is aligned with the first //byte ordered data assign bytord_valid0 = (rbytord_s2gx && !din_6g)? (rbytordplden? ((bytordpat_det_lsb == 1'b1 && bytordpaten4[0]) ? 1'b0: (bytordpaten4[0] && bytordpat_det[0]==1'b1 && wa_lock_achieved == 1'b1)? 1'b1 : bytord_valid): ((bytordpat_det_lsb == 1'b1 && bytordpaten4[0]) ? 1'b0: (bytordpaten4[0] && bytordpat_det[0]==1'b1 && wa_lock_achieved && !wa_lock_achieved_s2gx)? 1'b1 : bytord_valid)): (bytordpat_det_lsb == 1'b1 && bytordpaten4[0]) ? 1'b0: (bytordpaten4[0] && bytordpat_det[0]==1'b1 && wa_lock_achieved == 1'b1)? 1'b1 : bytord_valid; stratixiv_hssi_rx_digis_ph_fifo ph_fifo_rx_1 ( .rst_wclk(soft_reset_wclk1), .rst_rclk(soft_reset_rclk1), .wr_clk(rx_wr_clk), .rd_clk(rx_rd_clk), .en(1'b1), .lowlatency_en(rrxfifo_lowlatency_en), .we(wr_enable2), .re(rd_enable2), .din({pipe_status_in,bytord_valid0,din2[63:0]}), .data_out({pipe_status_out,bytord_valid_fifoout,fifo_data_out[63:0]}), .ph_fifo_full(ph_fifo_full), .ph_fifo_empty(ph_fifo_empty), .wptr_bin(wptr_bin), .rptr_bin(rptr_bin), .rphfifo_regmode_rx(rphfifo_regmode_rx), .rindv_rx(rindv_rx), .rmaster_rx(rmaster_rx), .rmaster_up_rx(rmaster_up_rx), .rauto_speed_ena(rauto_speed_ena), .reset_pc_ptrs(reset_pc_ptrs), .reset_pc_ptrs_centrl(reset_pc_ptrs_centrl), .reset_pc_ptrs_quad_up(reset_pc_ptrs_quad_up), .reset_pc_ptrs_quad_down(reset_pc_ptrs_quad_down), .pcs_wrapback_in(pcs_wrapback_in), .rpcs_wrapback_en(rpcs_wrapback_en), .scan_mode(scan_mode) ); wire error_char_low, error_char_high; assign error_char_high = (fifo_data_out[25:16] == 10'b0001011110) ? 1'b1 : 1'b0; assign error_char_low = (fifo_data_out[ 9: 0] == 10'b0001011110) ? 1'b1 : 1'b0; /** NOTE: Truth table for the 14th and 15th bits - and 30th, 29th (in digital bus numbering it would be 13th, 14th, 29th, 28th bits) Bit 15/30 Bit 14/29 Function ------------------------------------------------------------------------------- 0 0 Everything OK 1 0 Underflow if fifo_data_out1_sync = Error character, else indicates insertion 0 1 Indicates character deletion 1 1 Indicates overflow **/ //assign full = rgenericfifo ? rdfifo_full : //((fifo_data_out[30] & fifo_data_out[29]) | // overflow //(fifo_data_out[14] & fifo_data_out[13])); // overflow // byte de-serializer high/low select always @(posedge clk_2 or posedge soft_reset) begin if (soft_reset) begin rx_we_out <= #1 1'b1; rxfifo_en_clk2_0 <= #1 1'b0; rxfifo_en_clk2_1 <= #1 1'b0; wr_enable_clk2 <= #1 1'b0; end else begin //rxfifo_en_clk2_0 <= rxfifo_en; // rxfifo_en_clk2_0 <= 1'b1; rxfifo_en_clk2_0 <= #1 ~(rauto_speed_ena & dis_pc_byte); rxfifo_en_clk2_1 <= #1 rxfifo_en_clk2_0; if (rxfifo_en_clk2_1 == 1'b0) wr_enable_clk2 <= #1 1'b0; else if (wr_enable_clk2 == 1'b0) wr_enable_clk2 <= #1 wr_enable2; if (wr_enable_clk2 == 1'b1) rx_we_out <= #1 rmaster_rx ? (rindv_rx ? ~rx_we_out : ~rx_we_in_centrl) : (rmaster_up_rx ? ~rx_we_in_quad_up : ~rx_we_in_quad_down); else rx_we_out <= #1 1'b0; end end // synopsys translate_off wire [9:0] dbg_din0_b54_to_b45; wire [9:0] dbg_din0_b39_to_b30; wire [9:0] dbg_din0_b24_to_b15; wire [9:0] dbg_din0_b09_to_b00; wire [9:0] dbg_din1_b54_to_b45; wire [9:0] dbg_din1_b39_to_b30; wire [9:0] dbg_din1_b24_to_b15; wire [9:0] dbg_din1_b09_to_b00; wire [9:0] dbg_din2_b54_to_b45; wire [9:0] dbg_din2_b39_to_b30; wire [9:0] dbg_din2_b24_to_b15; wire [9:0] dbg_din2_b09_to_b00; assign dbg_din0_b54_to_b45 = din0[57:48]; assign dbg_din0_b39_to_b30 = din0[41:32]; assign dbg_din0_b24_to_b15 = din0[25:16]; assign dbg_din0_b09_to_b00 = din0[ 9: 0]; assign dbg_din1_b54_to_b45 = din1[57:48]; assign dbg_din1_b39_to_b30 = din1[41:32]; assign dbg_din1_b24_to_b15 = din1[25:16]; assign dbg_din1_b09_to_b00 = din1[ 9: 0]; assign dbg_din2_b54_to_b45 = din2[57:48]; assign dbg_din2_b39_to_b30 = din2[41:32]; assign dbg_din2_b24_to_b15 = din2[25:16]; assign dbg_din2_b09_to_b00 = din2[ 9: 0]; // synopsys translate_on endmodule // rx_ctrl //IP Functional Simulation Model //VERSION_BEGIN 12.0 cbx_mgl 2012:05:31:20:09:47:SJ cbx_simgen 2012:05:31:20:08:35:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 // Copyright (C) 1991-2012 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // You may only use these simulation model output files for simulation // purposes and expressly not for synthesis or any other purposes (in which // event Altera disclaims all warranties of any kind). //synopsys translate_off //synthesis_resources = lut 99 mux21 139 `timescale 1 ps / 1 ps module stratixiv_hssi_rx_digi_dec_chnl_top ( cascaded_8b10b_en, clk_2, data_in, data_in_valid, dec_ctl, dec_data, dec_data_valid, disp_err_delay, disp_val_delay, invalid_code_delay, ovr_undflow, polinv, r8b10b_dec_ibm_en, renpolinv, rerr_flags_sel, rlb_data, rrxpcsbypass_en, rst, sync_resync_delay, tenb_data) /* synthesis synthesis_clearbox=1 */; input cascaded_8b10b_en; input clk_2; input [31:0] data_in; input [1:0] data_in_valid; output [1:0] dec_ctl; output [15:0] dec_data; output [1:0] dec_data_valid; output [1:0] disp_err_delay; output [1:0] disp_val_delay; output [1:0] invalid_code_delay; output [3:0] ovr_undflow; input polinv; input [1:0] r8b10b_dec_ibm_en; input renpolinv; input rerr_flags_sel; output [19:0] rlb_data; input rrxpcsbypass_en; input rst; output [1:0] sync_resync_delay; output [19:0] tenb_data; reg n0l01O43; reg n0l01O44; reg n0l0li41; reg n0l0li42; reg n0l0lO39; reg n0l0lO40; reg n0li0l35; reg n0li0l36; reg n0li1i37; reg n0li1i38; reg n0liiO33; reg n0liiO34; reg n0liOi31; reg n0liOi32; reg n0ll0l27; reg n0ll0l28; reg n0ll1i29; reg n0ll1i30; reg n0llii25; reg n0llii26; reg n0llll23; reg n0llll24; reg n0llOi21; reg n0llOi22; reg n0lO0l17; reg n0lO0l18; reg n0lO1O19; reg n0lO1O20; reg n0lOiO15; reg n0lOiO16; reg n0lOOO13; reg n0lOOO14; reg n0O00l1; reg n0O00l2; reg n0O01i5; reg n0O01i6; reg n0O01O3; reg n0O01O4; reg n0O10i11; reg n0O10i12; reg n0O1ii10; reg n0O1ii9; reg n0O1ll7; reg n0O1ll8; reg n00O; reg n0Oi; reg ni1i; reg ni1l; reg ni1O; reg niiO; reg nili; reg nilO; reg nill_clk_prev; wire wire_nill_CLRN; reg n00i; reg n00l; reg n01i; reg n01l; reg n01O; reg n0Ol; reg n0OO; reg n10i; reg n10l; reg n10O; reg n11i; reg n11l; reg n11O; reg n1ii; reg n1il; reg n1iO; reg n1li; reg n1ll; reg n1lO; reg n1Oi; reg n1Ol; reg n1OO; reg ni; reg ni0i; reg ni0l; reg ni0O; reg niii; reg niil; reg niOi; reg niOl; reg niOO; reg nl0i; reg nl0O; reg nl1i; reg nl1l; reg nl1O; reg nlO0l; reg nlO0O; reg nlOii; reg nlOil; reg nlOiO; reg nlOli; reg nlOll; reg nlOlO; reg nlOOi; reg nlOOl; reg nlOOO; wire wire_nlO_CLRN; wire wire_n000i_dataout; wire wire_n000l_dataout; wire wire_n000O_dataout; wire wire_n001i_dataout; wire wire_n001l_dataout; wire wire_n001O_dataout; wire wire_n00ii_dataout; wire wire_n00il_dataout; wire wire_n00iO_dataout; wire wire_n00li_dataout; wire wire_n00ll_dataout; wire wire_n00lO_dataout; wire wire_n00Oi_dataout; wire wire_n00OO_dataout; wire wire_n01iO_dataout; wire wire_n01li_dataout; wire wire_n01ll_dataout; wire wire_n01lO_dataout; wire wire_n01Oi_dataout; wire wire_n01Ol_dataout; wire wire_n01OO_dataout; wire wire_n0i_dataout; wire wire_n0i1i_dataout; wire wire_n0i1l_dataout; wire wire_n0ii_dataout; wire wire_n0il_dataout; wire wire_n0iO_dataout; wire wire_n0l_dataout; wire wire_n0li_dataout; wire wire_n0liO_dataout; wire wire_n0ll_dataout; wire wire_n0lli_dataout; wire wire_n0lll_dataout; wire wire_n0llO_dataout; wire wire_n0lO_dataout; wire wire_n0lOi_dataout; wire wire_n0O_dataout; wire wire_n0O0i_dataout; wire wire_n0O0l_dataout; wire wire_n0O0O_dataout; wire wire_n0O1O_dataout; wire wire_n0Oii_dataout; wire wire_n0Oil_dataout; wire wire_n0OiO_dataout; wire wire_n0Oli_dataout; wire wire_n0Oll_dataout; wire wire_n0OlO_dataout; wire wire_n0OOi_dataout; wire wire_n0OOl_dataout; wire wire_n10il_dataout; wire wire_n10iO_dataout; wire wire_n10li_dataout; wire wire_n10ll_dataout; wire wire_n10lO_dataout; wire wire_n111i_dataout; wire wire_n1i_dataout; wire wire_n1i0i_dataout; wire wire_n1i0l_dataout; wire wire_n1i0O_dataout; wire wire_n1i1l_dataout; wire wire_n1i1O_dataout; wire wire_n1iii_dataout; wire wire_n1iil_dataout; wire wire_n1iiO_dataout; wire wire_n1ili_dataout; wire wire_n1ill_dataout; wire wire_n1ilO_dataout; wire wire_n1iOi_dataout; wire wire_n1l_dataout; wire wire_n1l1i_dataout; wire wire_n1l1l_dataout; wire wire_n1l1O_dataout; wire wire_n1O_dataout; wire wire_ni0lOl_dataout; wire wire_ni10i_dataout; wire wire_ni11iO_dataout; wire wire_ni11l_dataout; wire wire_ni11O_dataout; wire wire_nii_dataout; wire wire_nil_dataout; wire wire_niO_dataout; wire wire_niO00l_dataout; wire wire_nl0l_dataout; wire wire_nl0lll_dataout; wire wire_nl110O_dataout; wire wire_nli_dataout; wire wire_nlii_dataout; wire wire_nlil_dataout; wire wire_nliO_dataout; wire wire_nliOO_dataout; wire wire_nll_dataout; wire wire_nll0i_dataout; wire wire_nll0l_dataout; wire wire_nll0O_dataout; wire wire_nll1i_dataout; wire wire_nll1l_dataout; wire wire_nll1O_dataout; wire wire_nlli_dataout; wire wire_nllii_dataout; wire wire_nllil_dataout; wire wire_nlliO_dataout; wire wire_nlll_dataout; wire wire_nllli_dataout; wire wire_nllll_dataout; wire wire_nlllO_dataout; wire wire_nllO_dataout; wire wire_nllOi_dataout; wire wire_nllOl_dataout; wire wire_nllOO_dataout; wire wire_nlO01l_dataout; wire wire_nlO0i_dataout; wire wire_nlO1i_dataout; wire wire_nlO1l_dataout; wire wire_nlO1O_dataout; wire wire_nlOi_dataout; wire wire_nlOl_dataout; wire wire_nlOlil_dataout; wire wire_nlOliO_dataout; wire wire_nlOlli_dataout; wire wire_nlOlll_dataout; wire wire_nlOllO_dataout; wire wire_nlOlOi_dataout; wire wire_nlOlOl_dataout; wire wire_nlOlOO_dataout; wire wire_nlOO_dataout; wire wire_nlOO0i_dataout; wire wire_nlOO0l_dataout; wire wire_nlOO0O_dataout; wire wire_nlOO1i_dataout; wire wire_nlOO1l_dataout; wire wire_nlOO1O_dataout; wire wire_nlOOii_dataout; wire wire_nlOOil_dataout; wire wire_nlOOiO_dataout; wire wire_nlOOli_dataout; wire wire_nlOOll_dataout; wire wire_nlOOlO_dataout; wire wire_nlOOOl_dataout; wire wire_nlOOOO_dataout; wire n00OiO; wire n00Oli; wire n00Oll; wire n00OlO; wire n00OOi; wire n00OOl; wire n00OOO; wire n0i00i; wire n0i00l; wire n0i00O; wire n0i01i; wire n0i01l; wire n0i01O; wire n0i0ii; wire n0i0il; wire n0i0iO; wire n0i0li; wire n0i0ll; wire n0i0lO; wire n0i0Oi; wire n0i0Ol; wire n0i0OO; wire n0i10i; wire n0i10l; wire n0i10O; wire n0i11i; wire n0i11l; wire n0i11O; wire n0i1ii; wire n0i1il; wire n0i1iO; wire n0i1li; wire n0i1ll; wire n0i1lO; wire n0i1Oi; wire n0i1Ol; wire n0i1OO; wire n0ii0i; wire n0ii0l; wire n0ii0O; wire n0ii1i; wire n0ii1l; wire n0ii1O; wire n0iiii; wire n0iiil; wire n0iiiO; wire n0iili; wire n0iill; wire n0iilO; wire n0iiOi; wire n0iiOl; wire n0iiOO; wire n0il0i; wire n0il0l; wire n0il0O; wire n0il1i; wire n0il1l; wire n0il1O; wire n0ilii; wire n0ilil; wire n0iliO; wire n0illi; wire n0illl; wire n0illO; wire n0ilOi; wire n0ilOl; wire n0ilOO; wire n0iO0i; wire n0iO0l; wire n0iO0O; wire n0iO1i; wire n0iO1l; wire n0iO1O; wire n0iOii; wire n0iOil; wire n0iOiO; wire n0iOli; wire n0iOll; wire n0iOlO; wire n0iOOi; wire n0iOOl; wire n0iOOO; wire n0l00l; wire n0l00O; wire n0l01i; wire n0l01l; wire n0l0ii; wire n0l0il; wire n0l0iO; wire n0l0Ol; wire n0l0OO; wire n0l10i; wire n0l10l; wire n0l10O; wire n0l11i; wire n0l11l; wire n0l11O; wire n0l1ii; wire n0l1il; wire n0l1iO; wire n0l1li; wire n0l1ll; wire n0l1lO; wire n0l1Oi; wire n0l1Ol; wire n0l1OO; wire n0li0i; wire n0li1O; wire n0liii; wire n0liil; wire n0lill; wire n0lilO; wire n0liOO; wire n0ll0i; wire n0ll1O; wire n0lliO; wire n0llli; wire n0llOO; wire n0lO1i; wire n0lO1l; wire n0lOii; wire n0lOil; wire n0lOll; wire n0lOlO; wire n0lOOi; wire n0lOOl; wire n0O00i; wire n0O01l; wire n0O10O; wire n0O11l; wire n0O11O; wire n0O1iO; wire n0O1li; wire n0O1Oi; wire n0O1Ol; wire n0O1OO; initial n0l01O43 = 0; always @ ( posedge clk_2) n0l01O43 <= n0l01O44; event n0l01O43_event; initial #1 ->n0l01O43_event; always @(n0l01O43_event) n0l01O43 <= {1{1'b1}}; initial n0l01O44 = 0; always @ ( posedge clk_2) n0l01O44 <= n0l01O43; initial n0l0li41 = 0; always @ ( posedge clk_2) n0l0li41 <= n0l0li42; event n0l0li41_event; initial #1 ->n0l0li41_event; always @(n0l0li41_event) n0l0li41 <= {1{1'b1}}; initial n0l0li42 = 0; always @ ( posedge clk_2) n0l0li42 <= n0l0li41; initial n0l0lO39 = 0; always @ ( posedge clk_2) n0l0lO39 <= n0l0lO40; event n0l0lO39_event; initial #1 ->n0l0lO39_event; always @(n0l0lO39_event) n0l0lO39 <= {1{1'b1}}; initial n0l0lO40 = 0; always @ ( posedge clk_2) n0l0lO40 <= n0l0lO39; initial n0li0l35 = 0; always @ ( posedge clk_2) n0li0l35 <= n0li0l36; event n0li0l35_event; initial #1 ->n0li0l35_event; always @(n0li0l35_event) n0li0l35 <= {1{1'b1}}; initial n0li0l36 = 0; always @ ( posedge clk_2) n0li0l36 <= n0li0l35; initial n0li1i37 = 0; always @ ( posedge clk_2) n0li1i37 <= n0li1i38; event n0li1i37_event; initial #1 ->n0li1i37_event; always @(n0li1i37_event) n0li1i37 <= {1{1'b1}}; initial n0li1i38 = 0; always @ ( posedge clk_2) n0li1i38 <= n0li1i37; initial n0liiO33 = 0; always @ ( posedge clk_2) n0liiO33 <= n0liiO34; event n0liiO33_event; initial #1 ->n0liiO33_event; always @(n0liiO33_event) n0liiO33 <= {1{1'b1}}; initial n0liiO34 = 0; always @ ( posedge clk_2) n0liiO34 <= n0liiO33; initial n0liOi31 = 0; always @ ( posedge clk_2) n0liOi31 <= n0liOi32; event n0liOi31_event; initial #1 ->n0liOi31_event; always @(n0liOi31_event) n0liOi31 <= {1{1'b1}}; initial n0liOi32 = 0; always @ ( posedge clk_2) n0liOi32 <= n0liOi31; initial n0ll0l27 = 0; always @ ( posedge clk_2) n0ll0l27 <= n0ll0l28; event n0ll0l27_event; initial #1 ->n0ll0l27_event; always @(n0ll0l27_event) n0ll0l27 <= {1{1'b1}}; initial n0ll0l28 = 0; always @ ( posedge clk_2) n0ll0l28 <= n0ll0l27; initial n0ll1i29 = 0; always @ ( posedge clk_2) n0ll1i29 <= n0ll1i30; event n0ll1i29_event; initial #1 ->n0ll1i29_event; always @(n0ll1i29_event) n0ll1i29 <= {1{1'b1}}; initial n0ll1i30 = 0; always @ ( posedge clk_2) n0ll1i30 <= n0ll1i29; initial n0llii25 = 0; always @ ( posedge clk_2) n0llii25 <= n0llii26; event n0llii25_event; initial #1 ->n0llii25_event; always @(n0llii25_event) n0llii25 <= {1{1'b1}}; initial n0llii26 = 0; always @ ( posedge clk_2) n0llii26 <= n0llii25; initial n0llll23 = 0; always @ ( posedge clk_2) n0llll23 <= n0llll24; event n0llll23_event; initial #1 ->n0llll23_event; always @(n0llll23_event) n0llll23 <= {1{1'b1}}; initial n0llll24 = 0; always @ ( posedge clk_2) n0llll24 <= n0llll23; initial n0llOi21 = 0; always @ ( posedge clk_2) n0llOi21 <= n0llOi22; event n0llOi21_event; initial #1 ->n0llOi21_event; always @(n0llOi21_event) n0llOi21 <= {1{1'b1}}; initial n0llOi22 = 0; always @ ( posedge clk_2) n0llOi22 <= n0llOi21; initial n0lO0l17 = 0; always @ ( posedge clk_2) n0lO0l17 <= n0lO0l18; event n0lO0l17_event; initial #1 ->n0lO0l17_event; always @(n0lO0l17_event) n0lO0l17 <= {1{1'b1}}; initial n0lO0l18 = 0; always @ ( posedge clk_2) n0lO0l18 <= n0lO0l17; initial n0lO1O19 = 0; always @ ( posedge clk_2) n0lO1O19 <= n0lO1O20; event n0lO1O19_event; initial #1 ->n0lO1O19_event; always @(n0lO1O19_event) n0lO1O19 <= {1{1'b1}}; initial n0lO1O20 = 0; always @ ( posedge clk_2) n0lO1O20 <= n0lO1O19; initial n0lOiO15 = 0; always @ ( posedge clk_2) n0lOiO15 <= n0lOiO16; event n0lOiO15_event; initial #1 ->n0lOiO15_event; always @(n0lOiO15_event) n0lOiO15 <= {1{1'b1}}; initial n0lOiO16 = 0; always @ ( posedge clk_2) n0lOiO16 <= n0lOiO15; initial n0lOOO13 = 0; always @ ( posedge clk_2) n0lOOO13 <= n0lOOO14; event n0lOOO13_event; initial #1 ->n0lOOO13_event; always @(n0lOOO13_event) n0lOOO13 <= {1{1'b1}}; initial n0lOOO14 = 0; always @ ( posedge clk_2) n0lOOO14 <= n0lOOO13; initial n0O00l1 = 0; always @ ( posedge clk_2) n0O00l1 <= n0O00l2; event n0O00l1_event; initial #1 ->n0O00l1_event; always @(n0O00l1_event) n0O00l1 <= {1{1'b1}}; initial n0O00l2 = 0; always @ ( posedge clk_2) n0O00l2 <= n0O00l1; initial n0O01i5 = 0; always @ ( posedge clk_2) n0O01i5 <= n0O01i6; event n0O01i5_event; initial #1 ->n0O01i5_event; always @(n0O01i5_event) n0O01i5 <= {1{1'b1}}; initial n0O01i6 = 0; always @ ( posedge clk_2) n0O01i6 <= n0O01i5; initial n0O01O3 = 0; always @ ( posedge clk_2) n0O01O3 <= n0O01O4; event n0O01O3_event; initial #1 ->n0O01O3_event; always @(n0O01O3_event) n0O01O3 <= {1{1'b1}}; initial n0O01O4 = 0; always @ ( posedge clk_2) n0O01O4 <= n0O01O3; initial n0O10i11 = 0; always @ ( posedge clk_2) n0O10i11 <= n0O10i12; event n0O10i11_event; initial #1 ->n0O10i11_event; always @(n0O10i11_event) n0O10i11 <= {1{1'b1}}; initial n0O10i12 = 0; always @ ( posedge clk_2) n0O10i12 <= n0O10i11; initial n0O1ii10 = 0; always @ ( posedge clk_2) n0O1ii10 <= n0O1ii9; initial n0O1ii9 = 0; always @ ( posedge clk_2) n0O1ii9 <= n0O1ii10; event n0O1ii9_event; initial #1 ->n0O1ii9_event; always @(n0O1ii9_event) n0O1ii9 <= {1{1'b1}}; initial n0O1ll7 = 0; always @ ( posedge clk_2) n0O1ll7 <= n0O1ll8; event n0O1ll7_event; initial #1 ->n0O1ll7_event; always @(n0O1ll7_event) n0O1ll7 <= {1{1'b1}}; initial n0O1ll8 = 0; always @ ( posedge clk_2) n0O1ll8 <= n0O1ll7; initial begin n00O = 0; n0Oi = 0; ni1i = 0; ni1l = 0; ni1O = 0; niiO = 0; nili = 0; nilO = 0; end always @ (clk_2 or rst or wire_nill_CLRN) begin if (rst == 1'b1) begin n00O <= 1; n0Oi <= 1; ni1i <= 1; ni1l <= 1; ni1O <= 1; niiO <= 1; nili <= 1; nilO <= 1; end else if (wire_nill_CLRN == 1'b0) begin n00O <= 0; n0Oi <= 0; ni1i <= 0; ni1l <= 0; ni1O <= 0; niiO <= 0; nili <= 0; nilO <= 0; end else if (clk_2 != nill_clk_prev && clk_2 == 1'b1) begin n00O <= (n0l01l | (n0l01i & n0l1OO)); n0Oi <= ((n0O1OO | (n0O1Ol & n0O1Oi)) | (~ (n0O1ll8 ^ n0O1ll7))); ni1i <= wire_nlOllO_dataout; ni1l <= wire_nlOlll_dataout; ni1O <= wire_nlOlli_dataout; niiO <= wire_n01Oi_dataout; nili <= wire_n01lO_dataout; nilO <= wire_n01ll_dataout; end nill_clk_prev <= clk_2; end assign wire_nill_CLRN = (n0O01i6 ^ n0O01i5); event n00O_event; event n0Oi_event; event ni1i_event; event ni1l_event; event ni1O_event; event niiO_event; event nili_event; event nilO_event; initial #1 ->n00O_event; initial #1 ->n0Oi_event; initial #1 ->ni1i_event; initial #1 ->ni1l_event; initial #1 ->ni1O_event; initial #1 ->niiO_event; initial #1 ->nili_event; initial #1 ->nilO_event; always @(n00O_event) n00O <= 1; always @(n0Oi_event) n0Oi <= 1; always @(ni1i_event) ni1i <= 1; always @(ni1l_event) ni1l <= 1; always @(ni1O_event) ni1O <= 1; always @(niiO_event) niiO <= 1; always @(nili_event) nili <= 1; always @(nilO_event) nilO <= 1; initial begin n00i = 0; n00l = 0; n01i = 0; n01l = 0; n01O = 0; n0Ol = 0; n0OO = 0; n10i = 0; n10l = 0; n10O = 0; n11i = 0; n11l = 0; n11O = 0; n1ii = 0; n1il = 0; n1iO = 0; n1li = 0; n1ll = 0; n1lO = 0; n1Oi = 0; n1Ol = 0; n1OO = 0; ni = 0; ni0i = 0; ni0l = 0; ni0O = 0; niii = 0; niil = 0; niOi = 0; niOl = 0; niOO = 0; nl0i = 0; nl0O = 0; nl1i = 0; nl1l = 0; nl1O = 0; nlO0l = 0; nlO0O = 0; nlOii = 0; nlOil = 0; nlOiO = 0; nlOli = 0; nlOll = 0; nlOlO = 0; nlOOi = 0; nlOOl = 0; nlOOO = 0; end always @ ( posedge clk_2 or negedge wire_nlO_CLRN) begin if (wire_nlO_CLRN == 1'b0) begin n00i <= 0; n00l <= 0; n01i <= 0; n01l <= 0; n01O <= 0; n0Ol <= 0; n0OO <= 0; n10i <= 0; n10l <= 0; n10O <= 0; n11i <= 0; n11l <= 0; n11O <= 0; n1ii <= 0; n1il <= 0; n1iO <= 0; n1li <= 0; n1ll <= 0; n1lO <= 0; n1Oi <= 0; n1Ol <= 0; n1OO <= 0; ni <= 0; ni0i <= 0; ni0l <= 0; ni0O <= 0; niii <= 0; niil <= 0; niOi <= 0; niOl <= 0; niOO <= 0; nl0i <= 0; nl0O <= 0; nl1i <= 0; nl1l <= 0; nl1O <= 0; nlO0l <= 0; nlO0O <= 0; nlOii <= 0; nlOil <= 0; nlOiO <= 0; nlOli <= 0; nlOll <= 0; nlOlO <= 0; nlOOi <= 0; nlOOl <= 0; nlOOO <= 0; end else begin n00i <= wire_n0lO_dataout; n00l <= wire_n0ll_dataout; n01i <= wire_n0ii_dataout; n01l <= wire_n0li_dataout; n01O <= wire_n0iO_dataout; n0Ol <= data_in_valid[0]; n0OO <= data_in_valid[1]; n10i <= data_in[21]; n10l <= data_in[22]; n10O <= data_in[23]; n11i <= data_in[18]; n11l <= data_in[19]; n11O <= data_in[20]; n1ii <= data_in[24]; n1il <= data_in[25]; n1iO <= data_in[14]; n1li <= data_in[15]; n1ll <= data_in[30]; n1lO <= data_in[31]; n1Oi <= data_in[11]; n1Ol <= data_in[27]; n1OO <= wire_n0il_dataout; ni <= (renpolinv & polinv); ni0i <= wire_nlOliO_dataout; ni0l <= wire_nlOlil_dataout; ni0O <= wire_n1i0i_dataout; niii <= wire_n1i1O_dataout; niil <= wire_n1i1l_dataout; niOi <= wire_n01li_dataout; niOl <= wire_n01iO_dataout; niOO <= wire_n0O0l_dataout; nl0i <= ni; nl0O <= data_in[0]; nl1i <= wire_n0O0i_dataout; nl1l <= wire_n0O1O_dataout; nl1O <= wire_nl0l_dataout; nlO0l <= data_in[1]; nlO0O <= data_in[2]; nlOii <= data_in[3]; nlOil <= data_in[4]; nlOiO <= data_in[5]; nlOli <= data_in[6]; nlOll <= data_in[7]; nlOlO <= data_in[8]; nlOOi <= data_in[9]; nlOOl <= data_in[16]; nlOOO <= data_in[17]; end end assign wire_nlO_CLRN = ((n0O01O4 ^ n0O01O3) & (~ rst)); assign wire_n000i_dataout = (n0l1li === 1'b1) ? wire_n00OO_dataout : wire_n00iO_dataout; assign wire_n000l_dataout = (n0l1li === 1'b1) ? wire_n0i1i_dataout : wire_n00li_dataout; assign wire_n000O_dataout = (n0l1li === 1'b1) ? wire_n0i1i_dataout : wire_n00ll_dataout; and(wire_n001i_dataout, wire_n000O_dataout, ~(n0l1ll)); and(wire_n001l_dataout, wire_n00ii_dataout, ~(n0l1ll)); and(wire_n001O_dataout, wire_n00il_dataout, ~(n0l1ll)); assign wire_n00ii_dataout = (n0l1li === 1'b1) ? wire_n0i1i_dataout : wire_n00lO_dataout; assign wire_n00il_dataout = (n0l1li === 1'b1) ? wire_n0i1i_dataout : wire_n00Oi_dataout; assign wire_n00iO_dataout = (n0l10O === 1'b1) ? wire_nlll_dataout : n0O1Ol; assign wire_n00li_dataout = (n0l10O === 1'b1) ? wire_nlli_dataout : (~ wire_n0lli_dataout); assign wire_n00ll_dataout = (n0l10O === 1'b1) ? wire_nliO_dataout : (~ wire_n0lll_dataout); assign wire_n00lO_dataout = (n0l10O === 1'b1) ? wire_nlil_dataout : (~ wire_n0llO_dataout); assign wire_n00Oi_dataout = (n0l10O === 1'b1) ? wire_nlii_dataout : (~ wire_n0lOi_dataout); and(wire_n00OO_dataout, wire_n0i1l_dataout, ~(n0l10l)); or(wire_n01iO_dataout, wire_n01Ol_dataout, n0O1OO); or(wire_n01li_dataout, wire_n01OO_dataout, n0O1OO); or(wire_n01ll_dataout, wire_n001i_dataout, n0O1OO); and(wire_n01lO_dataout, wire_n001l_dataout, ~(n0O1OO)); and(wire_n01Oi_dataout, wire_n001O_dataout, ~(n0O1OO)); or(wire_n01Ol_dataout, wire_n000i_dataout, n0l1ll); or(wire_n01OO_dataout, wire_n000l_dataout, n0l1ll); assign wire_n0i_dataout = (nl0i === 1'b1) ? (~ data_in[2]) : data_in[2]; and(wire_n0i1i_dataout, (~ n0l10i), ~(n0l10l)); or(wire_n0i1l_dataout, (~ (wire_n0llO_dataout & (~ wire_n0lll_dataout))), n0l10i); assign wire_n0ii_dataout = (n0O00i === 1'b1) ? wire_nl0lll_dataout : data_in[29]; assign wire_n0il_dataout = (n0O00i === 1'b1) ? wire_ni0lOl_dataout : data_in[13]; assign wire_n0iO_dataout = (n0O00i === 1'b1) ? (((((((~ wire_ni0lOl_dataout) & ((((((((((n0ll0i | n0ll1O) | (~ (n0ll1i30 ^ n0ll1i29))) | n0liOO) | (~ (n0liOi32 ^ n0liOi31))) | (n0lilO & n0lill)) | (~ (n0liiO34 ^ n0liiO33))) | (n0liil & n0liii)) | (~ (n0li0l36 ^ n0li0l35))) | n0li0i) | n0li1O)) & (n0li1i38 ^ n0li1i37)) | ((wire_ni0lOl_dataout & (n0l0OO | ((~ wire_nlli_dataout) & n0l0Ol))) & (n0l0lO40 ^ n0l0lO39))) | (~ (n0l0li42 ^ n0l0li41))) | ((n0l0iO | (n0l0il | n0l0ii)) & (~ wire_nl110O_dataout))) | ((n0l00O | (wire_nlOl_dataout & ((wire_nlOi_dataout & n0l00l) & (n0l01O44 ^ n0l01O43)))) & wire_nl110O_dataout)) : data_in[28]; assign wire_n0l_dataout = (nl0i === 1'b1) ? (~ data_in[3]) : data_in[3]; assign wire_n0li_dataout = (n0O00i === 1'b1) ? (((((((~ nl1O) & ((((((((((n0O1li | n0O1iO) | (~ (n0O1ii10 ^ n0O1ii9))) | n0O10O) | (~ (n0O10i12 ^ n0O10i11))) | (n0O11O & n0O11l)) | (~ (n0lOOO14 ^ n0lOOO13))) | (n0lOOl & n0lOOi)) | n0lOlO) | n0lOll) | (~ (n0lOiO16 ^ n0lOiO15)))) | ((nl1O & ((n0lOil | ((~ wire_n0l_dataout) & n0lOii)) | (~ (n0lO0l18 ^ n0lO0l17)))) & (n0lO1O20 ^ n0lO1O19))) | (((n0lO1l | (n0lO1i | n0llOO)) & (~ wire_ni11iO_dataout)) & (n0llOi22 ^ n0llOi21))) | (~ (n0llll24 ^ n0llll23))) | (((n0llli | (wire_niO_dataout & (wire_nil_dataout & n0lliO))) | (~ (n0llii26 ^ n0llii25))) & wire_ni11iO_dataout)) | (~ (n0ll0l28 ^ n0ll0l27))) : data_in[12]; assign wire_n0liO_dataout = (wire_nllO_dataout === 1'b1) ? wire_nlll_dataout : (~ wire_nlll_dataout); assign wire_n0ll_dataout = (n0O00i === 1'b1) ? (~ wire_nlO01l_dataout) : data_in[26]; assign wire_n0lli_dataout = (wire_nllO_dataout === 1'b1) ? wire_nlli_dataout : (~ wire_nlli_dataout); assign wire_n0lll_dataout = (wire_nllO_dataout === 1'b1) ? wire_nliO_dataout : (~ wire_nliO_dataout); assign wire_n0llO_dataout = (wire_nllO_dataout === 1'b1) ? wire_nlil_dataout : (~ wire_nlil_dataout); assign wire_n0lO_dataout = (n0O00i === 1'b1) ? (~ wire_niO00l_dataout) : data_in[10]; assign wire_n0lOi_dataout = (wire_nllO_dataout === 1'b1) ? wire_nlii_dataout : (~ wire_nlii_dataout); assign wire_n0O_dataout = (nl0i === 1'b1) ? (~ data_in[4]) : data_in[4]; and(wire_n0O0i_dataout, wire_n0Oii_dataout, ~(n0l1lO)); and(wire_n0O0l_dataout, wire_n0Oil_dataout, ~(n0l1lO)); or(wire_n0O0O_dataout, wire_n0OiO_dataout, n0O1Oi); and(wire_n0O1O_dataout, wire_n0O0O_dataout, ~(n0l1lO)); or(wire_n0Oii_dataout, wire_n0Oli_dataout, n0O1Oi); or(wire_n0Oil_dataout, wire_n0Oll_dataout, n0O1Oi); assign wire_n0OiO_dataout = ((~ n0l1Ol) === 1'b1) ? wire_ni11l_dataout : wire_n0OlO_dataout; assign wire_n0Oli_dataout = ((~ n0l1Ol) === 1'b1) ? wire_ni11O_dataout : wire_n0OOi_dataout; assign wire_n0Oll_dataout = ((~ n0l1Ol) === 1'b1) ? wire_ni10i_dataout : wire_n0OOl_dataout; assign wire_n0OlO_dataout = (n0l1Oi === 1'b1) ? (~ wire_nlOO_dataout) : wire_nlOO_dataout; assign wire_n0OOi_dataout = (n0l1Oi === 1'b1) ? (~ wire_nlOl_dataout) : wire_nlOl_dataout; assign wire_n0OOl_dataout = (n0l1Oi === 1'b1) ? (~ wire_nlOi_dataout) : wire_nlOi_dataout; assign wire_n10il_dataout = (wire_nii_dataout === 1'b1) ? wire_n0O_dataout : (~ wire_n0O_dataout); assign wire_n10iO_dataout = (wire_nii_dataout === 1'b1) ? wire_n0l_dataout : (~ wire_n0l_dataout); assign wire_n10li_dataout = (wire_nii_dataout === 1'b1) ? wire_n0i_dataout : (~ wire_n0i_dataout); assign wire_n10ll_dataout = (wire_nii_dataout === 1'b1) ? wire_n1O_dataout : (~ wire_n1O_dataout); assign wire_n10lO_dataout = (wire_nii_dataout === 1'b1) ? wire_n1l_dataout : (~ wire_n1l_dataout); or(wire_n111i_dataout, (~ (wire_n10ll_dataout & (~ wire_n10li_dataout))), n0iOii); assign wire_n1i_dataout = (nl0i === 1'b1) ? (~ data_in[25]) : data_in[25]; and(wire_n1i0i_dataout, wire_n1iii_dataout, ~(n0iOOO)); or(wire_n1i0l_dataout, wire_n1iil_dataout, n0l1OO); or(wire_n1i0O_dataout, wire_n1iiO_dataout, n0l1OO); and(wire_n1i1l_dataout, wire_n1i0l_dataout, ~(n0iOOO)); and(wire_n1i1O_dataout, wire_n1i0O_dataout, ~(n0iOOO)); or(wire_n1iii_dataout, wire_n1ili_dataout, n0l1OO); assign wire_n1iil_dataout = ((~ n0l11l) === 1'b1) ? wire_n1l1i_dataout : wire_n1ill_dataout; assign wire_n1iiO_dataout = ((~ n0l11l) === 1'b1) ? wire_n1l1l_dataout : wire_n1ilO_dataout; assign wire_n1ili_dataout = ((~ n0l11l) === 1'b1) ? wire_n1l1O_dataout : wire_n1iOi_dataout; assign wire_n1ill_dataout = (n0l11i === 1'b1) ? (~ wire_nli_dataout) : wire_nli_dataout; assign wire_n1ilO_dataout = (n0l11i === 1'b1) ? (~ wire_niO_dataout) : wire_niO_dataout; assign wire_n1iOi_dataout = (n0l11i === 1'b1) ? (~ wire_nil_dataout) : wire_nil_dataout; assign wire_n1l_dataout = (nl0i === 1'b1) ? (~ data_in[0]) : data_in[0]; assign wire_n1l1i_dataout = (wire_nll_dataout === 1'b1) ? (~ wire_nli_dataout) : wire_nli_dataout; assign wire_n1l1l_dataout = (wire_nll_dataout === 1'b1) ? (~ wire_niO_dataout) : wire_niO_dataout; assign wire_n1l1O_dataout = (wire_nll_dataout === 1'b1) ? (~ wire_nil_dataout) : wire_nil_dataout; assign wire_n1O_dataout = (nl0i === 1'b1) ? (~ data_in[1]) : data_in[1]; assign wire_ni0lOl_dataout = (((wire_niO_dataout ^ wire_nil_dataout) & n0lliO) === 1'b1) ? wire_ni11iO_dataout : (n0llli | n0lO1l); assign wire_ni10i_dataout = (wire_n1i_dataout === 1'b1) ? (~ wire_nlOi_dataout) : wire_nlOi_dataout; assign wire_ni11iO_dataout = (((((~ wire_n0l_dataout) & n00OOi) | (wire_n0l_dataout & n0lOii)) | (n0O11O & n0lOOi)) === 1'b1) ? nl1O : (n0lOil | n0lOll); assign wire_ni11l_dataout = (wire_n1i_dataout === 1'b1) ? (~ wire_nlOO_dataout) : wire_nlOO_dataout; assign wire_ni11O_dataout = (wire_n1i_dataout === 1'b1) ? (~ wire_nlOl_dataout) : wire_nlOl_dataout; assign wire_nii_dataout = (nl0i === 1'b1) ? (~ data_in[5]) : data_in[5]; assign wire_nil_dataout = (nl0i === 1'b1) ? (~ data_in[6]) : data_in[6]; assign wire_niO_dataout = (nl0i === 1'b1) ? (~ data_in[7]) : data_in[7]; assign wire_niO00l_dataout = (((~ r8b10b_dec_ibm_en[0]) & (~ r8b10b_dec_ibm_en[1])) === 1'b1) ? ((~ ((n0i01O | (n0i01l | n0i01i)) | (n0lOlO | (n0O1iO | (n0O1li | n0O10O))))) & (~ (((n0i1OO | n0llOO) | ((~ (((n0i1Ol | n0i1Oi) | (wire_nii_dataout & ((~ wire_n0O_dataout) & n0lOOl))) | ((~ wire_nii_dataout) & (wire_n0O_dataout & n0i1lO)))) & ((~ n0i1ll) & (((~ wire_nil_dataout) & n0i1li) | (wire_nil_dataout & n0lO1i))))) | ((((~ wire_nll_dataout) & n0i1li) | (wire_nll_dataout & n0lO1i)) & (n0i1Oi | (n0i1Ol | n0i1ll)))))) : (~ ((((((((((((((n0i0Ol | n0i0Oi) | ((~ wire_nii_dataout) & ((~ wire_n0O_dataout) & n0i0lO))) | (wire_nii_dataout & (wire_n0O_dataout & n0i0ll))) | ((wire_nll_dataout & (wire_nli_dataout & (wire_niO_dataout & wire_nil_dataout))) | ((~ wire_nll_dataout) & ((~ wire_nli_dataout) & ((~ wire_niO_dataout) & (~ wire_nil_dataout)))))) | ((~ wire_nli_dataout) & ((~ wire_niO_dataout) & ((~ wire_nil_dataout) & ((~ wire_nii_dataout) & (~ wire_n0O_dataout)))))) | (wire_nli_dataout & (wire_niO_dataout & (wire_nil_dataout & (wire_nii_dataout & wire_n0O_dataout))))) | ((~ wire_nll_dataout) & ((~ wire_nli_dataout) & ((~ wire_niO_dataout) & n0i0li)))) | (wire_nll_dataout & (wire_nli_dataout & (wire_niO_dataout & n0i0iO)))) | ((((~ wire_nll_dataout) & ((~ wire_nli_dataout) & ((~ wire_niO_dataout) & wire_nii_dataout))) | (wire_nll_dataout & (wire_nli_dataout & (wire_niO_dataout & (~ wire_nii_dataout))))) & (~ n0i0il))) | (n0i0il & ((wire_nli_dataout & n0i0ii) | ((~ wire_nli_dataout) & n0i00O)))) | (((~ wire_nll_dataout) & ((~ wire_nli_dataout) & ((~ wire_niO_dataout) & n0i0iO))) & (~ n0i0ll))) | ((wire_nll_dataout & (wire_nli_dataout & (wire_niO_dataout & n0i0li))) & (~ n0i0lO))) | (r8b10b_dec_ibm_en[1] & ((((((~ wire_nii_dataout) & ((~ wire_n0O_dataout) & n0i00l)) | n0i0Oi) | (((~ wire_nii_dataout) | (~ wire_n0O_dataout)) & n0i0lO)) | ((~ wire_nii_dataout) & ((~ wire_n0O_dataout) & (~ wire_n0l_dataout)))) & ((n0i00O | (n0i00O & n0i00i)) | (n0i00i & ((~ wire_niO_dataout) | (~ wire_nil_dataout))))))) | (r8b10b_dec_ibm_en[1] & (((((wire_nii_dataout & (wire_n0O_dataout & n0i00l)) | n0i0Ol) | ((wire_nii_dataout | wire_n0O_dataout) & n0i0ll)) | (wire_nii_dataout & (wire_n0O_dataout & wire_n0l_dataout))) & ((n0i0ii | (n0i0ii & (wire_nll_dataout | wire_nli_dataout))) | ((wire_nll_dataout & wire_nli_dataout) & (wire_niO_dataout | wire_nil_dataout))))))); assign wire_nl0l_dataout = (cascaded_8b10b_en === 1'b1) ? wire_nl0lll_dataout : wire_ni0lOl_dataout; assign wire_nl0lll_dataout = (((wire_nlOl_dataout ^ wire_nlOi_dataout) & n0l00l) === 1'b1) ? wire_nl110O_dataout : (n0l00O | n0l0iO); assign wire_nl110O_dataout = (((((~ wire_nlli_dataout) & n0ii0i) | (wire_nlli_dataout & n0l0Ol)) | (n0lilO & n0liii)) === 1'b1) ? wire_ni0lOl_dataout : (n0l0OO | n0li1O); assign wire_nli_dataout = (nl0i === 1'b1) ? (~ data_in[8]) : data_in[8]; assign wire_nlii_dataout = (nl0i === 1'b1) ? (~ data_in[16]) : data_in[16]; assign wire_nlil_dataout = (nl0i === 1'b1) ? (~ data_in[17]) : data_in[17]; assign wire_nliO_dataout = (nl0i === 1'b1) ? (~ data_in[18]) : data_in[18]; assign wire_nliOO_dataout = (rrxpcsbypass_en === 1'b1) ? data_in[0] : nl0O; assign wire_nll_dataout = (nl0i === 1'b1) ? (~ data_in[9]) : data_in[9]; assign wire_nll0i_dataout = (rrxpcsbypass_en === 1'b1) ? data_in[4] : nlOil; assign wire_nll0l_dataout = (rrxpcsbypass_en === 1'b1) ? data_in[5] : nlOiO; assign wire_nll0O_dataout = (rrxpcsbypass_en === 1'b1) ? data_in[6] : nlOli; assign wire_nll1i_dataout = (rrxpcsbypass_en === 1'b1) ? data_in[1] : nlO0l; assign wire_nll1l_dataout = (rrxpcsbypass_en === 1'b1) ? data_in[2] : nlO0O; assign wire_nll1O_dataout = (rrxpcsbypass_en === 1'b1) ? data_in[3] : nlOii; assign wire_nlli_dataout = (nl0i === 1'b1) ? (~ data_in[19]) : data_in[19]; assign wire_nllii_dataout = (rrxpcsbypass_en === 1'b1) ? data_in[7] : nlOll; assign wire_nllil_dataout = (rrxpcsbypass_en === 1'b1) ? data_in[8] : nlOlO; assign wire_nlliO_dataout = (rrxpcsbypass_en === 1'b1) ? data_in[9] : nlOOi; assign wire_nlll_dataout = (nl0i === 1'b1) ? (~ data_in[20]) : data_in[20]; assign wire_nllli_dataout = (rrxpcsbypass_en === 1'b1) ? data_in[16] : nlOOl; assign wire_nllll_dataout = (rrxpcsbypass_en === 1'b1) ? data_in[17] : nlOOO; assign wire_nlllO_dataout = (rrxpcsbypass_en === 1'b1) ? data_in[18] : n11i; assign wire_nllO_dataout = (nl0i === 1'b1) ? (~ data_in[21]) : data_in[21]; assign wire_nllOi_dataout = (rrxpcsbypass_en === 1'b1) ? data_in[19] : n11l; assign wire_nllOl_dataout = (rrxpcsbypass_en === 1'b1) ? data_in[20] : n11O; assign wire_nllOO_dataout = (rrxpcsbypass_en === 1'b1) ? data_in[21] : n10i; assign wire_nlO01l_dataout = (((~ r8b10b_dec_ibm_en[0]) & (~ r8b10b_dec_ibm_en[1])) === 1'b1) ? ((~ ((n0iliO | (n0ilil | n0ilii)) | (n0li0i | (n0ll1O | (n0ll0i | n0liOO))))) & (~ (((n0il0O | n0l0ii) | ((~ (((n0il0l | n0il0i) | (wire_nllO_dataout & ((~ wire_nlll_dataout) & n0liil))) | ((~ wire_nllO_dataout) & (wire_nlll_dataout & n0il1O)))) & ((~ n0il1l) & (((~ wire_nlOi_dataout) & n0il1i) | (wire_nlOi_dataout & n0l0il))))) | ((((~ wire_n1i_dataout) & n0il1i) | (wire_n1i_dataout & n0l0il)) & (n0il0i | (n0il0l | n0il1l)))))) : (~ ((((((((((((((n0iO0l | n0iO0i) | ((~ wire_nllO_dataout) & ((~ wire_nlll_dataout) & n0iO1O))) | (wire_nllO_dataout & (wire_nlll_dataout & n0iO1l))) | ((wire_n1i_dataout & (wire_nlOO_dataout & (wire_nlOl_dataout & wire_nlOi_dataout))) | ((~ wire_n1i_dataout) & ((~ wire_nlOO_dataout) & ((~ wire_nlOl_dataout) & (~ wire_nlOi_dataout)))))) | ((~ wire_nlOO_dataout) & ((~ wire_nlOl_dataout) & ((~ wire_nlOi_dataout) & ((~ wire_nllO_dataout) & (~ wire_nlll_dataout)))))) | (wire_nlOO_dataout & (wire_nlOl_dataout & (wire_nlOi_dataout & (wire_nllO_dataout & wire_nlll_dataout))))) | ((~ wire_n1i_dataout) & ((~ wire_nlOO_dataout) & ((~ wire_nlOl_dataout) & n0iO1i)))) | (wire_n1i_dataout & (wire_nlOO_dataout & (wire_nlOl_dataout & n0ilOO)))) | ((((~ wire_n1i_dataout) & ((~ wire_nlOO_dataout) & ((~ wire_nlOl_dataout) & wire_nllO_dataout))) | (wire_n1i_dataout & (wire_nlOO_dataout & (wire_nlOl_dataout & (~ wire_nllO_dataout))))) & (~ n0ilOl))) | (n0ilOl & ((wire_nlOO_dataout & n0ilOi) | ((~ wire_nlOO_dataout) & n0illO)))) | (((~ wire_n1i_dataout) & ((~ wire_nlOO_dataout) & ((~ wire_nlOl_dataout) & n0ilOO))) & (~ n0iO1l))) | ((wire_n1i_dataout & (wire_nlOO_dataout & (wire_nlOl_dataout & n0iO1i))) & (~ n0iO1O))) | (r8b10b_dec_ibm_en[1] & ((((((~ wire_nllO_dataout) & ((~ wire_nlll_dataout) & n0illl)) | n0iO0i) | (((~ wire_nllO_dataout) | (~ wire_nlll_dataout)) & n0iO1O)) | ((~ wire_nllO_dataout) & ((~ wire_nlll_dataout) & (~ wire_nlli_dataout)))) & ((n0illO | (n0illO & n0illi)) | (n0illi & ((~ wire_nlOl_dataout ) | (~ wire_nlOi_dataout))))))) | (r8b10b_dec_ibm_en[1] & (((((wire_nllO_dataout & (wire_nlll_dataout & n0illl)) | n0iO0l) | ((wire_nllO_dataout | wire_nlll_dataout) & n0iO1l)) | (wire_nllO_dataout & (wire_nlll_dataout & wire_nlli_dataout))) & ((n0ilOi | (n0ilOi & (wire_n1i_dataout | wire_nlOO_dataout))) | ((wire_n1i_dataout & wire_nlOO_dataout) & (wire_nlOl_dataout | wire_nlOi_dataout))))))); assign wire_nlO0i_dataout = (rrxpcsbypass_en === 1'b1) ? data_in[25] : n1il; assign wire_nlO1i_dataout = (rrxpcsbypass_en === 1'b1) ? data_in[22] : n10l; assign wire_nlO1l_dataout = (rrxpcsbypass_en === 1'b1) ? data_in[23] : n10O; assign wire_nlO1O_dataout = (rrxpcsbypass_en === 1'b1) ? data_in[24] : n1ii; assign wire_nlOi_dataout = (nl0i === 1'b1) ? (~ data_in[22]) : data_in[22]; assign wire_nlOl_dataout = (nl0i === 1'b1) ? (~ data_in[23]) : data_in[23]; or(wire_nlOlil_dataout, wire_nlOlOi_dataout, n0l01l); or(wire_nlOliO_dataout, wire_nlOlOl_dataout, n0l01l); or(wire_nlOlli_dataout, wire_nlOlOO_dataout, n0l01l); and(wire_nlOlll_dataout, wire_nlOO1i_dataout, ~(n0l01l)); and(wire_nlOllO_dataout, wire_nlOO1l_dataout, ~(n0l01l)); or(wire_nlOlOi_dataout, wire_nlOO1O_dataout, n0iOOl); or(wire_nlOlOl_dataout, wire_nlOO0i_dataout, n0iOOl); and(wire_nlOlOO_dataout, wire_nlOO0l_dataout, ~(n0iOOl)); assign wire_nlOO_dataout = (nl0i === 1'b1) ? (~ data_in[24]) : data_in[24]; assign wire_nlOO0i_dataout = (n0iOOi === 1'b1) ? wire_nlOOOO_dataout : wire_nlOOiO_dataout; assign wire_nlOO0l_dataout = (n0iOOi === 1'b1) ? wire_nlOOOO_dataout : wire_nlOOli_dataout; assign wire_nlOO0O_dataout = (n0iOOi === 1'b1) ? wire_nlOOOO_dataout : wire_nlOOll_dataout; and(wire_nlOO1i_dataout, wire_nlOO0O_dataout, ~(n0iOOl)); and(wire_nlOO1l_dataout, wire_nlOOii_dataout, ~(n0iOOl)); assign wire_nlOO1O_dataout = (n0iOOi === 1'b1) ? wire_nlOOOl_dataout : wire_nlOOil_dataout; assign wire_nlOOii_dataout = (n0iOOi === 1'b1) ? wire_nlOOOO_dataout : wire_nlOOlO_dataout; assign wire_nlOOil_dataout = (n0iOiO === 1'b1) ? wire_n0O_dataout : n0l01i; assign wire_nlOOiO_dataout = (n0iOiO === 1'b1) ? wire_n0l_dataout : (~ wire_n10iO_dataout); assign wire_nlOOli_dataout = (n0iOiO === 1'b1) ? wire_n0i_dataout : (~ wire_n10li_dataout); assign wire_nlOOll_dataout = (n0iOiO === 1'b1) ? wire_n1O_dataout : (~ wire_n10ll_dataout); assign wire_nlOOlO_dataout = (n0iOiO === 1'b1) ? wire_n1l_dataout : (~ wire_n10lO_dataout); and(wire_nlOOOl_dataout, wire_n111i_dataout, ~(n0iOil)); and(wire_nlOOOO_dataout, (~ n0iOii), ~(n0iOil)); assign dec_ctl = {n0Oi, n00O}, dec_data = {nl1l, nl1i, niOO, niOl, niOi, nilO, nili, niiO, niil, niii, ni0O, ni0l, ni0i, ni1O, ni1l, ni1i}, dec_data_valid = {n0OO, n0Ol}, disp_err_delay = {n01O, n01l}, disp_val_delay = {n01i, n1OO}, invalid_code_delay = {n00l, n00i}, n00OiO = (wire_n1O_dataout & wire_n1l_dataout), n00Oli = ((~ wire_n1O_dataout) & (~ wire_n1l_dataout)), n00Oll = (wire_n1O_dataout & (~ wire_n1l_dataout)), n00OlO = ((~ wire_n1O_dataout) & wire_n1l_dataout), n00OOi = (n0lOOl & n00OOO), n00OOl = ((~ wire_n0l_dataout) & ((~ wire_n0i_dataout) & ((~ wire_n1O_dataout) & (~ wire_n1l_dataout)))), n00OOO = (wire_nii_dataout & wire_n0O_dataout), n0i00i = ((~ wire_nll_dataout) & (~ wire_nli_dataout)), n0i00l = (((((((~ wire_n0l_dataout) & ((~ wire_n0i_dataout) & (wire_n1O_dataout & wire_n1l_dataout))) | ((~ wire_n0l_dataout) & (wire_n0i_dataout & n0i1iO))) | ((~ wire_n0l_dataout) & (wire_n0i_dataout & n0i1il))) | (wire_n0l_dataout & ((~ wire_n0i_dataout) & n0i1iO))) | (wire_n0l_dataout & ((~ wire_n0i_dataout) & n0i1il))) | (wire_n0l_dataout & (wire_n0i_dataout & ((~ wire_n1O_dataout) & (~ wire_n1l_dataout))))), n0i00O = ((~ wire_niO_dataout) & (~ wire_nil_dataout)), n0i01i = (n0i11i & n0lOOi), n0i01l = ((n0i11i & n00OOO) | (n0i1lO & n00OOO)), n0i01O = (n0i11i & n0O11l), n0i0ii = (wire_niO_dataout & wire_nil_dataout), n0i0il = ((wire_nii_dataout & (wire_n0O_dataout & (wire_n0l_dataout & wire_n0i_dataout))) | ((~ wire_nii_dataout) & ((~ wire_n0O_dataout) & ((~ wire_n0l_dataout) & (~ wire_n0i_dataout))))), n0i0iO = ((~ wire_nii_dataout) & wire_n0O_dataout), n0i0li = (wire_nii_dataout & (~ wire_n0O_dataout)), n0i0ll = (((((~ wire_n0l_dataout) & (wire_n0i_dataout & n0i10O)) | (wire_n0l_dataout & ((~ wire_n0i_dataout) & n0i10O))) | (wire_n0l_dataout & (wire_n0i_dataout & ((~ wire_n1O_dataout) & wire_n1l_dataout)))) | (wire_n0l_dataout & (wire_n0i_dataout & (wire_n1O_dataout & (~ wire_n1l_dataout))))), n0i0lO = (((((~ wire_n0l_dataout) & ((~ wire_n0i_dataout) & ((~ wire_n1O_dataout) & wire_n1l_dataout))) | ((~ wire_n0l_dataout) & ((~ wire_n0i_dataout) & (wire_n1O_dataout & (~ wire_n1l_dataout))))) | ((~ wire_n0l_dataout) & (wire_n0i_dataout & n0i1ii))) | (wire_n0l_dataout & ((~ wire_n0i_dataout) & n0i1ii))), n0i0Oi = ((~ wire_n0l_dataout) & ((~ wire_n0i_dataout) & ((~ wire_n1O_dataout) & (~ wire_n1l_dataout)))), n0i0Ol = (wire_n0l_dataout & (wire_n0i_dataout & (wire_n1O_dataout & wire_n1l_dataout))), n0i0OO = (wire_nlil_dataout & wire_nlii_dataout), n0i10i = (wire_niO_dataout & (~ wire_nil_dataout)), n0i10l = ((~ wire_niO_dataout) & wire_nil_dataout), n0i10O = (wire_n1O_dataout & wire_n1l_dataout), n0i11i = (wire_n0l_dataout & (wire_n0i_dataout & (wire_n1O_dataout & wire_n1l_dataout))), n0i11l = (wire_niO_dataout & wire_nil_dataout), n0i11O = ((~ wire_niO_dataout) & (~ wire_nil_dataout)), n0i1ii = ((~ wire_n1O_dataout) & (~ wire_n1l_dataout)), n0i1il = (wire_n1O_dataout & (~ wire_n1l_dataout)), n0i1iO = ((~ wire_n1O_dataout) & wire_n1l_dataout), n0i1li = (((((~ wire_nll_dataout) & (wire_nli_dataout & n0i11l)) | (wire_nll_dataout & ((~ wire_nli_dataout) & n0i11l))) | (wire_nll_dataout & (wire_nli_dataout & ((~ wire_niO_dataout) & wire_nil_dataout)))) | (wire_nll_dataout & (wire_nli_dataout & (wire_niO_dataout & (~ wire_nil_dataout))))), n0i1ll = (((~ wire_ni11iO_dataout) & n00OOO) | (wire_ni11iO_dataout & n0O11l)), n0i1lO = (((((~ wire_n0l_dataout) & (wire_n0i_dataout & n00OiO)) | (wire_n0l_dataout & ((~ wire_n0i_dataout) & n00OiO))) | (wire_n0l_dataout & (wire_n0i_dataout & ((~ wire_n1O_dataout) & wire_n1l_dataout)))) | (wire_n0l_dataout & (wire_n0i_dataout & (wire_n1O_dataout & (~ wire_n1l_dataout))))), n0i1Oi = ((~ wire_nii_dataout) & ((~ wire_n0O_dataout) & ((~ wire_n0l_dataout) & ((~ wire_n0i_dataout) & (wire_n1O_dataout & wire_n1l_dataout))))), n0i1Ol = (wire_nii_dataout & (wire_n0O_dataout & (wire_n0l_dataout & (wire_n0i_dataout & ((~ wire_n1O_dataout) & (~ wire_n1l_dataout)))))), n0i1OO = (wire_nll_dataout & (wire_nli_dataout & (wire_niO_dataout & wire_nil_dataout))), n0ii0i = (n0liil & n0ii0O), n0ii0l = ((~ wire_nlli_dataout) & ((~ wire_nliO_dataout) & ((~ wire_nlil_dataout) & (~ wire_nlii_dataout)))), n0ii0O = (wire_nllO_dataout & wire_nlll_dataout), n0ii1i = ((~ wire_nlil_dataout) & (~ wire_nlii_dataout)), n0ii1l = (wire_nlil_dataout & (~ wire_nlii_dataout)), n0ii1O = ((~ wire_nlil_dataout) & wire_nlii_dataout), n0iiii = (wire_nlli_dataout & (wire_nliO_dataout & (wire_nlil_dataout & wire_nlii_dataout))), n0iiil = (wire_nlOl_dataout & wire_nlOi_dataout), n0iiiO = ((~ wire_nlOl_dataout) & (~ wire_nlOi_dataout)), n0iili = (wire_nlOl_dataout & (~ wire_nlOi_dataout)), n0iill = ((~ wire_nlOl_dataout) & wire_nlOi_dataout), n0iilO = (wire_nlil_dataout & wire_nlii_dataout), n0iiOi = ((~ wire_nlil_dataout) & (~ wire_nlii_dataout)), n0iiOl = (wire_nlil_dataout & (~ wire_nlii_dataout)), n0iiOO = ((~ wire_nlil_dataout) & wire_nlii_dataout), n0il0i = ((~ wire_nllO_dataout) & ((~ wire_nlll_dataout) & ((~ wire_nlli_dataout) & ((~ wire_nliO_dataout) & (wire_nlil_dataout & wire_nlii_dataout))))), n0il0l = (wire_nllO_dataout & (wire_nlll_dataout & (wire_nlli_dataout & (wire_nliO_dataout & ((~ wire_nlil_dataout) & (~ wire_nlii_dataout)))))), n0il0O = (wire_n1i_dataout & (wire_nlOO_dataout & (wire_nlOl_dataout & wire_nlOi_dataout))), n0il1i = (((((~ wire_n1i_dataout) & (wire_nlOO_dataout & n0iiil)) | (wire_n1i_dataout & ((~ wire_nlOO_dataout) & n0iiil))) | (wire_n1i_dataout & (wire_nlOO_dataout & ((~ wire_nlOl_dataout) & wire_nlOi_dataout)))) | (wire_n1i_dataout & (wire_nlOO_dataout & (wire_nlOl_dataout & (~ wire_nlOi_dataout))))), n0il1l = (((~ wire_nl110O_dataout) & n0ii0O) | (wire_nl110O_dataout & n0lill)), n0il1O = (((((~ wire_nlli_dataout) & (wire_nliO_dataout & n0i0OO)) | (wire_nlli_dataout & ((~ wire_nliO_dataout) & n0i0OO))) | (wire_nlli_dataout & (wire_nliO_dataout & ((~ wire_nlil_dataout) & wire_nlii_dataout)))) | (wire_nlli_dataout & (wire_nliO_dataout & (wire_nlil_dataout & (~ wire_nlii_dataout))))), n0ilii = (n0iiii & n0liii), n0ilil = ((n0iiii & n0ii0O) | (n0il1O & n0ii0O)), n0iliO = (n0iiii & n0lill), n0illi = ((~ wire_n1i_dataout) & (~ wire_nlOO_dataout)), n0illl = (((((((~ wire_nlli_dataout) & ((~ wire_nliO_dataout) & (wire_nlil_dataout & wire_nlii_dataout))) | ((~ wire_nlli_dataout) & (wire_nliO_dataout & n0iiOO))) | ((~ wire_nlli_dataout) & (wire_nliO_dataout & n0iiOl))) | (wire_nlli_dataout & ((~ wire_nliO_dataout) & n0iiOO))) | (wire_nlli_dataout & ((~ wire_nliO_dataout) & n0iiOl))) | (wire_nlli_dataout & (wire_nliO_dataout & ((~ wire_nlil_dataout) & (~ wire_nlii_dataout))))), n0illO = ((~ wire_nlOl_dataout) & (~ wire_nlOi_dataout)), n0ilOi = (wire_nlOl_dataout & wire_nlOi_dataout), n0ilOl = ((wire_nllO_dataout & (wire_nlll_dataout & (wire_nlli_dataout & wire_nliO_dataout))) | ((~ wire_nllO_dataout) & ((~ wire_nlll_dataout) & ((~ wire_nlli_dataout) & (~ wire_nliO_dataout))))), n0ilOO = ((~ wire_nllO_dataout) & wire_nlll_dataout), n0iO0i = ((~ wire_nlli_dataout) & ((~ wire_nliO_dataout) & ((~ wire_nlil_dataout) & (~ wire_nlii_dataout)))), n0iO0l = (wire_nlli_dataout & (wire_nliO_dataout & (wire_nlil_dataout & wire_nlii_dataout))), n0iO0O = ((~ wire_n10lO_dataout) & (~ wire_n10ll_dataout)), n0iO1i = (wire_nllO_dataout & (~ wire_nlll_dataout)), n0iO1l = (((((~ wire_nlli_dataout) & (wire_nliO_dataout & n0iilO)) | (wire_nlli_dataout & ((~ wire_nliO_dataout) & n0iilO))) | (wire_nlli_dataout & (wire_nliO_dataout & ((~ wire_nlil_dataout) & wire_nlii_dataout)))) | (wire_nlli_dataout & (wire_nliO_dataout & (wire_nlil_dataout & (~ wire_nlii_dataout))))), n0iO1O = (((((~ wire_nlli_dataout) & ((~ wire_nliO_dataout) & ((~ wire_nlil_dataout) & wire_nlii_dataout))) | ((~ wire_nlli_dataout) & ((~ wire_nliO_dataout) & (wire_nlil_dataout & (~ wire_nlii_dataout))))) | ((~ wire_nlli_dataout) & (wire_nliO_dataout & n0iiOi))) | (wire_nlli_dataout & ((~ wire_nliO_dataout) & n0iiOi))), n0iOii = (wire_n10ll_dataout & wire_n10li_dataout), n0iOil = ((~ wire_n10ll_dataout) & (~ wire_n10li_dataout)), n0iOiO = ((((~ wire_n10il_dataout) & (((((((~ wire_n10iO_dataout) & ((~ wire_n10li_dataout) & (wire_n10lO_dataout & wire_n10ll_dataout))) | ((~ wire_n10iO_dataout) & (wire_n10li_dataout & n0iOlO))) | ((~ wire_n10iO_dataout) & (wire_n10li_dataout & n0iOll))) | (wire_n10iO_dataout & ((~ wire_n10li_dataout) & n0iOlO))) | (wire_n10iO_dataout & ((~ wire_n10li_dataout) & n0iOll))) | (wire_n10iO_dataout & (wire_n10li_dataout & ((~ wire_n10lO_dataout) & (~ wire_n10ll_dataout)))))) | (wire_n10il_dataout & n0iOli)) & (wire_n10li_dataout | (wire_n10lO_dataout | wire_n10ll_dataout))), n0iOli = (((((~ wire_n10iO_dataout) & ((~ wire_n10li_dataout) & (wire_n10lO_dataout & (~ wire_n10ll_dataout)))) | ((~ wire_n10iO_dataout) & ((~ wire_n10li_dataout) & ((~ wire_n10lO_dataout) & wire_n10ll_dataout)))) | ((~ wire_n10iO_dataout) & (wire_n10li_dataout & n0iO0O))) | (wire_n10iO_dataout & ((~ wire_n10li_dataout) & n0iO0O))), n0iOll = ((~ wire_n10lO_dataout) & wire_n10ll_dataout), n0iOlO = (wire_n10lO_dataout & (~ wire_n10ll_dataout)), n0iOOi = (wire_n10il_dataout & ((wire_n10lO_dataout ^ wire_n10ll_dataout) & (wire_n10li_dataout ^ wire_n10iO_dataout))), n0iOOl = (wire_n10il_dataout & ((~ wire_n10iO_dataout) & ((~ wire_n10li_dataout) & (wire_n10lO_dataout & wire_n10ll_dataout)))), n0iOOO = (((~ wire_n1l1O_dataout) & wire_n1l1l_dataout) & (~ wire_n1l1i_dataout)), n0l00l = (((((((~ wire_n1i_dataout) & ((~ wire_nlOO_dataout) & (wire_nlOl_dataout & wire_nlOi_dataout))) | ((~ wire_n1i_dataout) & (wire_nlOO_dataout & n0iill))) | ((~ wire_n1i_dataout) & (wire_nlOO_dataout & n0iili))) | (wire_n1i_dataout & ((~ wire_nlOO_dataout) & n0iill))) | (wire_n1i_dataout & ((~ wire_nlOO_dataout) & n0iili))) | (wire_n1i_dataout & (wire_nlOO_dataout & ((~ wire_nlOl_dataout) & (~ wire_nlOi_dataout))))), n0l00O = (n0il1i | n0il0O), n0l01i = ((~ wire_n10il_dataout) & n0iOli), n0l01l = (wire_n10il_dataout & (wire_n10iO_dataout & (wire_n10li_dataout & ((~ wire_n10lO_dataout) & (~ wire_n10ll_dataout))))), n0l0ii = ((~ wire_n1i_dataout) & ((~ wire_nlOO_dataout) & ((~ wire_nlOl_dataout) & (~ wire_nlOi_dataout)))), n0l0il = (((((~ wire_n1i_dataout) & ((~ wire_nlOO_dataout) & ((~ wire_nlOl_dataout) & wire_nlOi_dataout))) | ((~ wire_n1i_dataout) & ((~ wire_nlOO_dataout) & (wire_nlOl_dataout & (~ wire_nlOi_dataout))))) | ((~ wire_n1i_dataout) & (wire_nlOO_dataout & n0iiiO))) | (wire_n1i_dataout & ((~ wire_nlOO_dataout) & n0iiiO))), n0l0iO = ((~ wire_nlOl_dataout) & ((~ wire_nlOi_dataout) & n0l00l)), n0l0Ol = (n0il1O & n0lill), n0l0OO = ((((n0ilil | (n0lilO & n0ii0O)) | (n0il1O & n0liii)) | n0ilii) | n0iliO), n0l10i = (wire_n0llO_dataout & wire_n0lll_dataout), n0l10l = ((~ wire_n0llO_dataout) & (~ wire_n0lll_dataout)), n0l10O = ((((~ wire_n0liO_dataout) & (((((((~ wire_n0lli_dataout) & ((~ wire_n0lll_dataout) & (wire_n0lOi_dataout & wire_n0llO_dataout))) | ((~ wire_n0lli_dataout) & (wire_n0lll_dataout & n0l1iO))) | ((~ wire_n0lli_dataout) & (wire_n0lll_dataout & n0l1il))) | (wire_n0lli_dataout & ((~ wire_n0lll_dataout) & n0l1iO))) | (wire_n0lli_dataout & ((~ wire_n0lll_dataout) & n0l1il))) | (wire_n0lli_dataout & (wire_n0lll_dataout & ((~ wire_n0lOi_dataout) & (~ wire_n0llO_dataout)))))) | (wire_n0liO_dataout & n0l1ii)) & (wire_n0lll_dataout | (wire_n0lOi_dataout | wire_n0llO_dataout))), n0l11i = ((~ wire_nii_dataout) & n0l01l), n0l11l = (wire_niO_dataout ^ wire_nil_dataout), n0l11O = ((~ wire_n0lOi_dataout) & (~ wire_n0llO_dataout)), n0l1ii = (((((~ wire_n0lli_dataout) & ((~ wire_n0lll_dataout) & (wire_n0lOi_dataout & (~ wire_n0llO_dataout)))) | ((~ wire_n0lli_dataout) & ((~ wire_n0lll_dataout) & ((~ wire_n0lOi_dataout) & wire_n0llO_dataout)))) | ((~ wire_n0lli_dataout) & (wire_n0lll_dataout & n0l11O))) | (wire_n0lli_dataout & ((~ wire_n0lll_dataout) & n0l11O))), n0l1il = ((~ wire_n0lOi_dataout) & wire_n0llO_dataout), n0l1iO = (wire_n0lOi_dataout & (~ wire_n0llO_dataout)), n0l1li = (wire_n0liO_dataout & ((wire_n0lOi_dataout ^ wire_n0llO_dataout) & (wire_n0lll_dataout ^ wire_n0lli_dataout))), n0l1ll = (wire_n0liO_dataout & ((~ wire_n0lli_dataout) & ((~ wire_n0lll_dataout) & (wire_n0lOi_dataout & wire_n0llO_dataout)))), n0l1lO = (((~ wire_ni10i_dataout) & wire_ni11O_dataout) & (~ wire_ni11l_dataout)), n0l1Oi = ((~ wire_nllO_dataout) & n0O1OO), n0l1Ol = (wire_nlOl_dataout ^ wire_nlOi_dataout), n0l1OO = ((wire_n1l1O_dataout & (~ wire_n1l1l_dataout)) & (~ wire_n1l1i_dataout)), n0li0i = (n0ii0l & n0ii0O), n0li1O = (wire_nlli_dataout & n0ii0i), n0liii = (((~ wire_nllO_dataout) & wire_nlll_dataout) | (wire_nllO_dataout & (~ wire_nlll_dataout))), n0liil = (((((~ wire_nlli_dataout) & ((~ wire_nliO_dataout) & ((~ wire_nlil_dataout) & wire_nlii_dataout))) | ((~ wire_nlli_dataout) & ((~ wire_nliO_dataout) & (wire_nlil_dataout & (~ wire_nlii_dataout))))) | ((~ wire_nlli_dataout) & (wire_nliO_dataout & n0ii1i))) | (wire_nlli_dataout & ((~ wire_nliO_dataout) & n0ii1i))), n0lill = ((~ wire_nllO_dataout) & (~ wire_nlll_dataout)), n0lilO = (((((((~ wire_nlli_dataout) & ((~ wire_nliO_dataout) & (wire_nlil_dataout & wire_nlii_dataout))) | ((~ wire_nlli_dataout) & (wire_nliO_dataout & n0ii1O))) | ((~ wire_nlli_dataout) & (wire_nliO_dataout & n0ii1l))) | (wire_nlli_dataout & ((~ wire_nliO_dataout) & n0ii1O))) | (wire_nlli_dataout & ((~ wire_nliO_dataout) & n0ii1l))) | (wire_nlli_dataout & (wire_nliO_dataout & ((~ wire_nlil_dataout) & (~ wire_nlii_dataout))))), n0liOO = (n0liil & n0lill), n0ll0i = (n0ii0l & n0lill), n0ll1O = (n0ii0l & n0liii), n0lliO = (((((((~ wire_nll_dataout) & ((~ wire_nli_dataout) & (wire_niO_dataout & wire_nil_dataout))) | ((~ wire_nll_dataout) & (wire_nli_dataout & n0i10l))) | ((~ wire_nll_dataout) & (wire_nli_dataout & n0i10i))) | (wire_nll_dataout & ((~ wire_nli_dataout) & n0i10l))) | (wire_nll_dataout & ((~ wire_nli_dataout) & n0i10i))) | (wire_nll_dataout & (wire_nli_dataout & ((~ wire_niO_dataout) & (~ wire_nil_dataout))))), n0llli = (n0i1li | n0i1OO), n0llOO = ((~ wire_nll_dataout) & ((~ wire_nli_dataout) & ((~ wire_niO_dataout) & (~ wire_nil_dataout)))), n0lO1i = (((((~ wire_nll_dataout) & ((~ wire_nli_dataout) & ((~ wire_niO_dataout) & wire_nil_dataout))) | ((~ wire_nll_dataout) & ((~ wire_nli_dataout) & (wire_niO_dataout & (~ wire_nil_dataout))))) | ((~ wire_nll_dataout) & (wire_nli_dataout & n0i11O))) | (wire_nll_dataout & ((~ wire_nli_dataout) & n0i11O))), n0lO1l = ((~ wire_niO_dataout) & ((~ wire_nil_dataout) & n0lliO)), n0lOii = (n0i1lO & n0O11l), n0lOil = ((((n0i01l | (n0O11O & n00OOO)) | (n0i1lO & n0lOOi)) | n0i01i) | n0i01O), n0lOll = (wire_n0l_dataout & n00OOi), n0lOlO = (n00OOl & n00OOO), n0lOOi = (((~ wire_nii_dataout) & wire_n0O_dataout) | (wire_nii_dataout & (~ wire_n0O_dataout))), n0lOOl = (((((~ wire_n0l_dataout) & ((~ wire_n0i_dataout) & ((~ wire_n1O_dataout) & wire_n1l_dataout))) | ((~ wire_n0l_dataout) & ((~ wire_n0i_dataout) & (wire_n1O_dataout & (~ wire_n1l_dataout))))) | ((~ wire_n0l_dataout) & (wire_n0i_dataout & n00Oli))) | (wire_n0l_dataout & ((~ wire_n0i_dataout) & n00Oli))), n0O00i = ((renpolinv | rerr_flags_sel) | (~ (n0O00l2 ^ n0O00l1))), n0O01l = 1'b1, n0O10O = (n0lOOl & n0O11l), n0O11l = ((~ wire_nii_dataout) & (~ wire_n0O_dataout)), n0O11O = (((((((~ wire_n0l_dataout) & ((~ wire_n0i_dataout) & (wire_n1O_dataout & wire_n1l_dataout))) | ((~ wire_n0l_dataout) & (wire_n0i_dataout & n00OlO))) | ((~ wire_n0l_dataout) & (wire_n0i_dataout & n00Oll))) | (wire_n0l_dataout & ((~ wire_n0i_dataout) & n00OlO))) | (wire_n0l_dataout & ((~ wire_n0i_dataout) & n00Oll))) | (wire_n0l_dataout & (wire_n0i_dataout & ((~ wire_n1O_dataout) & (~ wire_n1l_dataout))))), n0O1iO = (n00OOl & n0lOOi), n0O1li = (n00OOl & n0O11l), n0O1Oi = ((wire_ni10i_dataout & (~ wire_ni11O_dataout)) & (~ wire_ni11l_dataout)), n0O1Ol = ((~ wire_n0liO_dataout) & n0l1ii), n0O1OO = (wire_n0liO_dataout & (wire_n0lli_dataout & (wire_n0lll_dataout & ((~ wire_n0lOi_dataout) & (~ wire_n0llO_dataout))))), ovr_undflow = {n1lO, n1ll, n1li, n1iO}, rlb_data = {wire_n1i_dataout, wire_nlOO_dataout, wire_nlOl_dataout, wire_nlOi_dataout, wire_nllO_dataout, wire_nlll_dataout, wire_nlli_dataout, wire_nliO_dataout, wire_nlil_dataout, wire_nlii_dataout, wire_nll_dataout, wire_nli_dataout, wire_niO_dataout, wire_nil_dataout, wire_nii_dataout, wire_n0O_dataout, wire_n0l_dataout, wire_n0i_dataout, wire_n1O_dataout, wire_n1l_dataout}, sync_resync_delay = {n1Ol, n1Oi}, tenb_data = {wire_nlO0i_dataout, wire_nlO1O_dataout, wire_nlO1l_dataout, wire_nlO1i_dataout, wire_nllOO_dataout, wire_nllOl_dataout, wire_nllOi_dataout, wire_nlllO_dataout, wire_nllll_dataout, wire_nllli_dataout, wire_nlliO_dataout, wire_nllil_dataout, wire_nllii_dataout, wire_nll0O_dataout, wire_nll0l_dataout, wire_nll0i_dataout, wire_nll1O_dataout, wire_nll1l_dataout, wire_nll1i_dataout, wire_nliOO_dataout}; endmodule //stratixiv_hssi_rx_digi_dec_chnl_top //synopsys translate_on //VALID FILE //IP Functional Simulation Model //VERSION_BEGIN 12.0 cbx_mgl 2012:05:31:20:09:47:SJ cbx_simgen 2012:05:31:20:08:35:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 // Copyright (C) 1991-2012 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // You may only use these simulation model output files for simulation // purposes and expressly not for synthesis or any other purposes (in which // event Altera disclaims all warranties of any kind). //synopsys translate_off //synthesis_resources = lut 135 mux21 124 oper_add 1 stratixiv_hssi_rx_digis_ram16x14_syn 1 `timescale 1 ps / 1 ps module stratixiv_hssi_rx_digi_dskw_fifo ( align_det_sync, audi, audi_pre, clk_1, en_dskw_gp, en_dskw_qd, fifo_rst_rd_gp, fifo_rst_rd_qd, rcvd_clk, rd_align, rdskchrp, rdskposdisp, sel_gp_md, soft_reset, sudi) /* synthesis synthesis_clearbox=1 */; output align_det_sync; output [13:0] audi; output [13:0] audi_pre; input clk_1; input en_dskw_gp; input en_dskw_qd; input fifo_rst_rd_gp; input fifo_rst_rd_qd; input rcvd_clk; output rd_align; input [9:0] rdskchrp; input rdskposdisp; input sel_gp_md; input soft_reset; input [13:0] sudi; reg n100l17; reg n100l18; reg n101i21; reg n101i22; reg n101O19; reg n101O20; reg n10iO15; reg n10iO16; reg n10lO13; reg n10lO14; reg n10Ol11; reg n10Ol12; reg n10OO10; reg n10OO9; reg n110i33; reg n110i34; reg n110O31; reg n110O32; reg n111l35; reg n111l36; reg n11il29; reg n11il30; reg n11li27; reg n11li28; reg n11lO25; reg n11lO26; reg n11Ol23; reg n11Ol24; reg n1i0l3; reg n1i0l4; reg n1i1i7; reg n1i1i8; reg n1i1O5; reg n1i1O6; reg n1ili1; reg n1ili2; reg nlOO0l47; reg nlOO0l48; reg nlOOii45; reg nlOOii46; reg nlOOiO43; reg nlOOiO44; reg nlOOll41; reg nlOOll42; reg nlOOOi39; reg nlOOOi40; reg nlOOOO37; reg nlOOOO38; reg ni00l; reg ni10i; wire wire_ni00i_PRN; reg n0Oi; reg ni0l; reg ni0O; reg niii; reg niiO; reg nlliO; reg nllli; reg nllll; reg nlllO; reg nllOi; reg nllOl; reg nllOO; reg nlO0i; reg nlO0l; reg nlO0O; reg nlO1i; reg nlO1l; reg nlO1O; reg nlOii; reg nlOil; reg nlOiO; reg niil_clk_prev; wire wire_niil_PRN; reg ni00O; reg ni01i; reg ni01l; reg ni01O; reg ni0ii; reg ni0il; reg ni0iO; reg ni0li; reg ni0ll; reg ni0lO; reg ni0Oi; reg ni0Ol; reg ni0OO; reg ni10l; reg ni10O; reg ni11l; reg ni11O; reg ni1ii; reg ni1il; reg ni1iO; reg ni1li; reg ni1ll; reg ni1lO; reg ni1Oi; reg ni1Ol; reg ni1OO; reg nii0i; reg nii0l; reg nii0O; reg nii1i; reg nii1l; reg nii1O; reg nl0ll; reg nl0lO; reg nl0Oi; reg nl0Ol; reg nl0OO; reg nli0i; reg nli0l; reg nli0O; reg nli1i; reg nli1l; reg nli1O; reg nliii; reg nliil; reg nliiO; reg nlili; reg nlill; reg nlilO; reg nliOi; reg nliOl; reg nliOO; reg nll0i; reg nll0l; reg nll0O; reg nll1i; reg nll1l; reg nll1O; reg nllii; reg nlOi; wire wire_nllO_CLRN; reg ni; reg nlil; reg nll; reg nllil; reg nlO_clk_prev; wire wire_nlO_CLRN; wire wire_n00i_dataout; wire wire_n00l_dataout; wire wire_n00O_dataout; wire wire_n01i_dataout; wire wire_n01l_dataout; wire wire_n01O_dataout; wire wire_n0i_dataout; wire wire_n0ii_dataout; wire wire_n0il_dataout; wire wire_n0iO_dataout; wire wire_n0l_dataout; wire wire_n0li_dataout; wire wire_n0ll_dataout; wire wire_n0O_dataout; wire wire_n0Ol_dataout; wire wire_n0OO_dataout; wire wire_n10i_dataout; wire wire_n10l_dataout; wire wire_n10O_dataout; wire wire_n11i_dataout; wire wire_n11l_dataout; wire wire_n11O_dataout; wire wire_n1i_dataout; wire wire_n1ii_dataout; wire wire_n1il_dataout; wire wire_n1iO_dataout; wire wire_n1l_dataout; wire wire_n1li_dataout; wire wire_n1ll_dataout; wire wire_n1lO_dataout; wire wire_n1O_dataout; wire wire_n1Oi_dataout; wire wire_n1Ol_dataout; wire wire_n1OO_dataout; wire wire_nii_dataout; wire wire_niiii_dataout; wire wire_niiil_dataout; wire wire_niiiO_dataout; wire wire_niili_dataout; wire wire_niill_dataout; wire wire_niilO_dataout; wire wire_niiOi_dataout; wire wire_niiOl_dataout; wire wire_niiOO_dataout; wire wire_nil_dataout; wire wire_nil0i_dataout; wire wire_nil0l_dataout; wire wire_nil0O_dataout; wire wire_nil1i_dataout; wire wire_nil1l_dataout; wire wire_nil1O_dataout; wire wire_nili_dataout; wire wire_nilii_dataout; wire wire_nilil_dataout; wire wire_niliO_dataout; wire wire_nill_dataout; wire wire_nilli_dataout; wire wire_nilll_dataout; wire wire_nillO_dataout; wire wire_nilO_dataout; wire wire_nilOi_dataout; wire wire_nilOl_dataout; wire wire_nilOO_dataout; wire wire_niO_dataout; wire wire_niO0i_dataout; wire wire_niO0l_dataout; wire wire_niO0O_dataout; wire wire_niO1i_dataout; wire wire_niO1l_dataout; wire wire_niO1O_dataout; wire wire_niOi_dataout; wire wire_niOii_dataout; wire wire_niOil_dataout; wire wire_niOiO_dataout; wire wire_niOl_dataout; wire wire_niOli_dataout; wire wire_niOll_dataout; wire wire_niOlO_dataout; wire wire_niOO_dataout; wire wire_niOOi_dataout; wire wire_niOOl_dataout; wire wire_niOOO_dataout; wire wire_nl_dataout; wire wire_nl00i_dataout; wire wire_nl00l_dataout; wire wire_nl00O_dataout; wire wire_nl01i_dataout; wire wire_nl01l_dataout; wire wire_nl01O_dataout; wire wire_nl0i_dataout; wire wire_nl0ii_dataout; wire wire_nl0il_dataout; wire wire_nl0iO_dataout; wire wire_nl0l_dataout; wire wire_nl0li_dataout; wire wire_nl0O_dataout; wire wire_nl10i_dataout; wire wire_nl10l_dataout; wire wire_nl10O_dataout; wire wire_nl11i_dataout; wire wire_nl11l_dataout; wire wire_nl11O_dataout; wire wire_nl1i_dataout; wire wire_nl1ii_dataout; wire wire_nl1il_dataout; wire wire_nl1iO_dataout; wire wire_nl1l_dataout; wire wire_nl1li_dataout; wire wire_nl1ll_dataout; wire wire_nl1lO_dataout; wire wire_nl1O_dataout; wire wire_nl1Oi_dataout; wire wire_nl1Ol_dataout; wire wire_nl1OO_dataout; wire wire_nli_dataout; wire wire_nliO_dataout; wire wire_nlli_dataout; wire wire_nlOli_dataout; wire wire_nlOll_dataout; wire wire_nlOlO_dataout; wire wire_nlOOi_dataout; wire wire_nlOOl_dataout; wire wire_nlOOO_dataout; wire wire_nO_dataout; wire [4:0] wire_nlii_o; wire [13:0] wire_n1iOi_data_out1; wire [13:0] wire_n1iOi_data_out2; wire n10ii; wire n10il; wire n10li; wire n10ll; wire n1i0i; wire n1i1l; wire n1iii; wire n1iil; wire n1iiO; initial n100l17 = 0; always @ ( posedge clk_1) n100l17 <= n100l18; event n100l17_event; initial #1 ->n100l17_event; always @(n100l17_event) n100l17 <= {1{1'b1}}; initial n100l18 = 0; always @ ( posedge clk_1) n100l18 <= n100l17; initial n101i21 = 0; always @ ( posedge clk_1) n101i21 <= n101i22; event n101i21_event; initial #1 ->n101i21_event; always @(n101i21_event) n101i21 <= {1{1'b1}}; initial n101i22 = 0; always @ ( posedge clk_1) n101i22 <= n101i21; initial n101O19 = 0; always @ ( posedge clk_1) n101O19 <= n101O20; event n101O19_event; initial #1 ->n101O19_event; always @(n101O19_event) n101O19 <= {1{1'b1}}; initial n101O20 = 0; always @ ( posedge clk_1) n101O20 <= n101O19; initial n10iO15 = 0; always @ ( posedge clk_1) n10iO15 <= n10iO16; event n10iO15_event; initial #1 ->n10iO15_event; always @(n10iO15_event) n10iO15 <= {1{1'b1}}; initial n10iO16 = 0; always @ ( posedge clk_1) n10iO16 <= n10iO15; initial n10lO13 = 0; always @ ( posedge clk_1) n10lO13 <= n10lO14; event n10lO13_event; initial #1 ->n10lO13_event; always @(n10lO13_event) n10lO13 <= {1{1'b1}}; initial n10lO14 = 0; always @ ( posedge clk_1) n10lO14 <= n10lO13; initial n10Ol11 = 0; always @ ( posedge clk_1) n10Ol11 <= n10Ol12; event n10Ol11_event; initial #1 ->n10Ol11_event; always @(n10Ol11_event) n10Ol11 <= {1{1'b1}}; initial n10Ol12 = 0; always @ ( posedge clk_1) n10Ol12 <= n10Ol11; initial n10OO10 = 0; always @ ( posedge clk_1) n10OO10 <= n10OO9; initial n10OO9 = 0; always @ ( posedge clk_1) n10OO9 <= n10OO10; event n10OO9_event; initial #1 ->n10OO9_event; always @(n10OO9_event) n10OO9 <= {1{1'b1}}; initial n110i33 = 0; always @ ( posedge clk_1) n110i33 <= n110i34; event n110i33_event; initial #1 ->n110i33_event; always @(n110i33_event) n110i33 <= {1{1'b1}}; initial n110i34 = 0; always @ ( posedge clk_1) n110i34 <= n110i33; initial n110O31 = 0; always @ ( posedge clk_1) n110O31 <= n110O32; event n110O31_event; initial #1 ->n110O31_event; always @(n110O31_event) n110O31 <= {1{1'b1}}; initial n110O32 = 0; always @ ( posedge clk_1) n110O32 <= n110O31; initial n111l35 = 0; always @ ( posedge clk_1) n111l35 <= n111l36; event n111l35_event; initial #1 ->n111l35_event; always @(n111l35_event) n111l35 <= {1{1'b1}}; initial n111l36 = 0; always @ ( posedge clk_1) n111l36 <= n111l35; initial n11il29 = 0; always @ ( posedge clk_1) n11il29 <= n11il30; event n11il29_event; initial #1 ->n11il29_event; always @(n11il29_event) n11il29 <= {1{1'b1}}; initial n11il30 = 0; always @ ( posedge clk_1) n11il30 <= n11il29; initial n11li27 = 0; always @ ( posedge clk_1) n11li27 <= n11li28; event n11li27_event; initial #1 ->n11li27_event; always @(n11li27_event) n11li27 <= {1{1'b1}}; initial n11li28 = 0; always @ ( posedge clk_1) n11li28 <= n11li27; initial n11lO25 = 0; always @ ( posedge clk_1) n11lO25 <= n11lO26; event n11lO25_event; initial #1 ->n11lO25_event; always @(n11lO25_event) n11lO25 <= {1{1'b1}}; initial n11lO26 = 0; always @ ( posedge clk_1) n11lO26 <= n11lO25; initial n11Ol23 = 0; always @ ( posedge clk_1) n11Ol23 <= n11Ol24; event n11Ol23_event; initial #1 ->n11Ol23_event; always @(n11Ol23_event) n11Ol23 <= {1{1'b1}}; initial n11Ol24 = 0; always @ ( posedge clk_1) n11Ol24 <= n11Ol23; initial n1i0l3 = 0; always @ ( posedge clk_1) n1i0l3 <= n1i0l4; event n1i0l3_event; initial #1 ->n1i0l3_event; always @(n1i0l3_event) n1i0l3 <= {1{1'b1}}; initial n1i0l4 = 0; always @ ( posedge clk_1) n1i0l4 <= n1i0l3; initial n1i1i7 = 0; always @ ( posedge clk_1) n1i1i7 <= n1i1i8; event n1i1i7_event; initial #1 ->n1i1i7_event; always @(n1i1i7_event) n1i1i7 <= {1{1'b1}}; initial n1i1i8 = 0; always @ ( posedge clk_1) n1i1i8 <= n1i1i7; initial n1i1O5 = 0; always @ ( posedge clk_1) n1i1O5 <= n1i1O6; event n1i1O5_event; initial #1 ->n1i1O5_event; always @(n1i1O5_event) n1i1O5 <= {1{1'b1}}; initial n1i1O6 = 0; always @ ( posedge clk_1) n1i1O6 <= n1i1O5; initial n1ili1 = 0; always @ ( posedge clk_1) n1ili1 <= n1ili2; event n1ili1_event; initial #1 ->n1ili1_event; always @(n1ili1_event) n1ili1 <= {1{1'b1}}; initial n1ili2 = 0; always @ ( posedge clk_1) n1ili2 <= n1ili1; initial nlOO0l47 = 0; always @ ( posedge clk_1) nlOO0l47 <= nlOO0l48; event nlOO0l47_event; initial #1 ->nlOO0l47_event; always @(nlOO0l47_event) nlOO0l47 <= {1{1'b1}}; initial nlOO0l48 = 0; always @ ( posedge clk_1) nlOO0l48 <= nlOO0l47; initial nlOOii45 = 0; always @ ( posedge clk_1) nlOOii45 <= nlOOii46; event nlOOii45_event; initial #1 ->nlOOii45_event; always @(nlOOii45_event) nlOOii45 <= {1{1'b1}}; initial nlOOii46 = 0; always @ ( posedge clk_1) nlOOii46 <= nlOOii45; initial nlOOiO43 = 0; always @ ( posedge clk_1) nlOOiO43 <= nlOOiO44; event nlOOiO43_event; initial #1 ->nlOOiO43_event; always @(nlOOiO43_event) nlOOiO43 <= {1{1'b1}}; initial nlOOiO44 = 0; always @ ( posedge clk_1) nlOOiO44 <= nlOOiO43; initial nlOOll41 = 0; always @ ( posedge clk_1) nlOOll41 <= nlOOll42; event nlOOll41_event; initial #1 ->nlOOll41_event; always @(nlOOll41_event) nlOOll41 <= {1{1'b1}}; initial nlOOll42 = 0; always @ ( posedge clk_1) nlOOll42 <= nlOOll41; initial nlOOOi39 = 0; always @ ( posedge clk_1) nlOOOi39 <= nlOOOi40; event nlOOOi39_event; initial #1 ->nlOOOi39_event; always @(nlOOOi39_event) nlOOOi39 <= {1{1'b1}}; initial nlOOOi40 = 0; always @ ( posedge clk_1) nlOOOi40 <= nlOOOi39; initial nlOOOO37 = 0; always @ ( posedge clk_1) nlOOOO37 <= nlOOOO38; event nlOOOO37_event; initial #1 ->nlOOOO37_event; always @(nlOOOO37_event) nlOOOO37 <= {1{1'b1}}; initial nlOOOO38 = 0; always @ ( posedge clk_1) nlOOOO38 <= nlOOOO37; initial begin ni00l = 0; ni10i = 0; end always @ ( posedge clk_1 or negedge wire_ni00i_PRN) begin if (wire_ni00i_PRN == 1'b0) begin ni00l <= 1; ni10i <= 1; end else begin ni00l <= wire_nilil_dataout; ni10i <= wire_niiil_dataout; end end assign wire_ni00i_PRN = ((n10iO16 ^ n10iO15) & (~ soft_reset)); event ni00l_event; event ni10i_event; initial #1 ->ni00l_event; initial #1 ->ni10i_event; always @(ni00l_event) ni00l <= 1; always @(ni10i_event) ni10i <= 1; initial begin n0Oi = 0; ni0l = 0; ni0O = 0; niii = 0; niiO = 0; nlliO = 0; nllli = 0; nllll = 0; nlllO = 0; nllOi = 0; nllOl = 0; nllOO = 0; nlO0i = 0; nlO0l = 0; nlO0O = 0; nlO1i = 0; nlO1l = 0; nlO1O = 0; nlOii = 0; nlOil = 0; nlOiO = 0; end always @ (rcvd_clk or wire_niil_PRN or soft_reset) begin if (wire_niil_PRN == 1'b0) begin n0Oi <= 1; ni0l <= 1; ni0O <= 1; niii <= 1; niiO <= 1; nlliO <= 1; nllli <= 1; nllll <= 1; nlllO <= 1; nllOi <= 1; nllOl <= 1; nllOO <= 1; nlO0i <= 1; nlO0l <= 1; nlO0O <= 1; nlO1i <= 1; nlO1l <= 1; nlO1O <= 1; nlOii <= 1; nlOil <= 1; nlOiO <= 1; end else if (soft_reset == 1'b1) begin n0Oi <= 0; ni0l <= 0; ni0O <= 0; niii <= 0; niiO <= 0; nlliO <= 0; nllli <= 0; nllll <= 0; nlllO <= 0; nllOi <= 0; nllOl <= 0; nllOO <= 0; nlO0i <= 0; nlO0l <= 0; nlO0O <= 0; nlO1i <= 0; nlO1l <= 0; nlO1O <= 0; nlOii <= 0; nlOil <= 0; nlOiO <= 0; end else if (rcvd_clk != niil_clk_prev && rcvd_clk == 1'b1) begin n0Oi <= wire_nili_dataout; ni0l <= wire_nill_dataout; ni0O <= wire_nilO_dataout; niii <= wire_niOi_dataout; niiO <= wire_nliO_dataout; nlliO <= wire_nlOll_dataout; nllli <= wire_nlOlO_dataout; nllll <= wire_nlOOi_dataout; nlllO <= wire_nlOOl_dataout; nllOi <= wire_nlOOO_dataout; nllOl <= wire_n11i_dataout; nllOO <= wire_n11l_dataout; nlO0i <= wire_n10O_dataout; nlO0l <= wire_n1ii_dataout; nlO0O <= wire_n1il_dataout; nlO1i <= wire_n11O_dataout; nlO1l <= wire_n10i_dataout; nlO1O <= wire_n10l_dataout; nlOii <= wire_n1iO_dataout; nlOil <= wire_n1li_dataout; nlOiO <= wire_n0Ol_dataout; end niil_clk_prev <= rcvd_clk; end assign wire_niil_PRN = (n10Ol12 ^ n10Ol11); initial begin ni00O = 0; ni01i = 0; ni01l = 0; ni01O = 0; ni0ii = 0; ni0il = 0; ni0iO = 0; ni0li = 0; ni0ll = 0; ni0lO = 0; ni0Oi = 0; ni0Ol = 0; ni0OO = 0; ni10l = 0; ni10O = 0; ni11l = 0; ni11O = 0; ni1ii = 0; ni1il = 0; ni1iO = 0; ni1li = 0; ni1ll = 0; ni1lO = 0; ni1Oi = 0; ni1Ol = 0; ni1OO = 0; nii0i = 0; nii0l = 0; nii0O = 0; nii1i = 0; nii1l = 0; nii1O = 0; nl0ll = 0; nl0lO = 0; nl0Oi = 0; nl0Ol = 0; nl0OO = 0; nli0i = 0; nli0l = 0; nli0O = 0; nli1i = 0; nli1l = 0; nli1O = 0; nliii = 0; nliil = 0; nliiO = 0; nlili = 0; nlill = 0; nlilO = 0; nliOi = 0; nliOl = 0; nliOO = 0; nll0i = 0; nll0l = 0; nll0O = 0; nll1i = 0; nll1l = 0; nll1O = 0; nllii = 0; nlOi = 0; end always @ ( posedge clk_1 or negedge wire_nllO_CLRN) begin if (wire_nllO_CLRN == 1'b0) begin ni00O <= 0; ni01i <= 0; ni01l <= 0; ni01O <= 0; ni0ii <= 0; ni0il <= 0; ni0iO <= 0; ni0li <= 0; ni0ll <= 0; ni0lO <= 0; ni0Oi <= 0; ni0Ol <= 0; ni0OO <= 0; ni10l <= 0; ni10O <= 0; ni11l <= 0; ni11O <= 0; ni1ii <= 0; ni1il <= 0; ni1iO <= 0; ni1li <= 0; ni1ll <= 0; ni1lO <= 0; ni1Oi <= 0; ni1Ol <= 0; ni1OO <= 0; nii0i <= 0; nii0l <= 0; nii0O <= 0; nii1i <= 0; nii1l <= 0; nii1O <= 0; nl0ll <= 0; nl0lO <= 0; nl0Oi <= 0; nl0Ol <= 0; nl0OO <= 0; nli0i <= 0; nli0l <= 0; nli0O <= 0; nli1i <= 0; nli1l <= 0; nli1O <= 0; nliii <= 0; nliil <= 0; nliiO <= 0; nlili <= 0; nlill <= 0; nlilO <= 0; nliOi <= 0; nliOl <= 0; nliOO <= 0; nll0i <= 0; nll0l <= 0; nll0O <= 0; nll1i <= 0; nll1l <= 0; nll1O <= 0; nllii <= 0; nlOi <= 0; end else begin ni00O <= wire_niliO_dataout; ni01i <= wire_nil0l_dataout; ni01l <= wire_nil0O_dataout; ni01O <= wire_nilii_dataout; ni0ii <= wire_nilli_dataout; ni0il <= wire_nilll_dataout; ni0iO <= wire_nillO_dataout; ni0li <= wire_nilOi_dataout; ni0ll <= wire_nilOl_dataout; ni0lO <= wire_nilOO_dataout; ni0Oi <= wire_niO1i_dataout; ni0Ol <= wire_niO1l_dataout; ni0OO <= wire_niO1O_dataout; ni10l <= wire_niiiO_dataout; ni10O <= wire_niili_dataout; ni11l <= niiO; ni11O <= wire_niiii_dataout; ni1ii <= wire_niill_dataout; ni1il <= wire_niilO_dataout; ni1iO <= wire_niiOi_dataout; ni1li <= wire_niiOl_dataout; ni1ll <= wire_niiOO_dataout; ni1lO <= wire_nil1i_dataout; ni1Oi <= wire_nil1l_dataout; ni1Ol <= wire_nil1O_dataout; ni1OO <= wire_nil0i_dataout; nii0i <= wire_niOii_dataout; nii0l <= wire_niOil_dataout; nii0O <= wire_n1iOi_data_out2[0]; nii1i <= wire_niO0i_dataout; nii1l <= wire_niO0l_dataout; nii1O <= wire_niO0O_dataout; nl0ll <= wire_n1iOi_data_out2[1]; nl0lO <= wire_n1iOi_data_out2[2]; nl0Oi <= wire_n1iOi_data_out2[3]; nl0Ol <= wire_n1iOi_data_out2[4]; nl0OO <= wire_n1iOi_data_out2[5]; nli0i <= wire_n1iOi_data_out2[9]; nli0l <= wire_n1iOi_data_out2[10]; nli0O <= wire_n1iOi_data_out2[11]; nli1i <= wire_n1iOi_data_out2[6]; nli1l <= wire_n1iOi_data_out2[7]; nli1O <= wire_n1iOi_data_out2[8]; nliii <= wire_n1iOi_data_out2[12]; nliil <= wire_n1iOi_data_out2[13]; nliiO <= wire_n1iOi_data_out1[0]; nlili <= wire_n1iOi_data_out1[1]; nlill <= wire_n1iOi_data_out1[2]; nlilO <= wire_n1iOi_data_out1[3]; nliOi <= wire_n1iOi_data_out1[4]; nliOl <= wire_n1iOi_data_out1[5]; nliOO <= wire_n1iOi_data_out1[6]; nll0i <= wire_n1iOi_data_out1[10]; nll0l <= wire_n1iOi_data_out1[11]; nll0O <= wire_n1iOi_data_out1[12]; nll1i <= wire_n1iOi_data_out1[7]; nll1l <= wire_n1iOi_data_out1[8]; nll1O <= wire_n1iOi_data_out1[9]; nllii <= wire_n1iOi_data_out1[13]; nlOi <= ni11l; end end assign wire_nllO_CLRN = ((n1i1O6 ^ n1i1O5) & (~ soft_reset)); initial begin ni = 0; nlil = 0; nll = 0; nllil = 0; end always @ (rcvd_clk or soft_reset or wire_nlO_CLRN) begin if (soft_reset == 1'b1) begin ni <= 1; nlil <= 1; nll <= 1; nllil <= 1; end else if (wire_nlO_CLRN == 1'b0) begin ni <= 0; nlil <= 0; nll <= 0; nllil <= 0; end else if (rcvd_clk != nlO_clk_prev && rcvd_clk == 1'b1) begin ni <= wire_nO_dataout; nlil <= nll; nll <= ni; nllil <= wire_nlOli_dataout; end nlO_clk_prev <= rcvd_clk; end assign wire_nlO_CLRN = (n1ili2 ^ n1ili1); event ni_event; event nlil_event; event nll_event; event nllil_event; initial #1 ->ni_event; initial #1 ->nlil_event; initial #1 ->nll_event; initial #1 ->nllil_event; always @(ni_event) ni <= 1; always @(nlil_event) nlil <= 1; always @(nll_event) nll <= 1; always @(nllil_event) nllil <= 1; assign wire_n00i_dataout = (n10li === 1'b1) ? nllOO : nlO1i; assign wire_n00l_dataout = (n10li === 1'b1) ? nlO1i : nlO1l; assign wire_n00O_dataout = (n10li === 1'b1) ? nlO1l : nlO1O; assign wire_n01i_dataout = (n10li === 1'b1) ? nlllO : nllOi; assign wire_n01l_dataout = (n10li === 1'b1) ? nllOi : nllOl; assign wire_n01O_dataout = (n10li === 1'b1) ? nllOl : nllOO; assign wire_n0i_dataout = (rdskposdisp === 1'b1) ? rdskchrp[3] : (~ rdskchrp[3]); assign wire_n0ii_dataout = (n10li === 1'b1) ? nlO1O : nlO0i; assign wire_n0il_dataout = (n10li === 1'b1) ? nlO0i : nlO0l; assign wire_n0iO_dataout = (n10li === 1'b1) ? nlO0l : nlO0O; assign wire_n0l_dataout = (rdskposdisp === 1'b1) ? rdskchrp[4] : (~ rdskchrp[4]); assign wire_n0li_dataout = (n10li === 1'b1) ? nlO0O : nlOii; assign wire_n0ll_dataout = (n10li === 1'b1) ? nlOii : nlOil; assign wire_n0O_dataout = (rdskposdisp === 1'b1) ? rdskchrp[5] : (~ rdskchrp[5]); and(wire_n0Ol_dataout, wire_n0OO_dataout, ~(n10ll)); or(wire_n0OO_dataout, nlOiO, n1i0i); and(wire_n10i_dataout, wire_n00l_dataout, ~(n10ll)); and(wire_n10l_dataout, wire_n00O_dataout, ~(n10ll)); and(wire_n10O_dataout, wire_n0ii_dataout, ~(n10ll)); and(wire_n11i_dataout, wire_n01l_dataout, ~(n10ll)); and(wire_n11l_dataout, wire_n01O_dataout, ~(n10ll)); and(wire_n11O_dataout, wire_n00i_dataout, ~(n10ll)); assign wire_n1i_dataout = (rdskposdisp === 1'b1) ? rdskchrp[0] : (~ rdskchrp[0]); and(wire_n1ii_dataout, wire_n0il_dataout, ~(n10ll)); and(wire_n1il_dataout, wire_n0iO_dataout, ~(n10ll)); and(wire_n1iO_dataout, wire_n0li_dataout, ~(n10ll)); assign wire_n1l_dataout = (rdskposdisp === 1'b1) ? rdskchrp[1] : (~ rdskchrp[1]); and(wire_n1li_dataout, wire_n0ll_dataout, ~(n10ll)); assign wire_n1ll_dataout = (n10li === 1'b1) ? nlOil : nllil; assign wire_n1lO_dataout = (n10li === 1'b1) ? nllil : nlliO; assign wire_n1O_dataout = (rdskposdisp === 1'b1) ? rdskchrp[2] : (~ rdskchrp[2]); assign wire_n1Oi_dataout = (n10li === 1'b1) ? nlliO : nllli; assign wire_n1Ol_dataout = (n10li === 1'b1) ? nllli : nllll; assign wire_n1OO_dataout = (n10li === 1'b1) ? nllll : nlllO; assign wire_nii_dataout = (rdskposdisp === 1'b1) ? rdskchrp[6] : (~ rdskchrp[6]); and(wire_niiii_dataout, wire_niOiO_dataout, ~(wire_nl_dataout)); or(wire_niiil_dataout, wire_niOli_dataout, wire_nl_dataout); and(wire_niiiO_dataout, wire_niOll_dataout, ~(wire_nl_dataout)); and(wire_niili_dataout, wire_niOlO_dataout, ~(wire_nl_dataout)); and(wire_niill_dataout, wire_niOOi_dataout, ~(wire_nl_dataout)); and(wire_niilO_dataout, wire_niOOl_dataout, ~(wire_nl_dataout)); and(wire_niiOi_dataout, wire_niOOO_dataout, ~(wire_nl_dataout)); and(wire_niiOl_dataout, wire_nl11i_dataout, ~(wire_nl_dataout)); and(wire_niiOO_dataout, wire_nl11l_dataout, ~(wire_nl_dataout)); assign wire_nil_dataout = (rdskposdisp === 1'b1) ? rdskchrp[7] : (~ rdskchrp[7]); and(wire_nil0i_dataout, wire_nl10O_dataout, ~(wire_nl_dataout)); and(wire_nil0l_dataout, wire_nl1ii_dataout, ~(wire_nl_dataout)); and(wire_nil0O_dataout, wire_nl1il_dataout, ~(wire_nl_dataout)); and(wire_nil1i_dataout, wire_nl11O_dataout, ~(wire_nl_dataout)); and(wire_nil1l_dataout, wire_nl10i_dataout, ~(wire_nl_dataout)); and(wire_nil1O_dataout, wire_nl10l_dataout, ~(wire_nl_dataout)); and(wire_nili_dataout, wire_niOl_dataout, ~((~ nll))); and(wire_nilii_dataout, wire_nl1iO_dataout, ~(wire_nl_dataout)); or(wire_nilil_dataout, wire_nl1li_dataout, wire_nl_dataout); and(wire_niliO_dataout, wire_nl1ll_dataout, ~(wire_nl_dataout)); and(wire_nill_dataout, wire_niOO_dataout, ~((~ nll))); and(wire_nilli_dataout, wire_nl1lO_dataout, ~(wire_nl_dataout)); and(wire_nilll_dataout, wire_nl1Oi_dataout, ~(wire_nl_dataout)); and(wire_nillO_dataout, wire_nl1Ol_dataout, ~(wire_nl_dataout)); and(wire_nilO_dataout, wire_nl1i_dataout, ~((~ nll))); and(wire_nilOi_dataout, wire_nl1OO_dataout, ~(wire_nl_dataout)); and(wire_nilOl_dataout, wire_nl01i_dataout, ~(wire_nl_dataout)); and(wire_nilOO_dataout, wire_nl01l_dataout, ~(wire_nl_dataout)); assign wire_niO_dataout = (rdskposdisp === 1'b1) ? rdskchrp[8] : (~ rdskchrp[8]); and(wire_niO0i_dataout, wire_nl00O_dataout, ~(wire_nl_dataout)); and(wire_niO0l_dataout, wire_nl0ii_dataout, ~(wire_nl_dataout)); and(wire_niO0O_dataout, wire_nl0il_dataout, ~(wire_nl_dataout)); and(wire_niO1i_dataout, wire_nl01O_dataout, ~(wire_nl_dataout)); and(wire_niO1l_dataout, wire_nl00i_dataout, ~(wire_nl_dataout)); and(wire_niO1O_dataout, wire_nl00l_dataout, ~(wire_nl_dataout)); and(wire_niOi_dataout, wire_nl1l_dataout, ~((~ nll))); and(wire_niOii_dataout, wire_nl0iO_dataout, ~(wire_nl_dataout)); and(wire_niOil_dataout, wire_nl0li_dataout, ~(wire_nl_dataout)); and(wire_niOiO_dataout, ni01O, (~ wire_nO_dataout)); or(wire_niOl_dataout, wire_nl1O_dataout, n1i0i); or(wire_niOli_dataout, ni11O, ~((~ wire_nO_dataout))); and(wire_niOll_dataout, ni10i, (~ wire_nO_dataout)); and(wire_niOlO_dataout, ni10l, (~ wire_nO_dataout)); and(wire_niOO_dataout, wire_nl0i_dataout, ~(n1i0i)); and(wire_niOOi_dataout, ni10O, (~ wire_nO_dataout)); and(wire_niOOl_dataout, ni1ii, (~ wire_nO_dataout)); and(wire_niOOO_dataout, ni1il, (~ wire_nO_dataout)); assign wire_nl_dataout = (sel_gp_md === 1'b1) ? fifo_rst_rd_gp : fifo_rst_rd_qd; and(wire_nl00i_dataout, ni0Oi, (~ wire_nO_dataout)); and(wire_nl00l_dataout, ni0Ol, (~ wire_nO_dataout)); and(wire_nl00O_dataout, ni0OO, (~ wire_nO_dataout)); and(wire_nl01i_dataout, ni0li, (~ wire_nO_dataout)); and(wire_nl01l_dataout, ni0ll, (~ wire_nO_dataout)); and(wire_nl01O_dataout, ni0lO, (~ wire_nO_dataout)); assign wire_nl0i_dataout = ((~ n1i1l) === 1'b1) ? wire_nlii_o[2] : ni0l; and(wire_nl0ii_dataout, nii1i, (~ wire_nO_dataout)); and(wire_nl0il_dataout, nii1l, (~ wire_nO_dataout)); and(wire_nl0iO_dataout, nii1O, (~ wire_nO_dataout)); assign wire_nl0l_dataout = ((~ n1i1l) === 1'b1) ? wire_nlii_o[3] : ni0O; and(wire_nl0li_dataout, nii0i, (~ wire_nO_dataout)); assign wire_nl0O_dataout = ((~ n1i1l) === 1'b1) ? wire_nlii_o[4] : niii; and(wire_nl10i_dataout, ni1lO, (~ wire_nO_dataout)); and(wire_nl10l_dataout, ni1Oi, (~ wire_nO_dataout)); and(wire_nl10O_dataout, ni1Ol, (~ wire_nO_dataout)); and(wire_nl11i_dataout, ni1iO, (~ wire_nO_dataout)); and(wire_nl11l_dataout, ni1li, (~ wire_nO_dataout)); and(wire_nl11O_dataout, ni1ll, (~ wire_nO_dataout)); and(wire_nl1i_dataout, wire_nl0l_dataout, ~(n1i0i)); and(wire_nl1ii_dataout, ni1OO, (~ wire_nO_dataout)); and(wire_nl1il_dataout, ni01i, (~ wire_nO_dataout)); and(wire_nl1iO_dataout, ni01l, (~ wire_nO_dataout)); or(wire_nl1l_dataout, wire_nl0O_dataout, n1i0i); or(wire_nl1li_dataout, nii0l, ~((~ wire_nO_dataout))); and(wire_nl1ll_dataout, ni00l, (~ wire_nO_dataout)); and(wire_nl1lO_dataout, ni00O, (~ wire_nO_dataout)); assign wire_nl1O_dataout = ((~ n1i1l) === 1'b1) ? wire_nlii_o[1] : n0Oi; and(wire_nl1Oi_dataout, ni0ii, (~ wire_nO_dataout)); and(wire_nl1Ol_dataout, ni0il, (~ wire_nO_dataout)); and(wire_nl1OO_dataout, ni0iO, (~ wire_nO_dataout)); assign wire_nli_dataout = (rdskposdisp === 1'b1) ? rdskchrp[9] : (~ rdskchrp[9]); or(wire_nliO_dataout, wire_nlli_dataout, n1i0i); and(wire_nlli_dataout, niiO, ~(n1i1l)); or(wire_nlOli_dataout, wire_n1ll_dataout, n10ll); and(wire_nlOll_dataout, wire_n1lO_dataout, ~(n10ll)); and(wire_nlOlO_dataout, wire_n1Oi_dataout, ~(n10ll)); and(wire_nlOOi_dataout, wire_n1Ol_dataout, ~(n10ll)); and(wire_nlOOl_dataout, wire_n1OO_dataout, ~(n10ll)); and(wire_nlOOO_dataout, wire_n01i_dataout, ~(n10ll)); assign wire_nO_dataout = (sel_gp_md === 1'b1) ? en_dskw_gp : en_dskw_qd; oper_add nlii ( .a({((n10OO10 ^ n10OO9) & niii), ((n1i1i8 ^ n1i1i7) & ni0O), ni0l, n0Oi, 1'b1}), .b({{3{1'b1}}, 1'b0, 1'b1}), .cin(1'b0), .cout(), .o(wire_nlii_o)); defparam nlii.sgate_representation = 0, nlii.width_a = 5, nlii.width_b = 5, nlii.width_o = 5; stratixiv_hssi_rx_digis_ram16x14_syn n1iOi ( .addr_rd1({nii0l, nii0i, nii1O, nii1l, nii1i, ni0OO, ni0Ol, ni0Oi, ni0lO, ni0ll, ni0li, ni0iO, ni0il, ni0ii, ni00O, ni00l}), .addr_rd2({ni01O, ni01l, ni01i, ni1OO, ni1Ol, ni1Oi, ni1lO, ni1ll, ni1li, ni1iO, ni1il, ni1ii, ni10O, ni10l, ni10i, ni11O}), .addr_wr({nlOil, nlOii, nlO0O, nlO0l, nlO0i, nlO1O, nlO1l, nlO1i, nllOO, nllOl, nllOi, nlllO, nllll, nllli, nlliO, nllil}), .clk(rcvd_clk), .data_in({sudi[13:0]}), .data_out1(wire_n1iOi_data_out1), .data_out2(wire_n1iOi_data_out2), .re_l(1'b0), .rst_l((~ soft_reset)), .we(1'b1)); defparam n1iOi.ram_width = 14, n1iOi.read_access_time = 0, n1iOi.write_access_time = 0; assign align_det_sync = nlOi, audi = {nllii, nll0O, nll0l, nll0i, nll1O, nll1l, nll1i, nliOO, nliOl, nliOi, nlilO, nlill, nlili, nliiO}, audi_pre = {nliil, nliii, nli0O, nli0l, nli0i, nli1O, nli1l, nli1i, nl0OO, nl0Ol, nl0Oi, nl0lO, nl0ll, nii0O}, n10ii = ((((((((((((~ nll0O) & (~ nll0i)) & (~ (wire_n1i_dataout ^ nliiO))) & (~ (wire_n1l_dataout ^ nlili))) & (~ (wire_n1O_dataout ^ nlill))) & (~ (wire_n0i_dataout ^ nlilO))) & (~ (wire_n0l_dataout ^ nliOi))) & (~ (wire_n0O_dataout ^ nliOl))) & (~ (wire_nii_dataout ^ nliOO))) & (~ (wire_nil_dataout ^ nll1i))) & (~ (wire_niO_dataout ^ nll1l))) & (~ (wire_nli_dataout ^ nll1O))), n10il = ((((((((((((~ nll0O) & (~ nll0i)) & (~ ((nliiO ^ rdskchrp[0]) ^ (~ (nlOOOi40 ^ nlOOOi39))))) & (~ (nlili ^ rdskchrp[1]))) & (~ (nlill ^ rdskchrp[2]))) & (~ (nlilO ^ rdskchrp[3]))) & (~ (nliOi ^ rdskchrp[4]))) & (~ ((nliOl ^ rdskchrp[5]) ^ (~ (nlOOll42 ^ nlOOll41))))) & (~ (nliOO ^ rdskchrp[6]))) & (~ ((nll1i ^ rdskchrp[7]) ^ (~ (nlOOiO44 ^ nlOOiO43))))) & (~ ((nll1l ^ rdskchrp[8]) ^ (~ (nlOOii46 ^ nlOOii45))))) & (~ ((nll1O ^ rdskchrp[9]) ^ (~ (nlOO0l48 ^ nlOO0l47))))), n10li = (n1i0i | nlOiO), n10ll = (((nll & (nlOiO & nlOil)) | (nll & (~ nlil))) | (~ (n10lO14 ^ n10lO13))), n1i0i = (nll & ((n1iil | n1iii) | (~ (n1i0l4 ^ n1i0l3)))), n1i1l = ((((~ niii) & (~ ni0O)) & (~ ni0l)) & (~ n0Oi)), n1iii = (((((((((((((~ sudi[10]) & (~ sudi[12])) & (~ ((wire_n1i_dataout ^ sudi[0]) ^ (~ (n11il30 ^ n11il29))))) & (~ (wire_n1l_dataout ^ sudi[1]))) & (~ ((wire_n1O_dataout ^ sudi[2]) ^ (~ (n110O32 ^ n110O31))))) & (~ (wire_n0i_dataout ^ sudi[3]))) & (~ ((wire_n0l_dataout ^ sudi[4]) ^ (~ (n110i34 ^ n110i33))))) & (~ (wire_n0O_dataout ^ sudi[5]))) & (~ (wire_nii_dataout ^ sudi[6]))) & (~ ((wire_nil_dataout ^ sudi[7]) ^ (~ (n111l36 ^ n111l35))))) & (~ (wire_niO_dataout ^ sudi[8]))) & (~ (wire_nli_dataout ^ sudi[9]))) & (nlOOOO38 ^ nlOOOO37)), n1iil = (((((((((((((~ sudi[10]) & (~ sudi[12])) & (~ (sudi[0] ^ rdskchrp[0]))) & (~ (sudi[1] ^ rdskchrp[1]))) & (~ (sudi[2] ^ rdskchrp[2]))) & (~ ((sudi[3] ^ rdskchrp[3]) ^ (~ (n101O20 ^ n101O19))))) & (~ ((sudi[4] ^ rdskchrp[4]) ^ (~ (n101i22 ^ n101i21))))) & (~ (sudi[5] ^ rdskchrp[5]))) & (~ (sudi[6] ^ rdskchrp[6]))) & (~ ((sudi[7] ^ rdskchrp[7]) ^ (~ (n11Ol24 ^ n11Ol23))))) & (~ (sudi[8] ^ rdskchrp[8]))) & (~ ((sudi[9] ^ rdskchrp[9]) ^ (~ (n11lO26 ^ n11lO25))))) & (n11li28 ^ n11li27)), n1iiO = 1'b1, rd_align = ((n10il | n10ii) | (~ (n100l18 ^ n100l17))); endmodule //stratixiv_hssi_rx_digi_dskw_fifo //synopsys translate_on //VALID FILE //IP Functional Simulation Model //VERSION_BEGIN 12.0 cbx_mgl 2012:05:31:20:09:47:SJ cbx_simgen 2012:05:31:20:08:35:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 // Copyright (C) 1991-2012 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // You may only use these simulation model output files for simulation // purposes and expressly not for synthesis or any other purposes (in which // event Altera disclaims all warranties of any kind). //synopsys translate_off //synthesis_resources = lut 162 mux21 158 oper_add 7 oper_less_than 17 `timescale 1 ps / 1 ps module stratixiv_hssi_rx_digi_freqdet ( eidle_exit, fref, freq_lock, fvcobyn, gen2ngen1_bundle, gen2ngen1_indv, hard_reset, pd, ppm_cnt_latch, ppm_cnt_reset, ppmsel, rauto_speed_ena, rforcehigh, rforcelow, rindv_rx, rppm_gen1_2xcnt_en, rppm_post_eidle_del, scan_mode) /* synthesis synthesis_clearbox=1 */; input eidle_exit; input fref; output freq_lock; input fvcobyn; input gen2ngen1_bundle; input gen2ngen1_indv; input hard_reset; input pd; output [7:0] ppm_cnt_latch; input ppm_cnt_reset; input [5:0] ppmsel; input rauto_speed_ena; input rforcehigh; input rforcelow; input rindv_rx; input rppm_gen1_2xcnt_en; input rppm_post_eidle_del; input scan_mode; reg nlll0O57; reg nlll0O58; reg nllOOi55; reg nllOOi56; reg nlO00i21; reg nlO00i22; reg nlO00l19; reg nlO00l20; reg nlO00O17; reg nlO00O18; reg nlO01i27; reg nlO01i28; reg nlO01l25; reg nlO01l26; reg nlO01O23; reg nlO01O24; reg nlO0ii15; reg nlO0ii16; reg nlO0iO13; reg nlO0iO14; reg nlO0ll11; reg nlO0ll12; reg nlO0Oi10; reg nlO0Oi9; reg nlO0Ol7; reg nlO0Ol8; reg nlO10i47; reg nlO10i48; reg nlO10l45; reg nlO10l46; reg nlO10O43; reg nlO10O44; reg nlO11i53; reg nlO11i54; reg nlO11l51; reg nlO11l52; reg nlO11O49; reg nlO11O50; reg nlO1ii41; reg nlO1ii42; reg nlO1li39; reg nlO1li40; reg nlO1ll37; reg nlO1ll38; reg nlO1lO35; reg nlO1lO36; reg nlO1Oi33; reg nlO1Oi34; reg nlO1Ol31; reg nlO1Ol32; reg nlO1OO29; reg nlO1OO30; reg nlOi0l3; reg nlOi0l4; reg nlOi1l5; reg nlOi1l6; reg nlOiil1; reg nlOiil2; reg n0lOO; reg n1i; reg nii; reg n0O_clk_prev; wire wire_n0O_CLRN; reg n10iO; reg n1ilO; wire wire_n1ill_CLRN; reg n0lOi; reg ni00O; reg ni00l_clk_prev; wire wire_ni00l_CLRN; reg nl0lO; reg ni00i; reg ni01i; reg ni01l; reg ni01O; reg ni10i; reg ni10l; reg ni10O; reg ni11O; reg ni1ii; reg ni1il; reg ni1iO; reg ni1li; reg ni1ll; reg ni1lO; reg ni1Oi; reg ni1Ol; reg ni1OO; reg nl00O; reg nl01l; reg nl0Ol; reg n00ii; reg n00il; reg n00iO; reg n00li; reg n00ll; reg n00lO; reg n00Oi; reg n00Ol; reg n0lli; reg n0lll; reg n0llO; reg n100i; reg n100l; reg n100O; reg n101l; reg n101O; reg n10ii; reg n10il; reg n1iOi; reg n1iOO; reg niiOl; reg niiOO; reg nil0i; reg nil0l; reg nil0O; reg nil1i; reg nil1l; reg nil1O; reg nilii; reg nilil; reg niliO; reg nilli; reg nilll; reg nillO; reg nilOi; reg nilOl; reg nilOO; reg niO1i; reg nl01i; reg nl0ii; reg nl0il; reg nl0iO; reg nl0li; reg nl1iO; reg nl1li; reg nli1i; wire wire_nl0OO_CLRN; reg nli1O; reg nliil; wire wire_nliii_PRN; reg nliiO; reg nlilO; wire wire_nlill_PRN; reg nlli; reg nliO_clk_prev; wire wire_nliO_CLRN; reg nlii; reg nlil; reg nliOi; reg nll0i; reg nll0l; reg nll0O; reg nll1l; reg nll1O; reg nllii; reg nllil; reg nlliO; reg nllli; reg nllll; reg nlllO; reg nllO; reg nllOi; reg nllOl; reg nllOO; reg nlO0i; reg nlO0l; reg nlO1i; reg nlO1l; reg nlO1O; reg nlOi; reg nlOO; reg nlOl_clk_prev; wire wire_nlOl_CLRN; wire wire_nlOl_PRN; wire wire_n00i_dataout; wire wire_n00l_dataout; wire wire_n00O_dataout; wire wire_n00OO_dataout; wire wire_n01i_dataout; wire wire_n01l_dataout; wire wire_n01O_dataout; wire wire_n0i_dataout; wire wire_n0i0i_dataout; wire wire_n0i0l_dataout; wire wire_n0i0O_dataout; wire wire_n0i1i_dataout; wire wire_n0i1l_dataout; wire wire_n0i1O_dataout; wire wire_n0ii_dataout; wire wire_n0iii_dataout; wire wire_n0iil_dataout; wire wire_n0iiO_dataout; wire wire_n0il_dataout; wire wire_n0ili_dataout; wire wire_n0ill_dataout; wire wire_n0ilO_dataout; wire wire_n0iO_dataout; wire wire_n0iOi_dataout; wire wire_n0iOl_dataout; wire wire_n0iOO_dataout; wire wire_n0l_dataout; wire wire_n0l0i_dataout; wire wire_n0l0l_dataout; wire wire_n0l0O_dataout; wire wire_n0l1i_dataout; wire wire_n0l1l_dataout; wire wire_n0l1O_dataout; wire wire_n0li_dataout; wire wire_n0lii_dataout; wire wire_n0lil_dataout; wire wire_n0ll_dataout; wire wire_n0lO_dataout; wire wire_n0O0i_dataout; wire wire_n0O0l_dataout; wire wire_n0O0O_dataout; wire wire_n0O1i_dataout; wire wire_n0O1l_dataout; wire wire_n0O1O_dataout; wire wire_n0Oi_dataout; wire wire_n0Oii_dataout; wire wire_n0Oil_dataout; wire wire_n0OiO_dataout; wire wire_n0Ol_dataout; wire wire_n0Oli_dataout; wire wire_n0Oll_dataout; wire wire_n0OlO_dataout; wire wire_n0OO_dataout; wire wire_n0OOi_dataout; wire wire_n0OOl_dataout; wire wire_n101i_dataout; wire wire_n10i_dataout; wire wire_n10l_dataout; wire wire_n10li_dataout; wire wire_n10ll_dataout; wire wire_n10lO_dataout; wire wire_n10O_dataout; wire wire_n10Oi_dataout; wire wire_n10Ol_dataout; wire wire_n10OO_dataout; wire wire_n11i_dataout; wire wire_n11l_dataout; wire wire_n11O_dataout; wire wire_n11Oi_dataout; wire wire_n11Ol_dataout; wire wire_n11OO_dataout; wire wire_n1i0i_dataout; wire wire_n1i0l_dataout; wire wire_n1i0O_dataout; wire wire_n1i1i_dataout; wire wire_n1i1l_dataout; wire wire_n1i1O_dataout; wire wire_n1ii_dataout; wire wire_n1iii_dataout; wire wire_n1iil_dataout; wire wire_n1iiO_dataout; wire wire_n1il_dataout; wire wire_n1ili_dataout; wire wire_n1iO_dataout; wire wire_n1li_dataout; wire wire_n1ll_dataout; wire wire_n1lO_dataout; wire wire_n1Oi_dataout; wire wire_n1Ol_dataout; wire wire_n1OO_dataout; wire wire_ni0i_dataout; wire wire_ni0ii_dataout; wire wire_ni0il_dataout; wire wire_ni0iO_dataout; wire wire_ni0l_dataout; wire wire_ni0li_dataout; wire wire_ni0ll_dataout; wire wire_ni0lO_dataout; wire wire_ni0O_dataout; wire wire_ni0Oi_dataout; wire wire_ni0Ol_dataout; wire wire_ni0OO_dataout; wire wire_ni1i_dataout; wire wire_ni1l_dataout; wire wire_ni1O_dataout; wire wire_nii0i_dataout; wire wire_nii0l_dataout; wire wire_nii0O_dataout; wire wire_nii1i_dataout; wire wire_nii1l_dataout; wire wire_nii1O_dataout; wire wire_niii_dataout; wire wire_niiii_dataout; wire wire_niiil_dataout; wire wire_niiiO_dataout; wire wire_niil_dataout; wire wire_niiO_dataout; wire wire_nili_dataout; wire wire_nill_dataout; wire wire_nilO_dataout; wire wire_niO0i_dataout; wire wire_niO0l_dataout; wire wire_niO0O_dataout; wire wire_niO1l_dataout; wire wire_niO1O_dataout; wire wire_niOi_dataout; wire wire_niOii_dataout; wire wire_niOil_dataout; wire wire_niOiO_dataout; wire wire_niOl_dataout; wire wire_niOli_dataout; wire wire_niOll_dataout; wire wire_niOlO_dataout; wire wire_niOO_dataout; wire wire_niOOi_dataout; wire wire_niOOl_dataout; wire wire_niOOO_dataout; wire wire_nl00i_dataout; wire wire_nl00l_dataout; wire wire_nl01O_dataout; wire wire_nl10i_dataout; wire wire_nl11i_dataout; wire wire_nl11l_dataout; wire wire_nl11O_dataout; wire wire_nl1i_dataout; wire wire_nli0O_dataout; wire wire_nlili_dataout; wire wire_nliOl_dataout; wire wire_nlO0O_dataout; wire wire_nlOii_dataout; wire wire_nlOil_dataout; wire wire_nlOiO_dataout; wire wire_nlOli_dataout; wire wire_nlOll_dataout; wire wire_nlOlO_dataout; wire wire_nlOOi_dataout; wire wire_nlOOl_dataout; wire wire_nlOOO_dataout; wire [7:0] wire_n0liO_o; wire [4:0] wire_n0OOO_o; wire [16:0] wire_niiOi_o; wire [17:0] wire_nl0i_o; wire [16:0] wire_nl1il_o; wire [16:0] wire_nl1l_o; wire [12:0] wire_nli0l_o; wire wire_n000l_o; wire wire_n001l_o; wire wire_n010l_o; wire wire_n011i_o; wire wire_n01iO_o; wire wire_n01Oi_o; wire wire_n1liO_o; wire wire_n1lOl_o; wire wire_n1O1O_o; wire wire_n1Oil_o; wire wire_n1OlO_o; wire wire_nl0l_o; wire wire_nl1O_o; wire wire_nl1Ol_o; wire wire_nl1OO_o; wire wire_nli0i_o; wire wire_nli1l_o; wire nlllii; wire nlllil; wire nllliO; wire nlllli; wire nlllll; wire nllllO; wire nlllOi; wire nlllOl; wire nlllOO; wire nllO0i; wire nllO0l; wire nllO0O; wire nllO1i; wire nllO1l; wire nllO1O; wire nllOii; wire nllOil; wire nllOiO; wire nllOli; wire nllOll; wire nllOlO; wire nllOOl; wire nllOOO; wire nlO0il; wire nlO0li; wire nlO0OO; wire nlO1iO; wire nlOi0i; wire nlOi1i; wire nlOi1O; wire nlOiii; initial nlll0O57 = 0; always @ ( posedge fref) nlll0O57 <= nlll0O58; event nlll0O57_event; initial #1 ->nlll0O57_event; always @(nlll0O57_event) nlll0O57 <= {1{1'b1}}; initial nlll0O58 = 0; always @ ( posedge fref) nlll0O58 <= nlll0O57; initial nllOOi55 = 0; always @ ( posedge fref) nllOOi55 <= nllOOi56; event nllOOi55_event; initial #1 ->nllOOi55_event; always @(nllOOi55_event) nllOOi55 <= {1{1'b1}}; initial nllOOi56 = 0; always @ ( posedge fref) nllOOi56 <= nllOOi55; initial nlO00i21 = 0; always @ ( posedge fref) nlO00i21 <= nlO00i22; event nlO00i21_event; initial #1 ->nlO00i21_event; always @(nlO00i21_event) nlO00i21 <= {1{1'b1}}; initial nlO00i22 = 0; always @ ( posedge fref) nlO00i22 <= nlO00i21; initial nlO00l19 = 0; always @ ( posedge fref) nlO00l19 <= nlO00l20; event nlO00l19_event; initial #1 ->nlO00l19_event; always @(nlO00l19_event) nlO00l19 <= {1{1'b1}}; initial nlO00l20 = 0; always @ ( posedge fref) nlO00l20 <= nlO00l19; initial nlO00O17 = 0; always @ ( posedge fref) nlO00O17 <= nlO00O18; event nlO00O17_event; initial #1 ->nlO00O17_event; always @(nlO00O17_event) nlO00O17 <= {1{1'b1}}; initial nlO00O18 = 0; always @ ( posedge fref) nlO00O18 <= nlO00O17; initial nlO01i27 = 0; always @ ( posedge fref) nlO01i27 <= nlO01i28; event nlO01i27_event; initial #1 ->nlO01i27_event; always @(nlO01i27_event) nlO01i27 <= {1{1'b1}}; initial nlO01i28 = 0; always @ ( posedge fref) nlO01i28 <= nlO01i27; initial nlO01l25 = 0; always @ ( posedge fref) nlO01l25 <= nlO01l26; event nlO01l25_event; initial #1 ->nlO01l25_event; always @(nlO01l25_event) nlO01l25 <= {1{1'b1}}; initial nlO01l26 = 0; always @ ( posedge fref) nlO01l26 <= nlO01l25; initial nlO01O23 = 0; always @ ( posedge fref) nlO01O23 <= nlO01O24; event nlO01O23_event; initial #1 ->nlO01O23_event; always @(nlO01O23_event) nlO01O23 <= {1{1'b1}}; initial nlO01O24 = 0; always @ ( posedge fref) nlO01O24 <= nlO01O23; initial nlO0ii15 = 0; always @ ( posedge fref) nlO0ii15 <= nlO0ii16; event nlO0ii15_event; initial #1 ->nlO0ii15_event; always @(nlO0ii15_event) nlO0ii15 <= {1{1'b1}}; initial nlO0ii16 = 0; always @ ( posedge fref) nlO0ii16 <= nlO0ii15; initial nlO0iO13 = 0; always @ ( posedge fref) nlO0iO13 <= nlO0iO14; event nlO0iO13_event; initial #1 ->nlO0iO13_event; always @(nlO0iO13_event) nlO0iO13 <= {1{1'b1}}; initial nlO0iO14 = 0; always @ ( posedge fref) nlO0iO14 <= nlO0iO13; initial nlO0ll11 = 0; always @ ( posedge fref) nlO0ll11 <= nlO0ll12; event nlO0ll11_event; initial #1 ->nlO0ll11_event; always @(nlO0ll11_event) nlO0ll11 <= {1{1'b1}}; initial nlO0ll12 = 0; always @ ( posedge fref) nlO0ll12 <= nlO0ll11; initial nlO0Oi10 = 0; always @ ( posedge fref) nlO0Oi10 <= nlO0Oi9; initial nlO0Oi9 = 0; always @ ( posedge fref) nlO0Oi9 <= nlO0Oi10; event nlO0Oi9_event; initial #1 ->nlO0Oi9_event; always @(nlO0Oi9_event) nlO0Oi9 <= {1{1'b1}}; initial nlO0Ol7 = 0; always @ ( posedge fref) nlO0Ol7 <= nlO0Ol8; event nlO0Ol7_event; initial #1 ->nlO0Ol7_event; always @(nlO0Ol7_event) nlO0Ol7 <= {1{1'b1}}; initial nlO0Ol8 = 0; always @ ( posedge fref) nlO0Ol8 <= nlO0Ol7; initial nlO10i47 = 0; always @ ( posedge fref) nlO10i47 <= nlO10i48; event nlO10i47_event; initial #1 ->nlO10i47_event; always @(nlO10i47_event) nlO10i47 <= {1{1'b1}}; initial nlO10i48 = 0; always @ ( posedge fref) nlO10i48 <= nlO10i47; initial nlO10l45 = 0; always @ ( posedge fref) nlO10l45 <= nlO10l46; event nlO10l45_event; initial #1 ->nlO10l45_event; always @(nlO10l45_event) nlO10l45 <= {1{1'b1}}; initial nlO10l46 = 0; always @ ( posedge fref) nlO10l46 <= nlO10l45; initial nlO10O43 = 0; always @ ( posedge fref) nlO10O43 <= nlO10O44; event nlO10O43_event; initial #1 ->nlO10O43_event; always @(nlO10O43_event) nlO10O43 <= {1{1'b1}}; initial nlO10O44 = 0; always @ ( posedge fref) nlO10O44 <= nlO10O43; initial nlO11i53 = 0; always @ ( posedge fref) nlO11i53 <= nlO11i54; event nlO11i53_event; initial #1 ->nlO11i53_event; always @(nlO11i53_event) nlO11i53 <= {1{1'b1}}; initial nlO11i54 = 0; always @ ( posedge fref) nlO11i54 <= nlO11i53; initial nlO11l51 = 0; always @ ( posedge fref) nlO11l51 <= nlO11l52; event nlO11l51_event; initial #1 ->nlO11l51_event; always @(nlO11l51_event) nlO11l51 <= {1{1'b1}}; initial nlO11l52 = 0; always @ ( posedge fref) nlO11l52 <= nlO11l51; initial nlO11O49 = 0; always @ ( posedge fref) nlO11O49 <= nlO11O50; event nlO11O49_event; initial #1 ->nlO11O49_event; always @(nlO11O49_event) nlO11O49 <= {1{1'b1}}; initial nlO11O50 = 0; always @ ( posedge fref) nlO11O50 <= nlO11O49; initial nlO1ii41 = 0; always @ ( posedge fref) nlO1ii41 <= nlO1ii42; event nlO1ii41_event; initial #1 ->nlO1ii41_event; always @(nlO1ii41_event) nlO1ii41 <= {1{1'b1}}; initial nlO1ii42 = 0; always @ ( posedge fref) nlO1ii42 <= nlO1ii41; initial nlO1li39 = 0; always @ ( posedge fref) nlO1li39 <= nlO1li40; event nlO1li39_event; initial #1 ->nlO1li39_event; always @(nlO1li39_event) nlO1li39 <= {1{1'b1}}; initial nlO1li40 = 0; always @ ( posedge fref) nlO1li40 <= nlO1li39; initial nlO1ll37 = 0; always @ ( posedge fref) nlO1ll37 <= nlO1ll38; event nlO1ll37_event; initial #1 ->nlO1ll37_event; always @(nlO1ll37_event) nlO1ll37 <= {1{1'b1}}; initial nlO1ll38 = 0; always @ ( posedge fref) nlO1ll38 <= nlO1ll37; initial nlO1lO35 = 0; always @ ( posedge fref) nlO1lO35 <= nlO1lO36; event nlO1lO35_event; initial #1 ->nlO1lO35_event; always @(nlO1lO35_event) nlO1lO35 <= {1{1'b1}}; initial nlO1lO36 = 0; always @ ( posedge fref) nlO1lO36 <= nlO1lO35; initial nlO1Oi33 = 0; always @ ( posedge fref) nlO1Oi33 <= nlO1Oi34; event nlO1Oi33_event; initial #1 ->nlO1Oi33_event; always @(nlO1Oi33_event) nlO1Oi33 <= {1{1'b1}}; initial nlO1Oi34 = 0; always @ ( posedge fref) nlO1Oi34 <= nlO1Oi33; initial nlO1Ol31 = 0; always @ ( posedge fref) nlO1Ol31 <= nlO1Ol32; event nlO1Ol31_event; initial #1 ->nlO1Ol31_event; always @(nlO1Ol31_event) nlO1Ol31 <= {1{1'b1}}; initial nlO1Ol32 = 0; always @ ( posedge fref) nlO1Ol32 <= nlO1Ol31; initial nlO1OO29 = 0; always @ ( posedge fref) nlO1OO29 <= nlO1OO30; event nlO1OO29_event; initial #1 ->nlO1OO29_event; always @(nlO1OO29_event) nlO1OO29 <= {1{1'b1}}; initial nlO1OO30 = 0; always @ ( posedge fref) nlO1OO30 <= nlO1OO29; initial nlOi0l3 = 0; always @ ( posedge fref) nlOi0l3 <= nlOi0l4; event nlOi0l3_event; initial #1 ->nlOi0l3_event; always @(nlOi0l3_event) nlOi0l3 <= {1{1'b1}}; initial nlOi0l4 = 0; always @ ( posedge fref) nlOi0l4 <= nlOi0l3; initial nlOi1l5 = 0; always @ ( posedge fref) nlOi1l5 <= nlOi1l6; event nlOi1l5_event; initial #1 ->nlOi1l5_event; always @(nlOi1l5_event) nlOi1l5 <= {1{1'b1}}; initial nlOi1l6 = 0; always @ ( posedge fref) nlOi1l6 <= nlOi1l5; initial nlOiil1 = 0; always @ ( posedge fref) nlOiil1 <= nlOiil2; event nlOiil1_event; initial #1 ->nlOiil1_event; always @(nlOiil1_event) nlOiil1 <= {1{1'b1}}; initial nlOiil2 = 0; always @ ( posedge fref) nlOiil2 <= nlOiil1; initial begin n0lOO = 0; end always @ ( posedge fvcobyn or posedge wire_nli0O_dataout) begin if (wire_nli0O_dataout == 1'b1) begin n0lOO <= 1; end else begin n0lOO <= wire_ni0ii_dataout; end end event n0lOO_event; initial #1 ->n0lOO_event; always @(n0lOO_event) n0lOO <= 1; initial begin n1i = 0; nii = 0; end always @ (fref or hard_reset or wire_n0O_CLRN) begin if (hard_reset == 1'b0) begin n1i <= 1; nii <= 1; end else if (wire_n0O_CLRN == 1'b0) begin n1i <= 0; nii <= 0; end else if (fref != n0O_clk_prev && fref == 1'b1) begin n1i <= nii; nii <= nlOi1O; end n0O_clk_prev <= fref; end assign wire_n0O_CLRN = (nlOi1l6 ^ nlOi1l5); event n1i_event; event nii_event; initial #1 ->n1i_event; initial #1 ->nii_event; always @(n1i_event) n1i <= 1; always @(nii_event) nii <= 1; initial begin n10iO = 0; n1ilO = 0; end always @ ( posedge fref or negedge wire_n1ill_CLRN) begin if (wire_n1ill_CLRN == 1'b0) begin n10iO <= 0; n1ilO <= 0; end else if (nlOi0i == 1'b1) begin n10iO <= (nlllii | ((((((((nllOil & wire_n1O1O_o) | (wire_n000l_o & nllO0O)) | (nllO0i & wire_n1lOl_o)) | (wire_n001l_o & nllO1l)) | (nlllOO & wire_n1liO_o)) | (wire_n01iO_o & nlllOi)) | (wire_n010l_o & nlllll)) | (wire_n011i_o & nllliO))); n1ilO <= (((((((((nllOil & wire_n000l_o) | (nllO0O & wire_n001l_o)) | (nllO0i & wire_n01Oi_o)) | (nllO1l & wire_n01iO_o)) | (nlllOO & wire_n010l_o)) | (nlllOi & wire_n011i_o)) | (nlllll & wire_n1OlO_o)) | (nllliO & wire_n1Oil_o)) | nlllii); end end assign wire_n1ill_CLRN = ((nlll0O58 ^ nlll0O57) & (~ wire_nlili_dataout)); initial begin n0lOi = 0; ni00O = 0; end always @ (fref or wire_nlili_dataout or wire_ni00l_CLRN) begin if (wire_nlili_dataout == 1'b1) begin n0lOi <= 1; ni00O <= 1; end else if (wire_ni00l_CLRN == 1'b0) begin n0lOi <= 0; ni00O <= 0; end else if (fref != ni00l_clk_prev && fref == 1'b1) begin n0lOi <= wire_n0O0l_dataout; ni00O <= wire_niO1l_dataout; end ni00l_clk_prev <= fref; end assign wire_ni00l_CLRN = (nllOOi56 ^ nllOOi55); event n0lOi_event; event ni00O_event; initial #1 ->n0lOi_event; initial #1 ->ni00O_event; always @(n0lOi_event) n0lOi <= 1; always @(ni00O_event) ni00O <= 1; initial begin nl0lO = 0; end always @ ( posedge fvcobyn or posedge wire_nli0O_dataout) begin if (wire_nli0O_dataout == 1'b1) begin nl0lO <= 0; end else if (nllOOO == 1'b1) begin nl0lO <= nlOi1i; end end initial begin ni00i = 0; ni01i = 0; ni01l = 0; ni01O = 0; ni10i = 0; ni10l = 0; ni10O = 0; ni11O = 0; ni1ii = 0; ni1il = 0; ni1iO = 0; ni1li = 0; ni1ll = 0; ni1lO = 0; ni1Oi = 0; ni1Ol = 0; ni1OO = 0; nl00O = 0; nl01l = 0; nl0Ol = 0; end always @ ( posedge fvcobyn or posedge wire_nli0O_dataout) begin if (wire_nli0O_dataout == 1'b1) begin ni00i <= 0; ni01i <= 0; ni01l <= 0; ni01O <= 0; ni10i <= 0; ni10l <= 0; ni10O <= 0; ni11O <= 0; ni1ii <= 0; ni1il <= 0; ni1iO <= 0; ni1li <= 0; ni1ll <= 0; ni1lO <= 0; ni1Oi <= 0; ni1Ol <= 0; ni1OO <= 0; nl00O <= 0; nl01l <= 0; nl0Ol <= 0; end else begin ni00i <= wire_niiiO_dataout; ni01i <= wire_nii0O_dataout; ni01l <= wire_niiii_dataout; ni01O <= wire_niiil_dataout; ni10i <= wire_ni0iO_dataout; ni10l <= wire_ni0li_dataout; ni10O <= wire_ni0ll_dataout; ni11O <= wire_ni0il_dataout; ni1ii <= wire_ni0lO_dataout; ni1il <= wire_ni0Oi_dataout; ni1iO <= wire_ni0Ol_dataout; ni1li <= wire_ni0OO_dataout; ni1ll <= wire_nii1i_dataout; ni1lO <= wire_nii1l_dataout; ni1Oi <= wire_nii1O_dataout; ni1Ol <= wire_nii0i_dataout; ni1OO <= wire_nii0l_dataout; nl00O <= nl1iO; nl01l <= nl00O; nl0Ol <= wire_nli1l_o; end end initial begin n00ii = 0; n00il = 0; n00iO = 0; n00li = 0; n00ll = 0; n00lO = 0; n00Oi = 0; n00Ol = 0; n0lli = 0; n0lll = 0; n0llO = 0; n100i = 0; n100l = 0; n100O = 0; n101l = 0; n101O = 0; n10ii = 0; n10il = 0; n1iOi = 0; n1iOO = 0; niiOl = 0; niiOO = 0; nil0i = 0; nil0l = 0; nil0O = 0; nil1i = 0; nil1l = 0; nil1O = 0; nilii = 0; nilil = 0; niliO = 0; nilli = 0; nilll = 0; nillO = 0; nilOi = 0; nilOl = 0; nilOO = 0; niO1i = 0; nl01i = 0; nl0ii = 0; nl0il = 0; nl0iO = 0; nl0li = 0; nl1iO = 0; nl1li = 0; nli1i = 0; end always @ ( posedge fref or negedge wire_nl0OO_CLRN) begin if (wire_nl0OO_CLRN == 1'b0) begin n00ii <= 0; n00il <= 0; n00iO <= 0; n00li <= 0; n00ll <= 0; n00lO <= 0; n00Oi <= 0; n00Ol <= 0; n0lli <= 0; n0lll <= 0; n0llO <= 0; n100i <= 0; n100l <= 0; n100O <= 0; n101l <= 0; n101O <= 0; n10ii <= 0; n10il <= 0; n1iOi <= 0; n1iOO <= 0; niiOl <= 0; niiOO <= 0; nil0i <= 0; nil0l <= 0; nil0O <= 0; nil1i <= 0; nil1l <= 0; nil1O <= 0; nilii <= 0; nilil <= 0; niliO <= 0; nilli <= 0; nilll <= 0; nillO <= 0; nilOi <= 0; nilOl <= 0; nilOO <= 0; niO1i <= 0; nl01i <= 0; nl0ii <= 0; nl0il <= 0; nl0iO <= 0; nl0li <= 0; nl1iO <= 0; nl1li <= 0; nli1i <= 0; end else begin n00ii <= wire_n0i1i_dataout; n00il <= wire_n0i1l_dataout; n00iO <= wire_n0i1O_dataout; n00li <= wire_n0i0i_dataout; n00ll <= wire_n0i0l_dataout; n00lO <= wire_n0i0O_dataout; n00Oi <= wire_n0iii_dataout; n00Ol <= wire_n0O1i_dataout; n0lli <= wire_n0O1l_dataout; n0lll <= wire_n0O1O_dataout; n0llO <= wire_n0O0i_dataout; n100i <= wire_n10Oi_dataout; n100l <= wire_n10Ol_dataout; n100O <= wire_n10OO_dataout; n101l <= wire_n10ll_dataout; n101O <= wire_n10lO_dataout; n10ii <= wire_n1i1i_dataout; n10il <= wire_n1i1l_dataout; n1iOi <= wire_n00OO_dataout; n1iOO <= wire_n10li_dataout; niiOl <= wire_niO1O_dataout; niiOO <= wire_niO0i_dataout; nil0i <= wire_niOil_dataout; nil0l <= wire_niOiO_dataout; nil0O <= wire_niOli_dataout; nil1i <= wire_niO0l_dataout; nil1l <= wire_niO0O_dataout; nil1O <= wire_niOii_dataout; nilii <= wire_niOll_dataout; nilil <= wire_niOlO_dataout; niliO <= wire_niOOi_dataout; nilli <= wire_niOOl_dataout; nilll <= wire_niOOO_dataout; nillO <= wire_nl11i_dataout; nilOi <= wire_nl11l_dataout; nilOl <= wire_nl11O_dataout; nilOO <= wire_nl10i_dataout; niO1i <= nl1iO; nl01i <= wire_nl00i_dataout; nl0ii <= nl0il; nl0il <= nl0Ol; nl0iO <= nl0li; nl0li <= nl0lO; nl1iO <= ((wire_nl1OO_o & wire_nl1Ol_o) | nllOOl); nl1li <= wire_nl01O_dataout; nli1i <= wire_nli0i_o; end end assign wire_nl0OO_CLRN = ((nlO11i54 ^ nlO11i53) & (~ wire_nlili_dataout)); initial begin nli1O = 0; nliil = 0; end always @ ( posedge fvcobyn or negedge wire_nliii_PRN) begin if (wire_nliii_PRN == 1'b0) begin nli1O <= 1; nliil <= 1; end else begin nli1O <= nliil; nliil <= pd; end end assign wire_nliii_PRN = ((nlO10l46 ^ nlO10l45) & (~ wire_nliOl_dataout)); event nli1O_event; event nliil_event; initial #1 ->nli1O_event; initial #1 ->nliil_event; always @(nli1O_event) nli1O <= 1; always @(nliil_event) nliil <= 1; initial begin nliiO = 0; nlilO = 0; end always @ ( posedge fref or negedge wire_nlill_PRN) begin if (wire_nlill_PRN == 1'b0) begin nliiO <= 1; nlilO <= 1; end else begin nliiO <= nlilO; nlilO <= pd; end end assign wire_nlill_PRN = ((nlO10O44 ^ nlO10O43) & (~ wire_nliOl_dataout)); event nliiO_event; event nlilO_event; initial #1 ->nliiO_event; initial #1 ->nlilO_event; always @(nliiO_event) nliiO <= 1; always @(nlilO_event) nlilO <= 1; initial begin nlli = 0; end always @ (fref or wire_n0l_dataout or wire_nliO_CLRN) begin if (wire_n0l_dataout == 1'b1) begin nlli <= 1; end else if (wire_nliO_CLRN == 1'b0) begin nlli <= 0; end else if (fref != nliO_clk_prev && fref == 1'b1) begin nlli <= (nlOi ^ nllO); end nliO_clk_prev <= fref; end assign wire_nliO_CLRN = (nlO0iO14 ^ nlO0iO13); event nlli_event; initial #1 ->nlli_event; always @(nlli_event) nlli <= 1; initial begin nlii = 0; nlil = 0; nliOi = 0; nll0i = 0; nll0l = 0; nll0O = 0; nll1l = 0; nll1O = 0; nllii = 0; nllil = 0; nlliO = 0; nllli = 0; nllll = 0; nlllO = 0; nllO = 0; nllOi = 0; nllOl = 0; nllOO = 0; nlO0i = 0; nlO0l = 0; nlO1i = 0; nlO1l = 0; nlO1O = 0; nlOi = 0; nlOO = 0; end always @ (fref or wire_nlOl_PRN or wire_nlOl_CLRN) begin if (wire_nlOl_PRN == 1'b0) begin nlii <= 1; nlil <= 1; nliOi <= 1; nll0i <= 1; nll0l <= 1; nll0O <= 1; nll1l <= 1; nll1O <= 1; nllii <= 1; nllil <= 1; nlliO <= 1; nllli <= 1; nllll <= 1; nlllO <= 1; nllO <= 1; nllOi <= 1; nllOl <= 1; nllOO <= 1; nlO0i <= 1; nlO0l <= 1; nlO1i <= 1; nlO1l <= 1; nlO1O <= 1; nlOi <= 1; nlOO <= 1; end else if (wire_nlOl_CLRN == 1'b0) begin nlii <= 0; nlil <= 0; nliOi <= 0; nll0i <= 0; nll0l <= 0; nll0O <= 0; nll1l <= 0; nll1O <= 0; nllii <= 0; nllil <= 0; nlliO <= 0; nllli <= 0; nllll <= 0; nlllO <= 0; nllO <= 0; nllOi <= 0; nllOl <= 0; nllOO <= 0; nlO0i <= 0; nlO0l <= 0; nlO1i <= 0; nlO1l <= 0; nlO1O <= 0; nlOi <= 0; nlOO <= 0; end else if (fref != nlOl_clk_prev && fref == 1'b1) begin nlii <= nlil; nlil <= eidle_exit; nliOi <= wire_nlO0O_dataout; nll0i <= wire_nlOiO_dataout; nll0l <= wire_nlOli_dataout; nll0O <= wire_nlOll_dataout; nll1l <= wire_nlOii_dataout; nll1O <= wire_nlOil_dataout; nllii <= wire_nlOlO_dataout; nllil <= wire_nlOOi_dataout; nlliO <= wire_nlOOl_dataout; nllli <= wire_nlOOO_dataout; nllll <= wire_n11i_dataout; nlllO <= wire_n11l_dataout; nllO <= nlOi; nllOi <= wire_n11O_dataout; nllOl <= wire_n10i_dataout; nllOO <= wire_n10l_dataout; nlO0i <= wire_n1iO_dataout; nlO0l <= nlii; nlO1i <= wire_n10O_dataout; nlO1l <= wire_n1ii_dataout; nlO1O <= wire_n1il_dataout; nlOi <= nlOO; nlOO <= (~ nlO0OO); end nlOl_clk_prev <= fref; end assign wire_nlOl_CLRN = ((nlO0Ol8 ^ nlO0Ol7) & (~ wire_n0l_dataout)), wire_nlOl_PRN = (nlO0Oi10 ^ nlO0Oi9); and(wire_n00i_dataout, wire_niii_dataout, wire_nl0l_o); and(wire_n00l_dataout, wire_niil_dataout, wire_nl0l_o); and(wire_n00O_dataout, wire_niiO_dataout, wire_nl0l_o); and(wire_n00OO_dataout, wire_n0iil_dataout, ~((~ nlOiii))); and(wire_n01i_dataout, wire_ni0i_dataout, wire_nl0l_o); and(wire_n01l_dataout, wire_ni0l_dataout, wire_nl0l_o); and(wire_n01O_dataout, wire_ni0O_dataout, wire_nl0l_o); assign wire_n0i_dataout = (rindv_rx === 1'b1) ? gen2ngen1_indv : gen2ngen1_bundle; and(wire_n0i0i_dataout, wire_n0ilO_dataout, ~((~ nlOiii))); and(wire_n0i0l_dataout, wire_n0iOi_dataout, ~((~ nlOiii))); and(wire_n0i0O_dataout, wire_n0iOl_dataout, ~((~ nlOiii))); and(wire_n0i1i_dataout, wire_n0iiO_dataout, ~((~ nlOiii))); and(wire_n0i1l_dataout, wire_n0ili_dataout, ~((~ nlOiii))); and(wire_n0i1O_dataout, wire_n0ill_dataout, ~((~ nlOiii))); and(wire_n0ii_dataout, wire_nili_dataout, wire_nl0l_o); and(wire_n0iii_dataout, wire_n0iOO_dataout, ~((~ nlOiii))); or(wire_n0iil_dataout, wire_n0l1i_dataout, nllOli); or(wire_n0iiO_dataout, wire_n0l1l_dataout, nllOli); and(wire_n0il_dataout, wire_nill_dataout, wire_nl0l_o); or(wire_n0ili_dataout, wire_n0l1O_dataout, nllOli); or(wire_n0ill_dataout, wire_n0l0i_dataout, nllOli); or(wire_n0ilO_dataout, wire_n0l0l_dataout, nllOli); and(wire_n0iO_dataout, wire_nilO_dataout, wire_nl0l_o); or(wire_n0iOi_dataout, wire_n0l0O_dataout, nllOli); or(wire_n0iOl_dataout, wire_n0lii_dataout, nllOli); or(wire_n0iOO_dataout, wire_n0lil_dataout, nllOli); and(wire_n0l_dataout, n1i, ~(scan_mode)); assign wire_n0l0i_dataout = (nl1li === 1'b1) ? wire_n0liO_o[3] : n00iO; assign wire_n0l0l_dataout = (nl1li === 1'b1) ? wire_n0liO_o[4] : n00li; assign wire_n0l0O_dataout = (nl1li === 1'b1) ? wire_n0liO_o[5] : n00ll; assign wire_n0l1i_dataout = (nl1li === 1'b1) ? wire_n0liO_o[0] : n1iOi; assign wire_n0l1l_dataout = (nl1li === 1'b1) ? wire_n0liO_o[1] : n00ii; assign wire_n0l1O_dataout = (nl1li === 1'b1) ? wire_n0liO_o[2] : n00il; and(wire_n0li_dataout, wire_niOi_dataout, wire_nl0l_o); assign wire_n0lii_dataout = (nl1li === 1'b1) ? wire_n0liO_o[6] : n00lO; assign wire_n0lil_dataout = (nl1li === 1'b1) ? wire_n0liO_o[7] : n00Oi; and(wire_n0ll_dataout, wire_niOl_dataout, wire_nl0l_o); and(wire_n0lO_dataout, wire_niOO_dataout, wire_nl0l_o); and(wire_n0O0i_dataout, wire_n0Oil_dataout, ~((~ nlOiii))); or(wire_n0O0l_dataout, wire_n0OiO_dataout, (~ nlOiii)); assign wire_n0O0O_dataout = (nllOlO === 1'b1) ? n0lli : wire_n0Oll_dataout; and(wire_n0O1i_dataout, wire_n0Oli_dataout, ~((~ nlOiii))); and(wire_n0O1l_dataout, wire_n0O0O_dataout, ~((~ nlOiii))); and(wire_n0O1O_dataout, wire_n0Oii_dataout, ~((~ nlOiii))); and(wire_n0Oi_dataout, wire_nl1i_dataout, wire_nl0l_o); assign wire_n0Oii_dataout = (nllOlO === 1'b1) ? n0lll : wire_n0OlO_dataout; assign wire_n0Oil_dataout = (nllOlO === 1'b1) ? n0llO : wire_n0OOi_dataout; assign wire_n0OiO_dataout = (nllOlO === 1'b1) ? n0lOi : wire_n0OOl_dataout; and(wire_n0Ol_dataout, nlO1iO, wire_nl1O_o); or(wire_n0Oli_dataout, n00Ol, nllOlO); assign wire_n0Oll_dataout = (nllOll === 1'b1) ? wire_n0OOO_o[1] : n0lli; assign wire_n0OlO_dataout = (nllOll === 1'b1) ? wire_n0OOO_o[2] : n0lll; and(wire_n0OO_dataout, wire_nl1l_o[0], wire_nl1O_o); assign wire_n0OOi_dataout = (nllOll === 1'b1) ? wire_n0OOO_o[3] : n0llO; assign wire_n0OOl_dataout = (nllOll === 1'b1) ? wire_n0OOO_o[4] : n0lOi; assign wire_n101i_dataout = (nlO0li === 1'b1) ? n10iO : n1ilO; and(wire_n10i_dataout, wire_n0il_dataout, ~(nlO0il)); and(wire_n10l_dataout, wire_n0iO_dataout, ~(nlO0il)); and(wire_n10li_dataout, wire_n1i1O_dataout, ~(ppm_cnt_reset)); and(wire_n10ll_dataout, wire_n1i0i_dataout, ~(ppm_cnt_reset)); and(wire_n10lO_dataout, wire_n1i0l_dataout, ~(ppm_cnt_reset)); and(wire_n10O_dataout, wire_n0li_dataout, ~(nlO0il)); and(wire_n10Oi_dataout, wire_n1i0O_dataout, ~(ppm_cnt_reset)); and(wire_n10Ol_dataout, wire_n1iii_dataout, ~(ppm_cnt_reset)); and(wire_n10OO_dataout, wire_n1iil_dataout, ~(ppm_cnt_reset)); and(wire_n11i_dataout, wire_n00l_dataout, ~(nlO0il)); and(wire_n11l_dataout, wire_n00O_dataout, ~(nlO0il)); and(wire_n11O_dataout, wire_n0ii_dataout, ~(nlO0il)); or(wire_n11Oi_dataout, wire_n11Ol_dataout, nll1l); or(wire_n11Ol_dataout, wire_n11OO_dataout, rforcehigh); and(wire_n11OO_dataout, wire_n101i_dataout, ~(rforcelow)); assign wire_n1i0i_dataout = (nlOi0i === 1'b1) ? n00ii : n101l; assign wire_n1i0l_dataout = (nlOi0i === 1'b1) ? n00il : n101O; assign wire_n1i0O_dataout = (nlOi0i === 1'b1) ? n00iO : n100i; and(wire_n1i1i_dataout, wire_n1iiO_dataout, ~(ppm_cnt_reset)); and(wire_n1i1l_dataout, wire_n1ili_dataout, ~(ppm_cnt_reset)); assign wire_n1i1O_dataout = (nlOi0i === 1'b1) ? n1iOi : n1iOO; and(wire_n1ii_dataout, wire_n0ll_dataout, ~(nlO0il)); assign wire_n1iii_dataout = (nlOi0i === 1'b1) ? n00li : n100l; assign wire_n1iil_dataout = (nlOi0i === 1'b1) ? n00ll : n100O; assign wire_n1iiO_dataout = (nlOi0i === 1'b1) ? n00lO : n10ii; and(wire_n1il_dataout, wire_n0lO_dataout, ~(nlO0il)); assign wire_n1ili_dataout = (nlOi0i === 1'b1) ? n00Oi : n10il; and(wire_n1iO_dataout, wire_n0Oi_dataout, ~(nlO0il)); and(wire_n1li_dataout, wire_n0Ol_dataout, wire_nl0l_o); and(wire_n1ll_dataout, wire_nl1O_o, wire_nl0l_o); and(wire_n1lO_dataout, wire_n0OO_dataout, wire_nl0l_o); and(wire_n1Oi_dataout, wire_ni1i_dataout, wire_nl0l_o); and(wire_n1Ol_dataout, wire_ni1l_dataout, wire_nl0l_o); and(wire_n1OO_dataout, wire_ni1O_dataout, wire_nl0l_o); and(wire_ni0i_dataout, wire_nl1l_o[4], wire_nl1O_o); or(wire_ni0ii_dataout, (~ (((~ nlO0li) & ni01O) | (nlO0li & ni00i))), nl01l); and(wire_ni0il_dataout, wire_niiOi_o[0], ~(nl01l)); and(wire_ni0iO_dataout, wire_niiOi_o[1], ~(nl01l)); and(wire_ni0l_dataout, wire_nl1l_o[5], wire_nl1O_o); and(wire_ni0li_dataout, wire_niiOi_o[2], ~(nl01l)); and(wire_ni0ll_dataout, wire_niiOi_o[3], ~(nl01l)); and(wire_ni0lO_dataout, wire_niiOi_o[4], ~(nl01l)); and(wire_ni0O_dataout, wire_nl1l_o[6], wire_nl1O_o); and(wire_ni0Oi_dataout, wire_niiOi_o[5], ~(nl01l)); and(wire_ni0Ol_dataout, wire_niiOi_o[6], ~(nl01l)); and(wire_ni0OO_dataout, wire_niiOi_o[7], ~(nl01l)); and(wire_ni1i_dataout, wire_nl1l_o[1], wire_nl1O_o); and(wire_ni1l_dataout, wire_nl1l_o[2], wire_nl1O_o); and(wire_ni1O_dataout, wire_nl1l_o[3], wire_nl1O_o); and(wire_nii0i_dataout, wire_niiOi_o[11], ~(nl01l)); and(wire_nii0l_dataout, wire_niiOi_o[12], ~(nl01l)); and(wire_nii0O_dataout, wire_niiOi_o[13], ~(nl01l)); and(wire_nii1i_dataout, wire_niiOi_o[8], ~(nl01l)); and(wire_nii1l_dataout, wire_niiOi_o[9], ~(nl01l)); and(wire_nii1O_dataout, wire_niiOi_o[10], ~(nl01l)); and(wire_niii_dataout, wire_nl1l_o[7], wire_nl1O_o); and(wire_niiii_dataout, wire_niiOi_o[14], ~(nl01l)); and(wire_niiil_dataout, wire_niiOi_o[15], ~(nl01l)); and(wire_niiiO_dataout, wire_niiOi_o[16], ~(nl01l)); and(wire_niil_dataout, wire_nl1l_o[8], wire_nl1O_o); and(wire_niiO_dataout, wire_nl1l_o[9], wire_nl1O_o); and(wire_nili_dataout, wire_nl1l_o[10], wire_nl1O_o); and(wire_nill_dataout, wire_nl1l_o[11], wire_nl1O_o); and(wire_nilO_dataout, wire_nl1l_o[12], wire_nl1O_o); and(wire_niO0i_dataout, wire_nl1il_o[1], ~(niO1i)); and(wire_niO0l_dataout, wire_nl1il_o[2], ~(niO1i)); and(wire_niO0O_dataout, wire_nl1il_o[3], ~(niO1i)); or(wire_niO1l_dataout, (~ (((~ nlO0li) & nilOl) | (nlO0li & nilOO))), niO1i); and(wire_niO1O_dataout, wire_nl1il_o[0], ~(niO1i)); and(wire_niOi_dataout, wire_nl1l_o[13], wire_nl1O_o); and(wire_niOii_dataout, wire_nl1il_o[4], ~(niO1i)); and(wire_niOil_dataout, wire_nl1il_o[5], ~(niO1i)); and(wire_niOiO_dataout, wire_nl1il_o[6], ~(niO1i)); and(wire_niOl_dataout, wire_nl1l_o[14], wire_nl1O_o); and(wire_niOli_dataout, wire_nl1il_o[7], ~(niO1i)); and(wire_niOll_dataout, wire_nl1il_o[8], ~(niO1i)); and(wire_niOlO_dataout, wire_nl1il_o[9], ~(niO1i)); and(wire_niOO_dataout, wire_nl1l_o[15], wire_nl1O_o); and(wire_niOOi_dataout, wire_nl1il_o[10], ~(niO1i)); and(wire_niOOl_dataout, wire_nl1il_o[11], ~(niO1i)); and(wire_niOOO_dataout, wire_nl1il_o[12], ~(niO1i)); and(wire_nl00i_dataout, wire_nl00l_dataout, ~((~ nl0iO))); and(wire_nl00l_dataout, (ni00O ^ n0lOO), (((n0lOi & (~ n0llO)) & (~ n0lll)) & (~ n0lli))); and(wire_nl01O_dataout, nl01i, ~((~ nl0iO))); and(wire_nl10i_dataout, wire_nl1il_o[16], ~(niO1i)); and(wire_nl11i_dataout, wire_nl1il_o[13], ~(niO1i)); and(wire_nl11l_dataout, wire_nl1il_o[14], ~(niO1i)); and(wire_nl11O_dataout, wire_nl1il_o[15], ~(niO1i)); and(wire_nl1i_dataout, wire_nl1l_o[16], wire_nl1O_o); and(wire_nli0O_dataout, nli1O, ~(scan_mode)); and(wire_nlili_dataout, nliiO, ~(scan_mode)); and(wire_nliOl_dataout, (wire_n0l_dataout | ((nlli | nliOi) | (~ (nlO1ii42 ^ nlO1ii41)))), ~(scan_mode)); and(wire_nlO0O_dataout, wire_n1li_dataout, ~(nlO0il)); or(wire_nlOii_dataout, wire_n1ll_dataout, nlO0il); or(wire_nlOil_dataout, wire_n1lO_dataout, nlO0il); and(wire_nlOiO_dataout, wire_n1Oi_dataout, ~(nlO0il)); and(wire_nlOli_dataout, wire_n1Ol_dataout, ~(nlO0il)); and(wire_nlOll_dataout, wire_n1OO_dataout, ~(nlO0il)); and(wire_nlOlO_dataout, wire_n01i_dataout, ~(nlO0il)); and(wire_nlOOi_dataout, wire_n01l_dataout, ~(nlO0il)); and(wire_nlOOl_dataout, wire_n01O_dataout, ~(nlO0il)); and(wire_nlOOO_dataout, wire_n00i_dataout, ~(nlO0il)); oper_add n0liO ( .a({n00Oi, n00lO, n00ll, n00li, n00iO, n00il, n00ii, n1iOi}), .b({{7{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_n0liO_o)); defparam n0liO.sgate_representation = 0, n0liO.width_a = 8, n0liO.width_b = 8, n0liO.width_o = 8; oper_add n0OOO ( .a({n0lOi, n0llO, n0lll, n0lli, 1'b1}), .b({{3{1'b1}}, 1'b0, 1'b1}), .cin(1'b0), .cout(), .o(wire_n0OOO_o)); defparam n0OOO.sgate_representation = 0, n0OOO.width_a = 5, n0OOO.width_b = 5, n0OOO.width_o = 5; oper_add niiOi ( .a({ni00i, ni01O, ni01l, ni01i, ni1OO, ni1Ol, ni1Oi, ni1lO, ni1ll, ni1li, ni1iO, ni1il, ni1ii, ni10O, ni10l, ni10i, ni11O}), .b({{16{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_niiOi_o)); defparam niiOi.sgate_representation = 0, niiOi.width_a = 17, niiOi.width_b = 17, niiOi.width_o = 17; oper_add nl0i ( .a({1'b0, nlO0li, (~ nlO0li), {7{1'b0}}, ((nlO01O24 ^ nlO01O23) & nlO0li), {2{(~ nlO0li)}}, {5{1'b0}}}), .b({{9{1'b0}}, rppm_post_eidle_del, 1'b1, (~ rppm_post_eidle_del), 1'b0, rppm_post_eidle_del, (~ rppm_post_eidle_del), {3{1'b0}}}), .cin(1'b0), .cout(), .o(wire_nl0i_o)); defparam nl0i.sgate_representation = 0, nl0i.width_a = 18, nl0i.width_b = 18, nl0i.width_o = 18; oper_add nl1il ( .a({nilOO, nilOl, nilOi, nillO, nilll, nilli, niliO, nilil, nilii, nil0O, nil0l, nil0i, nil1O, nil1l, nil1i, niiOO, niiOl}), .b({{16{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_nl1il_o)); defparam nl1il.sgate_representation = 0, nl1il.width_a = 17, nl1il.width_b = 17, nl1il.width_o = 17; oper_add nl1l ( .a({((nlO1li40 ^ nlO1li39) & nlO0i), nlO1O, nlO1l, ((nlO1ll38 ^ nlO1ll37) & nlO1i), nllOO, nllOl, nllOi, ((nlO1lO36 ^ nlO1lO35) & nlllO), nllll, nllli, nlliO, nllil, nllii, nll0O, nll0l, nll0i, nll1O}), .b({{16{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_nl1l_o)); defparam nl1l.sgate_representation = 0, nl1l.width_a = 17, nl1l.width_b = 17, nl1l.width_o = 17; oper_add nli0l ( .a({nlO0li, ((nlO10i48 ^ nlO10i47) & (~ nlO0li)), {11{1'b0}}}), .b({{12{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_nli0l_o)); defparam nli0l.sgate_representation = 0, nli0l.width_a = 13, nli0l.width_b = 13, nli0l.width_o = 13; oper_less_than n000l ( .a({n00Oi, n00lO, n00ll, n00li, n00iO, n00il, n00ii, n1iOi}), .b({1'b0, 1'b1, {4{1'b0}}, {2{1'b1}}}), .cin(1'b1), .o(wire_n000l_o)); defparam n000l.sgate_representation = 0, n000l.width_a = 8, n000l.width_b = 8; oper_less_than n001l ( .a({n00Oi, n00lO, n00ll, n00li, n00iO, n00il, n00ii, n1iOi}), .b({{2{1'b0}}, 1'b1, {3{1'b0}}, 1'b1, 1'b0}), .cin(1'b1), .o(wire_n001l_o)); defparam n001l.sgate_representation = 0, n001l.width_a = 8, n001l.width_b = 8; oper_less_than n010l ( .a({n00Oi, n00lO, n00ll, n00li, n00iO, n00il, n00ii, n1iOi}), .b({{4{1'b0}}, {4{1'b1}}}), .cin(1'b1), .o(wire_n010l_o)); defparam n010l.sgate_representation = 0, n010l.width_a = 8, n010l.width_b = 8; oper_less_than n011i ( .a({n00Oi, n00lO, n00ll, n00li, n00iO, n00il, n00ii, n1iOi}), .b({{4{1'b0}}, 1'b1, 1'b0, 1'b1, 1'b0}), .cin(1'b1), .o(wire_n011i_o)); defparam n011i.sgate_representation = 0, n011i.width_a = 8, n011i.width_b = 8; oper_less_than n01iO ( .a({n00Oi, n00lO, n00ll, n00li, n00iO, n00il, n00ii, n1iOi}), .b({{3{1'b0}}, 1'b1, {2{1'b0}}, 1'b1, 1'b0}), .cin(1'b1), .o(wire_n01iO_o)); defparam n01iO.sgate_representation = 0, n01iO.width_a = 8, n01iO.width_b = 8; oper_less_than n01Oi ( .a({n00Oi, n00lO, n00ll, n00li, n00iO, n00il, n00ii, n1iOi}), .b({{3{1'b0}}, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1}), .cin(1'b1), .o(wire_n01Oi_o)); defparam n01Oi.sgate_representation = 0, n01Oi.width_a = 8, n01Oi.width_b = 8; oper_less_than n1liO ( .a({n00Oi, n00lO, n00ll, n00li, n00iO, n00il, n00ii, n1iOi}), .b({{3{1'b0}}, {3{1'b1}}, {2{1'b0}}}), .cin(1'b1), .o(wire_n1liO_o)); defparam n1liO.sgate_representation = 0, n1liO.width_a = 8, n1liO.width_b = 8; oper_less_than n1lOl ( .a({n00Oi, n00lO, n00ll, n00li, n00iO, n00il, n00ii, n1iOi}), .b({{2{1'b0}}, 1'b1, 1'b0, 1'b1, {2{1'b0}}, 1'b1}), .cin(1'b1), .o(wire_n1lOl_o)); defparam n1lOl.sgate_representation = 0, n1lOl.width_a = 8, n1lOl.width_b = 8; oper_less_than n1O1O ( .a({n00Oi, n00lO, n00ll, n00li, n00iO, n00il, n00ii, n1iOi}), .b({1'b1, {4{1'b0}}, 1'b1, 1'b0, 1'b1}), .cin(1'b1), .o(wire_n1O1O_o)); defparam n1O1O.sgate_representation = 0, n1O1O.width_a = 8, n1O1O.width_b = 8; oper_less_than n1Oil ( .a({n00Oi, n00lO, n00ll, n00li, n00iO, n00il, n00ii, n1iOi}), .b({{5{1'b0}}, {2{1'b1}}, 1'b0}), .cin(1'b1), .o(wire_n1Oil_o)); defparam n1Oil.sgate_representation = 0, n1Oil.width_a = 8, n1Oil.width_b = 8; oper_less_than n1OlO ( .a({n00Oi, n00lO, n00ll, n00li, n00iO, n00il, n00ii, n1iOi}), .b({{4{1'b0}}, 1'b1, {3{1'b0}}}), .cin(1'b1), .o(wire_n1OlO_o)); defparam n1OlO.sgate_representation = 0, n1OlO.width_a = 8, n1OlO.width_b = 8; oper_less_than nl0l ( .a({17{1'b0}}), .b({nlO0i, nlO1O, nlO1l, nlO1i, ((nlO00i22 ^ nlO00i21) & nllOO), ((nlO00l20 ^ nlO00l19) & nllOl), nllOi, nlllO, nllll, ((nlO00O18 ^ nlO00O17) & nllli), nlliO, nllil, nllii, ((nlO0ii16 ^ nlO0ii15) & nll0O), nll0l, nll0i, nll1O}), .cin(1'b0), .o(wire_nl0l_o)); defparam nl0l.sgate_representation = 0, nl0l.width_a = 17, nl0l.width_b = 17; oper_less_than nl1O ( .a({1'b0, nlO0i, nlO1O, nlO1l, nlO1i, ((nlO1Ol32 ^ nlO1Ol31) & nllOO), nllOl, nllOi, ((nlO1OO30 ^ nlO1OO29) & nlllO), nllll, nllli, nlliO, nllil, nllii, nll0O, ((nlO01i28 ^ nlO01i27) & nll0l), ((nlO01l26 ^ nlO01l25) & nll0i), nll1O}), .b({wire_nl0i_o[17:10], ((nlO1Oi34 ^ nlO1Oi33) & wire_nl0i_o[9]), wire_nl0i_o[8:0]}), .cin(1'b0), .o(wire_nl1O_o)); defparam nl1O.sgate_representation = 0, nl1O.width_a = 18, nl1O.width_b = 18; oper_less_than nl1Ol ( .a({n0lOi, n0llO, n0lll, n0lli}), .b({1'b1, {3{1'b0}}}), .cin(1'b0), .o(wire_nl1Ol_o)); defparam nl1Ol.sgate_representation = 0, nl1Ol.width_a = 4, nl1Ol.width_b = 4; oper_less_than nl1OO ( .a({4{1'b0}}), .b({n0lOi, n0llO, n0lll, n0lli}), .cin(1'b0), .o(wire_nl1OO_o)); defparam nl1OO.sgate_representation = 0, nl1OO.width_a = 4, nl1OO.width_b = 4; oper_less_than nli0i ( .a({((nlO11O50 ^ nlO11O49) & wire_nli0l_o[12]), wire_nli0l_o[11:0], {4{1'b0}}}), .b({nilOO, nilOl, nilOi, nillO, nilll, nilli, niliO, nilil, nilii, nil0O, nil0l, nil0i, nil1O, nil1l, nil1i, niiOO, ((nlO11l52 ^ nlO11l51) & niiOl)}), .cin(1'b0), .o(wire_nli0i_o)); defparam nli0i.sgate_representation = 0, nli0i.width_a = 17, nli0i.width_b = 17; oper_less_than nli1l ( .a({wire_nli0l_o[12:0], {4{1'b0}}}), .b({ni00i, ni01O, ni01l, ni01i, ni1OO, ni1Ol, ni1Oi, ni1lO, ni1ll, ni1li, ni1iO, ni1il, ni1ii, ni10O, ni10l, ni10i, ni11O}), .cin(1'b0), .o(wire_nli1l_o)); defparam nli1l.sgate_representation = 0, nli1l.width_a = 17, nli1l.width_b = 17; assign freq_lock = wire_n11Oi_dataout, nlllii = (nlOi0i & nlllil), nlllil = (((((ppmsel[0] & ppmsel[1]) & ppmsel[2]) & ppmsel[3]) & ppmsel[4]) & ppmsel[5]), nllliO = (nlOi0i & nlllli), nlllli = (((((ppmsel[0] & ppmsel[1]) & (~ ppmsel[2])) & (~ ppmsel[3])) & (~ ppmsel[4])) & (~ ppmsel[5])), nlllll = (nlOi0i & nllllO), nllllO = (((((ppmsel[0] & (~ ppmsel[1])) & (~ ppmsel[2])) & (~ ppmsel[3])) & (~ ppmsel[4])) & (~ ppmsel[5])), nlllOi = (nlOi0i & nlllOl), nlllOl = ((((((~ ppmsel[0]) & ppmsel[1]) & (~ ppmsel[2])) & (~ ppmsel[3])) & (~ ppmsel[4])) & (~ ppmsel[5])), nlllOO = (nlOi0i & nllO1i), nllO0i = (nlOi0i & nllO0l), nllO0l = ((((((~ ppmsel[0]) & (~ ppmsel[1])) & (~ ppmsel[2])) & ppmsel[3]) & (~ ppmsel[4])) & (~ ppmsel[5])), nllO0O = (nlOi0i & nllOii), nllO1i = ((((((~ ppmsel[0]) & (~ ppmsel[1])) & ppmsel[2]) & (~ ppmsel[3])) & (~ ppmsel[4])) & (~ ppmsel[5])), nllO1l = (nlOi0i & nllO1O), nllO1O = (((((ppmsel[0] & (~ ppmsel[1])) & (~ ppmsel[2])) & ppmsel[3]) & (~ ppmsel[4])) & (~ ppmsel[5])), nllOii = ((((((~ ppmsel[0]) & (~ ppmsel[1])) & (~ ppmsel[2])) & (~ ppmsel[3])) & ppmsel[4]) & (~ ppmsel[5])), nllOil = (nlOi0i & nllOiO), nllOiO = ((((((~ ppmsel[0]) & (~ ppmsel[1])) & (~ ppmsel[2])) & (~ ppmsel[3])) & (~ ppmsel[4])) & ppmsel[5]), nllOli = (((((((n00Oi & n00lO) & n00ll) & n00li) & n00iO) & n00il) & n00ii) & n1iOi), nllOll = ((~ nl1li) & n00Ol), nllOlO = (nllOOl | nl1li), nllOOl = (nli1i & nl0ii), nllOOO = (((((((((((((((((~ ni00i) & (~ ni01O)) & (~ ni01l)) & (~ ni01i)) & (~ ni1OO)) & (~ ni1Ol)) & (~ ni1Oi)) & (~ ni1lO)) & (~ ni1ll)) & ni1li) & ni1iO) & ni1il) & ni1ii) & ni10O) & ni10l) & ni10i) & ni11O), nlO0il = (nlii & (~ nlO0l)), nlO0li = ((nlO0OO & rppm_gen1_2xcnt_en) & (nlO0ll12 ^ nlO0ll11)), nlO0OO = ((~ wire_n0i_dataout) & rauto_speed_ena), nlO1iO = (((((((((((((((((~ nlO0i) & (~ nlO1O)) & (~ nlO1l)) & (~ nlO1i)) & (~ nllOO)) & (~ nllOl)) & (~ nllOi)) & (~ nlllO)) & nllli) & (~ nllil)) & (~ nll0l)) & (~ nll0i)) & (~ nll1O)) & (~ (nll0O ^ (~ rppm_post_eidle_del)))) & (~ (nllii ^ rppm_post_eidle_del))) & (~ (nlliO ^ (~ rppm_post_eidle_del)))) & (~ (nllll ^ rppm_post_eidle_del))), nlOi0i = (((((~ n0lOi) & n0llO) & (~ n0lll)) & (nlOi0l4 ^ nlOi0l3)) & (~ n0lli)), nlOi1i = 1'b1, nlOi1O = 1'b0, nlOiii = ((((n0lOi | n0llO) | n0lll) | n0lli) | (~ (nlOiil2 ^ nlOiil1))), ppm_cnt_latch = {n10il, n10ii, n100O, n100l, n100i, n101O, n101l, n1iOO}; endmodule //stratixiv_hssi_rx_digi_freqdet //synopsys translate_on //VALID FILE //IP Functional Simulation Model //VERSION_BEGIN 12.0 cbx_mgl 2012:05:31:20:09:47:SJ cbx_simgen 2012:05:31:20:08:35:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 // Copyright (C) 1991-2012 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // You may only use these simulation model output files for simulation // purposes and expressly not for synthesis or any other purposes (in which // event Altera disclaims all warranties of any kind). //synopsys translate_off //synthesis_resources = lut 177 mux21 115 oper_add 3 oper_decoder 3 oper_less_than 2 oper_mux 1 oper_selector 4 `timescale 1 ps / 1 ps module stratixiv_hssi_rx_digi_eii_module ( eidleinfersel, eiosdetect_int, gen2ngen1, gen2ngen1_bundle, inferred_rxvalid, kcount, kflag, pipe_loopbk, rcvd_clk, reidle_com_detect, reidleinferenable, rgen1_sigdet_ena, riei_eios_priority_dis, rindv_rx, rwait_count, rxelecidle_int, rxpcsrst, signaldetect, skposdetect, sudi, syncstatus) /* synthesis synthesis_clearbox=1 */; input [2:0] eidleinfersel; input eiosdetect_int; input gen2ngen1; input gen2ngen1_bundle; input inferred_rxvalid; input [1:0] kcount; input kflag; input pipe_loopbk; input rcvd_clk; input [1:0] reidle_com_detect; input reidleinferenable; input rgen1_sigdet_ena; input riei_eios_priority_dis; input rindv_rx; input [7:0] rwait_count; output rxelecidle_int; input rxpcsrst; input signaldetect; input skposdetect; input [15:0] sudi; input syncstatus; reg niOi0l51; reg niOi0l52; reg niOi0O49; reg niOi0O50; reg nl000l23; reg nl000l24; reg nl001l25; reg nl001l26; reg nl00ii21; reg nl00ii22; reg nl00ll19; reg nl00ll20; reg nl00lO17; reg nl00lO18; reg nl00Oi15; reg nl00Oi16; reg nl00Ol13; reg nl00Ol14; reg nl011l37; reg nl011l38; reg nl01ii35; reg nl01ii36; reg nl01iO33; reg nl01iO34; reg nl01ll31; reg nl01ll32; reg nl01Oi29; reg nl01Oi30; reg nl01OO27; reg nl01OO28; reg nl0i0i10; reg nl0i0i9; reg nl0i0l7; reg nl0i0l8; reg nl0i1i11; reg nl0i1i12; reg nl0iii5; reg nl0iii6; reg nl0ili3; reg nl0ili4; reg nl0iOi1; reg nl0iOi2; reg nl1lOO47; reg nl1lOO48; reg nl1O1l45; reg nl1O1l46; reg nl1Oii43; reg nl1Oii44; reg nl1Oll41; reg nl1Oll42; reg nl1OOl39; reg nl1OOl40; reg n0l; reg n0OlO; reg n0OOi; reg n0OOl; reg n0OOO; reg n1Ol; reg n1OlO; reg n1OO; reg ni00i; reg ni00l; reg ni00O; reg ni01i; reg ni01l; reg ni01O; reg ni0i; reg ni0il; reg ni0iO; reg ni0li; reg ni0ll; reg ni0lO; reg ni0Oi; reg ni0Ol; reg ni0OO; reg ni10i; reg ni10l; reg ni10O; reg ni11i; reg ni11l; reg ni11O; reg ni1ii; reg ni1il; reg ni1iO; reg ni1li; reg ni1ll; reg ni1lO; reg ni1Oi; reg ni1Ol; reg ni1OO; reg nii0i; reg nii0l; reg nii0O; reg nii1i; reg nii1l; reg nii1O; reg niiii; reg niiil; reg niiiO; reg niili; reg niill; reg niilO; reg niiOi; reg niiOl; reg niiOO; reg nil1i; reg nil1l; reg nil1O; reg nl; reg nl0l0O; reg nl0lli; reg nl0O0i; reg nl0O0l; reg nl0O0O; reg nl0O1i; reg nl0O1l; reg nl0O1O; reg nl0Oii; reg nl0Oil; reg nl0OiO; reg nl0Oli; reg nl0Oll; reg nl0OlO; reg nli0ll; reg nli0Oi; reg nli0OO; reg nli10l; reg nli10O; reg nli1ii; reg nli1il; reg nli1iO; reg nli1li; reg nli1ll; reg nli1lO; reg nli1Oi; reg nlii0i; reg nlii0l; reg nlii0O; reg nlii1i; reg nlii1l; reg nlii1O; reg nliiii; reg nliiil; reg nliiiO; reg nliili; reg nliill; reg nliilO; reg nliiOi; reg nliiOl; reg nlil; reg nll; reg nlO; wire wire_ni_CLRN; reg n01i; reg n0ll; reg n0lO; reg n0Oi; reg n0Ol; reg n0OO; reg ni1i; reg ni1O; reg ni1l_clk_prev; wire wire_ni1l_CLRN; reg nliO0i; reg nliO0l; reg nliO0O; reg nliO1l; reg nliO1O; reg nliOii; reg nliOil; reg nliOiO; reg nliOli; reg nliOll; reg nliOOi; reg nliOlO_clk_prev; wire wire_nliOlO_CLRN; wire wire_nliOlO_PRN; reg n0li; reg ni0ii; reg nl0lOO; reg nliO; reg nll10i; reg nlll; reg nlli_clk_prev; wire wire_nlli_CLRN; wire wire_nlli_PRN; wire wire_n000i_dataout; wire wire_n001i_dataout; wire wire_n001l_dataout; wire wire_n001O_dataout; wire wire_n00i_dataout; wire wire_n00ii_dataout; wire wire_n00il_dataout; wire wire_n00iO_dataout; wire wire_n00l_dataout; wire wire_n00li_dataout; wire wire_n00ll_dataout; wire wire_n00lO_dataout; wire wire_n00Oi_dataout; wire wire_n00Ol_dataout; wire wire_n00OO_dataout; wire wire_n010i_dataout; wire wire_n010l_dataout; wire wire_n010O_dataout; wire wire_n011i_dataout; wire wire_n011l_dataout; wire wire_n011O_dataout; wire wire_n01ii_dataout; wire wire_n01il_dataout; wire wire_n01iO_dataout; wire wire_n01l_dataout; wire wire_n01li_dataout; wire wire_n01ll_dataout; wire wire_n01O_dataout; wire wire_n01Ol_dataout; wire wire_n01OO_dataout; wire wire_n0i0i_dataout; wire wire_n0i0l_dataout; wire wire_n0i0O_dataout; wire wire_n0i1i_dataout; wire wire_n0i1l_dataout; wire wire_n0i1O_dataout; wire wire_n0iii_dataout; wire wire_n0iil_dataout; wire wire_n0iiO_dataout; wire wire_n0ili_dataout; wire wire_n0ill_dataout; wire wire_n0ilO_dataout; wire wire_n0iOi_dataout; wire wire_n0iOl_dataout; wire wire_n0iOO_dataout; wire wire_n0l0i_dataout; wire wire_n0l0l_dataout; wire wire_n0l0O_dataout; wire wire_n0l1i_dataout; wire wire_n0lii_dataout; wire wire_n0lil_dataout; wire wire_n0liO_dataout; wire wire_n0lli_dataout; wire wire_n0lll_dataout; wire wire_n0llO_dataout; wire wire_n0lOi_dataout; wire wire_n0lOl_dataout; wire wire_n0lOO_dataout; wire wire_n0O_dataout; wire wire_n0O0i_dataout; wire wire_n0O0l_dataout; wire wire_n0O0O_dataout; wire wire_n0O1i_dataout; wire wire_n0O1l_dataout; wire wire_n0O1O_dataout; wire wire_n0Oii_dataout; wire wire_n0Oil_dataout; wire wire_n0OiO_dataout; wire wire_n0Oli_dataout; wire wire_n1l_dataout; wire wire_n1O_dataout; wire wire_n1OiO_dataout; wire wire_n1Oli_dataout; wire wire_n1Oll_dataout; wire wire_n1OOi_dataout; wire wire_n1OOl_dataout; wire wire_n1OOO_dataout; wire wire_ni0l_dataout; wire wire_ni0O_dataout; wire wire_nii_dataout; wire wire_niii_dataout; wire wire_niil_dataout; wire wire_niiO_dataout; wire wire_nili_dataout; wire wire_nill_dataout; wire wire_nilO_dataout; wire wire_niOi_dataout; wire wire_niOl_dataout; wire wire_niOO_dataout; wire wire_nl0i_dataout; wire wire_nl0l_dataout; wire wire_nl0lii_dataout; wire wire_nl0lll_dataout; wire wire_nl1i_dataout; wire wire_nl1l_dataout; wire wire_nl1O_dataout; wire wire_nli0lO_dataout; wire wire_nliiOO_dataout; wire wire_nlil0i_dataout; wire wire_nlil0l_dataout; wire wire_nlil0O_dataout; wire wire_nlil1i_dataout; wire wire_nlil1l_dataout; wire wire_nlil1O_dataout; wire wire_nlilii_dataout; wire wire_nlilil_dataout; wire wire_nliliO_dataout; wire wire_nlilli_dataout; wire wire_nlilll_dataout; wire wire_nlillO_dataout; wire wire_nlilOi_dataout; wire wire_nlilOl_dataout; wire wire_nlilOO_dataout; wire wire_nliOOl_dataout; wire wire_nO_dataout; wire [1:0] wire_n00O_o; wire [7:0] wire_nl0O_o; wire [15:0] wire_nliO1i_o; wire [3:0] wire_nl0OOi_o; wire [3:0] wire_nl0OOO_o; wire [7:0] wire_nli10i_o; wire wire_n0il_o; wire wire_nl0lOi_o; wire wire_nl0lil_o; wire wire_n000l_o; wire wire_n000O_o; wire wire_n01lO_o; wire wire_n1Oii_o; wire niOi0i; wire niOi1l; wire niOi1O; wire niOiii; wire niOiil; wire niOiiO; wire niOili; wire niOill; wire niOilO; wire niOiOi; wire niOiOl; wire niOiOO; wire niOl0i; wire niOl0l; wire niOl0O; wire niOl1i; wire niOl1l; wire niOl1O; wire niOlii; wire niOlil; wire niOliO; wire niOlli; wire niOlll; wire niOllO; wire niOlOi; wire niOlOl; wire niOlOO; wire niOO0i; wire niOO0l; wire niOO0O; wire niOO1i; wire niOO1l; wire niOO1O; wire niOOii; wire niOOil; wire niOOiO; wire niOOli; wire niOOll; wire niOOlO; wire niOOOi; wire niOOOl; wire niOOOO; wire nl000i; wire nl00iO; wire nl00li; wire nl00OO; wire nl010i; wire nl010l; wire nl010O; wire nl011i; wire nl0i0O; wire nl0i1O; wire nl0iiO; wire nl0ilO; wire nl100i; wire nl100l; wire nl100O; wire nl101i; wire nl101l; wire nl101O; wire nl10ii; wire nl10il; wire nl10iO; wire nl10li; wire nl10ll; wire nl10lO; wire nl10Oi; wire nl10Ol; wire nl10OO; wire nl110i; wire nl110l; wire nl110O; wire nl111i; wire nl111l; wire nl111O; wire nl11ii; wire nl11il; wire nl11iO; wire nl11li; wire nl11ll; wire nl11lO; wire nl11Oi; wire nl11Ol; wire nl11OO; wire nl1i0i; wire nl1i0l; wire nl1i0O; wire nl1i1i; wire nl1i1l; wire nl1i1O; wire nl1iii; wire nl1iil; wire nl1iiO; wire nl1ili; wire nl1ill; wire nl1ilO; wire nl1iOi; wire nl1iOl; wire nl1iOO; wire nl1l0i; wire nl1l0l; wire nl1l0O; wire nl1l1i; wire nl1l1l; wire nl1l1O; wire nl1lii; wire nl1lil; wire nl1liO; wire nl1lli; wire nl1lll; wire nl1llO; wire nl1lOi; wire nl1lOl; wire nl1O0i; wire nl1O0l; wire nl1O0O; wire nl1OiO; wire nl1Oli; wire nl1OOi; initial niOi0l51 = 0; always @ ( posedge rcvd_clk) niOi0l51 <= niOi0l52; event niOi0l51_event; initial #1 ->niOi0l51_event; always @(niOi0l51_event) niOi0l51 <= {1{1'b1}}; initial niOi0l52 = 0; always @ ( posedge rcvd_clk) niOi0l52 <= niOi0l51; initial niOi0O49 = 0; always @ ( posedge rcvd_clk) niOi0O49 <= niOi0O50; event niOi0O49_event; initial #1 ->niOi0O49_event; always @(niOi0O49_event) niOi0O49 <= {1{1'b1}}; initial niOi0O50 = 0; always @ ( posedge rcvd_clk) niOi0O50 <= niOi0O49; initial nl000l23 = 0; always @ ( posedge rcvd_clk) nl000l23 <= nl000l24; event nl000l23_event; initial #1 ->nl000l23_event; always @(nl000l23_event) nl000l23 <= {1{1'b1}}; initial nl000l24 = 0; always @ ( posedge rcvd_clk) nl000l24 <= nl000l23; initial nl001l25 = 0; always @ ( posedge rcvd_clk) nl001l25 <= nl001l26; event nl001l25_event; initial #1 ->nl001l25_event; always @(nl001l25_event) nl001l25 <= {1{1'b1}}; initial nl001l26 = 0; always @ ( posedge rcvd_clk) nl001l26 <= nl001l25; initial nl00ii21 = 0; always @ ( posedge rcvd_clk) nl00ii21 <= nl00ii22; event nl00ii21_event; initial #1 ->nl00ii21_event; always @(nl00ii21_event) nl00ii21 <= {1{1'b1}}; initial nl00ii22 = 0; always @ ( posedge rcvd_clk) nl00ii22 <= nl00ii21; initial nl00ll19 = 0; always @ ( posedge rcvd_clk) nl00ll19 <= nl00ll20; event nl00ll19_event; initial #1 ->nl00ll19_event; always @(nl00ll19_event) nl00ll19 <= {1{1'b1}}; initial nl00ll20 = 0; always @ ( posedge rcvd_clk) nl00ll20 <= nl00ll19; initial nl00lO17 = 0; always @ ( posedge rcvd_clk) nl00lO17 <= nl00lO18; event nl00lO17_event; initial #1 ->nl00lO17_event; always @(nl00lO17_event) nl00lO17 <= {1{1'b1}}; initial nl00lO18 = 0; always @ ( posedge rcvd_clk) nl00lO18 <= nl00lO17; initial nl00Oi15 = 0; always @ ( posedge rcvd_clk) nl00Oi15 <= nl00Oi16; event nl00Oi15_event; initial #1 ->nl00Oi15_event; always @(nl00Oi15_event) nl00Oi15 <= {1{1'b1}}; initial nl00Oi16 = 0; always @ ( posedge rcvd_clk) nl00Oi16 <= nl00Oi15; initial nl00Ol13 = 0; always @ ( posedge rcvd_clk) nl00Ol13 <= nl00Ol14; event nl00Ol13_event; initial #1 ->nl00Ol13_event; always @(nl00Ol13_event) nl00Ol13 <= {1{1'b1}}; initial nl00Ol14 = 0; always @ ( posedge rcvd_clk) nl00Ol14 <= nl00Ol13; initial nl011l37 = 0; always @ ( posedge rcvd_clk) nl011l37 <= nl011l38; event nl011l37_event; initial #1 ->nl011l37_event; always @(nl011l37_event) nl011l37 <= {1{1'b1}}; initial nl011l38 = 0; always @ ( posedge rcvd_clk) nl011l38 <= nl011l37; initial nl01ii35 = 0; always @ ( posedge rcvd_clk) nl01ii35 <= nl01ii36; event nl01ii35_event; initial #1 ->nl01ii35_event; always @(nl01ii35_event) nl01ii35 <= {1{1'b1}}; initial nl01ii36 = 0; always @ ( posedge rcvd_clk) nl01ii36 <= nl01ii35; initial nl01iO33 = 0; always @ ( posedge rcvd_clk) nl01iO33 <= nl01iO34; event nl01iO33_event; initial #1 ->nl01iO33_event; always @(nl01iO33_event) nl01iO33 <= {1{1'b1}}; initial nl01iO34 = 0; always @ ( posedge rcvd_clk) nl01iO34 <= nl01iO33; initial nl01ll31 = 0; always @ ( posedge rcvd_clk) nl01ll31 <= nl01ll32; event nl01ll31_event; initial #1 ->nl01ll31_event; always @(nl01ll31_event) nl01ll31 <= {1{1'b1}}; initial nl01ll32 = 0; always @ ( posedge rcvd_clk) nl01ll32 <= nl01ll31; initial nl01Oi29 = 0; always @ ( posedge rcvd_clk) nl01Oi29 <= nl01Oi30; event nl01Oi29_event; initial #1 ->nl01Oi29_event; always @(nl01Oi29_event) nl01Oi29 <= {1{1'b1}}; initial nl01Oi30 = 0; always @ ( posedge rcvd_clk) nl01Oi30 <= nl01Oi29; initial nl01OO27 = 0; always @ ( posedge rcvd_clk) nl01OO27 <= nl01OO28; event nl01OO27_event; initial #1 ->nl01OO27_event; always @(nl01OO27_event) nl01OO27 <= {1{1'b1}}; initial nl01OO28 = 0; always @ ( posedge rcvd_clk) nl01OO28 <= nl01OO27; initial nl0i0i10 = 0; always @ ( posedge rcvd_clk) nl0i0i10 <= nl0i0i9; initial nl0i0i9 = 0; always @ ( posedge rcvd_clk) nl0i0i9 <= nl0i0i10; event nl0i0i9_event; initial #1 ->nl0i0i9_event; always @(nl0i0i9_event) nl0i0i9 <= {1{1'b1}}; initial nl0i0l7 = 0; always @ ( posedge rcvd_clk) nl0i0l7 <= nl0i0l8; event nl0i0l7_event; initial #1 ->nl0i0l7_event; always @(nl0i0l7_event) nl0i0l7 <= {1{1'b1}}; initial nl0i0l8 = 0; always @ ( posedge rcvd_clk) nl0i0l8 <= nl0i0l7; initial nl0i1i11 = 0; always @ ( posedge rcvd_clk) nl0i1i11 <= nl0i1i12; event nl0i1i11_event; initial #1 ->nl0i1i11_event; always @(nl0i1i11_event) nl0i1i11 <= {1{1'b1}}; initial nl0i1i12 = 0; always @ ( posedge rcvd_clk) nl0i1i12 <= nl0i1i11; initial nl0iii5 = 0; always @ ( posedge rcvd_clk) nl0iii5 <= nl0iii6; event nl0iii5_event; initial #1 ->nl0iii5_event; always @(nl0iii5_event) nl0iii5 <= {1{1'b1}}; initial nl0iii6 = 0; always @ ( posedge rcvd_clk) nl0iii6 <= nl0iii5; initial nl0ili3 = 0; always @ ( posedge rcvd_clk) nl0ili3 <= nl0ili4; event nl0ili3_event; initial #1 ->nl0ili3_event; always @(nl0ili3_event) nl0ili3 <= {1{1'b1}}; initial nl0ili4 = 0; always @ ( posedge rcvd_clk) nl0ili4 <= nl0ili3; initial nl0iOi1 = 0; always @ ( posedge rcvd_clk) nl0iOi1 <= nl0iOi2; event nl0iOi1_event; initial #1 ->nl0iOi1_event; always @(nl0iOi1_event) nl0iOi1 <= {1{1'b1}}; initial nl0iOi2 = 0; always @ ( posedge rcvd_clk) nl0iOi2 <= nl0iOi1; initial nl1lOO47 = 0; always @ ( posedge rcvd_clk) nl1lOO47 <= nl1lOO48; event nl1lOO47_event; initial #1 ->nl1lOO47_event; always @(nl1lOO47_event) nl1lOO47 <= {1{1'b1}}; initial nl1lOO48 = 0; always @ ( posedge rcvd_clk) nl1lOO48 <= nl1lOO47; initial nl1O1l45 = 0; always @ ( posedge rcvd_clk) nl1O1l45 <= nl1O1l46; event nl1O1l45_event; initial #1 ->nl1O1l45_event; always @(nl1O1l45_event) nl1O1l45 <= {1{1'b1}}; initial nl1O1l46 = 0; always @ ( posedge rcvd_clk) nl1O1l46 <= nl1O1l45; initial nl1Oii43 = 0; always @ ( posedge rcvd_clk) nl1Oii43 <= nl1Oii44; event nl1Oii43_event; initial #1 ->nl1Oii43_event; always @(nl1Oii43_event) nl1Oii43 <= {1{1'b1}}; initial nl1Oii44 = 0; always @ ( posedge rcvd_clk) nl1Oii44 <= nl1Oii43; initial nl1Oll41 = 0; always @ ( posedge rcvd_clk) nl1Oll41 <= nl1Oll42; event nl1Oll41_event; initial #1 ->nl1Oll41_event; always @(nl1Oll41_event) nl1Oll41 <= {1{1'b1}}; initial nl1Oll42 = 0; always @ ( posedge rcvd_clk) nl1Oll42 <= nl1Oll41; initial nl1OOl39 = 0; always @ ( posedge rcvd_clk) nl1OOl39 <= nl1OOl40; event nl1OOl39_event; initial #1 ->nl1OOl39_event; always @(nl1OOl39_event) nl1OOl39 <= {1{1'b1}}; initial nl1OOl40 = 0; always @ ( posedge rcvd_clk) nl1OOl40 <= nl1OOl39; initial begin n0l = 0; n0OlO = 0; n0OOi = 0; n0OOl = 0; n0OOO = 0; n1Ol = 0; n1OlO = 0; n1OO = 0; ni00i = 0; ni00l = 0; ni00O = 0; ni01i = 0; ni01l = 0; ni01O = 0; ni0i = 0; ni0il = 0; ni0iO = 0; ni0li = 0; ni0ll = 0; ni0lO = 0; ni0Oi = 0; ni0Ol = 0; ni0OO = 0; ni10i = 0; ni10l = 0; ni10O = 0; ni11i = 0; ni11l = 0; ni11O = 0; ni1ii = 0; ni1il = 0; ni1iO = 0; ni1li = 0; ni1ll = 0; ni1lO = 0; ni1Oi = 0; ni1Ol = 0; ni1OO = 0; nii0i = 0; nii0l = 0; nii0O = 0; nii1i = 0; nii1l = 0; nii1O = 0; niiii = 0; niiil = 0; niiiO = 0; niili = 0; niill = 0; niilO = 0; niiOi = 0; niiOl = 0; niiOO = 0; nil1i = 0; nil1l = 0; nil1O = 0; nl = 0; nl0l0O = 0; nl0lli = 0; nl0O0i = 0; nl0O0l = 0; nl0O0O = 0; nl0O1i = 0; nl0O1l = 0; nl0O1O = 0; nl0Oii = 0; nl0Oil = 0; nl0OiO = 0; nl0Oli = 0; nl0Oll = 0; nl0OlO = 0; nli0ll = 0; nli0Oi = 0; nli0OO = 0; nli10l = 0; nli10O = 0; nli1ii = 0; nli1il = 0; nli1iO = 0; nli1li = 0; nli1ll = 0; nli1lO = 0; nli1Oi = 0; nlii0i = 0; nlii0l = 0; nlii0O = 0; nlii1i = 0; nlii1l = 0; nlii1O = 0; nliiii = 0; nliiil = 0; nliiiO = 0; nliili = 0; nliill = 0; nliilO = 0; nliiOi = 0; nliiOl = 0; nlil = 0; nll = 0; nlO = 0; end always @ ( posedge rcvd_clk or negedge wire_ni_CLRN) begin if (wire_ni_CLRN == 1'b0) begin n0l <= 0; n0OlO <= 0; n0OOi <= 0; n0OOl <= 0; n0OOO <= 0; n1Ol <= 0; n1OlO <= 0; n1OO <= 0; ni00i <= 0; ni00l <= 0; ni00O <= 0; ni01i <= 0; ni01l <= 0; ni01O <= 0; ni0i <= 0; ni0il <= 0; ni0iO <= 0; ni0li <= 0; ni0ll <= 0; ni0lO <= 0; ni0Oi <= 0; ni0Ol <= 0; ni0OO <= 0; ni10i <= 0; ni10l <= 0; ni10O <= 0; ni11i <= 0; ni11l <= 0; ni11O <= 0; ni1ii <= 0; ni1il <= 0; ni1iO <= 0; ni1li <= 0; ni1ll <= 0; ni1lO <= 0; ni1Oi <= 0; ni1Ol <= 0; ni1OO <= 0; nii0i <= 0; nii0l <= 0; nii0O <= 0; nii1i <= 0; nii1l <= 0; nii1O <= 0; niiii <= 0; niiil <= 0; niiiO <= 0; niili <= 0; niill <= 0; niilO <= 0; niiOi <= 0; niiOl <= 0; niiOO <= 0; nil1i <= 0; nil1l <= 0; nil1O <= 0; nl <= 0; nl0l0O <= 0; nl0lli <= 0; nl0O0i <= 0; nl0O0l <= 0; nl0O0O <= 0; nl0O1i <= 0; nl0O1l <= 0; nl0O1O <= 0; nl0Oii <= 0; nl0Oil <= 0; nl0OiO <= 0; nl0Oli <= 0; nl0Oll <= 0; nl0OlO <= 0; nli0ll <= 0; nli0Oi <= 0; nli0OO <= 0; nli10l <= 0; nli10O <= 0; nli1ii <= 0; nli1il <= 0; nli1iO <= 0; nli1li <= 0; nli1ll <= 0; nli1lO <= 0; nli1Oi <= 0; nlii0i <= 0; nlii0l <= 0; nlii0O <= 0; nlii1i <= 0; nlii1l <= 0; nlii1O <= 0; nliiii <= 0; nliiil <= 0; nliiiO <= 0; nliili <= 0; nliill <= 0; nliilO <= 0; nliiOi <= 0; nliiOl <= 0; nlil <= 0; nll <= 0; nlO <= 0; end else begin n0l <= nll; n0OlO <= wire_n1OiO_dataout; n0OOi <= wire_n1Oli_dataout; n0OOl <= wire_n1Oll_dataout; n0OOO <= wire_n1OOi_dataout; n1Ol <= wire_n01l_dataout; n1OlO <= wire_n1Oii_o; n1OO <= wire_n01O_dataout; ni00i <= wire_n001O_dataout; ni00l <= wire_n000i_dataout; ni00O <= wire_n000l_o; ni01i <= wire_n01OO_dataout; ni01l <= wire_n001i_dataout; ni01O <= wire_n001l_dataout; ni0i <= nl0i1O; ni0il <= syncstatus; ni0iO <= kflag; ni0li <= sudi[0]; ni0ll <= sudi[1]; ni0lO <= sudi[2]; ni0Oi <= sudi[3]; ni0Ol <= sudi[4]; ni0OO <= sudi[5]; ni10i <= wire_n011l_dataout; ni10l <= wire_n011O_dataout; ni10O <= wire_n010i_dataout; ni11i <= wire_n1OOl_dataout; ni11l <= wire_n1OOO_dataout; ni11O <= wire_n011i_dataout; ni1ii <= wire_n010l_dataout; ni1il <= wire_n010O_dataout; ni1iO <= wire_n01ii_dataout; ni1li <= wire_n01il_dataout; ni1ll <= wire_n01iO_dataout; ni1lO <= wire_n01li_dataout; ni1Oi <= wire_n01ll_dataout; ni1Ol <= wire_n01lO_o; ni1OO <= wire_n01Ol_dataout; nii0i <= sudi[9]; nii0l <= sudi[10]; nii0O <= sudi[12]; nii1i <= sudi[6]; nii1l <= sudi[7]; nii1O <= sudi[8]; niiii <= sudi[0]; niiil <= sudi[1]; niiiO <= sudi[2]; niili <= sudi[3]; niill <= sudi[4]; niilO <= sudi[5]; niiOi <= sudi[6]; niiOl <= sudi[7]; niiOO <= sudi[8]; nil1i <= sudi[9]; nil1l <= sudi[10]; nil1O <= sudi[12]; nl <= signaldetect; nl0l0O <= nl0lli; nl0lli <= wire_nl0lll_dataout; nl0O0i <= wire_nl0OOO_o[0]; nl0O0l <= (wire_nli10i_o[6] | wire_nli10i_o[5]); nl0O0O <= ((wire_nli10i_o[2] | wire_nli10i_o[0]) | wire_nli10i_o[5]); nl0O1i <= wire_nli10i_o[1]; nl0O1l <= wire_nl0OOi_o[1]; nl0O1O <= ((wire_nli10i_o[7] | wire_nli10i_o[3]) | wire_nli10i_o[1]); nl0Oii <= niOi1l; nl0Oil <= niOi1l; nl0OiO <= niOi1l; nl0Oli <= niOi1l; nl0Oll <= wire_nli10i_o[6]; nl0OlO <= (~ (((~ (nli1il ^ nli10l)) & (~ (nli1iO ^ nli10O))) & (~ (nli1li ^ nli1ii)))); nli0ll <= wire_nliiOO_dataout; nli0Oi <= wire_nli0lO_dataout; nli0OO <= wire_nlil1i_dataout; nli10l <= nli1il; nli10O <= nli1iO; nli1ii <= nli1li; nli1il <= nli1ll; nli1iO <= nli1lO; nli1li <= nli1Oi; nli1ll <= eidleinfersel[0]; nli1lO <= eidleinfersel[1]; nli1Oi <= eidleinfersel[2]; nlii0i <= wire_nlil0l_dataout; nlii0l <= wire_nlil0O_dataout; nlii0O <= wire_nlilii_dataout; nlii1i <= wire_nlil1l_dataout; nlii1l <= wire_nlil1O_dataout; nlii1O <= wire_nlil0i_dataout; nliiii <= wire_nlilil_dataout; nliiil <= wire_nliliO_dataout; nliiiO <= wire_nlilli_dataout; nliili <= wire_nlilll_dataout; nliill <= wire_nlillO_dataout; nliilO <= wire_nlilOi_dataout; nliiOi <= wire_nlilOl_dataout; nliiOl <= wire_nlilOO_dataout; nlil <= (((~ ni0i) & nl0i1O) & (nl0i1i12 ^ nl0i1i11)); nll <= wire_nO_dataout; nlO <= nl; end end assign wire_ni_CLRN = ((nl0iOi2 ^ nl0iOi1) & (~ rxpcsrst)); initial begin n01i = 0; n0ll = 0; n0lO = 0; n0Oi = 0; n0Ol = 0; n0OO = 0; ni1i = 0; ni1O = 0; end always @ (rcvd_clk or wire_ni1l_CLRN or rxpcsrst) begin if (wire_ni1l_CLRN == 1'b0) begin n01i <= 0; n0ll <= 0; n0lO <= 0; n0Oi <= 0; n0Ol <= 0; n0OO <= 0; ni1i <= 0; ni1O <= 0; end else if (rxpcsrst == 1'b1) begin n01i <= rwait_count[0]; n0ll <= rwait_count[1]; n0lO <= rwait_count[2]; n0Oi <= rwait_count[3]; n0Ol <= rwait_count[4]; n0OO <= rwait_count[5]; ni1i <= rwait_count[6]; ni1O <= rwait_count[7]; end else if (rcvd_clk != ni1l_clk_prev && rcvd_clk == 1'b1) begin n01i <= wire_ni0l_dataout; n0ll <= wire_ni0O_dataout; n0lO <= wire_niii_dataout; n0Oi <= wire_niil_dataout; n0Ol <= wire_niiO_dataout; n0OO <= wire_nili_dataout; ni1i <= wire_nill_dataout; ni1O <= wire_nilO_dataout; end ni1l_clk_prev <= rcvd_clk; end always @(rwait_count[0]) if (rxpcsrst == 1'b1) n01i = rwait_count[0]; always @(rwait_count[1]) if (rxpcsrst == 1'b1) n0ll = rwait_count[1]; always @(rwait_count[2]) if (rxpcsrst == 1'b1) n0lO = rwait_count[2]; always @(rwait_count[3]) if (rxpcsrst == 1'b1) n0Oi = rwait_count[3]; always @(rwait_count[4]) if (rxpcsrst == 1'b1) n0Ol = rwait_count[4]; always @(rwait_count[5]) if (rxpcsrst == 1'b1) n0OO = rwait_count[5]; always @(rwait_count[6]) if (rxpcsrst == 1'b1) ni1i = rwait_count[6]; always @(rwait_count[7]) if (rxpcsrst == 1'b1) ni1O = rwait_count[7]; assign wire_ni1l_CLRN = (nl00lO18 ^ nl00lO17); initial begin nliO0i = 0; nliO0l = 0; nliO0O = 0; nliO1l = 0; nliO1O = 0; nliOii = 0; nliOil = 0; nliOiO = 0; nliOli = 0; nliOll = 0; nliOOi = 0; end always @ (rcvd_clk or wire_nliOlO_PRN or wire_nliOlO_CLRN) begin if (wire_nliOlO_PRN == 1'b0) begin nliO0i <= 1; nliO0l <= 1; nliO0O <= 1; nliO1l <= 1; nliO1O <= 1; nliOii <= 1; nliOil <= 1; nliOiO <= 1; nliOli <= 1; nliOll <= 1; nliOOi <= 1; end else if (wire_nliOlO_CLRN == 1'b0) begin nliO0i <= 0; nliO0l <= 0; nliO0O <= 0; nliO1l <= 0; nliO1O <= 0; nliOii <= 0; nliOil <= 0; nliOiO <= 0; nliOli <= 0; nliOll <= 0; nliOOi <= 0; end else if (niOiii == 1'b1) if (rcvd_clk != nliOlO_clk_prev && rcvd_clk == 1'b1) begin nliO0i <= nl0O1O; nliO0l <= nl0O0i; nliO0O <= nl0O0l; nliO1l <= nl0O1i; nliO1O <= nl0O1l; nliOii <= nl0O0O; nliOil <= nl0Oii; nliOiO <= nl0Oil; nliOli <= nl0OiO; nliOll <= nl0Oli; nliOOi <= nl0Oll; end nliOlO_clk_prev <= rcvd_clk; end assign wire_nliOlO_CLRN = ((niOi0O50 ^ niOi0O49) & (~ rxpcsrst)), wire_nliOlO_PRN = (niOi0l52 ^ niOi0l51); initial begin n0li = 0; ni0ii = 0; nl0lOO = 0; nliO = 0; nll10i = 0; nlll = 0; end always @ (rcvd_clk or wire_nlli_PRN or wire_nlli_CLRN) begin if (wire_nlli_PRN == 1'b0) begin n0li <= 1; ni0ii <= 1; nl0lOO <= 1; nliO <= 1; nll10i <= 1; nlll <= 1; end else if (wire_nlli_CLRN == 1'b0) begin n0li <= 0; ni0ii <= 0; nl0lOO <= 0; nliO <= 0; nll10i <= 0; nlll <= 0; end else if (rcvd_clk != nlli_clk_prev && rcvd_clk == 1'b1) begin n0li <= nll10i; ni0ii <= wire_n000O_o; nl0lOO <= wire_nl0lii_dataout; nliO <= wire_n1l_dataout; nll10i <= wire_nliOOl_dataout; nlll <= wire_n0O_dataout; end nlli_clk_prev <= rcvd_clk; end assign wire_nlli_CLRN = (nl0i0l8 ^ nl0i0l7), wire_nlli_PRN = ((nl0i0i10 ^ nl0i0i9) & (~ rxpcsrst)); event n0li_event; event ni0ii_event; event nl0lOO_event; event nliO_event; event nll10i_event; event nlll_event; initial #1 ->n0li_event; initial #1 ->ni0ii_event; initial #1 ->nl0lOO_event; initial #1 ->nliO_event; initial #1 ->nll10i_event; initial #1 ->nlll_event; always @(n0li_event) n0li <= 1; always @(ni0ii_event) ni0ii <= 1; always @(nl0lOO_event) nl0lOO <= 1; always @(nliO_event) nliO <= 1; always @(nll10i_event) nll10i <= 1; always @(nlll_event) nlll <= 1; and(wire_n000i_dataout, wire_n0O0i_dataout, ni00O); and(wire_n001i_dataout, wire_n0l0i_dataout, ni01O); and(wire_n001l_dataout, wire_n0liO_dataout, ni00i); and(wire_n001O_dataout, wire_n0lOl_dataout, ni00l); assign wire_n00i_dataout = (nl000i === 1'b1) ? wire_n00O_o[0] : n1Ol; and(wire_n00ii_dataout, niOO0l, ~(niOOiO)); and(wire_n00il_dataout, wire_n0i0O_dataout, ~(niOOiO)); or(wire_n00iO_dataout, wire_n0iii_dataout, niOOiO); assign wire_n00l_dataout = (nl000i === 1'b1) ? wire_n00O_o[1] : n1OO; and(wire_n00li_dataout, wire_n00lO_dataout, ~(niOOiO)); or(wire_n00ll_dataout, wire_n00Oi_dataout, niOOiO); and(wire_n00lO_dataout, niOOil, ~(niOO0i)); and(wire_n00Oi_dataout, (~ niOOil), ~(niOO0i)); and(wire_n00Ol_dataout, wire_n0i1O_dataout, ~(niOOiO)); and(wire_n00OO_dataout, niOO0i, ~(niOOiO)); and(wire_n010i_dataout, wire_n00OO_dataout, ni1ii); and(wire_n010l_dataout, wire_n00OO_dataout, ni1il); and(wire_n010O_dataout, wire_n00OO_dataout, ni1iO); and(wire_n011i_dataout, wire_n00ii_dataout, ni10i); and(wire_n011l_dataout, wire_n00ii_dataout, ni10l); and(wire_n011O_dataout, wire_n00Ol_dataout, ni01i); and(wire_n01ii_dataout, wire_n00OO_dataout, ni1li); and(wire_n01il_dataout, wire_n00OO_dataout, ni1ll); and(wire_n01iO_dataout, wire_n00OO_dataout, ni1lO); and(wire_n01l_dataout, wire_n00i_dataout, ~(nl0i0O)); and(wire_n01li_dataout, wire_n00OO_dataout, ni1Oi); and(wire_n01ll_dataout, wire_n00OO_dataout, ni1Ol); and(wire_n01O_dataout, wire_n00l_dataout, ~(nl0i0O)); and(wire_n01Ol_dataout, wire_n0iil_dataout, ni01l); and(wire_n01OO_dataout, wire_n0iiO_dataout, ni01l); and(wire_n0i0i_dataout, wire_n0i0O_dataout, ~(niOO0i)); and(wire_n0i0l_dataout, wire_n0iii_dataout, ~(niOO0i)); and(wire_n0i0O_dataout, niOOil, ~(niOO0l)); and(wire_n0i1i_dataout, wire_n0i0i_dataout, ~(niOOiO)); or(wire_n0i1l_dataout, wire_n0i0l_dataout, niOOiO); and(wire_n0i1O_dataout, niOO0l, ~(niOO0i)); and(wire_n0iii_dataout, (~ niOOil), ~(niOO0l)); and(wire_n0iil_dataout, wire_n0ilO_dataout, ~(niOOiO)); and(wire_n0iiO_dataout, niOOii, ~(niOOiO)); and(wire_n0ili_dataout, wire_n0iOi_dataout, ~(niOOiO)); or(wire_n0ill_dataout, wire_n0iOl_dataout, niOOiO); and(wire_n0ilO_dataout, niOO0O, ~(niOOii)); and(wire_n0iOi_dataout, wire_n0iOO_dataout, ~(niOOii)); and(wire_n0iOl_dataout, wire_n0l1i_dataout, ~(niOOii)); and(wire_n0iOO_dataout, niOOil, ~(niOO0O)); and(wire_n0l0i_dataout, niOOlO, ~(niOOiO)); and(wire_n0l0l_dataout, wire_n0lii_dataout, ~(niOOiO)); or(wire_n0l0O_dataout, wire_n0lil_dataout, niOOiO); and(wire_n0l1i_dataout, (~ niOOil), ~(niOO0O)); and(wire_n0lii_dataout, niOOil, ~(niOOlO)); and(wire_n0lil_dataout, (~ niOOil), ~(niOOlO)); and(wire_n0liO_dataout, nl11li, ~(niOOiO)); and(wire_n0lli_dataout, wire_n0llO_dataout, ~(niOOiO)); or(wire_n0lll_dataout, wire_n0lOi_dataout, niOOiO); and(wire_n0llO_dataout, niOOil, ~(nl11li)); and(wire_n0lOi_dataout, (~ niOOil), ~(nl11li)); and(wire_n0lOl_dataout, nl11ll, ~(niOOiO)); and(wire_n0lOO_dataout, wire_n0O1l_dataout, ~(niOOiO)); or(wire_n0O_dataout, wire_nii_dataout, ~(nlO)); and(wire_n0O0i_dataout, nl010l, ~(niOOiO)); and(wire_n0O0l_dataout, wire_n0Oii_dataout, ~(niOOiO)); or(wire_n0O0O_dataout, wire_n0Oil_dataout, niOOiO); or(wire_n0O1i_dataout, wire_n0O1O_dataout, niOOiO); and(wire_n0O1l_dataout, niOOil, ~(nl11ll)); and(wire_n0O1O_dataout, (~ niOOil), ~(nl11ll)); and(wire_n0Oii_dataout, niOOil, ~(nl010l)); and(wire_n0Oil_dataout, (~ niOOil), ~(nl010l)); and(wire_n0OiO_dataout, niOOil, ~(niOOiO)); or(wire_n0Oli_dataout, (~ niOOil), niOOiO); assign wire_n1l_dataout = (reidleinferenable === 1'b1) ? wire_n1O_dataout : nlll; assign wire_n1O_dataout = (((~ n0l) & rgen1_sigdet_ena) === 1'b1) ? nlll : n0li; and(wire_n1OiO_dataout, wire_n00ii_dataout, n0OOi); and(wire_n1Oli_dataout, wire_n00ii_dataout, n0OOl); and(wire_n1Oll_dataout, wire_n00ii_dataout, n0OOO); and(wire_n1OOi_dataout, wire_n00ii_dataout, ni11i); and(wire_n1OOl_dataout, wire_n00ii_dataout, ni11l); and(wire_n1OOO_dataout, wire_n00ii_dataout, ni11O); assign wire_ni0l_dataout = (nl00OO === 1'b1) ? wire_nl0O_o[0] : wire_niOi_dataout; assign wire_ni0O_dataout = (nl00OO === 1'b1) ? wire_nl0O_o[1] : wire_niOl_dataout; assign wire_nii_dataout = (nlll === 1'b1) ? (~ (((nlO & nl0iiO) | nlil) | (~ (nl0iii6 ^ nl0iii5)))) : (((~ riei_eios_priority_dis) & eiosdetect_int) & (nl0ili4 ^ nl0ili3)); assign wire_niii_dataout = (nl00OO === 1'b1) ? wire_nl0O_o[2] : wire_niOO_dataout; assign wire_niil_dataout = (nl00OO === 1'b1) ? wire_nl0O_o[3] : wire_nl1i_dataout; assign wire_niiO_dataout = (nl00OO === 1'b1) ? wire_nl0O_o[4] : wire_nl1l_dataout; assign wire_nili_dataout = (nl00OO === 1'b1) ? wire_nl0O_o[5] : wire_nl1O_dataout; assign wire_nill_dataout = (nl00OO === 1'b1) ? wire_nl0O_o[6] : wire_nl0i_dataout; assign wire_nilO_dataout = (nl00OO === 1'b1) ? wire_nl0O_o[7] : wire_nl0l_dataout; and(wire_niOi_dataout, n01i, wire_n1l_dataout); and(wire_niOl_dataout, n0ll, wire_n1l_dataout); and(wire_niOO_dataout, n0lO, wire_n1l_dataout); and(wire_nl0i_dataout, ni1i, wire_n1l_dataout); and(wire_nl0l_dataout, ni1O, wire_n1l_dataout); or(wire_nl0lii_dataout, wire_nl0lil_o, ~(reidleinferenable)); assign wire_nl0lll_dataout = ((inferred_rxvalid & (reidle_com_detect[0] & reidle_com_detect[1])) === 1'b1) ? syncstatus : (inferred_rxvalid & wire_nl0lOi_o); and(wire_nl1i_dataout, n0Oi, wire_n1l_dataout); and(wire_nl1l_dataout, n0Ol, wire_n1l_dataout); and(wire_nl1O_dataout, n0OO, wire_n1l_dataout); and(wire_nli0lO_dataout, niOi1O, ~(niOi0i)); and(wire_nliiOO_dataout, wire_nliO1i_o[0], ~(niOi0i)); and(wire_nlil0i_dataout, wire_nliO1i_o[4], ~(niOi0i)); and(wire_nlil0l_dataout, wire_nliO1i_o[5], ~(niOi0i)); and(wire_nlil0O_dataout, wire_nliO1i_o[6], ~(niOi0i)); and(wire_nlil1i_dataout, wire_nliO1i_o[1], ~(niOi0i)); and(wire_nlil1l_dataout, wire_nliO1i_o[2], ~(niOi0i)); and(wire_nlil1O_dataout, wire_nliO1i_o[3], ~(niOi0i)); and(wire_nlilii_dataout, wire_nliO1i_o[7], ~(niOi0i)); and(wire_nlilil_dataout, wire_nliO1i_o[8], ~(niOi0i)); and(wire_nliliO_dataout, wire_nliO1i_o[9], ~(niOi0i)); and(wire_nlilli_dataout, wire_nliO1i_o[10], ~(niOi0i)); and(wire_nlilll_dataout, wire_nliO1i_o[11], ~(niOi0i)); and(wire_nlillO_dataout, wire_nliO1i_o[12], ~(niOi0i)); and(wire_nlilOi_dataout, wire_nliO1i_o[13], ~(niOi0i)); and(wire_nlilOl_dataout, wire_nliO1i_o[14], ~(niOi0i)); and(wire_nlilOO_dataout, wire_nliO1i_o[15], ~(niOi0i)); assign wire_nliOOl_dataout = (nll10i === 1'b1) ? (~ nlil) : ((eiosdetect_int & ((~ riei_eios_priority_dis) | (~ nli1li))) | nli0Oi); assign wire_nO_dataout = (rindv_rx === 1'b1) ? gen2ngen1 : gen2ngen1_bundle; oper_add n00O ( .a({n1OO, n1Ol}), .b({1'b0, 1'b1}), .cin(1'b0), .cout(), .o(wire_n00O_o)); defparam n00O.sgate_representation = 0, n00O.width_a = 2, n00O.width_b = 2, n00O.width_o = 2; oper_add nl0O ( .a({ni1O, ((nl00Oi16 ^ nl00Oi15) & ni1i), n0OO, n0Ol, n0Oi, n0lO, n0ll, ((nl00Ol14 ^ nl00Ol13) & n01i)}), .b({{7{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_nl0O_o)); defparam nl0O.sgate_representation = 0, nl0O.width_a = 8, nl0O.width_b = 8, nl0O.width_o = 8; oper_add nliO1i ( .a({nliiOl, nliiOi, nliilO, nliill, nliili, nliiiO, nliiil, nliiii, nlii0O, nlii0l, nlii0i, nlii1O, nlii1l, nlii1i, nli0OO, nli0ll}), .b({{15{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_nliO1i_o)); defparam nliO1i.sgate_representation = 0, nliO1i.width_a = 16, nliO1i.width_b = 16, nliO1i.width_o = 16; oper_decoder nl0OOi ( .i({nli1iO, nli1il}), .o(wire_nl0OOi_o)); defparam nl0OOi.width_i = 2, nl0OOi.width_o = 4; oper_decoder nl0OOO ( .i({n0l, nli1il}), .o(wire_nl0OOO_o)); defparam nl0OOO.width_i = 2, nl0OOO.width_o = 4; oper_decoder nli10i ( .i({n0l, nli1iO, nli1il}), .o(wire_nli10i_o)); defparam nli10i.width_i = 3, nli10i.width_o = 8; oper_less_than n0il ( .a({n1OO, ((nl00ll20 ^ nl00ll19) & n1Ol)}), .b({reidle_com_detect[1:0]}), .cin(1'b0), .o(wire_n0il_o)); defparam n0il.sgate_representation = 0, n0il.width_a = 2, n0il.width_b = 2; oper_less_than nl0lOi ( .a({reidle_com_detect[1:0]}), .b({kcount[1:0]}), .cin(1'b1), .o(wire_nl0lOi_o)); defparam nl0lOi.sgate_representation = 0, nl0lOi.width_a = 2, nl0lOi.width_b = 2; oper_mux nl0lil ( .data({n1OlO, skposdetect, nl0l0O, (n0l | nl0l0O), {4{1'b1}}}), .o(wire_nl0lil_o), .sel({nli1li, nli1iO, nli1il})); defparam nl0lil.width_data = 8, nl0lil.width_sel = 3; oper_selector n000l ( .data({wire_n0OiO_dataout, wire_n0O0l_dataout, wire_n0lOO_dataout, wire_n0lli_dataout, wire_n0l0l_dataout, wire_n0ili_dataout, wire_n0i1i_dataout, {10{wire_n00li_dataout}}, {9{wire_n00il_dataout}}, wire_n0OiO_dataout}), .o(wire_n000l_o), .sel({ni0ii, ni00O, ni00l, ni00i, ni01O, ni01l, ni01i, ni1OO, ni1Ol, ni1Oi, ni1lO, ni1ll, ni1li, ni1iO, ni1il, ni1ii, ni10O, ni10l, ni10i, ni11O, ni11l, ni11i, n0OOO, n0OOl, n0OOi, n0OlO, n1OlO})); defparam n000l.width_data = 27, n000l.width_sel = 27; oper_selector n000O ( .data({wire_n0Oli_dataout, wire_n0O0O_dataout, wire_n0O1i_dataout, wire_n0lll_dataout, wire_n0l0O_dataout, wire_n0ill_dataout, wire_n0i1l_dataout, {10{wire_n00ll_dataout}}, {9{wire_n00iO_dataout}}, wire_n0Oli_dataout}), .o(wire_n000O_o), .sel({ni0ii, ni00O, ni00l, ni00i, ni01O, ni01l, ni01i, ni1OO, ni1Ol, ni1Oi, ni1lO, ni1ll, ni1li, ni1iO, ni1il, ni1ii, ni10O, ni10l, ni10i, ni11O, ni11l, ni11i, n0OOO, n0OOl, n0OOi, n0OlO, n1OlO})); defparam n000O.width_data = 27, n000O.width_sel = 27; oper_selector n01lO ( .data({1'b0, wire_n00OO_dataout}), .o(wire_n01lO_o), .sel({niOO1O, (~ niOO1O)})); defparam n01lO.width_data = 2, n01lO.width_sel = 2; oper_selector n1Oii ( .data({1'b0, wire_n00OO_dataout, wire_n00ii_dataout}), .o(wire_n1Oii_o), .sel({niOO1l, ni10O, n0OlO})); defparam n1Oii.width_data = 3, n1Oii.width_sel = 3; assign niOi0i = (nll10i | niOiii), niOi1l = ((wire_nli10i_o[6] | wire_nli10i_o[2]) | wire_nli10i_o[0]), niOi1O = ((((((((((((((((~ nlii0i) & (~ nlii1O)) & (~ nlii1i)) & (~ nli0OO)) & (~ nli0ll)) & (~ (nliO1l ^ nlii1l))) & (~ (nliO1O ^ nlii0l))) & (~ (nliO0i ^ nlii0O))) & (~ (nliO0l ^ nliiii))) & (~ (nliO0O ^ nliiil))) & (~ (nliOii ^ nliiiO))) & (~ (nliOil ^ nliili))) & (~ (nliOiO ^ nliill))) & (~ (nliOli ^ nliilO))) & (~ (nliOll ^ nliiOi))) & (~ (nliOOi ^ nliiOl))), niOiii = (nl0OlO | nl0lOO), niOiil = (((((((((nil1i & niiOO) & (~ niiOl)) & niiOi) & (~ niilO)) & (~ niill)) & (~ niili)) & niiiO) & niiil) & (~ niiii)), niOiiO = ((((((((((~ nil1i) & (~ niiOO)) & niiOl) & (~ niiOi)) & niilO) & niill) & niili) & (~ niiiO)) & (~ niiil)) & niiii), niOili = (((((((((nil1i & niiOO) & (~ niiOl)) & niiOi) & (~ niilO)) & niill) & (~ niili)) & (~ niiiO)) & (~ niiil)) & niiii), niOill = ((((((((((~ nil1i) & (~ niiOO)) & niiOl) & (~ niiOi)) & niilO) & (~ niill)) & niili) & niiiO) & niiil) & (~ niiii)), niOilO = (((((((((nil1i & niiOO) & (~ niiOl)) & niiOi) & (~ niilO)) & niill) & (~ niili)) & (~ niiiO)) & niiil) & (~ niiii)), niOiOi = ((((((((((~ nil1i) & (~ niiOO)) & niiOl) & (~ niiOi)) & niilO) & (~ niill)) & niili) & niiiO) & (~ niiil)) & niiii), niOiOl = (((((((((nil1i & niiOO) & (~ niiOl)) & niiOi) & (~ niilO)) & niill) & (~ niili)) & niiiO) & (~ niiil)) & (~ niiii)), niOiOO = ((((((((((~ nil1i) & (~ niiOO)) & niiOl) & (~ niiOi)) & niilO) & (~ niill)) & niili) & (~ niiiO)) & niiil) & niiii), niOl0i = ((((((((((~ nil1i) & (~ niiOO)) & niiOl) & (~ niiOi)) & niilO) & (~ niill)) & (~ niili)) & niiiO) & niiil) & niiii), niOl0l = (((((((((nil1i & niiOO) & (~ niiOl)) & niiOi) & (~ niilO)) & (~ niill)) & niili) & (~ niiiO)) & (~ niiil)) & niiii), niOl0O = ((((((((((~ nil1i) & (~ niiOO)) & niiOl) & (~ niiOi)) & niilO) & niill) & (~ niili)) & niiiO) & niiil) & (~ niiii)), niOl1i = ((((((((((~ nil1i) & (~ niiOO)) & niiOl) & (~ niiOi)) & niilO) & (~ niill)) & (~ niili)) & niiiO) & niiil) & (~ niiii)), niOl1l = (((((((((nil1i & niiOO) & (~ niiOl)) & niiOi) & niilO) & (~ niill)) & (~ niili)) & niiiO) & niiil) & (~ niiii)), niOl1O = (((((((((nil1i & niiOO) & (~ niiOl)) & niiOi) & (~ niilO)) & niill) & niili) & (~ niiiO)) & (~ niiil)) & (~ niiii)), niOlii = ((((((((((~ nil1i) & (~ niiOO)) & niiOl) & (~ niiOi)) & niilO) & niill) & (~ niili)) & niiiO) & (~ niiil)) & (~ niiii)), niOlil = (((((((((nil1i & niiOO) & (~ niiOl)) & niiOi) & niilO) & niill) & (~ niili)) & niiiO) & (~ niiil)) & (~ niiii)), niOliO = (((((((((nii0i & (~ nii1O)) & nii1l) & (~ nii1i)) & (~ ni0OO)) & (~ ni0Ol)) & (~ ni0Oi)) & (~ ni0lO)) & ni0ll) & ni0li), niOlli = ((((((((((~ nii0i) & nii1O) & (~ nii1l)) & nii1i) & ni0OO) & ni0Ol) & ni0Oi) & ni0lO) & (~ ni0ll)) & (~ ni0li)), niOlll = (((((((((nii0i & nii1O) & nii1l) & (~ nii1i)) & ni0OO) & (~ ni0Ol)) & ni0Oi) & (~ ni0lO)) & (~ ni0ll)) & (~ ni0li)), niOllO = ((((((((((~ nii0i) & (~ nii1O)) & (~ nii1l)) & nii1i) & (~ ni0OO)) & ni0Ol) & (~ ni0Oi)) & ni0lO) & ni0ll) & ni0li), niOlOi = (((((((((nii0i & (~ nii1O)) & nii1l) & (~ nii1i)) & ni0OO) & (~ ni0Ol)) & ni0Oi) & (~ ni0lO)) & ni0ll) & (~ ni0li)), niOlOl = (((((((((nii0i & (~ nii1O)) & nii1l) & (~ nii1i)) & ni0OO) & (~ ni0Ol)) & ni0Oi) & (~ ni0lO)) & ni0ll) & (~ ni0li)), niOlOO = (((((((((nii0i & (~ nii1O)) & nii1l) & (~ nii1i)) & ni0OO) & (~ ni0Ol)) & (~ ni0Oi)) & ni0lO) & (~ ni0ll)) & ni0li), niOO0i = ((~ nii0O) & ((~ nii0l) & (niOlOl | niOlOi))), niOO0l = ((~ nii0O) & ((~ nii0l) & (niOO1i | niOlOO))), niOO0O = (niOOll & (~ niOOli)), niOO1i = (((((((((nii0i & (~ nii1O)) & nii1l) & (~ nii1i)) & ni0OO) & (~ ni0Ol)) & (~ ni0Oi)) & ni0lO) & (~ ni0ll)) & ni0li), niOO1l = ((((((((((((((((((((((((ni0ii | ni00O) | ni00l) | ni00i) | ni01O) | ni01l) | ni01i) | ni1OO) | ni1Ol) | ni1Oi) | ni1lO) | ni1ll) | ni1li) | ni1iO) | ni1il) | ni1ii) | ni10l) | ni10i) | ni11O) | ni11l) | ni11i) | n0OOO) | n0OOl) | n0OOi) | n1OlO), niOO1O = ((((((((((((((((((((((((ni0ii | ni00O) | ni00l) | ni00i) | ni01O) | ni01l) | ni1Ol) | ni1Oi) | ni1lO) | ni1ll) | ni1li) | ni1iO) | ni1il) | ni1ii) | ni10O) | ni10l) | ni10i) | ni11O) | ni11l) | ni11i) | n0OOO) | n0OOl) | n0OOi) | n0OlO) | n1OlO), niOOii = (niOOll & niOOli), niOOil = (ni0iO & ((~ nii0O) & ((~ nii0l) & (niOlli | niOliO)))), niOOiO = ((~ reidleinferenable) | (~ ni0il)), niOOli = ((((nl010i | nl011i) | nl1OOi) | nl1O0O) | nl1lll), niOOll = ((((((nl010i | nl011i) | nl1OOi) | nl1O0O) | nl1lll) | nl1ill) | nl1i0i), niOOlO = (((((((nl1OOi | ((~ nii0O) & ((~ nii0l) & (nl11iO | nl11il)))) | ((~ nii0O) & ((~ nii0l) & (nl11ii | nl110O)))) | ((~ nii0O) & ((~ nii0l) & (nl110l | nl110i)))) | nl1lOl) | ((~ nii0O) & ((~ nii0l) & (nl111O | nl111l)))) | ((~ nii0O) & ((~ nii0l) & (nl111i | niOOOO)))) | ((~ nii0O) & ((~ nii0l) & (niOOOl | niOOOi)))), niOOOi = ((((((((((~ nii0i) & nii1O) & nii1l) & (~ nii1i)) & ni0OO) & (~ ni0Ol)) & (~ ni0Oi)) & ni0lO) & ni0ll) & (~ ni0li)), niOOOl = ((((((((((~ nii0i) & nii1O) & nii1l) & (~ nii1i)) & ni0OO) & (~ ni0Ol)) & (~ ni0Oi)) & ni0lO) & ni0ll) & (~ ni0li)), niOOOO = ((((((((((~ nii0i) & nii1O) & (~ nii1l)) & (~ nii1i)) & ni0OO) & (~ ni0Ol)) & (~ ni0Oi)) & ni0lO) & ni0ll) & (~ ni0li)), nl000i = (((((((~ sudi[10]) & (~ sudi[12])) & (nl00li | nl00iO)) & (nl00ii22 ^ nl00ii21)) & nl0iiO) & wire_n0il_o) & (nl000l24 ^ nl000l23)), nl00iO = (((((((((((~ sudi[0]) & (~ sudi[1])) & sudi[2]) & sudi[3]) & sudi[4]) & sudi[5]) & sudi[6]) & (~ sudi[7])) & sudi[8]) & (~ sudi[9])) & (nl01iO34 ^ nl01iO33)), nl00li = ((((((((((sudi[0] & sudi[1]) & (~ sudi[2])) & (~ sudi[3])) & (~ sudi[4])) & (~ sudi[5])) & (~ sudi[6])) & sudi[7]) & (~ sudi[8])) & sudi[9]) & (nl01ll32 ^ nl01ll31)), nl00OO = (wire_n1l_dataout & (~ nl0iiO)), nl010i = ((~ nil1O) & ((~ nil1l) & (niOiiO | niOiil))), nl010l = (((((~ nii0l) & (~ ni0iO)) & (~ nii0O)) & (nl01ii36 ^ nl01ii35)) | nl010O), nl010O = (ni0iO & ((~ nii0O) & ((~ nii0l) & (niOllO | niOlll)))), nl011i = ((~ nil1O) & ((~ nil1l) & (niOill | niOili))), nl0i0O = (wire_n1l_dataout & (~ nliO)), nl0i1O = ((~ (n1Ol ^ reidle_com_detect[0])) & (~ (n1OO ^ reidle_com_detect[1]))), nl0iiO = ((((((((~ (n01i ^ rwait_count[0])) & (~ ((n0ll ^ rwait_count[1]) ^ (~ (nl001l26 ^ nl001l25))))) & (~ (n0lO ^ rwait_count[2]))) & (~ ((n0Oi ^ rwait_count[3]) ^ (~ (nl01OO28 ^ nl01OO27))))) & (~ (n0Ol ^ rwait_count[4]))) & (~ (n0OO ^ rwait_count[5]))) & (~ ((ni1i ^ rwait_count[6]) ^ (~ (nl01Oi30 ^ nl01Oi29))))) & (~ (ni1O ^ rwait_count[7]))), nl0ilO = 1'b1, nl100i = (((((((((nii0i & nii1O) & (~ nii1l)) & nii1i) & (~ ni0OO)) & ni0Ol) & ni0Oi) & ni0lO) & (~ ni0ll)) & (~ ni0li)), nl100l = (((((((((nii0i & nii1O) & (~ nii1l)) & nii1i) & ni0OO) & (~ ni0Ol)) & (~ ni0Oi)) & ni0lO) & (~ ni0ll)) & (~ ni0li)), nl100O = ((((((((((~ nii0i) & (~ nii1O)) & nii1l) & (~ nii1i)) & (~ ni0OO)) & ni0Ol) & ni0Oi) & (~ ni0lO)) & ni0ll) & ni0li), nl101i = (((((((((nii0i & nii1O) & (~ nii1l)) & nii1i) & ni0OO) & (~ ni0Ol)) & (~ ni0Oi)) & (~ ni0lO)) & ni0ll) & (~ ni0li)), nl101l = ((((((((((~ nii0i) & (~ nii1O)) & nii1l) & (~ nii1i)) & (~ ni0OO)) & ni0Ol) & ni0Oi) & ni0lO) & (~ ni0ll)) & ni0li), nl101O = ((((((((((~ nii0i) & (~ nii1O)) & nii1l) & (~ nii1i)) & (~ ni0OO)) & ni0Ol) & ni0Oi) & ni0lO) & (~ ni0ll)) & (~ ni0li)), nl10ii = ((((((((((~ nii0i) & (~ nii1O)) & nii1l) & (~ nii1i)) & (~ ni0OO)) & ni0Ol) & ni0Oi) & (~ ni0lO)) & ni0ll) & (~ ni0li)), nl10il = (((((((((nii0i & nii1O) & (~ nii1l)) & nii1i) & (~ ni0OO)) & ni0Ol) & ni0Oi) & (~ ni0lO)) & ni0ll) & (~ ni0li)), nl10iO = ((((((((((~ nii0i) & (~ nii1O)) & nii1l) & (~ nii1i)) & (~ ni0OO)) & ni0Ol) & ni0Oi) & (~ ni0lO)) & (~ ni0ll)) & ni0li), nl10li = (((((((((nii0i & nii1O) & (~ nii1l)) & nii1i) & (~ ni0OO)) & ni0Ol) & ni0Oi) & (~ ni0lO)) & (~ ni0ll)) & ni0li), nl10ll = (((((((((nii0i & nii1O) & (~ nii1l)) & nii1i) & (~ ni0OO)) & (~ ni0Ol)) & ni0Oi) & ni0lO) & (~ ni0ll)) & (~ ni0li)), nl10lO = ((((((((((~ nii0i) & (~ nii1O)) & nii1l) & (~ nii1i)) & ni0OO) & ni0Ol) & (~ ni0Oi)) & (~ ni0lO)) & ni0ll) & ni0li), nl10Oi = (((((((((nii0i & nii1O) & (~ nii1l)) & nii1i) & ni0OO) & (~ ni0Ol)) & ni0Oi) & (~ ni0lO)) & (~ ni0ll)) & (~ ni0li)), nl10Ol = ((((((((((~ nii0i) & (~ nii1O)) & nii1l) & (~ nii1i)) & (~ ni0OO)) & ni0Ol) & (~ ni0Oi)) & ni0lO) & ni0ll) & ni0li), nl10OO = ((((((((((~ nii0i) & (~ nii1O)) & nii1l) & (~ nii1i)) & (~ ni0OO)) & ni0Ol) & (~ ni0Oi)) & ni0lO) & ni0ll) & (~ ni0li)), nl110i = ((((((((((~ nii0i) & nii1O) & nii1l) & (~ nii1i)) & (~ ni0OO)) & ni0Ol) & (~ ni0Oi)) & (~ ni0lO)) & ni0ll) & (~ ni0li)), nl110l = ((((((((((~ nii0i) & nii1O) & nii1l) & (~ nii1i)) & ni0OO) & (~ ni0Ol)) & ni0Oi) & ni0lO) & (~ ni0ll)) & ni0li), nl110O = (((((((((nii0i & (~ nii1O)) & nii1l) & nii1i) & (~ ni0OO)) & ni0Ol) & (~ ni0Oi)) & (~ ni0lO)) & ni0ll) & (~ ni0li)), nl111i = (((((((((nii0i & (~ nii1O)) & nii1l) & nii1i) & ni0OO) & (~ ni0Ol)) & (~ ni0Oi)) & ni0lO) & ni0ll) & (~ ni0li)), nl111l = (((((((((nii0i & (~ nii1O)) & nii1l) & (~ nii1i)) & ni0OO) & (~ ni0Ol)) & (~ ni0Oi)) & ni0lO) & ni0ll) & (~ ni0li)), nl111O = (((((((((nii0i & (~ nii1O)) & nii1l) & (~ nii1i)) & ni0OO) & (~ ni0Ol)) & (~ ni0Oi)) & ni0lO) & ni0ll) & (~ ni0li)), nl11ii = ((((((((((~ nii0i) & nii1O) & (~ nii1l)) & (~ nii1i)) & ni0OO) & (~ ni0Ol)) & ni0Oi) & ni0lO) & (~ ni0ll)) & ni0li), nl11il = (((((((((nii0i & (~ nii1O)) & nii1l) & (~ nii1i)) & (~ ni0OO)) & ni0Ol) & (~ ni0Oi)) & (~ ni0lO)) & ni0ll) & (~ ni0li)), nl11iO = (((((((((nii0i & (~ nii1O)) & nii1l) & (~ nii1i)) & ni0OO) & (~ ni0Ol)) & ni0Oi) & ni0lO) & (~ ni0ll)) & ni0li), nl11li = (((~ nii0l) & (~ ni0iO)) & (~ nii0O)), nl11ll = ((((((((((((((((((((((((((((((((((((nl010i | nl010O) | (~ (nl011l38 ^ nl011l37))) | nl011i) | (~ (nl1OOl40 ^ nl1OOl39))) | nl1OOi) | (~ (nl1Oll42 ^ nl1Oll41))) | (((~ nil1O) & ((~ nil1l) & (nl1Oli | nl1OiO))) & (nl1Oii44 ^ nl1Oii43))) | nl1O0O) | (((~ nil1O) & ((~ nil1l) & (nl1O0l | nl1O0i))) & (nl1O1l46 ^ nl1O1l45))) | (~ (nl1lOO48 ^ nl1lOO47))) | nl1lOl) | ((~ nil1O) & ((~ nil1l) & (nl1lOi | nl1llO)))) | nl1lll) | ((~ nil1O) & ((~ nil1l) & (nl1lli | nl1liO)))) | ((~ nil1O) & ((~ nil1l) & (nl1lil | nl1lii)))) | ((~ nil1O) & ((~ nil1l) & (nl1l0O | nl1l0l)))) | ((~ nil1O) & ((~ nil1l) & (nl1l0i | nl1l1O)))) | ((~ nil1O) & ((~ nil1l) & (nl1l1l | nl1l1i)))) | ((~ nil1O) & ((~ nil1l) & (nl1iOO | nl1iOl)))) | ((~ nil1O) & ((~ nil1l) & (nl1iOi | nl1ilO)))) | nl1ill) | ((~ nil1O) & ((~ nil1l) & (nl1ili | nl1iiO)))) | ((~ nil1O) & ((~ nil1l) & (nl1iil | nl1iii)))) | ((~ nil1O) & ((~ nil1l) & (nl1i0O | nl1i0l)))) | nl1i0i) | ((~ nii0O) & ((~ nii0l) & (nl1i1O | nl1i1l)))) | ((~ nii0O) & ((~ nii0l) & (nl1i1i | nl10OO)))) | ((~ nii0O) & ((~ nii0l) & (nl10Ol | nl10Oi)))) | ((~ nii0O) & ((~ nii0l) & (nl10lO | nl10ll)))) | ((~ nii0O) & ((~ nii0l) & (nl10li | nl10iO)))) | ((~ nii0O) & ((~ nii0l) & (nl10il | nl10ii)))) | ((~ nii0O) & ((~ nii0l) & (nl100O | nl100l)))) | ((~ nii0O) & ((~ nii0l) & (nl100i | nl101O)))) | ((~ nii0O) & ((~ nii0l) & (nl101l | nl101i)))) | ((~ nii0O) & ((~ nii0l) & (nl11OO | nl11Ol)))) | ((~ nii0O) & ((~ nii0l) & (nl11Oi | nl11lO)))), nl11lO = (((((((((nii0i & nii1O) & (~ nii1l)) & nii1i) & (~ ni0OO)) & (~ ni0Ol)) & ni0Oi) & (~ ni0lO)) & ni0ll) & (~ ni0li)), nl11Oi = ((((((((((~ nii0i) & (~ nii1O)) & nii1l) & (~ nii1i)) & ni0OO) & ni0Ol) & (~ ni0Oi)) & ni0lO) & (~ ni0ll)) & ni0li), nl11Ol = (((((((((nii0i & nii1O) & (~ nii1l)) & nii1i) & ni0OO) & (~ ni0Ol)) & (~ ni0Oi)) & (~ ni0lO)) & (~ ni0ll)) & ni0li), nl11OO = ((((((((((~ nii0i) & (~ nii1O)) & nii1l) & (~ nii1i)) & (~ ni0OO)) & ni0Ol) & ni0Oi) & ni0lO) & ni0ll) & (~ ni0li)), nl1i0i = ((~ nil1O) & ((~ nil1l) & (niOlil | niOlii))), nl1i0l = ((((((((((~ nil1i) & (~ niiOO)) & niiOl) & (~ niiOi)) & (~ niilO)) & niill) & (~ niili)) & (~ niiiO)) & niiil) & niiii), nl1i0O = (((((((((nil1i & niiOO) & (~ niiOl)) & niiOi) & (~ niilO)) & niill) & (~ niili)) & (~ niiiO)) & niiil) & niiii), nl1i1i = (((((((((nii0i & nii1O) & (~ nii1l)) & nii1i) & (~ ni0OO)) & ni0Ol) & (~ ni0Oi)) & ni0lO) & ni0ll) & (~ ni0li)), nl1i1l = ((((((((((~ nii0i) & (~ nii1O)) & nii1l) & (~ nii1i)) & (~ ni0OO)) & ni0Ol) & (~ ni0Oi)) & ni0lO) & (~ ni0ll)) & ni0li), nl1i1O = (((((((((nii0i & nii1O) & (~ nii1l)) & nii1i) & (~ ni0OO)) & ni0Ol) & (~ ni0Oi)) & ni0lO) & (~ ni0ll)) & ni0li), nl1iii = ((((((((((~ nil1i) & (~ niiOO)) & niiOl) & (~ niiOi)) & niilO) & niill) & (~ niili)) & (~ niiiO)) & niiil) & (~ niiii)), nl1iil = (((((((((nil1i & niiOO) & (~ niiOl)) & niiOi) & niilO) & niill) & (~ niili)) & (~ niiiO)) & niiil) & (~ niiii)), nl1iiO = ((((((((((~ nil1i) & (~ niiOO)) & niiOl) & (~ niiOi)) & niilO) & niill) & (~ niili)) & (~ niiiO)) & (~ niiil)) & niiii), nl1ili = (((((((((nil1i & niiOO) & (~ niiOl)) & niiOi) & niilO) & niill) & (~ niili)) & (~ niiiO)) & (~ niiil)) & niiii), nl1ill = ((~ nil1O) & ((~ nil1l) & (niOl0O | niOl0l))), nl1ilO = (((((((((nil1i & niiOO) & (~ niiOl)) & niiOi) & (~ niilO)) & (~ niill)) & (~ niili)) & niiiO) & (~ niiil)) & niiii), nl1iOi = ((((((((((~ nil1i) & (~ niiOO)) & niiOl) & (~ niiOi)) & niilO) & niill) & niili) & (~ niiiO)) & niiil) & (~ niiii)), nl1iOl = ((((((((((~ nil1i) & (~ niiOO)) & niiOl) & (~ niiOi)) & (~ niilO)) & (~ niill)) & niili) & niiiO) & niiil) & (~ niiii)), nl1iOO = (((((((((nil1i & niiOO) & (~ niiOl)) & niiOi) & (~ niilO)) & (~ niill)) & niili) & niiiO) & niiil) & (~ niiii)), nl1l0i = (((((((((nil1i & niiOO) & (~ niiOl)) & niiOi) & niilO) & (~ niill)) & niili) & niiiO) & (~ niiil)) & (~ niiii)), nl1l0l = ((((((((((~ nil1i) & (~ niiOO)) & niiOl) & (~ niiOi)) & (~ niilO)) & (~ niill)) & niili) & (~ niiiO)) & niiil) & niiii), nl1l0O = (((((((((nil1i & niiOO) & (~ niiOl)) & niiOi) & (~ niilO)) & (~ niill)) & niili) & (~ niiiO)) & niiil) & niiii), nl1l1i = ((((((((((~ nil1i) & (~ niiOO)) & niiOl) & (~ niiOi)) & (~ niilO)) & (~ niill)) & niili) & niiiO) & (~ niiil)) & niiii), nl1l1l = (((((((((nil1i & niiOO) & (~ niiOl)) & niiOi) & (~ niilO)) & (~ niill)) & niili) & niiiO) & (~ niiil)) & niiii), nl1l1O = ((((((((((~ nil1i) & (~ niiOO)) & niiOl) & (~ niiOi)) & niilO) & (~ niill)) & niili) & niiiO) & (~ niiil)) & (~ niiii)), nl1lii = ((((((((((~ nil1i) & (~ niiOO)) & niiOl) & (~ niiOi)) & niilO) & (~ niill)) & niili) & (~ niiiO)) & niiil) & (~ niiii)), nl1lil = (((((((((nil1i & niiOO) & (~ niiOl)) & niiOi) & niilO) & (~ niill)) & niili) & (~ niiiO)) & niiil) & (~ niiii)), nl1liO = ((((((((((~ nil1i) & (~ niiOO)) & niiOl) & (~ niiOi)) & niilO) & (~ niill)) & niili) & (~ niiiO)) & (~ niiil)) & niiii), nl1lli = (((((((((nil1i & niiOO) & (~ niiOl)) & niiOi) & niilO) & (~ niill)) & niili) & (~ niiiO)) & (~ niiil)) & niiii), nl1lll = ((~ nil1O) & ((~ nil1l) & (niOl0i | niOl1O))), nl1llO = ((((((((((~ nil1i) & (~ niiOO)) & niiOl) & (~ niiOi)) & niilO) & niill) & niili) & (~ niiiO)) & (~ niiil)) & (~ niiii)), nl1lOi = (((((((((nil1i & niiOO) & (~ niiOl)) & niiOi) & (~ niilO)) & (~ niill)) & (~ niili)) & niiiO) & niiil) & niiii), nl1lOl = ((~ nil1O) & ((~ nil1l) & (niOl1l | niOl1i))), nl1O0i = ((((((((((~ nil1i) & (~ niiOO)) & niiOl) & (~ niiOi)) & niilO) & (~ niill)) & (~ niili)) & niiiO) & (~ niiil)) & niiii), nl1O0l = (((((((((nil1i & niiOO) & (~ niiOl)) & niiOi) & niilO) & (~ niill)) & (~ niili)) & niiiO) & (~ niiil)) & niiii), nl1O0O = ((~ nil1O) & ((~ nil1l) & (niOiOO | niOiOl))), nl1OiO = ((((((((((~ nil1i) & (~ niiOO)) & niiOl) & (~ niiOi)) & niilO) & (~ niill)) & (~ niili)) & (~ niiiO)) & niiil) & niiii), nl1Oli = (((((((((nil1i & niiOO) & (~ niiOl)) & niiOi) & niilO) & (~ niill)) & (~ niili)) & (~ niiiO)) & niiil) & niiii), nl1OOi = ((~ nil1O) & ((~ nil1l) & (niOiOi | niOilO))), rxelecidle_int = wire_n1l_dataout; endmodule //stratixiv_hssi_rx_digi_eii_module //synopsys translate_on //VALID FILE //IP Functional Simulation Model //VERSION_BEGIN 12.0 cbx_mgl 2012:05:31:20:09:47:SJ cbx_simgen 2012:05:31:20:08:35:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 // Copyright (C) 1991-2012 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // You may only use these simulation model output files for simulation // purposes and expressly not for synthesis or any other purposes (in which // event Altera disclaims all warranties of any kind). //synopsys translate_off //synthesis_resources = lut 14 mux21 120 `timescale 1 ps / 1 ps module stratixiv_hssi_rx_digi_pcs_channel_testbus ( chnl_test_bus_out, rtest_bus_sel, test_bus_in0, test_bus_in1, test_bus_in10, test_bus_in11, test_bus_in13, test_bus_in14, test_bus_in2, test_bus_in3, test_bus_in4, test_bus_in5, test_bus_in6, test_bus_in7) /* synthesis synthesis_clearbox=1 */; output [9:0] chnl_test_bus_out; input [3:0] rtest_bus_sel; input [9:0] test_bus_in0; input [9:0] test_bus_in1; input [9:0] test_bus_in10; input [9:0] test_bus_in11; input [9:0] test_bus_in13; input [9:0] test_bus_in14; input [9:0] test_bus_in2; input [9:0] test_bus_in3; input [9:0] test_bus_in4; input [9:0] test_bus_in5; input [9:0] test_bus_in6; input [9:0] test_bus_in7; reg n000i1; reg n000i2; reg n001i3; reg n001i4; reg n010O13; reg n010O14; reg n01il11; reg n01il12; reg n01li10; reg n01li9; reg n01lO7; reg n01lO8; reg n01Ol5; reg n01Ol6; wire wire_n00i_dataout; wire wire_n00l_dataout; wire wire_n00O_dataout; wire wire_n01i_dataout; wire wire_n01l_dataout; wire wire_n01O_dataout; wire wire_n0i_dataout; wire wire_n0ii_dataout; wire wire_n0il_dataout; wire wire_n0iO_dataout; wire wire_n0l_dataout; wire wire_n0li_dataout; wire wire_n0ll_dataout; wire wire_n0lO_dataout; wire wire_n0O_dataout; wire wire_n0Oi_dataout; wire wire_n0Ol_dataout; wire wire_n0OO_dataout; wire wire_n10i_dataout; wire wire_n10l_dataout; wire wire_n10O_dataout; wire wire_n11i_dataout; wire wire_n11l_dataout; wire wire_n11O_dataout; wire wire_n1i_dataout; wire wire_n1ii_dataout; wire wire_n1il_dataout; wire wire_n1iO_dataout; wire wire_n1l_dataout; wire wire_n1li_dataout; wire wire_n1ll_dataout; wire wire_n1lO_dataout; wire wire_n1O_dataout; wire wire_n1Oi_dataout; wire wire_n1Ol_dataout; wire wire_n1OO_dataout; wire wire_ni_dataout; wire wire_ni0i_dataout; wire wire_ni0l_dataout; wire wire_ni0O_dataout; wire wire_ni1i_dataout; wire wire_ni1l_dataout; wire wire_ni1O_dataout; wire wire_nii_dataout; wire wire_niii_dataout; wire wire_niil_dataout; wire wire_niiO_dataout; wire wire_nil_dataout; wire wire_nili_dataout; wire wire_nill_dataout; wire wire_nilO_dataout; wire wire_niO_dataout; wire wire_niOi_dataout; wire wire_niOl_dataout; wire wire_niOO_dataout; wire wire_nl_dataout; wire wire_nl0i_dataout; wire wire_nl0l_dataout; wire wire_nl0O_dataout; wire wire_nl1i_dataout; wire wire_nl1l_dataout; wire wire_nl1O_dataout; wire wire_nli_dataout; wire wire_nli0i_dataout; wire wire_nli0l_dataout; wire wire_nli0O_dataout; wire wire_nli1i_dataout; wire wire_nli1l_dataout; wire wire_nli1O_dataout; wire wire_nlii_dataout; wire wire_nliii_dataout; wire wire_nliil_dataout; wire wire_nliiO_dataout; wire wire_nlil_dataout; wire wire_nlili_dataout; wire wire_nlill_dataout; wire wire_nlilO_dataout; wire wire_nliO_dataout; wire wire_nliOi_dataout; wire wire_nliOl_dataout; wire wire_nliOO_dataout; wire wire_nll_dataout; wire wire_nll0i_dataout; wire wire_nll0l_dataout; wire wire_nll0O_dataout; wire wire_nll1i_dataout; wire wire_nll1l_dataout; wire wire_nll1O_dataout; wire wire_nlli_dataout; wire wire_nllii_dataout; wire wire_nllil_dataout; wire wire_nlliO_dataout; wire wire_nlll_dataout; wire wire_nllli_dataout; wire wire_nllll_dataout; wire wire_nlllO_dataout; wire wire_nllO_dataout; wire wire_nllOi_dataout; wire wire_nllOl_dataout; wire wire_nllOO_dataout; wire wire_nlO_dataout; wire wire_nlO0i_dataout; wire wire_nlO0l_dataout; wire wire_nlO0O_dataout; wire wire_nlO1i_dataout; wire wire_nlO1l_dataout; wire wire_nlO1O_dataout; wire wire_nlOi_dataout; wire wire_nlOii_dataout; wire wire_nlOil_dataout; wire wire_nlOiO_dataout; wire wire_nlOl_dataout; wire wire_nlOli_dataout; wire wire_nlOll_dataout; wire wire_nlOlO_dataout; wire wire_nlOO_dataout; wire wire_nlOOi_dataout; wire wire_nlOOl_dataout; wire wire_nlOOO_dataout; wire wire_nO_dataout; wire n000O; wire n001O; wire n00ii; wire n00il; wire n00iO; wire n00li; wire n00ll; wire n00lO; wire n00Oi; wire n00Ol; wire n00OO; wire n0i1i; wire n0i1l; initial n000i1 = 0; always @ ( posedge n001O) n000i1 <= n000i2; event n000i1_event; initial #1 ->n000i1_event; always @(n000i1_event) n000i1 <= {1{1'b1}}; initial n000i2 = 0; always @ ( posedge n001O) n000i2 <= n000i1; initial n001i3 = 0; always @ ( posedge n001O) n001i3 <= n001i4; event n001i3_event; initial #1 ->n001i3_event; always @(n001i3_event) n001i3 <= {1{1'b1}}; initial n001i4 = 0; always @ ( posedge n001O) n001i4 <= n001i3; initial n010O13 = 0; always @ ( posedge n001O) n010O13 <= n010O14; event n010O13_event; initial #1 ->n010O13_event; always @(n010O13_event) n010O13 <= {1{1'b1}}; initial n010O14 = 0; always @ ( posedge n001O) n010O14 <= n010O13; initial n01il11 = 0; always @ ( posedge n001O) n01il11 <= n01il12; event n01il11_event; initial #1 ->n01il11_event; always @(n01il11_event) n01il11 <= {1{1'b1}}; initial n01il12 = 0; always @ ( posedge n001O) n01il12 <= n01il11; initial n01li10 = 0; always @ ( posedge n001O) n01li10 <= n01li9; initial n01li9 = 0; always @ ( posedge n001O) n01li9 <= n01li10; event n01li9_event; initial #1 ->n01li9_event; always @(n01li9_event) n01li9 <= {1{1'b1}}; initial n01lO7 = 0; always @ ( posedge n001O) n01lO7 <= n01lO8; event n01lO7_event; initial #1 ->n01lO7_event; always @(n01lO7_event) n01lO7 <= {1{1'b1}}; initial n01lO8 = 0; always @ ( posedge n001O) n01lO8 <= n01lO7; initial n01Ol5 = 0; always @ ( posedge n001O) n01Ol5 <= n01Ol6; event n01Ol5_event; initial #1 ->n01Ol5_event; always @(n01Ol5_event) n01Ol5 <= {1{1'b1}}; initial n01Ol6 = 0; always @ ( posedge n001O) n01Ol6 <= n01Ol5; assign wire_n00i_dataout = (n00lO === 1'b1) ? test_bus_in6[3] : wire_n0Ol_dataout; assign wire_n00l_dataout = (n00lO === 1'b1) ? test_bus_in6[4] : wire_n0OO_dataout; assign wire_n00O_dataout = (n00lO === 1'b1) ? test_bus_in6[5] : wire_ni1i_dataout; assign wire_n01i_dataout = (n00lO === 1'b1) ? test_bus_in6[0] : wire_n0ll_dataout; assign wire_n01l_dataout = (n00lO === 1'b1) ? test_bus_in6[1] : wire_n0lO_dataout; assign wire_n01O_dataout = (n00lO === 1'b1) ? test_bus_in6[2] : wire_n0Oi_dataout; assign wire_n0i_dataout = (n0i1i === 1'b1) ? test_bus_in13[8] : wire_nl_dataout; assign wire_n0ii_dataout = (n00lO === 1'b1) ? test_bus_in6[6] : wire_ni1l_dataout; assign wire_n0il_dataout = (n00lO === 1'b1) ? test_bus_in6[7] : wire_ni1O_dataout; assign wire_n0iO_dataout = (n00lO === 1'b1) ? test_bus_in6[8] : wire_ni0i_dataout; assign wire_n0l_dataout = (n0i1i === 1'b1) ? test_bus_in13[9] : wire_nO_dataout; assign wire_n0li_dataout = (n00lO === 1'b1) ? test_bus_in6[9] : wire_ni0l_dataout; assign wire_n0ll_dataout = (n00Oi === 1'b1) ? test_bus_in7[0] : wire_ni0O_dataout; assign wire_n0lO_dataout = (n00Oi === 1'b1) ? test_bus_in7[1] : wire_niii_dataout; assign wire_n0O_dataout = (n0i1l === 1'b1) ? test_bus_in14[0] : test_bus_in0[0]; assign wire_n0Oi_dataout = (n00Oi === 1'b1) ? test_bus_in7[2] : wire_niil_dataout; assign wire_n0Ol_dataout = (n00Oi === 1'b1) ? test_bus_in7[3] : wire_niiO_dataout; assign wire_n0OO_dataout = (n00Oi === 1'b1) ? test_bus_in7[4] : wire_nili_dataout; assign wire_n10i_dataout = (n00li === 1'b1) ? test_bus_in4[8] : wire_n1Ol_dataout; assign wire_n10l_dataout = (n00li === 1'b1) ? test_bus_in4[9] : wire_n1OO_dataout; assign wire_n10O_dataout = (n00ll === 1'b1) ? test_bus_in5[0] : wire_n01i_dataout; assign wire_n11i_dataout = (n00li === 1'b1) ? test_bus_in4[5] : wire_n1ll_dataout; assign wire_n11l_dataout = (n00li === 1'b1) ? test_bus_in4[6] : wire_n1lO_dataout; assign wire_n11O_dataout = (n00li === 1'b1) ? test_bus_in4[7] : wire_n1Oi_dataout; assign wire_n1i_dataout = (n0i1i === 1'b1) ? test_bus_in13[5] : wire_nll_dataout; assign wire_n1ii_dataout = (n00ll === 1'b1) ? test_bus_in5[1] : wire_n01l_dataout; assign wire_n1il_dataout = (n00ll === 1'b1) ? test_bus_in5[2] : wire_n01O_dataout; assign wire_n1iO_dataout = (n00ll === 1'b1) ? test_bus_in5[3] : wire_n00i_dataout; assign wire_n1l_dataout = (n0i1i === 1'b1) ? test_bus_in13[6] : wire_nlO_dataout; assign wire_n1li_dataout = (n00ll === 1'b1) ? test_bus_in5[4] : wire_n00l_dataout; assign wire_n1ll_dataout = (n00ll === 1'b1) ? test_bus_in5[5] : wire_n00O_dataout; assign wire_n1lO_dataout = (n00ll === 1'b1) ? test_bus_in5[6] : wire_n0ii_dataout; assign wire_n1O_dataout = (n0i1i === 1'b1) ? test_bus_in13[7] : wire_ni_dataout; assign wire_n1Oi_dataout = (n00ll === 1'b1) ? test_bus_in5[7] : wire_n0il_dataout; assign wire_n1Ol_dataout = (n00ll === 1'b1) ? test_bus_in5[8] : wire_n0iO_dataout; assign wire_n1OO_dataout = (n00ll === 1'b1) ? test_bus_in5[9] : wire_n0li_dataout; assign wire_ni_dataout = (n0i1l === 1'b1) ? test_bus_in14[7] : test_bus_in0[7]; assign wire_ni0i_dataout = (n00Oi === 1'b1) ? test_bus_in7[8] : wire_niOl_dataout; assign wire_ni0l_dataout = (n00Oi === 1'b1) ? test_bus_in7[9] : wire_niOO_dataout; assign wire_ni0O_dataout = (n00Ol === 1'b1) ? test_bus_in10[0] : wire_nl1i_dataout; assign wire_ni1i_dataout = (n00Oi === 1'b1) ? test_bus_in7[5] : wire_nill_dataout; assign wire_ni1l_dataout = (n00Oi === 1'b1) ? test_bus_in7[6] : wire_nilO_dataout; assign wire_ni1O_dataout = (n00Oi === 1'b1) ? test_bus_in7[7] : wire_niOi_dataout; assign wire_nii_dataout = (n0i1l === 1'b1) ? test_bus_in14[1] : test_bus_in0[1]; assign wire_niii_dataout = (n00Ol === 1'b1) ? test_bus_in10[1] : wire_nl1l_dataout; assign wire_niil_dataout = (n00Ol === 1'b1) ? test_bus_in10[2] : wire_nl1O_dataout; assign wire_niiO_dataout = (n00Ol === 1'b1) ? test_bus_in10[3] : wire_nl0i_dataout; assign wire_nil_dataout = (n0i1l === 1'b1) ? test_bus_in14[2] : test_bus_in0[2]; assign wire_nili_dataout = (n00Ol === 1'b1) ? test_bus_in10[4] : wire_nl0l_dataout; assign wire_nill_dataout = (n00Ol === 1'b1) ? test_bus_in10[5] : wire_nl0O_dataout; assign wire_nilO_dataout = (n00Ol === 1'b1) ? test_bus_in10[6] : wire_nlii_dataout; assign wire_niO_dataout = (n0i1l === 1'b1) ? test_bus_in14[3] : test_bus_in0[3]; assign wire_niOi_dataout = (n00Ol === 1'b1) ? test_bus_in10[7] : wire_nlil_dataout; assign wire_niOl_dataout = (n00Ol === 1'b1) ? test_bus_in10[8] : wire_nliO_dataout; assign wire_niOO_dataout = (n00Ol === 1'b1) ? test_bus_in10[9] : wire_nlli_dataout; assign wire_nl_dataout = (n0i1l === 1'b1) ? test_bus_in14[8] : test_bus_in0[8]; assign wire_nl0i_dataout = (n00OO === 1'b1) ? test_bus_in11[3] : wire_nlOl_dataout; assign wire_nl0l_dataout = (n00OO === 1'b1) ? test_bus_in11[4] : wire_nlOO_dataout; assign wire_nl0O_dataout = (n00OO === 1'b1) ? test_bus_in11[5] : wire_n1i_dataout; assign wire_nl1i_dataout = (n00OO === 1'b1) ? test_bus_in11[0] : wire_nlll_dataout; assign wire_nl1l_dataout = (n00OO === 1'b1) ? test_bus_in11[1] : wire_nllO_dataout; assign wire_nl1O_dataout = (n00OO === 1'b1) ? test_bus_in11[2] : wire_nlOi_dataout; assign wire_nli_dataout = (n0i1l === 1'b1) ? test_bus_in14[4] : test_bus_in0[4]; assign wire_nli0i_dataout = (n000O === 1'b1) ? test_bus_in0[3] : wire_nliOl_dataout; assign wire_nli0l_dataout = (n000O === 1'b1) ? test_bus_in0[4] : wire_nliOO_dataout; assign wire_nli0O_dataout = (n000O === 1'b1) ? test_bus_in0[5] : wire_nll1i_dataout; assign wire_nli1i_dataout = (n000O === 1'b1) ? test_bus_in0[0] : wire_nlill_dataout; assign wire_nli1l_dataout = (n000O === 1'b1) ? test_bus_in0[1] : wire_nlilO_dataout; assign wire_nli1O_dataout = (n000O === 1'b1) ? test_bus_in0[2] : wire_nliOi_dataout; assign wire_nlii_dataout = (n00OO === 1'b1) ? test_bus_in11[6] : wire_n1l_dataout; assign wire_nliii_dataout = (n000O === 1'b1) ? test_bus_in0[6] : wire_nll1l_dataout; assign wire_nliil_dataout = (n000O === 1'b1) ? test_bus_in0[7] : wire_nll1O_dataout; assign wire_nliiO_dataout = (n000O === 1'b1) ? test_bus_in0[8] : wire_nll0i_dataout; assign wire_nlil_dataout = (n00OO === 1'b1) ? test_bus_in11[7] : wire_n1O_dataout; assign wire_nlili_dataout = (n000O === 1'b1) ? test_bus_in0[9] : wire_nll0l_dataout; assign wire_nlill_dataout = (n00ii === 1'b1) ? test_bus_in1[0] : wire_nll0O_dataout; assign wire_nlilO_dataout = (n00ii === 1'b1) ? test_bus_in1[1] : wire_nllii_dataout; assign wire_nliO_dataout = (n00OO === 1'b1) ? test_bus_in11[8] : wire_n0i_dataout; assign wire_nliOi_dataout = (n00ii === 1'b1) ? test_bus_in1[2] : wire_nllil_dataout; assign wire_nliOl_dataout = (n00ii === 1'b1) ? test_bus_in1[3] : wire_nlliO_dataout; assign wire_nliOO_dataout = (n00ii === 1'b1) ? test_bus_in1[4] : wire_nllli_dataout; assign wire_nll_dataout = (n0i1l === 1'b1) ? test_bus_in14[5] : test_bus_in0[5]; assign wire_nll0i_dataout = (n00ii === 1'b1) ? test_bus_in1[8] : wire_nllOl_dataout; assign wire_nll0l_dataout = (n00ii === 1'b1) ? test_bus_in1[9] : wire_nllOO_dataout; assign wire_nll0O_dataout = (n00il === 1'b1) ? test_bus_in2[0] : wire_nlO1i_dataout; assign wire_nll1i_dataout = (n00ii === 1'b1) ? test_bus_in1[5] : wire_nllll_dataout; assign wire_nll1l_dataout = (n00ii === 1'b1) ? test_bus_in1[6] : wire_nlllO_dataout; assign wire_nll1O_dataout = (n00ii === 1'b1) ? test_bus_in1[7] : wire_nllOi_dataout; assign wire_nlli_dataout = (n00OO === 1'b1) ? test_bus_in11[9] : wire_n0l_dataout; assign wire_nllii_dataout = (n00il === 1'b1) ? test_bus_in2[1] : wire_nlO1l_dataout; assign wire_nllil_dataout = (n00il === 1'b1) ? test_bus_in2[2] : wire_nlO1O_dataout; assign wire_nlliO_dataout = (n00il === 1'b1) ? test_bus_in2[3] : wire_nlO0i_dataout; assign wire_nlll_dataout = (n0i1i === 1'b1) ? test_bus_in13[0] : wire_n0O_dataout; assign wire_nllli_dataout = (n00il === 1'b1) ? test_bus_in2[4] : wire_nlO0l_dataout; assign wire_nllll_dataout = (n00il === 1'b1) ? test_bus_in2[5] : wire_nlO0O_dataout; assign wire_nlllO_dataout = (n00il === 1'b1) ? test_bus_in2[6] : wire_nlOii_dataout; assign wire_nllO_dataout = (n0i1i === 1'b1) ? test_bus_in13[1] : wire_nii_dataout; assign wire_nllOi_dataout = (n00il === 1'b1) ? test_bus_in2[7] : wire_nlOil_dataout; assign wire_nllOl_dataout = (n00il === 1'b1) ? test_bus_in2[8] : wire_nlOiO_dataout; assign wire_nllOO_dataout = (n00il === 1'b1) ? test_bus_in2[9] : wire_nlOli_dataout; assign wire_nlO_dataout = (n0i1l === 1'b1) ? test_bus_in14[6] : test_bus_in0[6]; assign wire_nlO0i_dataout = (n00iO === 1'b1) ? test_bus_in3[3] : wire_nlOOl_dataout; assign wire_nlO0l_dataout = (n00iO === 1'b1) ? test_bus_in3[4] : wire_nlOOO_dataout; assign wire_nlO0O_dataout = (n00iO === 1'b1) ? test_bus_in3[5] : wire_n11i_dataout; assign wire_nlO1i_dataout = (n00iO === 1'b1) ? test_bus_in3[0] : wire_nlOll_dataout; assign wire_nlO1l_dataout = (n00iO === 1'b1) ? test_bus_in3[1] : wire_nlOlO_dataout; assign wire_nlO1O_dataout = (n00iO === 1'b1) ? test_bus_in3[2] : wire_nlOOi_dataout; assign wire_nlOi_dataout = (n0i1i === 1'b1) ? test_bus_in13[2] : wire_nil_dataout; assign wire_nlOii_dataout = (n00iO === 1'b1) ? test_bus_in3[6] : wire_n11l_dataout; assign wire_nlOil_dataout = (n00iO === 1'b1) ? test_bus_in3[7] : wire_n11O_dataout; assign wire_nlOiO_dataout = (n00iO === 1'b1) ? test_bus_in3[8] : wire_n10i_dataout; assign wire_nlOl_dataout = (n0i1i === 1'b1) ? test_bus_in13[3] : wire_niO_dataout; assign wire_nlOli_dataout = (n00iO === 1'b1) ? test_bus_in3[9] : wire_n10l_dataout; assign wire_nlOll_dataout = (n00li === 1'b1) ? test_bus_in4[0] : wire_n10O_dataout; assign wire_nlOlO_dataout = (n00li === 1'b1) ? test_bus_in4[1] : wire_n1ii_dataout; assign wire_nlOO_dataout = (n0i1i === 1'b1) ? test_bus_in13[4] : wire_nli_dataout; assign wire_nlOOi_dataout = (n00li === 1'b1) ? test_bus_in4[2] : wire_n1il_dataout; assign wire_nlOOl_dataout = (n00li === 1'b1) ? test_bus_in4[3] : wire_n1iO_dataout; assign wire_nlOOO_dataout = (n00li === 1'b1) ? test_bus_in4[4] : wire_n1li_dataout; assign wire_nO_dataout = (n0i1l === 1'b1) ? test_bus_in14[9] : test_bus_in0[9]; assign chnl_test_bus_out = {wire_nlili_dataout, wire_nliiO_dataout, wire_nliil_dataout, wire_nliii_dataout, wire_nli0O_dataout, wire_nli0l_dataout, wire_nli0i_dataout, wire_nli1O_dataout, wire_nli1l_dataout, wire_nli1i_dataout}, n000O = (((((~ rtest_bus_sel[0]) & (~ rtest_bus_sel[1])) & (~ rtest_bus_sel[2])) & (~ rtest_bus_sel[3])) & (n000i2 ^ n000i1)), n00ii = (((rtest_bus_sel[0] & (~ rtest_bus_sel[1])) & (~ rtest_bus_sel[2])) & (~ rtest_bus_sel[3])), n00il = (((((~ rtest_bus_sel[0]) & rtest_bus_sel[1]) & (~ rtest_bus_sel[2])) & (~ rtest_bus_sel[3])) & (n001i4 ^ n001i3)), n00iO = (((rtest_bus_sel[0] & rtest_bus_sel[1]) & (~ rtest_bus_sel[2])) & (~ rtest_bus_sel[3])), n00li = (((((~ rtest_bus_sel[0]) & (~ rtest_bus_sel[1])) & rtest_bus_sel[2]) & (~ rtest_bus_sel[3])) & (n01Ol6 ^ n01Ol5)), n00ll = (((rtest_bus_sel[0] & (~ rtest_bus_sel[1])) & rtest_bus_sel[2]) & (~ rtest_bus_sel[3])), n00lO = ((((~ rtest_bus_sel[0]) & rtest_bus_sel[1]) & rtest_bus_sel[2]) & (~ rtest_bus_sel[3])), n00Oi = ((((rtest_bus_sel[0] & rtest_bus_sel[1]) & rtest_bus_sel[2]) & (~ rtest_bus_sel[3])) & (n01lO8 ^ n01lO7)), n00Ol = (((((~ rtest_bus_sel[0]) & rtest_bus_sel[1]) & (~ rtest_bus_sel[2])) & rtest_bus_sel[3]) & (n01li10 ^ n01li9)), n00OO = ((((rtest_bus_sel[0] & rtest_bus_sel[1]) & (~ rtest_bus_sel[2])) & rtest_bus_sel[3]) & (n01il12 ^ n01il11)), n0i1i = (((rtest_bus_sel[0] & (~ rtest_bus_sel[1])) & rtest_bus_sel[2]) & rtest_bus_sel[3]), n0i1l = (((((~ rtest_bus_sel[0]) & rtest_bus_sel[1]) & rtest_bus_sel[2]) & rtest_bus_sel[3]) & (n010O14 ^ n010O13)); endmodule //stratixiv_hssi_rx_digi_pcs_channel_testbus //synopsys translate_on //VALID FILE //IP Functional Simulation Model //VERSION_BEGIN 12.0 cbx_mgl 2012:05:31:20:09:47:SJ cbx_simgen 2012:05:31:20:08:35:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 // Copyright (C) 1991-2012 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // You may only use these simulation model output files for simulation // purposes and expressly not for synthesis or any other purposes (in which // event Altera disclaims all warranties of any kind). //synopsys translate_off //synthesis_resources = lut 18 mux21 19 `timescale 1 ps / 1 ps module stratixiv_hssi_rx_digi_iq_pipe_rx ( clk_2_b_raw, rd_enable_in_centrl, rd_enable_in_pipe_quad_down, rd_enable_in_pipe_quad_up, rd_enable_out_pipe, reset_pc_ptrs_in_centrl, reset_pc_ptrs_in_pipe_quad_down, reset_pc_ptrs_in_pipe_quad_up, reset_pc_ptrs_out_pipe, rfreerun_rx, rmaster_rx, rmaster_up_rx, rpipeline_bypass_rx, rx_div2_sync_in_centrl, rx_div2_sync_in_pipe_quad_down, rx_div2_sync_in_pipe_quad_up, rx_div2_sync_out_pipe, rx_rd_clk_raw, rx_we_in_centrl, rx_we_in_pipe_quad_down, rx_we_in_pipe_quad_up, rx_we_out_pipe, rx_wr_clk_raw, rxrst, soft_reset_rclk1, soft_reset_wclk1, speed_change_in_centrl, speed_change_in_pipe_quad_down, speed_change_in_pipe_quad_up, speed_change_out_pipe, wr_enable_in_centrl, wr_enable_in_pipe_quad_down, wr_enable_in_pipe_quad_up, wr_enable_out_pipe) /* synthesis synthesis_clearbox=1 */; input clk_2_b_raw; input rd_enable_in_centrl; input rd_enable_in_pipe_quad_down; input rd_enable_in_pipe_quad_up; output rd_enable_out_pipe; input reset_pc_ptrs_in_centrl; input reset_pc_ptrs_in_pipe_quad_down; input reset_pc_ptrs_in_pipe_quad_up; output reset_pc_ptrs_out_pipe; input rfreerun_rx; input rmaster_rx; input rmaster_up_rx; input rpipeline_bypass_rx; input rx_div2_sync_in_centrl; input rx_div2_sync_in_pipe_quad_down; input rx_div2_sync_in_pipe_quad_up; output rx_div2_sync_out_pipe; input rx_rd_clk_raw; input rx_we_in_centrl; input rx_we_in_pipe_quad_down; input rx_we_in_pipe_quad_up; output rx_we_out_pipe; input rx_wr_clk_raw; input rxrst; input soft_reset_rclk1; input soft_reset_wclk1; input speed_change_in_centrl; input speed_change_in_pipe_quad_down; input speed_change_in_pipe_quad_up; output speed_change_out_pipe; input wr_enable_in_centrl; input wr_enable_in_pipe_quad_down; input wr_enable_in_pipe_quad_up; output wr_enable_out_pipe; reg n10i10; reg n10i9; reg n10l7; reg n10l8; reg n10O5; reg n10O6; reg n11O11; reg n11O12; reg n1il3; reg n1il4; reg n1ll1; reg n1ll2; reg nlii; reg nO; wire wire_nl_CLRN; reg nliO; reg nlil_clk_prev; wire wire_nlil_CLRN; wire wire_nlil_PRN; reg nlll; reg nlli_clk_prev; wire wire_nlli_PRN; reg nlOi; reg nllO_clk_prev; wire wire_nllO_CLRN; reg ni; reg nlO_clk_prev; wire wire_nlO_CLRN; wire wire_n0i_dataout; wire wire_n0l_dataout; wire wire_n0O_dataout; wire wire_n1i_dataout; wire wire_n1l_dataout; wire wire_n1O_dataout; wire wire_nii_dataout; wire wire_nil_dataout; wire wire_niO_dataout; wire wire_nl0i_dataout; wire wire_nl0l_dataout; wire wire_nl0O_dataout; wire wire_nl1i_dataout; wire wire_nl1l_dataout; wire wire_nl1O_dataout; wire wire_nli_dataout; wire wire_nll_dataout; wire wire_nlOl_dataout; wire wire_nlOO_dataout; wire n1iO; initial n10i10 = 0; always @ ( posedge clk_2_b_raw) n10i10 <= n10i9; initial n10i9 = 0; always @ ( posedge clk_2_b_raw) n10i9 <= n10i10; event n10i9_event; initial #1 ->n10i9_event; always @(n10i9_event) n10i9 <= {1{1'b1}}; initial n10l7 = 0; always @ ( posedge clk_2_b_raw) n10l7 <= n10l8; event n10l7_event; initial #1 ->n10l7_event; always @(n10l7_event) n10l7 <= {1{1'b1}}; initial n10l8 = 0; always @ ( posedge clk_2_b_raw) n10l8 <= n10l7; initial n10O5 = 0; always @ ( posedge clk_2_b_raw) n10O5 <= n10O6; event n10O5_event; initial #1 ->n10O5_event; always @(n10O5_event) n10O5 <= {1{1'b1}}; initial n10O6 = 0; always @ ( posedge clk_2_b_raw) n10O6 <= n10O5; initial n11O11 = 0; always @ ( posedge clk_2_b_raw) n11O11 <= n11O12; event n11O11_event; initial #1 ->n11O11_event; always @(n11O11_event) n11O11 <= {1{1'b1}}; initial n11O12 = 0; always @ ( posedge clk_2_b_raw) n11O12 <= n11O11; initial n1il3 = 0; always @ ( posedge clk_2_b_raw) n1il3 <= n1il4; event n1il3_event; initial #1 ->n1il3_event; always @(n1il3_event) n1il3 <= {1{1'b1}}; initial n1il4 = 0; always @ ( posedge clk_2_b_raw) n1il4 <= n1il3; initial n1ll1 = 0; always @ ( posedge clk_2_b_raw) n1ll1 <= n1ll2; event n1ll1_event; initial #1 ->n1ll1_event; always @(n1ll1_event) n1ll1 <= {1{1'b1}}; initial n1ll2 = 0; always @ ( posedge clk_2_b_raw) n1ll2 <= n1ll1; initial begin nlii = 0; nO = 0; end always @ ( posedge clk_2_b_raw or negedge wire_nl_CLRN) begin if (wire_nl_CLRN == 1'b0) begin nlii <= 0; nO <= 0; end else begin nlii <= wire_n1l_dataout; nO <= wire_nlOO_dataout; end end assign wire_nl_CLRN = ((n1ll2 ^ n1ll1) & (~ rxrst)); initial begin nliO = 0; end always @ (rx_rd_clk_raw or wire_nlil_PRN or wire_nlil_CLRN) begin if (wire_nlil_PRN == 1'b0) begin nliO <= 1; end else if (wire_nlil_CLRN == 1'b0) begin nliO <= 0; end else if (rx_rd_clk_raw != nlil_clk_prev && rx_rd_clk_raw == 1'b1) begin nliO <= wire_n0i_dataout; end nlil_clk_prev <= rx_rd_clk_raw; end assign wire_nlil_CLRN = ((n10i10 ^ n10i9) & (~ soft_reset_rclk1)), wire_nlil_PRN = (n11O12 ^ n11O11); initial begin nlll = 0; end always @ (rx_wr_clk_raw or wire_nlli_PRN or soft_reset_wclk1) begin if (wire_nlli_PRN == 1'b0) begin nlll <= 1; end else if (soft_reset_wclk1 == 1'b1) begin nlll <= 0; end else if (rx_wr_clk_raw != nlli_clk_prev && rx_wr_clk_raw == 1'b1) begin nlll <= wire_n0O_dataout; end nlli_clk_prev <= rx_wr_clk_raw; end assign wire_nlli_PRN = (n10l8 ^ n10l7); initial begin nlOi = 0; end always @ (clk_2_b_raw or wire_nlOl_dataout or wire_nllO_CLRN) begin if (wire_nlOl_dataout == 1'b1) begin nlOi <= 1; end else if (wire_nllO_CLRN == 1'b0) begin nlOi <= 0; end else if (clk_2_b_raw != nllO_clk_prev && clk_2_b_raw == 1'b1) begin nlOi <= wire_nli_dataout; end nllO_clk_prev <= clk_2_b_raw; end assign wire_nllO_CLRN = (n10O6 ^ n10O5); event nlOi_event; initial #1 ->nlOi_event; always @(nlOi_event) nlOi <= 1; initial begin ni = 0; end always @ (clk_2_b_raw or rxrst or wire_nlO_CLRN) begin if (rxrst == 1'b1) begin ni <= 1; end else if (wire_nlO_CLRN == 1'b0) begin ni <= 0; end else if (clk_2_b_raw != nlO_clk_prev && clk_2_b_raw == 1'b1) begin ni <= wire_nil_dataout; end nlO_clk_prev <= clk_2_b_raw; end assign wire_nlO_CLRN = (n1il4 ^ n1il3); event ni_event; initial #1 ->ni_event; always @(ni_event) ni <= 1; assign wire_n0i_dataout = ((~ rmaster_rx) === 1'b1) ? wire_n0l_dataout : rd_enable_in_centrl; assign wire_n0l_dataout = (rmaster_up_rx === 1'b1) ? rd_enable_in_pipe_quad_up : rd_enable_in_pipe_quad_down; assign wire_n0O_dataout = ((~ rmaster_rx) === 1'b1) ? wire_nii_dataout : wr_enable_in_centrl; assign wire_n1i_dataout = (rmaster_up_rx === 1'b1) ? speed_change_in_pipe_quad_up : speed_change_in_pipe_quad_down; assign wire_n1l_dataout = ((~ rmaster_rx) === 1'b1) ? wire_n1O_dataout : reset_pc_ptrs_in_centrl; assign wire_n1O_dataout = (rmaster_up_rx === 1'b1) ? reset_pc_ptrs_in_pipe_quad_up : reset_pc_ptrs_in_pipe_quad_down; assign wire_nii_dataout = (rmaster_up_rx === 1'b1) ? wr_enable_in_pipe_quad_up : wr_enable_in_pipe_quad_down; assign wire_nil_dataout = ((~ rmaster_rx) === 1'b1) ? wire_niO_dataout : rx_we_in_centrl; assign wire_niO_dataout = (rmaster_up_rx === 1'b1) ? rx_we_in_pipe_quad_up : rx_we_in_pipe_quad_down; assign wire_nl0i_dataout = (rpipeline_bypass_rx === 1'b1) ? wire_n0O_dataout : nlll; assign wire_nl0l_dataout = (rpipeline_bypass_rx === 1'b1) ? wire_nil_dataout : ni; assign wire_nl0O_dataout = (rpipeline_bypass_rx === 1'b1) ? wire_nli_dataout : nlOi; assign wire_nl1i_dataout = (rpipeline_bypass_rx === 1'b1) ? wire_nlOO_dataout : nO; assign wire_nl1l_dataout = (rpipeline_bypass_rx === 1'b1) ? wire_n1l_dataout : nlii; assign wire_nl1O_dataout = (rpipeline_bypass_rx === 1'b1) ? wire_n0i_dataout : nliO; assign wire_nli_dataout = ((~ rmaster_rx) === 1'b1) ? wire_nll_dataout : rx_div2_sync_in_centrl; assign wire_nll_dataout = (rmaster_up_rx === 1'b1) ? rx_div2_sync_in_pipe_quad_up : rx_div2_sync_in_pipe_quad_down; and(wire_nlOl_dataout, rxrst, ~(rfreerun_rx)); assign wire_nlOO_dataout = ((~ rmaster_rx) === 1'b1) ? wire_n1i_dataout : speed_change_in_centrl; assign n1iO = 1'b1, rd_enable_out_pipe = wire_nl1O_dataout, reset_pc_ptrs_out_pipe = wire_nl1l_dataout, rx_div2_sync_out_pipe = wire_nl0O_dataout, rx_we_out_pipe = wire_nl0l_dataout, speed_change_out_pipe = wire_nl1i_dataout, wr_enable_out_pipe = wire_nl0i_dataout; endmodule //stratixiv_hssi_rx_digi_iq_pipe_rx //synopsys translate_on //VALID FILE //IP Functional Simulation Model //VERSION_BEGIN 12.0 cbx_mgl 2012:05:31:20:09:47:SJ cbx_simgen 2012:05:31:20:08:35:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 // Copyright (C) 1991-2012 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // You may only use these simulation model output files for simulation // purposes and expressly not for synthesis or any other purposes (in which // event Altera disclaims all warranties of any kind). //synopsys translate_off //synthesis_resources = lut 122 mux21 276 oper_add 1 oper_decoder 1 oper_less_than 1 oper_mux 36 oper_selector 10 `timescale 1 ps / 1 ps module stratixiv_hssi_rx_digi_prbs_ver ( cid_en, data_in, encdet_prbs, prbs_done, prbs_err, prbs_err_lt, rall_one_dect_only, rcid_len, rcid_pattern, rcvd_clk, rpma_doublewidth_rx, rpmadwidth_rx, rprbs_clr_rslt_rx, rprbs_en_rx, rprbs_sel, scan_mode, soft_reset, sync_status, verify_on) /* synthesis synthesis_clearbox=1 */; input cid_en; input [19:0] data_in; output encdet_prbs; output prbs_done; output prbs_err; output prbs_err_lt; input rall_one_dect_only; input [7:0] rcid_len; input rcid_pattern; input rcvd_clk; input rpma_doublewidth_rx; input rpmadwidth_rx; input rprbs_clr_rslt_rx; input rprbs_en_rx; input [2:0] rprbs_sel; input scan_mode; input soft_reset; input sync_status; output verify_on; reg nillOi49; reg nillOi50; reg nillOl47; reg nillOl48; reg nillOO45; reg nillOO46; reg nilO1i43; reg nilO1i44; reg nilO1O41; reg nilO1O42; reg nilOiO39; reg nilOiO40; reg niO00i21; reg niO00i22; reg niO01l23; reg niO01l24; reg niO0iO19; reg niO0iO20; reg niO0ll17; reg niO0ll18; reg niO0lO15; reg niO0lO16; reg niO0Oi13; reg niO0Oi14; reg niO0OO11; reg niO0OO12; reg niO10i35; reg niO10i36; reg niO10l33; reg niO10l34; reg niO11i37; reg niO11i38; reg niO1li31; reg niO1li32; reg niO1ll29; reg niO1ll30; reg niO1lO27; reg niO1lO28; reg niO1Ol25; reg niO1Ol26; reg niOi0l3; reg niOi0l4; reg niOi1i10; reg niOi1i9; reg niOi1l7; reg niOi1l8; reg niOi1O5; reg niOi1O6; reg niOiii1; reg niOiii2; reg n0i; reg n0l; reg n0O; reg nii; reg nil; reg niO; reg nl; reg nl0i; reg nl0l; reg nl0O; reg nl1i; reg nl1l; reg nl1O; reg nli; reg nlii; reg nlil; reg nliO; reg nll; reg nlO; wire wire_ni_CLRN; reg niOi; reg nlliO; reg nilO_clk_prev; wire wire_nilO_PRN; reg niOO; reg nli0lO; reg nlii0O; reg nliOl; reg nll0il; reg nll0iO; reg nll0li; reg nll0ll; reg nll0lO; reg nll0Oi; reg nll0Ol; reg nll0OO; reg nlli0i; reg nlli0l; reg nlli0O; reg nlli1i; reg nlli1l; reg nlli1O; reg nlliii; reg nlliil; reg nlliiO; reg nllili; reg nllill; reg nllilO; reg nlliOi; reg nlliOl; reg nlliOO; reg nlll0i; reg nlll0l; reg nlll0O; reg nlll1i; reg nlll1l; reg nlll1O; reg nlllii; reg nliOi_clk_prev; wire wire_nliOi_CLRN; reg nli00O; reg nli0ii; reg nli0il; reg nli0iO; reg nli0li; reg nli0ll; reg nliiO; reg nlili; reg nlill; reg nlilO; reg nliOO; reg nll0i; reg nll1i; reg nll1l; reg nlllil; reg nll0l; reg nllil; reg nllii_clk_prev; wire wire_nllii_CLRN; wire wire_nllii_PRN; wire wire_n00i_dataout; wire wire_n00l_dataout; wire wire_n00O_dataout; wire wire_n01i_dataout; wire wire_n01l_dataout; wire wire_n01O_dataout; wire wire_n0i0l_dataout; wire wire_n0i0O_dataout; wire wire_n0ii_dataout; wire wire_n0iii_dataout; wire wire_n0iil_dataout; wire wire_n0iiO_dataout; wire wire_n0il_dataout; wire wire_n0ili_dataout; wire wire_n0ill_dataout; wire wire_n0ilO_dataout; wire wire_n0iO_dataout; wire wire_n0iOi_dataout; wire wire_n0iOl_dataout; wire wire_n0iOO_dataout; wire wire_n0l0i_dataout; wire wire_n0l0l_dataout; wire wire_n0l0O_dataout; wire wire_n0l1i_dataout; wire wire_n0l1l_dataout; wire wire_n0l1O_dataout; wire wire_n0li_dataout; wire wire_n0lii_dataout; wire wire_n0lil_dataout; wire wire_n0liO_dataout; wire wire_n0lli_dataout; wire wire_n0lll_dataout; wire wire_n0llO_dataout; wire wire_n0lOi_dataout; wire wire_n0lOl_dataout; wire wire_n0lOO_dataout; wire wire_n0O0i_dataout; wire wire_n0O0l_dataout; wire wire_n0O0O_dataout; wire wire_n0O1i_dataout; wire wire_n0O1l_dataout; wire wire_n0O1O_dataout; wire wire_n0Oii_dataout; wire wire_n0Oil_dataout; wire wire_n0OiO_dataout; wire wire_n0Oli_dataout; wire wire_n0Oll_dataout; wire wire_n0OlO_dataout; wire wire_n0OO_dataout; wire wire_n0OOi_dataout; wire wire_n10i_dataout; wire wire_n10l_dataout; wire wire_n10O_dataout; wire wire_n110i_dataout; wire wire_n111i_dataout; wire wire_n111l_dataout; wire wire_n111O_dataout; wire wire_n11i_dataout; wire wire_n11l_dataout; wire wire_n11O_dataout; wire wire_n1i_dataout; wire wire_n1ii_dataout; wire wire_n1il_dataout; wire wire_n1iO_dataout; wire wire_n1l_dataout; wire wire_n1li_dataout; wire wire_n1ll_dataout; wire wire_n1lO_dataout; wire wire_n1Oi_dataout; wire wire_n1Ol_dataout; wire wire_n1OO_dataout; wire wire_ni0i_dataout; wire wire_ni0il_dataout; wire wire_ni0li_dataout; wire wire_ni0ll_dataout; wire wire_ni0Ol_dataout; wire wire_ni0OO_dataout; wire wire_ni1i_dataout; wire wire_ni1l_dataout; wire wire_ni1O_dataout; wire wire_nii1i_dataout; wire wire_nilii_dataout; wire wire_nilil_dataout; wire wire_niliO_dataout; wire wire_nillO_dataout; wire wire_nilOi_dataout; wire wire_nilOl_dataout; wire wire_nilOO_dataout; wire wire_niO0i_dataout; wire wire_niO0l_dataout; wire wire_niO0O_dataout; wire wire_niO1i_dataout; wire wire_niO1l_dataout; wire wire_niO1O_dataout; wire wire_niOii_dataout; wire wire_niOil_dataout; wire wire_niOiO_dataout; wire wire_niOli_dataout; wire wire_niOll_dataout; wire wire_niOlO_dataout; wire wire_niOOi_dataout; wire wire_niOOl_dataout; wire wire_niOOO_dataout; wire wire_nl00l_dataout; wire wire_nl00O_dataout; wire wire_nl01i_dataout; wire wire_nl01l_dataout; wire wire_nl01O_dataout; wire wire_nl0ii_dataout; wire wire_nl0il_dataout; wire wire_nl0li_dataout; wire wire_nl0ll_dataout; wire wire_nl0lO_dataout; wire wire_nl0Oi_dataout; wire wire_nl0Ol_dataout; wire wire_nl10i_dataout; wire wire_nl10l_dataout; wire wire_nl10O_dataout; wire wire_nl11i_dataout; wire wire_nl11l_dataout; wire wire_nl11O_dataout; wire wire_nl1ii_dataout; wire wire_nl1il_dataout; wire wire_nl1iO_dataout; wire wire_nl1li_dataout; wire wire_nl1ll_dataout; wire wire_nl1lO_dataout; wire wire_nl1Oi_dataout; wire wire_nl1Ol_dataout; wire wire_nl1OO_dataout; wire wire_nli0i_dataout; wire wire_nli0l_dataout; wire wire_nli0Oi_dataout; wire wire_nli0Ol_dataout; wire wire_nli0OO_dataout; wire wire_nli1i_dataout; wire wire_nli1l_dataout; wire wire_nli1O_dataout; wire wire_nlii0i_dataout; wire wire_nlii0l_dataout; wire wire_nlii1i_dataout; wire wire_nlii1l_dataout; wire wire_nlii1O_dataout; wire wire_nliiii_dataout; wire wire_nliiil_dataout; wire wire_nliil_dataout; wire wire_nliOil_dataout; wire wire_nll01i_dataout; wire wire_nll0O_dataout; wire wire_nll1li_dataout; wire wire_nll1ll_dataout; wire wire_nll1OO_dataout; wire wire_nlli_dataout; wire wire_nlll_dataout; wire wire_nllli_dataout; wire wire_nllliO_dataout; wire wire_nllll_dataout; wire wire_nlllli_dataout; wire wire_nlllll_dataout; wire wire_nllllO_dataout; wire wire_nlllO_dataout; wire wire_nlllOi_dataout; wire wire_nlllOl_dataout; wire wire_nlllOO_dataout; wire wire_nllO_dataout; wire wire_nllO0i_dataout; wire wire_nllO0l_dataout; wire wire_nllO0O_dataout; wire wire_nllO1i_dataout; wire wire_nllO1l_dataout; wire wire_nllO1O_dataout; wire wire_nllOi_dataout; wire wire_nllOii_dataout; wire wire_nllOil_dataout; wire wire_nllOiO_dataout; wire wire_nllOl_dataout; wire wire_nllOli_dataout; wire wire_nllOll_dataout; wire wire_nllOlO_dataout; wire wire_nllOO_dataout; wire wire_nllOOi_dataout; wire wire_nllOOl_dataout; wire wire_nllOOO_dataout; wire wire_nlO00i_dataout; wire wire_nlO00l_dataout; wire wire_nlO00O_dataout; wire wire_nlO01i_dataout; wire wire_nlO01l_dataout; wire wire_nlO01O_dataout; wire wire_nlO0i_dataout; wire wire_nlO0ii_dataout; wire wire_nlO0il_dataout; wire wire_nlO0iO_dataout; wire wire_nlO0l_dataout; wire wire_nlO0li_dataout; wire wire_nlO0ll_dataout; wire wire_nlO0lO_dataout; wire wire_nlO0O_dataout; wire wire_nlO0Oi_dataout; wire wire_nlO0Ol_dataout; wire wire_nlO0OO_dataout; wire wire_nlO10i_dataout; wire wire_nlO10l_dataout; wire wire_nlO10O_dataout; wire wire_nlO11i_dataout; wire wire_nlO11l_dataout; wire wire_nlO11O_dataout; wire wire_nlO1i_dataout; wire wire_nlO1ii_dataout; wire wire_nlO1il_dataout; wire wire_nlO1iO_dataout; wire wire_nlO1l_dataout; wire wire_nlO1li_dataout; wire wire_nlO1ll_dataout; wire wire_nlO1lO_dataout; wire wire_nlO1O_dataout; wire wire_nlO1Oi_dataout; wire wire_nlO1Ol_dataout; wire wire_nlO1OO_dataout; wire wire_nlOi_dataout; wire wire_nlOi0i_dataout; wire wire_nlOi0l_dataout; wire wire_nlOi0O_dataout; wire wire_nlOi1i_dataout; wire wire_nlOi1l_dataout; wire wire_nlOi1O_dataout; wire wire_nlOii_dataout; wire wire_nlOiii_dataout; wire wire_nlOiil_dataout; wire wire_nlOiiO_dataout; wire wire_nlOil_dataout; wire wire_nlOili_dataout; wire wire_nlOill_dataout; wire wire_nlOilO_dataout; wire wire_nlOiO_dataout; wire wire_nlOiOi_dataout; wire wire_nlOiOl_dataout; wire wire_nlOiOO_dataout; wire wire_nlOl_dataout; wire wire_nlOl0i_dataout; wire wire_nlOl0l_dataout; wire wire_nlOl0O_dataout; wire wire_nlOl1i_dataout; wire wire_nlOl1l_dataout; wire wire_nlOl1O_dataout; wire wire_nlOli_dataout; wire wire_nlOlii_dataout; wire wire_nlOlil_dataout; wire wire_nlOliO_dataout; wire wire_nlOll_dataout; wire wire_nlOlli_dataout; wire wire_nlOlll_dataout; wire wire_nlOllO_dataout; wire wire_nlOlO_dataout; wire wire_nlOlOi_dataout; wire wire_nlOlOl_dataout; wire wire_nlOlOO_dataout; wire wire_nlOO_dataout; wire wire_nlOO0i_dataout; wire wire_nlOO0l_dataout; wire wire_nlOO0O_dataout; wire wire_nlOO1i_dataout; wire wire_nlOO1l_dataout; wire wire_nlOO1O_dataout; wire wire_nlOOi_dataout; wire wire_nlOOii_dataout; wire wire_nlOOil_dataout; wire wire_nlOOiO_dataout; wire wire_nlOOl_dataout; wire wire_nlOOli_dataout; wire wire_nlOOll_dataout; wire wire_nlOOlO_dataout; wire wire_nlOOO_dataout; wire wire_nlOOOi_dataout; wire wire_nlOOOl_dataout; wire wire_nlOOOO_dataout; wire [8:0] wire_n1O_o; wire [31:0] wire_nil0O_o; wire wire_nill_o; wire wire_n100i_o; wire wire_n100l_o; wire wire_n100O_o; wire wire_n101i_o; wire wire_n101l_o; wire wire_n101O_o; wire wire_n10ii_o; wire wire_n10il_o; wire wire_n10iO_o; wire wire_n10li_o; wire wire_n10ll_o; wire wire_n10lO_o; wire wire_n110l_o; wire wire_n110O_o; wire wire_n11ii_o; wire wire_n11il_o; wire wire_n11iO_o; wire wire_n11li_o; wire wire_n11ll_o; wire wire_n11lO_o; wire wire_n11Oi_o; wire wire_n11Ol_o; wire wire_n11OO_o; wire wire_nii0i_o; wire wire_nii0l_o; wire wire_nii0O_o; wire wire_nii1O_o; wire wire_niiii_o; wire wire_niiiO_o; wire wire_niill_o; wire wire_niilO_o; wire wire_nliiiO_o; wire wire_nliili_o; wire wire_nliill_o; wire wire_nliilO_o; wire wire_nliiOi_o; wire wire_n0ll_o; wire wire_n0lO_o; wire wire_n0Oi_o; wire wire_n0Ol_o; wire wire_ni0iO_o; wire wire_ni0lO_o; wire wire_nl00i_o; wire wire_nl0iO_o; wire wire_nl0OO_o; wire wire_nli0O_o; wire niil0i; wire niil0l; wire niil0O; wire niil1l; wire niil1O; wire niilii; wire niilil; wire niiliO; wire niilli; wire niilll; wire niillO; wire niilOi; wire niilOl; wire niilOO; wire niiO0i; wire niiO0l; wire niiO0O; wire niiO1i; wire niiO1l; wire niiO1O; wire niiOii; wire niiOil; wire niiOiO; wire niiOli; wire niiOll; wire niiOlO; wire niiOOi; wire niiOOl; wire niiOOO; wire nil00i; wire nil00l; wire nil00O; wire nil01i; wire nil01l; wire nil01O; wire nil0ii; wire nil0il; wire nil0iO; wire nil0li; wire nil0ll; wire nil0lO; wire nil0Oi; wire nil0Ol; wire nil0OO; wire nil10i; wire nil10l; wire nil10O; wire nil11i; wire nil11l; wire nil11O; wire nil1ii; wire nil1il; wire nil1iO; wire nil1li; wire nil1ll; wire nil1lO; wire nil1Oi; wire nil1Ol; wire nil1OO; wire nili0i; wire nili0l; wire nili0O; wire nili1i; wire nili1l; wire nili1O; wire niliii; wire niliil; wire niliiO; wire nilili; wire nilill; wire nililO; wire niliOi; wire niliOl; wire niliOO; wire nill0i; wire nill0l; wire nill0O; wire nill1i; wire nill1l; wire nill1O; wire nillii; wire nillil; wire nilliO; wire nillli; wire nillll; wire nilllO; wire nilO0i; wire nilO0l; wire nilO0O; wire nilO1l; wire nilOii; wire nilOil; wire nilOli; wire nilOll; wire nilOlO; wire nilOOi; wire nilOOl; wire nilOOO; wire niO00O; wire niO01i; wire niO0ii; wire niO0il; wire niO0Ol; wire niO10O; wire niO11l; wire niO11O; wire niO1ii; wire niO1il; wire niO1iO; wire niO1Oi; wire niO1OO; wire niOi0i; wire niOi0O; initial nillOi49 = 0; always @ ( posedge rcvd_clk) nillOi49 <= nillOi50; event nillOi49_event; initial #1 ->nillOi49_event; always @(nillOi49_event) nillOi49 <= {1{1'b1}}; initial nillOi50 = 0; always @ ( posedge rcvd_clk) nillOi50 <= nillOi49; initial nillOl47 = 0; always @ ( posedge rcvd_clk) nillOl47 <= nillOl48; event nillOl47_event; initial #1 ->nillOl47_event; always @(nillOl47_event) nillOl47 <= {1{1'b1}}; initial nillOl48 = 0; always @ ( posedge rcvd_clk) nillOl48 <= nillOl47; initial nillOO45 = 0; always @ ( posedge rcvd_clk) nillOO45 <= nillOO46; event nillOO45_event; initial #1 ->nillOO45_event; always @(nillOO45_event) nillOO45 <= {1{1'b1}}; initial nillOO46 = 0; always @ ( posedge rcvd_clk) nillOO46 <= nillOO45; initial nilO1i43 = 0; always @ ( posedge rcvd_clk) nilO1i43 <= nilO1i44; event nilO1i43_event; initial #1 ->nilO1i43_event; always @(nilO1i43_event) nilO1i43 <= {1{1'b1}}; initial nilO1i44 = 0; always @ ( posedge rcvd_clk) nilO1i44 <= nilO1i43; initial nilO1O41 = 0; always @ ( posedge rcvd_clk) nilO1O41 <= nilO1O42; event nilO1O41_event; initial #1 ->nilO1O41_event; always @(nilO1O41_event) nilO1O41 <= {1{1'b1}}; initial nilO1O42 = 0; always @ ( posedge rcvd_clk) nilO1O42 <= nilO1O41; initial nilOiO39 = 0; always @ ( posedge rcvd_clk) nilOiO39 <= nilOiO40; event nilOiO39_event; initial #1 ->nilOiO39_event; always @(nilOiO39_event) nilOiO39 <= {1{1'b1}}; initial nilOiO40 = 0; always @ ( posedge rcvd_clk) nilOiO40 <= nilOiO39; initial niO00i21 = 0; always @ ( posedge rcvd_clk) niO00i21 <= niO00i22; event niO00i21_event; initial #1 ->niO00i21_event; always @(niO00i21_event) niO00i21 <= {1{1'b1}}; initial niO00i22 = 0; always @ ( posedge rcvd_clk) niO00i22 <= niO00i21; initial niO01l23 = 0; always @ ( posedge rcvd_clk) niO01l23 <= niO01l24; event niO01l23_event; initial #1 ->niO01l23_event; always @(niO01l23_event) niO01l23 <= {1{1'b1}}; initial niO01l24 = 0; always @ ( posedge rcvd_clk) niO01l24 <= niO01l23; initial niO0iO19 = 0; always @ ( posedge rcvd_clk) niO0iO19 <= niO0iO20; event niO0iO19_event; initial #1 ->niO0iO19_event; always @(niO0iO19_event) niO0iO19 <= {1{1'b1}}; initial niO0iO20 = 0; always @ ( posedge rcvd_clk) niO0iO20 <= niO0iO19; initial niO0ll17 = 0; always @ ( posedge rcvd_clk) niO0ll17 <= niO0ll18; event niO0ll17_event; initial #1 ->niO0ll17_event; always @(niO0ll17_event) niO0ll17 <= {1{1'b1}}; initial niO0ll18 = 0; always @ ( posedge rcvd_clk) niO0ll18 <= niO0ll17; initial niO0lO15 = 0; always @ ( posedge rcvd_clk) niO0lO15 <= niO0lO16; event niO0lO15_event; initial #1 ->niO0lO15_event; always @(niO0lO15_event) niO0lO15 <= {1{1'b1}}; initial niO0lO16 = 0; always @ ( posedge rcvd_clk) niO0lO16 <= niO0lO15; initial niO0Oi13 = 0; always @ ( posedge rcvd_clk) niO0Oi13 <= niO0Oi14; event niO0Oi13_event; initial #1 ->niO0Oi13_event; always @(niO0Oi13_event) niO0Oi13 <= {1{1'b1}}; initial niO0Oi14 = 0; always @ ( posedge rcvd_clk) niO0Oi14 <= niO0Oi13; initial niO0OO11 = 0; always @ ( posedge rcvd_clk) niO0OO11 <= niO0OO12; event niO0OO11_event; initial #1 ->niO0OO11_event; always @(niO0OO11_event) niO0OO11 <= {1{1'b1}}; initial niO0OO12 = 0; always @ ( posedge rcvd_clk) niO0OO12 <= niO0OO11; initial niO10i35 = 0; always @ ( posedge rcvd_clk) niO10i35 <= niO10i36; event niO10i35_event; initial #1 ->niO10i35_event; always @(niO10i35_event) niO10i35 <= {1{1'b1}}; initial niO10i36 = 0; always @ ( posedge rcvd_clk) niO10i36 <= niO10i35; initial niO10l33 = 0; always @ ( posedge rcvd_clk) niO10l33 <= niO10l34; event niO10l33_event; initial #1 ->niO10l33_event; always @(niO10l33_event) niO10l33 <= {1{1'b1}}; initial niO10l34 = 0; always @ ( posedge rcvd_clk) niO10l34 <= niO10l33; initial niO11i37 = 0; always @ ( posedge rcvd_clk) niO11i37 <= niO11i38; event niO11i37_event; initial #1 ->niO11i37_event; always @(niO11i37_event) niO11i37 <= {1{1'b1}}; initial niO11i38 = 0; always @ ( posedge rcvd_clk) niO11i38 <= niO11i37; initial niO1li31 = 0; always @ ( posedge rcvd_clk) niO1li31 <= niO1li32; event niO1li31_event; initial #1 ->niO1li31_event; always @(niO1li31_event) niO1li31 <= {1{1'b1}}; initial niO1li32 = 0; always @ ( posedge rcvd_clk) niO1li32 <= niO1li31; initial niO1ll29 = 0; always @ ( posedge rcvd_clk) niO1ll29 <= niO1ll30; event niO1ll29_event; initial #1 ->niO1ll29_event; always @(niO1ll29_event) niO1ll29 <= {1{1'b1}}; initial niO1ll30 = 0; always @ ( posedge rcvd_clk) niO1ll30 <= niO1ll29; initial niO1lO27 = 0; always @ ( posedge rcvd_clk) niO1lO27 <= niO1lO28; event niO1lO27_event; initial #1 ->niO1lO27_event; always @(niO1lO27_event) niO1lO27 <= {1{1'b1}}; initial niO1lO28 = 0; always @ ( posedge rcvd_clk) niO1lO28 <= niO1lO27; initial niO1Ol25 = 0; always @ ( posedge rcvd_clk) niO1Ol25 <= niO1Ol26; event niO1Ol25_event; initial #1 ->niO1Ol25_event; always @(niO1Ol25_event) niO1Ol25 <= {1{1'b1}}; initial niO1Ol26 = 0; always @ ( posedge rcvd_clk) niO1Ol26 <= niO1Ol25; initial niOi0l3 = 0; always @ ( posedge rcvd_clk) niOi0l3 <= niOi0l4; event niOi0l3_event; initial #1 ->niOi0l3_event; always @(niOi0l3_event) niOi0l3 <= {1{1'b1}}; initial niOi0l4 = 0; always @ ( posedge rcvd_clk) niOi0l4 <= niOi0l3; initial niOi1i10 = 0; always @ ( posedge rcvd_clk) niOi1i10 <= niOi1i9; initial niOi1i9 = 0; always @ ( posedge rcvd_clk) niOi1i9 <= niOi1i10; event niOi1i9_event; initial #1 ->niOi1i9_event; always @(niOi1i9_event) niOi1i9 <= {1{1'b1}}; initial niOi1l7 = 0; always @ ( posedge rcvd_clk) niOi1l7 <= niOi1l8; event niOi1l7_event; initial #1 ->niOi1l7_event; always @(niOi1l7_event) niOi1l7 <= {1{1'b1}}; initial niOi1l8 = 0; always @ ( posedge rcvd_clk) niOi1l8 <= niOi1l7; initial niOi1O5 = 0; always @ ( posedge rcvd_clk) niOi1O5 <= niOi1O6; event niOi1O5_event; initial #1 ->niOi1O5_event; always @(niOi1O5_event) niOi1O5 <= {1{1'b1}}; initial niOi1O6 = 0; always @ ( posedge rcvd_clk) niOi1O6 <= niOi1O5; initial niOiii1 = 0; always @ ( posedge rcvd_clk) niOiii1 <= niOiii2; event niOiii1_event; initial #1 ->niOiii1_event; always @(niOiii1_event) niOiii1 <= {1{1'b1}}; initial niOiii2 = 0; always @ ( posedge rcvd_clk) niOiii2 <= niOiii1; initial begin n0i = 0; n0l = 0; n0O = 0; nii = 0; nil = 0; niO = 0; nl = 0; nl0i = 0; nl0l = 0; nl0O = 0; nl1i = 0; nl1l = 0; nl1O = 0; nli = 0; nlii = 0; nlil = 0; nliO = 0; nll = 0; nlO = 0; end always @ ( posedge rcvd_clk or negedge wire_ni_CLRN) begin if (wire_ni_CLRN == 1'b0) begin n0i <= 0; n0l <= 0; n0O <= 0; nii <= 0; nil <= 0; niO <= 0; nl <= 0; nl0i <= 0; nl0l <= 0; nl0O <= 0; nl1i <= 0; nl1l <= 0; nl1O <= 0; nli <= 0; nlii <= 0; nlil <= 0; nliO <= 0; nll <= 0; nlO <= 0; end else begin n0i <= data_in[1]; n0l <= data_in[2]; n0O <= data_in[3]; nii <= data_in[4]; nil <= data_in[5]; niO <= data_in[6]; nl <= cid_en; nl0i <= wire_nlOi_dataout; nl0l <= wire_nlOl_dataout; nl0O <= wire_nlOO_dataout; nl1i <= wire_nlli_dataout; nl1l <= wire_nlll_dataout; nl1O <= wire_nllO_dataout; nli <= data_in[7]; nlii <= wire_n1i_dataout; nlil <= wire_n1l_dataout; nliO <= data_in[0]; nll <= niOi0O; nlO <= nl; end end assign wire_ni_CLRN = ((niOi0l4 ^ niOi0l3) & (~ soft_reset)); initial begin niOi = 0; nlliO = 0; end always @ (rcvd_clk or wire_nilO_PRN or soft_reset) begin if (wire_nilO_PRN == 1'b0) begin niOi <= 1; nlliO <= 1; end else if (soft_reset == 1'b1) begin niOi <= 0; nlliO <= 0; end else if (niO0Ol == 1'b1) if (rcvd_clk != nilO_clk_prev && rcvd_clk == 1'b1) begin niOi <= wire_n0Oi_o; nlliO <= wire_n0lO_o; end nilO_clk_prev <= rcvd_clk; end assign wire_nilO_PRN = (niO0Oi14 ^ niO0Oi13); initial begin niOO = 0; end always @ ( posedge rcvd_clk or posedge soft_reset) begin if (soft_reset == 1'b1) begin niOO <= 1; end else if (niO0Ol == 1'b1) begin niOO <= wire_n0Ol_o; end end event niOO_event; initial #1 ->niOO_event; always @(niOO_event) niOO <= 1; initial begin nli0lO = 0; nlii0O = 0; nliOl = 0; nll0il = 0; nll0iO = 0; nll0li = 0; nll0ll = 0; nll0lO = 0; nll0Oi = 0; nll0Ol = 0; nll0OO = 0; nlli0i = 0; nlli0l = 0; nlli0O = 0; nlli1i = 0; nlli1l = 0; nlli1O = 0; nlliii = 0; nlliil = 0; nlliiO = 0; nllili = 0; nllill = 0; nllilO = 0; nlliOi = 0; nlliOl = 0; nlliOO = 0; nlll0i = 0; nlll0l = 0; nlll0O = 0; nlll1i = 0; nlll1l = 0; nlll1O = 0; nlllii = 0; end always @ (rcvd_clk or wire_nll0O_dataout or wire_nliOi_CLRN) begin if (wire_nll0O_dataout == 1'b1) begin nli0lO <= 1; nlii0O <= 1; nliOl <= 1; nll0il <= 1; nll0iO <= 1; nll0li <= 1; nll0ll <= 1; nll0lO <= 1; nll0Oi <= 1; nll0Ol <= 1; nll0OO <= 1; nlli0i <= 1; nlli0l <= 1; nlli0O <= 1; nlli1i <= 1; nlli1l <= 1; nlli1O <= 1; nlliii <= 1; nlliil <= 1; nlliiO <= 1; nllili <= 1; nllill <= 1; nllilO <= 1; nlliOi <= 1; nlliOl <= 1; nlliOO <= 1; nlll0i <= 1; nlll0l <= 1; nlll0O <= 1; nlll1i <= 1; nlll1l <= 1; nlll1O <= 1; nlllii <= 1; end else if (wire_nliOi_CLRN == 1'b0) begin nli0lO <= 0; nlii0O <= 0; nliOl <= 0; nll0il <= 0; nll0iO <= 0; nll0li <= 0; nll0ll <= 0; nll0lO <= 0; nll0Oi <= 0; nll0Ol <= 0; nll0OO <= 0; nlli0i <= 0; nlli0l <= 0; nlli0O <= 0; nlli1i <= 0; nlli1l <= 0; nlli1O <= 0; nlliii <= 0; nlliil <= 0; nlliiO <= 0; nllili <= 0; nllill <= 0; nllilO <= 0; nlliOi <= 0; nlliOl <= 0; nlliOO <= 0; nlll0i <= 0; nlll0l <= 0; nlll0O <= 0; nlll1i <= 0; nlll1l <= 0; nlll1O <= 0; nlllii <= 0; end else if (rcvd_clk != nliOi_clk_prev && rcvd_clk == 1'b1) begin nli0lO <= wire_nllliO_dataout; nlii0O <= wire_nli0Oi_dataout; nliOl <= wire_niO0i_dataout; nll0il <= wire_nlllli_dataout; nll0iO <= wire_nlllll_dataout; nll0li <= wire_nllllO_dataout; nll0ll <= wire_nlllOi_dataout; nll0lO <= wire_nlllOl_dataout; nll0Oi <= wire_nlllOO_dataout; nll0Ol <= wire_nllO1i_dataout; nll0OO <= wire_nllO1l_dataout; nlli0i <= wire_nllO0O_dataout; nlli0l <= wire_nllOii_dataout; nlli0O <= wire_nllOil_dataout; nlli1i <= wire_nllO1O_dataout; nlli1l <= wire_nllO0i_dataout; nlli1O <= wire_nllO0l_dataout; nlliii <= wire_nllOiO_dataout; nlliil <= wire_nllOli_dataout; nlliiO <= wire_nllOll_dataout; nllili <= wire_nllOlO_dataout; nllill <= wire_nllOOi_dataout; nllilO <= wire_nllOOl_dataout; nlliOi <= wire_nllOOO_dataout; nlliOl <= wire_nlO11i_dataout; nlliOO <= wire_nlO11l_dataout; nlll0i <= wire_nlO10O_dataout; nlll0l <= wire_nlO1ii_dataout; nlll0O <= wire_nlO1il_dataout; nlll1i <= wire_nlO11O_dataout; nlll1l <= wire_nlO10i_dataout; nlll1O <= wire_nlO10l_dataout; nlllii <= wire_nlO1iO_dataout; end nliOi_clk_prev <= rcvd_clk; end assign wire_nliOi_CLRN = (niO11i38 ^ niO11i37); event nli0lO_event; event nlii0O_event; event nliOl_event; event nll0il_event; event nll0iO_event; event nll0li_event; event nll0ll_event; event nll0lO_event; event nll0Oi_event; event nll0Ol_event; event nll0OO_event; event nlli0i_event; event nlli0l_event; event nlli0O_event; event nlli1i_event; event nlli1l_event; event nlli1O_event; event nlliii_event; event nlliil_event; event nlliiO_event; event nllili_event; event nllill_event; event nllilO_event; event nlliOi_event; event nlliOl_event; event nlliOO_event; event nlll0i_event; event nlll0l_event; event nlll0O_event; event nlll1i_event; event nlll1l_event; event nlll1O_event; event nlllii_event; initial #1 ->nli0lO_event; initial #1 ->nlii0O_event; initial #1 ->nliOl_event; initial #1 ->nll0il_event; initial #1 ->nll0iO_event; initial #1 ->nll0li_event; initial #1 ->nll0ll_event; initial #1 ->nll0lO_event; initial #1 ->nll0Oi_event; initial #1 ->nll0Ol_event; initial #1 ->nll0OO_event; initial #1 ->nlli0i_event; initial #1 ->nlli0l_event; initial #1 ->nlli0O_event; initial #1 ->nlli1i_event; initial #1 ->nlli1l_event; initial #1 ->nlli1O_event; initial #1 ->nlliii_event; initial #1 ->nlliil_event; initial #1 ->nlliiO_event; initial #1 ->nllili_event; initial #1 ->nllill_event; initial #1 ->nllilO_event; initial #1 ->nlliOi_event; initial #1 ->nlliOl_event; initial #1 ->nlliOO_event; initial #1 ->nlll0i_event; initial #1 ->nlll0l_event; initial #1 ->nlll0O_event; initial #1 ->nlll1i_event; initial #1 ->nlll1l_event; initial #1 ->nlll1O_event; initial #1 ->nlllii_event; always @(nli0lO_event) nli0lO <= 1; always @(nlii0O_event) nlii0O <= 1; always @(nliOl_event) nliOl <= 1; always @(nll0il_event) nll0il <= 1; always @(nll0iO_event) nll0iO <= 1; always @(nll0li_event) nll0li <= 1; always @(nll0ll_event) nll0ll <= 1; always @(nll0lO_event) nll0lO <= 1; always @(nll0Oi_event) nll0Oi <= 1; always @(nll0Ol_event) nll0Ol <= 1; always @(nll0OO_event) nll0OO <= 1; always @(nlli0i_event) nlli0i <= 1; always @(nlli0l_event) nlli0l <= 1; always @(nlli0O_event) nlli0O <= 1; always @(nlli1i_event) nlli1i <= 1; always @(nlli1l_event) nlli1l <= 1; always @(nlli1O_event) nlli1O <= 1; always @(nlliii_event) nlliii <= 1; always @(nlliil_event) nlliil <= 1; always @(nlliiO_event) nlliiO <= 1; always @(nllili_event) nllili <= 1; always @(nllill_event) nllill <= 1; always @(nllilO_event) nllilO <= 1; always @(nlliOi_event) nlliOi <= 1; always @(nlliOl_event) nlliOl <= 1; always @(nlliOO_event) nlliOO <= 1; always @(nlll0i_event) nlll0i <= 1; always @(nlll0l_event) nlll0l <= 1; always @(nlll0O_event) nlll0O <= 1; always @(nlll1i_event) nlll1i <= 1; always @(nlll1l_event) nlll1l <= 1; always @(nlll1O_event) nlll1O <= 1; always @(nlllii_event) nlllii <= 1; initial begin nli00O = 0; nli0ii = 0; nli0il = 0; nli0iO = 0; nli0li = 0; nli0ll = 0; nliiO = 0; nlili = 0; nlill = 0; nlilO = 0; nliOO = 0; nll0i = 0; nll1i = 0; nll1l = 0; nlllil = 0; end always @ ( posedge rcvd_clk or posedge wire_nll0O_dataout) begin if (wire_nll0O_dataout == 1'b1) begin nli00O <= 0; nli0ii <= 0; nli0il <= 0; nli0iO <= 0; nli0li <= 0; nli0ll <= 0; nliiO <= 0; nlili <= 0; nlill <= 0; nlilO <= 0; nliOO <= 0; nll0i <= 0; nll1i <= 0; nll1l <= 0; nlllil <= 0; end else begin nli00O <= wire_nli0Ol_dataout; nli0ii <= nli0il; nli0il <= nli0iO; nli0iO <= wire_nli0OO_dataout; nli0li <= wire_nlii1l_dataout; nli0ll <= wire_nlii1i_dataout; nliiO <= wire_nilOO_dataout; nlili <= wire_niO1i_dataout; nlill <= wire_niO1l_dataout; nlilO <= wire_niO1O_dataout; nliOO <= niO11l; nll0i <= rprbs_en_rx; nll1i <= niO11O; nll1l <= nll0i; nlllil <= wire_nilOl_dataout; end end initial begin nll0l = 0; nllil = 0; end always @ (rcvd_clk or wire_nllii_PRN or wire_nllii_CLRN) begin if (wire_nllii_PRN == 1'b0) begin nll0l <= 1; nllil <= 1; end else if (wire_nllii_CLRN == 1'b0) begin nll0l <= 0; nllil <= 0; end else if (rcvd_clk != nllii_clk_prev && rcvd_clk == 1'b1) begin nll0l <= nllil; nllil <= niO10O; end nllii_clk_prev <= rcvd_clk; end assign wire_nllii_CLRN = (niO10l34 ^ niO10l33), wire_nllii_PRN = ((niO10i36 ^ niO10i35) & (~ soft_reset)); event nll0l_event; event nllil_event; initial #1 ->nll0l_event; initial #1 ->nllil_event; always @(nll0l_event) nll0l <= 1; always @(nllil_event) nllil <= 1; and(wire_n00i_dataout, nlll0i, niO1iO); and(wire_n00l_dataout, nlll1O, niO1iO); and(wire_n00O_dataout, nlll1l, niO1iO); and(wire_n01i_dataout, nlllii, niO1iO); and(wire_n01l_dataout, nlll0O, niO1iO); and(wire_n01O_dataout, nlll0l, niO1iO); and(wire_n0i0l_dataout, wire_n0iOi_dataout, ~(wire_n0li_dataout)); or(wire_n0i0O_dataout, wire_n0iOl_dataout, wire_n0li_dataout); and(wire_n0ii_dataout, nlll1i, niO1iO); and(wire_n0iii_dataout, wire_n0iOO_dataout, ~(wire_n0li_dataout)); or(wire_n0iil_dataout, wire_n0l1i_dataout, wire_n0li_dataout); or(wire_n0iiO_dataout, wire_n0l1l_dataout, wire_n0li_dataout); and(wire_n0il_dataout, nlliOO, niO1iO); and(wire_n0ili_dataout, wire_n0l1O_dataout, ~(wire_n0li_dataout)); or(wire_n0ill_dataout, wire_n0l0i_dataout, wire_n0li_dataout); and(wire_n0ilO_dataout, wire_n0l0l_dataout, ~(wire_n0li_dataout)); and(wire_n0iO_dataout, wire_n0ll_o, niO0Ol); assign wire_n0iOi_dataout = (wire_n0iO_dataout === 1'b1) ? rcid_pattern : nll0OO; assign wire_n0iOl_dataout = (wire_n0iO_dataout === 1'b1) ? rcid_pattern : nlli1i; assign wire_n0iOO_dataout = (wire_n0iO_dataout === 1'b1) ? rcid_pattern : nlli1l; assign wire_n0l0i_dataout = (wire_n0iO_dataout === 1'b1) ? rcid_pattern : nlli0O; assign wire_n0l0l_dataout = (wire_n0iO_dataout === 1'b1) ? rcid_pattern : nlliii; assign wire_n0l0O_dataout = (niliil === 1'b1) ? nll0OO : ((nili0O ^ nlli1i) ^ nll0OO); assign wire_n0l1i_dataout = (wire_n0iO_dataout === 1'b1) ? rcid_pattern : nlli1O; assign wire_n0l1l_dataout = (wire_n0iO_dataout === 1'b1) ? rcid_pattern : nlli0i; assign wire_n0l1O_dataout = (wire_n0iO_dataout === 1'b1) ? rcid_pattern : nlli0l; and(wire_n0li_dataout, niOO, niO0Ol); assign wire_n0lii_dataout = (niliil === 1'b1) ? nlli1i : ((niliii ^ nlli1l) ^ nlli1i); assign wire_n0lil_dataout = (niliil === 1'b1) ? nlli1l : (((((niliii ^ nlli0l) ^ nlli1O) ^ nlli1l) ^ nlli1i) ^ nll0OO); assign wire_n0liO_dataout = (niliil === 1'b1) ? nlli1O : (((((nlliii ^ nlli0l) ^ nlli0i) ^ nlli1O) ^ nlli1l) ^ nll0OO); assign wire_n0lli_dataout = (niliil === 1'b1) ? nlli0i : (nili0i ^ nll0OO); assign wire_n0lll_dataout = (niliil === 1'b1) ? nlli0l : (nili0l ^ nlli1i); assign wire_n0llO_dataout = (niliil === 1'b1) ? nlli0O : (nili0O ^ nlli1l); assign wire_n0lOi_dataout = (niliil === 1'b1) ? nlliii : (niliii ^ nlli1O); or(wire_n0lOl_dataout, nlliil, ~(niliil)); or(wire_n0lOO_dataout, nlliiO, ~(niliil)); or(wire_n0O0i_dataout, nlliOi, ~(niliil)); or(wire_n0O0l_dataout, nlliOl, ~(niliil)); or(wire_n0O0O_dataout, nlliOO, ~(niliil)); or(wire_n0O1i_dataout, nllili, ~(niliil)); or(wire_n0O1l_dataout, nllill, ~(niliil)); or(wire_n0O1O_dataout, nllilO, ~(niliil)); or(wire_n0Oii_dataout, nlll1i, ~(niliil)); or(wire_n0Oil_dataout, nlll1l, ~(niliil)); or(wire_n0OiO_dataout, nlll1O, ~(niliil)); or(wire_n0Oli_dataout, nlll0i, ~(niliil)); or(wire_n0Oll_dataout, nlll0l, ~(niliil)); or(wire_n0OlO_dataout, nlll0O, ~(niliil)); or(wire_n0OO_dataout, niO01i, niO0ii); or(wire_n0OOi_dataout, nlllii, ~(niliil)); assign wire_n10i_dataout = (niO1il === 1'b1) ? nlll1O : wire_n00l_dataout; assign wire_n10l_dataout = (niO1il === 1'b1) ? nlll1l : wire_n00O_dataout; assign wire_n10O_dataout = (niO1il === 1'b1) ? nlll1i : wire_n0ii_dataout; assign wire_n110i_dataout = (wire_nil0O_o[0] === 1'b1) ? wire_n0ilO_dataout : nll0Ol; assign wire_n111i_dataout = (wire_nil0O_o[0] === 1'b1) ? wire_n0iiO_dataout : nll0ll; assign wire_n111l_dataout = (wire_nil0O_o[0] === 1'b1) ? wire_n0ili_dataout : nll0lO; assign wire_n111O_dataout = (wire_nil0O_o[0] === 1'b1) ? wire_n0ill_dataout : nll0Oi; assign wire_n11i_dataout = (niO1il === 1'b1) ? nlll0O : wire_n01l_dataout; assign wire_n11l_dataout = (niO1il === 1'b1) ? nlll0l : wire_n01O_dataout; assign wire_n11O_dataout = (niO1il === 1'b1) ? nlll0i : wire_n00i_dataout; assign wire_n1i_dataout = (wire_n0iO_dataout === 1'b1) ? wire_n1O_o[7] : rcid_len[6]; assign wire_n1ii_dataout = (niO1il === 1'b1) ? nlliOO : wire_n0il_dataout; and(wire_n1il_dataout, nlliOl, niO1il); and(wire_n1iO_dataout, nlliOi, niO1il); assign wire_n1l_dataout = (wire_n0iO_dataout === 1'b1) ? wire_n1O_o[8] : rcid_len[7]; and(wire_n1li_dataout, nllilO, niO1il); and(wire_n1ll_dataout, nllill, niO1il); and(wire_n1lO_dataout, nllili, niO1il); and(wire_n1Oi_dataout, nlliiO, niO1il); and(wire_n1Ol_dataout, nlliil, niO1il); and(wire_n1OO_dataout, nlliii, niO1il); and(wire_ni0i_dataout, niO1OO, ~(niO01i)); or(wire_ni0il_dataout, nli0lO, ~(nilill)); or(wire_ni0li_dataout, nll0iO, ~(nilill)); or(wire_ni0ll_dataout, nll0li, ~(nilill)); or(wire_ni0Ol_dataout, nll0lO, ~(nilill)); or(wire_ni0OO_dataout, nll0Oi, ~(nilill)); and(wire_ni1i_dataout, wire_ni1O_dataout, ~(niO0ii)); and(wire_ni1l_dataout, wire_ni0i_dataout, ~(niO0ii)); or(wire_ni1O_dataout, (~ niO1OO), niO01i); or(wire_nii1i_dataout, nll0Ol, ~(nilill)); assign wire_nilii_dataout = (rall_one_dect_only === 1'b1) ? wire_nilOi_dataout : wire_nillO_dataout; assign wire_nilil_dataout = (niO1ii === 1'b1) ? (nll1i & nill0i) : wire_niliO_dataout; and(wire_niliO_dataout, (nliOO & nill0l), niO1il); assign wire_nillO_dataout = (niO0Ol === 1'b1) ? nlllil : wire_niO0O_dataout; assign wire_nilOi_dataout = (niO0Ol === 1'b1) ? wire_nli1i_dataout : wire_niO0l_dataout; assign wire_nilOl_dataout = (niO0Ol === 1'b1) ? wire_nli1l_dataout : wire_niOii_dataout; assign wire_nilOO_dataout = (niO0Ol === 1'b1) ? wire_nli1O_dataout : wire_niOil_dataout; assign wire_niO0i_dataout = (niO0Ol === 1'b1) ? wire_nli0O_o : wire_niOlO_dataout; and(wire_niO0l_dataout, wire_niOOl_dataout, ~(nill0O)); assign wire_niO0O_dataout = (nill0O === 1'b1) ? nlllil : wire_niOOi_dataout; assign wire_niO1i_dataout = (niO0Ol === 1'b1) ? wire_nli0i_dataout : wire_niOiO_dataout; assign wire_niO1l_dataout = (niO0Ol === 1'b1) ? wire_nli1i_dataout : wire_niOli_dataout; assign wire_niO1O_dataout = (niO0Ol === 1'b1) ? wire_nli0l_dataout : wire_niOll_dataout; assign wire_niOii_dataout = (nill0O === 1'b1) ? wire_nl0li_dataout : wire_niOOO_dataout; assign wire_niOil_dataout = (nill0O === 1'b1) ? wire_nl0ll_dataout : wire_nl11i_dataout; assign wire_niOiO_dataout = (nill0O === 1'b1) ? wire_nl0lO_dataout : wire_nl11l_dataout; assign wire_niOli_dataout = (nill0O === 1'b1) ? wire_nl0Oi_dataout : wire_nl11O_dataout; assign wire_niOll_dataout = (nill0O === 1'b1) ? wire_nl0Ol_dataout : wire_nl10i_dataout; assign wire_niOlO_dataout = (nill0O === 1'b1) ? wire_nl0OO_o : wire_nl10l_dataout; assign wire_niOOi_dataout = (niO1iO === 1'b1) ? nlllil : wire_nl10O_dataout; assign wire_niOOl_dataout = (niO1iO === 1'b1) ? wire_nl00l_dataout : wire_nl1ii_dataout; assign wire_niOOO_dataout = (niO1iO === 1'b1) ? wire_nl00O_dataout : wire_nl1il_dataout; and(wire_nl00l_dataout, nilO1l, nlill); and(wire_nl00O_dataout, nilOOO, nliiO); and(wire_nl01i_dataout, nillll, nlili); and(wire_nl01l_dataout, nillli, nlill); and(wire_nl01O_dataout, nilliO, nlilO); and(wire_nl0ii_dataout, nilOOO, nlili); and(wire_nl0il_dataout, nilOOl, nliOl); and(wire_nl0li_dataout, nilOil, nliiO); and(wire_nl0ll_dataout, nilOii, nlili); and(wire_nl0lO_dataout, nilO0O, nlill); and(wire_nl0Oi_dataout, nilO0l, nlilO); and(wire_nl0Ol_dataout, nilO0i, nliOl); assign wire_nl10i_dataout = (niO1iO === 1'b1) ? wire_nl0il_dataout : wire_nl1lO_dataout; assign wire_nl10l_dataout = (niO1iO === 1'b1) ? wire_nl0iO_o : wire_nl1Oi_dataout; and(wire_nl10O_dataout, nlllil, nillii); assign wire_nl11i_dataout = (niO1iO === 1'b1) ? wire_nl0ii_dataout : wire_nl1iO_dataout; assign wire_nl11l_dataout = (niO1iO === 1'b1) ? wire_nl00l_dataout : wire_nl1li_dataout; assign wire_nl11O_dataout = (niO1iO === 1'b1) ? wire_nli1i_dataout : wire_nl1ll_dataout; and(wire_nl1ii_dataout, wire_nl1Ol_dataout, nillii); assign wire_nl1il_dataout = (nillii === 1'b1) ? wire_nl1OO_dataout : nlllil; assign wire_nl1iO_dataout = (nillii === 1'b1) ? wire_nl01i_dataout : nliiO; assign wire_nl1li_dataout = (nillii === 1'b1) ? wire_nl01l_dataout : nlili; assign wire_nl1ll_dataout = (nillii === 1'b1) ? wire_nl01O_dataout : nlill; assign wire_nl1lO_dataout = (nillii === 1'b1) ? wire_nl1Ol_dataout : nlilO; assign wire_nl1Oi_dataout = (nillii === 1'b1) ? wire_nl00i_o : nliOl; and(wire_nl1Ol_dataout, nillil, nliOl); and(wire_nl1OO_dataout, nilllO, nliiO); and(wire_nli0i_dataout, nilOll, nlill); and(wire_nli0l_dataout, nilOli, nliOl); or(wire_nli0Oi_dataout, wire_nlii1O_dataout, (~ nll1l)); and(wire_nli0Ol_dataout, wire_nlii0l_dataout, ~((~ nll1l))); and(wire_nli0OO_dataout, wire_nliiii_dataout, ~((~ nll1l))); and(wire_nli1i_dataout, nilOOl, nlilO); and(wire_nli1l_dataout, nilOOi, nliiO); and(wire_nli1O_dataout, nilOlO, nlili); assign wire_nlii0i_dataout = (rprbs_clr_rslt_rx === 1'b1) ? nli0li : wire_nliiOi_o; and(wire_nlii0l_dataout, wire_nliill_o, ~(rprbs_clr_rslt_rx)); and(wire_nlii1i_dataout, wire_nliiil_dataout, ~((~ nll1l))); and(wire_nlii1l_dataout, wire_nlii0i_dataout, ~((~ nll1l))); assign wire_nlii1O_dataout = (rprbs_clr_rslt_rx === 1'b1) ? nlii0O : wire_nliiiO_o; and(wire_nliiii_dataout, wire_nliilO_o, ~(rprbs_clr_rslt_rx)); and(wire_nliiil_dataout, wire_nliili_o, ~(rprbs_clr_rslt_rx)); assign wire_nliil_dataout = (rcid_pattern === 1'b1) ? nilOOl : nilOOO; assign wire_nliOil_dataout = (rall_one_dect_only === 1'b1) ? ((nli0li & niiO0l) | nli0ll) : ((nli0li & niiO0O) | nli0ll); and(wire_nll01i_dataout, ((nli0li & nil11l) | nli0ll), ~(nil11i)); and(wire_nll0O_dataout, nll0l, ~(scan_mode)); assign wire_nll1li_dataout = (rall_one_dect_only === 1'b1) ? wire_nll1OO_dataout : wire_nll1ll_dataout; and(wire_nll1ll_dataout, ((nli0li & niiOOl) | nli0ll), ~(nil11i)); assign wire_nll1OO_dataout = (nlO === 1'b1) ? wire_nll01i_dataout : ((nli0li & niiOOO) | nli0ll); assign wire_nlli_dataout = (wire_n0iO_dataout === 1'b1) ? wire_n1O_o[1] : rcid_len[0]; assign wire_nlll_dataout = (wire_n0iO_dataout === 1'b1) ? wire_n1O_o[2] : rcid_len[1]; assign wire_nllli_dataout = (niO1ii === 1'b1) ? nlllii : wire_nlOOO_dataout; or(wire_nllliO_dataout, wire_nlO1li_dataout, (~ nll1l)); assign wire_nllll_dataout = (niO1ii === 1'b1) ? nlll0O : wire_n11i_dataout; or(wire_nlllli_dataout, wire_nlO1ll_dataout, (~ nll1l)); or(wire_nlllll_dataout, wire_nlO1lO_dataout, (~ nll1l)); or(wire_nllllO_dataout, wire_nlO1Oi_dataout, (~ nll1l)); assign wire_nlllO_dataout = (niO1ii === 1'b1) ? nlll0l : wire_n11l_dataout; or(wire_nlllOi_dataout, wire_nlO1Ol_dataout, (~ nll1l)); or(wire_nlllOl_dataout, wire_nlO1OO_dataout, (~ nll1l)); or(wire_nlllOO_dataout, wire_nlO01i_dataout, (~ nll1l)); assign wire_nllO_dataout = (wire_n0iO_dataout === 1'b1) ? wire_n1O_o[3] : rcid_len[2]; or(wire_nllO0i_dataout, wire_nlO00l_dataout, (~ nll1l)); or(wire_nllO0l_dataout, wire_nlO00O_dataout, (~ nll1l)); or(wire_nllO0O_dataout, wire_nlO0ii_dataout, (~ nll1l)); or(wire_nllO1i_dataout, wire_nlO01l_dataout, (~ nll1l)); or(wire_nllO1l_dataout, wire_nlO01O_dataout, (~ nll1l)); or(wire_nllO1O_dataout, wire_nlO00i_dataout, (~ nll1l)); assign wire_nllOi_dataout = (niO1ii === 1'b1) ? nlll0i : wire_n11O_dataout; or(wire_nllOii_dataout, wire_nlO0il_dataout, (~ nll1l)); or(wire_nllOil_dataout, wire_nlO0iO_dataout, (~ nll1l)); or(wire_nllOiO_dataout, wire_nlO0li_dataout, (~ nll1l)); assign wire_nllOl_dataout = (niO1ii === 1'b1) ? nlll1O : wire_n10i_dataout; or(wire_nllOli_dataout, wire_nlO0ll_dataout, (~ nll1l)); or(wire_nllOll_dataout, wire_nlO0lO_dataout, (~ nll1l)); or(wire_nllOlO_dataout, wire_nlO0Oi_dataout, (~ nll1l)); assign wire_nllOO_dataout = (niO1ii === 1'b1) ? nlll1l : wire_n10l_dataout; or(wire_nllOOi_dataout, wire_nlO0Ol_dataout, (~ nll1l)); or(wire_nllOOl_dataout, wire_nlO0OO_dataout, (~ nll1l)); or(wire_nllOOO_dataout, wire_nlOi1i_dataout, (~ nll1l)); assign wire_nlO00i_dataout = ((~ nli0li) === 1'b1) ? wire_nii0i_o : wire_nlOl0l_dataout; assign wire_nlO00l_dataout = ((~ nli0li) === 1'b1) ? wire_nii0l_o : wire_nlOl0O_dataout; assign wire_nlO00O_dataout = ((~ nli0li) === 1'b1) ? wire_nii0O_o : wire_nlOlii_dataout; assign wire_nlO01i_dataout = ((~ nli0li) === 1'b1) ? wire_ni0OO_dataout : wire_nlOl1l_dataout; assign wire_nlO01l_dataout = ((~ nli0li) === 1'b1) ? wire_nii1i_dataout : wire_nlOl1O_dataout; assign wire_nlO01O_dataout = ((~ nli0li) === 1'b1) ? wire_nii1O_o : wire_nlOl0i_dataout; assign wire_nlO0i_dataout = (niO1ii === 1'b1) ? nlliOi : wire_n1iO_dataout; assign wire_nlO0ii_dataout = ((~ nli0li) === 1'b1) ? wire_niiii_o : wire_nlOlil_dataout; assign wire_nlO0il_dataout = ((~ nli0li) === 1'b1) ? (~ (((wire_nil0O_o[25] | wire_nil0O_o[17]) | wire_nil0O_o[16]) | wire_nil0O_o[8])) : wire_nlOliO_dataout; assign wire_nlO0iO_dataout = ((~ nli0li) === 1'b1) ? wire_niiiO_o : wire_nlOlli_dataout; assign wire_nlO0l_dataout = (niO1ii === 1'b1) ? nllilO : wire_n1li_dataout; assign wire_nlO0li_dataout = ((~ nli0li) === 1'b1) ? (~ ((wire_nil0O_o[25] | wire_nil0O_o[17]) | wire_nil0O_o[16])) : wire_nlOlll_dataout; assign wire_nlO0ll_dataout = ((~ nli0li) === 1'b1) ? wire_niill_o : wire_nlOllO_dataout; assign wire_nlO0lO_dataout = ((~ nli0li) === 1'b1) ? wire_niilO_o : wire_nlOlOi_dataout; assign wire_nlO0O_dataout = (niO1ii === 1'b1) ? nllill : wire_n1ll_dataout; assign wire_nlO0Oi_dataout = ((~ nli0li) === 1'b1) ? (~ (((wire_nil0O_o[25] | wire_nil0O_o[8]) | wire_nil0O_o[2]) | wire_nil0O_o[0])) : wire_nlOlOl_dataout; assign wire_nlO0Ol_dataout = ((~ nli0li) === 1'b1) ? (~ nililO) : wire_nlOlOO_dataout; assign wire_nlO0OO_dataout = ((~ nli0li) === 1'b1) ? (~ niliOi) : wire_nlOO1i_dataout; or(wire_nlO10i_dataout, wire_nlOi0l_dataout, (~ nll1l)); or(wire_nlO10l_dataout, wire_nlOi0O_dataout, (~ nll1l)); or(wire_nlO10O_dataout, wire_nlOiii_dataout, (~ nll1l)); or(wire_nlO11i_dataout, wire_nlOi1l_dataout, (~ nll1l)); or(wire_nlO11l_dataout, wire_nlOi1O_dataout, (~ nll1l)); or(wire_nlO11O_dataout, wire_nlOi0i_dataout, (~ nll1l)); assign wire_nlO1i_dataout = (niO1ii === 1'b1) ? nlll1i : wire_n10O_dataout; or(wire_nlO1ii_dataout, wire_nlOiil_dataout, (~ nll1l)); or(wire_nlO1il_dataout, wire_nlOiiO_dataout, (~ nll1l)); or(wire_nlO1iO_dataout, wire_nlOili_dataout, (~ nll1l)); assign wire_nlO1l_dataout = (niO1ii === 1'b1) ? nlliOO : wire_n1ii_dataout; assign wire_nlO1li_dataout = ((~ nli0li) === 1'b1) ? wire_ni0il_dataout : wire_nlOill_dataout; assign wire_nlO1ll_dataout = ((~ nli0li) === 1'b1) ? wire_ni0iO_o : wire_nlOilO_dataout; assign wire_nlO1lO_dataout = ((~ nli0li) === 1'b1) ? wire_ni0li_dataout : wire_nlOiOi_dataout; assign wire_nlO1O_dataout = (niO1ii === 1'b1) ? nlliOl : wire_n1il_dataout; assign wire_nlO1Oi_dataout = ((~ nli0li) === 1'b1) ? wire_ni0ll_dataout : wire_nlOiOl_dataout; assign wire_nlO1Ol_dataout = ((~ nli0li) === 1'b1) ? wire_ni0lO_o : wire_nlOiOO_dataout; assign wire_nlO1OO_dataout = ((~ nli0li) === 1'b1) ? wire_ni0Ol_dataout : wire_nlOl1i_dataout; assign wire_nlOi_dataout = (wire_n0iO_dataout === 1'b1) ? wire_n1O_o[4] : rcid_len[3]; assign wire_nlOi0i_dataout = ((~ nli0li) === 1'b1) ? (~ niliOO) : wire_nlOO0l_dataout; assign wire_nlOi0l_dataout = ((~ nli0li) === 1'b1) ? (~ nill1i) : wire_nlOO0O_dataout; assign wire_nlOi0O_dataout = ((~ nli0li) === 1'b1) ? (~ nill1l) : wire_nlOOii_dataout; assign wire_nlOi1i_dataout = ((~ nli0li) === 1'b1) ? (~ niliOi) : wire_nlOO1l_dataout; assign wire_nlOi1l_dataout = ((~ nli0li) === 1'b1) ? (~ niliOl) : wire_nlOO1O_dataout; assign wire_nlOi1O_dataout = ((~ nli0li) === 1'b1) ? (~ nill1O) : wire_nlOO0i_dataout; assign wire_nlOii_dataout = (niO1ii === 1'b1) ? nllili : wire_n1lO_dataout; assign wire_nlOiii_dataout = ((~ nli0li) === 1'b1) ? (~ nill1l) : wire_nlOOil_dataout; assign wire_nlOiil_dataout = ((~ nli0li) === 1'b1) ? (~ nill1l) : wire_nlOOiO_dataout; assign wire_nlOiiO_dataout = ((~ nli0li) === 1'b1) ? (~ nill1l) : wire_nlOOli_dataout; assign wire_nlOil_dataout = (niO1ii === 1'b1) ? nlliiO : wire_n1Oi_dataout; assign wire_nlOili_dataout = ((~ nli0li) === 1'b1) ? (~ nill1O) : wire_nlOOll_dataout; assign wire_nlOill_dataout = (niliiO === 1'b1) ? wire_nlOOlO_dataout : nli0lO; assign wire_nlOilO_dataout = (niliiO === 1'b1) ? wire_nlOOOi_dataout : nll0il; assign wire_nlOiO_dataout = (niO1ii === 1'b1) ? nlliil : wire_n1Ol_dataout; assign wire_nlOiOi_dataout = (niliiO === 1'b1) ? wire_nlOOOl_dataout : nll0iO; assign wire_nlOiOl_dataout = (niliiO === 1'b1) ? wire_nlOOOO_dataout : nll0li; assign wire_nlOiOO_dataout = (niliiO === 1'b1) ? wire_n111i_dataout : nll0ll; assign wire_nlOl_dataout = (wire_n0iO_dataout === 1'b1) ? wire_n1O_o[5] : rcid_len[4]; assign wire_nlOl0i_dataout = (niliiO === 1'b1) ? wire_n110l_o : nll0OO; assign wire_nlOl0l_dataout = (niliiO === 1'b1) ? wire_n110O_o : nlli1i; assign wire_nlOl0O_dataout = (niliiO === 1'b1) ? wire_n11ii_o : nlli1l; assign wire_nlOl1i_dataout = (niliiO === 1'b1) ? wire_n111l_dataout : nll0lO; assign wire_nlOl1l_dataout = (niliiO === 1'b1) ? wire_n111O_dataout : nll0Oi; assign wire_nlOl1O_dataout = (niliiO === 1'b1) ? wire_n110i_dataout : nll0Ol; assign wire_nlOli_dataout = (niO1ii === 1'b1) ? nlliii : wire_n1OO_dataout; assign wire_nlOlii_dataout = (niliiO === 1'b1) ? wire_n11il_o : nlli1O; assign wire_nlOlil_dataout = (niliiO === 1'b1) ? wire_n11iO_o : nlli0i; assign wire_nlOliO_dataout = (niliiO === 1'b1) ? wire_n11li_o : nlli0l; and(wire_nlOll_dataout, nlli0O, niO1ii); assign wire_nlOlli_dataout = (niliiO === 1'b1) ? wire_n11ll_o : nlli0O; assign wire_nlOlll_dataout = (niliiO === 1'b1) ? wire_n11lO_o : nlliii; assign wire_nlOllO_dataout = (niliiO === 1'b1) ? wire_n11Oi_o : nlliil; and(wire_nlOlO_dataout, nlli0l, niO1ii); assign wire_nlOlOi_dataout = (niliiO === 1'b1) ? wire_n11Ol_o : nlliiO; assign wire_nlOlOl_dataout = (niliiO === 1'b1) ? wire_n11OO_o : nllili; assign wire_nlOlOO_dataout = (niliiO === 1'b1) ? wire_n101i_o : nllill; assign wire_nlOO_dataout = (wire_n0iO_dataout === 1'b1) ? wire_n1O_o[6] : rcid_len[5]; assign wire_nlOO0i_dataout = (niliiO === 1'b1) ? wire_n100l_o : nlliOO; assign wire_nlOO0l_dataout = (niliiO === 1'b1) ? wire_n100O_o : nlll1i; assign wire_nlOO0O_dataout = (niliiO === 1'b1) ? wire_n10ii_o : nlll1l; assign wire_nlOO1i_dataout = (niliiO === 1'b1) ? wire_n101l_o : nllilO; assign wire_nlOO1l_dataout = (niliiO === 1'b1) ? wire_n101O_o : nlliOi; assign wire_nlOO1O_dataout = (niliiO === 1'b1) ? wire_n100i_o : nlliOl; and(wire_nlOOi_dataout, nlli0i, niO1ii); assign wire_nlOOii_dataout = (niliiO === 1'b1) ? wire_n10il_o : nlll1O; assign wire_nlOOil_dataout = (niliiO === 1'b1) ? wire_n10iO_o : nlll0i; assign wire_nlOOiO_dataout = (niliiO === 1'b1) ? wire_n10li_o : nlll0l; and(wire_nlOOl_dataout, nlli1O, niO1ii); assign wire_nlOOli_dataout = (niliiO === 1'b1) ? wire_n10ll_o : nlll0O; assign wire_nlOOll_dataout = (niliiO === 1'b1) ? wire_n10lO_o : nlllii; assign wire_nlOOlO_dataout = (wire_nil0O_o[0] === 1'b1) ? wire_n0i0l_dataout : nli0lO; assign wire_nlOOO_dataout = (niO1il === 1'b1) ? nlllii : wire_n01i_dataout; assign wire_nlOOOi_dataout = (wire_nil0O_o[0] === 1'b1) ? wire_n0i0O_dataout : nll0il; assign wire_nlOOOl_dataout = (wire_nil0O_o[0] === 1'b1) ? wire_n0iii_dataout : nll0iO; assign wire_nlOOOO_dataout = (wire_nil0O_o[0] === 1'b1) ? wire_n0iil_dataout : nll0li; oper_add n1O ( .a({((niO0OO12 ^ niO0OO11) & nlil), nlii, ((niOi1i10 ^ niOi1i9) & nl0O), ((niOi1l8 ^ niOi1l7) & nl0l), nl0i, nl1O, ((niOi1O6 ^ niOi1O5) & nl1l), nl1i, 1'b1}), .b({{7{1'b1}}, 1'b0, 1'b1}), .cin(1'b0), .cout(), .o(wire_n1O_o)); defparam n1O.sgate_representation = 0, n1O.width_a = 9, n1O.width_b = 9, n1O.width_o = 9; oper_decoder nil0O ( .i({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]}), .o(wire_nil0O_o)); defparam nil0O.width_i = 5, nil0O.width_o = 32; oper_less_than nill ( .a({{7{1'b0}}, 1'b1}), .b({nlil, nlii, ((niO0ll18 ^ niO0ll17) & nl0O), nl0l, nl0i, nl1O, ((niO0lO16 ^ niO0lO15) & nl1l), nl1i}), .cin(1'b0), .o(wire_nill_o)); defparam nill.sgate_representation = 0, nill.width_a = 8, nill.width_b = 8; oper_mux n100i ( .data({{6{1'b0}}, nil1OO, ((nil00O ^ nlliOl) ^ nlliOi), {6{1'b0}}, nil00i, ((nil0Ol ^ nllili) ^ nlliiO), {7{1'b0}}, 1'b1, {3{1'b0}}, nlli0O, {3{1'b0}}, wire_n0O0l_dataout}), .o(wire_n100i_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam n100i.width_data = 32, n100i.width_sel = 5; oper_mux n100l ( .data({{6{1'b0}}, nil01i, ((nil0ii ^ nlliOO) ^ nlliOl), {6{1'b0}}, nil00l, ((nil0OO ^ nllill) ^ nllili), {7{1'b0}}, 1'b1, {3{1'b0}}, nlliii, {3{1'b0}}, wire_n0O0O_dataout}), .o(wire_n100l_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam n100l.width_data = 32, n100l.width_sel = 5; oper_mux n100O ( .data({{6{1'b0}}, nil01l, ((nil0il ^ nlll1i) ^ nlliOO), {6{1'b0}}, nll0OO, 1'b1, {7{1'b0}}, 1'b1, {3{1'b0}}, nlliil, {3{1'b0}}, wire_n0Oii_dataout}), .o(wire_n100O_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam n100O.width_data = 32, n100O.width_sel = 5; oper_mux n101i ( .data({{6{1'b0}}, nil1lO, (nlll0i ^ nlll1l), {6{1'b0}}, nil01i, nil0Oi, {7{1'b0}}, 1'b1, {3{1'b0}}, nlli1O, {3{1'b0}}, wire_n0O1l_dataout}), .o(wire_n101i_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam n101i.width_data = 32, n101i.width_sel = 5; oper_mux n101l ( .data({{6{1'b0}}, nil1Oi, ((nlll1O ^ nlliOl) ^ nlliOi), {6{1'b0}}, nil01l, ((nlliOl ^ nllili) ^ nlliiO), {7{1'b0}}, 1'b1, {3{1'b0}}, nlli0i, {3{1'b0}}, wire_n0O1O_dataout}), .o(wire_n101l_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam n101l.width_data = 32, n101l.width_sel = 5; oper_mux n101O ( .data({{6{1'b0}}, nil1Ol, ((nlll0i ^ nlliOO) ^ nlliOl), {6{1'b0}}, nil01O, ((nlliOO ^ nllill) ^ nllili), {7{1'b0}}, 1'b1, {3{1'b0}}, nlli0l, {3{1'b0}}, wire_n0O0i_dataout}), .o(wire_n101O_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam n101O.width_data = 32, n101O.width_sel = 5; oper_mux n10ii ( .data({{6{1'b0}}, nil01O, (nil0iO ^ nlll1i), {6{1'b0}}, nlli1i, 1'b1, {7{1'b0}}, 1'b1, {3{1'b0}}, nlliiO, {3{1'b0}}, wire_n0Oil_dataout}), .o(wire_n10ii_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam n10ii.width_data = 32, n10ii.width_sel = 5; oper_mux n10il ( .data({{6{1'b0}}, nil00i, ((nil0iO ^ nlliOl) ^ nlliOi), {6{1'b0}}, nlli1l, 1'b1, {7{1'b0}}, 1'b1, {3{1'b0}}, nllili, {3{1'b0}}, wire_n0OiO_dataout}), .o(wire_n10il_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam n10il.width_data = 32, n10il.width_sel = 5; oper_mux n10iO ( .data({{6{1'b0}}, nil00l, ((nil0li ^ nlliOO) ^ nlliOi), {6{1'b0}}, nlli1O, 1'b1, {7{1'b0}}, 1'b1, {3{1'b0}}, nllill, {3{1'b0}}, wire_n0Oli_dataout}), .o(wire_n10iO_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam n10iO.width_data = 32, n10iO.width_sel = 5; oper_mux n10li ( .data({{6{1'b0}}, nll0OO, 1'b1, {6{1'b0}}, nlli0i, 1'b1, {7{1'b0}}, 1'b1, {3{1'b0}}, nllilO, {3{1'b0}}, wire_n0Oll_dataout}), .o(wire_n10li_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam n10li.width_data = 32, n10li.width_sel = 5; oper_mux n10ll ( .data({{6{1'b0}}, nlli1i, 1'b1, {6{1'b0}}, nlli0l, 1'b1, {7{1'b0}}, 1'b1, {3{1'b0}}, nlliOi, {3{1'b0}}, wire_n0OlO_dataout}), .o(wire_n10ll_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam n10ll.width_data = 32, n10ll.width_sel = 5; oper_mux n10lO ( .data({{6{1'b0}}, nlli1l, 1'b1, {6{1'b0}}, nlli0O, 1'b1, {7{1'b0}}, 1'b1, {3{1'b0}}, nlliOl, {3{1'b0}}, wire_n0OOi_dataout}), .o(wire_n10lO_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam n10lO.width_data = 32, n10lO.width_sel = 5; oper_mux n110l ( .data({{6{1'b0}}, ((nlll1i ^ nlli1O) ^ nlll0O), nil0ll, {6{1'b0}}, nil10l, (nllili ^ nlliiO), {7{1'b0}}, nili1O, {3{1'b0}}, nil1Oi, 1'b0, (nlli1l ^ nlli1i), 1'b0, wire_n0l0O_dataout}), .o(wire_n110l_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam n110l.width_data = 32, n110l.width_sel = 5; oper_mux n110O ( .data({{6{1'b0}}, ((nlll1l ^ nlli0i) ^ nlllii), nil0lO, {6{1'b0}}, nil10O, (nllill ^ nllili), {7{1'b0}}, nili1l, {3{1'b0}}, nil1Ol, 1'b0, (nlli1O ^ nlli1l), 1'b0, wire_n0lii_dataout}), .o(wire_n110O_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam n110O.width_data = 32, n110O.width_sel = 5; oper_mux n11ii ( .data({{6{1'b0}}, (nlli0l ^ nll0OO), nil00O, {6{1'b0}}, nil1ii, nil0Ol, {7{1'b0}}, nili1i, {3{1'b0}}, nil1OO, 1'b0, nili0i, 1'b0, wire_n0lil_dataout}), .o(wire_n11ii_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam n11ii.width_data = 32, n11ii.width_sel = 5; oper_mux n11il ( .data({{6{1'b0}}, (nlli0O ^ nlli1i), nil0ii, {6{1'b0}}, nil1il, nil0OO, {7{1'b0}}, (nlli0O ^ nlli1O), {3{1'b0}}, nil01i, 1'b0, nili0l, 1'b0, wire_n0liO_dataout}), .o(wire_n11il_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam n11il.width_data = 32, n11il.width_sel = 5; oper_mux n11iO ( .data({{6{1'b0}}, nil10l, nil0il, {6{1'b0}}, nil1iO, nil0ll, {7{1'b0}}, (nlliii ^ nlli0i), {3{1'b0}}, nil01l, 1'b0, nili0O, 1'b0, wire_n0lli_dataout}), .o(wire_n11iO_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam n11iO.width_data = 32, n11iO.width_sel = 5; oper_mux n11li ( .data({{6{1'b0}}, nil10O, nil0li, {6{1'b0}}, nil1li, nil0lO, {7{1'b0}}, (nlliil ^ nlli0l), {3{1'b0}}, nil01O, 1'b0, niliii, 1'b0, wire_n0lll_dataout}), .o(wire_n11li_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam n11li.width_data = 32, n11li.width_sel = 5; oper_mux n11ll ( .data({{6{1'b0}}, nil1ii, (nil01l ^ nlliOi), {6{1'b0}}, nil1ll, (nil1Oi ^ nlliiO), {7{1'b0}}, (nlliiO ^ nlli0O), {3{1'b0}}, nil00i, 1'b0, ((nlliii ^ nlli1i) ^ nlli1l), 1'b0, wire_n0llO_dataout}), .o(wire_n11ll_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam n11ll.width_data = 32, n11ll.width_sel = 5; oper_mux n11lO ( .data({{6{1'b0}}, nil1il, nil0Oi, {6{1'b0}}, nil1lO, (nllill ^ nlliiO), {7{1'b0}}, (nili1O ^ nlliii), {3{1'b0}}, nil00l, 1'b0, (nlli1O ^ nlli1i), 1'b0, wire_n0lOi_dataout}), .o(wire_n11lO_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam n11lO.width_data = 32, n11lO.width_sel = 5; oper_mux n11Oi ( .data({{6{1'b0}}, nil1iO, (nlll1i ^ nlliOl), {6{1'b0}}, nil1Oi, (nllilO ^ nllili), {7{1'b0}}, (nili1l ^ nlliil), {3{1'b0}}, nll0OO, {3{1'b0}}, wire_n0lOl_dataout}), .o(wire_n11Oi_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam n11Oi.width_data = 32, n11Oi.width_sel = 5; oper_mux n11Ol ( .data({{6{1'b0}}, nil1li, (nlll1l ^ nlliOO), {6{1'b0}}, nil1Ol, (nlliOi ^ nllill), {7{1'b0}}, (nili1i ^ nlliiO), {3{1'b0}}, nlli1i, {3{1'b0}}, wire_n0lOO_dataout}), .o(wire_n11Ol_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam n11Ol.width_data = 32, n11Ol.width_sel = 5; oper_mux n11OO ( .data({{6{1'b0}}, nil1ll, (nlll1O ^ nlll1i), {6{1'b0}}, nil1OO, (nlliOl ^ nllilO), {7{1'b0}}, 1'b1, {3{1'b0}}, nlli1l, {3{1'b0}}, wire_n0O1i_dataout}), .o(wire_n11OO_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam n11OO.width_data = 32, n11OO.width_sel = 5; oper_mux nii0i ( .data({{7{1'b1}}, 1'b0, {6{1'b1}}, {2{1'b0}}, {7{1'b1}}, (~ rall_one_dect_only), {3{1'b1}}, 1'b0, {3{1'b1}}, (~ rall_one_dect_only)}), .o(wire_nii0i_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam nii0i.width_data = 32, nii0i.width_sel = 5; oper_mux nii0l ( .data({{7{1'b1}}, 1'b0, {6{1'b1}}, 1'b0, {8{1'b1}}, 1'b0, {7{1'b1}}, rall_one_dect_only}), .o(wire_nii0l_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam nii0l.width_data = 32, nii0l.width_sel = 5; oper_mux nii0O ( .data({{7{1'b1}}, 1'b0, {6{1'b1}}, {2{1'b0}}, {7{1'b1}}, 1'b0, {7{1'b1}}, (~ rall_one_dect_only)}), .o(wire_nii0O_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam nii0O.width_data = 32, nii0O.width_sel = 5; oper_mux nii1O ( .data({{14{1'b1}}, {2{1'b0}}, {7{1'b1}}, (~ rall_one_dect_only), {3{1'b1}}, 1'b0, 1'b1, 1'b0, 1'b1, (~ rall_one_dect_only)}), .o(wire_nii1O_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam nii1O.width_data = 32, nii1O.width_sel = 5; oper_mux niiii ( .data({{6{1'b1}}, 1'b0, {7{1'b1}}, 1'b0, {8{1'b1}}, (~ rall_one_dect_only), {7{1'b1}}, rall_one_dect_only}), .o(wire_niiii_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam niiii.width_data = 32, niiii.width_sel = 5; oper_mux niiiO ( .data({{6{1'b1}}, 1'b0, {7{1'b1}}, {2{1'b0}}, {7{1'b1}}, (~ rall_one_dect_only), {5{1'b1}}, 1'b0, {2{1'b1}}}), .o(wire_niiiO_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam niiiO.width_data = 32, niiiO.width_sel = 5; oper_mux niill ( .data({{6{1'b1}}, {2{1'b0}}, {6{1'b1}}, 1'b0, {8{1'b1}}, rall_one_dect_only, {5{1'b1}}, 1'b0, 1'b1, 1'b0}), .o(wire_niill_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam niill.width_data = 32, niill.width_sel = 5; oper_mux niilO ( .data({{6{1'b1}}, {2{1'b0}}, {15{1'b1}}, rall_one_dect_only, {5{1'b1}}, 1'b0, 1'b1, 1'b0}), .o(wire_niilO_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam niilO.width_data = 32, niilO.width_sel = 5; oper_mux nliiiO ( .data({{6{nlii0O}}, niilil, (nlii0O & (~ niil0O)), {6{nlii0O}}, niilil, (nlii0O & (~ niilii)), {7{nlii0O}}, niiO0i, {3{nlii0O}}, niiO0i, nlii0O, niiO0i, nlii0O, niiO0i}), .o(wire_nliiiO_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam nliiiO.width_data = 32, nliiiO.width_sel = 5; oper_mux nliili ( .data({{6{1'b0}}, niiliO, ((nli0li & niil1l) | nli0ll), {6{1'b0}}, niiliO, ((nli0li & niil1O) | nli0ll), {7{1'b0}}, wire_nliOil_dataout, {3{1'b0}}, ((wire_nilii_dataout & (nli0li & niil0i)) | nli0ll), 1'b0, ((nli0li & niil0l) | nli0ll), 1'b0, wire_nll1li_dataout}), .o(wire_nliili_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam nliili.width_data = 32, nliili.width_sel = 5; oper_mux nliill ( .data({{6{1'b0}}, (niilli | nli00O), (niilOi | nli00O), {6{1'b0}}, (niilOO | nli00O), (niiO1l | nli00O), {7{1'b0}}, (niiOii | nli00O), {3{1'b0}}, (niiOli | nli00O), 1'b0, (niiOlO | nli00O), 1'b0, (nil11O | nli00O)}), .o(wire_nliill_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam nliill.width_data = 32, nliill.width_sel = 5; oper_mux nliilO ( .data({{6{1'b0}}, niilli, niilOi, {6{1'b0}}, niilOO, niiO1l, {7{1'b0}}, niiOii, {3{1'b0}}, niiOli, 1'b0, niiOlO, 1'b0, nil11O}), .o(wire_nliilO_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam nliilO.width_data = 32, nliilO.width_sel = 5; oper_mux nliiOi ( .data({{6{1'b0}}, niillO, ((sync_status & niil0O) | nli0li), {6{1'b0}}, niillO, ((sync_status & niilii) | nli0li), {7{1'b0}}, niiOiO, {3{1'b0}}, niiOiO, 1'b0, niiOiO, 1'b0, niiOiO}), .o(wire_nliiOi_o), .sel({rpma_doublewidth_rx, rpmadwidth_rx, rprbs_sel[2:0]})); defparam nliiOi.width_data = 32, nliiOi.width_sel = 5; oper_selector n0ll ( .data({1'b0, ((niO1li32 ^ niO1li31) & wire_n0OO_dataout), 1'b1}), .o(wire_n0ll_o), .sel({niOO, niOi, nlliO})); defparam n0ll.width_data = 3, n0ll.width_sel = 3; oper_selector n0lO ( .data({1'b0, niO0ii, (~ niO00O)}), .o(wire_n0lO_o), .sel({niOO, ((niO1ll30 ^ niO1ll29) & niOi), ((niO1lO28 ^ niO1lO27) & nlliO)})); defparam n0lO.width_data = 3, n0lO.width_sel = 3; oper_selector n0Oi ( .data({niO1Oi, wire_ni1i_dataout, niO00O}), .o(wire_n0Oi_o), .sel({niOO, niOi, nlliO})); defparam n0Oi.width_data = 3, n0Oi.width_sel = 3; oper_selector n0Ol ( .data({(~ niO1Oi), ((niO1Ol26 ^ niO1Ol25) & wire_ni1l_dataout), 1'b0}), .o(wire_n0Ol_o), .sel({niOO, niOi, nlliO})); defparam n0Ol.width_data = 3, n0Ol.width_sel = 3; oper_selector ni0iO ( .data({1'b1, nll0il, rall_one_dect_only}), .o(wire_ni0iO_o), .sel({nilili, nilill, wire_nil0O_o[0]})); defparam ni0iO.width_data = 3, ni0iO.width_sel = 3; oper_selector ni0lO ( .data({1'b1, nll0ll, rall_one_dect_only}), .o(wire_ni0lO_o), .sel({nilili, nilill, wire_nil0O_o[0]})); defparam ni0lO.width_data = 3, ni0lO.width_sel = 3; oper_selector nl00i ( .data({(~ nillil), (~ nilliO), (~ nillli), (~ nillll), (~ nilllO), 1'b1}), .o(wire_nl00i_o), .sel({((nillOi50 ^ nillOi49) & nliOl), ((nillOl48 ^ nillOl47) & nlilO), nlill, ((nillOO46 ^ nillOO45) & nlili), nliiO, nlllil})); defparam nl00i.width_data = 6, nl00i.width_sel = 6; oper_selector nl0iO ( .data({((nilO1i44 ^ nilO1i43) & (~ nilOOl)), (~ nilOOl), (~ nilO1l), (~ nilOOO), ((nilO1O42 ^ nilO1O41) & (~ nilOOO)), 1'b1}), .o(wire_nl0iO_o), .sel({nliOl, nlilO, nlill, nlili, nliiO, nlllil})); defparam nl0iO.width_data = 6, nl0iO.width_sel = 6; oper_selector nl0OO ( .data({(~ nilO0i), (~ nilO0l), (~ nilO0O), (~ nilOii), (~ nilOil), 1'b1}), .o(wire_nl0OO_o), .sel({nliOl, nlilO, nlill, nlili, nliiO, nlllil})); defparam nl0OO.width_data = 6, nl0OO.width_sel = 6; oper_selector nli0O ( .data({((nilOiO40 ^ nilOiO39) & (~ nilOli)), (~ nilOOl), (~ nilOll), (~ nilOlO), (~ nilOOi), 1'b1}), .o(wire_nli0O_o), .sel({nliOl, nlilO, nlill, nlili, nliiO, nlllil})); defparam nli0O.width_data = 6, nli0O.width_sel = 6; assign encdet_prbs = nlii0O, niil0i = ((((((((~ wire_nlO1l_dataout) & (~ wire_nlO1i_dataout)) & wire_nllOO_dataout) & wire_nllOl_dataout) & wire_nllOi_dataout) & wire_nlllO_dataout) & wire_nllll_dataout) & (~ wire_nllli_dataout)), niil0l = ((((((((~ nlliii) & nlli0O) & (~ nlli0l)) & nlli0i) & (~ nlli1O)) & nlli1l) & nlli1i) & nll0OO), niil0O = ((((((((((((((((((((~ data_in[0]) & (~ data_in[1])) & (~ data_in[2])) & (~ data_in[3])) & (~ data_in[4])) & (~ data_in[5])) & data_in[6]) & (~ data_in[7])) & (~ data_in[8])) & (~ data_in[9])) & (~ data_in[10])) & (~ data_in[11])) & data_in[12]) & data_in[13]) & (~ data_in[14])) & (~ data_in[15])) & (~ data_in[16])) & (~ data_in[17])) & data_in[18]) & (~ data_in[19])), niil1l = ((((((((((((((((((((~ nlll0i) & nlll1O) & (~ nlll1l)) & (~ nlll1i)) & (~ nlliOO)) & (~ nlliOl)) & nlliOi) & nllilO) & (~ nllill)) & (~ nllili)) & (~ nlliiO)) & (~ nlliil)) & (~ nlliii)) & nlli0O) & (~ nlli0l)) & (~ nlli0i)) & (~ nlli1O)) & (~ nlli1l)) & (~ nlli1i)) & (~ nll0OO)), niil1O = ((((((((((((((((~ nlliOO) & (~ nlliOl)) & nlliOi) & nllilO) & (~ nllill)) & (~ nllili)) & (~ nlliiO)) & (~ nlliil)) & (~ nlliii)) & nlli0O) & (~ nlli0l)) & (~ nlli0i)) & (~ nlli1O)) & (~ nlli1l)) & (~ nlli1i)) & (~ nll0OO)), niilii = ((((((((((((((((~ data_in[0]) & (~ data_in[1])) & (~ data_in[2])) & (~ data_in[3])) & (~ data_in[4])) & (~ data_in[5])) & data_in[6]) & (~ data_in[7])) & (~ data_in[10])) & (~ data_in[11])) & (~ data_in[12])) & (~ data_in[13])) & data_in[14]) & data_in[15]) & (~ data_in[16])) & (~ data_in[17])), niilil = ((~ wire_nilil_dataout) & nlii0O), niiliO = ((wire_nilil_dataout & nli0li) | nli0ll), niilli = (nli0li & (~ niilll)), niilll = ((((((((((((((((((((~ (wire_nllli_dataout ^ data_in[0])) & (~ (wire_nllll_dataout ^ data_in[1]))) & (~ (wire_nlllO_dataout ^ data_in[2]))) & (~ (wire_nllOi_dataout ^ data_in[3]))) & (~ (wire_nllOl_dataout ^ data_in[4]))) & (~ (wire_nllOO_dataout ^ data_in[5]))) & (~ (wire_nlO1i_dataout ^ data_in[6]))) & (~ (wire_nlO1l_dataout ^ data_in[7]))) & (~ (wire_nlO1O_dataout ^ data_in[8]))) & (~ (wire_nlO0i_dataout ^ data_in[9]))) & (~ (wire_nlO0l_dataout ^ data_in[10]))) & (~ (wire_nlO0O_dataout ^ data_in[11]))) & (~ (wire_nlOii_dataout ^ data_in[12]))) & (~ (wire_nlOil_dataout ^ data_in[13]))) & (~ (wire_nlOiO_dataout ^ data_in[14]))) & (~ (wire_nlOli_dataout ^ data_in[15]))) & (~ (wire_nlOll_dataout ^ data_in[16]))) & (~ (wire_nlOlO_dataout ^ data_in[17]))) & (~ (wire_nlOOi_dataout ^ data_in[18]))) & (~ (wire_nlOOl_dataout ^ data_in[19]))), niillO = ((wire_nilil_dataout & sync_status) | nli0li), niilOi = (nli0li & (~ niilOl)), niilOl = ((((((((((((((((((((~ (nll0OO ^ data_in[0])) & (~ (nlli1i ^ data_in[1]))) & (~ (nlli1l ^ data_in[2]))) & (~ (nlli1O ^ data_in[3]))) & (~ (nlli0i ^ data_in[4]))) & (~ (nlli0l ^ data_in[5]))) & (~ (nlli0O ^ data_in[6]))) & (~ (nlliii ^ data_in[7]))) & (~ (nlliil ^ data_in[8]))) & (~ (nlliiO ^ data_in[9]))) & (~ (nllili ^ data_in[10]))) & (~ (nllill ^ data_in[11]))) & (~ (nllilO ^ data_in[12]))) & (~ (nlliOi ^ data_in[13]))) & (~ (nlliOl ^ data_in[14]))) & (~ (nlliOO ^ data_in[15]))) & (~ (nlll1i ^ data_in[16]))) & (~ (nlll1l ^ data_in[17]))) & (~ (nlll1O ^ data_in[18]))) & (~ (nlll0i ^ data_in[19]))), niilOO = (nli0li & (~ niiO1i)), niiO0i = ((~ wire_nilii_dataout) & nlii0O), niiO0l = (((((((((nlliiO & nlliil) & nlliii) & nlli0O) & nlli0l) & nlli0i) & nlli1O) & nlli1l) & nlli1i) & nll0OO), niiO0O = ((((((((((~ nlliiO) & nlliil) & (~ nlliii)) & nlli0O) & nlli0l) & nlli0i) & nlli1O) & nlli1l) & (~ nlli1i)) & (~ nll0OO)), niiO1i = ((((((((((((((((~ (wire_nllli_dataout ^ data_in[0])) & (~ (wire_nllll_dataout ^ data_in[1]))) & (~ (wire_nlllO_dataout ^ data_in[2]))) & (~ (wire_nllOi_dataout ^ data_in[3]))) & (~ (wire_nllOl_dataout ^ data_in[4]))) & (~ (wire_nllOO_dataout ^ data_in[5]))) & (~ (wire_nlO1i_dataout ^ data_in[6]))) & (~ (wire_nlO1l_dataout ^ data_in[7]))) & (~ (wire_nlO1O_dataout ^ data_in[10]))) & (~ (wire_nlO0i_dataout ^ data_in[11]))) & (~ (wire_nlO0l_dataout ^ data_in[12]))) & (~ (wire_nlO0O_dataout ^ data_in[13]))) & (~ (wire_nlOii_dataout ^ data_in[14]))) & (~ (wire_nlOil_dataout ^ data_in[15]))) & (~ (wire_nlOiO_dataout ^ data_in[16]))) & (~ (wire_nlOli_dataout ^ data_in[17]))), niiO1l = (nli0li & (~ niiO1O)), niiO1O = ((((((((((((((((~ (nll0OO ^ data_in[0])) & (~ (nlli1i ^ data_in[1]))) & (~ (nlli1l ^ data_in[2]))) & (~ (nlli1O ^ data_in[3]))) & (~ (nlli0i ^ data_in[4]))) & (~ (nlli0l ^ data_in[5]))) & (~ (nlli0O ^ data_in[6]))) & (~ (nlliii ^ data_in[7]))) & (~ (nlliil ^ data_in[10]))) & (~ (nlliiO ^ data_in[11]))) & (~ (nllili ^ data_in[12]))) & (~ (nllill ^ data_in[13]))) & (~ (nllilO ^ data_in[14]))) & (~ (nlliOi ^ data_in[15]))) & (~ (nlliOl ^ data_in[16]))) & (~ (nlliOO ^ data_in[17]))), niiOii = (nli0li & (~ niiOil)), niiOil = ((((((((((~ (nll0OO ^ data_in[0])) & (~ (nlli1i ^ data_in[1]))) & (~ (nlli1l ^ data_in[2]))) & (~ (nlli1O ^ data_in[3]))) & (~ (nlli0i ^ data_in[4]))) & (~ (nlli0l ^ data_in[5]))) & (~ (nlli0O ^ data_in[6]))) & (~ (nlliii ^ data_in[7]))) & (~ (nlliil ^ data_in[8]))) & (~ (nlliiO ^ data_in[9]))), niiOiO = (wire_nilii_dataout | nli0li), niiOli = (nli0li & (~ niiOll)), niiOll = ((((((((~ (wire_nllli_dataout ^ data_in[0])) & (~ (wire_nllll_dataout ^ data_in[1]))) & (~ (wire_nlllO_dataout ^ data_in[2]))) & (~ (wire_nllOi_dataout ^ data_in[3]))) & (~ (wire_nllOl_dataout ^ data_in[4]))) & (~ (wire_nllOO_dataout ^ data_in[5]))) & (~ (wire_nlO1i_dataout ^ data_in[6]))) & (~ (wire_nlO1l_dataout ^ data_in[7]))), niiOlO = (nli0li & (~ niiOOi)), niiOOi = ((((((((~ (nll0OO ^ data_in[0])) & (~ (nlli1i ^ data_in[1]))) & (~ (nlli1l ^ data_in[2]))) & (~ (nlli1O ^ data_in[3]))) & (~ (nlli0i ^ data_in[4]))) & (~ (nlli0l ^ data_in[5]))) & (~ (nlli0O ^ data_in[6]))) & (~ (nlliii ^ data_in[7]))), niiOOl = (((((((nll0Ol & nll0Oi) & (~ nll0lO)) & nll0ll) & nll0li) & (~ nll0iO)) & (~ nll0il)) & (~ nli0lO)), niiOOO = ((((((((~ nll0Ol) & nll0Oi) & (~ nll0lO)) & nll0ll) & (~ nll0li)) & (~ nll0iO)) & (~ nll0il)) & (~ nli0lO)), nil00i = (nlll0O ^ nlll1i), nil00l = (nlllii ^ nlll1l), nil00O = (nlll1i ^ nlliOO), nil01i = (nlll1O ^ nlliOi), nil01l = (nlll0i ^ nlliOl), nil01O = (nlll0l ^ nlliOO), nil0ii = (nlll1l ^ nlll1i), nil0il = (nlll1O ^ nlll1l), nil0iO = (nil0li ^ nlll1l), nil0li = (nlll0i ^ nlll1O), nil0ll = (nlliOl ^ nlliOi), nil0lO = (nlliOO ^ nlliOl), nil0Oi = (nlliOO ^ nlliOi), nil0Ol = (nllilO ^ nllill), nil0OO = (nlliOi ^ nllilO), nil10i = ((((((((~ (nliO ^ nli0lO)) & (~ (n0i ^ nll0il))) & (~ (n0l ^ nll0iO))) & (~ (n0O ^ nll0li))) & (~ (nii ^ nll0ll))) & (~ (nil ^ nll0lO))) & (~ (niO ^ nll0Oi))) & (~ (nli ^ nll0Ol))), nil10l = (nlliii ^ nlli1l), nil10O = (nlliil ^ nlli1O), nil11i = (nlO & (~ nll)), nil11l = (((((((nll0Ol & nll0Oi) & nll0lO) & nll0ll) & (~ nll0li)) & nll0iO) & (~ nll0il)) & (~ nli0lO)), nil11O = (nli0li & (~ nil10i)), nil1ii = (nlliiO ^ nlli0i), nil1il = (nllili ^ nlli0l), nil1iO = (nllill ^ nlli0O), nil1li = (nllilO ^ nlliii), nil1ll = (nlliOi ^ nlliil), nil1lO = (nlliOl ^ nlliiO), nil1Oi = (nlliOO ^ nllili), nil1Ol = (nlll1i ^ nllill), nil1OO = (nlll1l ^ nllilO), nili0i = (nlli0i ^ nlli1O), nili0l = (nlli0l ^ nlli0i), nili0O = (nlli0O ^ nlli0l), nili1i = (nlli0l ^ nlli1l), nili1l = (nlli0i ^ nlli1i), nili1O = (nlli1O ^ nll0OO), niliii = (nlliii ^ nlli0O), niliil = (wire_n0li_dataout | wire_n0iO_dataout), niliiO = (nll1l & nli0li), nilili = (((((((((((((((((((((((wire_nil0O_o[31] | wire_nil0O_o[30]) | wire_nil0O_o[29]) | wire_nil0O_o[28]) | wire_nil0O_o[27]) | wire_nil0O_o[26]) | wire_nil0O_o[23]) | wire_nil0O_o[22]) | wire_nil0O_o[21]) | wire_nil0O_o[20]) | wire_nil0O_o[19]) | wire_nil0O_o[18]) | wire_nil0O_o[15]) | wire_nil0O_o[14]) | wire_nil0O_o[13]) | wire_nil0O_o[12]) | wire_nil0O_o[11]) | wire_nil0O_o[10]) | wire_nil0O_o[9]) | wire_nil0O_o[7]) | wire_nil0O_o[6]) | wire_nil0O_o[5]) | wire_nil0O_o[3]) | wire_nil0O_o[1]), nilill = ((((((wire_nil0O_o[25] | wire_nil0O_o[17]) | wire_nil0O_o[16]) | wire_nil0O_o[8]) | wire_nil0O_o[2]) | wire_nil0O_o[24]) | wire_nil0O_o[4]), nililO = ((((wire_nil0O_o[25] | wire_nil0O_o[8]) | wire_nil0O_o[2]) | wire_nil0O_o[0]) | wire_nil0O_o[24]), niliOi = ((((((wire_nil0O_o[25] | wire_nil0O_o[16]) | wire_nil0O_o[8]) | wire_nil0O_o[2]) | wire_nil0O_o[0]) | wire_nil0O_o[24]) | wire_nil0O_o[4]), niliOl = (((((wire_nil0O_o[25] | wire_nil0O_o[17]) | wire_nil0O_o[8]) | wire_nil0O_o[2]) | wire_nil0O_o[0]) | wire_nil0O_o[4]), niliOO = ((((((wire_nil0O_o[25] | wire_nil0O_o[17]) | wire_nil0O_o[16]) | wire_nil0O_o[8]) | wire_nil0O_o[2]) | wire_nil0O_o[0]) | wire_nil0O_o[4]), nill0i = (((((((((((((((((((data_in[0] & data_in[1]) & data_in[2]) & (~ data_in[3])) & (~ data_in[4])) & (~ data_in[5])) & (~ data_in[6])) & (~ data_in[7])) & (~ data_in[8])) & (~ data_in[9])) & (~ data_in[10])) & (~ data_in[11])) & (~ data_in[12])) & (~ data_in[13])) & (~ data_in[14])) & (~ data_in[15])) & (~ data_in[16])) & (~ data_in[17])) & (~ data_in[18])) & (~ data_in[19])), nill0l = (((((((((((((((data_in[0] & data_in[1]) & data_in[2]) & data_in[3]) & data_in[4]) & data_in[5]) & data_in[6]) & (~ data_in[7])) & (~ data_in[10])) & (~ data_in[11])) & (~ data_in[12])) & (~ data_in[13])) & (~ data_in[14])) & (~ data_in[15])) & (~ data_in[16])) & (~ data_in[17])), nill0O = (((((~ rpmadwidth_rx) & (~ rpma_doublewidth_rx)) & (~ rprbs_sel[0])) & rprbs_sel[1]) & (~ rprbs_sel[2])), nill1i = (((((wire_nil0O_o[17] | wire_nil0O_o[16]) | wire_nil0O_o[8]) | wire_nil0O_o[2]) | wire_nil0O_o[0]) | wire_nil0O_o[4]), nill1l = ((((((wire_nil0O_o[17] | wire_nil0O_o[16]) | wire_nil0O_o[8]) | wire_nil0O_o[2]) | wire_nil0O_o[0]) | wire_nil0O_o[24]) | wire_nil0O_o[4]), nill1O = (((((((wire_nil0O_o[25] | wire_nil0O_o[17]) | wire_nil0O_o[16]) | wire_nil0O_o[8]) | wire_nil0O_o[2]) | wire_nil0O_o[0]) | wire_nil0O_o[24]) | wire_nil0O_o[4]), nillii = ((((rpmadwidth_rx & (~ rpma_doublewidth_rx)) & (~ rprbs_sel[0])) & (~ rprbs_sel[1])) & (~ rprbs_sel[2])), nillil = (((((((((data_in[0] & data_in[1]) & data_in[2]) & data_in[3]) & data_in[4]) & data_in[5]) & data_in[6]) & data_in[7]) & data_in[8]) & data_in[9]), nilliO = ((((((((((~ data_in[0]) & (~ data_in[1])) & (~ data_in[2])) & (~ data_in[3])) & (~ data_in[4])) & (~ data_in[5])) & (~ data_in[6])) & data_in[7]) & data_in[8]) & data_in[9]), nillli = ((((((((((~ data_in[0]) & (~ data_in[1])) & (~ data_in[2])) & (~ data_in[3])) & data_in[4]) & data_in[5]) & data_in[6]) & data_in[7]) & data_in[8]) & data_in[9]), nillll = ((((((((((~ data_in[0]) & data_in[1]) & data_in[2]) & data_in[3]) & (~ data_in[4])) & (~ data_in[5])) & (~ data_in[6])) & data_in[7]) & (~ data_in[8])) & (~ data_in[9])), nilllO = (((((((((data_in[0] & data_in[1]) & data_in[2]) & data_in[3]) & data_in[4]) & (~ data_in[5])) & (~ data_in[6])) & (~ data_in[7])) & data_in[8]) & data_in[9]), nilO0i = ((((((((~ data_in[0]) & (~ data_in[1])) & (~ data_in[2])) & (~ data_in[3])) & (~ data_in[4])) & (~ data_in[5])) & data_in[6]) & (~ data_in[7])), nilO0l = ((((((((~ data_in[0]) & (~ data_in[1])) & (~ data_in[2])) & (~ data_in[3])) & data_in[4]) & data_in[5]) & (~ data_in[6])) & (~ data_in[7])), nilO0O = ((((((((~ data_in[0]) & (~ data_in[1])) & data_in[2]) & (~ data_in[3])) & data_in[4]) & (~ data_in[5])) & (~ data_in[6])) & (~ data_in[7])), nilO1l = (((((((data_in[0] & data_in[1]) & data_in[2]) & data_in[3]) & data_in[4]) & data_in[5]) & data_in[6]) & (~ data_in[7])), nilOii = (((((((data_in[0] & data_in[1]) & data_in[2]) & data_in[3]) & (~ data_in[4])) & (~ data_in[5])) & data_in[6]) & (~ data_in[7])), nilOil = ((((((((~ data_in[0]) & (~ data_in[1])) & data_in[2]) & (~ data_in[3])) & data_in[4]) & data_in[5]) & (~ data_in[6])) & (~ data_in[7])), nilOli = ((((((((~ data_in[0]) & data_in[1]) & (~ data_in[2])) & data_in[3]) & data_in[4]) & (~ data_in[5])) & data_in[6]) & (~ data_in[7])), nilOll = ((((((((~ data_in[0]) & (~ data_in[1])) & data_in[2]) & (~ data_in[3])) & data_in[4]) & data_in[5]) & data_in[6]) & data_in[7]), nilOlO = ((((((((~ data_in[0]) & data_in[1]) & (~ data_in[2])) & (~ data_in[3])) & data_in[4]) & (~ data_in[5])) & data_in[6]) & (~ data_in[7])), nilOOi = ((((((((~ data_in[0]) & (~ data_in[1])) & (~ data_in[2])) & data_in[3]) & data_in[4]) & (~ data_in[5])) & data_in[6]) & data_in[7]), nilOOl = (((((((data_in[0] & data_in[1]) & data_in[2]) & data_in[3]) & data_in[4]) & data_in[5]) & data_in[6]) & data_in[7]), nilOOO = ((((((((~ data_in[0]) & (~ data_in[1])) & (~ data_in[2])) & (~ data_in[3])) & (~ data_in[4])) & (~ data_in[5])) & (~ data_in[6])) & (~ data_in[7])), niO00O = ((((((((~ nlil) & (~ nlii)) & (~ nl0O)) & (~ nl0l)) & (~ nl0i)) & (~ nl1O)) & (~ nl1l)) & nl1i), niO01i = ((niOi0O & (((nlO & niO00O) & (niO00i22 ^ niO00i21)) & niO0il)) & (niO01l24 ^ niO01l23)), niO0ii = (niOi0O & (((nlO & wire_nill_o) & (niO0iO20 ^ niO0iO19)) & niO0il)), niO0il = (((((((nlliii & nlli0O) & nlli0l) & (~ nlli0i)) & nlli1O) & nlli1l) & (~ nlli1i)) & nll0OO), niO0Ol = (((((~ rpmadwidth_rx) & (~ rpma_doublewidth_rx)) & (~ rprbs_sel[0])) & (~ rprbs_sel[1])) & (~ rprbs_sel[2])), niO10O = 1'b0, niO11l = (((((((((((((((data_in[0] & data_in[1]) & data_in[2]) & data_in[3]) & data_in[4]) & data_in[5]) & data_in[6]) & data_in[7]) & data_in[10]) & data_in[11]) & data_in[12]) & data_in[13]) & data_in[14]) & data_in[15]) & data_in[16]) & data_in[17]), niO11O = (((((((((((((((((((data_in[0] & data_in[1]) & data_in[2]) & data_in[3]) & data_in[4]) & data_in[5]) & data_in[6]) & data_in[7]) & data_in[8]) & data_in[9]) & data_in[10]) & data_in[11]) & data_in[12]) & data_in[13]) & data_in[14]) & data_in[15]) & data_in[16]) & data_in[17]) & data_in[18]) & data_in[19]), niO1ii = ((((rpmadwidth_rx & rpma_doublewidth_rx) & rprbs_sel[0]) & (~ rprbs_sel[1])) & (~ rprbs_sel[2])), niO1il = (((((~ rpmadwidth_rx) & rpma_doublewidth_rx) & rprbs_sel[0]) & (~ rprbs_sel[1])) & (~ rprbs_sel[2])), niO1iO = (((((~ rpmadwidth_rx) & (~ rpma_doublewidth_rx)) & (~ rprbs_sel[0])) & (~ rprbs_sel[1])) & rprbs_sel[2]), niO1Oi = (((((((nlliii & nlli0O) & nlli0l) & nlli0i) & nlli1O) & nlli1l) & nlli1i) & nll0OO), niO1OO = ((((((((~ nlliii) & nlli0O) & (~ nlli0l)) & nlli0i) & (~ nlli1O)) & (~ nlli1l)) & (~ nlli1i)) & (~ nll0OO)), niOi0i = 1'b1, niOi0O = (nll | ((wire_nliil_dataout & wire_nillO_dataout) & (niOiii2 ^ niOiii1))), prbs_done = nli0ll, prbs_err = (nli0ii | (nli0iO | nli0il)), prbs_err_lt = nli00O, verify_on = nli0li; endmodule //stratixiv_hssi_rx_digi_prbs_ver //synopsys translate_on //VALID FILE //IP Functional Simulation Model //VERSION_BEGIN 12.0 cbx_mgl 2012:05:31:20:09:47:SJ cbx_simgen 2012:05:31:20:08:35:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 // Copyright (C) 1991-2012 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // You may only use these simulation model output files for simulation // purposes and expressly not for synthesis or any other purposes (in which // event Altera disclaims all warranties of any kind). //synopsys translate_off //synthesis_resources = lut 577 mux21 929 oper_add 13 oper_less_than 8 oper_mux 157 oper_selector 81 `timescale 1 ps / 1 ps module stratixiv_hssi_rx_digi_wordalign ( a1a2_k1k2_flag, a1a2_size, adata, adata_valid, autobytealign_dis, bitloc_rev_en, bitslip, byte_rev_en, cg_syncpat, clk, comp_pat, comp_pat_porn, comp_pat_size, disable_rx_disp, dwidth, encdet_prbs, encdt, enumber, gen2ngen1, gen2ngen1_bundle, gnumber, ib_invalid_code, kchar, kcount, knumber, lpbk_en, max_rlv_sel, pipe_loose_sync, pmadwidth, polinv_en, prbs_en, pudi, pudr, r8b10b_dec_ibm_en, rauto_speed_ena, rbitloc_rev_en, rbyte_rev_en, rencdt_rising, resync_badcg_en, rforce_sig_det_pcs, rfreq_sel, rindv_rx, rkchar, rlv, rlv_en, rlv_lt, rosbased, rosnumber, rpolinv_en, rrxpcsbypass_en, rst, rst1, scan_mode, signal_detect, signal_detect_rcvdclk, sudi, sudi_pre, sync_sm_dis, sync_status, testbus, wa_6g_en, wa_boundary) /* synthesis synthesis_clearbox=1 */; output [3:0] a1a2_k1k2_flag; input a1a2_size; output [9:0] adata; output adata_valid; input autobytealign_dis; input bitloc_rev_en; input bitslip; input byte_rev_en; output [1:0] cg_syncpat; input clk; input [39:0] comp_pat; input comp_pat_porn; input [2:0] comp_pat_size; input disable_rx_disp; input dwidth; input encdet_prbs; input encdt; input [9:0] enumber; input gen2ngen1; input gen2ngen1_bundle; input [9:0] gnumber; input [1:0] ib_invalid_code; output kchar; output [9:0] kcount; input [9:0] knumber; input lpbk_en; input [5:0] max_rlv_sel; input pipe_loose_sync; input [1:0] pmadwidth; input polinv_en; input prbs_en; input [19:0] pudi; input [19:0] pudr; input [1:0] r8b10b_dec_ibm_en; input rauto_speed_ena; input rbitloc_rev_en; input rbyte_rev_en; input rencdt_rising; input [1:0] resync_badcg_en; input rforce_sig_det_pcs; input rfreq_sel; input rindv_rx; input rkchar; output rlv; input rlv_en; output rlv_lt; input rosbased; input [3:0] rosnumber; input rpolinv_en; input rrxpcsbypass_en; input rst; output rst1; input scan_mode; input signal_detect; output signal_detect_rcvdclk; output [31:0] sudi; output [13:0] sudi_pre; input sync_sm_dis; output sync_status; output [9:0] testbus; input wa_6g_en; output [4:0] wa_boundary; reg n1i00OO49; reg n1i00OO50; reg n1i0lOi47; reg n1i0lOi48; reg n1i0O0i43; reg n1i0O0i44; reg n1i0O1l45; reg n1i0O1l46; reg n1i0Oil41; reg n1i0Oil42; reg n1i0Oli39; reg n1i0Oli40; reg n1i0OlO37; reg n1i0OlO38; reg n1i0OOl35; reg n1i0OOl36; reg n1ii00O19; reg n1ii00O20; reg n1ii0ii17; reg n1ii0ii18; reg n1ii0ll15; reg n1ii0ll16; reg n1ii0OO13; reg n1ii0OO14; reg n1ii10l33; reg n1ii10l34; reg n1ii1ii31; reg n1ii1ii32; reg n1ii1il29; reg n1ii1il30; reg n1ii1iO27; reg n1ii1iO28; reg n1ii1li25; reg n1ii1li26; reg n1ii1ll23; reg n1ii1ll24; reg n1ii1Oi21; reg n1ii1Oi22; reg n1iii0i11; reg n1iii0i12; reg n1iii0O10; reg n1iii0O9; reg n1iiiil7; reg n1iiiil8; reg n1iiiOl5; reg n1iiiOl6; reg n1iil0O1; reg n1iil0O2; reg n1iil1i3; reg n1iil1i4; reg ni0li; reg ni0Ol; reg ni0Oi_clk_prev; wire wire_ni0Oi_CLRN; reg n01000i; reg n01000l; reg n01000O; reg n01001i; reg n01001l; reg n01001O; reg n0100ii; reg n0100il; reg n0101il; reg n0101iO; reg n0101li; reg n0101ll; reg n0101lO; reg n0101Oi; reg n0101Ol; reg n0101OO; reg n010Ol; reg n010OO; reg n0110i; reg n0110l; reg n0110O; reg n0111i; reg n0111l; reg n0111O; reg n011ii; reg n011il; reg n011iO; reg n011l0i; reg n011l0l; reg n011l0O; reg n011l1l; reg n011l1O; reg n011li; reg n011lii; reg n011lil; reg n011liO; reg n011ll; reg n011lli; reg n011lll; reg n011llO; reg n011lO; reg n011lOi; reg n011lOl; reg n011lOO; reg n011O0i; reg n011O1i; reg n011O1l; reg n011O1O; reg n011Oi; reg n01i0i; reg n01i0l; reg n01i0O; reg n01i1i; reg n01i1l; reg n01i1O; reg n01iii; reg n01iil; reg n01iiO; reg n01ili; reg n01ill; reg n1l00O; reg n1l0ii; reg n1l0il; reg n1l0iO; reg n1l0li; reg n1l0ll; reg n1l0lO; reg n1l0Oi; reg n1liii; reg n1O01i; reg n1O01O; reg n1O1ll; reg n1O1lO; reg n1O1Oi; reg n1O1Ol; reg n1O1OO; reg n1Oi0i; reg n1Oi0l; reg n1Oi0O; reg n1Oi1O; reg n1OilO; reg n1OiOi; reg n1OiOl; reg n1OiOO; reg n1Ol00i; reg n1Ol00l; reg n1Ol00O; reg n1Ol01i; reg n1Ol01l; reg n1Ol01O; reg n1Ol0ii; reg n1Ol0il; reg n1Ol1Ol; reg n1Ol1OO; reg n1Oli0i; reg n1OO00i; reg n1OO01i; reg n1OO01l; reg n1OO0iO; reg n1OO0li; reg n1OO0ll; reg n1OO0lO; reg n1OO1lO; reg n1OO1Oi; reg n1OO1Ol; reg n1OO1OO; reg n1OOi0i; reg n1OOi1O; reg n1OOOl; reg n1OOOO; reg ni0iO; reg ni0OO; reg niii0i; reg niii0l; reg niii0O; reg niiill; reg nil00i; reg nil00l; reg nil00O; reg nil01i; reg nil01l; reg nil01O; reg nil0ii; reg nil0il; reg nil0iO; reg nil0li; reg nil0ll; reg nil0lO; reg nil0Oi; reg nil0Ol; reg nil0OO; reg nil1il; reg nil1iO; reg nil1li; reg nil1ll; reg nil1lO; reg nil1Ol; reg nil1OO; reg nili0i; reg nili0l; reg nili0O; reg nili1i; reg nili1l; reg nili1O; reg niliii; reg niliil; reg niliiO; reg nilili; reg nilill; reg nililO; reg niliOi; reg niliOl; reg niliOO; reg nill0i; reg nill0l; reg nill1i; reg nill1l; reg nill1O; reg niOlii; reg niOlil; reg niOlli; reg niOlll; reg niOllO; reg niOlOi; reg niOlOl; reg niOlOO; reg niOO0i; reg niOO1i; reg niOO1l; reg niOO1O; reg niOOOO; reg nl010il; reg nl010iO; reg nl010li; reg nl010ll; reg nl010lO; reg nl010Oi; reg nl010Ol; reg nl010OO; reg nl0110i; reg nl0110l; reg nl0110O; reg nl0111i; reg nl0111l; reg nl0111O; reg nl011ii; reg nl011il; reg nl011iO; reg nl011li; reg nl011ll; reg nl011lO; reg nl01i0i; reg nl01i0l; reg nl01i0O; reg nl01i1i; reg nl01i1l; reg nl01i1O; reg nl01iii; reg nl01iil; reg nl01iiO; reg nl01ili; reg nl01ill; reg nl01ilO; reg nl01iOi; reg nl01iOl; reg nl01iOO; reg nl01l0i; reg nl01l0l; reg nl01l0O; reg nl01l1i; reg nl01l1l; reg nl01l1O; reg nl01lii; reg nl01lil; reg nl01liO; reg nl01lli; reg nl01lll; reg nl01llO; reg nl01lOi; reg nl01lOl; reg nl01lOO; reg nl01O1i; reg nl01O1l; reg nl01O1O; reg nl100l; reg nl100O; reg nl10ii; reg nl10Ol; reg nl110i; reg nl110l; reg nl110O; reg nl111i; reg nl111l; reg nl111O; reg nl11ii; reg nl11il; reg nl11iO; reg nl1ill; reg nl1ilO; reg nl1l1l; reg nl1lii; reg nl1liii; reg nl1liil; reg nl1lOi; reg nl1Oiil; reg nl1OiiO; reg nl1Oili; reg nl1Oill; reg nl1OilO; reg nl1OiOi; reg nl1OiOl; reg nl1OiOO; reg nl1Ol0i; reg nl1Ol0l; reg nl1Ol0O; reg nl1Ol1i; reg nl1Ol1l; reg nl1Ol1O; reg nl1Olii; reg nl1Olil; reg nl1OliO; reg nl1Olli; reg nl1Olll; reg nl1OllO; reg nl1OlOi; reg nl1OlOl; reg nl1OlOO; reg nl1OO0i; reg nl1OO0l; reg nl1OO0O; reg nl1OO1i; reg nl1OO1l; reg nl1OO1O; reg nl1OOii; reg nl1OOil; reg nl1OOiO; reg nl1OOli; reg nl1OOll; reg nl1OOlO; reg nl1OOOi; reg nl1OOOl; reg nl1OOOO; reg nliiOl; reg nliiOO; reg nlil0i; reg nlil0l; reg nlil0O; reg nlil1i; reg nlil1l; reg nlil1O; reg nlilii; reg nlilll; reg nlillO; reg nlilOi; reg nlilOl; reg nlilOO; reg nliO0i; reg nliO0l; reg nliO0O; reg nliO1i; reg nliO1l; reg nliO1O; reg nliOii; reg nliOil; reg nliOiO; reg nliOli; reg nliOll; reg nliOlO; reg nliOOi; reg nliOOl; reg nliOOO; reg nll000i; reg nll000l; reg nll000O; reg nll001i; reg nll001l; reg nll001O; reg nll00ii; reg nll00il; reg nll00iO; reg nll00li; reg nll00ll; reg nll00lO; reg nll00Oi; reg nll00Ol; reg nll00OO; reg nll01ll; reg nll01lO; reg nll01Oi; reg nll01Ol; reg nll01OO; reg nll0i0i; reg nll0i0l; reg nll0i0O; reg nll0i1i; reg nll0i1l; reg nll0i1O; reg nll0iii; reg nll0iil; reg nll0iiO; reg nll0ili; reg nll0ill; reg nll0ilO; reg nll0iOi; reg nll0iOl; reg nll0iOO; reg nll0l0i; reg nll0l0l; reg nll0l0O; reg nll0l1i; reg nll0l1l; reg nll0l1O; reg nll0lii; reg nll0lil; reg nll0liO; reg nll0lli; reg nll0lll; reg nll0llO; reg nll0lOi; reg nll0lOl; reg nll0lOO; reg nll0O0i; reg nll0O0l; reg nll0O0O; reg nll0O1i; reg nll0O1l; reg nll0O1O; reg nll0Oii; reg nll0Oil; reg nll0OiO; reg nll0Oli; reg nll0Oll; reg nll0OlO; reg nll0OOi; reg nll0OOl; reg nll0OOO; reg nll10i; reg nll11i; reg nll11l; reg nll11O; reg nlli00i; reg nlli00l; reg nlli00O; reg nlli01i; reg nlli01l; reg nlli01O; reg nlli0ii; reg nlli0il; reg nlli0iO; reg nlli0li; reg nlli0ll; reg nlli0lO; reg nlli0Oi; reg nlli0Ol; reg nlli0OO; reg nlli10i; reg nlli10l; reg nlli10O; reg nlli11i; reg nlli11l; reg nlli11O; reg nlli1ii; reg nlli1il; reg nlli1iO; reg nlli1li; reg nlli1ll; reg nlli1lO; reg nlli1Oi; reg nlli1Ol; reg nlli1OO; reg nllii0i; reg nllii0l; reg nllii1i; reg nllii1l; reg nllii1O; reg nllll1i; reg nlllOl; reg nlllOO; reg nlO; reg nlO000i; reg nlO000l; reg nlO000O; reg nlO001i; reg nlO001l; reg nlO001O; reg nlO00ii; reg nlO00il; reg nlO00iO; reg nlO00li; reg nlO00ll; reg nlO00lO; reg nlO00Oi; reg nlO00Ol; reg nlO00OO; reg nlO010i; reg nlO010l; reg nlO011i; reg nlO011l; reg nlO011O; reg nlO01ii; reg nlO01il; reg nlO01iO; reg nlO01li; reg nlO01ll; reg nlO01lO; reg nlO01Oi; reg nlO01Ol; reg nlO01OO; reg nlO0i0i; reg nlO0i0l; reg nlO0i0O; reg nlO0i1i; reg nlO0i1l; reg nlO0i1O; reg nlO0iii; reg nlO0iil; reg nlO0iiO; reg nlO0ili; reg nlO0ill; reg nlO0ilO; reg nlO0l1i; reg nlO0l1l; reg nlO0l1O; reg nlOi0ll; reg nlOi0lO; reg nlOi0Oi; reg nlOi0Ol; reg nlOi0OO; reg nlOii0i; reg nlOii0l; reg nlOii0O; reg nlOii1i; reg nlOii1l; reg nlOii1O; reg nlOiiii; reg nlOiiil; reg nlOiiiO; reg nlOiili; reg nlOiill; reg nlOiilO; reg nlOilOl; reg nlOilOO; reg nlOiO0i; reg nlOiO0l; reg nlOiO1i; reg nlOiO1l; reg nlOiO1O; reg nO; wire wire_nl_CLRN; reg nl10il; reg nl10li; reg nl10ll; reg nl10Oi; wire wire_nl10lO_CLRN; reg nl1lil; reg nl1liO; reg nl1lli; reg nl1llO; reg nlilil; reg nliliO; reg nlilli; reg nll10l; reg nll1ii; reg nll10O_clk_prev; wire wire_nll10O_PRN; wire wire_nll10O_ENA; reg n1O01l; reg n1OO01O; reg nil1Oi; reg nl0100i; reg nl0100l; reg nl0100O; reg nl0101i; reg nl0101l; reg nl0101O; reg nl010ii; reg nl011Oi; reg nl011Ol; reg nl011OO; reg nl1iOi; reg nl1iOl; reg nl1iOO; reg nl1l1i; reg nll01li; reg nll1il; reg nlli0l; reg nlli0O; reg nlliii; reg nllO1l; reg nlO010O; reg nllO1i_clk_prev; wire wire_nllO1i_CLRN; wire wire_n00i_dataout; wire wire_n00l_dataout; wire wire_n00O_dataout; wire wire_n0100i_dataout; wire wire_n0100iO_dataout; wire wire_n0100l_dataout; wire wire_n0100li_dataout; wire wire_n0100ll_dataout; wire wire_n0100lO_dataout; wire wire_n0100O_dataout; wire wire_n0100Oi_dataout; wire wire_n0100Ol_dataout; wire wire_n0100OO_dataout; wire wire_n01010i_dataout; wire wire_n01010l_dataout; wire wire_n01010O_dataout; wire wire_n01011i_dataout; wire wire_n01011l_dataout; wire wire_n01011O_dataout; wire wire_n0101i_dataout; wire wire_n0101ii_dataout; wire wire_n0101l_dataout; wire wire_n0101O_dataout; wire wire_n010i0i_dataout; wire wire_n010i0l_dataout; wire wire_n010i0O_dataout; wire wire_n010i1i_dataout; wire wire_n010i1l_dataout; wire wire_n010i1O_dataout; wire wire_n010ii_dataout; wire wire_n010iii_dataout; wire wire_n010iil_dataout; wire wire_n010iiO_dataout; wire wire_n010il_dataout; wire wire_n010ili_dataout; wire wire_n010iO_dataout; wire wire_n010li_dataout; wire wire_n010ll_dataout; wire wire_n010lO_dataout; wire wire_n010Oi_dataout; wire wire_n0110il_dataout; wire wire_n0110iO_dataout; wire wire_n0110li_dataout; wire wire_n0110ll_dataout; wire wire_n0110lO_dataout; wire wire_n0110Oi_dataout; wire wire_n0110Ol_dataout; wire wire_n0110OO_dataout; wire wire_n011i0i_dataout; wire wire_n011i0l_dataout; wire wire_n011i0O_dataout; wire wire_n011i1i_dataout; wire wire_n011i1l_dataout; wire wire_n011i1O_dataout; wire wire_n011iii_dataout; wire wire_n011iil_dataout; wire wire_n011iiO_dataout; wire wire_n011ill_dataout; wire wire_n011ilO_dataout; wire wire_n011iOi_dataout; wire wire_n011iOl_dataout; wire wire_n011iOO_dataout; wire wire_n011l1i_dataout; wire wire_n011O0l_dataout; wire wire_n011O0O_dataout; wire wire_n011Oii_dataout; wire wire_n011Oil_dataout; wire wire_n011OiO_dataout; wire wire_n011Ol_dataout; wire wire_n011Oli_dataout; wire wire_n011Oll_dataout; wire wire_n011OlO_dataout; wire wire_n011OO_dataout; wire wire_n011OOi_dataout; wire wire_n011OOl_dataout; wire wire_n011OOO_dataout; wire wire_n01i_dataout; wire wire_n01ilO_dataout; wire wire_n01iOi_dataout; wire wire_n01iOl_dataout; wire wire_n01iOO_dataout; wire wire_n01l_dataout; wire wire_n01l0i_dataout; wire wire_n01l0l_dataout; wire wire_n01l0O_dataout; wire wire_n01l1i_dataout; wire wire_n01l1l_dataout; wire wire_n01l1O_dataout; wire wire_n01lii_dataout; wire wire_n01lil_dataout; wire wire_n01liO_dataout; wire wire_n01lli_dataout; wire wire_n01O_dataout; wire wire_n0i_dataout; wire wire_n0ii_dataout; wire wire_n0il_dataout; wire wire_n0iO_dataout; wire wire_n0l_dataout; wire wire_n0li_dataout; wire wire_n0ll_dataout; wire wire_n0lO_dataout; wire wire_n0O_dataout; wire wire_n0Oi_dataout; wire wire_n0Ol_dataout; wire wire_n0OO_dataout; wire wire_n10i_dataout; wire wire_n10l_dataout; wire wire_n10O_dataout; wire wire_n110ll_dataout; wire wire_n11i_dataout; wire wire_n11l_dataout; wire wire_n11O_dataout; wire wire_n1i_dataout; wire wire_n1ii_dataout; wire wire_n1il_dataout; wire wire_n1iliii_dataout; wire wire_n1iO_dataout; wire wire_n1l_dataout; wire wire_n1l0Ol_dataout; wire wire_n1l0OO_dataout; wire wire_n1l11lO_dataout; wire wire_n1l1Ol_dataout; wire wire_n1li_dataout; wire wire_n1li0l_dataout; wire wire_n1li0O_dataout; wire wire_n1li1i_dataout; wire wire_n1li1l_dataout; wire wire_n1liil_dataout; wire wire_n1liiO_dataout; wire wire_n1liO0O_dataout; wire wire_n1ll_dataout; wire wire_n1lliO_dataout; wire wire_n1lllii_dataout; wire wire_n1llOl_dataout; wire wire_n1llOO_dataout; wire wire_n1lO_dataout; wire wire_n1lO0i_dataout; wire wire_n1lO0l_dataout; wire wire_n1lO0O_dataout; wire wire_n1lO1i_dataout; wire wire_n1lO1l_dataout; wire wire_n1lO1O_dataout; wire wire_n1lOii_dataout; wire wire_n1lOil_dataout; wire wire_n1lOiO_dataout; wire wire_n1lOlO_dataout; wire wire_n1lOOi_dataout; wire wire_n1lOOl_dataout; wire wire_n1lOOO_dataout; wire wire_n1O_dataout; wire wire_n1O00i_dataout; wire wire_n1O00l_dataout; wire wire_n1O00O_dataout; wire wire_n1O0ii_dataout; wire wire_n1O0il_dataout; wire wire_n1O0iO_dataout; wire wire_n1O0li_dataout; wire wire_n1O0ll_dataout; wire wire_n1O10i_dataout; wire wire_n1O10l_dataout; wire wire_n1O10lO_dataout; wire wire_n1O10O_dataout; wire wire_n1O11l_dataout; wire wire_n1O11O_dataout; wire wire_n1O1iO_dataout; wire wire_n1O1li_dataout; wire wire_n1Oi_dataout; wire wire_n1Oiii_dataout; wire wire_n1Oiil_dataout; wire wire_n1OiiO_dataout; wire wire_n1Oili_dataout; wire wire_n1Ol_dataout; wire wire_n1Ol0iO_dataout; wire wire_n1Ol0li_dataout; wire wire_n1Ol0ll_dataout; wire wire_n1Ol0lO_dataout; wire wire_n1Ol0Oi_dataout; wire wire_n1Ol10O_dataout; wire wire_n1Oli0l_dataout; wire wire_n1Oli0O_dataout; wire wire_n1Oli1i_dataout; wire wire_n1Oli1l_dataout; wire wire_n1Oli1O_dataout; wire wire_n1Ollil_dataout; wire wire_n1OllOi_dataout; wire wire_n1OllOl_dataout; wire wire_n1OllOO_dataout; wire wire_n1OlO0i_dataout; wire wire_n1OlO0l_dataout; wire wire_n1OlO0O_dataout; wire wire_n1OlO1i_dataout; wire wire_n1OlO1l_dataout; wire wire_n1OlO1O_dataout; wire wire_n1OlOii_dataout; wire wire_n1OlOil_dataout; wire wire_n1OlOiO_dataout; wire wire_n1OlOlO_dataout; wire wire_n1OlOOi_dataout; wire wire_n1OlOOl_dataout; wire wire_n1OlOOO_dataout; wire wire_n1OO_dataout; wire wire_n1OO0Oi_dataout; wire wire_n1OO0Ol_dataout; wire wire_n1OO0OO_dataout; wire wire_n1OO10i_dataout; wire wire_n1OO10l_dataout; wire wire_n1OO10O_dataout; wire wire_n1OO11i_dataout; wire wire_n1OO11O_dataout; wire wire_n1OO1ii_dataout; wire wire_n1OO1li_dataout; wire wire_n1OO1ll_dataout; wire wire_n1OOi1i_dataout; wire wire_n1OOOi_dataout; wire wire_ni_dataout; wire wire_ni0i_dataout; wire wire_ni0l_dataout; wire wire_ni0lO_dataout; wire wire_ni0O_dataout; wire wire_ni1i_dataout; wire wire_ni1l_dataout; wire wire_ni1O_dataout; wire wire_nii_dataout; wire wire_nii00i_dataout; wire wire_nii00l_dataout; wire wire_nii00O_dataout; wire wire_nii01i_dataout; wire wire_nii01l_dataout; wire wire_nii01O_dataout; wire wire_nii0i_dataout; wire wire_nii0ii_dataout; wire wire_nii0il_dataout; wire wire_nii0iO_dataout; wire wire_nii0l_dataout; wire wire_nii0li_dataout; wire wire_nii0ll_dataout; wire wire_nii0lO_dataout; wire wire_nii0O_dataout; wire wire_nii0Oi_dataout; wire wire_nii0Ol_dataout; wire wire_nii0OO_dataout; wire wire_nii1i_dataout; wire wire_nii1l_dataout; wire wire_nii1O_dataout; wire wire_niii_dataout; wire wire_niii1i_dataout; wire wire_niii1l_dataout; wire wire_niii1O_dataout; wire wire_niiii_dataout; wire wire_niiil_dataout; wire wire_niiiO_dataout; wire wire_niiiOO_dataout; wire wire_niil_dataout; wire wire_niil0i_dataout; wire wire_niil0l_dataout; wire wire_niil0O_dataout; wire wire_niil1i_dataout; wire wire_niil1l_dataout; wire wire_niil1O_dataout; wire wire_niili_dataout; wire wire_niilii_dataout; wire wire_niilil_dataout; wire wire_niiliO_dataout; wire wire_niill_dataout; wire wire_niilli_dataout; wire wire_niilll_dataout; wire wire_niillO_dataout; wire wire_niilO_dataout; wire wire_niilOi_dataout; wire wire_niilOl_dataout; wire wire_niilOO_dataout; wire wire_niiO_dataout; wire wire_niiO0i_dataout; wire wire_niiO0l_dataout; wire wire_niiO0O_dataout; wire wire_niiO1i_dataout; wire wire_niiO1l_dataout; wire wire_niiO1O_dataout; wire wire_niiOi_dataout; wire wire_niiOii_dataout; wire wire_niiOil_dataout; wire wire_niiOiO_dataout; wire wire_niiOl_dataout; wire wire_niiOli_dataout; wire wire_niiOO_dataout; wire wire_nil_dataout; wire wire_nil0i_dataout; wire wire_nil0l_dataout; wire wire_nil0O_dataout; wire wire_nil10l_dataout; wire wire_nil1i_dataout; wire wire_nil1l_dataout; wire wire_nil1O_dataout; wire wire_nili_dataout; wire wire_nilii_dataout; wire wire_nilil_dataout; wire wire_niliO_dataout; wire wire_nill_dataout; wire wire_nilli_dataout; wire wire_nillii_dataout; wire wire_nillil_dataout; wire wire_nilll_dataout; wire wire_nilllO_dataout; wire wire_nillO_dataout; wire wire_nillOi_dataout; wire wire_nillOl_dataout; wire wire_nillOO_dataout; wire wire_nilO_dataout; wire wire_nilO0i_dataout; wire wire_nilO0l_dataout; wire wire_nilO0O_dataout; wire wire_nilO1i_dataout; wire wire_nilO1l_dataout; wire wire_nilO1O_dataout; wire wire_nilOi_dataout; wire wire_nilOii_dataout; wire wire_nilOil_dataout; wire wire_nilOiO_dataout; wire wire_nilOl_dataout; wire wire_nilOli_dataout; wire wire_nilOll_dataout; wire wire_nilOlO_dataout; wire wire_nilOO_dataout; wire wire_nilOOi_dataout; wire wire_nilOOl_dataout; wire wire_nilOOO_dataout; wire wire_niO0i_dataout; wire wire_niO0l_dataout; wire wire_niO0O_dataout; wire wire_niO10l_dataout; wire wire_niO10O_dataout; wire wire_niO11i_dataout; wire wire_niO1i_dataout; wire wire_niO1ii_dataout; wire wire_niO1il_dataout; wire wire_niO1iO_dataout; wire wire_niO1l_dataout; wire wire_niO1li_dataout; wire wire_niO1ll_dataout; wire wire_niO1lO_dataout; wire wire_niO1O_dataout; wire wire_niOi_dataout; wire wire_niOi0i_dataout; wire wire_niOi0l_dataout; wire wire_niOi0O_dataout; wire wire_niOi1i_dataout; wire wire_niOi1l_dataout; wire wire_niOi1O_dataout; wire wire_niOii_dataout; wire wire_niOiii_dataout; wire wire_niOiil_dataout; wire wire_niOiiO_dataout; wire wire_niOil_dataout; wire wire_niOili_dataout; wire wire_niOiO_dataout; wire wire_niOl_dataout; wire wire_niOl0i_dataout; wire wire_niOl0l_dataout; wire wire_niOli_dataout; wire wire_niOll_dataout; wire wire_niOlO_dataout; wire wire_niOO_dataout; wire wire_niOOi_dataout; wire wire_niOOl_dataout; wire wire_niOOO_dataout; wire wire_nl0000i_dataout; wire wire_nl0000l_dataout; wire wire_nl0000O_dataout; wire wire_nl0001i_dataout; wire wire_nl0001l_dataout; wire wire_nl0001O_dataout; wire wire_nl000i_dataout; wire wire_nl000ii_dataout; wire wire_nl000il_dataout; wire wire_nl000iO_dataout; wire wire_nl000li_dataout; wire wire_nl000ll_dataout; wire wire_nl000lO_dataout; wire wire_nl000Oi_dataout; wire wire_nl000Ol_dataout; wire wire_nl000OO_dataout; wire wire_nl0010i_dataout; wire wire_nl0010l_dataout; wire wire_nl0010O_dataout; wire wire_nl0011i_dataout; wire wire_nl0011l_dataout; wire wire_nl0011O_dataout; wire wire_nl001i_dataout; wire wire_nl001ii_dataout; wire wire_nl001il_dataout; wire wire_nl001iO_dataout; wire wire_nl001li_dataout; wire wire_nl001ll_dataout; wire wire_nl001lO_dataout; wire wire_nl001Oi_dataout; wire wire_nl001Ol_dataout; wire wire_nl001OO_dataout; wire wire_nl00i_dataout; wire wire_nl00i0i_dataout; wire wire_nl00i0l_dataout; wire wire_nl00i0O_dataout; wire wire_nl00i1i_dataout; wire wire_nl00i1l_dataout; wire wire_nl00i1O_dataout; wire wire_nl00ii_dataout; wire wire_nl00iii_dataout; wire wire_nl00iil_dataout; wire wire_nl00iiO_dataout; wire wire_nl00ili_dataout; wire wire_nl00ill_dataout; wire wire_nl00ilO_dataout; wire wire_nl00iOi_dataout; wire wire_nl00iOl_dataout; wire wire_nl00iOO_dataout; wire wire_nl00l_dataout; wire wire_nl00l1i_dataout; wire wire_nl00l1l_dataout; wire wire_nl00l1O_dataout; wire wire_nl00li_dataout; wire wire_nl00O_dataout; wire wire_nl00Oi_dataout; wire wire_nl010l_dataout; wire wire_nl011i_dataout; wire wire_nl011l_dataout; wire wire_nl011O_dataout; wire wire_nl01i_dataout; wire wire_nl01ii_dataout; wire wire_nl01l_dataout; wire wire_nl01li_dataout; wire wire_nl01O_dataout; wire wire_nl01O0i_dataout; wire wire_nl01O0l_dataout; wire wire_nl01O0O_dataout; wire wire_nl01Oi_dataout; wire wire_nl01Oii_dataout; wire wire_nl01Oil_dataout; wire wire_nl01OiO_dataout; wire wire_nl01Oli_dataout; wire wire_nl01Oll_dataout; wire wire_nl01OlO_dataout; wire wire_nl01OOi_dataout; wire wire_nl01OOl_dataout; wire wire_nl01OOO_dataout; wire wire_nl0i_dataout; wire wire_nl0i00i_dataout; wire wire_nl0i00l_dataout; wire wire_nl0i00O_dataout; wire wire_nl0i01i_dataout; wire wire_nl0i01l_dataout; wire wire_nl0i01O_dataout; wire wire_nl0i0i_dataout; wire wire_nl0i0ii_dataout; wire wire_nl0i0il_dataout; wire wire_nl0i0iO_dataout; wire wire_nl0i0l_dataout; wire wire_nl0i0li_dataout; wire wire_nl0i0ll_dataout; wire wire_nl0i0lO_dataout; wire wire_nl0i0O_dataout; wire wire_nl0i0Oi_dataout; wire wire_nl0i1i_dataout; wire wire_nl0i1l_dataout; wire wire_nl0i1O_dataout; wire wire_nl0i1Ol_dataout; wire wire_nl0i1OO_dataout; wire wire_nl0ii_dataout; wire wire_nl0ii0i_dataout; wire wire_nl0ii0l_dataout; wire wire_nl0ii0O_dataout; wire wire_nl0iii_dataout; wire wire_nl0iiii_dataout; wire wire_nl0iiil_dataout; wire wire_nl0iiiO_dataout; wire wire_nl0iil_dataout; wire wire_nl0iili_dataout; wire wire_nl0iill_dataout; wire wire_nl0iilO_dataout; wire wire_nl0iiO_dataout; wire wire_nl0iiOi_dataout; wire wire_nl0il_dataout; wire wire_nl0il0i_dataout; wire wire_nl0il0l_dataout; wire wire_nl0il0O_dataout; wire wire_nl0il1i_dataout; wire wire_nl0il1l_dataout; wire wire_nl0il1O_dataout; wire wire_nl0ili_dataout; wire wire_nl0ilii_dataout; wire wire_nl0ilil_dataout; wire wire_nl0iliO_dataout; wire wire_nl0ill_dataout; wire wire_nl0illi_dataout; wire wire_nl0illO_dataout; wire wire_nl0ilO_dataout; wire wire_nl0ilOi_dataout; wire wire_nl0ilOl_dataout; wire wire_nl0ilOO_dataout; wire wire_nl0iO_dataout; wire wire_nl0iO0i_dataout; wire wire_nl0iO0l_dataout; wire wire_nl0iO0O_dataout; wire wire_nl0iO1i_dataout; wire wire_nl0iO1l_dataout; wire wire_nl0iO1O_dataout; wire wire_nl0iOi_dataout; wire wire_nl0iOil_dataout; wire wire_nl0iOiO_dataout; wire wire_nl0iOl_dataout; wire wire_nl0iOli_dataout; wire wire_nl0iOll_dataout; wire wire_nl0iOlO_dataout; wire wire_nl0iOO_dataout; wire wire_nl0iOOi_dataout; wire wire_nl0iOOl_dataout; wire wire_nl0iOOO_dataout; wire wire_nl0l_dataout; wire wire_nl0l00i_dataout; wire wire_nl0l01i_dataout; wire wire_nl0l01l_dataout; wire wire_nl0l0i_dataout; wire wire_nl0l0ii_dataout; wire wire_nl0l0il_dataout; wire wire_nl0l0iO_dataout; wire wire_nl0l0l_dataout; wire wire_nl0l0ll_dataout; wire wire_nl0l0lO_dataout; wire wire_nl0l0O_dataout; wire wire_nl0l11i_dataout; wire wire_nl0l11l_dataout; wire wire_nl0l1i_dataout; wire wire_nl0l1ii_dataout; wire wire_nl0l1il_dataout; wire wire_nl0l1l_dataout; wire wire_nl0l1lO_dataout; wire wire_nl0l1O_dataout; wire wire_nl0l1Oi_dataout; wire wire_nl0l1Ol_dataout; wire wire_nl0l1OO_dataout; wire wire_nl0li_dataout; wire wire_nl0lii_dataout; wire wire_nl0lil_dataout; wire wire_nl0liO_dataout; wire wire_nl0ll_dataout; wire wire_nl0lli_dataout; wire wire_nl0lll_dataout; wire wire_nl0llO_dataout; wire wire_nl0lO_dataout; wire wire_nl0lOi_dataout; wire wire_nl0lOl_dataout; wire wire_nl0lOO_dataout; wire wire_nl0O_dataout; wire wire_nl0O0i_dataout; wire wire_nl0O0l_dataout; wire wire_nl0O0O_dataout; wire wire_nl0O1i_dataout; wire wire_nl0O1l_dataout; wire wire_nl0O1O_dataout; wire wire_nl0Oi_dataout; wire wire_nl0Oii_dataout; wire wire_nl0Oil_dataout; wire wire_nl0OiO_dataout; wire wire_nl0Ol_dataout; wire wire_nl0Oli_dataout; wire wire_nl0Oll_dataout; wire wire_nl0OlO_dataout; wire wire_nl0OO_dataout; wire wire_nl0OOi_dataout; wire wire_nl0OOl_dataout; wire wire_nl0OOO_dataout; wire wire_nl10i_dataout; wire wire_nl10l_dataout; wire wire_nl10O_dataout; wire wire_nl10OO_dataout; wire wire_nl11i_dataout; wire wire_nl11l_dataout; wire wire_nl11O_dataout; wire wire_nl1i_dataout; wire wire_nl1i0i_dataout; wire wire_nl1i0l_dataout; wire wire_nl1i0O_dataout; wire wire_nl1i1i_dataout; wire wire_nl1i1l_dataout; wire wire_nl1i1O_dataout; wire wire_nl1ii_dataout; wire wire_nl1iii_dataout; wire wire_nl1il_dataout; wire wire_nl1iO_dataout; wire wire_nl1iOil_dataout; wire wire_nl1iOiO_dataout; wire wire_nl1iOli_dataout; wire wire_nl1iOll_dataout; wire wire_nl1iOlO_dataout; wire wire_nl1iOOi_dataout; wire wire_nl1iOOl_dataout; wire wire_nl1iOOO_dataout; wire wire_nl1l_dataout; wire wire_nl1l00i_dataout; wire wire_nl1l00l_dataout; wire wire_nl1l00O_dataout; wire wire_nl1l01i_dataout; wire wire_nl1l01l_dataout; wire wire_nl1l01O_dataout; wire wire_nl1l0i_dataout; wire wire_nl1l0ii_dataout; wire wire_nl1l0il_dataout; wire wire_nl1l0iO_dataout; wire wire_nl1l0l_dataout; wire wire_nl1l0li_dataout; wire wire_nl1l0ll_dataout; wire wire_nl1l0lO_dataout; wire wire_nl1l0O_dataout; wire wire_nl1l0Oi_dataout; wire wire_nl1l0Ol_dataout; wire wire_nl1l0OO_dataout; wire wire_nl1l10i_dataout; wire wire_nl1l10l_dataout; wire wire_nl1l10O_dataout; wire wire_nl1l11i_dataout; wire wire_nl1l11l_dataout; wire wire_nl1l11O_dataout; wire wire_nl1l1ii_dataout; wire wire_nl1l1il_dataout; wire wire_nl1l1iO_dataout; wire wire_nl1l1li_dataout; wire wire_nl1l1ll_dataout; wire wire_nl1l1lO_dataout; wire wire_nl1l1O_dataout; wire wire_nl1l1Oi_dataout; wire wire_nl1l1Ol_dataout; wire wire_nl1l1OO_dataout; wire wire_nl1li_dataout; wire wire_nl1li0i_dataout; wire wire_nl1li0l_dataout; wire wire_nl1li0O_dataout; wire wire_nl1li1i_dataout; wire wire_nl1li1l_dataout; wire wire_nl1li1O_dataout; wire wire_nl1ll_dataout; wire wire_nl1lO_dataout; wire wire_nl1O_dataout; wire wire_nl1O00l_dataout; wire wire_nl1O00O_dataout; wire wire_nl1O0ii_dataout; wire wire_nl1O0il_dataout; wire wire_nl1O0iO_dataout; wire wire_nl1O0li_dataout; wire wire_nl1O0ll_dataout; wire wire_nl1O0lO_dataout; wire wire_nl1O0Oi_dataout; wire wire_nl1O0Ol_dataout; wire wire_nl1O0OO_dataout; wire wire_nl1Oi_dataout; wire wire_nl1Oi0i_dataout; wire wire_nl1Oi0l_dataout; wire wire_nl1Oi0O_dataout; wire wire_nl1Oi1i_dataout; wire wire_nl1Oi1l_dataout; wire wire_nl1Oi1O_dataout; wire wire_nl1Oiii_dataout; wire wire_nl1Ol_dataout; wire wire_nl1OO_dataout; wire wire_nl1OOl_dataout; wire wire_nl1OOO_dataout; wire wire_nli00i_dataout; wire wire_nli00l_dataout; wire wire_nli00O_dataout; wire wire_nli01i_dataout; wire wire_nli01l_dataout; wire wire_nli01O_dataout; wire wire_nli0i_dataout; wire wire_nli0ii_dataout; wire wire_nli0il_dataout; wire wire_nli0iO_dataout; wire wire_nli0l_dataout; wire wire_nli0li_dataout; wire wire_nli0ll_dataout; wire wire_nli0lO_dataout; wire wire_nli0O_dataout; wire wire_nli0Oi_dataout; wire wire_nli0Ol_dataout; wire wire_nli0OO_dataout; wire wire_nli10i_dataout; wire wire_nli10l_dataout; wire wire_nli10O_dataout; wire wire_nli11i_dataout; wire wire_nli11l_dataout; wire wire_nli11O_dataout; wire wire_nli1i_dataout; wire wire_nli1ii_dataout; wire wire_nli1il_dataout; wire wire_nli1iO_dataout; wire wire_nli1l_dataout; wire wire_nli1li_dataout; wire wire_nli1ll_dataout; wire wire_nli1lO_dataout; wire wire_nli1O_dataout; wire wire_nli1Oi_dataout; wire wire_nli1Ol_dataout; wire wire_nli1OO_dataout; wire wire_nlii_dataout; wire wire_nlii0i_dataout; wire wire_nlii0l_dataout; wire wire_nlii0O_dataout; wire wire_nlii1i_dataout; wire wire_nlii1l_dataout; wire wire_nlii1O_dataout; wire wire_nliii_dataout; wire wire_nliiii_dataout; wire wire_nliiil_dataout; wire wire_nliiiO_dataout; wire wire_nliil_dataout; wire wire_nliili_dataout; wire wire_nliill_dataout; wire wire_nliilO_dataout; wire wire_nliiO_dataout; wire wire_nliiOi_dataout; wire wire_nlil_dataout; wire wire_nlili_dataout; wire wire_nlill_dataout; wire wire_nlilO_dataout; wire wire_nliO_dataout; wire wire_nliOi_dataout; wire wire_nliOl_dataout; wire wire_nliOO_dataout; wire wire_nll00i_dataout; wire wire_nll00l_dataout; wire wire_nll00O_dataout; wire wire_nll01i_dataout; wire wire_nll01l_dataout; wire wire_nll01O_dataout; wire wire_nll0i_dataout; wire wire_nll0ii_dataout; wire wire_nll0il_dataout; wire wire_nll0iO_dataout; wire wire_nll0l_dataout; wire wire_nll0li_dataout; wire wire_nll0ll_dataout; wire wire_nll0lO_dataout; wire wire_nll0O_dataout; wire wire_nll0Oi_dataout; wire wire_nll0Ol_dataout; wire wire_nll0OO_dataout; wire wire_nll1i_dataout; wire wire_nll1iO_dataout; wire wire_nll1l_dataout; wire wire_nll1li_dataout; wire wire_nll1ll_dataout; wire wire_nll1lO_dataout; wire wire_nll1lOi_dataout; wire wire_nll1lOl_dataout; wire wire_nll1O_dataout; wire wire_nll1O0i_dataout; wire wire_nll1O0l_dataout; wire wire_nll1O0O_dataout; wire wire_nll1O1O_dataout; wire wire_nll1Oi_dataout; wire wire_nll1Ol_dataout; wire wire_nll1OO_dataout; wire wire_nlli_dataout; wire wire_nlli0i_dataout; wire wire_nlli1i_dataout; wire wire_nlli1l_dataout; wire wire_nlli1O_dataout; wire wire_nllii_dataout; wire wire_nllii0O_dataout; wire wire_nlliiii_dataout; wire wire_nlliiil_dataout; wire wire_nlliiiO_dataout; wire wire_nlliil_dataout; wire wire_nlliili_dataout; wire wire_nlliill_dataout; wire wire_nlliilO_dataout; wire wire_nlliiO_dataout; wire wire_nlliiOi_dataout; wire wire_nlliiOl_dataout; wire wire_nlliiOO_dataout; wire wire_nllil_dataout; wire wire_nllil0i_dataout; wire wire_nllil0l_dataout; wire wire_nllil0O_dataout; wire wire_nllil1i_dataout; wire wire_nllil1l_dataout; wire wire_nllil1O_dataout; wire wire_nllili_dataout; wire wire_nllilii_dataout; wire wire_nllilil_dataout; wire wire_nlliliO_dataout; wire wire_nllill_dataout; wire wire_nllilli_dataout; wire wire_nllilO_dataout; wire wire_nllilOO_dataout; wire wire_nlliO_dataout; wire wire_nlliO1i_dataout; wire wire_nlliOi_dataout; wire wire_nlliOl_dataout; wire wire_nlliOO_dataout; wire wire_nlll_dataout; wire wire_nlll0l_dataout; wire wire_nlll0O_dataout; wire wire_nllli_dataout; wire wire_nlllii_dataout; wire wire_nllliil_dataout; wire wire_nllliiO_dataout; wire wire_nlllil_dataout; wire wire_nlllili_dataout; wire wire_nlllill_dataout; wire wire_nlllilO_dataout; wire wire_nllliO_dataout; wire wire_nllliOi_dataout; wire wire_nllliOl_dataout; wire wire_nllll_dataout; wire wire_nlllli_dataout; wire wire_nlllO_dataout; wire wire_nllO_dataout; wire wire_nllO00i_dataout; wire wire_nllO00l_dataout; wire wire_nllO00O_dataout; wire wire_nllO01i_dataout; wire wire_nllO01l_dataout; wire wire_nllO01O_dataout; wire wire_nllO0ii_dataout; wire wire_nllO0il_dataout; wire wire_nllOi_dataout; wire wire_nllOi0l_dataout; wire wire_nllOi0O_dataout; wire wire_nllOi1l_dataout; wire wire_nllOi1O_dataout; wire wire_nllOiii_dataout; wire wire_nllOiil_dataout; wire wire_nllOiiO_dataout; wire wire_nllOili_dataout; wire wire_nllOill_dataout; wire wire_nllOilO_dataout; wire wire_nllOiOi_dataout; wire wire_nllOiOl_dataout; wire wire_nllOiOO_dataout; wire wire_nllOl_dataout; wire wire_nllOl0i_dataout; wire wire_nllOl0l_dataout; wire wire_nllOl0O_dataout; wire wire_nllOl1i_dataout; wire wire_nllOl1l_dataout; wire wire_nllOl1O_dataout; wire wire_nllOlii_dataout; wire wire_nllOlil_dataout; wire wire_nllOliO_dataout; wire wire_nllOO_dataout; wire wire_nllOO0O_dataout; wire wire_nllOOii_dataout; wire wire_nllOOil_dataout; wire wire_nllOOiO_dataout; wire wire_nllOOli_dataout; wire wire_nllOOll_dataout; wire wire_nllOOlO_dataout; wire wire_nllOOOi_dataout; wire wire_nllOOOl_dataout; wire wire_nllOOOO_dataout; wire wire_nlO0i_dataout; wire wire_nlO0l_dataout; wire wire_nlO0O_dataout; wire wire_nlO0O0l_dataout; wire wire_nlO0Oli_dataout; wire wire_nlO0OOO_dataout; wire wire_nlO100i_dataout; wire wire_nlO100l_dataout; wire wire_nlO101i_dataout; wire wire_nlO101l_dataout; wire wire_nlO101O_dataout; wire wire_nlO110O_dataout; wire wire_nlO11ii_dataout; wire wire_nlO11il_dataout; wire wire_nlO11iO_dataout; wire wire_nlO11li_dataout; wire wire_nlO11ll_dataout; wire wire_nlO11lO_dataout; wire wire_nlO11Oi_dataout; wire wire_nlO11Ol_dataout; wire wire_nlO11OO_dataout; wire wire_nlO1i_dataout; wire wire_nlO1i0i_dataout; wire wire_nlO1i0l_dataout; wire wire_nlO1i0O_dataout; wire wire_nlO1i1i_dataout; wire wire_nlO1i1l_dataout; wire wire_nlO1i1O_dataout; wire wire_nlO1iii_dataout; wire wire_nlO1iil_dataout; wire wire_nlO1iiO_dataout; wire wire_nlO1ili_dataout; wire wire_nlO1ill_dataout; wire wire_nlO1ilO_dataout; wire wire_nlO1iOi_dataout; wire wire_nlO1iOl_dataout; wire wire_nlO1iOO_dataout; wire wire_nlO1l_dataout; wire wire_nlO1l0i_dataout; wire wire_nlO1l0l_dataout; wire wire_nlO1l0O_dataout; wire wire_nlO1l1l_dataout; wire wire_nlO1l1O_dataout; wire wire_nlO1lii_dataout; wire wire_nlO1lil_dataout; wire wire_nlO1liO_dataout; wire wire_nlO1O_dataout; wire wire_nlO1O0i_dataout; wire wire_nlO1O0l_dataout; wire wire_nlO1O0O_dataout; wire wire_nlO1O1l_dataout; wire wire_nlO1O1O_dataout; wire wire_nlO1Oll_dataout; wire wire_nlO1OlO_dataout; wire wire_nlOi_dataout; wire wire_nlOi00l_dataout; wire wire_nlOi0li_dataout; wire wire_nlOi10l_dataout; wire wire_nlOi1li_dataout; wire wire_nlOi1OO_dataout; wire wire_nlOii_dataout; wire wire_nlOil_dataout; wire wire_nlOiO_dataout; wire wire_nlOl_dataout; wire wire_nlOli_dataout; wire wire_nlOll_dataout; wire wire_nlOll0O_dataout; wire wire_nlOlO_dataout; wire wire_nlOO_dataout; wire wire_nlOOi_dataout; wire wire_nlOOl_dataout; wire wire_nlOOO_dataout; wire [6:0] wire_n011ili_o; wire [4:0] wire_n1li0i_o; wire [3:0] wire_n1li1O_o; wire [5:0] wire_n1O0lO_o; wire [4:0] wire_n1Ol0Ol_o; wire [5:0] wire_n1Ol0OO_o; wire [4:0] wire_nl0iiOl_o; wire [4:0] wire_nl1iil_o; wire [10:0] wire_nllO1lO_o; wire [9:0] wire_nllO1Oi_o; wire [9:0] wire_nllO1Ol_o; wire [9:0] wire_nllO1OO_o; wire [3:0] wire_nlO0l0i_o; wire wire_n1Oill_o; wire wire_n1OOi1l_o; wire wire_nl0iiOO_o; wire wire_nl0illl_o; wire wire_nl0iOii_o; wire wire_nl0l11O_o; wire wire_nllOO1l_o; wire wire_nlO10Ol_o; wire wire_niOO0l_o; wire wire_niOO0O_o; wire wire_niOOii_o; wire wire_niOOil_o; wire wire_niOOiO_o; wire wire_niOOli_o; wire wire_niOOll_o; wire wire_niOOlO_o; wire wire_niOOOi_o; wire wire_niOOOl_o; wire wire_nl00l0i_o; wire wire_nl00l0l_o; wire wire_nl00l0O_o; wire wire_nl00lii_o; wire wire_nl00lil_o; wire wire_nl00liO_o; wire wire_nl00lli_o; wire wire_nl00lll_o; wire wire_nl00llO_o; wire wire_nl00lOi_o; wire wire_nl00lOl_o; wire wire_nl00lOO_o; wire wire_nl00O0i_o; wire wire_nl00O0l_o; wire wire_nl00O0O_o; wire wire_nl00O1i_o; wire wire_nl00O1l_o; wire wire_nl00O1O_o; wire wire_nl00Oil_o; wire wire_nl00OiO_o; wire wire_nl00Oli_o; wire wire_nl00Oll_o; wire wire_nl00OlO_o; wire wire_nl00OOi_o; wire wire_nl00OOl_o; wire wire_nl00OOO_o; wire wire_nl0i0Ol_o; wire wire_nl0i0OO_o; wire wire_nl0i10i_o; wire wire_nl0i10l_o; wire wire_nl0i10O_o; wire wire_nl0i11i_o; wire wire_nl0i11l_o; wire wire_nl0i11O_o; wire wire_nl0i1ii_o; wire wire_nl0i1il_o; wire wire_nl0i1iO_o; wire wire_nl0i1li_o; wire wire_nl0i1ll_o; wire wire_nl0i1lO_o; wire wire_nl0ii1i_o; wire wire_nl0ii1l_o; wire wire_nl0ii1O_o; wire wire_nl0l0OO_o; wire wire_nl0li1i_o; wire wire_nl0OiOl_o; wire wire_nl0OiOO_o; wire wire_nl0Ol0i_o; wire wire_nl0Ol0l_o; wire wire_nl0Ol0O_o; wire wire_nl0Ol1i_o; wire wire_nl0Ol1l_o; wire wire_nl0Ol1O_o; wire wire_nl0Olii_o; wire wire_nl0Olil_o; wire wire_nl0OliO_o; wire wire_nl0Olli_o; wire wire_nl0Olll_o; wire wire_nl0OllO_o; wire wire_nl0OlOi_o; wire wire_nl0OlOl_o; wire wire_nl0OlOO_o; wire wire_nl0OO1i_o; wire wire_nl0OO1l_o; wire wire_nl0OO1O_o; wire wire_nl100i_o; wire wire_nl101i_o; wire wire_nl101l_o; wire wire_nl101O_o; wire wire_nl11li_o; wire wire_nl11ll_o; wire wire_nl11lO_o; wire wire_nl11Oi_o; wire wire_nl11Ol_o; wire wire_nl11OO_o; wire wire_nl1liiO_o; wire wire_nl1lili_o; wire wire_nl1lill_o; wire wire_nl1lilO_o; wire wire_nl1liOi_o; wire wire_nl1liOl_o; wire wire_nl1liOO_o; wire wire_nl1ll0i_o; wire wire_nl1ll0l_o; wire wire_nl1ll0O_o; wire wire_nl1ll1i_o; wire wire_nl1ll1l_o; wire wire_nl1ll1O_o; wire wire_nl1llii_o; wire wire_nl1llil_o; wire wire_nl1lliO_o; wire wire_nl1llli_o; wire wire_nl1llll_o; wire wire_nl1lllO_o; wire wire_nl1llOi_o; wire wire_nl1llOl_o; wire wire_nl1llOO_o; wire wire_nl1lO0i_o; wire wire_nl1lO0l_o; wire wire_nl1lO0O_o; wire wire_nl1lO1i_o; wire wire_nl1lO1l_o; wire wire_nl1lO1O_o; wire wire_nl1lOii_o; wire wire_nl1lOil_o; wire wire_nl1lOiO_o; wire wire_nl1lOli_o; wire wire_nl1lOll_o; wire wire_nl1lOlO_o; wire wire_nl1lOOi_o; wire wire_nl1lOOl_o; wire wire_nl1lOOO_o; wire wire_nl1O00i_o; wire wire_nl1O01i_o; wire wire_nl1O01l_o; wire wire_nl1O01O_o; wire wire_nl1O10i_o; wire wire_nl1O10l_o; wire wire_nl1O10O_o; wire wire_nl1O11i_o; wire wire_nl1O11l_o; wire wire_nl1O11O_o; wire wire_nl1O1ii_o; wire wire_nl1O1il_o; wire wire_nl1O1iO_o; wire wire_nl1O1li_o; wire wire_nl1O1ll_o; wire wire_nl1O1lO_o; wire wire_nl1O1Oi_o; wire wire_nl1O1Ol_o; wire wire_nl1O1OO_o; wire wire_nllO0iO_o; wire wire_nllO0li_o; wire wire_nllO0ll_o; wire wire_nllO0lO_o; wire wire_nllO0Oi_o; wire wire_nllO0Ol_o; wire wire_nllO0OO_o; wire wire_nllOi1i_o; wire wire_nlO0O0i_o; wire wire_nlO0OiO_o; wire wire_nlO0OOl_o; wire wire_nlOi00i_o; wire wire_nlOi0iO_o; wire wire_nlOi10i_o; wire wire_nlOi1iO_o; wire wire_nlOi1Ol_o; wire wire_n1lili_o; wire wire_n1lill_o; wire wire_n1lilO_o; wire wire_n1liOi_o; wire wire_n1liOO_o; wire wire_n1ll0O_o; wire wire_n1ll1i_o; wire wire_n1ll1l_o; wire wire_n1ll1O_o; wire wire_n1llil_o; wire wire_n1llli_o; wire wire_n1lllO_o; wire wire_n1Oliii_o; wire wire_n1Oliil_o; wire wire_n1OliiO_o; wire wire_n1Olili_o; wire wire_n1Olill_o; wire wire_n1OliOi_o; wire wire_n1OliOl_o; wire wire_n1OliOO_o; wire wire_n1Oll0l_o; wire wire_n1Oll1i_o; wire wire_n1Oll1l_o; wire wire_n1Ollii_o; wire wire_n1OlliO_o; wire wire_n1Ollll_o; wire wire_niO00i_o; wire wire_niO00l_o; wire wire_niO00O_o; wire wire_niO01i_o; wire wire_niO01l_o; wire wire_niO01O_o; wire wire_niO1Ol_o; wire wire_niO1OO_o; wire wire_niOill_o; wire wire_niOilO_o; wire wire_niOiOi_o; wire wire_niOiOl_o; wire wire_niOiOO_o; wire wire_niOl1i_o; wire wire_niOl1l_o; wire wire_niOl1O_o; wire wire_nll1llO_o; wire wire_nll1lOO_o; wire wire_nll1O1i_o; wire wire_nlll0i_o; wire wire_nlll1i_o; wire wire_nlll1l_o; wire wire_nlll1O_o; wire wire_nllll0i_o; wire wire_nllll0l_o; wire wire_nllll0O_o; wire wire_nllll1l_o; wire wire_nllll1O_o; wire wire_nllllii_o; wire wire_nllllil_o; wire wire_nlllliO_o; wire wire_nllllli_o; wire wire_nllllll_o; wire wire_nllllOl_o; wire wire_nllllOO_o; wire wire_nlllO0i_o; wire wire_nlllO0l_o; wire wire_nlllO0O_o; wire wire_nlllO1i_o; wire wire_nlllO1l_o; wire wire_nlllO1O_o; wire wire_nlllOii_o; wire wire_nlllOil_o; wire wire_nlllOli_o; wire wire_nlllOOi_o; wire wire_nlllOOl_o; wire wire_nlllOOO_o; wire wire_nllO10i_o; wire wire_nllO10l_o; wire wire_nllO10O_o; wire wire_nllO11i_o; wire wire_nllO11l_o; wire wire_nllO11O_o; wire wire_nllO1ii_o; wire wire_nllO1iO_o; wire n10000i; wire n10000l; wire n10000O; wire n10001i; wire n10001l; wire n10001O; wire n1000ii; wire n1000il; wire n1000iO; wire n1000li; wire n1000ll; wire n1000lO; wire n1000Oi; wire n1000Ol; wire n1000OO; wire n10010i; wire n10010l; wire n10010O; wire n10011i; wire n10011l; wire n10011O; wire n1001ii; wire n1001il; wire n1001iO; wire n1001li; wire n1001ll; wire n1001lO; wire n1001Oi; wire n1001Ol; wire n1001OO; wire n100i0i; wire n100i0l; wire n100i0O; wire n100i1i; wire n100i1l; wire n100i1O; wire n100iii; wire n100iil; wire n100iiO; wire n100ili; wire n100ill; wire n100ilO; wire n100iOi; wire n100iOl; wire n100iOO; wire n100l0i; wire n100l0l; wire n100l0O; wire n100l1i; wire n100l1l; wire n100l1O; wire n100lii; wire n100lil; wire n100liO; wire n100lli; wire n100lll; wire n100llO; wire n100lOi; wire n100lOl; wire n100lOO; wire n100O0i; wire n100O0l; wire n100O0O; wire n100O1i; wire n100O1l; wire n100O1O; wire n100Oii; wire n100Oil; wire n100OiO; wire n100Oli; wire n100Oll; wire n100OlO; wire n100OOi; wire n100OOl; wire n100OOO; wire n10100i; wire n10100l; wire n10100O; wire n10101i; wire n10101l; wire n10101O; wire n1010ii; wire n1010il; wire n1010iO; wire n1010li; wire n1010ll; wire n1010lO; wire n1010Oi; wire n1010Ol; wire n1010OO; wire n10110i; wire n10110l; wire n10110O; wire n10111i; wire n10111l; wire n10111O; wire n1011ii; wire n1011il; wire n1011iO; wire n1011li; wire n1011ll; wire n1011lO; wire n1011Oi; wire n1011Ol; wire n1011OO; wire n101i0i; wire n101i0l; wire n101i0O; wire n101i1i; wire n101i1l; wire n101i1O; wire n101iii; wire n101iil; wire n101iiO; wire n101ili; wire n101ill; wire n101ilO; wire n101iOi; wire n101iOl; wire n101iOO; wire n101l0i; wire n101l0l; wire n101l0O; wire n101l1i; wire n101l1l; wire n101l1O; wire n101lii; wire n101lil; wire n101liO; wire n101lli; wire n101lll; wire n101llO; wire n101lOi; wire n101lOl; wire n101lOO; wire n101O0i; wire n101O0l; wire n101O0O; wire n101O1i; wire n101O1l; wire n101O1O; wire n101Oii; wire n101Oil; wire n101OiO; wire n101Oli; wire n101Oll; wire n101OlO; wire n101OOi; wire n101OOl; wire n101OOO; wire n10i00i; wire n10i00l; wire n10i00O; wire n10i01i; wire n10i01l; wire n10i01O; wire n10i0ii; wire n10i0il; wire n10i0iO; wire n10i0li; wire n10i0ll; wire n10i0lO; wire n10i0Oi; wire n10i0Ol; wire n10i0OO; wire n10i10i; wire n10i10l; wire n10i10O; wire n10i11i; wire n10i11l; wire n10i11O; wire n10i1ii; wire n10i1il; wire n10i1iO; wire n10i1li; wire n10i1ll; wire n10i1lO; wire n10i1Oi; wire n10i1Ol; wire n10i1OO; wire n10ii0i; wire n10ii0l; wire n10ii0O; wire n10ii1i; wire n10ii1l; wire n10ii1O; wire n10iiii; wire n10iiil; wire n10iiiO; wire n10iili; wire n10iill; wire n10iilO; wire n10iiOi; wire n10iiOl; wire n10iiOO; wire n10il0i; wire n10il0l; wire n10il0O; wire n10il1i; wire n10il1l; wire n10il1O; wire n10ilii; wire n10ilil; wire n10iliO; wire n10illi; wire n10illl; wire n10illO; wire n10ilOi; wire n10ilOl; wire n10ilOO; wire n10iO0i; wire n10iO0l; wire n10iO0O; wire n10iO1i; wire n10iO1l; wire n10iO1O; wire n10iOii; wire n10iOil; wire n10iOiO; wire n10iOli; wire n10iOll; wire n10iOlO; wire n10iOOi; wire n10iOOl; wire n10iOOO; wire n10l00i; wire n10l00l; wire n10l00O; wire n10l01i; wire n10l01l; wire n10l01O; wire n10l0ii; wire n10l0il; wire n10l0iO; wire n10l0li; wire n10l0ll; wire n10l0lO; wire n10l0Oi; wire n10l0Ol; wire n10l0OO; wire n10l10i; wire n10l10l; wire n10l10O; wire n10l11i; wire n10l11l; wire n10l11O; wire n10l1ii; wire n10l1il; wire n10l1iO; wire n10l1li; wire n10l1ll; wire n10l1lO; wire n10l1Oi; wire n10l1Ol; wire n10l1OO; wire n10li0i; wire n10li0l; wire n10li0O; wire n10li1i; wire n10li1l; wire n10li1O; wire n10liii; wire n10liil; wire n10liiO; wire n10lili; wire n10lill; wire n10lilO; wire n10liOi; wire n10liOl; wire n10liOO; wire n10ll0i; wire n10ll0l; wire n10ll0O; wire n10ll1i; wire n10ll1l; wire n10ll1O; wire n10llii; wire n10llil; wire n10lliO; wire n10llli; wire n10llll; wire n10lllO; wire n10llOi; wire n10llOl; wire n10llOO; wire n10lO0i; wire n10lO0l; wire n10lO0O; wire n10lO1i; wire n10lO1l; wire n10lO1O; wire n10lOii; wire n10lOil; wire n10lOiO; wire n10lOli; wire n10lOll; wire n10lOlO; wire n10lOOi; wire n10lOOl; wire n10lOOO; wire n10O00i; wire n10O00l; wire n10O00O; wire n10O01i; wire n10O01l; wire n10O01O; wire n10O0ii; wire n10O0il; wire n10O0iO; wire n10O0li; wire n10O0ll; wire n10O0lO; wire n10O0Oi; wire n10O0Ol; wire n10O0OO; wire n10O10i; wire n10O10l; wire n10O10O; wire n10O11i; wire n10O11l; wire n10O11O; wire n10O1ii; wire n10O1il; wire n10O1iO; wire n10O1li; wire n10O1ll; wire n10O1lO; wire n10O1Oi; wire n10O1Ol; wire n10O1OO; wire n10Oi0i; wire n10Oi0l; wire n10Oi0O; wire n10Oi1i; wire n10Oi1l; wire n10Oi1O; wire n10Oiii; wire n10Oiil; wire n10OiiO; wire n10Oili; wire n10Oill; wire n10OilO; wire n10OiOi; wire n10OiOl; wire n10OiOO; wire n10Ol0i; wire n10Ol0l; wire n10Ol0O; wire n10Ol1i; wire n10Ol1l; wire n10Ol1O; wire n10Olii; wire n10Olil; wire n10OliO; wire n10Olli; wire n10Olll; wire n10OllO; wire n10OlOi; wire n10OlOl; wire n10OlOO; wire n10OO0i; wire n10OO0l; wire n10OO0O; wire n10OO1i; wire n10OO1l; wire n10OO1O; wire n10OOii; wire n10OOil; wire n10OOiO; wire n10OOli; wire n10OOll; wire n10OOlO; wire n10OOOi; wire n10OOOl; wire n10OOOO; wire n11000i; wire n11000l; wire n11000O; wire n11001i; wire n11001l; wire n11001O; wire n1100ii; wire n1100il; wire n1100iO; wire n1100li; wire n1100ll; wire n1100lO; wire n1100Oi; wire n1100Ol; wire n1100OO; wire n11010i; wire n11010l; wire n11010O; wire n11011i; wire n11011l; wire n11011O; wire n1101ii; wire n1101il; wire n1101iO; wire n1101li; wire n1101ll; wire n1101lO; wire n1101Oi; wire n1101Ol; wire n1101OO; wire n110i0i; wire n110i0l; wire n110i0O; wire n110i1i; wire n110i1l; wire n110i1O; wire n110iii; wire n110iil; wire n110iiO; wire n110ili; wire n110ill; wire n110ilO; wire n110iOi; wire n110iOl; wire n110iOO; wire n110l0i; wire n110l0l; wire n110l0O; wire n110l1i; wire n110l1l; wire n110l1O; wire n110lii; wire n110lil; wire n110liO; wire n110lli; wire n110lll; wire n110llO; wire n110lOi; wire n110lOl; wire n110lOO; wire n110O0i; wire n110O0l; wire n110O0O; wire n110O1i; wire n110O1l; wire n110O1O; wire n110Oii; wire n110Oil; wire n110OiO; wire n110Oli; wire n110Oll; wire n110OlO; wire n110OOi; wire n110OOl; wire n110OOO; wire n11100i; wire n11100l; wire n11100O; wire n11101i; wire n11101l; wire n11101O; wire n1110ii; wire n1110il; wire n1110iO; wire n1110li; wire n1110ll; wire n1110lO; wire n1110Oi; wire n1110Ol; wire n1110OO; wire n11110i; wire n11110l; wire n11110O; wire n11111i; wire n11111l; wire n11111O; wire n1111ii; wire n1111il; wire n1111iO; wire n1111li; wire n1111ll; wire n1111lO; wire n1111Oi; wire n1111Ol; wire n1111OO; wire n111i0i; wire n111i0l; wire n111i0O; wire n111i1i; wire n111i1l; wire n111i1O; wire n111iii; wire n111iil; wire n111iiO; wire n111ili; wire n111ill; wire n111ilO; wire n111iOi; wire n111iOl; wire n111iOO; wire n111l0i; wire n111l0l; wire n111l0O; wire n111l1i; wire n111l1l; wire n111l1O; wire n111lii; wire n111lil; wire n111liO; wire n111lli; wire n111lll; wire n111llO; wire n111lOi; wire n111lOl; wire n111lOO; wire n111O0i; wire n111O0l; wire n111O0O; wire n111O1i; wire n111O1l; wire n111O1O; wire n111Oii; wire n111Oil; wire n111OiO; wire n111Oli; wire n111Oll; wire n111OlO; wire n111OOi; wire n111OOl; wire n111OOO; wire n11i00i; wire n11i00l; wire n11i00O; wire n11i01i; wire n11i01l; wire n11i01O; wire n11i0ii; wire n11i0il; wire n11i0iO; wire n11i0li; wire n11i0ll; wire n11i0lO; wire n11i0Oi; wire n11i0Ol; wire n11i0OO; wire n11i10i; wire n11i10l; wire n11i10O; wire n11i11i; wire n11i11l; wire n11i11O; wire n11i1ii; wire n11i1il; wire n11i1iO; wire n11i1li; wire n11i1ll; wire n11i1lO; wire n11i1Oi; wire n11i1Ol; wire n11i1OO; wire n11ii0i; wire n11ii0l; wire n11ii0O; wire n11ii1i; wire n11ii1l; wire n11ii1O; wire n11iiii; wire n11iiil; wire n11iiiO; wire n11iili; wire n11iill; wire n11iilO; wire n11iiOi; wire n11iiOl; wire n11iiOO; wire n11il0i; wire n11il0l; wire n11il0O; wire n11il1i; wire n11il1l; wire n11il1O; wire n11ilii; wire n11ilil; wire n11iliO; wire n11illi; wire n11illl; wire n11illO; wire n11ilOi; wire n11ilOl; wire n11ilOO; wire n11iO0i; wire n11iO0l; wire n11iO0O; wire n11iO1i; wire n11iO1l; wire n11iO1O; wire n11iOii; wire n11iOil; wire n11iOiO; wire n11iOli; wire n11iOll; wire n11iOlO; wire n11iOOi; wire n11iOOl; wire n11iOOO; wire n11l00i; wire n11l00l; wire n11l00O; wire n11l01i; wire n11l01l; wire n11l01O; wire n11l0ii; wire n11l0il; wire n11l0iO; wire n11l0li; wire n11l0ll; wire n11l0lO; wire n11l0Oi; wire n11l0Ol; wire n11l0OO; wire n11l10i; wire n11l10l; wire n11l10O; wire n11l11i; wire n11l11l; wire n11l11O; wire n11l1ii; wire n11l1il; wire n11l1iO; wire n11l1li; wire n11l1ll; wire n11l1lO; wire n11l1Oi; wire n11l1Ol; wire n11l1OO; wire n11li0i; wire n11li0l; wire n11li0O; wire n11li1i; wire n11li1l; wire n11li1O; wire n11liii; wire n11liil; wire n11liiO; wire n11lili; wire n11lill; wire n11lilO; wire n11liOi; wire n11liOl; wire n11liOO; wire n11ll0i; wire n11ll0l; wire n11ll0O; wire n11ll1i; wire n11ll1l; wire n11ll1O; wire n11llii; wire n11llil; wire n11lliO; wire n11llli; wire n11llll; wire n11lllO; wire n11llOi; wire n11llOl; wire n11llOO; wire n11lO0i; wire n11lO0l; wire n11lO0O; wire n11lO1i; wire n11lO1l; wire n11lO1O; wire n11lOii; wire n11lOil; wire n11lOiO; wire n11lOli; wire n11lOll; wire n11lOlO; wire n11lOOi; wire n11lOOl; wire n11lOOO; wire n11O00i; wire n11O00l; wire n11O00O; wire n11O01i; wire n11O01l; wire n11O01O; wire n11O0ii; wire n11O0il; wire n11O0iO; wire n11O0li; wire n11O0ll; wire n11O0lO; wire n11O0Oi; wire n11O0Ol; wire n11O0OO; wire n11O10i; wire n11O10l; wire n11O10O; wire n11O11i; wire n11O11l; wire n11O11O; wire n11O1ii; wire n11O1il; wire n11O1iO; wire n11O1li; wire n11O1ll; wire n11O1lO; wire n11O1Oi; wire n11O1Ol; wire n11O1OO; wire n11Oi0i; wire n11Oi0l; wire n11Oi0O; wire n11Oi1i; wire n11Oi1l; wire n11Oi1O; wire n11Oiii; wire n11Oiil; wire n11OiiO; wire n11Oili; wire n11Oill; wire n11OilO; wire n11OiOi; wire n11OiOl; wire n11OiOO; wire n11Ol0i; wire n11Ol0l; wire n11Ol0O; wire n11Ol1i; wire n11Ol1l; wire n11Ol1O; wire n11Olii; wire n11Olil; wire n11OliO; wire n11Olli; wire n11Olll; wire n11OllO; wire n11OlOi; wire n11OlOl; wire n11OlOO; wire n11OO0i; wire n11OO0l; wire n11OO0O; wire n11OO1i; wire n11OO1l; wire n11OO1O; wire n11OOii; wire n11OOil; wire n11OOiO; wire n11OOli; wire n11OOll; wire n11OOlO; wire n11OOOi; wire n11OOOl; wire n11OOOO; wire n1i000i; wire n1i000l; wire n1i000O; wire n1i001i; wire n1i001l; wire n1i001O; wire n1i00ii; wire n1i00il; wire n1i00iO; wire n1i00li; wire n1i00ll; wire n1i00lO; wire n1i00Oi; wire n1i00Ol; wire n1i010i; wire n1i010l; wire n1i010O; wire n1i011i; wire n1i011l; wire n1i011O; wire n1i01ii; wire n1i01il; wire n1i01iO; wire n1i01li; wire n1i01ll; wire n1i01lO; wire n1i01Oi; wire n1i01Ol; wire n1i01OO; wire n1i0i0i; wire n1i0i0l; wire n1i0i0O; wire n1i0i1i; wire n1i0i1l; wire n1i0i1O; wire n1i0iii; wire n1i0iil; wire n1i0iiO; wire n1i0ili; wire n1i0ill; wire n1i0ilO; wire n1i0iOi; wire n1i0iOl; wire n1i0iOO; wire n1i0l0i; wire n1i0l0l; wire n1i0l0O; wire n1i0l1i; wire n1i0l1l; wire n1i0l1O; wire n1i0lii; wire n1i0lil; wire n1i0liO; wire n1i0lli; wire n1i0lll; wire n1i0llO; wire n1i0lOO; wire n1i0O0O; wire n1i0O1i; wire n1i0Oii; wire n1i100i; wire n1i100l; wire n1i100O; wire n1i101i; wire n1i101l; wire n1i101O; wire n1i10ii; wire n1i10il; wire n1i10iO; wire n1i10li; wire n1i10ll; wire n1i10lO; wire n1i10Oi; wire n1i10Ol; wire n1i10OO; wire n1i110i; wire n1i110l; wire n1i110O; wire n1i111i; wire n1i111l; wire n1i111O; wire n1i11ii; wire n1i11il; wire n1i11iO; wire n1i11li; wire n1i11ll; wire n1i11lO; wire n1i11Oi; wire n1i11Ol; wire n1i11OO; wire n1i1i0i; wire n1i1i0l; wire n1i1i0O; wire n1i1i1i; wire n1i1i1l; wire n1i1i1O; wire n1i1iii; wire n1i1iil; wire n1i1iiO; wire n1i1ili; wire n1i1ill; wire n1i1ilO; wire n1i1iOi; wire n1i1iOl; wire n1i1iOO; wire n1i1l0i; wire n1i1l0l; wire n1i1l0O; wire n1i1l1i; wire n1i1l1l; wire n1i1l1O; wire n1i1lii; wire n1i1lil; wire n1i1liO; wire n1i1lli; wire n1i1lll; wire n1i1llO; wire n1i1lOi; wire n1i1lOl; wire n1i1lOO; wire n1i1O0i; wire n1i1O0l; wire n1i1O0O; wire n1i1O1i; wire n1i1O1l; wire n1i1O1O; wire n1i1Oii; wire n1i1Oil; wire n1i1OiO; wire n1i1Oli; wire n1i1Oll; wire n1i1OlO; wire n1i1OOi; wire n1i1OOl; wire n1i1OOO; wire n1ii00i; wire n1ii00l; wire n1ii01i; wire n1ii01l; wire n1ii01O; wire n1ii0iO; wire n1ii0li; wire n1ii0Oi; wire n1ii0Ol; wire n1ii10i; wire n1ii10O; wire n1ii11i; wire n1ii11l; wire n1ii11O; wire n1ii1lO; wire n1ii1OO; wire n1iii1i; wire n1iii1l; wire n1iii1O; wire n1iiili; wire n1iiill; wire n1iiilO; wire n1iiiOi; wire n1iil0i; wire nlOO000i; wire nlOO000l; wire nlOO000O; wire nlOO001i; wire nlOO001l; wire nlOO001O; wire nlOO00ii; wire nlOO00il; wire nlOO00iO; wire nlOO00li; wire nlOO00ll; wire nlOO00lO; wire nlOO00Oi; wire nlOO00Ol; wire nlOO00OO; wire nlOO010i; wire nlOO010l; wire nlOO010O; wire nlOO011i; wire nlOO011l; wire nlOO011O; wire nlOO01ii; wire nlOO01il; wire nlOO01iO; wire nlOO01li; wire nlOO01ll; wire nlOO01lO; wire nlOO01Oi; wire nlOO01Ol; wire nlOO01OO; wire nlOO0i0i; wire nlOO0i0l; wire nlOO0i0O; wire nlOO0i1i; wire nlOO0i1l; wire nlOO0i1O; wire nlOO0iii; wire nlOO0iil; wire nlOO0iiO; wire nlOO0ili; wire nlOO0ill; wire nlOO0ilO; wire nlOO0iOi; wire nlOO0iOl; wire nlOO0iOO; wire nlOO0l0i; wire nlOO0l0l; wire nlOO0l0O; wire nlOO0l1i; wire nlOO0l1l; wire nlOO0l1O; wire nlOO0lii; wire nlOO0lil; wire nlOO0liO; wire nlOO0lli; wire nlOO0lll; wire nlOO0llO; wire nlOO0lOi; wire nlOO0lOl; wire nlOO0lOO; wire nlOO0O0i; wire nlOO0O0l; wire nlOO0O0O; wire nlOO0O1i; wire nlOO0O1l; wire nlOO0O1O; wire nlOO0Oii; wire nlOO0Oil; wire nlOO0OiO; wire nlOO0Oli; wire nlOO0Oll; wire nlOO0OlO; wire nlOO0OOi; wire nlOO0OOl; wire nlOO0OOO; wire nlOO1iOl; wire nlOO1iOO; wire nlOO1l0i; wire nlOO1l0l; wire nlOO1l0O; wire nlOO1l1i; wire nlOO1l1l; wire nlOO1l1O; wire nlOO1lii; wire nlOO1lil; wire nlOO1liO; wire nlOO1lli; wire nlOO1lll; wire nlOO1llO; wire nlOO1lOi; wire nlOO1lOl; wire nlOO1lOO; wire nlOO1O0i; wire nlOO1O0l; wire nlOO1O0O; wire nlOO1O1i; wire nlOO1O1l; wire nlOO1O1O; wire nlOO1Oii; wire nlOO1Oil; wire nlOO1OiO; wire nlOO1Oli; wire nlOO1Oll; wire nlOO1OlO; wire nlOO1OOi; wire nlOO1OOl; wire nlOO1OOO; wire nlOOi00i; wire nlOOi00l; wire nlOOi00O; wire nlOOi01i; wire nlOOi01l; wire nlOOi01O; wire nlOOi0ii; wire nlOOi0il; wire nlOOi0iO; wire nlOOi0li; wire nlOOi0ll; wire nlOOi0lO; wire nlOOi0Oi; wire nlOOi0Ol; wire nlOOi0OO; wire nlOOi10i; wire nlOOi10l; wire nlOOi10O; wire nlOOi11i; wire nlOOi11l; wire nlOOi11O; wire nlOOi1ii; wire nlOOi1il; wire nlOOi1iO; wire nlOOi1li; wire nlOOi1ll; wire nlOOi1lO; wire nlOOi1Oi; wire nlOOi1Ol; wire nlOOi1OO; wire nlOOii0i; wire nlOOii0l; wire nlOOii0O; wire nlOOii1i; wire nlOOii1l; wire nlOOii1O; wire nlOOiiii; wire nlOOiiil; wire nlOOiiiO; wire nlOOiili; wire nlOOiill; wire nlOOiilO; wire nlOOiiOi; wire nlOOiiOl; wire nlOOiiOO; wire nlOOil0i; wire nlOOil0l; wire nlOOil0O; wire nlOOil1i; wire nlOOil1l; wire nlOOil1O; wire nlOOilii; wire nlOOilil; wire nlOOiliO; wire nlOOilli; wire nlOOilll; wire nlOOillO; wire nlOOilOi; wire nlOOilOl; wire nlOOilOO; wire nlOOiO0i; wire nlOOiO0l; wire nlOOiO0O; wire nlOOiO1i; wire nlOOiO1l; wire nlOOiO1O; wire nlOOiOii; wire nlOOiOil; wire nlOOiOiO; wire nlOOiOli; wire nlOOiOll; wire nlOOiOlO; wire nlOOiOOi; wire nlOOiOOl; wire nlOOiOOO; wire nlOOl00i; wire nlOOl00l; wire nlOOl00O; wire nlOOl01i; wire nlOOl01l; wire nlOOl01O; wire nlOOl0ii; wire nlOOl0il; wire nlOOl0iO; wire nlOOl0li; wire nlOOl0ll; wire nlOOl0lO; wire nlOOl0Oi; wire nlOOl0Ol; wire nlOOl0OO; wire nlOOl10i; wire nlOOl10l; wire nlOOl10O; wire nlOOl11i; wire nlOOl11l; wire nlOOl11O; wire nlOOl1ii; wire nlOOl1il; wire nlOOl1iO; wire nlOOl1li; wire nlOOl1ll; wire nlOOl1lO; wire nlOOl1Oi; wire nlOOl1Ol; wire nlOOl1OO; wire nlOOli0i; wire nlOOli0l; wire nlOOli0O; wire nlOOli1i; wire nlOOli1l; wire nlOOli1O; wire nlOOliii; wire nlOOliil; wire nlOOliiO; wire nlOOlili; wire nlOOlill; wire nlOOlilO; wire nlOOliOi; wire nlOOliOl; wire nlOOliOO; wire nlOOll0i; wire nlOOll0l; wire nlOOll0O; wire nlOOll1i; wire nlOOll1l; wire nlOOll1O; wire nlOOllii; wire nlOOllil; wire nlOOlliO; wire nlOOllli; wire nlOOllll; wire nlOOlllO; wire nlOOllOi; wire nlOOllOl; wire nlOOllOO; wire nlOOlO0i; wire nlOOlO0l; wire nlOOlO0O; wire nlOOlO1i; wire nlOOlO1l; wire nlOOlO1O; wire nlOOlOii; wire nlOOlOil; wire nlOOlOiO; wire nlOOlOli; wire nlOOlOll; wire nlOOlOlO; wire nlOOlOOi; wire nlOOlOOl; wire nlOOlOOO; wire nlOOO00i; wire nlOOO00l; wire nlOOO00O; wire nlOOO01i; wire nlOOO01l; wire nlOOO01O; wire nlOOO0ii; wire nlOOO0il; wire nlOOO0iO; wire nlOOO0li; wire nlOOO0ll; wire nlOOO0lO; wire nlOOO0Oi; wire nlOOO0Ol; wire nlOOO0OO; wire nlOOO10i; wire nlOOO10l; wire nlOOO10O; wire nlOOO11i; wire nlOOO11l; wire nlOOO11O; wire nlOOO1ii; wire nlOOO1il; wire nlOOO1iO; wire nlOOO1li; wire nlOOO1ll; wire nlOOO1lO; wire nlOOO1Oi; wire nlOOO1Ol; wire nlOOO1OO; wire nlOOOi0i; wire nlOOOi0l; wire nlOOOi0O; wire nlOOOi1i; wire nlOOOi1l; wire nlOOOi1O; wire nlOOOiii; wire nlOOOiil; wire nlOOOiiO; wire nlOOOili; wire nlOOOill; wire nlOOOilO; wire nlOOOiOi; wire nlOOOiOl; wire nlOOOiOO; wire nlOOOl0i; wire nlOOOl0l; wire nlOOOl0O; wire nlOOOl1i; wire nlOOOl1l; wire nlOOOl1O; wire nlOOOlii; wire nlOOOlil; wire nlOOOliO; wire nlOOOlli; wire nlOOOlll; wire nlOOOllO; wire nlOOOlOi; wire nlOOOlOl; wire nlOOOlOO; wire nlOOOO0i; wire nlOOOO0l; wire nlOOOO0O; wire nlOOOO1i; wire nlOOOO1l; wire nlOOOO1O; wire nlOOOOii; wire nlOOOOil; wire nlOOOOiO; wire nlOOOOli; wire nlOOOOll; wire nlOOOOlO; wire nlOOOOOi; wire nlOOOOOl; wire nlOOOOOO; initial n1i00OO49 = 0; always @ ( posedge clk) n1i00OO49 <= n1i00OO50; event n1i00OO49_event; initial #1 ->n1i00OO49_event; always @(n1i00OO49_event) n1i00OO49 <= {1{1'b1}}; initial n1i00OO50 = 0; always @ ( posedge clk) n1i00OO50 <= n1i00OO49; initial n1i0lOi47 = 0; always @ ( posedge clk) n1i0lOi47 <= n1i0lOi48; event n1i0lOi47_event; initial #1 ->n1i0lOi47_event; always @(n1i0lOi47_event) n1i0lOi47 <= {1{1'b1}}; initial n1i0lOi48 = 0; always @ ( posedge clk) n1i0lOi48 <= n1i0lOi47; initial n1i0O0i43 = 0; always @ ( posedge clk) n1i0O0i43 <= n1i0O0i44; event n1i0O0i43_event; initial #1 ->n1i0O0i43_event; always @(n1i0O0i43_event) n1i0O0i43 <= {1{1'b1}}; initial n1i0O0i44 = 0; always @ ( posedge clk) n1i0O0i44 <= n1i0O0i43; initial n1i0O1l45 = 0; always @ ( posedge clk) n1i0O1l45 <= n1i0O1l46; event n1i0O1l45_event; initial #1 ->n1i0O1l45_event; always @(n1i0O1l45_event) n1i0O1l45 <= {1{1'b1}}; initial n1i0O1l46 = 0; always @ ( posedge clk) n1i0O1l46 <= n1i0O1l45; initial n1i0Oil41 = 0; always @ ( posedge clk) n1i0Oil41 <= n1i0Oil42; event n1i0Oil41_event; initial #1 ->n1i0Oil41_event; always @(n1i0Oil41_event) n1i0Oil41 <= {1{1'b1}}; initial n1i0Oil42 = 0; always @ ( posedge clk) n1i0Oil42 <= n1i0Oil41; initial n1i0Oli39 = 0; always @ ( posedge clk) n1i0Oli39 <= n1i0Oli40; event n1i0Oli39_event; initial #1 ->n1i0Oli39_event; always @(n1i0Oli39_event) n1i0Oli39 <= {1{1'b1}}; initial n1i0Oli40 = 0; always @ ( posedge clk) n1i0Oli40 <= n1i0Oli39; initial n1i0OlO37 = 0; always @ ( posedge clk) n1i0OlO37 <= n1i0OlO38; event n1i0OlO37_event; initial #1 ->n1i0OlO37_event; always @(n1i0OlO37_event) n1i0OlO37 <= {1{1'b1}}; initial n1i0OlO38 = 0; always @ ( posedge clk) n1i0OlO38 <= n1i0OlO37; initial n1i0OOl35 = 0; always @ ( posedge clk) n1i0OOl35 <= n1i0OOl36; event n1i0OOl35_event; initial #1 ->n1i0OOl35_event; always @(n1i0OOl35_event) n1i0OOl35 <= {1{1'b1}}; initial n1i0OOl36 = 0; always @ ( posedge clk) n1i0OOl36 <= n1i0OOl35; initial n1ii00O19 = 0; always @ ( posedge clk) n1ii00O19 <= n1ii00O20; event n1ii00O19_event; initial #1 ->n1ii00O19_event; always @(n1ii00O19_event) n1ii00O19 <= {1{1'b1}}; initial n1ii00O20 = 0; always @ ( posedge clk) n1ii00O20 <= n1ii00O19; initial n1ii0ii17 = 0; always @ ( posedge clk) n1ii0ii17 <= n1ii0ii18; event n1ii0ii17_event; initial #1 ->n1ii0ii17_event; always @(n1ii0ii17_event) n1ii0ii17 <= {1{1'b1}}; initial n1ii0ii18 = 0; always @ ( posedge clk) n1ii0ii18 <= n1ii0ii17; initial n1ii0ll15 = 0; always @ ( posedge clk) n1ii0ll15 <= n1ii0ll16; event n1ii0ll15_event; initial #1 ->n1ii0ll15_event; always @(n1ii0ll15_event) n1ii0ll15 <= {1{1'b1}}; initial n1ii0ll16 = 0; always @ ( posedge clk) n1ii0ll16 <= n1ii0ll15; initial n1ii0OO13 = 0; always @ ( posedge clk) n1ii0OO13 <= n1ii0OO14; event n1ii0OO13_event; initial #1 ->n1ii0OO13_event; always @(n1ii0OO13_event) n1ii0OO13 <= {1{1'b1}}; initial n1ii0OO14 = 0; always @ ( posedge clk) n1ii0OO14 <= n1ii0OO13; initial n1ii10l33 = 0; always @ ( posedge clk) n1ii10l33 <= n1ii10l34; event n1ii10l33_event; initial #1 ->n1ii10l33_event; always @(n1ii10l33_event) n1ii10l33 <= {1{1'b1}}; initial n1ii10l34 = 0; always @ ( posedge clk) n1ii10l34 <= n1ii10l33; initial n1ii1ii31 = 0; always @ ( posedge clk) n1ii1ii31 <= n1ii1ii32; event n1ii1ii31_event; initial #1 ->n1ii1ii31_event; always @(n1ii1ii31_event) n1ii1ii31 <= {1{1'b1}}; initial n1ii1ii32 = 0; always @ ( posedge clk) n1ii1ii32 <= n1ii1ii31; initial n1ii1il29 = 0; always @ ( posedge clk) n1ii1il29 <= n1ii1il30; event n1ii1il29_event; initial #1 ->n1ii1il29_event; always @(n1ii1il29_event) n1ii1il29 <= {1{1'b1}}; initial n1ii1il30 = 0; always @ ( posedge clk) n1ii1il30 <= n1ii1il29; initial n1ii1iO27 = 0; always @ ( posedge clk) n1ii1iO27 <= n1ii1iO28; event n1ii1iO27_event; initial #1 ->n1ii1iO27_event; always @(n1ii1iO27_event) n1ii1iO27 <= {1{1'b1}}; initial n1ii1iO28 = 0; always @ ( posedge clk) n1ii1iO28 <= n1ii1iO27; initial n1ii1li25 = 0; always @ ( posedge clk) n1ii1li25 <= n1ii1li26; event n1ii1li25_event; initial #1 ->n1ii1li25_event; always @(n1ii1li25_event) n1ii1li25 <= {1{1'b1}}; initial n1ii1li26 = 0; always @ ( posedge clk) n1ii1li26 <= n1ii1li25; initial n1ii1ll23 = 0; always @ ( posedge clk) n1ii1ll23 <= n1ii1ll24; event n1ii1ll23_event; initial #1 ->n1ii1ll23_event; always @(n1ii1ll23_event) n1ii1ll23 <= {1{1'b1}}; initial n1ii1ll24 = 0; always @ ( posedge clk) n1ii1ll24 <= n1ii1ll23; initial n1ii1Oi21 = 0; always @ ( posedge clk) n1ii1Oi21 <= n1ii1Oi22; event n1ii1Oi21_event; initial #1 ->n1ii1Oi21_event; always @(n1ii1Oi21_event) n1ii1Oi21 <= {1{1'b1}}; initial n1ii1Oi22 = 0; always @ ( posedge clk) n1ii1Oi22 <= n1ii1Oi21; initial n1iii0i11 = 0; always @ ( posedge clk) n1iii0i11 <= n1iii0i12; event n1iii0i11_event; initial #1 ->n1iii0i11_event; always @(n1iii0i11_event) n1iii0i11 <= {1{1'b1}}; initial n1iii0i12 = 0; always @ ( posedge clk) n1iii0i12 <= n1iii0i11; initial n1iii0O10 = 0; always @ ( posedge clk) n1iii0O10 <= n1iii0O9; initial n1iii0O9 = 0; always @ ( posedge clk) n1iii0O9 <= n1iii0O10; event n1iii0O9_event; initial #1 ->n1iii0O9_event; always @(n1iii0O9_event) n1iii0O9 <= {1{1'b1}}; initial n1iiiil7 = 0; always @ ( posedge clk) n1iiiil7 <= n1iiiil8; event n1iiiil7_event; initial #1 ->n1iiiil7_event; always @(n1iiiil7_event) n1iiiil7 <= {1{1'b1}}; initial n1iiiil8 = 0; always @ ( posedge clk) n1iiiil8 <= n1iiiil7; initial n1iiiOl5 = 0; always @ ( posedge clk) n1iiiOl5 <= n1iiiOl6; event n1iiiOl5_event; initial #1 ->n1iiiOl5_event; always @(n1iiiOl5_event) n1iiiOl5 <= {1{1'b1}}; initial n1iiiOl6 = 0; always @ ( posedge clk) n1iiiOl6 <= n1iiiOl5; initial n1iil0O1 = 0; always @ ( posedge clk) n1iil0O1 <= n1iil0O2; event n1iil0O1_event; initial #1 ->n1iil0O1_event; always @(n1iil0O1_event) n1iil0O1 <= {1{1'b1}}; initial n1iil0O2 = 0; always @ ( posedge clk) n1iil0O2 <= n1iil0O1; initial n1iil1i3 = 0; always @ ( posedge clk) n1iil1i3 <= n1iil1i4; event n1iil1i3_event; initial #1 ->n1iil1i3_event; always @(n1iil1i3_event) n1iil1i3 <= {1{1'b1}}; initial n1iil1i4 = 0; always @ ( posedge clk) n1iil1i4 <= n1iil1i3; initial begin ni0li = 0; ni0Ol = 0; end always @ (clk or rst or wire_ni0Oi_CLRN) begin if (rst == 1'b1) begin ni0li <= 1; ni0Ol <= 1; end else if (wire_ni0Oi_CLRN == 1'b0) begin ni0li <= 0; ni0Ol <= 0; end else if (clk != ni0Oi_clk_prev && clk == 1'b1) begin ni0li <= ni0Ol; ni0Ol <= n1iii1i; end ni0Oi_clk_prev <= clk; end assign wire_ni0Oi_CLRN = (n1ii0OO14 ^ n1ii0OO13); event ni0li_event; event ni0Ol_event; initial #1 ->ni0li_event; initial #1 ->ni0Ol_event; always @(ni0li_event) ni0li <= 1; always @(ni0Ol_event) ni0Ol <= 1; initial begin n01000i = 0; n01000l = 0; n01000O = 0; n01001i = 0; n01001l = 0; n01001O = 0; n0100ii = 0; n0100il = 0; n0101il = 0; n0101iO = 0; n0101li = 0; n0101ll = 0; n0101lO = 0; n0101Oi = 0; n0101Ol = 0; n0101OO = 0; n010Ol = 0; n010OO = 0; n0110i = 0; n0110l = 0; n0110O = 0; n0111i = 0; n0111l = 0; n0111O = 0; n011ii = 0; n011il = 0; n011iO = 0; n011l0i = 0; n011l0l = 0; n011l0O = 0; n011l1l = 0; n011l1O = 0; n011li = 0; n011lii = 0; n011lil = 0; n011liO = 0; n011ll = 0; n011lli = 0; n011lll = 0; n011llO = 0; n011lO = 0; n011lOi = 0; n011lOl = 0; n011lOO = 0; n011O0i = 0; n011O1i = 0; n011O1l = 0; n011O1O = 0; n011Oi = 0; n01i0i = 0; n01i0l = 0; n01i0O = 0; n01i1i = 0; n01i1l = 0; n01i1O = 0; n01iii = 0; n01iil = 0; n01iiO = 0; n01ili = 0; n01ill = 0; n1l00O = 0; n1l0ii = 0; n1l0il = 0; n1l0iO = 0; n1l0li = 0; n1l0ll = 0; n1l0lO = 0; n1l0Oi = 0; n1liii = 0; n1O01i = 0; n1O01O = 0; n1O1ll = 0; n1O1lO = 0; n1O1Oi = 0; n1O1Ol = 0; n1O1OO = 0; n1Oi0i = 0; n1Oi0l = 0; n1Oi0O = 0; n1Oi1O = 0; n1OilO = 0; n1OiOi = 0; n1OiOl = 0; n1OiOO = 0; n1Ol00i = 0; n1Ol00l = 0; n1Ol00O = 0; n1Ol01i = 0; n1Ol01l = 0; n1Ol01O = 0; n1Ol0ii = 0; n1Ol0il = 0; n1Ol1Ol = 0; n1Ol1OO = 0; n1Oli0i = 0; n1OO00i = 0; n1OO01i = 0; n1OO01l = 0; n1OO0iO = 0; n1OO0li = 0; n1OO0ll = 0; n1OO0lO = 0; n1OO1lO = 0; n1OO1Oi = 0; n1OO1Ol = 0; n1OO1OO = 0; n1OOi0i = 0; n1OOi1O = 0; n1OOOl = 0; n1OOOO = 0; ni0iO = 0; ni0OO = 0; niii0i = 0; niii0l = 0; niii0O = 0; niiill = 0; nil00i = 0; nil00l = 0; nil00O = 0; nil01i = 0; nil01l = 0; nil01O = 0; nil0ii = 0; nil0il = 0; nil0iO = 0; nil0li = 0; nil0ll = 0; nil0lO = 0; nil0Oi = 0; nil0Ol = 0; nil0OO = 0; nil1il = 0; nil1iO = 0; nil1li = 0; nil1ll = 0; nil1lO = 0; nil1Ol = 0; nil1OO = 0; nili0i = 0; nili0l = 0; nili0O = 0; nili1i = 0; nili1l = 0; nili1O = 0; niliii = 0; niliil = 0; niliiO = 0; nilili = 0; nilill = 0; nililO = 0; niliOi = 0; niliOl = 0; niliOO = 0; nill0i = 0; nill0l = 0; nill1i = 0; nill1l = 0; nill1O = 0; niOlii = 0; niOlil = 0; niOlli = 0; niOlll = 0; niOllO = 0; niOlOi = 0; niOlOl = 0; niOlOO = 0; niOO0i = 0; niOO1i = 0; niOO1l = 0; niOO1O = 0; niOOOO = 0; nl010il = 0; nl010iO = 0; nl010li = 0; nl010ll = 0; nl010lO = 0; nl010Oi = 0; nl010Ol = 0; nl010OO = 0; nl0110i = 0; nl0110l = 0; nl0110O = 0; nl0111i = 0; nl0111l = 0; nl0111O = 0; nl011ii = 0; nl011il = 0; nl011iO = 0; nl011li = 0; nl011ll = 0; nl011lO = 0; nl01i0i = 0; nl01i0l = 0; nl01i0O = 0; nl01i1i = 0; nl01i1l = 0; nl01i1O = 0; nl01iii = 0; nl01iil = 0; nl01iiO = 0; nl01ili = 0; nl01ill = 0; nl01ilO = 0; nl01iOi = 0; nl01iOl = 0; nl01iOO = 0; nl01l0i = 0; nl01l0l = 0; nl01l0O = 0; nl01l1i = 0; nl01l1l = 0; nl01l1O = 0; nl01lii = 0; nl01lil = 0; nl01liO = 0; nl01lli = 0; nl01lll = 0; nl01llO = 0; nl01lOi = 0; nl01lOl = 0; nl01lOO = 0; nl01O1i = 0; nl01O1l = 0; nl01O1O = 0; nl100l = 0; nl100O = 0; nl10ii = 0; nl10Ol = 0; nl110i = 0; nl110l = 0; nl110O = 0; nl111i = 0; nl111l = 0; nl111O = 0; nl11ii = 0; nl11il = 0; nl11iO = 0; nl1ill = 0; nl1ilO = 0; nl1l1l = 0; nl1lii = 0; nl1liii = 0; nl1liil = 0; nl1lOi = 0; nl1Oiil = 0; nl1OiiO = 0; nl1Oili = 0; nl1Oill = 0; nl1OilO = 0; nl1OiOi = 0; nl1OiOl = 0; nl1OiOO = 0; nl1Ol0i = 0; nl1Ol0l = 0; nl1Ol0O = 0; nl1Ol1i = 0; nl1Ol1l = 0; nl1Ol1O = 0; nl1Olii = 0; nl1Olil = 0; nl1OliO = 0; nl1Olli = 0; nl1Olll = 0; nl1OllO = 0; nl1OlOi = 0; nl1OlOl = 0; nl1OlOO = 0; nl1OO0i = 0; nl1OO0l = 0; nl1OO0O = 0; nl1OO1i = 0; nl1OO1l = 0; nl1OO1O = 0; nl1OOii = 0; nl1OOil = 0; nl1OOiO = 0; nl1OOli = 0; nl1OOll = 0; nl1OOlO = 0; nl1OOOi = 0; nl1OOOl = 0; nl1OOOO = 0; nliiOl = 0; nliiOO = 0; nlil0i = 0; nlil0l = 0; nlil0O = 0; nlil1i = 0; nlil1l = 0; nlil1O = 0; nlilii = 0; nlilll = 0; nlillO = 0; nlilOi = 0; nlilOl = 0; nlilOO = 0; nliO0i = 0; nliO0l = 0; nliO0O = 0; nliO1i = 0; nliO1l = 0; nliO1O = 0; nliOii = 0; nliOil = 0; nliOiO = 0; nliOli = 0; nliOll = 0; nliOlO = 0; nliOOi = 0; nliOOl = 0; nliOOO = 0; nll000i = 0; nll000l = 0; nll000O = 0; nll001i = 0; nll001l = 0; nll001O = 0; nll00ii = 0; nll00il = 0; nll00iO = 0; nll00li = 0; nll00ll = 0; nll00lO = 0; nll00Oi = 0; nll00Ol = 0; nll00OO = 0; nll01ll = 0; nll01lO = 0; nll01Oi = 0; nll01Ol = 0; nll01OO = 0; nll0i0i = 0; nll0i0l = 0; nll0i0O = 0; nll0i1i = 0; nll0i1l = 0; nll0i1O = 0; nll0iii = 0; nll0iil = 0; nll0iiO = 0; nll0ili = 0; nll0ill = 0; nll0ilO = 0; nll0iOi = 0; nll0iOl = 0; nll0iOO = 0; nll0l0i = 0; nll0l0l = 0; nll0l0O = 0; nll0l1i = 0; nll0l1l = 0; nll0l1O = 0; nll0lii = 0; nll0lil = 0; nll0liO = 0; nll0lli = 0; nll0lll = 0; nll0llO = 0; nll0lOi = 0; nll0lOl = 0; nll0lOO = 0; nll0O0i = 0; nll0O0l = 0; nll0O0O = 0; nll0O1i = 0; nll0O1l = 0; nll0O1O = 0; nll0Oii = 0; nll0Oil = 0; nll0OiO = 0; nll0Oli = 0; nll0Oll = 0; nll0OlO = 0; nll0OOi = 0; nll0OOl = 0; nll0OOO = 0; nll10i = 0; nll11i = 0; nll11l = 0; nll11O = 0; nlli00i = 0; nlli00l = 0; nlli00O = 0; nlli01i = 0; nlli01l = 0; nlli01O = 0; nlli0ii = 0; nlli0il = 0; nlli0iO = 0; nlli0li = 0; nlli0ll = 0; nlli0lO = 0; nlli0Oi = 0; nlli0Ol = 0; nlli0OO = 0; nlli10i = 0; nlli10l = 0; nlli10O = 0; nlli11i = 0; nlli11l = 0; nlli11O = 0; nlli1ii = 0; nlli1il = 0; nlli1iO = 0; nlli1li = 0; nlli1ll = 0; nlli1lO = 0; nlli1Oi = 0; nlli1Ol = 0; nlli1OO = 0; nllii0i = 0; nllii0l = 0; nllii1i = 0; nllii1l = 0; nllii1O = 0; nllll1i = 0; nlllOl = 0; nlllOO = 0; nlO = 0; nlO000i = 0; nlO000l = 0; nlO000O = 0; nlO001i = 0; nlO001l = 0; nlO001O = 0; nlO00ii = 0; nlO00il = 0; nlO00iO = 0; nlO00li = 0; nlO00ll = 0; nlO00lO = 0; nlO00Oi = 0; nlO00Ol = 0; nlO00OO = 0; nlO010i = 0; nlO010l = 0; nlO011i = 0; nlO011l = 0; nlO011O = 0; nlO01ii = 0; nlO01il = 0; nlO01iO = 0; nlO01li = 0; nlO01ll = 0; nlO01lO = 0; nlO01Oi = 0; nlO01Ol = 0; nlO01OO = 0; nlO0i0i = 0; nlO0i0l = 0; nlO0i0O = 0; nlO0i1i = 0; nlO0i1l = 0; nlO0i1O = 0; nlO0iii = 0; nlO0iil = 0; nlO0iiO = 0; nlO0ili = 0; nlO0ill = 0; nlO0ilO = 0; nlO0l1i = 0; nlO0l1l = 0; nlO0l1O = 0; nlOi0ll = 0; nlOi0lO = 0; nlOi0Oi = 0; nlOi0Ol = 0; nlOi0OO = 0; nlOii0i = 0; nlOii0l = 0; nlOii0O = 0; nlOii1i = 0; nlOii1l = 0; nlOii1O = 0; nlOiiii = 0; nlOiiil = 0; nlOiiiO = 0; nlOiili = 0; nlOiill = 0; nlOiilO = 0; nlOilOl = 0; nlOilOO = 0; nlOiO0i = 0; nlOiO0l = 0; nlOiO1i = 0; nlOiO1l = 0; nlOiO1O = 0; nO = 0; end always @ ( posedge clk or negedge wire_nl_CLRN) begin if (wire_nl_CLRN == 1'b0) begin n01000i <= 0; n01000l <= 0; n01000O <= 0; n01001i <= 0; n01001l <= 0; n01001O <= 0; n0100ii <= 0; n0100il <= 0; n0101il <= 0; n0101iO <= 0; n0101li <= 0; n0101ll <= 0; n0101lO <= 0; n0101Oi <= 0; n0101Ol <= 0; n0101OO <= 0; n010Ol <= 0; n010OO <= 0; n0110i <= 0; n0110l <= 0; n0110O <= 0; n0111i <= 0; n0111l <= 0; n0111O <= 0; n011ii <= 0; n011il <= 0; n011iO <= 0; n011l0i <= 0; n011l0l <= 0; n011l0O <= 0; n011l1l <= 0; n011l1O <= 0; n011li <= 0; n011lii <= 0; n011lil <= 0; n011liO <= 0; n011ll <= 0; n011lli <= 0; n011lll <= 0; n011llO <= 0; n011lO <= 0; n011lOi <= 0; n011lOl <= 0; n011lOO <= 0; n011O0i <= 0; n011O1i <= 0; n011O1l <= 0; n011O1O <= 0; n011Oi <= 0; n01i0i <= 0; n01i0l <= 0; n01i0O <= 0; n01i1i <= 0; n01i1l <= 0; n01i1O <= 0; n01iii <= 0; n01iil <= 0; n01iiO <= 0; n01ili <= 0; n01ill <= 0; n1l00O <= 0; n1l0ii <= 0; n1l0il <= 0; n1l0iO <= 0; n1l0li <= 0; n1l0ll <= 0; n1l0lO <= 0; n1l0Oi <= 0; n1liii <= 0; n1O01i <= 0; n1O01O <= 0; n1O1ll <= 0; n1O1lO <= 0; n1O1Oi <= 0; n1O1Ol <= 0; n1O1OO <= 0; n1Oi0i <= 0; n1Oi0l <= 0; n1Oi0O <= 0; n1Oi1O <= 0; n1OilO <= 0; n1OiOi <= 0; n1OiOl <= 0; n1OiOO <= 0; n1Ol00i <= 0; n1Ol00l <= 0; n1Ol00O <= 0; n1Ol01i <= 0; n1Ol01l <= 0; n1Ol01O <= 0; n1Ol0ii <= 0; n1Ol0il <= 0; n1Ol1Ol <= 0; n1Ol1OO <= 0; n1Oli0i <= 0; n1OO00i <= 0; n1OO01i <= 0; n1OO01l <= 0; n1OO0iO <= 0; n1OO0li <= 0; n1OO0ll <= 0; n1OO0lO <= 0; n1OO1lO <= 0; n1OO1Oi <= 0; n1OO1Ol <= 0; n1OO1OO <= 0; n1OOi0i <= 0; n1OOi1O <= 0; n1OOOl <= 0; n1OOOO <= 0; ni0iO <= 0; ni0OO <= 0; niii0i <= 0; niii0l <= 0; niii0O <= 0; niiill <= 0; nil00i <= 0; nil00l <= 0; nil00O <= 0; nil01i <= 0; nil01l <= 0; nil01O <= 0; nil0ii <= 0; nil0il <= 0; nil0iO <= 0; nil0li <= 0; nil0ll <= 0; nil0lO <= 0; nil0Oi <= 0; nil0Ol <= 0; nil0OO <= 0; nil1il <= 0; nil1iO <= 0; nil1li <= 0; nil1ll <= 0; nil1lO <= 0; nil1Ol <= 0; nil1OO <= 0; nili0i <= 0; nili0l <= 0; nili0O <= 0; nili1i <= 0; nili1l <= 0; nili1O <= 0; niliii <= 0; niliil <= 0; niliiO <= 0; nilili <= 0; nilill <= 0; nililO <= 0; niliOi <= 0; niliOl <= 0; niliOO <= 0; nill0i <= 0; nill0l <= 0; nill1i <= 0; nill1l <= 0; nill1O <= 0; niOlii <= 0; niOlil <= 0; niOlli <= 0; niOlll <= 0; niOllO <= 0; niOlOi <= 0; niOlOl <= 0; niOlOO <= 0; niOO0i <= 0; niOO1i <= 0; niOO1l <= 0; niOO1O <= 0; niOOOO <= 0; nl010il <= 0; nl010iO <= 0; nl010li <= 0; nl010ll <= 0; nl010lO <= 0; nl010Oi <= 0; nl010Ol <= 0; nl010OO <= 0; nl0110i <= 0; nl0110l <= 0; nl0110O <= 0; nl0111i <= 0; nl0111l <= 0; nl0111O <= 0; nl011ii <= 0; nl011il <= 0; nl011iO <= 0; nl011li <= 0; nl011ll <= 0; nl011lO <= 0; nl01i0i <= 0; nl01i0l <= 0; nl01i0O <= 0; nl01i1i <= 0; nl01i1l <= 0; nl01i1O <= 0; nl01iii <= 0; nl01iil <= 0; nl01iiO <= 0; nl01ili <= 0; nl01ill <= 0; nl01ilO <= 0; nl01iOi <= 0; nl01iOl <= 0; nl01iOO <= 0; nl01l0i <= 0; nl01l0l <= 0; nl01l0O <= 0; nl01l1i <= 0; nl01l1l <= 0; nl01l1O <= 0; nl01lii <= 0; nl01lil <= 0; nl01liO <= 0; nl01lli <= 0; nl01lll <= 0; nl01llO <= 0; nl01lOi <= 0; nl01lOl <= 0; nl01lOO <= 0; nl01O1i <= 0; nl01O1l <= 0; nl01O1O <= 0; nl100l <= 0; nl100O <= 0; nl10ii <= 0; nl10Ol <= 0; nl110i <= 0; nl110l <= 0; nl110O <= 0; nl111i <= 0; nl111l <= 0; nl111O <= 0; nl11ii <= 0; nl11il <= 0; nl11iO <= 0; nl1ill <= 0; nl1ilO <= 0; nl1l1l <= 0; nl1lii <= 0; nl1liii <= 0; nl1liil <= 0; nl1lOi <= 0; nl1Oiil <= 0; nl1OiiO <= 0; nl1Oili <= 0; nl1Oill <= 0; nl1OilO <= 0; nl1OiOi <= 0; nl1OiOl <= 0; nl1OiOO <= 0; nl1Ol0i <= 0; nl1Ol0l <= 0; nl1Ol0O <= 0; nl1Ol1i <= 0; nl1Ol1l <= 0; nl1Ol1O <= 0; nl1Olii <= 0; nl1Olil <= 0; nl1OliO <= 0; nl1Olli <= 0; nl1Olll <= 0; nl1OllO <= 0; nl1OlOi <= 0; nl1OlOl <= 0; nl1OlOO <= 0; nl1OO0i <= 0; nl1OO0l <= 0; nl1OO0O <= 0; nl1OO1i <= 0; nl1OO1l <= 0; nl1OO1O <= 0; nl1OOii <= 0; nl1OOil <= 0; nl1OOiO <= 0; nl1OOli <= 0; nl1OOll <= 0; nl1OOlO <= 0; nl1OOOi <= 0; nl1OOOl <= 0; nl1OOOO <= 0; nliiOl <= 0; nliiOO <= 0; nlil0i <= 0; nlil0l <= 0; nlil0O <= 0; nlil1i <= 0; nlil1l <= 0; nlil1O <= 0; nlilii <= 0; nlilll <= 0; nlillO <= 0; nlilOi <= 0; nlilOl <= 0; nlilOO <= 0; nliO0i <= 0; nliO0l <= 0; nliO0O <= 0; nliO1i <= 0; nliO1l <= 0; nliO1O <= 0; nliOii <= 0; nliOil <= 0; nliOiO <= 0; nliOli <= 0; nliOll <= 0; nliOlO <= 0; nliOOi <= 0; nliOOl <= 0; nliOOO <= 0; nll000i <= 0; nll000l <= 0; nll000O <= 0; nll001i <= 0; nll001l <= 0; nll001O <= 0; nll00ii <= 0; nll00il <= 0; nll00iO <= 0; nll00li <= 0; nll00ll <= 0; nll00lO <= 0; nll00Oi <= 0; nll00Ol <= 0; nll00OO <= 0; nll01ll <= 0; nll01lO <= 0; nll01Oi <= 0; nll01Ol <= 0; nll01OO <= 0; nll0i0i <= 0; nll0i0l <= 0; nll0i0O <= 0; nll0i1i <= 0; nll0i1l <= 0; nll0i1O <= 0; nll0iii <= 0; nll0iil <= 0; nll0iiO <= 0; nll0ili <= 0; nll0ill <= 0; nll0ilO <= 0; nll0iOi <= 0; nll0iOl <= 0; nll0iOO <= 0; nll0l0i <= 0; nll0l0l <= 0; nll0l0O <= 0; nll0l1i <= 0; nll0l1l <= 0; nll0l1O <= 0; nll0lii <= 0; nll0lil <= 0; nll0liO <= 0; nll0lli <= 0; nll0lll <= 0; nll0llO <= 0; nll0lOi <= 0; nll0lOl <= 0; nll0lOO <= 0; nll0O0i <= 0; nll0O0l <= 0; nll0O0O <= 0; nll0O1i <= 0; nll0O1l <= 0; nll0O1O <= 0; nll0Oii <= 0; nll0Oil <= 0; nll0OiO <= 0; nll0Oli <= 0; nll0Oll <= 0; nll0OlO <= 0; nll0OOi <= 0; nll0OOl <= 0; nll0OOO <= 0; nll10i <= 0; nll11i <= 0; nll11l <= 0; nll11O <= 0; nlli00i <= 0; nlli00l <= 0; nlli00O <= 0; nlli01i <= 0; nlli01l <= 0; nlli01O <= 0; nlli0ii <= 0; nlli0il <= 0; nlli0iO <= 0; nlli0li <= 0; nlli0ll <= 0; nlli0lO <= 0; nlli0Oi <= 0; nlli0Ol <= 0; nlli0OO <= 0; nlli10i <= 0; nlli10l <= 0; nlli10O <= 0; nlli11i <= 0; nlli11l <= 0; nlli11O <= 0; nlli1ii <= 0; nlli1il <= 0; nlli1iO <= 0; nlli1li <= 0; nlli1ll <= 0; nlli1lO <= 0; nlli1Oi <= 0; nlli1Ol <= 0; nlli1OO <= 0; nllii0i <= 0; nllii0l <= 0; nllii1i <= 0; nllii1l <= 0; nllii1O <= 0; nllll1i <= 0; nlllOl <= 0; nlllOO <= 0; nlO <= 0; nlO000i <= 0; nlO000l <= 0; nlO000O <= 0; nlO001i <= 0; nlO001l <= 0; nlO001O <= 0; nlO00ii <= 0; nlO00il <= 0; nlO00iO <= 0; nlO00li <= 0; nlO00ll <= 0; nlO00lO <= 0; nlO00Oi <= 0; nlO00Ol <= 0; nlO00OO <= 0; nlO010i <= 0; nlO010l <= 0; nlO011i <= 0; nlO011l <= 0; nlO011O <= 0; nlO01ii <= 0; nlO01il <= 0; nlO01iO <= 0; nlO01li <= 0; nlO01ll <= 0; nlO01lO <= 0; nlO01Oi <= 0; nlO01Ol <= 0; nlO01OO <= 0; nlO0i0i <= 0; nlO0i0l <= 0; nlO0i0O <= 0; nlO0i1i <= 0; nlO0i1l <= 0; nlO0i1O <= 0; nlO0iii <= 0; nlO0iil <= 0; nlO0iiO <= 0; nlO0ili <= 0; nlO0ill <= 0; nlO0ilO <= 0; nlO0l1i <= 0; nlO0l1l <= 0; nlO0l1O <= 0; nlOi0ll <= 0; nlOi0lO <= 0; nlOi0Oi <= 0; nlOi0Ol <= 0; nlOi0OO <= 0; nlOii0i <= 0; nlOii0l <= 0; nlOii0O <= 0; nlOii1i <= 0; nlOii1l <= 0; nlOii1O <= 0; nlOiiii <= 0; nlOiiil <= 0; nlOiiiO <= 0; nlOiili <= 0; nlOiill <= 0; nlOiilO <= 0; nlOilOl <= 0; nlOilOO <= 0; nlOiO0i <= 0; nlOiO0l <= 0; nlOiO1i <= 0; nlOiO1l <= 0; nlOiO1O <= 0; nO <= 0; end else begin n01000i <= wire_n010i0O_dataout; n01000l <= wire_n010iii_dataout; n01000O <= wire_n010iil_dataout; n01001i <= wire_n010i1O_dataout; n01001l <= wire_n010i0i_dataout; n01001O <= wire_n010i0l_dataout; n0100ii <= wire_n010iiO_dataout; n0100il <= wire_n010ili_dataout; n0101il <= wire_n0100li_dataout; n0101iO <= wire_n0100ll_dataout; n0101li <= wire_n0100lO_dataout; n0101ll <= wire_n0100Oi_dataout; n0101lO <= wire_n0100Ol_dataout; n0101Oi <= wire_n0100OO_dataout; n0101Ol <= wire_n010i1i_dataout; n0101OO <= wire_n010i1l_dataout; n010Ol <= wire_n01iOi_dataout; n010OO <= wire_n01iOl_dataout; n0110i <= wire_n0100l_dataout; n0110l <= wire_n0100O_dataout; n0110O <= wire_n010ii_dataout; n0111i <= wire_n0101l_dataout; n0111l <= wire_n0101O_dataout; n0111O <= wire_n0100i_dataout; n011ii <= wire_n010il_dataout; n011il <= wire_n010iO_dataout; n011iO <= wire_n010li_dataout; n011l0i <= wire_n011Oil_dataout; n011l0l <= wire_n011OiO_dataout; n011l0O <= wire_n011Oli_dataout; n011l1l <= wire_n011O0O_dataout; n011l1O <= wire_n011Oii_dataout; n011li <= wire_n010ll_dataout; n011lii <= wire_n011Oll_dataout; n011lil <= wire_n011OlO_dataout; n011liO <= wire_n011OOi_dataout; n011ll <= wire_n010lO_dataout; n011lli <= wire_n011OOl_dataout; n011lll <= wire_n011OOO_dataout; n011llO <= wire_n01011i_dataout; n011lO <= wire_n010Oi_dataout; n011lOi <= wire_n01011l_dataout; n011lOl <= wire_n01011O_dataout; n011lOO <= wire_n01010i_dataout; n011O0i <= wire_n0100iO_dataout; n011O1i <= wire_n01010l_dataout; n011O1l <= wire_n01010O_dataout; n011O1O <= wire_n0101ii_dataout; n011Oi <= wire_n01ilO_dataout; n01i0i <= wire_n01l1O_dataout; n01i0l <= wire_n01l0i_dataout; n01i0O <= wire_n01l0l_dataout; n01i1i <= wire_n01iOO_dataout; n01i1l <= wire_n01l1i_dataout; n01i1O <= wire_n01l1l_dataout; n01iii <= wire_n01l0O_dataout; n01iil <= wire_n01lii_dataout; n01iiO <= wire_n01lil_dataout; n01ili <= wire_n01liO_dataout; n01ill <= wire_n01lli_dataout; n1l00O <= wire_n1li0i_o[1]; n1l0ii <= wire_n1li0i_o[2]; n1l0il <= wire_n1li0i_o[3]; n1l0iO <= wire_n1l0Ol_dataout; n1l0li <= wire_n1l0OO_dataout; n1l0ll <= wire_n1li1i_dataout; n1l0lO <= wire_n1li1l_dataout; n1l0Oi <= wire_n1ll0O_o; n1liii <= wire_n1li0i_o[0]; n1O01i <= wire_n1llOO_dataout; n1O01O <= wire_n1Oiii_dataout; n1O1ll <= wire_n1llil_o; n1O1lO <= wire_n1lliO_dataout; n1O1Oi <= wire_n1llli_o; n1O1Ol <= wire_n1lllO_o; n1O1OO <= wire_n1llOl_dataout; n1Oi0i <= wire_n1OiiO_dataout; n1Oi0l <= wire_n1Oili_dataout; n1Oi0O <= n1OilO; n1Oi1O <= wire_n1Oiil_dataout; n1OilO <= (n011Oi | n1OiOO); n1OiOi <= n1OiOl; n1OiOl <= rlv_en; n1OiOO <= wire_n011Ol_dataout; n1Ol00i <= wire_n1Ol0li_dataout; n1Ol00l <= wire_n1Ol0ll_dataout; n1Ol00O <= wire_n1Ol0lO_dataout; n1Ol01i <= wire_n1Ol0OO_o[3]; n1Ol01l <= wire_n1Ol0OO_o[4]; n1Ol01O <= wire_n1Ol0iO_dataout; n1Ol0ii <= wire_n1Ol0Oi_dataout; n1Ol0il <= wire_n1Oll0l_o; n1Ol1Ol <= wire_n1Ol0OO_o[1]; n1Ol1OO <= wire_n1Ol0OO_o[2]; n1Oli0i <= wire_n1Ol0OO_o[0]; n1OO00i <= wire_n1OO0Oi_dataout; n1OO01i <= wire_n1OllOi_dataout; n1OO01l <= wire_n1OllOl_dataout; n1OO0iO <= wire_n1OO0Ol_dataout; n1OO0li <= wire_n1OO0OO_dataout; n1OO0ll <= wire_n1OOi1i_dataout; n1OO0lO <= n1OOi1O; n1OO1lO <= wire_n1Ollii_o; n1OO1Oi <= wire_n1Ollil_dataout; n1OO1Ol <= wire_n1OlliO_o; n1OO1OO <= wire_n1Ollll_o; n1OOi0i <= wire_n011O0l_dataout; n1OOi1O <= (n011O0i | n1OOi0i); n1OOOl <= wire_n011OO_dataout; n1OOOO <= wire_n0101i_dataout; ni0iO <= (rpolinv_en & polinv_en); ni0OO <= nlO; niii0i <= wire_n110ll_dataout; niii0l <= (((n1i1Oil | n1i1Oii) & n1i1OOi) | (pmadwidth[0] & ((n1ii11O & wire_n1l1Ol_dataout) & (n1i1O0O | n1i1O0l)))); niii0O <= nil1li; niiill <= (((n1i1OlO | n1i1Oll) | ((~ wire_niOl0l_dataout) & ((~ wire_niOl0i_dataout) & ((~ wire_niOl1O_o) & n1i1Oli)))) | (wire_niOl0l_dataout & (wire_niOl0i_dataout & (wire_niOl1O_o & n1i1OiO)))); nil00i <= wire_nillOO_dataout; nil00l <= wire_nilO1i_dataout; nil00O <= wire_nilO1l_dataout; nil01i <= wire_nilllO_dataout; nil01l <= wire_nillOi_dataout; nil01O <= wire_nillOl_dataout; nil0ii <= wire_nilO1O_dataout; nil0il <= wire_nilO0i_dataout; nil0iO <= wire_nilO0l_dataout; nil0li <= wire_nilO0O_dataout; nil0ll <= (~ wire_n1l1Ol_dataout); nil0lO <= (n1ii0li | (n1ii0Oi | (pmadwidth[0] & n1ii0Ol))); nil0Oi <= n1ii0iO; nil0Ol <= wire_n110ll_dataout; nil0OO <= wire_nillil_dataout; nil1il <= nil1ll; nil1iO <= nil1lO; nil1li <= wire_nil10l_dataout; nil1ll <= n1i011O; nil1lO <= n1i010i; nil1Ol <= nil1OO; nil1OO <= nl10Ol; nili0i <= wire_niO1ii_dataout; nili0l <= wire_niO1il_dataout; nili0O <= wire_niO1iO_dataout; nili1i <= wire_nillii_dataout; nili1l <= wire_niO10l_dataout; nili1O <= wire_niO10O_dataout; niliii <= wire_niO1li_dataout; niliil <= wire_niO1ll_dataout; niliiO <= wire_niO1lO_dataout; nilili <= nill0i; nilill <= wire_niO1Ol_o; nililO <= wire_niO1OO_o; niliOi <= wire_niO01i_o; niliOl <= wire_niO01l_o; niliOO <= wire_niO01O_o; nill0i <= nl1l1l; nill0l <= niOlii; nill1i <= wire_niO00i_o; nill1l <= wire_niO00l_o; nill1O <= wire_niO00O_o; niOlii <= (rbitloc_rev_en & bitloc_rev_en); niOlil <= wire_niOO0l_o; niOlli <= wire_niOO0O_o; niOlll <= wire_niOOii_o; niOllO <= wire_niOOil_o; niOlOi <= wire_niOOiO_o; niOlOl <= wire_niOOli_o; niOlOO <= wire_niOOll_o; niOO0i <= wire_nl11li_o; niOO1i <= wire_niOOlO_o; niOO1l <= wire_niOOOi_o; niOO1O <= wire_niOOOl_o; niOOOO <= wire_nl11ll_o; nl010il <= nl01iOi; nl010iO <= nl01iOl; nl010li <= nl01iOO; nl010ll <= nl01l1i; nl010lO <= nl01l1l; nl010Oi <= nl01l1O; nl010Ol <= nl01l0i; nl010OO <= nl01l0l; nl0110i <= wire_nl1llll_o; nl0110l <= wire_nl1lllO_o; nl0110O <= wire_nl1llOi_o; nl0111i <= wire_nl1llil_o; nl0111l <= wire_nl1lliO_o; nl0111O <= wire_nl1llli_o; nl011ii <= (~ wire_n1Ol10O_dataout); nl011il <= wire_nl0l1OO_dataout; nl011iO <= ((~ disable_rx_disp) & n10l10l); nl011li <= wire_n1O10lO_dataout; nl011ll <= wire_nl0l0ii_dataout; nl011lO <= wire_nl0l0il_dataout; nl01i0i <= nl01liO; nl01i0l <= nl01lli; nl01i0O <= nl01lll; nl01i1i <= nl01l0O; nl01i1l <= nl01lii; nl01i1O <= nl01lil; nl01iii <= nl01llO; nl01iil <= nl01lOi; nl01iiO <= nl01lOl; nl01ili <= nl01lOO; nl01ill <= nl01O1i; nl01ilO <= nl01O1l; nl01iOi <= wire_nl01O0i_dataout; nl01iOl <= wire_nl01O0l_dataout; nl01iOO <= wire_nl01O0O_dataout; nl01l0i <= wire_nl01Oli_dataout; nl01l0l <= wire_nl01Oll_dataout; nl01l0O <= wire_nl01OlO_dataout; nl01l1i <= wire_nl01Oii_dataout; nl01l1l <= wire_nl01Oil_dataout; nl01l1O <= wire_nl01OiO_dataout; nl01lii <= wire_nl01OOi_dataout; nl01lil <= wire_nl01OOl_dataout; nl01liO <= wire_nl01OOO_dataout; nl01lli <= wire_nl0011i_dataout; nl01lll <= wire_nl0011l_dataout; nl01llO <= wire_nl0011O_dataout; nl01lOi <= wire_nl0010i_dataout; nl01lOl <= wire_nl0010l_dataout; nl01lOO <= wire_nl0010O_dataout; nl01O1i <= wire_nl001ii_dataout; nl01O1l <= wire_nl001il_dataout; nl01O1O <= wire_nll1lOl_dataout; nl100l <= nl100O; nl100O <= nl10ii; nl10ii <= bitslip; nl10Ol <= (~ ((((~ (nll1il ^ nl1iOi)) & (~ (nlli0l ^ nl1iOl))) & (~ (nlli0O ^ nl1iOO))) & (~ (nlliii ^ nl1l1i)))); nl110i <= wire_nl11OO_o; nl110l <= wire_nl101i_o; nl110O <= wire_nl101l_o; nl111i <= wire_nl11lO_o; nl111l <= wire_nl11Oi_o; nl111O <= wire_nl11Ol_o; nl11ii <= wire_nl101O_o; nl11il <= wire_nl100i_o; nl11iO <= (nl100O & (~ nl100l)); nl1ill <= nl1ilO; nl1ilO <= a1a2_size; nl1l1l <= nl1ill; nl1lii <= n1ii10O; nl1liii <= wire_nl0l0lO_dataout; nl1liil <= wire_n1O10lO_dataout; nl1lOi <= nliOlO; nl1Oiil <= ((~ wire_nll1llO_o) & ((~ n111lOi) & (~ n111O1i))); nl1OiiO <= wire_nl0l0ll_dataout; nl1Oili <= nl1Ol1O; nl1Oill <= nl1Ol0i; nl1OilO <= nl1Ol0l; nl1OiOi <= nl1Ol0O; nl1OiOl <= nl1Olii; nl1OiOO <= nl1Olil; nl1Ol0i <= n1101il; nl1Ol0l <= n11001l; nl1Ol0O <= n1101Ol; nl1Ol1i <= nl1OliO; nl1Ol1l <= nl1Olli; nl1Ol1O <= n1101ll; nl1Olii <= n1100il; nl1Olil <= n11000l; nl1OliO <= n1100Ol; nl1Olli <= n1100ll; nl1Olll <= wire_nl1liiO_o; nl1OllO <= wire_nl1lili_o; nl1OlOi <= wire_nl1lill_o; nl1OlOl <= wire_nl1lilO_o; nl1OlOO <= wire_nl1liOi_o; nl1OO0i <= wire_nl1ll1l_o; nl1OO0l <= wire_nl1ll1O_o; nl1OO0O <= (~ wire_n1liO0O_dataout); nl1OO1i <= wire_nl1liOl_o; nl1OO1l <= wire_nl1liOO_o; nl1OO1O <= wire_nl1ll1i_o; nl1OOii <= wire_nl0l1ii_dataout; nl1OOil <= ((~ disable_rx_disp) & n10l10O); nl1OOiO <= wire_n1l11lO_dataout; nl1OOli <= wire_nl0l1lO_dataout; nl1OOll <= wire_nl0l1Oi_dataout; nl1OOlO <= wire_nl1ll0i_o; nl1OOOi <= wire_nl1ll0l_o; nl1OOOl <= wire_nl1ll0O_o; nl1OOOO <= wire_nl1llii_o; nliiOl <= nliOOi; nliiOO <= nliOOl; nlil0i <= nll11O; nlil0l <= nll10i; nlil0O <= nll10l; nlil1i <= nliOOO; nlil1l <= nll11i; nlil1O <= nll11l; nlilii <= nll1ii; nlilll <= wire_nll1iO_dataout; nlillO <= wire_nll1li_dataout; nlilOi <= wire_nll1ll_dataout; nlilOl <= wire_nll1lO_dataout; nlilOO <= wire_nll1Oi_dataout; nliO0i <= wire_nll01l_dataout; nliO0l <= wire_nll01O_dataout; nliO0O <= wire_nll00i_dataout; nliO1i <= wire_nll1Ol_dataout; nliO1l <= wire_nll1OO_dataout; nliO1O <= wire_nll01i_dataout; nliOii <= wire_nll00l_dataout; nliOil <= wire_nll00O_dataout; nliOiO <= wire_nll0ii_dataout; nliOli <= wire_nll0il_dataout; nliOll <= wire_nll0iO_dataout; nliOlO <= wire_nll0li_dataout; nliOOi <= wire_nll0ll_dataout; nliOOl <= wire_nll0lO_dataout; nliOOO <= wire_nll0Oi_dataout; nll000i <= nll0iiO; nll000l <= nll0ili; nll000O <= nll0ill; nll001i <= nll0i0O; nll001l <= nll0iii; nll001O <= nll0iil; nll00ii <= nll0ilO; nll00il <= nll0iOi; nll00iO <= nll0iOl; nll00li <= nll0iOO; nll00ll <= nll0l1i; nll00lO <= nll0l1l; nll00Oi <= nll0l1O; nll00Ol <= nll0l0i; nll00OO <= nll0l0l; nll01ll <= wire_nll1O1i_o; nll01lO <= nll01Oi; nll01Oi <= (signal_detect | rforce_sig_det_pcs); nll01Ol <= nll0i0i; nll01OO <= nll0i0l; nll0i0i <= nll0liO; nll0i0l <= nll0lli; nll0i0O <= nll0lll; nll0i1i <= nll0l0O; nll0i1l <= nll0lii; nll0i1O <= nll0lil; nll0iii <= nll0llO; nll0iil <= nll0lOi; nll0iiO <= nll0lOl; nll0ili <= nll0lOO; nll0ill <= nll0O1i; nll0ilO <= nll0O1l; nll0iOi <= nll0O1O; nll0iOl <= nll0O0i; nll0iOO <= nll0O0l; nll0l0i <= nll0OiO; nll0l0l <= nll0Oli; nll0l0O <= nll0Oll; nll0l1i <= nll0O0O; nll0l1l <= nll0Oii; nll0l1O <= nll0Oil; nll0lii <= nll0OlO; nll0lil <= nll0OOi; nll0liO <= nll0OOl; nll0lli <= nll0OOO; nll0lll <= nlli11i; nll0llO <= nlli11l; nll0lOi <= nlli11O; nll0lOl <= nlli10i; nll0lOO <= nlli10l; nll0O0i <= nlli1iO; nll0O0l <= nlli1li; nll0O0O <= nlli1ll; nll0O1i <= nlli10O; nll0O1l <= nlli1ii; nll0O1O <= nlli1il; nll0Oii <= nlli1lO; nll0Oil <= nlli1Oi; nll0OiO <= nlli1Ol; nll0Oli <= nlli1OO; nll0Oll <= nlli01i; nll0OlO <= nlli01l; nll0OOi <= nlli01O; nll0OOl <= wire_nllii0O_dataout; nll0OOO <= wire_nlliiii_dataout; nll10i <= wire_nlli1l_dataout; nll11i <= wire_nll0Ol_dataout; nll11l <= wire_nll0OO_dataout; nll11O <= wire_nlli1i_dataout; nlli00i <= (nlli00O & (~ nlli00l)); nlli00l <= nlli00O; nlli00O <= nlli0ii; nlli01i <= wire_nllilil_dataout; nlli01l <= wire_nlliliO_dataout; nlli01O <= wire_nllilli_dataout; nlli0ii <= bitslip; nlli0il <= nlli0iO; nlli0iO <= (rbyte_rev_en & byte_rev_en); nlli0li <= nlli0ll; nlli0ll <= (rbitloc_rev_en & bitloc_rev_en); nlli0lO <= nlli0Oi; nlli0Oi <= rlv_en; nlli0Ol <= (nllii0i & (~ nllii1O)); nlli0OO <= wire_nllilOO_dataout; nlli10i <= wire_nlliill_dataout; nlli10l <= wire_nlliilO_dataout; nlli10O <= wire_nlliiOi_dataout; nlli11i <= wire_nlliiil_dataout; nlli11l <= wire_nlliiiO_dataout; nlli11O <= wire_nlliili_dataout; nlli1ii <= wire_nlliiOl_dataout; nlli1il <= wire_nlliiOO_dataout; nlli1iO <= wire_nllil1i_dataout; nlli1li <= wire_nllil1l_dataout; nlli1ll <= wire_nllil1O_dataout; nlli1lO <= wire_nllil0i_dataout; nlli1Oi <= wire_nllil0l_dataout; nlli1Ol <= wire_nllil0O_dataout; nlli1OO <= wire_nllilii_dataout; nllii0i <= nllii0l; nllii0l <= encdt; nllii1i <= nllii1l; nllii1l <= nllii1O; nllii1O <= nllii0i; nllll1i <= (((wire_nllO0ii_dataout | wire_nllO00l_dataout) | wire_nllO00i_dataout) | wire_nllO01l_dataout); nlllOl <= wire_nlll1l_o; nlllOO <= wire_nlll1O_o; nlO <= wire_ni_dataout; nlO000i <= wire_nlllliO_o; nlO000l <= wire_nllllli_o; nlO000O <= wire_nllllll_o; nlO001i <= wire_nllll0O_o; nlO001l <= wire_nllllii_o; nlO001O <= wire_nllllil_o; nlO00ii <= wire_nllllOl_o; nlO00il <= wire_nllllOO_o; nlO00iO <= wire_nlllO1i_o; nlO00li <= wire_nlllO1l_o; nlO00ll <= wire_nlllO1O_o; nlO00lO <= wire_nlllO0i_o; nlO00Oi <= wire_nlllO0l_o; nlO00Ol <= wire_nlllO0O_o; nlO00OO <= wire_nlllOii_o; nlO010i <= (pipe_loose_sync & (rforce_sig_det_pcs | (signal_detect | lpbk_en))); nlO010l <= nlO010i; nlO011i <= (((wire_nllO00O_dataout | wire_nllO00l_dataout) | wire_nllO01O_dataout) | wire_nllO01l_dataout); nlO011l <= (~ (((wire_nllO0il_dataout | wire_nllO0ii_dataout) | wire_nllO00O_dataout) | wire_nllO00l_dataout)); nlO011O <= wire_nllO01i_dataout; nlO01ii <= wire_nllO1iO_o; nlO01il <= wire_nlllill_dataout; nlO01iO <= wire_nlllilO_dataout; nlO01li <= wire_nllliOi_dataout; nlO01ll <= wire_nllliOl_dataout; nlO01lO <= wire_nllll1l_o; nlO01Oi <= wire_nllll1O_o; nlO01Ol <= wire_nllll0i_o; nlO01OO <= wire_nllll0l_o; nlO0i0i <= wire_nlllOOO_o; nlO0i0l <= wire_nllO11i_o; nlO0i0O <= wire_nllO11l_o; nlO0i1i <= wire_nlllOil_o; nlO0i1l <= wire_nlllOOi_o; nlO0i1O <= wire_nlllOOl_o; nlO0iii <= wire_nllO11O_o; nlO0iil <= wire_nllO10i_o; nlO0iiO <= wire_nllO10l_o; nlO0ili <= wire_nllO10O_o; nlO0ill <= wire_nllO1ii_o; nlO0ilO <= nlO0l1i; nlO0l1i <= prbs_en; nlO0l1l <= nlO0l1O; nlO0l1O <= encdt; nlOi0ll <= n1i0l0i; nlOi0lO <= wire_nlOi0iO_o; nlOi0Oi <= n1i0l0O; nlOi0Ol <= wire_nlOi00i_o; nlOi0OO <= n1i0lil; nlOii0i <= n1i0llO; nlOii0l <= wire_nlOi10i_o; nlOii0O <= n1i0O1i; nlOii1i <= wire_nlOi1Ol_o; nlOii1l <= n1i0lli; nlOii1O <= wire_nlOi1iO_o; nlOiiii <= wire_nlO0OOl_o; nlOiiil <= n1i0Oii; nlOiiiO <= wire_nlO0OiO_o; nlOiili <= n1ii11l; nlOiill <= wire_nlO0O0i_o; nlOiilO <= n1ii11l; nlOilOl <= n1i0Oii; nlOilOO <= n1i0O1i; nlOiO0i <= n1i0l0O; nlOiO0l <= n1i0l0i; nlOiO1i <= n1i0llO; nlOiO1l <= n1i0lli; nlOiO1O <= n1i0lil; nO <= ni0iO; end end assign wire_nl_CLRN = ((n1iil0O2 ^ n1iil0O1) & (~ wire_ni0lO_dataout)); initial begin nl10il = 0; nl10li = 0; nl10ll = 0; nl10Oi = 0; end always @ ( posedge clk or negedge wire_nl10lO_CLRN) begin if (wire_nl10lO_CLRN == 1'b0) begin nl10il <= 0; nl10li <= 0; nl10ll <= 0; nl10Oi <= 0; end else if (nl11iO == 1'b1) begin nl10il <= wire_nl10OO_dataout; nl10li <= wire_nl1i1i_dataout; nl10ll <= wire_nl1i1l_dataout; nl10Oi <= wire_nl1i1O_dataout; end end assign wire_nl10lO_CLRN = ((n1i00OO50 ^ n1i00OO49) & (~ wire_ni0lO_dataout)); initial begin nl1lil = 0; nl1liO = 0; nl1lli = 0; nl1llO = 0; end always @ ( posedge clk or posedge wire_ni0lO_dataout) begin if (wire_ni0lO_dataout == 1'b1) begin nl1lil <= 1; nl1liO <= 1; nl1lli <= 1; nl1llO <= 1; end else if (n1ii10O == 1'b1) begin nl1lil <= (~ n1ii1OO); nl1liO <= n1ii01i; nl1lli <= n1ii01l; nl1llO <= n1ii01O; end end event nl1lil_event; event nl1liO_event; event nl1lli_event; event nl1llO_event; initial #1 ->nl1lil_event; initial #1 ->nl1liO_event; initial #1 ->nl1lli_event; initial #1 ->nl1llO_event; always @(nl1lil_event) nl1lil <= 1; always @(nl1liO_event) nl1liO <= 1; always @(nl1lli_event) nl1lli <= 1; always @(nl1llO_event) nl1llO <= 1; initial begin nlilil = 0; nliliO = 0; nlilli = 0; nll10l = 0; nll1ii = 0; end always @ (clk or wire_nll10O_PRN or wire_ni0lO_dataout) begin if (wire_nll10O_PRN == 1'b0) begin nlilil <= 1; nliliO <= 1; nlilli <= 1; nll10l <= 1; nll1ii <= 1; end else if (wire_ni0lO_dataout == 1'b1) begin nlilil <= 0; nliliO <= 0; nlilli <= 0; nll10l <= 0; nll1ii <= 0; end else if (wire_nll10O_ENA == 1'b1) if (clk != nll10O_clk_prev && clk == 1'b1) begin nlilil <= nliO1O; nliliO <= nliO0i; nlilli <= nliO0l; nll10l <= wire_nlli1O_dataout; nll1ii <= wire_nlli0i_dataout; end nll10O_clk_prev <= clk; end assign wire_nll10O_ENA = pmadwidth[0], wire_nll10O_PRN = (n1ii10l34 ^ n1ii10l33); initial begin n1O01l = 0; n1OO01O = 0; nil1Oi = 0; nl0100i = 0; nl0100l = 0; nl0100O = 0; nl0101i = 0; nl0101l = 0; nl0101O = 0; nl010ii = 0; nl011Oi = 0; nl011Ol = 0; nl011OO = 0; nl1iOi = 0; nl1iOl = 0; nl1iOO = 0; nl1l1i = 0; nll01li = 0; nll1il = 0; nlli0l = 0; nlli0O = 0; nlliii = 0; nllO1l = 0; nlO010O = 0; end always @ (clk or wire_ni0lO_dataout or wire_nllO1i_CLRN) begin if (wire_ni0lO_dataout == 1'b1) begin n1O01l <= 1; n1OO01O <= 1; nil1Oi <= 1; nl0100i <= 1; nl0100l <= 1; nl0100O <= 1; nl0101i <= 1; nl0101l <= 1; nl0101O <= 1; nl010ii <= 1; nl011Oi <= 1; nl011Ol <= 1; nl011OO <= 1; nl1iOi <= 1; nl1iOl <= 1; nl1iOO <= 1; nl1l1i <= 1; nll01li <= 1; nll1il <= 1; nlli0l <= 1; nlli0O <= 1; nlliii <= 1; nllO1l <= 1; nlO010O <= 1; end else if (wire_nllO1i_CLRN == 1'b0) begin n1O01l <= 0; n1OO01O <= 0; nil1Oi <= 0; nl0100i <= 0; nl0100l <= 0; nl0100O <= 0; nl0101i <= 0; nl0101l <= 0; nl0101O <= 0; nl010ii <= 0; nl011Oi <= 0; nl011Ol <= 0; nl011OO <= 0; nl1iOi <= 0; nl1iOl <= 0; nl1iOO <= 0; nl1l1i <= 0; nll01li <= 0; nll1il <= 0; nlli0l <= 0; nlli0O <= 0; nlliii <= 0; nllO1l <= 0; nlO010O <= 0; end else if (clk != nllO1i_clk_prev && clk == 1'b1) begin n1O01l <= (~ n1OiOi); n1OO01O <= (~ nlli0lO); nil1Oi <= (n1ii0iO | (~ wire_n1l1Ol_dataout)); nl0100i <= wire_nl0i1OO_dataout; nl0100l <= wire_nl0i01i_dataout; nl0100O <= wire_nl0i01l_dataout; nl0101i <= nl0100O; nl0101l <= nl010ii; nl0101O <= wire_nl0i1Ol_dataout; nl010ii <= wire_nl0i01O_dataout; nl011Oi <= nl0101O; nl011Ol <= nl0100i; nl011OO <= nl0100l; nl1iOi <= wire_nl1l1O_dataout; nl1iOl <= wire_nl1l0i_dataout; nl1iOO <= wire_nl1l0l_dataout; nl1l1i <= wire_nl1l0O_dataout; nll01li <= wire_nll1lOO_o; nll1il <= wire_nlliil_dataout; nlli0l <= wire_nlliiO_dataout; nlli0O <= wire_nllili_dataout; nlliii <= wire_nllill_dataout; nllO1l <= wire_nlll0i_o; nlO010O <= wire_nlllOli_o; end nllO1i_clk_prev <= clk; end assign wire_nllO1i_CLRN = (n1ii00O20 ^ n1ii00O19); event n1O01l_event; event n1OO01O_event; event nil1Oi_event; event nl0100i_event; event nl0100l_event; event nl0100O_event; event nl0101i_event; event nl0101l_event; event nl0101O_event; event nl010ii_event; event nl011Oi_event; event nl011Ol_event; event nl011OO_event; event nl1iOi_event; event nl1iOl_event; event nl1iOO_event; event nl1l1i_event; event nll01li_event; event nll1il_event; event nlli0l_event; event nlli0O_event; event nlliii_event; event nllO1l_event; event nlO010O_event; initial #1 ->n1O01l_event; initial #1 ->n1OO01O_event; initial #1 ->nil1Oi_event; initial #1 ->nl0100i_event; initial #1 ->nl0100l_event; initial #1 ->nl0100O_event; initial #1 ->nl0101i_event; initial #1 ->nl0101l_event; initial #1 ->nl0101O_event; initial #1 ->nl010ii_event; initial #1 ->nl011Oi_event; initial #1 ->nl011Ol_event; initial #1 ->nl011OO_event; initial #1 ->nl1iOi_event; initial #1 ->nl1iOl_event; initial #1 ->nl1iOO_event; initial #1 ->nl1l1i_event; initial #1 ->nll01li_event; initial #1 ->nll1il_event; initial #1 ->nlli0l_event; initial #1 ->nlli0O_event; initial #1 ->nlliii_event; initial #1 ->nllO1l_event; initial #1 ->nlO010O_event; always @(n1O01l_event) n1O01l <= 1; always @(n1OO01O_event) n1OO01O <= 1; always @(nil1Oi_event) nil1Oi <= 1; always @(nl0100i_event) nl0100i <= 1; always @(nl0100l_event) nl0100l <= 1; always @(nl0100O_event) nl0100O <= 1; always @(nl0101i_event) nl0101i <= 1; always @(nl0101l_event) nl0101l <= 1; always @(nl0101O_event) nl0101O <= 1; always @(nl010ii_event) nl010ii <= 1; always @(nl011Oi_event) nl011Oi <= 1; always @(nl011Ol_event) nl011Ol <= 1; always @(nl011OO_event) nl011OO <= 1; always @(nl1iOi_event) nl1iOi <= 1; always @(nl1iOl_event) nl1iOl <= 1; always @(nl1iOO_event) nl1iOO <= 1; always @(nl1l1i_event) nl1l1i <= 1; always @(nll01li_event) nll01li <= 1; always @(nll1il_event) nll1il <= 1; always @(nlli0l_event) nlli0l <= 1; always @(nlli0O_event) nlli0O <= 1; always @(nlliii_event) nlliii <= 1; always @(nllO1l_event) nllO1l <= 1; always @(nlO010O_event) nlO010O <= 1; assign wire_n00i_dataout = (nO === 1'b1) ? (~ pudi[15]) : pudi[15]; assign wire_n00l_dataout = (nO === 1'b1) ? (~ pudi[16]) : pudi[16]; assign wire_n00O_dataout = (nO === 1'b1) ? (~ pudi[17]) : pudi[17]; and(wire_n0100i_dataout, ((((~ n10Ol0l) | (~ n10Ol0i)) | (~ n10Ol1O)) | (~ n10Ol1l)), n1OiOi); and(wire_n0100iO_dataout, ((~ nlOOil1l) | ((~ nlOOil1i) | ((~ nlOOiiOO) | ((~ nlOOiiOl) | ((~ nlOOiiOi) | ((~ nlOOiilO) | ((~ nlOOiill) | ((~ nlOOiili) | ((~ nlOOiiiO) | ((~ nlOOiiil) | ((~ nlOOiiii) | ((~ nlOOii0O) | ((~ nlOOii0l) | ((~ nlOOii0i) | ((~ nlOOii1O) | (~ nlOOii1l)))))))))))))))), nlli0lO); and(wire_n0100l_dataout, ((n1i11ii | (~ n10Ol0O)) | (~ (((~ n1i100O) | n1i11il) | n1i11ii))), n1OiOi); and(wire_n0100li_dataout, ((pmadwidth[0] & nlOOOO0i) | ((~ pmadwidth[0]) & (~ n11100i))), nlli0lO); and(wire_n0100ll_dataout, nlOOl00O, nlli0lO); and(wire_n0100lO_dataout, nlOOl0il, nlli0lO); and(wire_n0100O_dataout, n011iO, n1OiOi); and(wire_n0100Oi_dataout, nlOOl0iO, nlli0lO); and(wire_n0100Ol_dataout, nlOOl0li, nlli0lO); and(wire_n0100OO_dataout, nlOOl0ll, nlli0lO); and(wire_n01010i_dataout, nlOOiOOl, nlli0lO); and(wire_n01010l_dataout, nlOOiOOO, nlli0lO); and(wire_n01010O_dataout, nlOOl11i, nlli0lO); and(wire_n01011i_dataout, n011O1l, nlli0lO); and(wire_n01011l_dataout, n011O1O, nlli0lO); and(wire_n01011O_dataout, nlOOiOlO, nlli0lO); and(wire_n0101i_dataout, ((pmadwidth[0] & n1i11ii) | ((~ pmadwidth[0]) & n1i100O)), n1OiOi); and(wire_n0101ii_dataout, nlOOl11l, nlli0lO); and(wire_n0101l_dataout, n10OilO, n1OiOi); and(wire_n0101O_dataout, n10OiOl, n1OiOi); and(wire_n010i0i_dataout, n0100ii, nlli0lO); and(wire_n010i0l_dataout, n0100il, nlli0lO); and(wire_n010i0O_dataout, nlOOliOO, nlli0lO); and(wire_n010i1i_dataout, n01000i, nlli0lO); and(wire_n010i1l_dataout, n01000l, nlli0lO); and(wire_n010i1O_dataout, n01000O, nlli0lO); and(wire_n010ii_dataout, n011li, n1OiOi); and(wire_n010iii_dataout, nlOOll1l, nlli0lO); and(wire_n010iil_dataout, nlOOll1O, nlli0lO); and(wire_n010iiO_dataout, nlOOll0i, nlli0lO); and(wire_n010il_dataout, n011ll, n1OiOi); and(wire_n010ili_dataout, nlOOll0l, nlli0lO); and(wire_n010iO_dataout, n011lO, n1OiOi); and(wire_n010li_dataout, n10Olii, n1OiOi); and(wire_n010ll_dataout, n10OliO, n1OiOi); and(wire_n010lO_dataout, ((((~ n10OlOO) | (~ n10OlOl)) | (~ n10OlOi)) | (~ n10OllO)), n1OiOi); and(wire_n010Oi_dataout, ((n1i101i | (~ n10OO1i)) | (~ (((~ n1i100l) | n1i101O) | n1i101i))), n1OiOi); assign wire_n0110il_dataout = ((~ pmadwidth[0]) === 1'b1) ? nlOOi1Oi : nlOOi1Ol; and(wire_n0110iO_dataout, wire_n011ill_dataout, ~((~ pmadwidth[0]))); and(wire_n0110li_dataout, wire_n011ilO_dataout, ~((~ pmadwidth[0]))); assign wire_n0110ll_dataout = ((~ pmadwidth[0]) === 1'b1) ? wire_n011ill_dataout : wire_n011i1O_dataout; assign wire_n0110lO_dataout = ((~ pmadwidth[0]) === 1'b1) ? wire_n011ilO_dataout : wire_n011i0i_dataout; assign wire_n0110Oi_dataout = ((~ pmadwidth[0]) === 1'b1) ? wire_n011iOi_dataout : wire_n011i0l_dataout; assign wire_n0110Ol_dataout = ((~ pmadwidth[0]) === 1'b1) ? wire_n011iOl_dataout : wire_n011i0O_dataout; assign wire_n0110OO_dataout = ((~ pmadwidth[0]) === 1'b1) ? wire_n011iOO_dataout : wire_n011iii_dataout; and(wire_n011i0i_dataout, wire_n011ili_o[1], ~(nlOOi1OO)); and(wire_n011i0l_dataout, wire_n011ili_o[2], ~(nlOOi1OO)); and(wire_n011i0O_dataout, wire_n011ili_o[3], ~(nlOOi1OO)); assign wire_n011i1i_dataout = ((~ pmadwidth[0]) === 1'b1) ? wire_n011l1i_dataout : wire_n011iil_dataout; assign wire_n011i1l_dataout = ((~ pmadwidth[0]) === 1'b1) ? nlOOi1OO : wire_n011iiO_dataout; and(wire_n011i1O_dataout, wire_n011ili_o[0], ~(nlOOi1OO)); or(wire_n011iii_dataout, wire_n011ili_o[4], nlOOi1OO); and(wire_n011iil_dataout, wire_n011ili_o[5], ~(nlOOi1OO)); or(wire_n011iiO_dataout, wire_n011ili_o[6], nlOOi1OO); and(wire_n011ill_dataout, max_rlv_sel[0], ~(nlOOi1OO)); and(wire_n011ilO_dataout, max_rlv_sel[1], ~(nlOOi1OO)); and(wire_n011iOi_dataout, max_rlv_sel[2], ~(nlOOi1OO)); and(wire_n011iOl_dataout, max_rlv_sel[3], ~(nlOOi1OO)); and(wire_n011iOO_dataout, max_rlv_sel[4], ~(nlOOi1OO)); and(wire_n011l1i_dataout, max_rlv_sel[5], ~(nlOOi1OO)); and(wire_n011O0l_dataout, ((~ nlOOii1i) | ((~ nlOOi0OO) | ((~ nlOOi0Ol) | ((~ nlOOi0Oi) | ((~ nlOOi0lO) | ((~ nlOOi0ll) | ((~ nlOOi0li) | ((~ nlOOi0iO) | ((~ nlOOi0il) | ((~ nlOOi0ii) | ((~ nlOOi00O) | ((~ nlOOi00l) | ((~ nlOOi00i) | ((~ nlOOi01O) | ((~ nlOOi01l) | (~ nlOOi01i)))))))))))))))), nlli0lO); and(wire_n011O0O_dataout, (nlOOOO1O | nlOOOO1l), nlli0lO); and(wire_n011Oii_dataout, ((pmadwidth[0] & nlOOlOiO) | ((~ pmadwidth[0]) & nlOOO0iO)), nlli0lO); and(wire_n011Oil_dataout, nlOOil1O, nlli0lO); and(wire_n011OiO_dataout, nlOOil0l, nlli0lO); and(wire_n011Ol_dataout, ((~ n10Oi0i) | ((~ n10Oi1O) | ((~ n10Oi1l) | ((~ n10Oi1i) | ((~ n10O0OO) | ((~ n10O0Ol) | (~ n10O0Oi))))))), n1OiOi); and(wire_n011Oli_dataout, nlOOil0O, nlli0lO); and(wire_n011Oll_dataout, nlOOilii, nlli0lO); and(wire_n011OlO_dataout, nlOOilil, nlli0lO); and(wire_n011OO_dataout, (n1i1i0O | n1i1i0l), n1OiOi); and(wire_n011OOi_dataout, n011lOl, nlli0lO); and(wire_n011OOl_dataout, n011lOO, nlli0lO); and(wire_n011OOO_dataout, n011O1i, nlli0lO); assign wire_n01i_dataout = (nO === 1'b1) ? (~ pudi[12]) : pudi[12]; and(wire_n01ilO_dataout, ((~ n10Oill) | ((~ n10Oili) | ((~ n10OiiO) | ((~ n10Oiil) | ((~ n10Oiii) | ((~ n10Oi0O) | (~ n10Oi0l))))))), n1OiOi); and(wire_n01iOi_dataout, ((pmadwidth[0] & n1i1iii) | ((~ pmadwidth[0]) & (~ n1i1l0O))), n1OiOi); and(wire_n01iOl_dataout, n10OO1l, n1OiOi); and(wire_n01iOO_dataout, n10OO0i, n1OiOi); assign wire_n01l_dataout = (nO === 1'b1) ? (~ pudi[13]) : pudi[13]; and(wire_n01l0i_dataout, n01iiO, n1OiOi); and(wire_n01l0l_dataout, n01ili, n1OiOi); and(wire_n01l0O_dataout, n01ill, n1OiOi); and(wire_n01l1i_dataout, ((((~ n10OOli) | (~ n10OOiO)) | (~ n10OOil)) | (~ n10OOii)), n1OiOi); and(wire_n01l1l_dataout, ((n1i1iii | (~ n10OOll)) | (~ ((n1i1l0O | n1i1iil) | n1i1iii))), n1OiOi); and(wire_n01l1O_dataout, n01iil, n1OiOi); and(wire_n01lii_dataout, n10OOlO, n1OiOi); and(wire_n01lil_dataout, n10OOOl, n1OiOi); and(wire_n01liO_dataout, ((((~ n1i110l) | (~ n1i110i)) | (~ n1i111O)) | (~ n1i111l)), n1OiOi); and(wire_n01lli_dataout, ((n1i1l1i | (~ n1i110O)) | (~ (((~ n1i1l0l) | n1i1l1O) | n1i1l1i))), n1OiOi); assign wire_n01O_dataout = (nO === 1'b1) ? (~ pudi[14]) : pudi[14]; assign wire_n0i_dataout = (wa_6g_en === 1'b1) ? nl0101O : nl1liO; assign wire_n0ii_dataout = (wa_6g_en === 1'b1) ? (((n1OO0li | n1OO0iO) | (~ (n1iii0O10 ^ n1iii0O9))) | ((n1iiiOi & n1OO00i) & (n1iii0i12 ^ n1iii0i11))) : (((n1Oi0i | n1Oi1O) | (n1iiiOi & n1O01O)) | (~ (n1iiiil8 ^ n1iiiil7))); assign wire_n0il_dataout = (wa_6g_en === 1'b1) ? n1iiili : n1iiill; assign wire_n0iO_dataout = (wa_6g_en === 1'b1) ? nl01O1O : nlO01ii; assign wire_n0l_dataout = (wa_6g_en === 1'b1) ? nl0100i : nl1lli; assign wire_n0li_dataout = (wa_6g_en === 1'b1) ? wire_nl1iOOl_dataout : wire_nii0ii_dataout; assign wire_n0ll_dataout = (wa_6g_en === 1'b1) ? wire_nl1iOOO_dataout : wire_nii0il_dataout; assign wire_n0lO_dataout = (wa_6g_en === 1'b1) ? wire_nl1l11i_dataout : wire_nii0iO_dataout; assign wire_n0O_dataout = (wa_6g_en === 1'b1) ? nl0100l : nl1llO; assign wire_n0Oi_dataout = (wa_6g_en === 1'b1) ? wire_nl1l11l_dataout : wire_nii0li_dataout; assign wire_n0Ol_dataout = (wa_6g_en === 1'b1) ? wire_nl1l11O_dataout : wire_nii0ll_dataout; assign wire_n0OO_dataout = (wa_6g_en === 1'b1) ? wire_nl1l10i_dataout : wire_nii0lO_dataout; assign wire_n10i_dataout = (nO === 1'b1) ? (~ pudi[18]) : pudi[18]; assign wire_n10l_dataout = (nO === 1'b1) ? (~ pudi[19]) : pudi[19]; assign wire_n10O_dataout = (nO === 1'b1) ? (~ pudi[0]) : pudi[0]; assign wire_n110ll_dataout = (((wire_niOl1O_o ^ wire_niOl1l_o) & n1i01ll) === 1'b1) ? wire_nlOll0O_dataout : (n1i01lO | n1i01OO); assign wire_n11i_dataout = (nO === 1'b1) ? (~ pudi[15]) : pudi[15]; assign wire_n11l_dataout = (nO === 1'b1) ? (~ pudi[16]) : pudi[16]; assign wire_n11O_dataout = (nO === 1'b1) ? (~ pudi[17]) : pudi[17]; assign wire_n1i_dataout = (wa_6g_en === 1'b1) ? nll01ll : nlO011l; assign wire_n1ii_dataout = (nO === 1'b1) ? (~ pudi[1]) : pudi[1]; assign wire_n1il_dataout = (nO === 1'b1) ? (~ pudi[2]) : pudi[2]; assign wire_n1iliii_dataout = (((((~ wire_nl1lilO_o) & nlOO1l1O) | (wire_nl1lilO_o & nlOO1lii)) | (nlOO1llO & nlOO1lli)) === 1'b1) ? nl1liil : (nlOO1lil | nlOO1liO); assign wire_n1iO_dataout = (nO === 1'b1) ? (~ pudi[3]) : pudi[3]; assign wire_n1l_dataout = (wa_6g_en === 1'b1) ? wire_nllO_dataout : nlO011O; assign wire_n1l0Ol_dataout = (wire_n1li0i_o[4] === 1'b1) ? wire_n1li1O_o[0] : wire_n1li0l_dataout; assign wire_n1l0OO_dataout = (wire_n1li0i_o[4] === 1'b1) ? wire_n1li1O_o[1] : wire_n1li0O_dataout; assign wire_n1l11lO_dataout = (((wire_nl1ll1i_o ^ wire_nl1liOO_o) & nlOO1O0i) === 1'b1) ? wire_n1iliii_dataout : (nlOO1O0l | nlOO1O1O); assign wire_n1l1Ol_dataout = (((~ r8b10b_dec_ibm_en[0]) & (~ r8b10b_dec_ibm_en[1])) === 1'b1) ? ((~ n10O1Oi) & ((~ ((n10O11i | (n10lOOO | n10lOOl)) | (n1i000i | (n1i00li | (n1i00ll | n1i00iO))))) & (~ (((n10lOOi | n1i01Oi) | ((~ (((n1i1OlO | n1i1Oll) | n1i1OiO) | n1i1Oli)) & ((~ n10lOlO) & (((~ wire_niOl1l_o) & n10lOll) | (wire_niOl1l_o & n1i01Ol))))) | ((((~ wire_niOl0l_dataout) & n10lOll) | (wire_niOl0l_dataout & n1i01Ol)) & (n1i1Oll | (n1i1OlO | n10lOlO))))))) : (~ ((((((((((((((n10O1Oi | (n10O1lO | n10O1ll)) | ((~ wire_niOl1i_o) & ((~ wire_niOiOO_o) & n10O1li))) | (wire_niOl1i_o & (wire_niOiOO_o & n10O1iO))) | ((wire_niOl0l_dataout & (wire_niOl0i_dataout & (wire_niOl1O_o & wire_niOl1l_o))) | ((~ wire_niOl0l_dataout) & ((~ wire_niOl0i_dataout) & ((~ wire_niOl1O_o) & (~ wire_niOl1l_o)))))) | ((~ wire_niOl0i_dataout) & ((~ wire_niOl1O_o) & ((~ wire_niOl1l_o) & ((~ wire_niOl1i_o) & (~ wire_niOiOO_o)))))) | (wire_niOl0i_dataout & (wire_niOl1O_o & (wire_niOl1l_o & (wire_niOl1i_o & wire_niOiOO_o))))) | ((~ wire_niOl0l_dataout) & ((~ wire_niOl0i_dataout) & ((~ wire_niOl1O_o) & n10O1il)))) | (wire_niOl0l_dataout & (wire_niOl0i_dataout & (wire_niOl1O_o & n10O1ii)))) | ((((~ wire_niOl0l_dataout) & ((~ wire_niOl0i_dataout) & ((~ wire_niOl1O_o) & wire_niOl1i_o))) | (wire_niOl0l_dataout & (wire_niOl0i_dataout & (wire_niOl1O_o & (~ wire_niOl1i_o))))) & (~ n10O10O))) | (n10O10O & ((wire_niOl0i_dataout & n10O10l) | ((~ wire_niOl0i_dataout) & n10O10i)))) | (((~ wire_niOl0l_dataout) & ((~ wire_niOl0i_dataout) & ((~ wire_niOl1O_o) & n10O1ii))) & (~ n10O1iO))) | ((wire_niOl0l_dataout & (wire_niOl0i_dataout & (wire_niOl1O_o & n10O1il))) & (~ n10O1li))) | (r8b10b_dec_ibm_en[1] & ((((((~ wire_niOl1i_o) & ((~ wire_niOiOO_o) & n10O11O)) | n10O1ll) | (((~ wire_niOl1i_o) | (~ wire_niOiOO_o)) & n10O1li)) | ((~ wire_niOl1i_o) & ((~ wire_niOiOO_o) & (~ wire_niOiOl_o)))) & ((n10O10i | (n10O10i & n10O11l)) | (n10O11l & ((~ wire_niOl1O_o) | (~ wire_niOl1l_o))))))) | (r8b10b_dec_ibm_en[1] & (((((wire_niOl1i_o & (wire_niOiOO_o & n10O11O)) | n10O1lO ) | ((wire_niOl1i_o | wire_niOiOO_o) & n10O1iO)) | (wire_niOl1i_o & (wire_niOiOO_o & wire_niOiOl_o))) & ((n10O10l | (n10O10l & (wire_niOl0l_dataout | wire_niOl0i_dataout))) | ((wire_niOl0l_dataout & wire_niOl0i_dataout) & (wire_niOl1O_o | wire_niOl1l_o))))))); assign wire_n1li_dataout = (nO === 1'b1) ? (~ pudi[4]) : pudi[4]; and(wire_n1li0l_dataout, n1l0iO, n10O1Ol); and(wire_n1li0O_dataout, n1l0li, n10O1Ol); assign wire_n1li1i_dataout = (wire_n1li0i_o[4] === 1'b1) ? wire_n1li1O_o[2] : wire_n1liil_dataout; assign wire_n1li1l_dataout = (wire_n1li0i_o[4] === 1'b1) ? wire_n1li1O_o[3] : wire_n1liiO_dataout; and(wire_n1liil_dataout, n1l0ll, n10O1Ol); and(wire_n1liiO_dataout, n1l0lO, n10O1Ol); assign wire_n1liO0O_dataout = (((~ r8b10b_dec_ibm_en[0]) & (~ r8b10b_dec_ibm_en[1])) === 1'b1) ? ((~ nlOO00ii) & ((~ ((nlOO01li | (nlOO01iO | nlOO01il)) | (nlOO01ii | (nlOO010O | (nlOO010l | nlOO010i))))) & (~ (((nlOO011O | nlOO011l) | ((~ (((nlOO011i | nlOO1OOO) | (wire_nl1liOl_o & ((~ wire_nl1liOi_o) & nlOO1OOl))) | ((~ wire_nl1liOl_o) & (wire_nl1liOi_o & nlOO1OOi)))) & ((~ nlOO1OlO) & (((~ wire_nl1liOO_o) & nlOO1Oll) | (wire_nl1liOO_o & nlOO1Oli))))) | ((((~ wire_nl1ll1O_o) & nlOO1Oll) | (wire_nl1ll1O_o & nlOO1Oli)) & (nlOO1OOO | (nlOO011i | nlOO1OlO))))))) : (~ ((((((((((((((nlOO00ii | (nlOO000O | nlOO000l)) | ((~ wire_nl1liOl_o) & ((~ wire_nl1liOi_o) & nlOO000i))) | (wire_nl1liOl_o & (wire_nl1liOi_o & nlOO001O))) | ((wire_nl1ll1O_o & (wire_nl1ll1l_o & (wire_nl1ll1i_o & wire_nl1liOO_o))) | ((~ wire_nl1ll1O_o) & ((~ wire_nl1ll1l_o) & ((~ wire_nl1ll1i_o) & (~ wire_nl1liOO_o)))))) | ((~ wire_nl1ll1l_o) & ((~ wire_nl1ll1i_o) & ((~ wire_nl1liOO_o) & ((~ wire_nl1liOl_o) & (~ wire_nl1liOi_o)))))) | (wire_nl1ll1l_o & (wire_nl1ll1i_o & (wire_nl1liOO_o & (wire_nl1liOl_o & wire_nl1liOi_o))))) | ((~ wire_nl1ll1O_o) & ((~ wire_nl1ll1l_o) & ((~ wire_nl1ll1i_o) & nlOO001l)))) | (wire_nl1ll1O_o & (wire_nl1ll1l_o & (wire_nl1ll1i_o & nlOO001i)))) | ((((~ wire_nl1ll1O_o) & ((~ wire_nl1ll1l_o) & ((~ wire_nl1ll1i_o) & wire_nl1liOl_o))) | (wire_nl1ll1O_o & (wire_nl1ll1l_o & (wire_nl1ll1i_o & (~ wire_nl1liOl_o))))) & (~ nlOO01OO))) | (nlOO01OO & ((wire_nl1ll1l_o & nlOO01Ol) | ((~ wire_nl1ll1l_o) & nlOO01Oi)))) | (((~ wire_nl1ll1O_o) & ((~ wire_nl1ll1l_o) & ((~ wire_nl1ll1i_o) & nlOO001i))) & (~ nlOO001O))) | ((wire_nl1ll1O_o & (wire_nl1ll1l_o & (wire_nl1ll1i_o & nlOO001l))) & (~ nlOO000i))) | (r8b10b_dec_ibm_en[1] & ((((((~ wire_nl1liOl_o) & ((~ wire_nl1liOi_o) & nlOO01lO)) | nlOO000l) | (((~ wire_nl1liOl_o) | (~ wire_nl1liOi_o)) & nlOO000i)) | ((~ wire_nl1liOl_o) & ((~ wire_nl1liOi_o) & (~ wire_nl1lilO_o)))) & ((nlOO01Oi | (nlOO01Oi & nlOO01ll)) | (nlOO01ll & ((~ wire_nl1ll1i_o) | (~ wire_nl1liOO_o))))))) | (r8b10b_dec_ibm_en[1] & (((((wire_nl1liOl_o & (wire_nl1liOi_o & nlOO01lO)) | nlOO000O) | ((wire_nl1liOl_o | wire_nl1liOi_o) & nlOO001O)) | (wire_nl1liOl_o & (wire_nl1liOi_o & wire_nl1lilO_o))) & ((nlOO01Ol | (nlOO01Ol & (wire_nl1ll1O_o | wire_nl1ll1l_o))) | ((wire_nl1ll1O_o & wire_nl1ll1l_o) & (wire_nl1ll1i_o | wire_nl1liOO_o))))))); assign wire_n1ll_dataout = (nO === 1'b1) ? (~ pudi[5]) : pudi[5]; and(wire_n1lliO_dataout, wire_n1O1iO_dataout, n1O01i); assign wire_n1lllii_dataout = (((((~ wire_nl1llii_o) & nlOO00lO) | (wire_nl1llii_o & nlOO0i1i)) | (nlOO0i0O & nlOO0i0i)) === 1'b1) ? wire_n1l11lO_dataout : (nlOO0i1l | nlOO0i1O); and(wire_n1llOl_dataout, wire_n1O1li_dataout, n1O01i); and(wire_n1llOO_dataout, n1OiOi, n1O01l); assign wire_n1lO_dataout = (nO === 1'b1) ? (~ pudi[6]) : pudi[6]; and(wire_n1lO0i_dataout, n0110i, ~(n10O0ii)); and(wire_n1lO0l_dataout, wire_n1lOil_dataout, ~((~ n1OiOi))); and(wire_n1lO0O_dataout, n10O00O, ~((~ n1OiOi))); and(wire_n1lO1i_dataout, n0111i, ~(n10O0ii)); and(wire_n1lO1l_dataout, n0111l, ~(n10O0ii)); and(wire_n1lO1O_dataout, n0111O, ~(n10O0ii)); and(wire_n1lOii_dataout, wire_n1lOiO_dataout, ~((~ n1OiOi))); and(wire_n1lOil_dataout, (~ n10O00l), ~(n10O00O)); and(wire_n1lOiO_dataout, n10O00l, ~(n10O00O)); and(wire_n1lOlO_dataout, n010OO, ~(n10O0ii)); and(wire_n1lOOi_dataout, n01i1i, ~(n10O0ii)); and(wire_n1lOOl_dataout, n01i1l, ~(n10O0ii)); and(wire_n1lOOO_dataout, n01i1O, ~(n10O0ii)); assign wire_n1O_dataout = (wa_6g_en === 1'b1) ? wire_nlOi_dataout : nl1lil; and(wire_n1O00i_dataout, max_rlv_sel[0], ~((~ pmadwidth[0]))); and(wire_n1O00l_dataout, max_rlv_sel[1], ~((~ pmadwidth[0]))); assign wire_n1O00O_dataout = ((~ pmadwidth[0]) === 1'b1) ? max_rlv_sel[0] : wire_n1O0lO_o[0]; assign wire_n1O0ii_dataout = ((~ pmadwidth[0]) === 1'b1) ? max_rlv_sel[1] : wire_n1O0lO_o[1]; assign wire_n1O0il_dataout = ((~ pmadwidth[0]) === 1'b1) ? max_rlv_sel[2] : wire_n1O0lO_o[2]; assign wire_n1O0iO_dataout = ((~ pmadwidth[0]) === 1'b1) ? max_rlv_sel[3] : wire_n1O0lO_o[3]; assign wire_n1O0li_dataout = ((~ pmadwidth[0]) === 1'b1) ? max_rlv_sel[4] : wire_n1O0lO_o[4]; assign wire_n1O0ll_dataout = ((~ pmadwidth[0]) === 1'b1) ? (~ n10O0li) : wire_n1O0lO_o[5]; and(wire_n1O10i_dataout, wire_n1O10O_dataout, ~((~ n1OiOi))); and(wire_n1O10l_dataout, (~ n10O0il), ~(n10O0iO)); assign wire_n1O10lO_dataout = (((wire_nl1llll_o ^ wire_nl1llli_o) & nlOO0iOi) === 1'b1) ? wire_n1lllii_dataout : (nlOO0iOl | nlOO0ilO); and(wire_n1O10O_dataout, n10O0il, ~(n10O0iO)); and(wire_n1O11l_dataout, n10O0iO, ~((~ n1OiOi))); and(wire_n1O11O_dataout, wire_n1O10l_dataout, ~((~ n1OiOi))); and(wire_n1O1iO_dataout, n1OOOl, ~((~ n1OiOi))); and(wire_n1O1li_dataout, (~ n1OOOl), ~((~ n1OiOi))); assign wire_n1Oi_dataout = (nO === 1'b1) ? (~ pudi[7]) : pudi[7]; and(wire_n1Oiii_dataout, n1Oi1O, n1OiOi); and(wire_n1Oiil_dataout, n1Oi0i, n1OiOi); and(wire_n1OiiO_dataout, n1iiill, n1OiOi); and(wire_n1Oili_dataout, wire_n1Oill_o, n1OiOi); assign wire_n1Ol_dataout = (nO === 1'b1) ? (~ pudi[10]) : pudi[10]; assign wire_n1Ol0iO_dataout = (wire_n1Ol0OO_o[5] === 1'b1) ? wire_n1Ol0Ol_o[0] : wire_n1Oli1i_dataout; assign wire_n1Ol0li_dataout = (wire_n1Ol0OO_o[5] === 1'b1) ? wire_n1Ol0Ol_o[1] : wire_n1Oli1l_dataout; assign wire_n1Ol0ll_dataout = (wire_n1Ol0OO_o[5] === 1'b1) ? wire_n1Ol0Ol_o[2] : wire_n1Oli1O_dataout; assign wire_n1Ol0lO_dataout = (wire_n1Ol0OO_o[5] === 1'b1) ? wire_n1Ol0Ol_o[3] : wire_n1Oli0l_dataout; assign wire_n1Ol0Oi_dataout = (wire_n1Ol0OO_o[5] === 1'b1) ? wire_n1Ol0Ol_o[4] : wire_n1Oli0O_dataout; assign wire_n1Ol10O_dataout = (((~ r8b10b_dec_ibm_en[0]) & (~ r8b10b_dec_ibm_en[1])) === 1'b1) ? ((~ nlOOi11i) & ((~ ((nlOO0O0i | (nlOO0O1O | nlOO0O1l)) | (nlOO0O1i | (nlOO0lOO | (nlOO0lOl | nlOO0lOi))))) & (~ (((nlOO0llO | nlOO0lll) | ((~ (((nlOO0lli | nlOO0liO) | (wire_nl1lliO_o & ((~ wire_nl1llil_o) & nlOO0lil))) | ((~ wire_nl1lliO_o) & (wire_nl1llil_o & nlOO0lii)))) & ((~ nlOO0l0O) & (((~ wire_nl1llli_o) & nlOO0l0l) | (wire_nl1llli_o & nlOO0l0i))))) | ((((~ wire_nl1llOi_o) & nlOO0l0l) | (wire_nl1llOi_o & nlOO0l0i)) & (nlOO0liO | (nlOO0lli | nlOO0l0O))))))) : (~ ((((((((((((((nlOOi11i | (nlOO0OOO | nlOO0OOl)) | ((~ wire_nl1lliO_o) & ((~ wire_nl1llil_o) & nlOO0OOi))) | (wire_nl1lliO_o & (wire_nl1llil_o & nlOO0OlO))) | ((wire_nl1llOi_o & (wire_nl1lllO_o & (wire_nl1llll_o & wire_nl1llli_o))) | ((~ wire_nl1llOi_o) & ((~ wire_nl1lllO_o) & ((~ wire_nl1llll_o) & (~ wire_nl1llli_o)))))) | ((~ wire_nl1lllO_o) & ((~ wire_nl1llll_o) & ((~ wire_nl1llli_o) & ((~ wire_nl1lliO_o) & (~ wire_nl1llil_o)))))) | (wire_nl1lllO_o & (wire_nl1llll_o & (wire_nl1llli_o & (wire_nl1lliO_o & wire_nl1llil_o))))) | ((~ wire_nl1llOi_o) & ((~ wire_nl1lllO_o) & ((~ wire_nl1llll_o) & nlOO0Oll)))) | (wire_nl1llOi_o & (wire_nl1lllO_o & (wire_nl1llll_o & nlOO0Oli)))) | ((((~ wire_nl1llOi_o) & ((~ wire_nl1lllO_o) & ((~ wire_nl1llll_o) & wire_nl1lliO_o))) | (wire_nl1llOi_o & (wire_nl1lllO_o & (wire_nl1llll_o & (~ wire_nl1lliO_o))))) & (~ nlOO0OiO))) | (nlOO0OiO & ((wire_nl1lllO_o & nlOO0Oil) | ((~ wire_nl1lllO_o) & nlOO0Oii)))) | (((~ wire_nl1llOi_o) & ((~ wire_nl1lllO_o) & ((~ wire_nl1llll_o) & nlOO0Oli))) & (~ nlOO0OlO))) | ((wire_nl1llOi_o & (wire_nl1lllO_o & (wire_nl1llll_o & nlOO0Oll))) & (~ nlOO0OOi))) | (r8b10b_dec_ibm_en[1] & ((((((~ wire_nl1lliO_o) & ((~ wire_nl1llil_o) & nlOO0O0O)) | nlOO0OOl) | (((~ wire_nl1lliO_o) | (~ wire_nl1llil_o)) & nlOO0OOi)) | ((~ wire_nl1lliO_o) & ((~ wire_nl1llil_o) & (~ wire_nl1llii_o)))) & ((nlOO0Oii | (nlOO0Oii & nlOO0O0l)) | (nlOO0O0l & ((~ wire_nl1llll_o) | (~ wire_nl1llli_o))))))) | (r8b10b_dec_ibm_en[1] & (((((wire_nl1lliO_o & (wire_nl1llil_o & nlOO0O0O)) | nlOO0OOO) | ((wire_nl1lliO_o | wire_nl1llil_o) & nlOO0OlO)) | (wire_nl1lliO_o & (wire_nl1llil_o & wire_nl1llii_o))) & ((nlOO0Oil | (nlOO0Oil & (wire_nl1llOi_o | wire_nl1lllO_o))) | ((wire_nl1llOi_o & wire_nl1lllO_o) & (wire_nl1llll_o | wire_nl1llli_o))))))); and(wire_n1Oli0l_dataout, n1Ol00O, nlOOi11l); and(wire_n1Oli0O_dataout, n1Ol0ii, nlOOi11l); and(wire_n1Oli1i_dataout, n1Ol01O, nlOOi11l); and(wire_n1Oli1l_dataout, n1Ol00i, nlOOi11l); and(wire_n1Oli1O_dataout, n1Ol00l, nlOOi11l); and(wire_n1Ollil_dataout, wire_n1OO1li_dataout, n1OO01l); and(wire_n1OllOi_dataout, wire_n1OO1ll_dataout, n1OO01l); and(wire_n1OllOl_dataout, nlli0lO, n1OO01O); and(wire_n1OllOO_dataout, n011l0i, ~(nlOOi1li)); and(wire_n1OlO0i_dataout, n011lil, ~(nlOOi1li)); and(wire_n1OlO0l_dataout, wire_n1OlOil_dataout, ~((~ nlli0lO))); and(wire_n1OlO0O_dataout, nlOOi1iO, ~((~ nlli0lO))); and(wire_n1OlO1i_dataout, n011l0l, ~(nlOOi1li)); and(wire_n1OlO1l_dataout, n011l0O, ~(nlOOi1li)); and(wire_n1OlO1O_dataout, n011lii, ~(nlOOi1li)); and(wire_n1OlOii_dataout, wire_n1OlOiO_dataout, ~((~ nlli0lO))); and(wire_n1OlOil_dataout, (~ nlOOi1il), ~(nlOOi1iO)); and(wire_n1OlOiO_dataout, nlOOi1il, ~(nlOOi1iO)); and(wire_n1OlOlO_dataout, n0101iO, ~(nlOOi1li)); and(wire_n1OlOOi_dataout, n0101li, ~(nlOOi1li)); and(wire_n1OlOOl_dataout, n0101ll, ~(nlOOi1li)); and(wire_n1OlOOO_dataout, n0101lO, ~(nlOOi1li)); assign wire_n1OO_dataout = (nO === 1'b1) ? (~ pudi[11]) : pudi[11]; and(wire_n1OO0Oi_dataout, n1OO0iO, nlli0lO); and(wire_n1OO0Ol_dataout, n1OO0li, nlli0lO); and(wire_n1OO0OO_dataout, n1iiili, nlli0lO); and(wire_n1OO10i_dataout, wire_n1OO10O_dataout, ~((~ nlli0lO))); and(wire_n1OO10l_dataout, wire_n1OO1ii_dataout, ~((~ nlli0lO))); and(wire_n1OO10O_dataout, (~ nlOOi1ll), ~(nlOOi1lO)); and(wire_n1OO11i_dataout, n0101Oi, ~(nlOOi1li)); and(wire_n1OO11O_dataout, nlOOi1lO, ~((~ nlli0lO))); and(wire_n1OO1ii_dataout, nlOOi1ll, ~(nlOOi1lO)); and(wire_n1OO1li_dataout, n011l1l, ~((~ nlli0lO))); and(wire_n1OO1ll_dataout, (~ n011l1l), ~((~ nlli0lO))); and(wire_n1OOi1i_dataout, wire_n1OOi1l_o, nlli0lO); assign wire_n1OOOi_dataout = ((~ pmadwidth[0]) === 1'b1) ? n10O0ll : n10O0lO; assign wire_ni_dataout = (rindv_rx === 1'b1) ? gen2ngen1 : gen2ngen1_bundle; assign wire_ni0i_dataout = (wa_6g_en === 1'b1) ? wire_nl1l1il_dataout : wire_niii1i_dataout; assign wire_ni0l_dataout = (wa_6g_en === 1'b1) ? wire_nl1iOil_dataout : wire_nii01i_dataout; and(wire_ni0lO_dataout, ni0li, ~(scan_mode)); assign wire_ni0O_dataout = (wa_6g_en === 1'b1) ? wire_nl1iOiO_dataout : wire_nii01l_dataout; assign wire_ni1i_dataout = (wa_6g_en === 1'b1) ? wire_nl1l10l_dataout : wire_nii0Oi_dataout; assign wire_ni1l_dataout = (wa_6g_en === 1'b1) ? wire_nl1l10O_dataout : wire_nii0Ol_dataout; assign wire_ni1O_dataout = (wa_6g_en === 1'b1) ? wire_nl1l1ii_dataout : wire_nii0OO_dataout; assign wire_nii_dataout = (wa_6g_en === 1'b1) ? nl0100O : niii0l; and(wire_nii00i_dataout, nil0Ol, ~(rrxpcsbypass_en)); and(wire_nii00l_dataout, nil0OO, ~(rrxpcsbypass_en)); and(wire_nii00O_dataout, nili1i, ~(rrxpcsbypass_en)); and(wire_nii01i_dataout, nil0ll, ~(rrxpcsbypass_en)); and(wire_nii01l_dataout, nil0lO, ~(rrxpcsbypass_en)); and(wire_nii01O_dataout, nil0Oi, ~(rrxpcsbypass_en)); assign wire_nii0i_dataout = (wa_6g_en === 1'b1) ? nl0100O : nl1llO; assign wire_nii0ii_dataout = (rrxpcsbypass_en === 1'b1) ? nliOlO : nil01i; assign wire_nii0il_dataout = (rrxpcsbypass_en === 1'b1) ? nliOOi : nil01l; assign wire_nii0iO_dataout = (rrxpcsbypass_en === 1'b1) ? nliOOl : nil01O; and(wire_nii0l_dataout, nl010ii, wa_6g_en); assign wire_nii0li_dataout = (rrxpcsbypass_en === 1'b1) ? nliOOO : nil00i; assign wire_nii0ll_dataout = (rrxpcsbypass_en === 1'b1) ? nll11i : nil00l; assign wire_nii0lO_dataout = (rrxpcsbypass_en === 1'b1) ? nll11l : nil00O; assign wire_nii0O_dataout = (wa_6g_en === 1'b1) ? wire_nl1iOlO_dataout : wire_nii00l_dataout; assign wire_nii0Oi_dataout = (rrxpcsbypass_en === 1'b1) ? nll11O : nil0ii; assign wire_nii0Ol_dataout = (rrxpcsbypass_en === 1'b1) ? nll10i : nil0il; assign wire_nii0OO_dataout = (rrxpcsbypass_en === 1'b1) ? wire_niii1l_dataout : nil0iO; assign wire_nii1i_dataout = (wa_6g_en === 1'b1) ? nl0101O : nl1lil; assign wire_nii1l_dataout = (wa_6g_en === 1'b1) ? nl0100i : nl1liO; assign wire_nii1O_dataout = (wa_6g_en === 1'b1) ? nl0100l : nl1lli; assign wire_niii_dataout = (wa_6g_en === 1'b1) ? wire_nl1iOli_dataout : wire_nii01O_dataout; assign wire_niii1i_dataout = (rrxpcsbypass_en === 1'b1) ? wire_niii1O_dataout : nil0li; and(wire_niii1l_dataout, nll10l, ~((~ pmadwidth[0]))); and(wire_niii1O_dataout, nll1ii, ~((~ pmadwidth[0]))); assign wire_niiii_dataout = (wa_6g_en === 1'b1) ? wire_nl1iOOi_dataout : wire_nii00O_dataout; and(wire_niiil_dataout, wire_nl1l1OO_dataout, wa_6g_en); and(wire_niiiO_dataout, wire_nl1l01i_dataout, wa_6g_en); assign wire_niiiOO_dataout = (nill0l === 1'b1) ? comp_pat[7] : comp_pat[0]; assign wire_niil_dataout = (wa_6g_en === 1'b1) ? wire_nl1iOll_dataout : wire_nii00i_dataout; assign wire_niil0i_dataout = (nill0l === 1'b1) ? comp_pat[3] : comp_pat[4]; assign wire_niil0l_dataout = (nill0l === 1'b1) ? comp_pat[2] : comp_pat[5]; assign wire_niil0O_dataout = (nill0l === 1'b1) ? comp_pat[1] : comp_pat[6]; assign wire_niil1i_dataout = (nill0l === 1'b1) ? comp_pat[6] : comp_pat[1]; assign wire_niil1l_dataout = (nill0l === 1'b1) ? comp_pat[5] : comp_pat[2]; assign wire_niil1O_dataout = (nill0l === 1'b1) ? comp_pat[4] : comp_pat[3]; assign wire_niili_dataout = (nO === 1'b1) ? (~ pudr[0]) : pudr[0]; assign wire_niilii_dataout = (nill0l === 1'b1) ? comp_pat[0] : comp_pat[7]; assign wire_niilil_dataout = (nill0l === 1'b1) ? comp_pat[15] : comp_pat[8]; assign wire_niiliO_dataout = (nill0l === 1'b1) ? comp_pat[14] : comp_pat[9]; assign wire_niill_dataout = (nO === 1'b1) ? (~ pudr[1]) : pudr[1]; assign wire_niilli_dataout = (nill0l === 1'b1) ? comp_pat[13] : comp_pat[10]; assign wire_niilll_dataout = (nill0l === 1'b1) ? comp_pat[12] : comp_pat[11]; assign wire_niillO_dataout = (nill0l === 1'b1) ? comp_pat[11] : comp_pat[12]; assign wire_niilO_dataout = (nO === 1'b1) ? (~ pudr[2]) : pudr[2]; assign wire_niilOi_dataout = (nill0l === 1'b1) ? comp_pat[10] : comp_pat[13]; assign wire_niilOl_dataout = (nill0l === 1'b1) ? comp_pat[9] : comp_pat[14]; assign wire_niilOO_dataout = (nill0l === 1'b1) ? comp_pat[8] : comp_pat[15]; assign wire_niiO_dataout = (wa_6g_en === 1'b1) ? wire_nl1iOlO_dataout : wire_nii00l_dataout; assign wire_niiO0i_dataout = (nill0l === 1'b1) ? comp_pat[6] : comp_pat[3]; assign wire_niiO0l_dataout = (nill0l === 1'b1) ? comp_pat[5] : comp_pat[4]; assign wire_niiO0O_dataout = (nill0l === 1'b1) ? comp_pat[4] : comp_pat[5]; assign wire_niiO1i_dataout = (nill0l === 1'b1) ? comp_pat[9] : comp_pat[0]; assign wire_niiO1l_dataout = (nill0l === 1'b1) ? comp_pat[8] : comp_pat[1]; assign wire_niiO1O_dataout = (nill0l === 1'b1) ? comp_pat[7] : comp_pat[2]; assign wire_niiOi_dataout = (nO === 1'b1) ? (~ pudr[3]) : pudr[3]; assign wire_niiOii_dataout = (nill0l === 1'b1) ? comp_pat[3] : comp_pat[6]; assign wire_niiOil_dataout = (nill0l === 1'b1) ? comp_pat[2] : comp_pat[7]; assign wire_niiOiO_dataout = (nill0l === 1'b1) ? comp_pat[1] : comp_pat[8]; assign wire_niiOl_dataout = (nO === 1'b1) ? (~ pudr[4]) : pudr[4]; assign wire_niiOli_dataout = (nill0l === 1'b1) ? comp_pat[0] : comp_pat[9]; assign wire_niiOO_dataout = (nO === 1'b1) ? (~ pudr[5]) : pudr[5]; assign wire_nil_dataout = (wa_6g_en === 1'b1) ? nl010ii : nlO01ii; assign wire_nil0i_dataout = (nO === 1'b1) ? (~ pudr[9]) : pudr[9]; assign wire_nil0l_dataout = (nO === 1'b1) ? (~ pudi[0]) : pudi[0]; assign wire_nil0O_dataout = (nO === 1'b1) ? (~ pudi[1]) : pudi[1]; assign wire_nil10l_dataout = (n1i1OOi === 1'b1) ? (n1i1OOO | n1i1OOl) : (n1i011l | n1i011i); assign wire_nil1i_dataout = (nO === 1'b1) ? (~ pudr[6]) : pudr[6]; assign wire_nil1l_dataout = (nO === 1'b1) ? (~ pudr[7]) : pudr[7]; assign wire_nil1O_dataout = (nO === 1'b1) ? (~ pudr[8]) : pudr[8]; assign wire_nili_dataout = (wa_6g_en === 1'b1) ? wire_nl1iOOi_dataout : wire_nii00O_dataout; assign wire_nilii_dataout = (nO === 1'b1) ? (~ pudi[2]) : pudi[2]; assign wire_nilil_dataout = (nO === 1'b1) ? (~ pudi[3]) : pudi[3]; assign wire_niliO_dataout = (nO === 1'b1) ? (~ pudi[4]) : pudi[4]; and(wire_nill_dataout, wire_nl1l01l_dataout, wa_6g_en); assign wire_nilli_dataout = (nO === 1'b1) ? (~ pudi[5]) : pudi[5]; and(wire_nillii_dataout, ((nil1ll | n1i011O) | (n1iiiOi & nil1il)), n1ii10i); assign wire_nillil_dataout = (n1ii10i === 1'b1) ? ((nil1lO | n1i010i) | (n1iiiOi & nil1iO)) : ((nil1li | wire_nil10l_dataout) | (n1iiiOi & niii0O)); assign wire_nilll_dataout = (nO === 1'b1) ? (~ pudi[6]) : pudi[6]; assign wire_nilllO_dataout = (n1i010O === 1'b1) ? wire_niiiOO_dataout : wire_nilOii_dataout; assign wire_nillO_dataout = (nO === 1'b1) ? (~ pudi[7]) : pudi[7]; assign wire_nillOi_dataout = (n1i010O === 1'b1) ? wire_niil1i_dataout : wire_nilOil_dataout; assign wire_nillOl_dataout = (n1i010O === 1'b1) ? wire_niil1l_dataout : wire_nilOiO_dataout; assign wire_nillOO_dataout = (n1i010O === 1'b1) ? wire_niil1O_dataout : wire_nilOli_dataout; and(wire_nilO_dataout, wire_nl1l01O_dataout, wa_6g_en); assign wire_nilO0i_dataout = (n1i010O === 1'b1) ? wire_niilii_dataout : wire_nilOOl_dataout; assign wire_nilO0l_dataout = (n1i010O === 1'b1) ? nilili : wire_nilOOO_dataout; and(wire_nilO0O_dataout, wire_niO11i_dataout, ~(n1i010O)); assign wire_nilO1i_dataout = (n1i010O === 1'b1) ? wire_niil0i_dataout : wire_nilOll_dataout; assign wire_nilO1l_dataout = (n1i010O === 1'b1) ? wire_niil0l_dataout : wire_nilOlO_dataout; assign wire_nilO1O_dataout = (n1i010O === 1'b1) ? wire_niil0O_dataout : wire_nilOOi_dataout; assign wire_nilOi_dataout = (nO === 1'b1) ? (~ pudi[8]) : pudi[8]; assign wire_nilOii_dataout = (n1i010l === 1'b1) ? nili1l : wire_niOill_o; assign wire_nilOil_dataout = (n1i010l === 1'b1) ? nili1O : wire_niOilO_o; assign wire_nilOiO_dataout = (n1i010l === 1'b1) ? nili0i : wire_niOiOi_o; assign wire_nilOl_dataout = (nO === 1'b1) ? (~ pudi[9]) : pudi[9]; assign wire_nilOli_dataout = (n1i010l === 1'b1) ? nili0l : wire_niOiOl_o; assign wire_nilOll_dataout = (n1i010l === 1'b1) ? nili0O : wire_niOiOO_o; assign wire_nilOlO_dataout = (n1i010l === 1'b1) ? niliii : wire_niOl1i_o; assign wire_nilOO_dataout = (n1iii1l === 1'b1) ? wire_nl0li_dataout : wire_nl10l_dataout; assign wire_nilOOi_dataout = (n1i010l === 1'b1) ? niliil : wire_niOl1l_o; assign wire_nilOOl_dataout = (n1i010l === 1'b1) ? niliiO : wire_niOl1O_o; assign wire_nilOOO_dataout = (n1i010l === 1'b1) ? nilili : wire_niOl0i_dataout; assign wire_niO0i_dataout = (n1iii1l === 1'b1) ? wire_nl0Ol_dataout : wire_nl1iO_dataout; assign wire_niO0l_dataout = (n1iii1l === 1'b1) ? wire_nl0OO_dataout : wire_nl1li_dataout; assign wire_niO0O_dataout = (n1iii1l === 1'b1) ? wire_nli1i_dataout : wire_nl1ll_dataout; assign wire_niO10l_dataout = (n1i01ii === 1'b1) ? wire_niiiOO_dataout : nilill; assign wire_niO10O_dataout = (n1i01ii === 1'b1) ? wire_niil1i_dataout : nililO; and(wire_niO11i_dataout, wire_niOl0l_dataout, ~(n1i010l)); assign wire_niO1i_dataout = (n1iii1l === 1'b1) ? wire_nl0ll_dataout : wire_nl10O_dataout; assign wire_niO1ii_dataout = (n1i01ii === 1'b1) ? wire_niil1l_dataout : niliOi; assign wire_niO1il_dataout = (n1i01ii === 1'b1) ? wire_niil1O_dataout : niliOl; assign wire_niO1iO_dataout = (n1i01ii === 1'b1) ? wire_niil0i_dataout : niliOO; assign wire_niO1l_dataout = (n1iii1l === 1'b1) ? wire_nl0lO_dataout : wire_nl1ii_dataout; assign wire_niO1li_dataout = (n1i01ii === 1'b1) ? wire_niil0l_dataout : nill1i; assign wire_niO1ll_dataout = (n1i01ii === 1'b1) ? wire_niil0O_dataout : nill1l; assign wire_niO1lO_dataout = (n1i01ii === 1'b1) ? wire_niilii_dataout : nill1O; assign wire_niO1O_dataout = (n1iii1l === 1'b1) ? wire_nl0Oi_dataout : wire_nl1il_dataout; and(wire_niOi_dataout, wire_nl1l00i_dataout, wa_6g_en); assign wire_niOi0i_dataout = (nill0l === 1'b1) ? niOlOO : niOllO; assign wire_niOi0l_dataout = (nill0l === 1'b1) ? niOlOl : niOlOi; assign wire_niOi0O_dataout = (nill0l === 1'b1) ? niOlOi : niOlOl; assign wire_niOi1i_dataout = (nill0l === 1'b1) ? niOO1O : niOlil; assign wire_niOi1l_dataout = (nill0l === 1'b1) ? niOO1l : niOlli; assign wire_niOi1O_dataout = (nill0l === 1'b1) ? niOO1i : niOlll; assign wire_niOii_dataout = (n1iii1l === 1'b1) ? wire_nli1l_dataout : wire_nl1lO_dataout; assign wire_niOiii_dataout = (nill0l === 1'b1) ? niOllO : niOlOO; assign wire_niOiil_dataout = (nill0l === 1'b1) ? niOlll : niOO1i; assign wire_niOiiO_dataout = (nill0l === 1'b1) ? niOlli : niOO1l; assign wire_niOil_dataout = (n1iii1l === 1'b1) ? wire_nli1O_dataout : wire_nl1Oi_dataout; assign wire_niOili_dataout = (nill0l === 1'b1) ? niOlil : niOO1O; assign wire_niOiO_dataout = (n1iii1l === 1'b1) ? wire_nli0i_dataout : wire_nl1Ol_dataout; and(wire_niOl_dataout, wire_nl1l00l_dataout, wa_6g_en); assign wire_niOl0i_dataout = (n1i00Oi === 1'b1) ? niOOOO : nl11ii; assign wire_niOl0l_dataout = (n1i00Oi === 1'b1) ? niOO0i : nl11il; assign wire_niOli_dataout = (n1iii1l === 1'b1) ? wire_nli0l_dataout : wire_nl1OO_dataout; assign wire_niOll_dataout = (n1iii1l === 1'b1) ? wire_nli0O_dataout : wire_nl01i_dataout; assign wire_niOlO_dataout = (n1iii1l === 1'b1) ? wire_nliii_dataout : wire_nl01l_dataout; and(wire_niOO_dataout, wire_nl1l00O_dataout, wa_6g_en); assign wire_niOOi_dataout = (n1iii1l === 1'b1) ? wire_nliil_dataout : wire_nl01O_dataout; assign wire_niOOl_dataout = (n1iii1l === 1'b1) ? wire_nliiO_dataout : wire_nl00i_dataout; assign wire_niOOO_dataout = (n1iii1l === 1'b1) ? wire_nlili_dataout : wire_nl00l_dataout; assign wire_nl0000i_dataout = (n111lOl === 1'b1) ? wire_nl00O1i_o : wire_nl00iiO_dataout; assign wire_nl0000l_dataout = (n111lOl === 1'b1) ? wire_nl00O1l_o : wire_nl00ili_dataout; assign wire_nl0000O_dataout = (n111lOl === 1'b1) ? wire_nl00O1O_o : wire_nl00ill_dataout; assign wire_nl0001i_dataout = (n111lOl === 1'b1) ? wire_nl00lOi_o : wire_nl00i0O_dataout; assign wire_nl0001l_dataout = (n111lOl === 1'b1) ? wire_nl00lOl_o : wire_nl00iii_dataout; assign wire_nl0001O_dataout = (n111lOl === 1'b1) ? wire_nl00lOO_o : wire_nl00iil_dataout; assign wire_nl000i_dataout = ((~ pmadwidth[0]) === 1'b1) ? (((~ nl1ill) & (n1i0lll & nlOiO1i)) | (nl1ill & (n1i0lll & (nlOii0l & (~ nlOii0i))))) : (n1i0llO | n1i0lll); assign wire_nl000ii_dataout = (n111lOl === 1'b1) ? wire_nl00O0i_o : wire_nl00ilO_dataout; assign wire_nl000il_dataout = (n111lOl === 1'b1) ? wire_nl00O0l_o : wire_nl00iOi_dataout; assign wire_nl000iO_dataout = (n111lOl === 1'b1) ? wire_nl00O0O_o : wire_nl00iOl_dataout; and(wire_nl000li_dataout, wire_nl00iOO_dataout, ~(n111lOl)); and(wire_nl000ll_dataout, wire_nl00l1i_dataout, ~(n111lOl)); and(wire_nl000lO_dataout, wire_nl00l1l_dataout, ~(n111lOl)); and(wire_nl000Oi_dataout, wire_nl00l1O_dataout, ~(n111lOl)); assign wire_nl000Ol_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl00OiO_o : wire_nl00lii_o; assign wire_nl000OO_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl00Oli_o : wire_nl00lil_o; assign wire_nl0010i_dataout = (n111lOO === 1'b1) ? wire_nl0i1il_o : wire_nl000iO_dataout; assign wire_nl0010l_dataout = (n111lOO === 1'b1) ? wire_nl0i1iO_o : wire_nl000li_dataout; assign wire_nl0010O_dataout = (n111lOO === 1'b1) ? wire_nl0i1li_o : wire_nl000ll_dataout; assign wire_nl0011i_dataout = (n111lOO === 1'b1) ? wire_nl0i10l_o : wire_nl0000O_dataout; assign wire_nl0011l_dataout = (n111lOO === 1'b1) ? wire_nl0i10O_o : wire_nl000ii_dataout; assign wire_nl0011O_dataout = (n111lOO === 1'b1) ? wire_nl0i1ii_o : wire_nl000il_dataout; assign wire_nl001i_dataout = ((~ pmadwidth[0]) === 1'b1) ? (((~ nl1ill) & (n1i0liO & nlOiO1l)) | (nl1ill & (n1i0liO & (nlOii1O & (~ nlOii1l))))) : (n1i0lli | n1i0liO); assign wire_nl001ii_dataout = (n111lOO === 1'b1) ? wire_nl0i1ll_o : wire_nl000lO_dataout; assign wire_nl001il_dataout = (n111lOO === 1'b1) ? wire_nl0i1lO_o : wire_nl000Oi_dataout; assign wire_nl001iO_dataout = (n111lOl === 1'b1) ? wire_nl00l0O_o : wire_nl000Ol_dataout; assign wire_nl001li_dataout = (n111lOl === 1'b1) ? wire_nl00lii_o : wire_nl000OO_dataout; assign wire_nl001ll_dataout = (n111lOl === 1'b1) ? wire_nl00lil_o : wire_nl00i1i_dataout; assign wire_nl001lO_dataout = (n111lOl === 1'b1) ? wire_nl00liO_o : wire_nl00i1l_dataout; assign wire_nl001Oi_dataout = (n111lOl === 1'b1) ? wire_nl00lli_o : wire_nl00i1O_dataout; assign wire_nl001Ol_dataout = (n111lOl === 1'b1) ? wire_nl00lll_o : wire_nl00i0i_dataout; assign wire_nl001OO_dataout = (n111lOl === 1'b1) ? wire_nl00llO_o : wire_nl00i0l_dataout; assign wire_nl00i_dataout = (nO === 1'b1) ? (~ pudr[14]) : pudr[14]; assign wire_nl00i0i_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl00OOl_o : wire_nl00llO_o; assign wire_nl00i0l_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl00OOO_o : wire_nl00lOi_o; assign wire_nl00i0O_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl0i11i_o : wire_nl00lOl_o; assign wire_nl00i1i_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl00Oll_o : wire_nl00liO_o; assign wire_nl00i1l_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl00OlO_o : wire_nl00lli_o; assign wire_nl00i1O_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl00OOi_o : wire_nl00lll_o; assign wire_nl00ii_dataout = ((~ pmadwidth[0]) === 1'b1) ? (((~ nl1ill) & (n1i0lOO & nlOilOO)) | (nl1ill & (n1i0lOO & (nlOiiii & (~ nlOii0O))))) : ((n1i0O1i | n1i0lOO) | (~ (n1i0lOi48 ^ n1i0lOi47))); assign wire_nl00iii_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl0i11l_o : wire_nl00lOO_o; assign wire_nl00iil_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl0i11O_o : wire_nl00O1i_o; assign wire_nl00iiO_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl0i10i_o : wire_nl00O1l_o; assign wire_nl00ili_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl0i10l_o : wire_nl00O1O_o; assign wire_nl00ill_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl0i10O_o : wire_nl00O0i_o; assign wire_nl00ilO_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl0i1ii_o : wire_nl00O0l_o; assign wire_nl00iOi_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl0i1il_o : wire_nl00O0O_o; assign wire_nl00iOl_dataout = ((~ comp_pat_size[0]) === 1'b1) ? wire_nl0i1iO_o : wire_nl00l0i_o; and(wire_nl00iOO_dataout, wire_nl0i1li_o, (~ comp_pat_size[0])); assign wire_nl00l_dataout = (nO === 1'b1) ? (~ pudr[15]) : pudr[15]; and(wire_nl00l1i_dataout, wire_nl0i1ll_o, (~ comp_pat_size[0])); and(wire_nl00l1l_dataout, wire_nl0i1lO_o, (~ comp_pat_size[0])); and(wire_nl00l1O_dataout, wire_nl00l0l_o, (~ comp_pat_size[0])); assign wire_nl00li_dataout = ((~ pmadwidth[0]) === 1'b1) ? (((~ nl1ill) & (n1i0O0O & nlOilOl)) | ((nl1ill & ((n1i0O0O & (nlOiiiO & (~ nlOiiil))) & (n1i0O0i44 ^ n1i0O0i43))) & (n1i0O1l46 ^ n1i0O1l45))) : (n1i0Oii | n1i0O0O); assign wire_nl00O_dataout = (nO === 1'b1) ? (~ pudr[16]) : pudr[16]; assign wire_nl00Oi_dataout = ((~ pmadwidth[0]) === 1'b1) ? (((((~ nl1ill) & ((n1ii11i & nlOiilO) & (n1i0OOl36 ^ n1i0OOl35))) & (n1i0OlO38 ^ n1i0OlO37)) | (nl1ill & (n1ii11i & ((nlOiill & (~ nlOiili)) & (n1i0Oli40 ^ n1i0Oli39))))) | (~ (n1i0Oil42 ^ n1i0Oil41))) : (n1ii11l | n1ii11i); and(wire_nl010l_dataout, (n1i0l1l | n1i0l1i), ~((~ pmadwidth[0]))); assign wire_nl011i_dataout = (autobytealign_dis === 1'b1) ? nl10ll : nl1lli; assign wire_nl011l_dataout = (autobytealign_dis === 1'b1) ? nl10Oi : nl1llO; and(wire_nl011O_dataout, (n1i0iOO | n1i0iOl), ~((~ pmadwidth[0]))); assign wire_nl01i_dataout = (nO === 1'b1) ? (~ pudr[11]) : pudr[11]; assign wire_nl01ii_dataout = ((~ pmadwidth[0]) === 1'b1) ? (((~ nl1ill) & (n1i0l1O & nlOiO0l)) | (nl1ill & (n1i0l1O & (nlOi0lO & (~ nlOi0ll))))) : (n1i0l0i | n1i0l1O); assign wire_nl01l_dataout = (nO === 1'b1) ? (~ pudr[12]) : pudr[12]; assign wire_nl01li_dataout = ((~ pmadwidth[0]) === 1'b1) ? (((~ nl1ill) & (n1i0l0l & nlOiO0i)) | (nl1ill & (n1i0l0l & (nlOi0Ol & (~ nlOi0Oi))))) : (n1i0l0O | n1i0l0l); assign wire_nl01O_dataout = (nO === 1'b1) ? (~ pudr[13]) : pudr[13]; assign wire_nl01O0i_dataout = (n111lOO === 1'b1) ? wire_nl00Oil_o : wire_nl001iO_dataout; assign wire_nl01O0l_dataout = (n111lOO === 1'b1) ? wire_nl00OiO_o : wire_nl001li_dataout; assign wire_nl01O0O_dataout = (n111lOO === 1'b1) ? wire_nl00Oli_o : wire_nl001ll_dataout; assign wire_nl01Oi_dataout = ((~ pmadwidth[0]) === 1'b1) ? (((~ nl1ill) & (n1i0lii & nlOiO1O)) | (nl1ill & (n1i0lii & (nlOii1i & (~ nlOi0OO))))) : (n1i0lil | n1i0lii); assign wire_nl01Oii_dataout = (n111lOO === 1'b1) ? wire_nl00Oll_o : wire_nl001lO_dataout; assign wire_nl01Oil_dataout = (n111lOO === 1'b1) ? wire_nl00OlO_o : wire_nl001Oi_dataout; assign wire_nl01OiO_dataout = (n111lOO === 1'b1) ? wire_nl00OOi_o : wire_nl001Ol_dataout; assign wire_nl01Oli_dataout = (n111lOO === 1'b1) ? wire_nl00OOl_o : wire_nl001OO_dataout; assign wire_nl01Oll_dataout = (n111lOO === 1'b1) ? wire_nl00OOO_o : wire_nl0001i_dataout; assign wire_nl01OlO_dataout = (n111lOO === 1'b1) ? wire_nl0i11i_o : wire_nl0001l_dataout; assign wire_nl01OOi_dataout = (n111lOO === 1'b1) ? wire_nl0i11l_o : wire_nl0001O_dataout; assign wire_nl01OOl_dataout = (n111lOO === 1'b1) ? wire_nl0i11O_o : wire_nl0000i_dataout; assign wire_nl01OOO_dataout = (n111lOO === 1'b1) ? wire_nl0i10i_o : wire_nl0000l_dataout; and(wire_nl0i_dataout, wire_nl1l0li_dataout, wa_6g_en); assign wire_nl0i00i_dataout = (n111O1l === 1'b1) ? wire_nl0i0iO_dataout : nl0101O; assign wire_nl0i00l_dataout = (n111O1l === 1'b1) ? wire_nl0i0li_dataout : nl0100i; assign wire_nl0i00O_dataout = (n111O1l === 1'b1) ? wire_nl0i0ll_dataout : nl0100l; assign wire_nl0i01i_dataout = (n111O1O === 1'b1) ? n110ill : wire_nl0i00O_dataout; assign wire_nl0i01l_dataout = (n111O1O === 1'b1) ? n110ilO : wire_nl0i0ii_dataout; assign wire_nl0i01O_dataout = (n111O1O === 1'b1) ? n110iOi : wire_nl0i0il_dataout; assign wire_nl0i0i_dataout = (n1ii11O === 1'b1) ? nliO0O : wire_nl0iOl_dataout; assign wire_nl0i0ii_dataout = (n111O1l === 1'b1) ? wire_nl0i0lO_dataout : nl0100O; assign wire_nl0i0il_dataout = (n111O1l === 1'b1) ? wire_nl0i0Oi_dataout : nl010ii; and(wire_nl0i0iO_dataout, wire_nl0i0Ol_o, ~(n111O1i)); assign wire_nl0i0l_dataout = (n1ii11O === 1'b1) ? nliOii : wire_nl0iOO_dataout; and(wire_nl0i0li_dataout, wire_nl0i0OO_o, ~(n111O1i)); and(wire_nl0i0ll_dataout, wire_nl0ii1i_o, ~(n111O1i)); and(wire_nl0i0lO_dataout, wire_nl0ii1l_o, ~(n111O1i)); assign wire_nl0i0O_dataout = (n1ii11O === 1'b1) ? nliOil : wire_nl0l1i_dataout; and(wire_nl0i0Oi_dataout, wire_nl0ii1O_o, ~(n111O1i)); assign wire_nl0i1i_dataout = (n1ii11O === 1'b1) ? nliO1O : wire_nl0ill_dataout; assign wire_nl0i1l_dataout = (n1ii11O === 1'b1) ? nliO0i : wire_nl0ilO_dataout; assign wire_nl0i1O_dataout = (n1ii11O === 1'b1) ? nliO0l : wire_nl0iOi_dataout; assign wire_nl0i1Ol_dataout = (n111O1O === 1'b1) ? (~ n110iiO) : wire_nl0i00i_dataout; assign wire_nl0i1OO_dataout = (n111O1O === 1'b1) ? (~ n110ili) : wire_nl0i00l_dataout; assign wire_nl0ii_dataout = (nO === 1'b1) ? (~ pudr[17]) : pudr[17]; assign wire_nl0ii0i_dataout = (nlli00i === 1'b1) ? wire_nl0iiiO_dataout : nl0101O; assign wire_nl0ii0l_dataout = (nlli00i === 1'b1) ? wire_nl0iili_dataout : nl0100i; assign wire_nl0ii0O_dataout = (nlli00i === 1'b1) ? wire_nl0iill_dataout : nl0100l; assign wire_nl0iii_dataout = (n1ii11O === 1'b1) ? nliOiO : wire_nl0l1l_dataout; assign wire_nl0iiii_dataout = (nlli00i === 1'b1) ? wire_nl0iilO_dataout : nl0100O; assign wire_nl0iiil_dataout = (nlli00i === 1'b1) ? wire_nl0iiOi_dataout : nl010ii; and(wire_nl0iiiO_dataout, wire_nl0iiOl_o[0], ~(wire_nl0iiOO_o)); and(wire_nl0iil_dataout, wire_nl0l1O_dataout, ~(n1ii11O)); and(wire_nl0iili_dataout, wire_nl0iiOl_o[1], ~(wire_nl0iiOO_o)); and(wire_nl0iill_dataout, wire_nl0iiOl_o[2], ~(wire_nl0iiOO_o)); and(wire_nl0iilO_dataout, wire_nl0iiOl_o[3], ~(wire_nl0iiOO_o)); and(wire_nl0iiO_dataout, wire_nl0l0i_dataout, ~(n1ii11O)); and(wire_nl0iiOi_dataout, wire_nl0iiOl_o[4], ~(wire_nl0iiOO_o)); assign wire_nl0il_dataout = (nO === 1'b1) ? (~ pudr[18]) : pudr[18]; assign wire_nl0il0i_dataout = (nlli00i === 1'b1) ? wire_nl0iliO_dataout : nl0100O; assign wire_nl0il0l_dataout = (nlli00i === 1'b1) ? wire_nl0illi_dataout : nl010ii; and(wire_nl0il0O_dataout, wire_nl0iiOl_o[0], ~(wire_nl0illl_o)); assign wire_nl0il1i_dataout = (nlli00i === 1'b1) ? wire_nl0il0O_dataout : nl0101O; assign wire_nl0il1l_dataout = (nlli00i === 1'b1) ? wire_nl0ilii_dataout : nl0100i; assign wire_nl0il1O_dataout = (nlli00i === 1'b1) ? wire_nl0ilil_dataout : nl0100l; and(wire_nl0ili_dataout, wire_nl0l0l_dataout, ~(n1ii11O)); and(wire_nl0ilii_dataout, wire_nl0iiOl_o[1], ~(wire_nl0illl_o)); and(wire_nl0ilil_dataout, wire_nl0iiOl_o[2], ~(wire_nl0illl_o)); and(wire_nl0iliO_dataout, wire_nl0iiOl_o[3], ~(wire_nl0illl_o)); and(wire_nl0ill_dataout, nliO1O, ~(n1ii10i)); and(wire_nl0illi_dataout, wire_nl0iiOl_o[4], ~(wire_nl0illl_o)); assign wire_nl0illO_dataout = (nlli00i === 1'b1) ? wire_nl0iO1l_dataout : nl0101O; and(wire_nl0ilO_dataout, nliO0i, ~(n1ii10i)); assign wire_nl0ilOi_dataout = (nlli00i === 1'b1) ? wire_nl0iO1O_dataout : nl0100i; assign wire_nl0ilOl_dataout = (nlli00i === 1'b1) ? wire_nl0iO0i_dataout : nl0100l; assign wire_nl0ilOO_dataout = (nlli00i === 1'b1) ? wire_nl0iO0l_dataout : nl0100O; assign wire_nl0iO_dataout = (nO === 1'b1) ? (~ pudr[19]) : pudr[19]; and(wire_nl0iO0i_dataout, wire_nl0iiOl_o[2], ~(wire_nl0iOii_o)); and(wire_nl0iO0l_dataout, wire_nl0iiOl_o[3], ~(wire_nl0iOii_o)); and(wire_nl0iO0O_dataout, wire_nl0iiOl_o[4], ~(wire_nl0iOii_o)); assign wire_nl0iO1i_dataout = (nlli00i === 1'b1) ? wire_nl0iO0O_dataout : nl010ii; and(wire_nl0iO1l_dataout, wire_nl0iiOl_o[0], ~(wire_nl0iOii_o)); and(wire_nl0iO1O_dataout, wire_nl0iiOl_o[1], ~(wire_nl0iOii_o)); and(wire_nl0iOi_dataout, nliO0l, ~(n1ii10i)); assign wire_nl0iOil_dataout = (nlli00i === 1'b1) ? wire_nl0iOOi_dataout : nl0101O; assign wire_nl0iOiO_dataout = (nlli00i === 1'b1) ? wire_nl0iOOl_dataout : nl0100i; and(wire_nl0iOl_dataout, nliO0O, ~(n1ii10i)); assign wire_nl0iOli_dataout = (nlli00i === 1'b1) ? wire_nl0iOOO_dataout : nl0100l; assign wire_nl0iOll_dataout = (nlli00i === 1'b1) ? wire_nl0l11i_dataout : nl0100O; assign wire_nl0iOlO_dataout = (nlli00i === 1'b1) ? wire_nl0l11l_dataout : nl010ii; and(wire_nl0iOO_dataout, nliOii, ~(n1ii10i)); and(wire_nl0iOOi_dataout, wire_nl0iiOl_o[0], ~(wire_nl0l11O_o)); and(wire_nl0iOOl_dataout, wire_nl0iiOl_o[1], ~(wire_nl0l11O_o)); and(wire_nl0iOOO_dataout, wire_nl0iiOl_o[2], ~(wire_nl0l11O_o)); and(wire_nl0l_dataout, wire_nl1l0ll_dataout, wa_6g_en); assign wire_nl0l00i_dataout = (n111O0i === 1'b1) ? nl1OiiO : nl01O1O; assign wire_nl0l01i_dataout = ((n110i0l | n110i0i) === 1'b1) ? nl1Oiil : wire_nl0l01l_dataout; and(wire_nl0l01l_dataout, nl1liii, n111O0i); and(wire_nl0l0i_dataout, nliOll, ~(n1ii10i)); assign wire_nl0l0ii_dataout = (comp_pat_size[0] === 1'b1) ? ((n1100ll | nl1Olli) | (n1iiiOi & nl1Ol1l)) : n11010O; assign wire_nl0l0il_dataout = (comp_pat_size[0] === 1'b1) ? ((n11000l | nl1Olil) | (n1iiiOi & nl1OiOO)) : wire_nl0l0iO_dataout; assign wire_nl0l0iO_dataout = (n111O0l === 1'b1) ? n11010O : ((n1101il | nl1Ol0i) | (n1iiiOi & nl1Oill)); and(wire_nl0l0l_dataout, nliOlO, ~(n1ii10i)); and(wire_nl0l0ll_dataout, nl01O1O, ~(wire_nll1llO_o)); and(wire_nl0l0lO_dataout, nl1Oiil, ~(wire_nll1llO_o)); assign wire_nl0l0O_dataout = (n1ii11O === 1'b1) ? nliO0i : wire_nl0ilO_dataout; and(wire_nl0l11i_dataout, wire_nl0iiOl_o[3], ~(wire_nl0l11O_o)); and(wire_nl0l11l_dataout, wire_nl0iiOl_o[4], ~(wire_nl0l11O_o)); and(wire_nl0l1i_dataout, nliOil, ~(n1ii10i)); assign wire_nl0l1ii_dataout = (sync_sm_dis === 1'b1) ? wire_nl0l1il_dataout : wire_nl0l00i_dataout; and(wire_nl0l1il_dataout, nl1Oiil, ((n110iil | n110iii) | n110i0O)); and(wire_nl0l1l_dataout, nliOiO, ~(n1ii10i)); assign wire_nl0l1lO_dataout = (comp_pat_size[0] === 1'b1) ? ((n1100Ol | nl1OliO) | (n1iiiOi & nl1Ol1i)) : n1101ii; and(wire_nl0l1O_dataout, nliOli, ~(n1ii10i)); assign wire_nl0l1Oi_dataout = (comp_pat_size[0] === 1'b1) ? ((n1100il | nl1Olii) | (n1iiiOi & nl1OiOl)) : wire_nl0l1Ol_dataout; assign wire_nl0l1Ol_dataout = (n111O0l === 1'b1) ? n1101ii : ((n1101ll | nl1Ol1O) | (n1iiiOi & nl1Oili)); assign wire_nl0l1OO_dataout = (sync_sm_dis === 1'b1) ? wire_nl0l01i_dataout : wire_nl0l00i_dataout; assign wire_nl0li_dataout = (nO === 1'b1) ? (~ pudr[0]) : pudr[0]; assign wire_nl0lii_dataout = (n1ii11O === 1'b1) ? nliO0l : wire_nl0iOi_dataout; assign wire_nl0lil_dataout = (n1ii11O === 1'b1) ? nliO0O : wire_nl0iOl_dataout; assign wire_nl0liO_dataout = (n1ii11O === 1'b1) ? nliOii : wire_nl0iOO_dataout; assign wire_nl0ll_dataout = (nO === 1'b1) ? (~ pudr[1]) : pudr[1]; assign wire_nl0lli_dataout = (n1ii11O === 1'b1) ? nliOil : wire_nl0l1i_dataout; assign wire_nl0lll_dataout = (n1ii11O === 1'b1) ? nliOiO : wire_nl0l1l_dataout; assign wire_nl0llO_dataout = (n1ii11O === 1'b1) ? nliOli : wire_nl0l1O_dataout; assign wire_nl0lO_dataout = (nO === 1'b1) ? (~ pudr[2]) : pudr[2]; and(wire_nl0lOi_dataout, wire_nl0l0i_dataout, ~(n1ii11O)); and(wire_nl0lOl_dataout, wire_nl0l0l_dataout, ~(n1ii11O)); and(wire_nl0lOO_dataout, wire_nl0O1i_dataout, ~(n1ii11O)); and(wire_nl0O_dataout, wire_nl1l1ll_dataout, wa_6g_en); and(wire_nl0O0i_dataout, wire_nl0O0l_dataout, ~(n1ii11O)); and(wire_nl0O0l_dataout, nliOOl, ~(n1ii10i)); and(wire_nl0O0O_dataout, nliOOi, ~(n1ii11O)); and(wire_nl0O1i_dataout, nliOOi, ~(n1ii10i)); and(wire_nl0O1l_dataout, nliOlO, ~(n1ii11O)); and(wire_nl0O1O_dataout, wire_nl0O1i_dataout, ~(n1ii11O)); assign wire_nl0Oi_dataout = (nO === 1'b1) ? (~ pudr[3]) : pudr[3]; and(wire_nl0Oii_dataout, wire_nl0O0l_dataout, ~(n1ii11O)); and(wire_nl0Oil_dataout, wire_nl0OiO_dataout, ~(n1ii11O)); and(wire_nl0OiO_dataout, nliOOO, ~(n1ii10i)); assign wire_nl0Ol_dataout = (nO === 1'b1) ? (~ pudr[4]) : pudr[4]; and(wire_nl0Oli_dataout, nliOOl, ~(n1ii11O)); and(wire_nl0Oll_dataout, wire_nl0OiO_dataout, ~(n1ii11O)); and(wire_nl0OlO_dataout, wire_nl0OOi_dataout, ~(n1ii11O)); assign wire_nl0OO_dataout = (nO === 1'b1) ? (~ pudr[5]) : pudr[5]; and(wire_nl0OOi_dataout, nll11i, ~(n1ii10i)); and(wire_nl0OOl_dataout, nliOOO, ~(n1ii11O)); and(wire_nl0OOO_dataout, wire_nl0OOi_dataout, ~(n1ii11O)); and(wire_nl10i_dataout, wire_nl0iO_dataout, ~(n1iii1l)); assign wire_nl10l_dataout = (nO === 1'b1) ? (~ pudr[0]) : pudr[0]; assign wire_nl10O_dataout = (nO === 1'b1) ? (~ pudr[1]) : pudr[1]; or(wire_nl10OO_dataout, wire_nl1i0i_dataout, n1i0i1l); and(wire_nl11i_dataout, wire_nl00O_dataout, ~(n1iii1l)); and(wire_nl11l_dataout, wire_nl0ii_dataout, ~(n1iii1l)); and(wire_nl11O_dataout, wire_nl0il_dataout, ~(n1iii1l)); and(wire_nl1i_dataout, wire_nl1l0ii_dataout, wa_6g_en); or(wire_nl1i0i_dataout, wire_nl1iil_o[1], n1i0i1i); or(wire_nl1i0l_dataout, wire_nl1iil_o[2], n1i0i1i); or(wire_nl1i0O_dataout, wire_nl1iil_o[3], n1i0i1i); and(wire_nl1i1i_dataout, wire_nl1i0l_dataout, ~(n1i0i1l)); and(wire_nl1i1l_dataout, wire_nl1i0O_dataout, ~(n1i0i1l)); or(wire_nl1i1O_dataout, wire_nl1iii_dataout, n1i0i1l); assign wire_nl1ii_dataout = (nO === 1'b1) ? (~ pudr[2]) : pudr[2]; and(wire_nl1iii_dataout, wire_nl1iil_o[4], ~(n1i0i1i)); assign wire_nl1il_dataout = (nO === 1'b1) ? (~ pudr[3]) : pudr[3]; assign wire_nl1iO_dataout = (nO === 1'b1) ? (~ pudr[4]) : pudr[4]; and(wire_nl1iOil_dataout, nl1OO0O, ~(rrxpcsbypass_en)); and(wire_nl1iOiO_dataout, nl1OOii, ~(rrxpcsbypass_en)); and(wire_nl1iOli_dataout, nl1OOil, ~(rrxpcsbypass_en)); and(wire_nl1iOll_dataout, nl1OOiO, ~(rrxpcsbypass_en)); and(wire_nl1iOlO_dataout, nl1OOli, ~(rrxpcsbypass_en)); and(wire_nl1iOOi_dataout, nl1OOll, ~(rrxpcsbypass_en)); assign wire_nl1iOOl_dataout = (rrxpcsbypass_en === 1'b1) ? nll0OOl : nl1Olll; assign wire_nl1iOOO_dataout = (rrxpcsbypass_en === 1'b1) ? nll0OOO : nl1OllO; and(wire_nl1l_dataout, wire_nl1l0il_dataout, wa_6g_en); assign wire_nl1l00i_dataout = (rrxpcsbypass_en === 1'b1) ? wire_nl1l0Ol_dataout : nl1OOOl; assign wire_nl1l00l_dataout = (rrxpcsbypass_en === 1'b1) ? wire_nl1l0OO_dataout : nl1OOOO; assign wire_nl1l00O_dataout = (rrxpcsbypass_en === 1'b1) ? wire_nl1li1i_dataout : nl0111i; and(wire_nl1l01i_dataout, nl011lO, ~(rrxpcsbypass_en)); assign wire_nl1l01l_dataout = (rrxpcsbypass_en === 1'b1) ? wire_nl1l0lO_dataout : nl1OOlO; assign wire_nl1l01O_dataout = (rrxpcsbypass_en === 1'b1) ? wire_nl1l0Oi_dataout : nl1OOOi; or(wire_nl1l0i_dataout, nlli0l, (~ wire_nllliil_dataout)); assign wire_nl1l0ii_dataout = (rrxpcsbypass_en === 1'b1) ? wire_nl1li1l_dataout : nl0111l; assign wire_nl1l0il_dataout = (rrxpcsbypass_en === 1'b1) ? wire_nl1li1O_dataout : nl0111O; assign wire_nl1l0iO_dataout = (rrxpcsbypass_en === 1'b1) ? wire_nl1li0i_dataout : nl0110i; or(wire_nl1l0l_dataout, nlli0O, (~ wire_nllliil_dataout)); assign wire_nl1l0li_dataout = (rrxpcsbypass_en === 1'b1) ? wire_nl1li0l_dataout : nl0110l; assign wire_nl1l0ll_dataout = (rrxpcsbypass_en === 1'b1) ? wire_nl1li0O_dataout : nl0110O; assign wire_nl1l0lO_dataout = (n111llO === 1'b1) ? nlli1ii : nlli1iO; or(wire_nl1l0O_dataout, nlliii, (~ wire_nllliil_dataout)); assign wire_nl1l0Oi_dataout = (n111llO === 1'b1) ? nlli1il : nlli1li; assign wire_nl1l0Ol_dataout = (n111llO === 1'b1) ? nlli1iO : nlli1ll; assign wire_nl1l0OO_dataout = (n111llO === 1'b1) ? nlli1li : nlli1lO; assign wire_nl1l10i_dataout = (rrxpcsbypass_en === 1'b1) ? nlli10i : nl1OO1i; assign wire_nl1l10l_dataout = (rrxpcsbypass_en === 1'b1) ? nlli10l : nl1OO1l; assign wire_nl1l10O_dataout = (rrxpcsbypass_en === 1'b1) ? nlli10O : nl1OO1O; assign wire_nl1l11i_dataout = (rrxpcsbypass_en === 1'b1) ? nlli11i : nl1OlOi; assign wire_nl1l11l_dataout = (rrxpcsbypass_en === 1'b1) ? nlli11l : nl1OlOl; assign wire_nl1l11O_dataout = (rrxpcsbypass_en === 1'b1) ? nlli11O : nl1OlOO; assign wire_nl1l1ii_dataout = (rrxpcsbypass_en === 1'b1) ? wire_nl1l1iO_dataout : nl1OO0i; assign wire_nl1l1il_dataout = (rrxpcsbypass_en === 1'b1) ? wire_nl1l1li_dataout : nl1OO0l; and(wire_nl1l1iO_dataout, nlli1ii, ~(n111llO)); and(wire_nl1l1li_dataout, nlli1il, ~(n111llO)); and(wire_nl1l1ll_dataout, nl011ii, ~(rrxpcsbypass_en)); and(wire_nl1l1lO_dataout, nl011il, ~(rrxpcsbypass_en)); or(wire_nl1l1O_dataout, nll1il, (~ wire_nllliil_dataout)); and(wire_nl1l1Oi_dataout, nl011iO, ~(rrxpcsbypass_en)); and(wire_nl1l1Ol_dataout, nl011li, ~(rrxpcsbypass_en)); and(wire_nl1l1OO_dataout, nl011ll, ~(rrxpcsbypass_en)); assign wire_nl1li_dataout = (nO === 1'b1) ? (~ pudr[5]) : pudr[5]; assign wire_nl1li0i_dataout = (n111llO === 1'b1) ? nlli1Ol : nlli01i; and(wire_nl1li0l_dataout, nlli01l, ~(n111llO)); and(wire_nl1li0O_dataout, nlli01O, ~(n111llO)); assign wire_nl1li1i_dataout = (n111llO === 1'b1) ? nlli1ll : nlli1Oi; assign wire_nl1li1l_dataout = (n111llO === 1'b1) ? nlli1lO : nlli1Ol; assign wire_nl1li1O_dataout = (n111llO === 1'b1) ? nlli1Oi : nlli1OO; assign wire_nl1ll_dataout = (nO === 1'b1) ? (~ pudr[6]) : pudr[6]; assign wire_nl1lO_dataout = (nO === 1'b1) ? (~ pudr[7]) : pudr[7]; and(wire_nl1O_dataout, wire_nl1l0iO_dataout, wa_6g_en); assign wire_nl1O00l_dataout = (nlli0li === 1'b1) ? nl01lii : nl01iOi; assign wire_nl1O00O_dataout = (nlli0li === 1'b1) ? nl01l0O : nl01iOl; assign wire_nl1O0ii_dataout = (nlli0li === 1'b1) ? nl01l0l : nl01iOO; assign wire_nl1O0il_dataout = (nlli0li === 1'b1) ? nl01l0i : nl01l1i; assign wire_nl1O0iO_dataout = (nlli0li === 1'b1) ? nl01l1O : nl01l1l; assign wire_nl1O0li_dataout = (nlli0li === 1'b1) ? nl01l1l : nl01l1O; assign wire_nl1O0ll_dataout = (nlli0li === 1'b1) ? nl01l1i : nl01l0i; assign wire_nl1O0lO_dataout = (nlli0li === 1'b1) ? nl01iOO : nl01l0l; assign wire_nl1O0Oi_dataout = (nlli0li === 1'b1) ? nl01iOl : nl01l0O; assign wire_nl1O0Ol_dataout = (nlli0li === 1'b1) ? nl01iOi : nl01lii; assign wire_nl1O0OO_dataout = (nlli0li === 1'b1) ? nl01l0l : nl01iOi; assign wire_nl1Oi_dataout = (nO === 1'b1) ? (~ pudr[8]) : pudr[8]; assign wire_nl1Oi0i_dataout = (nlli0li === 1'b1) ? nl01l1i : nl01l1l; assign wire_nl1Oi0l_dataout = (nlli0li === 1'b1) ? nl01iOO : nl01l1O; assign wire_nl1Oi0O_dataout = (nlli0li === 1'b1) ? nl01iOl : nl01l0i; assign wire_nl1Oi1i_dataout = (nlli0li === 1'b1) ? nl01l0i : nl01iOl; assign wire_nl1Oi1l_dataout = (nlli0li === 1'b1) ? nl01l1O : nl01iOO; assign wire_nl1Oi1O_dataout = (nlli0li === 1'b1) ? nl01l1l : nl01l1i; assign wire_nl1Oiii_dataout = (nlli0li === 1'b1) ? nl01iOi : nl01l0l; assign wire_nl1Ol_dataout = (nO === 1'b1) ? (~ pudr[9]) : pudr[9]; assign wire_nl1OO_dataout = (nO === 1'b1) ? (~ pudr[10]) : pudr[10]; assign wire_nl1OOl_dataout = (autobytealign_dis === 1'b1) ? nl10il : nl1lil; assign wire_nl1OOO_dataout = (autobytealign_dis === 1'b1) ? nl10li : nl1liO; assign wire_nli00i_dataout = (n1ii11O === 1'b1) ? (~ comp_pat[0]) : wire_nli0Ol_dataout; assign wire_nli00l_dataout = (n1ii11O === 1'b1) ? (~ comp_pat[1]) : wire_nli0OO_dataout; assign wire_nli00O_dataout = (n1ii11O === 1'b1) ? (~ comp_pat[2]) : wire_nlii1i_dataout; and(wire_nli01i_dataout, wire_nli1Ol_dataout, ~(n1ii11O)); and(wire_nli01l_dataout, wire_nli01O_dataout, ~(n1ii11O)); and(wire_nli01O_dataout, nll1ii, ~(n1ii10i)); assign wire_nli0i_dataout = (nO === 1'b1) ? (~ pudr[11]) : pudr[11]; assign wire_nli0ii_dataout = (n1ii11O === 1'b1) ? (~ comp_pat[3]) : wire_nlii1l_dataout; assign wire_nli0il_dataout = (n1ii11O === 1'b1) ? (~ comp_pat[4]) : wire_nlii1O_dataout; assign wire_nli0iO_dataout = (n1ii11O === 1'b1) ? (~ comp_pat[5]) : wire_nlii0i_dataout; assign wire_nli0l_dataout = (nO === 1'b1) ? (~ pudr[12]) : pudr[12]; assign wire_nli0li_dataout = (n1ii11O === 1'b1) ? (~ comp_pat[6]) : wire_nlii0l_dataout; and(wire_nli0ll_dataout, wire_nlii0O_dataout, ~(n1ii11O)); and(wire_nli0lO_dataout, wire_nliiii_dataout, ~(n1ii11O)); assign wire_nli0O_dataout = (nO === 1'b1) ? (~ pudr[13]) : pudr[13]; and(wire_nli0Oi_dataout, wire_nliiil_dataout, ~(n1ii11O)); assign wire_nli0Ol_dataout = (n1ii10i === 1'b1) ? comp_pat[8] : (~ comp_pat[0]); assign wire_nli0OO_dataout = (n1ii10i === 1'b1) ? comp_pat[9] : (~ comp_pat[1]); and(wire_nli10i_dataout, wire_nli11l_dataout, ~(n1ii11O)); and(wire_nli10l_dataout, wire_nli10O_dataout, ~(n1ii11O)); and(wire_nli10O_dataout, nll11O, ~(n1ii10i)); and(wire_nli11i_dataout, wire_nli11l_dataout, ~(n1ii11O)); and(wire_nli11l_dataout, nll11l, ~(n1ii10i)); and(wire_nli11O_dataout, nll11i, ~(n1ii11O)); assign wire_nli1i_dataout = (nO === 1'b1) ? (~ pudr[6]) : pudr[6]; and(wire_nli1ii_dataout, nll11l, ~(n1ii11O)); and(wire_nli1il_dataout, wire_nli10O_dataout, ~(n1ii11O)); and(wire_nli1iO_dataout, wire_nli1li_dataout, ~(n1ii11O)); assign wire_nli1l_dataout = (nO === 1'b1) ? (~ pudr[7]) : pudr[7]; and(wire_nli1li_dataout, nll10i, ~(n1ii10i)); and(wire_nli1ll_dataout, nll11O, ~(n1ii11O)); and(wire_nli1lO_dataout, wire_nli1li_dataout, ~(n1ii11O)); assign wire_nli1O_dataout = (nO === 1'b1) ? (~ pudr[10]) : pudr[10]; and(wire_nli1Oi_dataout, wire_nli1Ol_dataout, ~(n1ii11O)); and(wire_nli1Ol_dataout, nll10l, ~(n1ii10i)); and(wire_nli1OO_dataout, nll10i, ~(n1ii11O)); and(wire_nlii_dataout, wire_nl1l1lO_dataout, wa_6g_en); assign wire_nlii0i_dataout = (n1ii10i === 1'b1) ? comp_pat[13] : (~ comp_pat[5]); assign wire_nlii0l_dataout = (n1ii10i === 1'b1) ? comp_pat[14] : (~ comp_pat[6]); assign wire_nlii0O_dataout = (n1ii10i === 1'b1) ? comp_pat[15] : (~ comp_pat[7]); assign wire_nlii1i_dataout = (n1ii10i === 1'b1) ? comp_pat[10] : (~ comp_pat[2]); assign wire_nlii1l_dataout = (n1ii10i === 1'b1) ? comp_pat[11] : (~ comp_pat[3]); assign wire_nlii1O_dataout = (n1ii10i === 1'b1) ? comp_pat[12] : (~ comp_pat[4]); assign wire_nliii_dataout = (nO === 1'b1) ? (~ pudr[14]) : pudr[14]; and(wire_nliiii_dataout, (~ comp_pat[8]), ~(n1ii10i)); and(wire_nliiil_dataout, (~ comp_pat[9]), ~(n1ii10i)); and(wire_nliiiO_dataout, comp_pat[7], ~(n1ii11O)); assign wire_nliil_dataout = (nO === 1'b1) ? (~ pudr[15]) : pudr[15]; and(wire_nliili_dataout, wire_nliilO_dataout, ~(n1ii11O)); and(wire_nliill_dataout, wire_nliiOi_dataout, ~(n1ii11O)); and(wire_nliilO_dataout, comp_pat[8], ~(n1ii10i)); assign wire_nliiO_dataout = (nO === 1'b1) ? (~ pudr[16]) : pudr[16]; and(wire_nliiOi_dataout, comp_pat[9], ~(n1ii10i)); and(wire_nlil_dataout, wire_nl1l1Oi_dataout, wa_6g_en); assign wire_nlili_dataout = (nO === 1'b1) ? (~ pudr[17]) : pudr[17]; assign wire_nlill_dataout = (n1iii1O === 1'b1) ? wire_n10O_dataout : wire_nlO1i_dataout; assign wire_nlilO_dataout = (n1iii1O === 1'b1) ? wire_n1ii_dataout : wire_nlO1l_dataout; and(wire_nliO_dataout, wire_nl1l1Ol_dataout, wa_6g_en); assign wire_nliOi_dataout = (n1iii1O === 1'b1) ? wire_n1il_dataout : wire_nlO1O_dataout; assign wire_nliOl_dataout = (n1iii1O === 1'b1) ? wire_n1iO_dataout : wire_nlO0i_dataout; assign wire_nliOO_dataout = (n1iii1O === 1'b1) ? wire_n1li_dataout : wire_nlO0l_dataout; assign wire_nll00i_dataout = (pmadwidth[0] === 1'b1) ? nll11i : nliOOl; assign wire_nll00l_dataout = (pmadwidth[0] === 1'b1) ? nll11l : nliOOO; assign wire_nll00O_dataout = (pmadwidth[0] === 1'b1) ? nll11O : nll11i; assign wire_nll01i_dataout = (pmadwidth[0] === 1'b1) ? nliOOi : nliOll; assign wire_nll01l_dataout = (pmadwidth[0] === 1'b1) ? nliOOl : nliOlO; assign wire_nll01O_dataout = (pmadwidth[0] === 1'b1) ? nliOOO : nliOOi; assign wire_nll0i_dataout = (n1iii1O === 1'b1) ? wire_n1Ol_dataout : wire_nlOiO_dataout; assign wire_nll0ii_dataout = (pmadwidth[0] === 1'b1) ? nll10i : nll11l; assign wire_nll0il_dataout = (pmadwidth[0] === 1'b1) ? nll10l : nll11O; assign wire_nll0iO_dataout = (pmadwidth[0] === 1'b1) ? nll1ii : nll10i; assign wire_nll0l_dataout = (n1iii1O === 1'b1) ? wire_n1OO_dataout : wire_nlOli_dataout; assign wire_nll0li_dataout = (lpbk_en === 1'b1) ? wire_niili_dataout : wire_nil0l_dataout; assign wire_nll0ll_dataout = (lpbk_en === 1'b1) ? wire_niill_dataout : wire_nil0O_dataout; assign wire_nll0lO_dataout = (lpbk_en === 1'b1) ? wire_niilO_dataout : wire_nilii_dataout; assign wire_nll0O_dataout = (n1iii1O === 1'b1) ? wire_n01i_dataout : wire_nlOll_dataout; assign wire_nll0Oi_dataout = (lpbk_en === 1'b1) ? wire_niiOi_dataout : wire_nilil_dataout; assign wire_nll0Ol_dataout = (lpbk_en === 1'b1) ? wire_niiOl_dataout : wire_niliO_dataout; assign wire_nll0OO_dataout = (lpbk_en === 1'b1) ? wire_niiOO_dataout : wire_nilli_dataout; assign wire_nll1i_dataout = (n1iii1O === 1'b1) ? wire_n1ll_dataout : wire_nlO0O_dataout; assign wire_nll1iO_dataout = (pmadwidth[0] === 1'b1) ? nliO0O : nliO0i; assign wire_nll1l_dataout = (n1iii1O === 1'b1) ? wire_n1lO_dataout : wire_nlOii_dataout; assign wire_nll1li_dataout = (pmadwidth[0] === 1'b1) ? nliOii : nliO0l; assign wire_nll1ll_dataout = (pmadwidth[0] === 1'b1) ? nliOil : nliO0O; assign wire_nll1lO_dataout = (pmadwidth[0] === 1'b1) ? nliOiO : nliOii; and(wire_nll1lOi_dataout, n10l1li, n10l11O); and(wire_nll1lOl_dataout, wire_nll1O0i_dataout, n10l11l); assign wire_nll1O_dataout = (n1iii1O === 1'b1) ? wire_n1Oi_dataout : wire_nlOil_dataout; and(wire_nll1O0i_dataout, (~ n10l10i), ~(n10l1iO)); or(wire_nll1O0l_dataout, n10l10i, n10l1iO); and(wire_nll1O0O_dataout, (~ n10l1il), n10l10i); or(wire_nll1O1O_dataout, wire_nll1O0O_dataout, n10l1iO); assign wire_nll1Oi_dataout = (pmadwidth[0] === 1'b1) ? nliOli : nliOil; assign wire_nll1Ol_dataout = (pmadwidth[0] === 1'b1) ? nliOll : nliOiO; assign wire_nll1OO_dataout = (pmadwidth[0] === 1'b1) ? nliOlO : nliOli; and(wire_nlli_dataout, wire_nl1l1OO_dataout, wa_6g_en); assign wire_nlli0i_dataout = (lpbk_en === 1'b1) ? wire_nil0i_dataout : wire_nilOl_dataout; assign wire_nlli1i_dataout = (lpbk_en === 1'b1) ? wire_nil1i_dataout : wire_nilll_dataout; assign wire_nlli1l_dataout = (lpbk_en === 1'b1) ? wire_nil1l_dataout : wire_nillO_dataout; assign wire_nlli1O_dataout = (lpbk_en === 1'b1) ? wire_nil1O_dataout : wire_nilOi_dataout; assign wire_nllii_dataout = (n1iii1O === 1'b1) ? wire_n01l_dataout : wire_nlOlO_dataout; assign wire_nllii0O_dataout = (lpbk_en === 1'b1) ? wire_nilOO_dataout : wire_nlill_dataout; assign wire_nlliiii_dataout = (lpbk_en === 1'b1) ? wire_niO1i_dataout : wire_nlilO_dataout; assign wire_nlliiil_dataout = (lpbk_en === 1'b1) ? wire_niO1l_dataout : wire_nliOi_dataout; assign wire_nlliiiO_dataout = (lpbk_en === 1'b1) ? wire_niO1O_dataout : wire_nliOl_dataout; or(wire_nlliil_dataout, wire_nllilO_dataout, (~ wire_nllliil_dataout)); assign wire_nlliili_dataout = (lpbk_en === 1'b1) ? wire_niO0i_dataout : wire_nliOO_dataout; assign wire_nlliill_dataout = (lpbk_en === 1'b1) ? wire_niO0l_dataout : wire_nll1i_dataout; assign wire_nlliilO_dataout = (lpbk_en === 1'b1) ? wire_niO0O_dataout : wire_nll1l_dataout; or(wire_nlliiO_dataout, wire_nlliOi_dataout, (~ wire_nllliil_dataout)); assign wire_nlliiOi_dataout = (lpbk_en === 1'b1) ? wire_niOii_dataout : wire_nll1O_dataout; assign wire_nlliiOl_dataout = (lpbk_en === 1'b1) ? wire_niOil_dataout : wire_nll0i_dataout; assign wire_nlliiOO_dataout = (lpbk_en === 1'b1) ? wire_niOiO_dataout : wire_nll0l_dataout; assign wire_nllil_dataout = (n1iii1O === 1'b1) ? wire_n01O_dataout : wire_nlOOi_dataout; assign wire_nllil0i_dataout = (lpbk_en === 1'b1) ? wire_niOOi_dataout : wire_nlliO_dataout; assign wire_nllil0l_dataout = (lpbk_en === 1'b1) ? wire_niOOl_dataout : wire_nllli_dataout; assign wire_nllil0O_dataout = (lpbk_en === 1'b1) ? wire_niOOO_dataout : wire_nllll_dataout; assign wire_nllil1i_dataout = (lpbk_en === 1'b1) ? wire_niOli_dataout : wire_nll0O_dataout; assign wire_nllil1l_dataout = (lpbk_en === 1'b1) ? wire_niOll_dataout : wire_nllii_dataout; assign wire_nllil1O_dataout = (lpbk_en === 1'b1) ? wire_niOlO_dataout : wire_nllil_dataout; or(wire_nllili_dataout, wire_nlliOl_dataout, (~ wire_nllliil_dataout)); assign wire_nllilii_dataout = (lpbk_en === 1'b1) ? wire_nl11i_dataout : wire_nlllO_dataout; assign wire_nllilil_dataout = (lpbk_en === 1'b1) ? wire_nl11l_dataout : wire_nllOi_dataout; assign wire_nlliliO_dataout = (lpbk_en === 1'b1) ? wire_nl11O_dataout : wire_nllOl_dataout; or(wire_nllill_dataout, wire_nlliOO_dataout, (~ wire_nllliil_dataout)); assign wire_nllilli_dataout = (lpbk_en === 1'b1) ? wire_nl10i_dataout : wire_nllOO_dataout; assign wire_nllilO_dataout = (n1ii10O === 1'b1) ? (~ n1ii1OO) : nll1il; or(wire_nllilOO_dataout, wire_nlliO1i_dataout, (nllii0l & (~ nllii0i))); assign wire_nlliO_dataout = (n1iii1O === 1'b1) ? wire_n00i_dataout : wire_nlOOl_dataout; and(wire_nlliO1i_dataout, nlli0OO, ~(nllii1i)); assign wire_nlliOi_dataout = (n1ii10O === 1'b1) ? n1ii01i : nlli0l; assign wire_nlliOl_dataout = (n1ii10O === 1'b1) ? n1ii01l : nlli0O; assign wire_nlliOO_dataout = (n1ii10O === 1'b1) ? n1ii01O : nlliii; and(wire_nlll_dataout, wire_nl1l01i_dataout, wa_6g_en); or(wire_nlll0l_dataout, n1ii00i, n1ii1lO); and(wire_nlll0O_dataout, n1ii00i, ~(n1ii1lO)); assign wire_nllli_dataout = (n1iii1O === 1'b1) ? wire_n00l_dataout : wire_nlOOO_dataout; and(wire_nlllii_dataout, (~ n1ii00i), ~(n1ii1lO)); assign wire_nllliil_dataout = (nlO0ilO === 1'b1) ? encdet_prbs : wire_nllliiO_dataout; assign wire_nllliiO_dataout = (sync_sm_dis === 1'b1) ? wire_nlllili_dataout : nlO010O; or(wire_nlllil_dataout, n1ii1lO, n1ii00i); assign wire_nlllili_dataout = ((~ pmadwidth[0]) === 1'b1) ? wire_nlll1i_o : nlO0l1l; and(wire_nlllill_dataout, wire_nlO0l0i_o[0], ~(n10l1ll)); and(wire_nlllilO_dataout, wire_nlO0l0i_o[1], ~(n10l1ll)); and(wire_nllliO_dataout, n1ii1lO, ~(n1ii00i)); and(wire_nllliOi_dataout, wire_nlO0l0i_o[2], ~(n10l1ll)); and(wire_nllliOl_dataout, wire_nlO0l0i_o[3], ~(n10l1ll)); assign wire_nllll_dataout = (n1iii1O === 1'b1) ? wire_n00O_dataout : wire_n11i_dataout; and(wire_nlllli_dataout, (~ n1ii1lO), ~(n1ii00i)); and(wire_nlllO_dataout, wire_n11l_dataout, ~(n1iii1O)); assign wire_nllO_dataout = (wa_6g_en === 1'b1) ? wire_nl0l0OO_o : niii0l; and(wire_nllO00i_dataout, wire_nllO0lO_o, ~((~ nlO010l))); and(wire_nllO00l_dataout, wire_nllO0Oi_o, ~((~ nlO010l))); and(wire_nllO00O_dataout, wire_nllO0Ol_o, ~((~ nlO010l))); and(wire_nllO01i_dataout, wire_nllO0iO_o, ~((~ nlO010l))); and(wire_nllO01l_dataout, wire_nllO0li_o, ~((~ nlO010l))); and(wire_nllO01O_dataout, wire_nllO0ll_o, ~((~ nlO010l))); and(wire_nllO0ii_dataout, wire_nllO0OO_o, ~((~ nlO010l))); or(wire_nllO0il_dataout, wire_nllOi1i_o, (~ nlO010l)); and(wire_nllOi_dataout, wire_n11O_dataout, ~(n1iii1O)); and(wire_nllOi0l_dataout, wire_nllOill_dataout, ~(n10l0li)); and(wire_nllOi0O_dataout, wire_nllOilO_dataout, ~(n10l0li)); and(wire_nllOi1l_dataout, n10l01O, ~((~ n10lili))); and(wire_nllOi1O_dataout, (~ n10l01O), ~((~ n10lili))); and(wire_nllOiii_dataout, wire_nllOiOi_dataout, ~(n10l0li)); and(wire_nllOiil_dataout, n10l0il, ~(n10l0li)); and(wire_nllOiiO_dataout, wire_nllOiOl_dataout, ~(n10l0li)); and(wire_nllOili_dataout, wire_nllOiOO_dataout, ~(n10l0li)); and(wire_nllOill_dataout, wire_nllOl1i_dataout, ~(n10l0il)); and(wire_nllOilO_dataout, wire_nllOl1l_dataout, ~(n10l0il)); and(wire_nllOiOi_dataout, wire_nllOl1O_dataout, ~(n10l0il)); and(wire_nllOiOl_dataout, n10l0ii, ~(n10l0il)); and(wire_nllOiOO_dataout, wire_nllOl0i_dataout, ~(n10l0il)); and(wire_nllOl_dataout, wire_n10i_dataout, ~(n1iii1O)); and(wire_nllOl0i_dataout, wire_nllOlii_dataout, ~(n10l0ii)); and(wire_nllOl0l_dataout, n10l00l, ~(n10l00O)); and(wire_nllOl0O_dataout, wire_nllOlil_dataout, ~(n10l00O)); and(wire_nllOl1i_dataout, wire_nllOl0l_dataout, ~(n10l0ii)); and(wire_nllOl1l_dataout, n10l00O, ~(n10l0ii)); and(wire_nllOl1O_dataout, wire_nllOl0O_dataout, ~(n10l0ii)); and(wire_nllOlii_dataout, wire_nllOliO_dataout, ~(n10l00O)); and(wire_nllOlil_dataout, n10l00i, ~(n10l00l)); and(wire_nllOliO_dataout, (~ n10l00i), ~(n10l00l)); and(wire_nllOO_dataout, wire_n10l_dataout, ~(n1iii1O)); and(wire_nllOO0O_dataout, wire_nllOOli_dataout, ~(n10li1i)); and(wire_nllOOii_dataout, wire_nllOOll_dataout, ~(n10li1i)); and(wire_nllOOil_dataout, wire_nllOOlO_dataout, ~(n10li1i)); and(wire_nllOOiO_dataout, n10li1O, ~(n10li1i)); and(wire_nllOOli_dataout, wire_nllOOOi_dataout, ~(n10li1O)); and(wire_nllOOll_dataout, n10li1l, ~(n10li1O)); and(wire_nllOOlO_dataout, wire_nllOOOl_dataout, ~(n10li1O)); and(wire_nllOOOi_dataout, wire_nllOOOO_dataout, ~(n10li1l)); and(wire_nllOOOl_dataout, n10liii, ~(n10li1l)); and(wire_nllOOOO_dataout, (~ n10li0i), ~(n10liii)); assign wire_nlO0i_dataout = (nO === 1'b1) ? (~ pudi[3]) : pudi[3]; assign wire_nlO0l_dataout = (nO === 1'b1) ? (~ pudi[4]) : pudi[4]; assign wire_nlO0O_dataout = (nO === 1'b1) ? (~ pudi[5]) : pudi[5]; or(wire_nlO0O0l_dataout, n1ii11i, n1ii11l); or(wire_nlO0Oli_dataout, n1i0O0O, n1i0Oii); or(wire_nlO0OOO_dataout, n1i0lOO, n1i0O1i); and(wire_nlO100i_dataout, n10li0l, ~(n10liiO)); and(wire_nlO100l_dataout, (~ n10li0i), ~(n10li0l)); and(wire_nlO101i_dataout, wire_nlO100i_dataout, ~(n10l0ll)); and(wire_nlO101l_dataout, n10liiO, ~(n10l0ll)); and(wire_nlO101O_dataout, wire_nlO100l_dataout, ~(n10liiO)); and(wire_nlO110O_dataout, wire_nlO11ll_dataout, ~(n10l0Ol)); and(wire_nlO11ii_dataout, wire_nlO11lO_dataout, ~(n10l0Ol)); and(wire_nlO11il_dataout, n10l0Oi, ~(n10l0Ol)); and(wire_nlO11iO_dataout, wire_nlO11Oi_dataout, ~(n10l0Ol)); and(wire_nlO11li_dataout, wire_nlO11Ol_dataout, ~(n10l0Ol)); and(wire_nlO11ll_dataout, wire_nlO11OO_dataout, ~(n10l0Oi)); and(wire_nlO11lO_dataout, wire_nlO101i_dataout, ~(n10l0Oi)); and(wire_nlO11Oi_dataout, n10l0ll, ~(n10l0Oi)); and(wire_nlO11Ol_dataout, wire_nlO101l_dataout, ~(n10l0Oi)); and(wire_nlO11OO_dataout, wire_nlO101O_dataout, ~(n10l0ll)); assign wire_nlO1i_dataout = (nO === 1'b1) ? (~ pudi[0]) : pudi[0]; and(wire_nlO1i0i_dataout, wire_nlO1iiO_dataout, ~(n10li0l)); and(wire_nlO1i0l_dataout, n10liiO, ~(n10li0l)); and(wire_nlO1i0O_dataout, wire_nlO1ili_dataout, ~(n10liiO)); and(wire_nlO1i1i_dataout, wire_nlO1i0O_dataout, ~(n10li0l)); and(wire_nlO1i1l_dataout, wire_nlO1iii_dataout, ~(n10li0l)); and(wire_nlO1i1O_dataout, wire_nlO1iil_dataout, ~(n10li0l)); and(wire_nlO1iii_dataout, wire_nlO1ill_dataout, ~(n10liiO)); and(wire_nlO1iil_dataout, n10li1i, ~(n10liiO)); and(wire_nlO1iiO_dataout, wire_nlO1ilO_dataout, ~(n10liiO)); and(wire_nlO1ili_dataout, wire_nlO1iOi_dataout, ~(n10li1i)); and(wire_nlO1ill_dataout, n10li1l, ~(n10li1i)); and(wire_nlO1ilO_dataout, wire_nlO1iOl_dataout, ~(n10li1i)); and(wire_nlO1iOi_dataout, wire_nlO1iOO_dataout, ~(n10li1l)); and(wire_nlO1iOl_dataout, n10li1O, ~(n10li1l)); and(wire_nlO1iOO_dataout, (~ n10li0i), ~(n10li1O)); assign wire_nlO1l_dataout = (nO === 1'b1) ? (~ pudi[1]) : pudi[1]; and(wire_nlO1l0i_dataout, n10liiO, ~(n10liil)); and(wire_nlO1l0l_dataout, wire_nlO1lil_dataout, ~(n10ll0i)); and(wire_nlO1l0O_dataout, wire_nlO1liO_dataout, ~(n10ll0i)); and(wire_nlO1l1l_dataout, wire_nlO101O_dataout, ~(n10liil)); and(wire_nlO1l1O_dataout, wire_nlO100i_dataout, ~(n10liil)); and(wire_nlO1lii_dataout, n10lill, ~(n10ll0i)); and(wire_nlO1lil_dataout, (~ n10lilO), ~(n10lill)); and(wire_nlO1liO_dataout, n10lilO, ~(n10lill)); assign wire_nlO1O_dataout = (nO === 1'b1) ? (~ pudi[2]) : pudi[2]; and(wire_nlO1O0i_dataout, n10liOi, ~(n10ll1i)); and(wire_nlO1O0l_dataout, (~ n10lilO), ~(n10liOi)); and(wire_nlO1O0O_dataout, n10lilO, ~(n10liOi)); and(wire_nlO1O1l_dataout, wire_nlO1O0l_dataout, ~(n10ll1i)); and(wire_nlO1O1O_dataout, wire_nlO1O0O_dataout, ~(n10ll1i)); and(wire_nlO1Oll_dataout, n10ll1l, ~((~ niii0l))); and(wire_nlO1OlO_dataout, (~ n10ll1l), ~((~ niii0l))); and(wire_nlOi_dataout, wire_nl0li1i_o, wa_6g_en); or(wire_nlOi00l_dataout, n1i0l0l, n1i0l0O); or(wire_nlOi0li_dataout, n1i0l1O, n1i0l0i); or(wire_nlOi10l_dataout, n1i0lll, n1i0llO); or(wire_nlOi1li_dataout, n1i0liO, n1i0lli); or(wire_nlOi1OO_dataout, n1i0lii, n1i0lil); assign wire_nlOii_dataout = (nO === 1'b1) ? (~ pudi[6]) : pudi[6]; assign wire_nlOil_dataout = (nO === 1'b1) ? (~ pudi[7]) : pudi[7]; assign wire_nlOiO_dataout = (nO === 1'b1) ? (~ pudi[8]) : pudi[8]; assign wire_nlOl_dataout = (wa_6g_en === 1'b1) ? n1iiilO : nllll1i; assign wire_nlOli_dataout = (nO === 1'b1) ? (~ pudi[9]) : pudi[9]; assign wire_nlOll_dataout = (nO === 1'b1) ? (~ pudi[10]) : pudi[10]; assign wire_nlOll0O_dataout = (((((~ wire_niOiOl_o) & n10lllO) | (wire_niOiOl_o & n1i001i)) | (n1i00il & n1i000l)) === 1'b1) ? niii0i : (n1i001l | n1i001O); assign wire_nlOlO_dataout = (nO === 1'b1) ? (~ pudi[11]) : pudi[11]; assign wire_nlOO_dataout = (wa_6g_en === 1'b1) ? nll01li : nlO011i; assign wire_nlOOi_dataout = (nO === 1'b1) ? (~ pudi[12]) : pudi[12]; assign wire_nlOOl_dataout = (nO === 1'b1) ? (~ pudi[13]) : pudi[13]; assign wire_nlOOO_dataout = (nO === 1'b1) ? (~ pudi[14]) : pudi[14]; oper_add n011ili ( .a({1'b0, max_rlv_sel[5:0]}), .b({{3{1'b0}}, max_rlv_sel[5:2]}), .cin(1'b0), .cout(), .o(wire_n011ili_o)); defparam n011ili.sgate_representation = 0, n011ili.width_a = 7, n011ili.width_b = 7, n011ili.width_o = 7; oper_add n1li0i ( .a({1'b0, wire_n1ll1O_o, wire_n1ll1l_o, wire_n1ll1i_o, wire_n1liOO_o}), .b({1'b0, wire_n1liOi_o, wire_n1lilO_o, wire_n1lill_o, wire_n1lili_o}), .cin(1'b0), .cout(), .o(wire_n1li0i_o)); defparam n1li0i.sgate_representation = 0, n1li0i.width_a = 5, n1li0i.width_b = 5, n1li0i.width_o = 5; oper_add n1li1O ( .a({wire_n1liiO_dataout, wire_n1liil_dataout, wire_n1li0O_dataout, wire_n1li0l_dataout}), .b({{3{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_n1li1O_o)); defparam n1li1O.sgate_representation = 0, n1li1O.width_a = 4, n1li1O.width_b = 4, n1li1O.width_o = 4; oper_add n1O0lO ( .a({{2{1'b0}}, (~ n10O0li), max_rlv_sel[4:2]}), .b({(~ n10O0li), max_rlv_sel[4:0]}), .cin(1'b0), .cout(), .o(wire_n1O0lO_o)); defparam n1O0lO.sgate_representation = 0, n1O0lO.width_a = 6, n1O0lO.width_b = 6, n1O0lO.width_o = 6; oper_add n1Ol0Ol ( .a({wire_n1Oli0O_dataout, wire_n1Oli0l_dataout, wire_n1Oli1O_dataout, wire_n1Oli1l_dataout, wire_n1Oli1i_dataout}), .b({{4{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_n1Ol0Ol_o)); defparam n1Ol0Ol.sgate_representation = 0, n1Ol0Ol.width_a = 5, n1Ol0Ol.width_b = 5, n1Ol0Ol.width_o = 5; oper_add n1Ol0OO ( .a({1'b0, wire_n1Oll1l_o, wire_n1Oll1i_o, wire_n1OliOO_o, wire_n1OliOl_o, wire_n1OliOi_o}), .b({1'b0, wire_n1Olill_o, wire_n1Olili_o, wire_n1OliiO_o, wire_n1Oliil_o, wire_n1Oliii_o}), .cin(1'b0), .cout(), .o(wire_n1Ol0OO_o)); defparam n1Ol0OO.sgate_representation = 0, n1Ol0OO.width_a = 6, n1Ol0OO.width_b = 6, n1Ol0OO.width_o = 6; oper_add nl0iiOl ( .a({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O}), .b({{4{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_nl0iiOl_o)); defparam nl0iiOl.sgate_representation = 0, nl0iiOl.width_a = 5, nl0iiOl.width_b = 5, nl0iiOl.width_o = 5; oper_add nl1iil ( .a({nl10Oi, nl10ll, nl10li, nl10il, 1'b1}), .b({{3{1'b1}}, 1'b0, 1'b1}), .cin(1'b0), .cout(), .o(wire_nl1iil_o)); defparam nl1iil.sgate_representation = 0, nl1iil.width_a = 5, nl1iil.width_b = 5, nl1iil.width_o = 5; oper_add nllO1lO ( .a({nlO0i1i, nlO00OO, nlO00Ol, nlO00Oi, nlO00lO, nlO00ll, nlO00li, nlO00iO, nlO00il, nlO00ii, 1'b1}), .b({{9{1'b1}}, 1'b0, 1'b1}), .cin(1'b0), .cout(), .o(wire_nllO1lO_o)); defparam nllO1lO.sgate_representation = 0, nllO1lO.width_a = 11, nllO1lO.width_b = 11, nllO1lO.width_o = 11; oper_add nllO1Oi ( .a({nlO000O, nlO000l, nlO000i, nlO001O, nlO001l, nlO001i, nlO01OO, nlO01Ol, nlO01Oi, nlO01lO}), .b({{9{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_nllO1Oi_o)); defparam nllO1Oi.sgate_representation = 0, nllO1Oi.width_a = 10, nllO1Oi.width_b = 10, nllO1Oi.width_o = 10; oper_add nllO1Ol ( .a({nlO0i1i, nlO00OO, nlO00Ol, nlO00Oi, nlO00lO, nlO00ll, nlO00li, nlO00iO, nlO00il, nlO00ii}), .b({{9{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_nllO1Ol_o)); defparam nllO1Ol.sgate_representation = 0, nllO1Ol.width_a = 10, nllO1Ol.width_b = 10, nllO1Ol.width_o = 10; oper_add nllO1OO ( .a({nlO0ill, nlO0ili, nlO0iiO, nlO0iil, nlO0iii, nlO0i0O, nlO0i0l, nlO0i0i, nlO0i1O, nlO0i1l}), .b({{9{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_nllO1OO_o)); defparam nllO1OO.sgate_representation = 0, nllO1OO.width_a = 10, nllO1OO.width_b = 10, nllO1OO.width_o = 10; oper_add nlO0l0i ( .a({nlO01ll, nlO01li, nlO01iO, nlO01il}), .b({{3{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_nlO0l0i_o)); defparam nlO0l0i.sgate_representation = 0, nlO0l0i.width_a = 4, nlO0l0i.width_b = 4, nlO0l0i.width_o = 4; oper_less_than n1Oill ( .a({wire_n1O0ll_dataout, wire_n1O0li_dataout, wire_n1O0iO_dataout, wire_n1O0il_dataout, wire_n1O0ii_dataout, wire_n1O00O_dataout, wire_n1O00l_dataout, wire_n1O00i_dataout}), .b({n1l0lO, n1l0ll, n1l0li, n1l0iO, n1l0il, n1l0ii, n1l00O, n1liii}), .cin(1'b0), .o(wire_n1Oill_o)); defparam n1Oill.sgate_representation = 0, n1Oill.width_a = 8, n1Oill.width_b = 8; oper_less_than n1OOi1l ( .a({wire_n011i1l_dataout, wire_n011i1i_dataout, wire_n0110OO_dataout, wire_n0110Ol_dataout, wire_n0110Oi_dataout, wire_n0110lO_dataout, wire_n0110ll_dataout, wire_n0110li_dataout, wire_n0110iO_dataout, 1'b0}), .b({n1Ol0ii, n1Ol00O, n1Ol00l, n1Ol00i, n1Ol01O, n1Ol01l, n1Ol01i, n1Ol1OO, n1Ol1Ol, n1Oli0i}), .cin(1'b0), .o(wire_n1OOi1l_o)); defparam n1OOi1l.sgate_representation = 0, n1OOi1l.width_a = 10, n1OOi1l.width_b = 10; oper_less_than nl0iiOO ( .a({1'b1, {2{1'b0}}, {2{1'b1}}}), .b({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O}), .cin(1'b1), .o(wire_nl0iiOO_o)); defparam nl0iiOO.sgate_representation = 0, nl0iiOO.width_a = 5, nl0iiOO.width_b = 5; oper_less_than nl0illl ( .a({1'b0, {4{1'b1}}}), .b({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O}), .cin(1'b1), .o(wire_nl0illl_o)); defparam nl0illl.sgate_representation = 0, nl0illl.width_a = 5, nl0illl.width_b = 5; oper_less_than nl0iOii ( .a({1'b0, 1'b1, {2{1'b0}}, 1'b1}), .b({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O}), .cin(1'b1), .o(wire_nl0iOii_o)); defparam nl0iOii.sgate_representation = 0, nl0iOii.width_a = 5, nl0iOii.width_b = 5; oper_less_than nl0l11O ( .a({{2{1'b0}}, {3{1'b1}}}), .b({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O}), .cin(1'b1), .o(wire_nl0l11O_o)); defparam nl0l11O.sgate_representation = 0, nl0l11O.width_a = 5, nl0l11O.width_b = 5; oper_less_than nllOO1l ( .a({nlO0i1i, nlO00OO, nlO00Ol, nlO00Oi, nlO00lO, nlO00ll, nlO00li, nlO00iO, nlO00il, nlO00ii}), .b({{9{1'b0}}, 1'b1}), .cin(1'b1), .o(wire_nllOO1l_o)); defparam nllOO1l.sgate_representation = 0, nllOO1l.width_a = 10, nllOO1l.width_b = 10; oper_less_than nlO10Ol ( .a({{9{1'b0}}, 1'b1}), .b({nlO0i1i, nlO00OO, nlO00Ol, nlO00Oi, nlO00lO, nlO00ll, nlO00li, nlO00iO, nlO00il, nlO00ii}), .cin(1'b0), .o(wire_nlO10Ol_o)); defparam nlO10Ol.sgate_representation = 0, nlO10Ol.width_a = 10, nlO10Ol.width_b = 10; oper_mux niOO0l ( .data({{6{nliO1l}}, nliO1O, nliO0i, nliO0l, nliO0O, nliOii, nliOil, nliOiO, nliOli, nliOll, nliOlO}), .o(wire_niOO0l_o), .sel({wire_nl011l_dataout, wire_nl011i_dataout, wire_nl1OOO_dataout, wire_nl1OOl_dataout})); defparam niOO0l.width_data = 16, niOO0l.width_sel = 4; oper_mux niOO0O ( .data({{6{nliO1O}}, nliO0i, nliO0l, nliO0O, nliOii, nliOil, nliOiO, nliOli, nliOll, nliOlO, nliOOi}), .o(wire_niOO0O_o), .sel({wire_nl011l_dataout, wire_nl011i_dataout, wire_nl1OOO_dataout, wire_nl1OOl_dataout})); defparam niOO0O.width_data = 16, niOO0O.width_sel = 4; oper_mux niOOii ( .data({{6{nliO0i}}, nliO0l, nliO0O, nliOii, nliOil, nliOiO, nliOli, nliOll, nliOlO, nliOOi, nliOOl}), .o(wire_niOOii_o), .sel({wire_nl011l_dataout, wire_nl011i_dataout, wire_nl1OOO_dataout, wire_nl1OOl_dataout})); defparam niOOii.width_data = 16, niOOii.width_sel = 4; oper_mux niOOil ( .data({{6{nliO0l}}, nliO0O, nliOii, nliOil, nliOiO, nliOli, nliOll, nliOlO, nliOOi, nliOOl, nliOOO}), .o(wire_niOOil_o), .sel({wire_nl011l_dataout, wire_nl011i_dataout, wire_nl1OOO_dataout, wire_nl1OOl_dataout})); defparam niOOil.width_data = 16, niOOil.width_sel = 4; oper_mux niOOiO ( .data({{6{nliO0O}}, nliOii, nliOil, nliOiO, nliOli, nliOll, nliOlO, nliOOi, nliOOl, nliOOO, nll11i}), .o(wire_niOOiO_o), .sel({wire_nl011l_dataout, wire_nl011i_dataout, wire_nl1OOO_dataout, wire_nl1OOl_dataout})); defparam niOOiO.width_data = 16, niOOiO.width_sel = 4; oper_mux niOOli ( .data({{6{nliOii}}, nliOil, nliOiO, nliOli, nliOll, nliOlO, nliOOi, nliOOl, nliOOO, nll11i, nll11l}), .o(wire_niOOli_o), .sel({wire_nl011l_dataout, wire_nl011i_dataout, wire_nl1OOO_dataout, wire_nl1OOl_dataout})); defparam niOOli.width_data = 16, niOOli.width_sel = 4; oper_mux niOOll ( .data({{6{nliOil}}, nliOiO, nliOli, nliOll, nliOlO, nliOOi, nliOOl, nliOOO, nll11i, nll11l, nll11O}), .o(wire_niOOll_o), .sel({wire_nl011l_dataout, wire_nl011i_dataout, wire_nl1OOO_dataout, wire_nl1OOl_dataout})); defparam niOOll.width_data = 16, niOOll.width_sel = 4; oper_mux niOOlO ( .data({{6{nliOiO}}, nliOli, nliOll, nliOlO, nliOOi, nliOOl, nliOOO, nll11i, nll11l, nll11O, nll10i}), .o(wire_niOOlO_o), .sel({wire_nl011l_dataout, wire_nl011i_dataout, wire_nl1OOO_dataout, wire_nl1OOl_dataout})); defparam niOOlO.width_data = 16, niOOlO.width_sel = 4; oper_mux niOOOi ( .data({{6{nliOli}}, nliOll, nliOlO, nliOOi, nliOOl, nliOOO, nll11i, nll11l, nll11O, nll10i, nll10l}), .o(wire_niOOOi_o), .sel({wire_nl011l_dataout, wire_nl011i_dataout, wire_nl1OOO_dataout, wire_nl1OOl_dataout})); defparam niOOOi.width_data = 16, niOOOi.width_sel = 4; oper_mux niOOOl ( .data({{6{nliOll}}, nliOlO, nliOOi, nliOOl, nliOOO, nll11i, nll11l, nll11O, nll10i, nll10l, nll1ii}), .o(wire_niOOOl_o), .sel({wire_nl011l_dataout, wire_nl011i_dataout, wire_nl1OOO_dataout, wire_nl1OOl_dataout})); defparam niOOOl.width_data = 16, niOOOl.width_sel = 4; oper_mux nl00l0i ( .data({{16{nll0i0i}}, nll0l0i, nll0l1O, nll0l1l, nll0l1i, nll0iOO, nll0iOl, nll0iOi, nll0ilO, nll0ill, nll0ili, nll0iiO, nll0iil, nll0iii, nll0i0O, nll0i0l, nll0i0i}), .o(wire_nl00l0i_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl00l0i.width_data = 32, nl00l0i.width_sel = 5; oper_mux nl00l0l ( .data({{12{nll0i0i}}, nll0lil, nll0lii, nll0l0O, nll0l0l, nll0l0i, nll0l1O, nll0l1l, nll0l1i, nll0iOO, nll0iOl, nll0iOi, nll0ilO, nll0ill, nll0ili, nll0iiO, nll0iil, nll0iii, nll0i0O, nll0i0l, nll0i0i}), .o(wire_nl00l0l_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl00l0l.width_data = 32, nl00l0l.width_sel = 5; oper_mux nl00l0O ( .data({{16{nll01Ol}}, nll00Ol, nll00Oi, nll00lO, nll00ll, nll00li, nll00iO, nll00il, nll00ii, nll000O, nll000l, nll000i, nll001O, nll001l, nll001i, nll01OO, nll01Ol}), .o(wire_nl00l0O_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl00l0O.width_data = 32, nl00l0O.width_sel = 5; oper_mux nl00lii ( .data({{16{nll01OO}}, nll0i0i, nll00Ol, nll00Oi, nll00lO, nll00ll, nll00li, nll00iO, nll00il, nll00ii, nll000O, nll000l, nll000i, nll001O, nll001l, nll001i, nll01OO}), .o(wire_nl00lii_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl00lii.width_data = 32, nl00lii.width_sel = 5; oper_mux nl00lil ( .data({{16{nll001i}}, nll0i0l, nll0i0i, nll00Ol, nll00Oi, nll00lO, nll00ll, nll00li, nll00iO, nll00il, nll00ii, nll000O, nll000l, nll000i, nll001O, nll001l, nll001i}), .o(wire_nl00lil_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl00lil.width_data = 32, nl00lil.width_sel = 5; oper_mux nl00liO ( .data({{16{nll001l}}, nll0i0O, nll0i0l, nll0i0i, nll00Ol, nll00Oi, nll00lO, nll00ll, nll00li, nll00iO, nll00il, nll00ii, nll000O, nll000l, nll000i, nll001O, nll001l}), .o(wire_nl00liO_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl00liO.width_data = 32, nl00liO.width_sel = 5; oper_mux nl00lli ( .data({{16{nll001O}}, nll0iii, nll0i0O, nll0i0l, nll0i0i, nll00Ol, nll00Oi, nll00lO, nll00ll, nll00li, nll00iO, nll00il, nll00ii, nll000O, nll000l, nll000i, nll001O}), .o(wire_nl00lli_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl00lli.width_data = 32, nl00lli.width_sel = 5; oper_mux nl00lll ( .data({{16{nll000i}}, nll0iil, nll0iii, nll0i0O, nll0i0l, nll0i0i, nll00Ol, nll00Oi, nll00lO, nll00ll, nll00li, nll00iO, nll00il, nll00ii, nll000O, nll000l, nll000i}), .o(wire_nl00lll_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl00lll.width_data = 32, nl00lll.width_sel = 5; oper_mux nl00llO ( .data({{16{nll000l}}, nll0iiO, nll0iil, nll0iii, nll0i0O, nll0i0l, nll0i0i, nll00Ol, nll00Oi, nll00lO, nll00ll, nll00li, nll00iO, nll00il, nll00ii, nll000O, nll000l}), .o(wire_nl00llO_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl00llO.width_data = 32, nl00llO.width_sel = 5; oper_mux nl00lOi ( .data({{16{nll000O}}, nll0ili, nll0iiO, nll0iil, nll0iii, nll0i0O, nll0i0l, nll0i0i, nll00Ol, nll00Oi, nll00lO, nll00ll, nll00li, nll00iO, nll00il, nll00ii, nll000O}), .o(wire_nl00lOi_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl00lOi.width_data = 32, nl00lOi.width_sel = 5; oper_mux nl00lOl ( .data({{16{nll00ii}}, nll0ill, nll0ili, nll0iiO, nll0iil, nll0iii, nll0i0O, nll0i0l, nll0i0i, nll00Ol, nll00Oi, nll00lO, nll00ll, nll00li, nll00iO, nll00il, nll00ii}), .o(wire_nl00lOl_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl00lOl.width_data = 32, nl00lOl.width_sel = 5; oper_mux nl00lOO ( .data({{16{nll00il}}, nll0ilO, nll0ill, nll0ili, nll0iiO, nll0iil, nll0iii, nll0i0O, nll0i0l, nll0i0i, nll00Ol, nll00Oi, nll00lO, nll00ll, nll00li, nll00iO, nll00il}), .o(wire_nl00lOO_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl00lOO.width_data = 32, nl00lOO.width_sel = 5; oper_mux nl00O0i ( .data({{16{nll00lO}}, nll0l1i, nll0iOO, nll0iOl, nll0iOi, nll0ilO, nll0ill, nll0ili, nll0iiO, nll0iil, nll0iii, nll0i0O, nll0i0l, nll0i0i, nll00Ol, nll00Oi, nll00lO}), .o(wire_nl00O0i_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl00O0i.width_data = 32, nl00O0i.width_sel = 5; oper_mux nl00O0l ( .data({{16{nll00Oi}}, nll0l1l, nll0l1i, nll0iOO, nll0iOl, nll0iOi, nll0ilO, nll0ill, nll0ili, nll0iiO, nll0iil, nll0iii, nll0i0O, nll0i0l, nll0i0i, nll00Ol, nll00Oi}), .o(wire_nl00O0l_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl00O0l.width_data = 32, nl00O0l.width_sel = 5; oper_mux nl00O0O ( .data({{16{nll00Ol}}, nll0l1O, nll0l1l, nll0l1i, nll0iOO, nll0iOl, nll0iOi, nll0ilO, nll0ill, nll0ili, nll0iiO, nll0iil, nll0iii, nll0i0O, nll0i0l, nll0i0i, nll00Ol}), .o(wire_nl00O0O_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl00O0O.width_data = 32, nl00O0O.width_sel = 5; oper_mux nl00O1i ( .data({{16{nll00iO}}, nll0iOi, nll0ilO, nll0ill, nll0ili, nll0iiO, nll0iil, nll0iii, nll0i0O, nll0i0l, nll0i0i, nll00Ol, nll00Oi, nll00lO, nll00ll, nll00li, nll00iO}), .o(wire_nl00O1i_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl00O1i.width_data = 32, nl00O1i.width_sel = 5; oper_mux nl00O1l ( .data({{16{nll00li}}, nll0iOl, nll0iOi, nll0ilO, nll0ill, nll0ili, nll0iiO, nll0iil, nll0iii, nll0i0O, nll0i0l, nll0i0i, nll00Ol, nll00Oi, nll00lO, nll00ll, nll00li}), .o(wire_nl00O1l_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl00O1l.width_data = 32, nl00O1l.width_sel = 5; oper_mux nl00O1O ( .data({{16{nll00ll}}, nll0iOO, nll0iOl, nll0iOi, nll0ilO, nll0ill, nll0ili, nll0iiO, nll0iil, nll0iii, nll0i0O, nll0i0l, nll0i0i, nll00Ol, nll00Oi, nll00lO, nll00ll}), .o(wire_nl00O1O_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl00O1O.width_data = 32, nl00O1O.width_sel = 5; oper_mux nl00Oil ( .data({{12{nll01Ol}}, nll0i1O, nll0i1l, nll0i1i, nll00OO, nll00Ol, nll00Oi, nll00lO, nll00ll, nll00li, nll00iO, nll00il, nll00ii, nll000O, nll000l, nll000i, nll001O, nll001l, nll001i, nll01OO, nll01Ol}), .o(wire_nl00Oil_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl00Oil.width_data = 32, nl00Oil.width_sel = 5; oper_mux nl00OiO ( .data({{12{nll01OO}}, nll0i0i, nll0i1O, nll0i1l, nll0i1i, nll00OO, nll00Ol, nll00Oi, nll00lO, nll00ll, nll00li, nll00iO, nll00il, nll00ii, nll000O, nll000l, nll000i, nll001O, nll001l, nll001i, nll01OO}), .o(wire_nl00OiO_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl00OiO.width_data = 32, nl00OiO.width_sel = 5; oper_mux nl00Oli ( .data({{12{nll001i}}, nll0i0l, nll0i0i, nll0i1O, nll0i1l, nll0i1i, nll00OO, nll00Ol, nll00Oi, nll00lO, nll00ll, nll00li, nll00iO, nll00il, nll00ii, nll000O, nll000l, nll000i, nll001O, nll001l, nll001i}), .o(wire_nl00Oli_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl00Oli.width_data = 32, nl00Oli.width_sel = 5; oper_mux nl00Oll ( .data({{12{nll001l}}, nll0i0O, nll0i0l, nll0i0i, nll0i1O, nll0i1l, nll0i1i, nll00OO, nll00Ol, nll00Oi, nll00lO, nll00ll, nll00li, nll00iO, nll00il, nll00ii, nll000O, nll000l, nll000i, nll001O, nll001l}), .o(wire_nl00Oll_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl00Oll.width_data = 32, nl00Oll.width_sel = 5; oper_mux nl00OlO ( .data({{12{nll001O}}, nll0iii, nll0i0O, nll0i0l, nll0i0i, nll0i1O, nll0i1l, nll0i1i, nll00OO, nll00Ol, nll00Oi, nll00lO, nll00ll, nll00li, nll00iO, nll00il, nll00ii, nll000O, nll000l, nll000i, nll001O}), .o(wire_nl00OlO_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl00OlO.width_data = 32, nl00OlO.width_sel = 5; oper_mux nl00OOi ( .data({{12{nll000i}}, nll0iil, nll0iii, nll0i0O, nll0i0l, nll0i0i, nll0i1O, nll0i1l, nll0i1i, nll00OO, nll00Ol, nll00Oi, nll00lO, nll00ll, nll00li, nll00iO, nll00il, nll00ii, nll000O, nll000l, nll000i}), .o(wire_nl00OOi_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl00OOi.width_data = 32, nl00OOi.width_sel = 5; oper_mux nl00OOl ( .data({{12{nll000l}}, nll0iiO, nll0iil, nll0iii, nll0i0O, nll0i0l, nll0i0i, nll0i1O, nll0i1l, nll0i1i, nll00OO, nll00Ol, nll00Oi, nll00lO, nll00ll, nll00li, nll00iO, nll00il, nll00ii, nll000O, nll000l}), .o(wire_nl00OOl_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl00OOl.width_data = 32, nl00OOl.width_sel = 5; oper_mux nl00OOO ( .data({{12{nll000O}}, nll0ili, nll0iiO, nll0iil, nll0iii, nll0i0O, nll0i0l, nll0i0i, nll0i1O, nll0i1l, nll0i1i, nll00OO, nll00Ol, nll00Oi, nll00lO, nll00ll, nll00li, nll00iO, nll00il, nll00ii, nll000O}), .o(wire_nl00OOO_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl00OOO.width_data = 32, nl00OOO.width_sel = 5; oper_mux nl0i0Ol ( .data({wire_nl0ii0i_dataout, wire_nl0il1i_dataout, wire_nl0illO_dataout, wire_nl0iOil_dataout}), .o(wire_nl0i0Ol_o), .sel({pmadwidth[1:0]})); defparam nl0i0Ol.width_data = 4, nl0i0Ol.width_sel = 2; oper_mux nl0i0OO ( .data({wire_nl0ii0l_dataout, wire_nl0il1l_dataout, wire_nl0ilOi_dataout, wire_nl0iOiO_dataout}), .o(wire_nl0i0OO_o), .sel({pmadwidth[1:0]})); defparam nl0i0OO.width_data = 4, nl0i0OO.width_sel = 2; oper_mux nl0i10i ( .data({{12{nll00li}}, nll0iOl, nll0iOi, nll0ilO, nll0ill, nll0ili, nll0iiO, nll0iil, nll0iii, nll0i0O, nll0i0l, nll0i0i, nll0i1O, nll0i1l, nll0i1i, nll00OO, nll00Ol, nll00Oi, nll00lO, nll00ll, nll00li}), .o(wire_nl0i10i_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl0i10i.width_data = 32, nl0i10i.width_sel = 5; oper_mux nl0i10l ( .data({{12{nll00ll}}, nll0iOO, nll0iOl, nll0iOi, nll0ilO, nll0ill, nll0ili, nll0iiO, nll0iil, nll0iii, nll0i0O, nll0i0l, nll0i0i, nll0i1O, nll0i1l, nll0i1i, nll00OO, nll00Ol, nll00Oi, nll00lO, nll00ll}), .o(wire_nl0i10l_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl0i10l.width_data = 32, nl0i10l.width_sel = 5; oper_mux nl0i10O ( .data({{12{nll00lO}}, nll0l1i, nll0iOO, nll0iOl, nll0iOi, nll0ilO, nll0ill, nll0ili, nll0iiO, nll0iil, nll0iii, nll0i0O, nll0i0l, nll0i0i, nll0i1O, nll0i1l, nll0i1i, nll00OO, nll00Ol, nll00Oi, nll00lO}), .o(wire_nl0i10O_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl0i10O.width_data = 32, nl0i10O.width_sel = 5; oper_mux nl0i11i ( .data({{12{nll00ii}}, nll0ill, nll0ili, nll0iiO, nll0iil, nll0iii, nll0i0O, nll0i0l, nll0i0i, nll0i1O, nll0i1l, nll0i1i, nll00OO, nll00Ol, nll00Oi, nll00lO, nll00ll, nll00li, nll00iO, nll00il, nll00ii}), .o(wire_nl0i11i_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl0i11i.width_data = 32, nl0i11i.width_sel = 5; oper_mux nl0i11l ( .data({{12{nll00il}}, nll0ilO, nll0ill, nll0ili, nll0iiO, nll0iil, nll0iii, nll0i0O, nll0i0l, nll0i0i, nll0i1O, nll0i1l, nll0i1i, nll00OO, nll00Ol, nll00Oi, nll00lO, nll00ll, nll00li, nll00iO, nll00il}), .o(wire_nl0i11l_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl0i11l.width_data = 32, nl0i11l.width_sel = 5; oper_mux nl0i11O ( .data({{12{nll00iO}}, nll0iOi, nll0ilO, nll0ill, nll0ili, nll0iiO, nll0iil, nll0iii, nll0i0O, nll0i0l, nll0i0i, nll0i1O, nll0i1l, nll0i1i, nll00OO, nll00Ol, nll00Oi, nll00lO, nll00ll, nll00li, nll00iO}), .o(wire_nl0i11O_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl0i11O.width_data = 32, nl0i11O.width_sel = 5; oper_mux nl0i1ii ( .data({{12{nll00Oi}}, nll0l1l, nll0l1i, nll0iOO, nll0iOl, nll0iOi, nll0ilO, nll0ill, nll0ili, nll0iiO, nll0iil, nll0iii, nll0i0O, nll0i0l, nll0i0i, nll0i1O, nll0i1l, nll0i1i, nll00OO, nll00Ol, nll00Oi}), .o(wire_nl0i1ii_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl0i1ii.width_data = 32, nl0i1ii.width_sel = 5; oper_mux nl0i1il ( .data({{12{nll00Ol}}, nll0l1O, nll0l1l, nll0l1i, nll0iOO, nll0iOl, nll0iOi, nll0ilO, nll0ill, nll0ili, nll0iiO, nll0iil, nll0iii, nll0i0O, nll0i0l, nll0i0i, nll0i1O, nll0i1l, nll0i1i, nll00OO, nll00Ol}), .o(wire_nl0i1il_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl0i1il.width_data = 32, nl0i1il.width_sel = 5; oper_mux nl0i1iO ( .data({{12{nll00OO}}, nll0l0i, nll0l1O, nll0l1l, nll0l1i, nll0iOO, nll0iOl, nll0iOi, nll0ilO, nll0ill, nll0ili, nll0iiO, nll0iil, nll0iii, nll0i0O, nll0i0l, nll0i0i, nll0i1O, nll0i1l, nll0i1i, nll00OO}), .o(wire_nl0i1iO_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl0i1iO.width_data = 32, nl0i1iO.width_sel = 5; oper_mux nl0i1li ( .data({{12{nll0i1i}}, nll0l0l, nll0l0i, nll0l1O, nll0l1l, nll0l1i, nll0iOO, nll0iOl, nll0iOi, nll0ilO, nll0ill, nll0ili, nll0iiO, nll0iil, nll0iii, nll0i0O, nll0i0l, nll0i0i, nll0i1O, nll0i1l, nll0i1i}), .o(wire_nl0i1li_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl0i1li.width_data = 32, nl0i1li.width_sel = 5; oper_mux nl0i1ll ( .data({{12{nll0i1l}}, nll0l0O, nll0l0l, nll0l0i, nll0l1O, nll0l1l, nll0l1i, nll0iOO, nll0iOl, nll0iOi, nll0ilO, nll0ill, nll0ili, nll0iiO, nll0iil, nll0iii, nll0i0O, nll0i0l, nll0i0i, nll0i1O, nll0i1l}), .o(wire_nl0i1ll_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl0i1ll.width_data = 32, nl0i1ll.width_sel = 5; oper_mux nl0i1lO ( .data({{12{nll0i1O}}, nll0lii, nll0l0O, nll0l0l, nll0l0i, nll0l1O, nll0l1l, nll0l1i, nll0iOO, nll0iOl, nll0iOi, nll0ilO, nll0ill, nll0ili, nll0iiO, nll0iil, nll0iii, nll0i0O, nll0i0l, nll0i0i, nll0i1O}), .o(wire_nl0i1lO_o), .sel({nl010ii, nl0100O, nl0100l, nl0100i, nl0101O})); defparam nl0i1lO.width_data = 32, nl0i1lO.width_sel = 5; oper_mux nl0ii1i ( .data({wire_nl0ii0O_dataout, wire_nl0il1O_dataout, wire_nl0ilOl_dataout, wire_nl0iOli_dataout}), .o(wire_nl0ii1i_o), .sel({pmadwidth[1:0]})); defparam nl0ii1i.width_data = 4, nl0ii1i.width_sel = 2; oper_mux nl0ii1l ( .data({wire_nl0iiii_dataout, wire_nl0il0i_dataout, wire_nl0ilOO_dataout, wire_nl0iOll_dataout}), .o(wire_nl0ii1l_o), .sel({pmadwidth[1:0]})); defparam nl0ii1l.width_data = 4, nl0ii1l.width_sel = 2; oper_mux nl0ii1O ( .data({wire_nl0iiil_dataout, wire_nl0il0l_dataout, wire_nl0iO1i_dataout, wire_nl0iOlO_dataout}), .o(wire_nl0ii1O_o), .sel({pmadwidth[1:0]})); defparam nl0ii1O.width_data = 4, nl0ii1O.width_sel = 2; oper_mux nl0l0OO ( .data({{2{n111OOO}}, n111O0O, n111OOO, n111O0O, n111OOO, n111O0O, ((comp_pat_porn & n111Oil) | n111Oii)}), .o(wire_nl0l0OO_o), .sel({comp_pat_size[2:0]})); defparam nl0l0OO.width_data = 8, nl0l0OO.width_sel = 3; oper_mux nl0li1i ( .data({{2{n11011O}}, n111OiO, n11011O, n111OiO, ((comp_pat_porn & n111Oll) | n111Oli), n111OlO, ((comp_pat_porn & n111OOl) | n111OOi)}), .o(wire_nl0li1i_o), .sel({comp_pat_size[2:0]})); defparam nl0li1i.width_data = 8, nl0li1i.width_sel = 3; oper_mux nl0OiOl ( .data({n10iOOi, n101iil, n11iO0i, n1000ll, n11lili, n10i1lO, n11O1Ol, n10iOOi}), .o(wire_nl0OiOl_o), .sel({comp_pat_size[2:0]})); defparam nl0OiOl.width_data = 8, nl0OiOl.width_sel = 3; oper_mux nl0OiOO ( .data({n10iOli, n101i1O, n11ilOl, n1000il, n11liii, n10i1iO, n11O1ll, n10iOli}), .o(wire_nl0OiOO_o), .sel({comp_pat_size[2:0]})); defparam nl0OiOO.width_data = 8, nl0OiOO.width_sel = 3; oper_mux nl0Ol0i ( .data({n10ilOi, n1011Oi, n11iiiO, n1001ll, n11l0li, n100OlO, n11lOOl, n10ilOi}), .o(wire_nl0Ol0i_o), .sel({comp_pat_size[2:0]})); defparam nl0Ol0i.width_data = 8, nl0Ol0i.width_sel = 3; oper_mux nl0Ol0l ( .data({n10illi, n1011il, n11ii0i, n1001il, n11l0ii, n100OiO, n11lOll, n10illi}), .o(wire_nl0Ol0l_o), .sel({comp_pat_size[2:0]})); defparam nl0Ol0l.width_data = 8, nl0Ol0l.width_sel = 3; oper_mux nl0Ol0O ( .data({n10ilii, n10111O, n11i0Ol, n10010l, n11l00i, n100O0O, n11lOil, n10ilii}), .o(wire_nl0Ol0O_o), .sel({comp_pat_size[2:0]})); defparam nl0Ol0O.width_data = 8, nl0Ol0O.width_sel = 3; oper_mux nl0Ol1i ( .data({n10iOii, n1010Oi, n11iliO, n10000l, n11li0i, n10i10O, n11O1il, n10iOii}), .o(wire_nl0Ol1i_o), .sel({comp_pat_size[2:0]})); defparam nl0Ol1i.width_data = 8, nl0Ol1i.width_sel = 3; oper_mux nl0Ol1l ( .data({n10iO0i, n1010il, n11il0i, n10001l, n11li1i, n10i11O, n11O10l, n10iO0i}), .o(wire_nl0Ol1l_o), .sel({comp_pat_size[2:0]})); defparam nl0Ol1l.width_data = 8, nl0Ol1l.width_sel = 3; oper_mux nl0Ol1O ( .data({n10iO1i, n10101O, n11iiOl, n1001Ol, n11l0Oi, n100OOO, n11O11l, n10iO1i}), .o(wire_nl0Ol1O_o), .sel({comp_pat_size[2:0]})); defparam nl0Ol1O.width_data = 8, nl0Ol1O.width_sel = 3; oper_mux nl0Olii ( .data({n10il0i, n11OOOi, n11i0iO, n10011l, n11l01i, n100O1O, n11lO0l, n10il0i}), .o(wire_nl0Olii_o), .sel({comp_pat_size[2:0]})); defparam nl0Olii.width_data = 8, nl0Olii.width_sel = 3; oper_mux nl0Olil ( .data({n10il1i, n11OOil, n11i00i, n101OOl, n11l1Oi, n100lOO, n11lO1l, n10il1i}), .o(wire_nl0Olil_o), .sel({comp_pat_size[2:0]})); defparam nl0Olil.width_data = 8, nl0Olil.width_sel = 3; oper_mux nl0OliO ( .data({n10iiOi, n11OO1O, n11i1Ol, n101Oll, n11l1li, n100llO, n11llOl, n10iiOi}), .o(wire_nl0OliO_o), .sel({comp_pat_size[2:0]})); defparam nl0OliO.width_data = 8, nl0OliO.width_sel = 3; oper_mux nl0Olli ( .data({n10iili, n11OlOi, n11i1iO, n101Oil, n11l1ii, n100liO, n11llll, n10iili}), .o(wire_nl0Olli_o), .sel({comp_pat_size[2:0]})); defparam nl0Olli.width_data = 8, nl0Olli.width_sel = 3; oper_mux nl0Olll ( .data({n10iiii, n11Olil, n11i10i, n101O0l, n11l10i, n100l0O, n11llil, n10iiii}), .o(wire_nl0Olll_o), .sel({comp_pat_size[2:0]})); defparam nl0Olll.width_data = 8, nl0Olll.width_sel = 3; oper_mux nl0OllO ( .data({n10ii0i, n11Ol1O, n110OOl, n101O1l, n11l11i, n100l1O, n11ll0l, n10ii0i}), .o(wire_nl0OllO_o), .sel({comp_pat_size[2:0]})); defparam nl0OllO.width_data = 8, nl0OllO.width_sel = 3; oper_mux nl0OlOi ( .data({n10ii1i, n11OiOi, n110OiO, n101lOl, n11iOOi, n100iOO, n11ll1l, n10ii1i}), .o(wire_nl0OlOi_o), .sel({comp_pat_size[2:0]})); defparam nl0OlOi.width_data = 8, nl0OlOi.width_sel = 3; oper_mux nl0OlOl ( .data({n10i0Oi, n11Oiil, n110O0i, n101lll, n11iOli, n100ilO, n11liOl, n10i0Oi}), .o(wire_nl0OlOl_o), .sel({comp_pat_size[2:0]})); defparam nl0OlOl.width_data = 8, nl0OlOl.width_sel = 3; oper_mux nl0OlOO ( .data({n10i0li, n11Oi1O, 1'b0, n101lil, 1'b0, n100iiO, 1'b0, n10i0li}), .o(wire_nl0OlOO_o), .sel({comp_pat_size[2:0]})); defparam nl0OlOO.width_data = 8, nl0OlOO.width_sel = 3; oper_mux nl0OO1i ( .data({n10i0ii, n11O0Oi, 1'b0, n101l0l, 1'b0, n100i0O, 1'b0, n10i0ii}), .o(wire_nl0OO1i_o), .sel({comp_pat_size[2:0]})); defparam nl0OO1i.width_data = 8, nl0OO1i.width_sel = 3; oper_mux nl0OO1l ( .data({n10i00i, n11O0il, 1'b0, n101l1l, 1'b0, n100i1O, 1'b0, n10i00i}), .o(wire_nl0OO1l_o), .sel({comp_pat_size[2:0]})); defparam nl0OO1l.width_data = 8, nl0OO1l.width_sel = 3; oper_mux nl0OO1O ( .data({n10i01i, n11O01O, 1'b0, n101iOl, 1'b0, n1000OO, 1'b0, n10i01i}), .o(wire_nl0OO1O_o), .sel({comp_pat_size[2:0]})); defparam nl0OO1O.width_data = 8, nl0OO1O.width_sel = 3; oper_mux nl100i ( .data({{6{nliOll}}, nliO1l, nliO1O, nliO0i, nliO0l, nliO0O, nliOii, nliOil, nliOiO, nliOli, {9{nliOll}}, {8{nl11il}}}), .o(wire_nl100i_o), .sel({pmadwidth[0], wire_nl011l_dataout, wire_nl011i_dataout, wire_nl1OOO_dataout, wire_nl1OOl_dataout})); defparam nl100i.width_data = 32, nl100i.width_sel = 5; oper_mux nl101i ( .data({{6{nliOil}}, nlilOl, nlilOO, nliO1i, nliO1l, nliO1O, nliO0i, nliO0l, nliO0O, nliOii, {9{nliOil}}, nliO1O, nliO0i, nliO0l, nliO0O, nliOii, nliOil, nliOiO, nliOli}), .o(wire_nl101i_o), .sel({pmadwidth[0], wire_nl011l_dataout, wire_nl011i_dataout, wire_nl1OOO_dataout, wire_nl1OOl_dataout})); defparam nl101i.width_data = 32, nl101i.width_sel = 5; oper_mux nl101l ( .data({{6{nliOiO}}, nlilOO, nliO1i, nliO1l, nliO1O, nliO0i, nliO0l, nliO0O, nliOii, nliOil, {9{nliOiO}}, nliO0i, nliO0l, nliO0O, nliOii, nliOil, nliOiO, nliOli, nliOll}), .o(wire_nl101l_o), .sel({pmadwidth[0], wire_nl011l_dataout, wire_nl011i_dataout, wire_nl1OOO_dataout, wire_nl1OOl_dataout})); defparam nl101l.width_data = 32, nl101l.width_sel = 5; oper_mux nl101O ( .data({{6{nliOli}}, nliO1i, nliO1l, nliO1O, nliO0i, nliO0l, nliO0O, nliOii, nliOil, nliOiO, {9{nliOli}}, {8{nl11ii}}}), .o(wire_nl101O_o), .sel({pmadwidth[0], wire_nl011l_dataout, wire_nl011i_dataout, wire_nl1OOO_dataout, wire_nl1OOl_dataout})); defparam nl101O.width_data = 32, nl101O.width_sel = 5; oper_mux nl11li ( .data({{6{nliO1l}}, nlilil, nliliO, nlilli, nlilll, nlillO, nlilOi, nlilOl, nlilOO, nliO1i, {9{nliO1l}}, nlillO, nlilOi, nlilOl, nlilOO, nliO1i, nliO1l, nliO1O, nliO0i}), .o(wire_nl11li_o), .sel({pmadwidth[0], wire_nl011l_dataout, wire_nl011i_dataout, wire_nl1OOO_dataout, wire_nl1OOl_dataout})); defparam nl11li.width_data = 32, nl11li.width_sel = 5; oper_mux nl11ll ( .data({{6{nliO1O}}, nliliO, nlilli, nlilll, nlillO, nlilOi, nlilOl, nlilOO, nliO1i, nliO1l, {9{nliO1O}}, nlilOi, nlilOl, nlilOO, nliO1i, nliO1l, nliO1O, nliO0i, nliO0l}), .o(wire_nl11ll_o), .sel({pmadwidth[0], wire_nl011l_dataout, wire_nl011i_dataout, wire_nl1OOO_dataout, wire_nl1OOl_dataout})); defparam nl11ll.width_data = 32, nl11ll.width_sel = 5; oper_mux nl11lO ( .data({{6{nliO0i}}, nlilli, nlilll, nlillO, nlilOi, nlilOl, nlilOO, nliO1i, nliO1l, nliO1O, {9{nliO0i}}, nlilOl, nlilOO, nliO1i, nliO1l, nliO1O, nliO0i, nliO0l, nliO0O}), .o(wire_nl11lO_o), .sel({pmadwidth[0], wire_nl011l_dataout, wire_nl011i_dataout, wire_nl1OOO_dataout, wire_nl1OOl_dataout})); defparam nl11lO.width_data = 32, nl11lO.width_sel = 5; oper_mux nl11Oi ( .data({{6{nliO0l}}, nlilll, nlillO, nlilOi, nlilOl, nlilOO, nliO1i, nliO1l, nliO1O, nliO0i, {9{nliO0l}}, nlilOO, nliO1i, nliO1l, nliO1O, nliO0i, nliO0l, nliO0O, nliOii}), .o(wire_nl11Oi_o), .sel({pmadwidth[0], wire_nl011l_dataout, wire_nl011i_dataout, wire_nl1OOO_dataout, wire_nl1OOl_dataout})); defparam nl11Oi.width_data = 32, nl11Oi.width_sel = 5; oper_mux nl11Ol ( .data({{6{nliO0O}}, nlillO, nlilOi, nlilOl, nlilOO, nliO1i, nliO1l, nliO1O, nliO0i, nliO0l, {9{nliO0O}}, nliO1i, nliO1l, nliO1O, nliO0i, nliO0l, nliO0O, nliOii, nliOil}), .o(wire_nl11Ol_o), .sel({pmadwidth[0], wire_nl011l_dataout, wire_nl011i_dataout, wire_nl1OOO_dataout, wire_nl1OOl_dataout})); defparam nl11Ol.width_data = 32, nl11Ol.width_sel = 5; oper_mux nl11OO ( .data({{6{nliOii}}, nlilOi, nlilOl, nlilOO, nliO1i, nliO1l, nliO1O, nliO0i, nliO0l, nliO0O, {9{nliOii}}, nliO1l, nliO1O, nliO0i, nliO0l, nliO0O, nliOii, nliOil, nliOiO}), .o(wire_nl11OO_o), .sel({pmadwidth[0], wire_nl011l_dataout, wire_nl011i_dataout, wire_nl1OOO_dataout, wire_nl1OOl_dataout})); defparam nl11OO.width_data = 32, nl11OO.width_sel = 5; oper_mux nl1liiO ( .data({wire_nl1llOl_o, wire_nl1O10i_o, wire_nl1O00l_dataout, wire_nl1O0OO_dataout}), .o(wire_nl1liiO_o), .sel({pmadwidth[1:0]})); defparam nl1liiO.width_data = 4, nl1liiO.width_sel = 2; oper_mux nl1lili ( .data({wire_nl1llOO_o, wire_nl1O10l_o, wire_nl1O00O_dataout, wire_nl1Oi1i_dataout}), .o(wire_nl1lili_o), .sel({pmadwidth[1:0]})); defparam nl1lili.width_data = 4, nl1lili.width_sel = 2; oper_mux nl1lill ( .data({wire_nl1lO1i_o, wire_nl1O10O_o, wire_nl1O0ii_dataout, wire_nl1Oi1l_dataout}), .o(wire_nl1lill_o), .sel({pmadwidth[1:0]})); defparam nl1lill.width_data = 4, nl1lill.width_sel = 2; oper_mux nl1lilO ( .data({wire_nl1lO1l_o, wire_nl1O1ii_o, wire_nl1O0il_dataout, wire_nl1Oi1O_dataout}), .o(wire_nl1lilO_o), .sel({pmadwidth[1:0]})); defparam nl1lilO.width_data = 4, nl1lilO.width_sel = 2; oper_mux nl1liOi ( .data({wire_nl1lO1O_o, wire_nl1O1il_o, wire_nl1O0iO_dataout, wire_nl1Oi0i_dataout}), .o(wire_nl1liOi_o), .sel({pmadwidth[1:0]})); defparam nl1liOi.width_data = 4, nl1liOi.width_sel = 2; oper_mux nl1liOl ( .data({wire_nl1lO0i_o, wire_nl1O1iO_o, wire_nl1O0li_dataout, wire_nl1Oi0l_dataout}), .o(wire_nl1liOl_o), .sel({pmadwidth[1:0]})); defparam nl1liOl.width_data = 4, nl1liOl.width_sel = 2; oper_mux nl1liOO ( .data({wire_nl1lO0l_o, wire_nl1O1li_o, wire_nl1O0ll_dataout, wire_nl1Oi0O_dataout}), .o(wire_nl1liOO_o), .sel({pmadwidth[1:0]})); defparam nl1liOO.width_data = 4, nl1liOO.width_sel = 2; oper_mux nl1ll0i ( .data({wire_nl1lOiO_o, wire_nl1O1lO_o, nl01lil, nl01l0O}), .o(wire_nl1ll0i_o), .sel({pmadwidth[1:0]})); defparam nl1ll0i.width_data = 4, nl1ll0i.width_sel = 2; oper_mux nl1ll0l ( .data({wire_nl1lOli_o, wire_nl1O1Oi_o, nl01liO, nl01lii}), .o(wire_nl1ll0l_o), .sel({pmadwidth[1:0]})); defparam nl1ll0l.width_data = 4, nl1ll0l.width_sel = 2; oper_mux nl1ll0O ( .data({wire_nl1lOll_o, wire_nl1O1Ol_o, nl01lli, nl01lil}), .o(wire_nl1ll0O_o), .sel({pmadwidth[1:0]})); defparam nl1ll0O.width_data = 4, nl1ll0O.width_sel = 2; oper_mux nl1ll1i ( .data({wire_nl1lO0O_o, wire_nl1O1ll_o, wire_nl1O0lO_dataout, wire_nl1Oiii_dataout}), .o(wire_nl1ll1i_o), .sel({pmadwidth[1:0]})); defparam nl1ll1i.width_data = 4, nl1ll1i.width_sel = 2; oper_mux nl1ll1l ( .data({wire_nl1lOii_o, 1'b0, wire_nl1O0Oi_dataout, 1'b0}), .o(wire_nl1ll1l_o), .sel({pmadwidth[1:0]})); defparam nl1ll1l.width_data = 4, nl1ll1l.width_sel = 2; oper_mux nl1ll1O ( .data({wire_nl1lOil_o, 1'b0, wire_nl1O0Ol_dataout, 1'b0}), .o(wire_nl1ll1O_o), .sel({pmadwidth[1:0]})); defparam nl1ll1O.width_data = 4, nl1ll1O.width_sel = 2; oper_mux nl1llii ( .data({wire_nl1lOlO_o, wire_nl1O1OO_o, nl01lll, nl01liO}), .o(wire_nl1llii_o), .sel({pmadwidth[1:0]})); defparam nl1llii.width_data = 4, nl1llii.width_sel = 2; oper_mux nl1llil ( .data({wire_nl1lOOi_o, wire_nl1O01i_o, nl01llO, nl01lli}), .o(wire_nl1llil_o), .sel({pmadwidth[1:0]})); defparam nl1llil.width_data = 4, nl1llil.width_sel = 2; oper_mux nl1lliO ( .data({wire_nl1lOOl_o, wire_nl1O01l_o, nl01lOi, nl01lll}), .o(wire_nl1lliO_o), .sel({pmadwidth[1:0]})); defparam nl1lliO.width_data = 4, nl1lliO.width_sel = 2; oper_mux nl1llli ( .data({wire_nl1lOOO_o, wire_nl1O01O_o, nl01lOl, nl01llO}), .o(wire_nl1llli_o), .sel({pmadwidth[1:0]})); defparam nl1llli.width_data = 4, nl1llli.width_sel = 2; oper_mux nl1llll ( .data({wire_nl1O11i_o, wire_nl1O00i_o, nl01lOO, nl01lOi}), .o(wire_nl1llll_o), .sel({pmadwidth[1:0]})); defparam nl1llll.width_data = 4, nl1llll.width_sel = 2; oper_mux nl1lllO ( .data({wire_nl1O11l_o, 1'b0, nl01O1i, 1'b0}), .o(wire_nl1lllO_o), .sel({pmadwidth[1:0]})); defparam nl1lllO.width_data = 4, nl1lllO.width_sel = 2; oper_mux nl1llOi ( .data({wire_nl1O11O_o, 1'b0, nl01O1l, 1'b0}), .o(wire_nl1llOi_o), .sel({pmadwidth[1:0]})); defparam nl1llOi.width_data = 4, nl1llOi.width_sel = 2; oper_mux nl1llOl ( .data({nl01lii, nl01O1l, nl01lil, nl01iOi}), .o(wire_nl1llOl_o), .sel({nlli0li, nlli0il})); defparam nl1llOl.width_data = 4, nl1llOl.width_sel = 2; oper_mux nl1llOO ( .data({nl01l0O, nl01O1i, nl01liO, nl01iOl}), .o(wire_nl1llOO_o), .sel({nlli0li, nlli0il})); defparam nl1llOO.width_data = 4, nl1llOO.width_sel = 2; oper_mux nl1lO0i ( .data({nl01l1l, nl01llO, nl01lOi, nl01l1O}), .o(wire_nl1lO0i_o), .sel({nlli0li, nlli0il})); defparam nl1lO0i.width_data = 4, nl1lO0i.width_sel = 2; oper_mux nl1lO0l ( .data({nl01l1i, nl01lll, nl01lOl, nl01l0i}), .o(wire_nl1lO0l_o), .sel({nlli0li, nlli0il})); defparam nl1lO0l.width_data = 4, nl1lO0l.width_sel = 2; oper_mux nl1lO0O ( .data({nl01iOO, nl01lli, nl01lOO, nl01l0l}), .o(wire_nl1lO0O_o), .sel({nlli0li, nlli0il})); defparam nl1lO0O.width_data = 4, nl1lO0O.width_sel = 2; oper_mux nl1lO1i ( .data({nl01l0l, nl01lOO, nl01lli, nl01iOO}), .o(wire_nl1lO1i_o), .sel({nlli0li, nlli0il})); defparam nl1lO1i.width_data = 4, nl1lO1i.width_sel = 2; oper_mux nl1lO1l ( .data({nl01l0i, nl01lOl, nl01lll, nl01l1i}), .o(wire_nl1lO1l_o), .sel({nlli0li, nlli0il})); defparam nl1lO1l.width_data = 4, nl1lO1l.width_sel = 2; oper_mux nl1lO1O ( .data({nl01l1O, nl01lOi, nl01llO, nl01l1l}), .o(wire_nl1lO1O_o), .sel({nlli0li, nlli0il})); defparam nl1lO1O.width_data = 4, nl1lO1O.width_sel = 2; oper_mux nl1lOii ( .data({nl01iOl, nl01liO, nl01O1i, nl01l0O}), .o(wire_nl1lOii_o), .sel({nlli0li, nlli0il})); defparam nl1lOii.width_data = 4, nl1lOii.width_sel = 2; oper_mux nl1lOil ( .data({nl01iOi, nl01lil, nl01O1l, nl01lii}), .o(wire_nl1lOil_o), .sel({nlli0li, nlli0il})); defparam nl1lOil.width_data = 4, nl1lOil.width_sel = 2; oper_mux nl1lOiO ( .data({nl01O1l, nl01lii, nl01iOi, nl01lil}), .o(wire_nl1lOiO_o), .sel({nlli0li, nlli0il})); defparam nl1lOiO.width_data = 4, nl1lOiO.width_sel = 2; oper_mux nl1lOli ( .data({nl01O1i, nl01l0O, nl01iOl, nl01liO}), .o(wire_nl1lOli_o), .sel({nlli0li, nlli0il})); defparam nl1lOli.width_data = 4, nl1lOli.width_sel = 2; oper_mux nl1lOll ( .data({nl01lOO, nl01l0l, nl01iOO, nl01lli}), .o(wire_nl1lOll_o), .sel({nlli0li, nlli0il})); defparam nl1lOll.width_data = 4, nl1lOll.width_sel = 2; oper_mux nl1lOlO ( .data({nl01lOl, nl01l0i, nl01l1i, nl01lll}), .o(wire_nl1lOlO_o), .sel({nlli0li, nlli0il})); defparam nl1lOlO.width_data = 4, nl1lOlO.width_sel = 2; oper_mux nl1lOOi ( .data({nl01lOi, nl01l1O, nl01l1l, nl01llO}), .o(wire_nl1lOOi_o), .sel({nlli0li, nlli0il})); defparam nl1lOOi.width_data = 4, nl1lOOi.width_sel = 2; oper_mux nl1lOOl ( .data({nl01llO, nl01l1l, nl01l1O, nl01lOi}), .o(wire_nl1lOOl_o), .sel({nlli0li, nlli0il})); defparam nl1lOOl.width_data = 4, nl1lOOl.width_sel = 2; oper_mux nl1lOOO ( .data({nl01lll, nl01l1i, nl01l0i, nl01lOl}), .o(wire_nl1lOOO_o), .sel({nlli0li, nlli0il})); defparam nl1lOOO.width_data = 4, nl1lOOO.width_sel = 2; oper_mux nl1O00i ( .data({nl01l0O, nl01iOi, nl01l0l, nl01lOi}), .o(wire_nl1O00i_o), .sel({nlli0li, nlli0il})); defparam nl1O00i.width_data = 4, nl1O00i.width_sel = 2; oper_mux nl1O01i ( .data({nl01liO, nl01l1i, nl01l1l, nl01lli}), .o(wire_nl1O01i_o), .sel({nlli0li, nlli0il})); defparam nl1O01i.width_data = 4, nl1O01i.width_sel = 2; oper_mux nl1O01l ( .data({nl01lil, nl01iOO, nl01l1O, nl01lll}), .o(wire_nl1O01l_o), .sel({nlli0li, nlli0il})); defparam nl1O01l.width_data = 4, nl1O01l.width_sel = 2; oper_mux nl1O01O ( .data({nl01lii, nl01iOl, nl01l0i, nl01llO}), .o(wire_nl1O01O_o), .sel({nlli0li, nlli0il})); defparam nl1O01O.width_data = 4, nl1O01O.width_sel = 2; oper_mux nl1O10i ( .data({nl01l0l, nl01lOi, nl01l0O, nl01iOi}), .o(wire_nl1O10i_o), .sel({nlli0li, nlli0il})); defparam nl1O10i.width_data = 4, nl1O10i.width_sel = 2; oper_mux nl1O10l ( .data({nl01l0i, nl01llO, nl01lii, nl01iOl}), .o(wire_nl1O10l_o), .sel({nlli0li, nlli0il})); defparam nl1O10l.width_data = 4, nl1O10l.width_sel = 2; oper_mux nl1O10O ( .data({nl01l1O, nl01lll, nl01lil, nl01iOO}), .o(wire_nl1O10O_o), .sel({nlli0li, nlli0il})); defparam nl1O10O.width_data = 4, nl1O10O.width_sel = 2; oper_mux nl1O11i ( .data({nl01lli, nl01iOO, nl01l0l, nl01lOO}), .o(wire_nl1O11i_o), .sel({nlli0li, nlli0il})); defparam nl1O11i.width_data = 4, nl1O11i.width_sel = 2; oper_mux nl1O11l ( .data({nl01liO, nl01iOl, nl01l0O, nl01O1i}), .o(wire_nl1O11l_o), .sel({nlli0li, nlli0il})); defparam nl1O11l.width_data = 4, nl1O11l.width_sel = 2; oper_mux nl1O11O ( .data({nl01lil, nl01iOi, nl01lii, nl01O1l}), .o(wire_nl1O11O_o), .sel({nlli0li, nlli0il})); defparam nl1O11O.width_data = 4, nl1O11O.width_sel = 2; oper_mux nl1O1ii ( .data({nl01l1l, nl01lli, nl01liO, nl01l1i}), .o(wire_nl1O1ii_o), .sel({nlli0li, nlli0il})); defparam nl1O1ii.width_data = 4, nl1O1ii.width_sel = 2; oper_mux nl1O1il ( .data({nl01l1i, nl01liO, nl01lli, nl01l1l}), .o(wire_nl1O1il_o), .sel({nlli0li, nlli0il})); defparam nl1O1il.width_data = 4, nl1O1il.width_sel = 2; oper_mux nl1O1iO ( .data({nl01iOO, nl01lil, nl01lll, nl01l1O}), .o(wire_nl1O1iO_o), .sel({nlli0li, nlli0il})); defparam nl1O1iO.width_data = 4, nl1O1iO.width_sel = 2; oper_mux nl1O1li ( .data({nl01iOl, nl01lii, nl01llO, nl01l0i}), .o(wire_nl1O1li_o), .sel({nlli0li, nlli0il})); defparam nl1O1li.width_data = 4, nl1O1li.width_sel = 2; oper_mux nl1O1ll ( .data({nl01iOi, nl01l0O, nl01lOi, nl01l0l}), .o(wire_nl1O1ll_o), .sel({nlli0li, nlli0il})); defparam nl1O1ll.width_data = 4, nl1O1ll.width_sel = 2; oper_mux nl1O1lO ( .data({nl01lOi, nl01l0l, nl01iOi, nl01l0O}), .o(wire_nl1O1lO_o), .sel({nlli0li, nlli0il})); defparam nl1O1lO.width_data = 4, nl1O1lO.width_sel = 2; oper_mux nl1O1Oi ( .data({nl01llO, nl01l0i, nl01iOl, nl01lii}), .o(wire_nl1O1Oi_o), .sel({nlli0li, nlli0il})); defparam nl1O1Oi.width_data = 4, nl1O1Oi.width_sel = 2; oper_mux nl1O1Ol ( .data({nl01lll, nl01l1O, nl01iOO, nl01lil}), .o(wire_nl1O1Ol_o), .sel({nlli0li, nlli0il})); defparam nl1O1Ol.width_data = 4, nl1O1Ol.width_sel = 2; oper_mux nl1O1OO ( .data({nl01lli, nl01l1l, nl01l1i, nl01liO}), .o(wire_nl1O1OO_o), .sel({nlli0li, nlli0il})); defparam nl1O1OO.width_data = 4, nl1O1OO.width_sel = 2; oper_mux nllO0iO ( .data({{3{1'b0}}, (~ n10lili), {4{1'b0}}, wire_nlO110O_dataout, wire_nlO1i1i_dataout, wire_nllOO0O_dataout, wire_nllOi0l_dataout, 1'b0, wire_nlO1l1l_dataout, {2{1'b0}}}), .o(wire_nllO0iO_o), .sel({nlO011O, nlO011l, nlO011i, nllll1i})); defparam nllO0iO.width_data = 16, nllO0iO.width_sel = 4; oper_mux nllO0li ( .data({{8{1'b0}}, n10l0Ol, wire_nlO1i1l_dataout, wire_nllOOii_dataout, wire_nllOi0O_dataout, {4{1'b0}}}), .o(wire_nllO0li_o), .sel({nlO011O, nlO011l, nlO011i, nllll1i})); defparam nllO0li.width_data = 16, nllO0li.width_sel = 4; oper_mux nllO0ll ( .data({{3{1'b0}}, wire_nllOi1l_dataout, {4{1'b0}}, wire_nlO11ii_dataout, n10li0l, wire_nllOOil_dataout, wire_nllOiii_dataout, 1'b0, wire_nlO1l1O_dataout, {2{1'b0}}}), .o(wire_nllO0ll_o), .sel({nlO011O, nlO011l, nlO011i, nllll1i})); defparam nllO0ll.width_data = 16, nllO0ll.width_sel = 4; oper_mux nllO0lO ( .data({{8{1'b0}}, wire_nlO11il_dataout, wire_nlO1i1O_dataout, n10li1i, wire_nllOiil_dataout, {4{1'b0}}}), .o(wire_nllO0lO_o), .sel({nlO011O, nlO011l, nlO011i, nllll1i})); defparam nllO0lO.width_data = 16, nllO0lO.width_sel = 4; oper_mux nllO0Oi ( .data({{12{1'b0}}, wire_nlO1l0l_dataout, 1'b0, wire_nlO1O1l_dataout, 1'b0}), .o(wire_nllO0Oi_o), .sel({nlO011O, nlO011l, nlO011i, nllll1i})); defparam nllO0Oi.width_data = 16, nllO0Oi.width_sel = 4; oper_mux nllO0Ol ( .data({{8{1'b0}}, wire_nlO11iO_dataout, wire_nlO1i0i_dataout, wire_nllOOiO_dataout, wire_nllOiiO_dataout, wire_nlO1l0O_dataout, n10liil, wire_nlO1O1O_dataout, wire_nlO1Oll_dataout}), .o(wire_nllO0Ol_o), .sel({nlO011O, nlO011l, nlO011i, nllll1i})); defparam nllO0Ol.width_data = 16, nllO0Ol.width_sel = 4; oper_mux nllO0OO ( .data({{12{1'b0}}, wire_nlO1lii_dataout, 1'b0, wire_nlO1O0i_dataout, wire_nlO1OlO_dataout}), .o(wire_nllO0OO_o), .sel({nlO011O, nlO011l, nlO011i, nllll1i})); defparam nllO0OO.width_data = 16, nllO0OO.width_sel = 4; oper_mux nllOi1i ( .data({{3{1'b1}}, wire_nllOi1O_dataout, {4{1'b1}}, wire_nlO11li_dataout, wire_nlO1i0l_dataout, 1'b0, wire_nllOili_dataout, n10ll0i, wire_nlO1l0i_dataout, n10ll1i, (~ niii0l)}), .o(wire_nllOi1i_o), .sel({nlO011O, nlO011l, nlO011i, nllll1i})); defparam nllOi1i.width_data = 16, nllOi1i.width_sel = 4; oper_mux nlO0O0i ( .data({wire_nlO0O0l_dataout, 1'b0, n1ii11l, 1'b0}), .o(wire_nlO0O0i_o), .sel({nlOiill, nlOiili})); defparam nlO0O0i.width_data = 4, nlO0O0i.width_sel = 2; oper_mux nlO0OiO ( .data({wire_nlO0Oli_dataout, 1'b0, n1i0Oii, 1'b0}), .o(wire_nlO0OiO_o), .sel({nlOiiiO, nlOiiil})); defparam nlO0OiO.width_data = 4, nlO0OiO.width_sel = 2; oper_mux nlO0OOl ( .data({wire_nlO0OOO_dataout, 1'b0, n1i0O1i, 1'b0}), .o(wire_nlO0OOl_o), .sel({nlOiiii, nlOii0O})); defparam nlO0OOl.width_data = 4, nlO0OOl.width_sel = 2; oper_mux nlOi00i ( .data({wire_nlOi00l_dataout, 1'b0, n1i0l0O, 1'b0}), .o(wire_nlOi00i_o), .sel({nlOi0Ol, nlOi0Oi})); defparam nlOi00i.width_data = 4, nlOi00i.width_sel = 2; oper_mux nlOi0iO ( .data({wire_nlOi0li_dataout, 1'b0, n1i0l0i, 1'b0}), .o(wire_nlOi0iO_o), .sel({nlOi0lO, nlOi0ll})); defparam nlOi0iO.width_data = 4, nlOi0iO.width_sel = 2; oper_mux nlOi10i ( .data({wire_nlOi10l_dataout, 1'b0, n1i0llO, 1'b0}), .o(wire_nlOi10i_o), .sel({nlOii0l, nlOii0i})); defparam nlOi10i.width_data = 4, nlOi10i.width_sel = 2; oper_mux nlOi1iO ( .data({wire_nlOi1li_dataout, 1'b0, n1i0lli, 1'b0}), .o(wire_nlOi1iO_o), .sel({nlOii1O, nlOii1l})); defparam nlOi1iO.width_data = 4, nlOi1iO.width_sel = 2; oper_mux nlOi1Ol ( .data({wire_nlOi1OO_dataout, 1'b0, n1i0lil, 1'b0}), .o(wire_nlOi1Ol_o), .sel({nlOii1i, nlOi0OO})); defparam nlOi1Ol.width_data = 4, nlOi1Ol.width_sel = 2; oper_selector n1lili ( .data({1'b0, n01i0i, n1liii, n0110l}), .o(wire_n1lili_o), .sel({n10O00i, n10O01i, n10O1Ol, n10O1OO})); defparam n1lili.width_data = 4, n1lili.width_sel = 4; oper_selector n1lill ( .data({1'b0, n01i0l, n1l00O, n0110O}), .o(wire_n1lill_o), .sel({n10O00i, n10O01i, n10O1Ol, n10O1OO})); defparam n1lill.width_data = 4, n1lill.width_sel = 4; oper_selector n1lilO ( .data({1'b0, n01i0O, n1l0ii, n011ii}), .o(wire_n1lilO_o), .sel({n10O00i, n10O01i, n10O1Ol, n10O1OO})); defparam n1lilO.width_data = 4, n1lilO.width_sel = 4; oper_selector n1liOi ( .data({1'b0, n01iii, n1l0il, n011il}), .o(wire_n1liOi_o), .sel({n10O00i, n10O01i, n10O1Ol, n10O1OO})); defparam n1liOi.width_data = 4, n1liOi.width_sel = 4; oper_selector n1liOO ( .data({1'b0, n010OO, wire_n1lOlO_dataout, n0111i, wire_n1lO1i_dataout}), .o(wire_n1liOO_o), .sel({n10O00i, n10O01i, n1O1Oi, n10O1OO, n1l0Oi})); defparam n1liOO.width_data = 5, n1liOO.width_sel = 5; oper_selector n1ll0O ( .data({1'b0, wire_n1lO0l_dataout}), .o(wire_n1ll0O_o), .sel({n10O01l, (~ n10O01l)})); defparam n1ll0O.width_data = 2, n1ll0O.width_sel = 2; oper_selector n1ll1i ( .data({1'b0, n01i1i, wire_n1lOOi_dataout, n0111l, wire_n1lO1l_dataout}), .o(wire_n1ll1i_o), .sel({n10O00i, n10O01i, n1O1Oi, n10O1OO, n1l0Oi})); defparam n1ll1i.width_data = 5, n1ll1i.width_sel = 5; oper_selector n1ll1l ( .data({1'b0, n01i1l, wire_n1lOOl_dataout, n0111O, wire_n1lO1O_dataout}), .o(wire_n1ll1l_o), .sel({n10O00i, n10O01i, n1O1Oi, n10O1OO, n1l0Oi})); defparam n1ll1l.width_data = 5, n1ll1l.width_sel = 5; oper_selector n1ll1O ( .data({1'b0, n01i1O, wire_n1lOOO_dataout, n0110i, wire_n1lO0i_dataout}), .o(wire_n1ll1O_o), .sel({n10O00i, n10O01i, n1O1Oi, n10O1OO, n1l0Oi})); defparam n1ll1O.width_data = 5, n1ll1O.width_sel = 5; oper_selector n1llil ( .data({1'b0, {3{wire_n1O11l_dataout}}, {3{wire_n1lO0O_dataout}}}), .o(wire_n1llil_o), .sel({n10O00i, n1O1OO, n1O1Ol, n1O1Oi, n1O1lO, n1O1ll, n1l0Oi})); defparam n1llil.width_data = 7, n1llil.width_sel = 7; oper_selector n1llli ( .data({1'b0, wire_n1O11O_dataout}), .o(wire_n1llli_o), .sel({n10O01O, (~ n10O01O)})); defparam n1llli.width_data = 2, n1llli.width_sel = 2; oper_selector n1lllO ( .data({1'b0, {3{wire_n1O10i_dataout}}, {3{wire_n1lOii_dataout}}}), .o(wire_n1lllO_o), .sel({n10O00i, n1O1OO, n1O1Ol, n1O1Oi, n1O1lO, n1O1ll, n1l0Oi})); defparam n1lllO.width_data = 7, n1lllO.width_sel = 7; oper_selector n1Oliii ( .data({1'b0, n0101Ol, n1Oli0i, n011liO}), .o(wire_n1Oliii_o), .sel({nlOOi1ii, nlOOi10i, nlOOi11l, nlOOi11O})); defparam n1Oliii.width_data = 4, n1Oliii.width_sel = 4; oper_selector n1Oliil ( .data({1'b0, n0101OO, n1Ol1Ol, n011lli}), .o(wire_n1Oliil_o), .sel({nlOOi1ii, nlOOi10i, nlOOi11l, nlOOi11O})); defparam n1Oliil.width_data = 4, n1Oliil.width_sel = 4; oper_selector n1OliiO ( .data({1'b0, n01001i, n1Ol1OO, n011lll}), .o(wire_n1OliiO_o), .sel({nlOOi1ii, nlOOi10i, nlOOi11l, nlOOi11O})); defparam n1OliiO.width_data = 4, n1OliiO.width_sel = 4; oper_selector n1Olili ( .data({1'b0, n01001l, n1Ol01i, n011llO}), .o(wire_n1Olili_o), .sel({nlOOi1ii, nlOOi10i, nlOOi11l, nlOOi11O})); defparam n1Olili.width_data = 4, n1Olili.width_sel = 4; oper_selector n1Olill ( .data({1'b0, n01001O, n1Ol01l, n011lOi}), .o(wire_n1Olill_o), .sel({nlOOi1ii, nlOOi10i, nlOOi11l, nlOOi11O})); defparam n1Olill.width_data = 4, n1Olill.width_sel = 4; oper_selector n1OliOi ( .data({1'b0, n0101iO, wire_n1OlOlO_dataout, n011l0i, wire_n1OllOO_dataout}), .o(wire_n1OliOi_o), .sel({nlOOi1ii, nlOOi10i, n1OO1Ol, nlOOi11O, n1Ol0il})); defparam n1OliOi.width_data = 5, n1OliOi.width_sel = 5; oper_selector n1OliOl ( .data({1'b0, n0101li, wire_n1OlOOi_dataout, n011l0l, wire_n1OlO1i_dataout}), .o(wire_n1OliOl_o), .sel({nlOOi1ii, nlOOi10i, n1OO1Ol, nlOOi11O, n1Ol0il})); defparam n1OliOl.width_data = 5, n1OliOl.width_sel = 5; oper_selector n1OliOO ( .data({1'b0, n0101ll, wire_n1OlOOl_dataout, n011l0O, wire_n1OlO1l_dataout}), .o(wire_n1OliOO_o), .sel({nlOOi1ii, nlOOi10i, n1OO1Ol, nlOOi11O, n1Ol0il})); defparam n1OliOO.width_data = 5, n1OliOO.width_sel = 5; oper_selector n1Oll0l ( .data({1'b0, wire_n1OlO0l_dataout}), .o(wire_n1Oll0l_o), .sel({nlOOi10l, (~ nlOOi10l)})); defparam n1Oll0l.width_data = 2, n1Oll0l.width_sel = 2; oper_selector n1Oll1i ( .data({1'b0, n0101lO, wire_n1OlOOO_dataout, n011lii, wire_n1OlO1O_dataout}), .o(wire_n1Oll1i_o), .sel({nlOOi1ii, nlOOi10i, n1OO1Ol, nlOOi11O, n1Ol0il})); defparam n1Oll1i.width_data = 5, n1Oll1i.width_sel = 5; oper_selector n1Oll1l ( .data({1'b0, n0101Oi, wire_n1OO11i_dataout, n011lil, wire_n1OlO0i_dataout}), .o(wire_n1Oll1l_o), .sel({nlOOi1ii, nlOOi10i, n1OO1Ol, nlOOi11O, n1Ol0il})); defparam n1Oll1l.width_data = 5, n1Oll1l.width_sel = 5; oper_selector n1Ollii ( .data({1'b0, {3{wire_n1OO11O_dataout}}, {3{wire_n1OlO0O_dataout}}}), .o(wire_n1Ollii_o), .sel({nlOOi1ii, n1OO01i, n1OO1OO, n1OO1Ol, n1OO1Oi, n1OO1lO, n1Ol0il})); defparam n1Ollii.width_data = 7, n1Ollii.width_sel = 7; oper_selector n1OlliO ( .data({1'b0, wire_n1OO10i_dataout}), .o(wire_n1OlliO_o), .sel({nlOOi10O, (~ nlOOi10O)})); defparam n1OlliO.width_data = 2, n1OlliO.width_sel = 2; oper_selector n1Ollll ( .data({1'b0, {3{wire_n1OO10l_dataout}}, {3{wire_n1OlOii_dataout}}}), .o(wire_n1Ollll_o), .sel({nlOOi1ii, n1OO01i, n1OO1OO, n1OO1Ol, n1OO1Oi, n1OO1lO, n1Ol0il})); defparam n1Ollll.width_data = 7, n1Ollll.width_sel = 7; oper_selector niO00i ( .data({wire_niilOi_dataout, wire_niil0l_dataout, wire_niOl1i_o}), .o(wire_niO00i_o), .sel({n1i01li, n1i01iO, (~ n1i01il)})); defparam niO00i.width_data = 3, niO00i.width_sel = 3; oper_selector niO00l ( .data({wire_niilOl_dataout, wire_niil0O_dataout, wire_niOl1l_o}), .o(wire_niO00l_o), .sel({n1i01li, n1i01iO, (~ n1i01il)})); defparam niO00l.width_data = 3, niO00l.width_sel = 3; oper_selector niO00O ( .data({wire_niilOO_dataout, wire_niilii_dataout, wire_niOl1O_o}), .o(wire_niO00O_o), .sel({n1i01li, n1i01iO, (~ n1i01il)})); defparam niO00O.width_data = 3, niO00O.width_sel = 3; oper_selector niO01i ( .data({wire_niilli_dataout, wire_niil1l_dataout, wire_niOiOi_o}), .o(wire_niO01i_o), .sel({n1i01li, n1i01iO, (~ n1i01il)})); defparam niO01i.width_data = 3, niO01i.width_sel = 3; oper_selector niO01l ( .data({wire_niilll_dataout, wire_niil1O_dataout, wire_niOiOl_o}), .o(wire_niO01l_o), .sel({n1i01li, n1i01iO, (~ n1i01il)})); defparam niO01l.width_data = 3, niO01l.width_sel = 3; oper_selector niO01O ( .data({wire_niillO_dataout, wire_niil0i_dataout, wire_niOiOO_o}), .o(wire_niO01O_o), .sel({n1i01li, n1i01iO, (~ n1i01il)})); defparam niO01O.width_data = 3, niO01O.width_sel = 3; oper_selector niO1Ol ( .data({wire_niilil_dataout, wire_niiiOO_dataout, wire_niOill_o}), .o(wire_niO1Ol_o), .sel({n1i01li, n1i01iO, (~ n1i01il)})); defparam niO1Ol.width_data = 3, niO1Ol.width_sel = 3; oper_selector niO1OO ( .data({wire_niiliO_dataout, wire_niil1i_dataout, wire_niOilO_o}), .o(wire_niO1OO_o), .sel({n1i01li, n1i01iO, (~ n1i01il)})); defparam niO1OO.width_data = 3, niO1OO.width_sel = 3; oper_selector niOill ( .data({nl110O, nl11il, niOO0i}), .o(wire_niOill_o), .sel({n1i00Ol, n1i00Oi, (~ n1i00lO)})); defparam niOill.width_data = 3, niOill.width_sel = 3; oper_selector niOilO ( .data({nl110l, nl11ii, niOOOO}), .o(wire_niOilO_o), .sel({n1i00Ol, n1i00Oi, (~ n1i00lO)})); defparam niOilO.width_data = 3, niOilO.width_sel = 3; oper_selector niOiOi ( .data({nl110i, nl110O, nl111i}), .o(wire_niOiOi_o), .sel({n1i00Ol, n1i00Oi, (~ n1i00lO)})); defparam niOiOi.width_data = 3, niOiOi.width_sel = 3; oper_selector niOiOl ( .data({nl111O, nl110l, nl111l}), .o(wire_niOiOl_o), .sel({n1i00Ol, n1i00Oi, (~ n1i00lO)})); defparam niOiOl.width_data = 3, niOiOl.width_sel = 3; oper_selector niOiOO ( .data({nl111l, nl110i, nl111O}), .o(wire_niOiOO_o), .sel({n1i00Ol, n1i00Oi, (~ n1i00lO)})); defparam niOiOO.width_data = 3, niOiOO.width_sel = 3; oper_selector niOl1i ( .data({nl111i, nl111O, nl110i}), .o(wire_niOl1i_o), .sel({n1i00Ol, n1i00Oi, (~ n1i00lO)})); defparam niOl1i.width_data = 3, niOl1i.width_sel = 3; oper_selector niOl1l ( .data({niOOOO, nl111l, nl110l}), .o(wire_niOl1l_o), .sel({n1i00Ol, n1i00Oi, (~ n1i00lO)})); defparam niOl1l.width_data = 3, niOl1l.width_sel = 3; oper_selector niOl1O ( .data({niOO0i, nl111i, nl110O}), .o(wire_niOl1O_o), .sel({n1i00Ol, n1i00Oi, (~ n1i00lO)})); defparam niOl1O.width_data = 3, niOl1O.width_sel = 3; oper_selector nll1llO ( .data({n10l1il, wire_nll1O1O_dataout, 1'b0}), .o(wire_nll1llO_o), .sel({n10l11O, n10l11l, (~ n10l11i)})); defparam nll1llO.width_data = 3, nll1llO.width_sel = 3; oper_selector nll1lOO ( .data({(~ n10l1li), wire_nll1O0l_dataout, 1'b1}), .o(wire_nll1lOO_o), .sel({n10l11O, n10l11l, (~ n10l11i)})); defparam nll1lOO.width_data = 3, nll1lOO.width_sel = 3; oper_selector nll1O1i ( .data({n10l1li, wire_nll1O0i_dataout, 1'b0}), .o(wire_nll1O1i_o), .sel({n10l11O, n10l11l, (~ n10l11i)})); defparam nll1O1i.width_data = 3, nll1O1i.width_sel = 3; oper_selector nlll0i ( .data({wire_nlllli_dataout, wire_nlllii_dataout, (~ nlO0l1l)}), .o(wire_nlll0i_o), .sel({((n1ii1li26 ^ n1ii1li25) & nllO1l), ((n1ii1ll24 ^ n1ii1ll23) & nlllOO), nlllOl})); defparam nlll0i.width_data = 3, nlll0i.width_sel = 3; oper_selector nlll1i ( .data({wire_nlllil_dataout, wire_nlll0l_dataout, 1'b0}), .o(wire_nlll1i_o), .sel({nllO1l, ((n1ii1ii32 ^ n1ii1ii31) & nlllOO), ((n1ii1il30 ^ n1ii1il29) & nlllOl)})); defparam nlll1i.width_data = 3, nlll1i.width_sel = 3; oper_selector nlll1l ( .data({wire_nllliO_dataout, n1ii1lO, nlO0l1l}), .o(wire_nlll1l_o), .sel({nllO1l, nlllOO, nlllOl})); defparam nlll1l.width_data = 3, nlll1l.width_sel = 3; oper_selector nlll1O ( .data({n1ii00i, ((n1ii1iO28 ^ n1ii1iO27) & wire_nlll0O_dataout), 1'b0}), .o(wire_nlll1O_o), .sel({nllO1l, nlllOO, nlllOl})); defparam nlll1O.width_data = 3, nlll1O.width_sel = 3; oper_selector nllll0i ( .data({nlO01Ol, gnumber[2], 1'b0, wire_nllO1Oi_o[2]}), .o(wire_nllll0i_o), .sel({n10l1Oi, wire_nllO00O_dataout, n10l1lO, wire_nllO01l_dataout})); defparam nllll0i.width_data = 4, nllll0i.width_sel = 4; oper_selector nllll0l ( .data({nlO01OO, gnumber[3], 1'b0, wire_nllO1Oi_o[3]}), .o(wire_nllll0l_o), .sel({n10l1Oi, wire_nllO00O_dataout, n10l1lO, wire_nllO01l_dataout})); defparam nllll0l.width_data = 4, nllll0l.width_sel = 4; oper_selector nllll0O ( .data({nlO001i, gnumber[4], 1'b0, wire_nllO1Oi_o[4]}), .o(wire_nllll0O_o), .sel({n10l1Oi, wire_nllO00O_dataout, n10l1lO, wire_nllO01l_dataout})); defparam nllll0O.width_data = 4, nllll0O.width_sel = 4; oper_selector nllll1l ( .data({nlO01lO, gnumber[0], 1'b0, wire_nllO1Oi_o[0]}), .o(wire_nllll1l_o), .sel({n10l1Oi, wire_nllO00O_dataout, n10l1lO, wire_nllO01l_dataout})); defparam nllll1l.width_data = 4, nllll1l.width_sel = 4; oper_selector nllll1O ( .data({nlO01Oi, gnumber[1], 1'b0, wire_nllO1Oi_o[1]}), .o(wire_nllll1O_o), .sel({n10l1Oi, wire_nllO00O_dataout, n10l1lO, wire_nllO01l_dataout})); defparam nllll1O.width_data = 4, nllll1O.width_sel = 4; oper_selector nllllii ( .data({nlO001l, gnumber[5], 1'b0, wire_nllO1Oi_o[5]}), .o(wire_nllllii_o), .sel({n10l1Oi, wire_nllO00O_dataout, n10l1lO, wire_nllO01l_dataout})); defparam nllllii.width_data = 4, nllllii.width_sel = 4; oper_selector nllllil ( .data({nlO001O, gnumber[6], 1'b0, wire_nllO1Oi_o[6]}), .o(wire_nllllil_o), .sel({n10l1Oi, wire_nllO00O_dataout, n10l1lO, wire_nllO01l_dataout})); defparam nllllil.width_data = 4, nllllil.width_sel = 4; oper_selector nlllliO ( .data({nlO000i, gnumber[7], 1'b0, wire_nllO1Oi_o[7]}), .o(wire_nlllliO_o), .sel({n10l1Oi, wire_nllO00O_dataout, n10l1lO, wire_nllO01l_dataout})); defparam nlllliO.width_data = 4, nlllliO.width_sel = 4; oper_selector nllllli ( .data({nlO000l, gnumber[8], 1'b0, wire_nllO1Oi_o[8]}), .o(wire_nllllli_o), .sel({n10l1Oi, wire_nllO00O_dataout, n10l1lO, wire_nllO01l_dataout})); defparam nllllli.width_data = 4, nllllli.width_sel = 4; oper_selector nllllll ( .data({nlO000O, gnumber[9], 1'b0, wire_nllO1Oi_o[9]}), .o(wire_nllllll_o), .sel({n10l1Oi, wire_nllO00O_dataout, n10l1lO, wire_nllO01l_dataout})); defparam nllllll.width_data = 4, nllllll.width_sel = 4; oper_selector nllllOl ( .data({nlO00ii, 1'b0, wire_nllO1Ol_o[0], wire_nllO1lO_o[1]}), .o(wire_nllllOl_o), .sel({n10l1Ol, wire_nllO00O_dataout, wire_nllO01O_dataout, wire_nllO00i_dataout})); defparam nllllOl.width_data = 4, nllllOl.width_sel = 4; oper_selector nllllOO ( .data({nlO00il, 1'b0, wire_nllO1Ol_o[1], wire_nllO1lO_o[2]}), .o(wire_nllllOO_o), .sel({n10l1Ol, wire_nllO00O_dataout, wire_nllO01O_dataout, wire_nllO00i_dataout})); defparam nllllOO.width_data = 4, nllllOO.width_sel = 4; oper_selector nlllO0i ( .data({nlO00lO, 1'b0, wire_nllO1Ol_o[5], wire_nllO1lO_o[6]}), .o(wire_nlllO0i_o), .sel({n10l1Ol, wire_nllO00O_dataout, wire_nllO01O_dataout, wire_nllO00i_dataout})); defparam nlllO0i.width_data = 4, nlllO0i.width_sel = 4; oper_selector nlllO0l ( .data({nlO00Oi, 1'b0, wire_nllO1Ol_o[6], wire_nllO1lO_o[7]}), .o(wire_nlllO0l_o), .sel({n10l1Ol, wire_nllO00O_dataout, wire_nllO01O_dataout, wire_nllO00i_dataout})); defparam nlllO0l.width_data = 4, nlllO0l.width_sel = 4; oper_selector nlllO0O ( .data({nlO00Ol, 1'b0, wire_nllO1Ol_o[7], wire_nllO1lO_o[8]}), .o(wire_nlllO0O_o), .sel({n10l1Ol, wire_nllO00O_dataout, wire_nllO01O_dataout, wire_nllO00i_dataout})); defparam nlllO0O.width_data = 4, nlllO0O.width_sel = 4; oper_selector nlllO1i ( .data({nlO00iO, 1'b0, wire_nllO1Ol_o[2], wire_nllO1lO_o[3]}), .o(wire_nlllO1i_o), .sel({n10l1Ol, wire_nllO00O_dataout, wire_nllO01O_dataout, wire_nllO00i_dataout})); defparam nlllO1i.width_data = 4, nlllO1i.width_sel = 4; oper_selector nlllO1l ( .data({nlO00li, 1'b0, wire_nllO1Ol_o[3], wire_nllO1lO_o[4]}), .o(wire_nlllO1l_o), .sel({n10l1Ol, wire_nllO00O_dataout, wire_nllO01O_dataout, wire_nllO00i_dataout})); defparam nlllO1l.width_data = 4, nlllO1l.width_sel = 4; oper_selector nlllO1O ( .data({nlO00ll, 1'b0, wire_nllO1Ol_o[4], wire_nllO1lO_o[5]}), .o(wire_nlllO1O_o), .sel({n10l1Ol, wire_nllO00O_dataout, wire_nllO01O_dataout, wire_nllO00i_dataout})); defparam nlllO1O.width_data = 4, nlllO1O.width_sel = 4; oper_selector nlllOii ( .data({nlO00OO, 1'b0, wire_nllO1Ol_o[8], wire_nllO1lO_o[9]}), .o(wire_nlllOii_o), .sel({n10l1Ol, wire_nllO00O_dataout, wire_nllO01O_dataout, wire_nllO00i_dataout})); defparam nlllOii.width_data = 4, nlllOii.width_sel = 4; oper_selector nlllOil ( .data({nlO0i1i, 1'b0, wire_nllO1Ol_o[9], wire_nllO1lO_o[10]}), .o(wire_nlllOil_o), .sel({n10l1Ol, wire_nllO00O_dataout, wire_nllO01O_dataout, wire_nllO00i_dataout})); defparam nlllOil.width_data = 4, nlllOil.width_sel = 4; oper_selector nlllOli ( .data({1'b1, 1'b0, nlO010O}), .o(wire_nlllOli_o), .sel({wire_nllO0il_dataout, (wire_nllO0ii_dataout | wire_nllO00O_dataout), (((wire_nllO00i_dataout | wire_nllO01O_dataout) | wire_nllO01l_dataout) | (~ n10l01l))})); defparam nlllOli.width_data = 3, nlllOli.width_sel = 3; oper_selector nlllOOi ( .data({1'b0, wire_nllO1OO_o[0], nlO0i1l}), .o(wire_nlllOOi_o), .sel({wire_nllO0il_dataout, wire_nllO0ii_dataout, n10l1OO})); defparam nlllOOi.width_data = 3, nlllOOi.width_sel = 3; oper_selector nlllOOl ( .data({1'b0, wire_nllO1OO_o[1], nlO0i1O}), .o(wire_nlllOOl_o), .sel({wire_nllO0il_dataout, wire_nllO0ii_dataout, n10l1OO})); defparam nlllOOl.width_data = 3, nlllOOl.width_sel = 3; oper_selector nlllOOO ( .data({1'b0, wire_nllO1OO_o[2], nlO0i0i}), .o(wire_nlllOOO_o), .sel({wire_nllO0il_dataout, wire_nllO0ii_dataout, n10l1OO})); defparam nlllOOO.width_data = 3, nlllOOO.width_sel = 3; oper_selector nllO10i ( .data({1'b0, wire_nllO1OO_o[6], nlO0iil}), .o(wire_nllO10i_o), .sel({wire_nllO0il_dataout, wire_nllO0ii_dataout, n10l1OO})); defparam nllO10i.width_data = 3, nllO10i.width_sel = 3; oper_selector nllO10l ( .data({1'b0, wire_nllO1OO_o[7], nlO0iiO}), .o(wire_nllO10l_o), .sel({wire_nllO0il_dataout, wire_nllO0ii_dataout, n10l1OO})); defparam nllO10l.width_data = 3, nllO10l.width_sel = 3; oper_selector nllO10O ( .data({1'b0, wire_nllO1OO_o[8], nlO0ili}), .o(wire_nllO10O_o), .sel({wire_nllO0il_dataout, wire_nllO0ii_dataout, n10l1OO})); defparam nllO10O.width_data = 3, nllO10O.width_sel = 3; oper_selector nllO11i ( .data({1'b0, wire_nllO1OO_o[3], nlO0i0l}), .o(wire_nllO11i_o), .sel({wire_nllO0il_dataout, wire_nllO0ii_dataout, n10l1OO})); defparam nllO11i.width_data = 3, nllO11i.width_sel = 3; oper_selector nllO11l ( .data({1'b0, wire_nllO1OO_o[4], nlO0i0O}), .o(wire_nllO11l_o), .sel({wire_nllO0il_dataout, wire_nllO0ii_dataout, n10l1OO})); defparam nllO11l.width_data = 3, nllO11l.width_sel = 3; oper_selector nllO11O ( .data({1'b0, wire_nllO1OO_o[5], nlO0iii}), .o(wire_nllO11O_o), .sel({wire_nllO0il_dataout, wire_nllO0ii_dataout, n10l1OO})); defparam nllO11O.width_data = 3, nllO11O.width_sel = 3; oper_selector nllO1ii ( .data({1'b0, wire_nllO1OO_o[9], nlO0ill}), .o(wire_nllO1ii_o), .sel({wire_nllO0il_dataout, wire_nllO0ii_dataout, n10l1OO})); defparam nllO1ii.width_data = 3, nllO1ii.width_sel = 3; oper_selector nllO1iO ( .data({1'b0, nlO01ii, 1'b1}), .o(wire_nllO1iO_o), .sel({wire_nllO0il_dataout, n10l01i, wire_nllO00O_dataout})); defparam nllO1iO.width_data = 3, nllO1iO.width_sel = 3; assign a1a2_k1k2_flag = {wire_niiiO_dataout, wire_niiil_dataout, wire_niiii_dataout, wire_nii0O_dataout}, adata = {wire_niOili_dataout, wire_niOiiO_dataout, wire_niOiil_dataout, wire_niOiii_dataout, wire_niOi0O_dataout, wire_niOi0l_dataout, wire_niOi0i_dataout, wire_niOi1O_dataout, wire_niOi1l_dataout, wire_niOi1i_dataout}, adata_valid = nlO01ii, cg_syncpat = {wire_nlOi_dataout, wire_nllO_dataout}, kchar = niiill, kcount = {nlO0ill, nlO0ili, nlO0iiO, nlO0iil, nlO0iii, nlO0i0O, nlO0i0l, nlO0i0i, nlO0i1O, nlO0i1l}, n10000i = ((((((((((~ ((~ comp_pat[10]) ^ nll0l1O)) & (~ ((~ comp_pat[11]) ^ nll0l0i))) & (~ ((~ comp_pat[12]) ^ nll0l0l))) & (~ ((~ comp_pat[13]) ^ nll0l0O))) & (~ ((~ comp_pat[14]) ^ nll0lii))) & (~ ((~ comp_pat[15]) ^ nll0lil))) & (~ ((~ comp_pat[16]) ^ nll0liO))) & (~ ((~ comp_pat[17]) ^ nll0lli))) & (~ ((~ comp_pat[18]) ^ nll0lll))) & (~ ((~ comp_pat[19]) ^ nll0llO))), n10000l = (n10i10O & ((comp_pat_porn & n1000ii) | n10000O)), n10000O = ((((((((((~ (comp_pat[10] ^ nll0l1l)) & (~ (comp_pat[11] ^ nll0l1O))) & (~ (comp_pat[12] ^ nll0l0i))) & (~ (comp_pat[13] ^ nll0l0l))) & (~ (comp_pat[14] ^ nll0l0O))) & (~ (comp_pat[15] ^ nll0lii))) & (~ (comp_pat[16] ^ nll0lil))) & (~ (comp_pat[17] ^ nll0liO))) & (~ (comp_pat[18] ^ nll0lli))) & (~ (comp_pat[19] ^ nll0lll))), n10001i = ((((((((((~ ((~ comp_pat[10]) ^ nll0l0i)) & (~ ((~ comp_pat[11]) ^ nll0l0l))) & (~ ((~ comp_pat[12]) ^ nll0l0O))) & (~ ((~ comp_pat[13]) ^ nll0lii))) & (~ ((~ comp_pat[14]) ^ nll0lil))) & (~ ((~ comp_pat[15]) ^ nll0liO))) & (~ ((~ comp_pat[16]) ^ nll0lli))) & (~ ((~ comp_pat[17]) ^ nll0lll))) & (~ ((~ comp_pat[18]) ^ nll0llO))) & (~ ((~ comp_pat[19]) ^ nll0lOi))), n10001l = (n10i11O & ((comp_pat_porn & n10000i) | n10001O)), n10001O = ((((((((((~ (comp_pat[10] ^ nll0l1O)) & (~ (comp_pat[11] ^ nll0l0i))) & (~ (comp_pat[12] ^ nll0l0l))) & (~ (comp_pat[13] ^ nll0l0O))) & (~ (comp_pat[14] ^ nll0lii))) & (~ (comp_pat[15] ^ nll0lil))) & (~ (comp_pat[16] ^ nll0liO))) & (~ (comp_pat[17] ^ nll0lli))) & (~ (comp_pat[18] ^ nll0lll))) & (~ (comp_pat[19] ^ nll0llO))), n1000ii = ((((((((((~ ((~ comp_pat[10]) ^ nll0l1l)) & (~ ((~ comp_pat[11]) ^ nll0l1O))) & (~ ((~ comp_pat[12]) ^ nll0l0i))) & (~ ((~ comp_pat[13]) ^ nll0l0l))) & (~ ((~ comp_pat[14]) ^ nll0l0O))) & (~ ((~ comp_pat[15]) ^ nll0lii))) & (~ ((~ comp_pat[16]) ^ nll0lil))) & (~ ((~ comp_pat[17]) ^ nll0liO))) & (~ ((~ comp_pat[18]) ^ nll0lli))) & (~ ((~ comp_pat[19]) ^ nll0lll))), n1000il = (n10i1iO & ((comp_pat_porn & n1000li) | n1000iO)), n1000iO = ((((((((((~ (comp_pat[10] ^ nll0l1i)) & (~ (comp_pat[11] ^ nll0l1l))) & (~ (comp_pat[12] ^ nll0l1O))) & (~ (comp_pat[13] ^ nll0l0i))) & (~ (comp_pat[14] ^ nll0l0l))) & (~ (comp_pat[15] ^ nll0l0O))) & (~ (comp_pat[16] ^ nll0lii))) & (~ (comp_pat[17] ^ nll0lil))) & (~ (comp_pat[18] ^ nll0liO))) & (~ (comp_pat[19] ^ nll0lli))), n1000li = ((((((((((~ ((~ comp_pat[10]) ^ nll0l1i)) & (~ ((~ comp_pat[11]) ^ nll0l1l))) & (~ ((~ comp_pat[12]) ^ nll0l1O))) & (~ ((~ comp_pat[13]) ^ nll0l0i))) & (~ ((~ comp_pat[14]) ^ nll0l0l))) & (~ ((~ comp_pat[15]) ^ nll0l0O))) & (~ ((~ comp_pat[16]) ^ nll0lii))) & (~ ((~ comp_pat[17]) ^ nll0lil))) & (~ ((~ comp_pat[18]) ^ nll0liO))) & (~ ((~ comp_pat[19]) ^ nll0lli))), n1000ll = (n10i1lO & ((comp_pat_porn & n1000Oi) | n1000lO)), n1000lO = ((((((((((~ (comp_pat[10] ^ nll0iOO)) & (~ (comp_pat[11] ^ nll0l1i))) & (~ (comp_pat[12] ^ nll0l1l))) & (~ (comp_pat[13] ^ nll0l1O))) & (~ (comp_pat[14] ^ nll0l0i))) & (~ (comp_pat[15] ^ nll0l0l))) & (~ (comp_pat[16] ^ nll0l0O))) & (~ (comp_pat[17] ^ nll0lii))) & (~ (comp_pat[18] ^ nll0lil))) & (~ (comp_pat[19] ^ nll0liO))), n1000Oi = ((((((((((~ ((~ comp_pat[10]) ^ nll0iOO)) & (~ ((~ comp_pat[11]) ^ nll0l1i))) & (~ ((~ comp_pat[12]) ^ nll0l1l))) & (~ ((~ comp_pat[13]) ^ nll0l1O))) & (~ ((~ comp_pat[14]) ^ nll0l0i))) & (~ ((~ comp_pat[15]) ^ nll0l0l))) & (~ ((~ comp_pat[16]) ^ nll0l0O))) & (~ ((~ comp_pat[17]) ^ nll0lii))) & (~ ((~ comp_pat[18]) ^ nll0lil))) & (~ ((~ comp_pat[19]) ^ nll0liO))), n1000Ol = (((((((((((((((((((n10i1lO | n10i1iO) | n10i10O) | n10i11O) | n100OOO) | n100OlO) | n100OiO) | n100O0O) | n100O1O) | n100lOO) | n100llO) | n100liO) | n100l0O) | n100l1O) | n100iOO) | n100ilO) | n100iiO) | n100i0O) | n100i1O) | n1000OO), n1000OO = ((comp_pat_porn & n100i1l) | n100i1i), n10010i = ((((((((((~ ((~ comp_pat[10]) ^ nll0lil)) & (~ ((~ comp_pat[11]) ^ nll0liO))) & (~ ((~ comp_pat[12]) ^ nll0lli))) & (~ ((~ comp_pat[13]) ^ nll0lll))) & (~ ((~ comp_pat[14]) ^ nll0llO))) & (~ ((~ comp_pat[15]) ^ nll0lOi))) & (~ ((~ comp_pat[16]) ^ nll0lOl))) & (~ ((~ comp_pat[17]) ^ nll0lOO))) & (~ ((~ comp_pat[18]) ^ nll0O1i))) & (~ ((~ comp_pat[19]) ^ nll0O1l))), n10010l = (n100O0O & ((comp_pat_porn & n1001ii) | n10010O)), n10010O = ((((((((((~ (comp_pat[10] ^ nll0lii)) & (~ (comp_pat[11] ^ nll0lil))) & (~ (comp_pat[12] ^ nll0liO))) & (~ (comp_pat[13] ^ nll0lli))) & (~ (comp_pat[14] ^ nll0lll))) & (~ (comp_pat[15] ^ nll0llO))) & (~ (comp_pat[16] ^ nll0lOi))) & (~ (comp_pat[17] ^ nll0lOl))) & (~ (comp_pat[18] ^ nll0lOO))) & (~ (comp_pat[19] ^ nll0O1i))), n10011i = ((((((((((~ ((~ comp_pat[10]) ^ nll0liO)) & (~ ((~ comp_pat[11]) ^ nll0lli))) & (~ ((~ comp_pat[12]) ^ nll0lll))) & (~ ((~ comp_pat[13]) ^ nll0llO))) & (~ ((~ comp_pat[14]) ^ nll0lOi))) & (~ ((~ comp_pat[15]) ^ nll0lOl))) & (~ ((~ comp_pat[16]) ^ nll0lOO))) & (~ ((~ comp_pat[17]) ^ nll0O1i))) & (~ ((~ comp_pat[18]) ^ nll0O1l))) & (~ ((~ comp_pat[19]) ^ nll0O1O))), n10011l = (n100O1O & ((comp_pat_porn & n10010i) | n10011O)), n10011O = ((((((((((~ (comp_pat[10] ^ nll0lil)) & (~ (comp_pat[11] ^ nll0liO))) & (~ (comp_pat[12] ^ nll0lli))) & (~ (comp_pat[13] ^ nll0lll))) & (~ (comp_pat[14] ^ nll0llO))) & (~ (comp_pat[15] ^ nll0lOi))) & (~ (comp_pat[16] ^ nll0lOl))) & (~ (comp_pat[17] ^ nll0lOO))) & (~ (comp_pat[18] ^ nll0O1i))) & (~ (comp_pat[19] ^ nll0O1l))), n1001ii = ((((((((((~ ((~ comp_pat[10]) ^ nll0lii)) & (~ ((~ comp_pat[11]) ^ nll0lil))) & (~ ((~ comp_pat[12]) ^ nll0liO))) & (~ ((~ comp_pat[13]) ^ nll0lli))) & (~ ((~ comp_pat[14]) ^ nll0lll))) & (~ ((~ comp_pat[15]) ^ nll0llO))) & (~ ((~ comp_pat[16]) ^ nll0lOi))) & (~ ((~ comp_pat[17]) ^ nll0lOl))) & (~ ((~ comp_pat[18]) ^ nll0lOO))) & (~ ((~ comp_pat[19]) ^ nll0O1i))), n1001il = (n100OiO & ((comp_pat_porn & n1001li) | n1001iO)), n1001iO = ((((((((((~ (comp_pat[10] ^ nll0l0O)) & (~ (comp_pat[11] ^ nll0lii))) & (~ (comp_pat[12] ^ nll0lil))) & (~ (comp_pat[13] ^ nll0liO))) & (~ (comp_pat[14] ^ nll0lli))) & (~ (comp_pat[15] ^ nll0lll))) & (~ (comp_pat[16] ^ nll0llO))) & (~ (comp_pat[17] ^ nll0lOi))) & (~ (comp_pat[18] ^ nll0lOl))) & (~ (comp_pat[19] ^ nll0lOO))), n1001li = ((((((((((~ ((~ comp_pat[10]) ^ nll0l0O)) & (~ ((~ comp_pat[11]) ^ nll0lii))) & (~ ((~ comp_pat[12]) ^ nll0lil))) & (~ ((~ comp_pat[13]) ^ nll0liO))) & (~ ((~ comp_pat[14]) ^ nll0lli))) & (~ ((~ comp_pat[15]) ^ nll0lll))) & (~ ((~ comp_pat[16]) ^ nll0llO))) & (~ ((~ comp_pat[17]) ^ nll0lOi))) & (~ ((~ comp_pat[18]) ^ nll0lOl))) & (~ ((~ comp_pat[19]) ^ nll0lOO))), n1001ll = (n100OlO & ((comp_pat_porn & n1001Oi) | n1001lO)), n1001lO = ((((((((((~ (comp_pat[10] ^ nll0l0l)) & (~ (comp_pat[11] ^ nll0l0O))) & (~ (comp_pat[12] ^ nll0lii))) & (~ (comp_pat[13] ^ nll0lil))) & (~ (comp_pat[14] ^ nll0liO))) & (~ (comp_pat[15] ^ nll0lli))) & (~ (comp_pat[16] ^ nll0lll))) & (~ (comp_pat[17] ^ nll0llO))) & (~ (comp_pat[18] ^ nll0lOi))) & (~ (comp_pat[19] ^ nll0lOl))), n1001Oi = ((((((((((~ ((~ comp_pat[10]) ^ nll0l0l)) & (~ ((~ comp_pat[11]) ^ nll0l0O))) & (~ ((~ comp_pat[12]) ^ nll0lii))) & (~ ((~ comp_pat[13]) ^ nll0lil))) & (~ ((~ comp_pat[14]) ^ nll0liO))) & (~ ((~ comp_pat[15]) ^ nll0lli))) & (~ ((~ comp_pat[16]) ^ nll0lll))) & (~ ((~ comp_pat[17]) ^ nll0llO))) & (~ ((~ comp_pat[18]) ^ nll0lOi))) & (~ ((~ comp_pat[19]) ^ nll0lOl))), n1001Ol = (n100OOO & ((comp_pat_porn & n10001i) | n1001OO)), n1001OO = ((((((((((~ (comp_pat[10] ^ nll0l0i)) & (~ (comp_pat[11] ^ nll0l0l))) & (~ (comp_pat[12] ^ nll0l0O))) & (~ (comp_pat[13] ^ nll0lii))) & (~ (comp_pat[14] ^ nll0lil))) & (~ (comp_pat[15] ^ nll0liO))) & (~ (comp_pat[16] ^ nll0lli))) & (~ (comp_pat[17] ^ nll0lll))) & (~ (comp_pat[18] ^ nll0llO))) & (~ (comp_pat[19] ^ nll0lOi))), n100i0i = ((((((((((~ (comp_pat[0] ^ nll0lil)) & (~ (comp_pat[1] ^ nll0liO))) & (~ (comp_pat[2] ^ nll0lli))) & (~ (comp_pat[3] ^ nll0lll))) & (~ (comp_pat[4] ^ nll0llO))) & (~ (comp_pat[5] ^ nll0lOi))) & (~ (comp_pat[6] ^ nll0lOl))) & (~ (comp_pat[7] ^ nll0lOO))) & (~ (comp_pat[8] ^ nll0O1i))) & (~ (comp_pat[9] ^ nll0O1l))), n100i0l = ((((((((((~ ((~ comp_pat[0]) ^ nll0lil)) & (~ ((~ comp_pat[1]) ^ nll0liO))) & (~ ((~ comp_pat[2]) ^ nll0lli))) & (~ ((~ comp_pat[3]) ^ nll0lll))) & (~ ((~ comp_pat[4]) ^ nll0llO))) & (~ ((~ comp_pat[5]) ^ nll0lOi))) & (~ ((~ comp_pat[6]) ^ nll0lOl))) & (~ ((~ comp_pat[7]) ^ nll0lOO))) & (~ ((~ comp_pat[8]) ^ nll0O1i))) & (~ ((~ comp_pat[9]) ^ nll0O1l))), n100i0O = ((comp_pat_porn & n100iil) | n100iii), n100i1i = ((((((((((~ (comp_pat[0] ^ nll0liO)) & (~ (comp_pat[1] ^ nll0lli))) & (~ (comp_pat[2] ^ nll0lll))) & (~ (comp_pat[3] ^ nll0llO))) & (~ (comp_pat[4] ^ nll0lOi))) & (~ (comp_pat[5] ^ nll0lOl))) & (~ (comp_pat[6] ^ nll0lOO))) & (~ (comp_pat[7] ^ nll0O1i))) & (~ (comp_pat[8] ^ nll0O1l))) & (~ (comp_pat[9] ^ nll0O1O))), n100i1l = ((((((((((~ ((~ comp_pat[0]) ^ nll0liO)) & (~ ((~ comp_pat[1]) ^ nll0lli))) & (~ ((~ comp_pat[2]) ^ nll0lll))) & (~ ((~ comp_pat[3]) ^ nll0llO))) & (~ ((~ comp_pat[4]) ^ nll0lOi))) & (~ ((~ comp_pat[5]) ^ nll0lOl))) & (~ ((~ comp_pat[6]) ^ nll0lOO))) & (~ ((~ comp_pat[7]) ^ nll0O1i))) & (~ ((~ comp_pat[8]) ^ nll0O1l))) & (~ ((~ comp_pat[9]) ^ nll0O1O))), n100i1O = ((comp_pat_porn & n100i0l) | n100i0i), n100iii = ((((((((((~ (comp_pat[0] ^ nll0lii)) & (~ (comp_pat[1] ^ nll0lil))) & (~ (comp_pat[2] ^ nll0liO))) & (~ (comp_pat[3] ^ nll0lli))) & (~ (comp_pat[4] ^ nll0lll))) & (~ (comp_pat[5] ^ nll0llO))) & (~ (comp_pat[6] ^ nll0lOi))) & (~ (comp_pat[7] ^ nll0lOl))) & (~ (comp_pat[8] ^ nll0lOO))) & (~ (comp_pat[9] ^ nll0O1i))), n100iil = ((((((((((~ ((~ comp_pat[0]) ^ nll0lii)) & (~ ((~ comp_pat[1]) ^ nll0lil))) & (~ ((~ comp_pat[2]) ^ nll0liO))) & (~ ((~ comp_pat[3]) ^ nll0lli))) & (~ ((~ comp_pat[4]) ^ nll0lll))) & (~ ((~ comp_pat[5]) ^ nll0llO))) & (~ ((~ comp_pat[6]) ^ nll0lOi))) & (~ ((~ comp_pat[7]) ^ nll0lOl))) & (~ ((~ comp_pat[8]) ^ nll0lOO))) & (~ ((~ comp_pat[9]) ^ nll0O1i))), n100iiO = ((comp_pat_porn & n100ill) | n100ili), n100ili = ((((((((((~ (comp_pat[0] ^ nll0l0O)) & (~ (comp_pat[1] ^ nll0lii))) & (~ (comp_pat[2] ^ nll0lil))) & (~ (comp_pat[3] ^ nll0liO))) & (~ (comp_pat[4] ^ nll0lli))) & (~ (comp_pat[5] ^ nll0lll))) & (~ (comp_pat[6] ^ nll0llO))) & (~ (comp_pat[7] ^ nll0lOi))) & (~ (comp_pat[8] ^ nll0lOl))) & (~ (comp_pat[9] ^ nll0lOO))), n100ill = ((((((((((~ ((~ comp_pat[0]) ^ nll0l0O)) & (~ ((~ comp_pat[1]) ^ nll0lii))) & (~ ((~ comp_pat[2]) ^ nll0lil))) & (~ ((~ comp_pat[3]) ^ nll0liO))) & (~ ((~ comp_pat[4]) ^ nll0lli))) & (~ ((~ comp_pat[5]) ^ nll0lll))) & (~ ((~ comp_pat[6]) ^ nll0llO))) & (~ ((~ comp_pat[7]) ^ nll0lOi))) & (~ ((~ comp_pat[8]) ^ nll0lOl))) & (~ ((~ comp_pat[9]) ^ nll0lOO))), n100ilO = ((comp_pat_porn & n100iOl) | n100iOi), n100iOi = ((((((((((~ (comp_pat[0] ^ nll0l0l)) & (~ (comp_pat[1] ^ nll0l0O))) & (~ (comp_pat[2] ^ nll0lii))) & (~ (comp_pat[3] ^ nll0lil))) & (~ (comp_pat[4] ^ nll0liO))) & (~ (comp_pat[5] ^ nll0lli))) & (~ (comp_pat[6] ^ nll0lll))) & (~ (comp_pat[7] ^ nll0llO))) & (~ (comp_pat[8] ^ nll0lOi))) & (~ (comp_pat[9] ^ nll0lOl))), n100iOl = ((((((((((~ ((~ comp_pat[0]) ^ nll0l0l)) & (~ ((~ comp_pat[1]) ^ nll0l0O))) & (~ ((~ comp_pat[2]) ^ nll0lii))) & (~ ((~ comp_pat[3]) ^ nll0lil))) & (~ ((~ comp_pat[4]) ^ nll0liO))) & (~ ((~ comp_pat[5]) ^ nll0lli))) & (~ ((~ comp_pat[6]) ^ nll0lll))) & (~ ((~ comp_pat[7]) ^ nll0llO))) & (~ ((~ comp_pat[8]) ^ nll0lOi))) & (~ ((~ comp_pat[9]) ^ nll0lOl))), n100iOO = ((comp_pat_porn & n100l1l) | n100l1i), n100l0i = ((((((((((~ (comp_pat[0] ^ nll0l1O)) & (~ (comp_pat[1] ^ nll0l0i))) & (~ (comp_pat[2] ^ nll0l0l))) & (~ (comp_pat[3] ^ nll0l0O))) & (~ (comp_pat[4] ^ nll0lii))) & (~ (comp_pat[5] ^ nll0lil))) & (~ (comp_pat[6] ^ nll0liO))) & (~ (comp_pat[7] ^ nll0lli))) & (~ (comp_pat[8] ^ nll0lll))) & (~ (comp_pat[9] ^ nll0llO))), n100l0l = ((((((((((~ ((~ comp_pat[0]) ^ nll0l1O)) & (~ ((~ comp_pat[1]) ^ nll0l0i))) & (~ ((~ comp_pat[2]) ^ nll0l0l))) & (~ ((~ comp_pat[3]) ^ nll0l0O))) & (~ ((~ comp_pat[4]) ^ nll0lii))) & (~ ((~ comp_pat[5]) ^ nll0lil))) & (~ ((~ comp_pat[6]) ^ nll0liO))) & (~ ((~ comp_pat[7]) ^ nll0lli))) & (~ ((~ comp_pat[8]) ^ nll0lll))) & (~ ((~ comp_pat[9]) ^ nll0llO))), n100l0O = ((comp_pat_porn & n100lil) | n100lii), n100l1i = ((((((((((~ (comp_pat[0] ^ nll0l0i)) & (~ (comp_pat[1] ^ nll0l0l))) & (~ (comp_pat[2] ^ nll0l0O))) & (~ (comp_pat[3] ^ nll0lii))) & (~ (comp_pat[4] ^ nll0lil))) & (~ (comp_pat[5] ^ nll0liO))) & (~ (comp_pat[6] ^ nll0lli))) & (~ (comp_pat[7] ^ nll0lll))) & (~ (comp_pat[8] ^ nll0llO))) & (~ (comp_pat[9] ^ nll0lOi))), n100l1l = ((((((((((~ ((~ comp_pat[0]) ^ nll0l0i)) & (~ ((~ comp_pat[1]) ^ nll0l0l))) & (~ ((~ comp_pat[2]) ^ nll0l0O))) & (~ ((~ comp_pat[3]) ^ nll0lii))) & (~ ((~ comp_pat[4]) ^ nll0lil))) & (~ ((~ comp_pat[5]) ^ nll0liO))) & (~ ((~ comp_pat[6]) ^ nll0lli))) & (~ ((~ comp_pat[7]) ^ nll0lll))) & (~ ((~ comp_pat[8]) ^ nll0llO))) & (~ ((~ comp_pat[9]) ^ nll0lOi))), n100l1O = ((comp_pat_porn & n100l0l) | n100l0i), n100lii = ((((((((((~ (comp_pat[0] ^ nll0l1l)) & (~ (comp_pat[1] ^ nll0l1O))) & (~ (comp_pat[2] ^ nll0l0i))) & (~ (comp_pat[3] ^ nll0l0l))) & (~ (comp_pat[4] ^ nll0l0O))) & (~ (comp_pat[5] ^ nll0lii))) & (~ (comp_pat[6] ^ nll0lil))) & (~ (comp_pat[7] ^ nll0liO))) & (~ (comp_pat[8] ^ nll0lli))) & (~ (comp_pat[9] ^ nll0lll))), n100lil = ((((((((((~ ((~ comp_pat[0]) ^ nll0l1l)) & (~ ((~ comp_pat[1]) ^ nll0l1O))) & (~ ((~ comp_pat[2]) ^ nll0l0i))) & (~ ((~ comp_pat[3]) ^ nll0l0l))) & (~ ((~ comp_pat[4]) ^ nll0l0O))) & (~ ((~ comp_pat[5]) ^ nll0lii))) & (~ ((~ comp_pat[6]) ^ nll0lil))) & (~ ((~ comp_pat[7]) ^ nll0liO))) & (~ ((~ comp_pat[8]) ^ nll0lli))) & (~ ((~ comp_pat[9]) ^ nll0lll))), n100liO = ((comp_pat_porn & n100lll) | n100lli), n100lli = ((((((((((~ (comp_pat[0] ^ nll0l1i)) & (~ (comp_pat[1] ^ nll0l1l))) & (~ (comp_pat[2] ^ nll0l1O))) & (~ (comp_pat[3] ^ nll0l0i))) & (~ (comp_pat[4] ^ nll0l0l))) & (~ (comp_pat[5] ^ nll0l0O))) & (~ (comp_pat[6] ^ nll0lii))) & (~ (comp_pat[7] ^ nll0lil))) & (~ (comp_pat[8] ^ nll0liO))) & (~ (comp_pat[9] ^ nll0lli))), n100lll = ((((((((((~ ((~ comp_pat[0]) ^ nll0l1i)) & (~ ((~ comp_pat[1]) ^ nll0l1l))) & (~ ((~ comp_pat[2]) ^ nll0l1O))) & (~ ((~ comp_pat[3]) ^ nll0l0i))) & (~ ((~ comp_pat[4]) ^ nll0l0l))) & (~ ((~ comp_pat[5]) ^ nll0l0O))) & (~ ((~ comp_pat[6]) ^ nll0lii))) & (~ ((~ comp_pat[7]) ^ nll0lil))) & (~ ((~ comp_pat[8]) ^ nll0liO))) & (~ ((~ comp_pat[9]) ^ nll0lli))), n100llO = ((comp_pat_porn & n100lOl) | n100lOi), n100lOi = ((((((((((~ (comp_pat[0] ^ nll0iOO)) & (~ (comp_pat[1] ^ nll0l1i))) & (~ (comp_pat[2] ^ nll0l1l))) & (~ (comp_pat[3] ^ nll0l1O))) & (~ (comp_pat[4] ^ nll0l0i))) & (~ (comp_pat[5] ^ nll0l0l))) & (~ (comp_pat[6] ^ nll0l0O))) & (~ (comp_pat[7] ^ nll0lii))) & (~ (comp_pat[8] ^ nll0lil))) & (~ (comp_pat[9] ^ nll0liO))), n100lOl = ((((((((((~ ((~ comp_pat[0]) ^ nll0iOO)) & (~ ((~ comp_pat[1]) ^ nll0l1i))) & (~ ((~ comp_pat[2]) ^ nll0l1l))) & (~ ((~ comp_pat[3]) ^ nll0l1O))) & (~ ((~ comp_pat[4]) ^ nll0l0i))) & (~ ((~ comp_pat[5]) ^ nll0l0l))) & (~ ((~ comp_pat[6]) ^ nll0l0O))) & (~ ((~ comp_pat[7]) ^ nll0lii))) & (~ ((~ comp_pat[8]) ^ nll0lil))) & (~ ((~ comp_pat[9]) ^ nll0liO))), n100lOO = ((comp_pat_porn & n100O1l) | n100O1i), n100O0i = ((((((((((~ (comp_pat[0] ^ nll0iOi)) & (~ (comp_pat[1] ^ nll0iOl))) & (~ (comp_pat[2] ^ nll0iOO))) & (~ (comp_pat[3] ^ nll0l1i))) & (~ (comp_pat[4] ^ nll0l1l))) & (~ (comp_pat[5] ^ nll0l1O))) & (~ (comp_pat[6] ^ nll0l0i))) & (~ (comp_pat[7] ^ nll0l0l))) & (~ (comp_pat[8] ^ nll0l0O))) & (~ (comp_pat[9] ^ nll0lii))), n100O0l = ((((((((((~ ((~ comp_pat[0]) ^ nll0iOi)) & (~ ((~ comp_pat[1]) ^ nll0iOl))) & (~ ((~ comp_pat[2]) ^ nll0iOO))) & (~ ((~ comp_pat[3]) ^ nll0l1i))) & (~ ((~ comp_pat[4]) ^ nll0l1l))) & (~ ((~ comp_pat[5]) ^ nll0l1O))) & (~ ((~ comp_pat[6]) ^ nll0l0i))) & (~ ((~ comp_pat[7]) ^ nll0l0l))) & (~ ((~ comp_pat[8]) ^ nll0l0O))) & (~ ((~ comp_pat[9]) ^ nll0lii))), n100O0O = ((comp_pat_porn & n100Oil) | n100Oii), n100O1i = ((((((((((~ (comp_pat[0] ^ nll0iOl)) & (~ (comp_pat[1] ^ nll0iOO))) & (~ (comp_pat[2] ^ nll0l1i))) & (~ (comp_pat[3] ^ nll0l1l))) & (~ (comp_pat[4] ^ nll0l1O))) & (~ (comp_pat[5] ^ nll0l0i))) & (~ (comp_pat[6] ^ nll0l0l))) & (~ (comp_pat[7] ^ nll0l0O))) & (~ (comp_pat[8] ^ nll0lii))) & (~ (comp_pat[9] ^ nll0lil))), n100O1l = ((((((((((~ ((~ comp_pat[0]) ^ nll0iOl)) & (~ ((~ comp_pat[1]) ^ nll0iOO))) & (~ ((~ comp_pat[2]) ^ nll0l1i))) & (~ ((~ comp_pat[3]) ^ nll0l1l))) & (~ ((~ comp_pat[4]) ^ nll0l1O))) & (~ ((~ comp_pat[5]) ^ nll0l0i))) & (~ ((~ comp_pat[6]) ^ nll0l0l))) & (~ ((~ comp_pat[7]) ^ nll0l0O))) & (~ ((~ comp_pat[8]) ^ nll0lii))) & (~ ((~ comp_pat[9]) ^ nll0lil))), n100O1O = ((comp_pat_porn & n100O0l) | n100O0i), n100Oii = ((((((((((~ (comp_pat[0] ^ nll0ilO)) & (~ (comp_pat[1] ^ nll0iOi))) & (~ (comp_pat[2] ^ nll0iOl))) & (~ (comp_pat[3] ^ nll0iOO))) & (~ (comp_pat[4] ^ nll0l1i))) & (~ (comp_pat[5] ^ nll0l1l))) & (~ (comp_pat[6] ^ nll0l1O))) & (~ (comp_pat[7] ^ nll0l0i))) & (~ (comp_pat[8] ^ nll0l0l))) & (~ (comp_pat[9] ^ nll0l0O))), n100Oil = ((((((((((~ ((~ comp_pat[0]) ^ nll0ilO)) & (~ ((~ comp_pat[1]) ^ nll0iOi))) & (~ ((~ comp_pat[2]) ^ nll0iOl))) & (~ ((~ comp_pat[3]) ^ nll0iOO))) & (~ ((~ comp_pat[4]) ^ nll0l1i))) & (~ ((~ comp_pat[5]) ^ nll0l1l))) & (~ ((~ comp_pat[6]) ^ nll0l1O))) & (~ ((~ comp_pat[7]) ^ nll0l0i))) & (~ ((~ comp_pat[8]) ^ nll0l0l))) & (~ ((~ comp_pat[9]) ^ nll0l0O))), n100OiO = ((comp_pat_porn & n100Oll) | n100Oli), n100Oli = ((((((((((~ (comp_pat[0] ^ nll0ill)) & (~ (comp_pat[1] ^ nll0ilO))) & (~ (comp_pat[2] ^ nll0iOi))) & (~ (comp_pat[3] ^ nll0iOl))) & (~ (comp_pat[4] ^ nll0iOO))) & (~ (comp_pat[5] ^ nll0l1i))) & (~ (comp_pat[6] ^ nll0l1l))) & (~ (comp_pat[7] ^ nll0l1O))) & (~ (comp_pat[8] ^ nll0l0i))) & (~ (comp_pat[9] ^ nll0l0l))), n100Oll = ((((((((((~ ((~ comp_pat[0]) ^ nll0ill)) & (~ ((~ comp_pat[1]) ^ nll0ilO))) & (~ ((~ comp_pat[2]) ^ nll0iOi))) & (~ ((~ comp_pat[3]) ^ nll0iOl))) & (~ ((~ comp_pat[4]) ^ nll0iOO))) & (~ ((~ comp_pat[5]) ^ nll0l1i))) & (~ ((~ comp_pat[6]) ^ nll0l1l))) & (~ ((~ comp_pat[7]) ^ nll0l1O))) & (~ ((~ comp_pat[8]) ^ nll0l0i))) & (~ ((~ comp_pat[9]) ^ nll0l0l))), n100OlO = ((comp_pat_porn & n100OOl) | n100OOi), n100OOi = ((((((((((~ (comp_pat[0] ^ nll0ili)) & (~ (comp_pat[1] ^ nll0ill))) & (~ (comp_pat[2] ^ nll0ilO))) & (~ (comp_pat[3] ^ nll0iOi))) & (~ (comp_pat[4] ^ nll0iOl))) & (~ (comp_pat[5] ^ nll0iOO))) & (~ (comp_pat[6] ^ nll0l1i))) & (~ (comp_pat[7] ^ nll0l1l))) & (~ (comp_pat[8] ^ nll0l1O))) & (~ (comp_pat[9] ^ nll0l0i))), n100OOl = ((((((((((~ ((~ comp_pat[0]) ^ nll0ili)) & (~ ((~ comp_pat[1]) ^ nll0ill))) & (~ ((~ comp_pat[2]) ^ nll0ilO))) & (~ ((~ comp_pat[3]) ^ nll0iOi))) & (~ ((~ comp_pat[4]) ^ nll0iOl))) & (~ ((~ comp_pat[5]) ^ nll0iOO))) & (~ ((~ comp_pat[6]) ^ nll0l1i))) & (~ ((~ comp_pat[7]) ^ nll0l1l))) & (~ ((~ comp_pat[8]) ^ nll0l1O))) & (~ ((~ comp_pat[9]) ^ nll0l0i))), n100OOO = ((comp_pat_porn & n10i11l) | n10i11i), n10100i = ((((((((((~ (comp_pat[20] ^ nll0lOl)) & (~ (comp_pat[21] ^ nll0lOO))) & (~ (comp_pat[22] ^ nll0O1i))) & (~ (comp_pat[23] ^ nll0O1l))) & (~ (comp_pat[24] ^ nll0O1O))) & (~ (comp_pat[25] ^ nll0O0i))) & (~ (comp_pat[26] ^ nll0O0l))) & (~ (comp_pat[27] ^ nll0O0O))) & (~ (comp_pat[28] ^ nll0Oii))) & (~ (comp_pat[29] ^ nll0Oil))), n10100l = ((((((((((~ ((~ comp_pat[20]) ^ nll0lOl)) & (~ ((~ comp_pat[21]) ^ nll0lOO))) & (~ ((~ comp_pat[22]) ^ nll0O1i))) & (~ ((~ comp_pat[23]) ^ nll0O1l))) & (~ ((~ comp_pat[24]) ^ nll0O1O))) & (~ ((~ comp_pat[25]) ^ nll0O0i))) & (~ ((~ comp_pat[26]) ^ nll0O0l))) & (~ ((~ comp_pat[27]) ^ nll0O0O))) & (~ ((~ comp_pat[28]) ^ nll0Oii))) & (~ ((~ comp_pat[29]) ^ nll0Oil))), n10100O = ((((((((((~ (comp_pat[30] ^ nll0OiO)) & (~ (comp_pat[31] ^ nll0Oli))) & (~ (comp_pat[32] ^ nll0Oll))) & (~ (comp_pat[33] ^ nll0OlO))) & (~ (comp_pat[34] ^ nll0OOi))) & (~ (comp_pat[35] ^ nll0OOl))) & (~ (comp_pat[36] ^ nll0OOO))) & (~ (comp_pat[37] ^ nlli11i))) & (~ (comp_pat[38] ^ nlli11l))) & (~ (comp_pat[39] ^ nlli11O))), n10101i = ((((((((((~ (comp_pat[30] ^ nll0Oli)) & (~ (comp_pat[31] ^ nll0Oll))) & (~ (comp_pat[32] ^ nll0OlO))) & (~ (comp_pat[33] ^ nll0OOi))) & (~ (comp_pat[34] ^ nll0OOl))) & (~ (comp_pat[35] ^ nll0OOO))) & (~ (comp_pat[36] ^ nlli11i))) & (~ (comp_pat[37] ^ nlli11l))) & (~ (comp_pat[38] ^ nlli11O))) & (~ (comp_pat[39] ^ nlli10i))), n10101l = ((((((((((~ ((~ comp_pat[30]) ^ nll0Oli)) & (~ ((~ comp_pat[31]) ^ nll0Oll))) & (~ ((~ comp_pat[32]) ^ nll0OlO))) & (~ ((~ comp_pat[33]) ^ nll0OOi))) & (~ ((~ comp_pat[34]) ^ nll0OOl))) & (~ ((~ comp_pat[35]) ^ nll0OOO))) & (~ ((~ comp_pat[36]) ^ nlli11i))) & (~ ((~ comp_pat[37]) ^ nlli11l))) & (~ ((~ comp_pat[38]) ^ nlli11O))) & (~ ((~ comp_pat[39]) ^ nlli10i))), n10101O = (n1001Ol & (((comp_pat_porn & n1010ii) | n10100O) & ((comp_pat_porn & n10100l) | n10100i))), n1010ii = ((((((((((~ ((~ comp_pat[30]) ^ nll0OiO)) & (~ ((~ comp_pat[31]) ^ nll0Oli))) & (~ ((~ comp_pat[32]) ^ nll0Oll))) & (~ ((~ comp_pat[33]) ^ nll0OlO))) & (~ ((~ comp_pat[34]) ^ nll0OOi))) & (~ ((~ comp_pat[35]) ^ nll0OOl))) & (~ ((~ comp_pat[36]) ^ nll0OOO))) & (~ ((~ comp_pat[37]) ^ nlli11i))) & (~ ((~ comp_pat[38]) ^ nlli11l))) & (~ ((~ comp_pat[39]) ^ nlli11O))), n1010il = (n10001l & (((comp_pat_porn & n1010lO) | n1010ll) & ((comp_pat_porn & n1010li) | n1010iO))), n1010iO = ((((((((((~ (comp_pat[20] ^ nll0lOi)) & (~ (comp_pat[21] ^ nll0lOl))) & (~ (comp_pat[22] ^ nll0lOO))) & (~ (comp_pat[23] ^ nll0O1i))) & (~ (comp_pat[24] ^ nll0O1l))) & (~ (comp_pat[25] ^ nll0O1O))) & (~ (comp_pat[26] ^ nll0O0i))) & (~ (comp_pat[27] ^ nll0O0l))) & (~ (comp_pat[28] ^ nll0O0O))) & (~ (comp_pat[29] ^ nll0Oii))), n1010li = ((((((((((~ ((~ comp_pat[20]) ^ nll0lOi)) & (~ ((~ comp_pat[21]) ^ nll0lOl))) & (~ ((~ comp_pat[22]) ^ nll0lOO))) & (~ ((~ comp_pat[23]) ^ nll0O1i))) & (~ ((~ comp_pat[24]) ^ nll0O1l))) & (~ ((~ comp_pat[25]) ^ nll0O1O))) & (~ ((~ comp_pat[26]) ^ nll0O0i))) & (~ ((~ comp_pat[27]) ^ nll0O0l))) & (~ ((~ comp_pat[28]) ^ nll0O0O))) & (~ ((~ comp_pat[29]) ^ nll0Oii))), n1010ll = ((((((((((~ (comp_pat[30] ^ nll0Oil)) & (~ (comp_pat[31] ^ nll0OiO))) & (~ (comp_pat[32] ^ nll0Oli))) & (~ (comp_pat[33] ^ nll0Oll))) & (~ (comp_pat[34] ^ nll0OlO))) & (~ (comp_pat[35] ^ nll0OOi))) & (~ (comp_pat[36] ^ nll0OOl))) & (~ (comp_pat[37] ^ nll0OOO))) & (~ (comp_pat[38] ^ nlli11i))) & (~ (comp_pat[39] ^ nlli11l))), n1010lO = ((((((((((~ ((~ comp_pat[30]) ^ nll0Oil)) & (~ ((~ comp_pat[31]) ^ nll0OiO))) & (~ ((~ comp_pat[32]) ^ nll0Oli))) & (~ ((~ comp_pat[33]) ^ nll0Oll))) & (~ ((~ comp_pat[34]) ^ nll0OlO))) & (~ ((~ comp_pat[35]) ^ nll0OOi))) & (~ ((~ comp_pat[36]) ^ nll0OOl))) & (~ ((~ comp_pat[37]) ^ nll0OOO))) & (~ ((~ comp_pat[38]) ^ nlli11i))) & (~ ((~ comp_pat[39]) ^ nlli11l))), n1010Oi = (n10000l & (((comp_pat_porn & n101i1l) | n101i1i) & ((comp_pat_porn & n1010OO) | n1010Ol))), n1010Ol = ((((((((((~ (comp_pat[20] ^ nll0llO)) & (~ (comp_pat[21] ^ nll0lOi))) & (~ (comp_pat[22] ^ nll0lOl))) & (~ (comp_pat[23] ^ nll0lOO))) & (~ (comp_pat[24] ^ nll0O1i))) & (~ (comp_pat[25] ^ nll0O1l))) & (~ (comp_pat[26] ^ nll0O1O))) & (~ (comp_pat[27] ^ nll0O0i))) & (~ (comp_pat[28] ^ nll0O0l))) & (~ (comp_pat[29] ^ nll0O0O))), n1010OO = ((((((((((~ ((~ comp_pat[20]) ^ nll0llO)) & (~ ((~ comp_pat[21]) ^ nll0lOi))) & (~ ((~ comp_pat[22]) ^ nll0lOl))) & (~ ((~ comp_pat[23]) ^ nll0lOO))) & (~ ((~ comp_pat[24]) ^ nll0O1i))) & (~ ((~ comp_pat[25]) ^ nll0O1l))) & (~ ((~ comp_pat[26]) ^ nll0O1O))) & (~ ((~ comp_pat[27]) ^ nll0O0i))) & (~ ((~ comp_pat[28]) ^ nll0O0l))) & (~ ((~ comp_pat[29]) ^ nll0O0O))), n10110i = ((((((((((~ (comp_pat[20] ^ nll0O1l)) & (~ (comp_pat[21] ^ nll0O1O))) & (~ (comp_pat[22] ^ nll0O0i))) & (~ (comp_pat[23] ^ nll0O0l))) & (~ (comp_pat[24] ^ nll0O0O))) & (~ (comp_pat[25] ^ nll0Oii))) & (~ (comp_pat[26] ^ nll0Oil))) & (~ (comp_pat[27] ^ nll0OiO))) & (~ (comp_pat[28] ^ nll0Oli))) & (~ (comp_pat[29] ^ nll0Oll))), n10110l = ((((((((((~ ((~ comp_pat[20]) ^ nll0O1l)) & (~ ((~ comp_pat[21]) ^ nll0O1O))) & (~ ((~ comp_pat[22]) ^ nll0O0i))) & (~ ((~ comp_pat[23]) ^ nll0O0l))) & (~ ((~ comp_pat[24]) ^ nll0O0O))) & (~ ((~ comp_pat[25]) ^ nll0Oii))) & (~ ((~ comp_pat[26]) ^ nll0Oil))) & (~ ((~ comp_pat[27]) ^ nll0OiO))) & (~ ((~ comp_pat[28]) ^ nll0Oli))) & (~ ((~ comp_pat[29]) ^ nll0Oll))), n10110O = ((((((((((~ (comp_pat[30] ^ nll0OlO)) & (~ (comp_pat[31] ^ nll0OOi))) & (~ (comp_pat[32] ^ nll0OOl))) & (~ (comp_pat[33] ^ nll0OOO))) & (~ (comp_pat[34] ^ nlli11i))) & (~ (comp_pat[35] ^ nlli11l))) & (~ (comp_pat[36] ^ nlli11O))) & (~ (comp_pat[37] ^ nlli10i))) & (~ (comp_pat[38] ^ nlli10l))) & (~ (comp_pat[39] ^ nlli10O))), n10111i = ((((((((((~ (comp_pat[30] ^ nll0OOi)) & (~ (comp_pat[31] ^ nll0OOl))) & (~ (comp_pat[32] ^ nll0OOO))) & (~ (comp_pat[33] ^ nlli11i))) & (~ (comp_pat[34] ^ nlli11l))) & (~ (comp_pat[35] ^ nlli11O))) & (~ (comp_pat[36] ^ nlli10i))) & (~ (comp_pat[37] ^ nlli10l))) & (~ (comp_pat[38] ^ nlli10O))) & (~ (comp_pat[39] ^ nlli1ii))), n10111l = ((((((((((~ ((~ comp_pat[30]) ^ nll0OOi)) & (~ ((~ comp_pat[31]) ^ nll0OOl))) & (~ ((~ comp_pat[32]) ^ nll0OOO))) & (~ ((~ comp_pat[33]) ^ nlli11i))) & (~ ((~ comp_pat[34]) ^ nlli11l))) & (~ ((~ comp_pat[35]) ^ nlli11O))) & (~ ((~ comp_pat[36]) ^ nlli10i))) & (~ ((~ comp_pat[37]) ^ nlli10l))) & (~ ((~ comp_pat[38]) ^ nlli10O))) & (~ ((~ comp_pat[39]) ^ nlli1ii))), n10111O = (n10010l & (((comp_pat_porn & n1011ii) | n10110O) & ((comp_pat_porn & n10110l) | n10110i))), n1011ii = ((((((((((~ ((~ comp_pat[30]) ^ nll0OlO)) & (~ ((~ comp_pat[31]) ^ nll0OOi))) & (~ ((~ comp_pat[32]) ^ nll0OOl))) & (~ ((~ comp_pat[33]) ^ nll0OOO))) & (~ ((~ comp_pat[34]) ^ nlli11i))) & (~ ((~ comp_pat[35]) ^ nlli11l))) & (~ ((~ comp_pat[36]) ^ nlli11O))) & (~ ((~ comp_pat[37]) ^ nlli10i))) & (~ ((~ comp_pat[38]) ^ nlli10l))) & (~ ((~ comp_pat[39]) ^ nlli10O))), n1011il = (n1001il & (((comp_pat_porn & n1011lO) | n1011ll) & ((comp_pat_porn & n1011li) | n1011iO))), n1011iO = ((((((((((~ (comp_pat[20] ^ nll0O1i)) & (~ (comp_pat[21] ^ nll0O1l))) & (~ (comp_pat[22] ^ nll0O1O))) & (~ (comp_pat[23] ^ nll0O0i))) & (~ (comp_pat[24] ^ nll0O0l))) & (~ (comp_pat[25] ^ nll0O0O))) & (~ (comp_pat[26] ^ nll0Oii))) & (~ (comp_pat[27] ^ nll0Oil))) & (~ (comp_pat[28] ^ nll0OiO))) & (~ (comp_pat[29] ^ nll0Oli))), n1011li = ((((((((((~ ((~ comp_pat[20]) ^ nll0O1i)) & (~ ((~ comp_pat[21]) ^ nll0O1l))) & (~ ((~ comp_pat[22]) ^ nll0O1O))) & (~ ((~ comp_pat[23]) ^ nll0O0i))) & (~ ((~ comp_pat[24]) ^ nll0O0l))) & (~ ((~ comp_pat[25]) ^ nll0O0O))) & (~ ((~ comp_pat[26]) ^ nll0Oii))) & (~ ((~ comp_pat[27]) ^ nll0Oil))) & (~ ((~ comp_pat[28]) ^ nll0OiO))) & (~ ((~ comp_pat[29]) ^ nll0Oli))), n1011ll = ((((((((((~ (comp_pat[30] ^ nll0Oll)) & (~ (comp_pat[31] ^ nll0OlO))) & (~ (comp_pat[32] ^ nll0OOi))) & (~ (comp_pat[33] ^ nll0OOl))) & (~ (comp_pat[34] ^ nll0OOO))) & (~ (comp_pat[35] ^ nlli11i))) & (~ (comp_pat[36] ^ nlli11l))) & (~ (comp_pat[37] ^ nlli11O))) & (~ (comp_pat[38] ^ nlli10i))) & (~ (comp_pat[39] ^ nlli10l))), n1011lO = ((((((((((~ ((~ comp_pat[30]) ^ nll0Oll)) & (~ ((~ comp_pat[31]) ^ nll0OlO))) & (~ ((~ comp_pat[32]) ^ nll0OOi))) & (~ ((~ comp_pat[33]) ^ nll0OOl))) & (~ ((~ comp_pat[34]) ^ nll0OOO))) & (~ ((~ comp_pat[35]) ^ nlli11i))) & (~ ((~ comp_pat[36]) ^ nlli11l))) & (~ ((~ comp_pat[37]) ^ nlli11O))) & (~ ((~ comp_pat[38]) ^ nlli10i))) & (~ ((~ comp_pat[39]) ^ nlli10l))), n1011Oi = (n1001ll & (((comp_pat_porn & n10101l) | n10101i) & ((comp_pat_porn & n1011OO) | n1011Ol))), n1011Ol = ((((((((((~ (comp_pat[20] ^ nll0lOO)) & (~ (comp_pat[21] ^ nll0O1i))) & (~ (comp_pat[22] ^ nll0O1l))) & (~ (comp_pat[23] ^ nll0O1O))) & (~ (comp_pat[24] ^ nll0O0i))) & (~ (comp_pat[25] ^ nll0O0l))) & (~ (comp_pat[26] ^ nll0O0O))) & (~ (comp_pat[27] ^ nll0Oii))) & (~ (comp_pat[28] ^ nll0Oil))) & (~ (comp_pat[29] ^ nll0OiO))), n1011OO = ((((((((((~ ((~ comp_pat[20]) ^ nll0lOO)) & (~ ((~ comp_pat[21]) ^ nll0O1i))) & (~ ((~ comp_pat[22]) ^ nll0O1l))) & (~ ((~ comp_pat[23]) ^ nll0O1O))) & (~ ((~ comp_pat[24]) ^ nll0O0i))) & (~ ((~ comp_pat[25]) ^ nll0O0l))) & (~ ((~ comp_pat[26]) ^ nll0O0O))) & (~ ((~ comp_pat[27]) ^ nll0Oii))) & (~ ((~ comp_pat[28]) ^ nll0Oil))) & (~ ((~ comp_pat[29]) ^ nll0OiO))), n101i0i = ((((((((((~ (comp_pat[20] ^ nll0lll)) & (~ (comp_pat[21] ^ nll0llO))) & (~ (comp_pat[22] ^ nll0lOi))) & (~ (comp_pat[23] ^ nll0lOl))) & (~ (comp_pat[24] ^ nll0lOO))) & (~ (comp_pat[25] ^ nll0O1i))) & (~ (comp_pat[26] ^ nll0O1l))) & (~ (comp_pat[27] ^ nll0O1O))) & (~ (comp_pat[28] ^ nll0O0i))) & (~ (comp_pat[29] ^ nll0O0l))), n101i0l = ((((((((((~ ((~ comp_pat[20]) ^ nll0lll)) & (~ ((~ comp_pat[21]) ^ nll0llO))) & (~ ((~ comp_pat[22]) ^ nll0lOi))) & (~ ((~ comp_pat[23]) ^ nll0lOl))) & (~ ((~ comp_pat[24]) ^ nll0lOO))) & (~ ((~ comp_pat[25]) ^ nll0O1i))) & (~ ((~ comp_pat[26]) ^ nll0O1l))) & (~ ((~ comp_pat[27]) ^ nll0O1O))) & (~ ((~ comp_pat[28]) ^ nll0O0i))) & (~ ((~ comp_pat[29]) ^ nll0O0l))), n101i0O = ((((((((((~ (comp_pat[30] ^ nll0O0O)) & (~ (comp_pat[31] ^ nll0Oii))) & (~ (comp_pat[32] ^ nll0Oil))) & (~ (comp_pat[33] ^ nll0OiO))) & (~ (comp_pat[34] ^ nll0Oli))) & (~ (comp_pat[35] ^ nll0Oll))) & (~ (comp_pat[36] ^ nll0OlO))) & (~ (comp_pat[37] ^ nll0OOi))) & (~ (comp_pat[38] ^ nll0OOl))) & (~ (comp_pat[39] ^ nll0OOO))), n101i1i = ((((((((((~ (comp_pat[30] ^ nll0Oii)) & (~ (comp_pat[31] ^ nll0Oil))) & (~ (comp_pat[32] ^ nll0OiO))) & (~ (comp_pat[33] ^ nll0Oli))) & (~ (comp_pat[34] ^ nll0Oll))) & (~ (comp_pat[35] ^ nll0OlO))) & (~ (comp_pat[36] ^ nll0OOi))) & (~ (comp_pat[37] ^ nll0OOl))) & (~ (comp_pat[38] ^ nll0OOO))) & (~ (comp_pat[39] ^ nlli11i))), n101i1l = ((((((((((~ ((~ comp_pat[30]) ^ nll0Oii)) & (~ ((~ comp_pat[31]) ^ nll0Oil))) & (~ ((~ comp_pat[32]) ^ nll0OiO))) & (~ ((~ comp_pat[33]) ^ nll0Oli))) & (~ ((~ comp_pat[34]) ^ nll0Oll))) & (~ ((~ comp_pat[35]) ^ nll0OlO))) & (~ ((~ comp_pat[36]) ^ nll0OOi))) & (~ ((~ comp_pat[37]) ^ nll0OOl))) & (~ ((~ comp_pat[38]) ^ nll0OOO))) & (~ ((~ comp_pat[39]) ^ nlli11i))), n101i1O = (n1000il & (((comp_pat_porn & n101iii) | n101i0O) & ((comp_pat_porn & n101i0l) | n101i0i))), n101iii = ((((((((((~ ((~ comp_pat[30]) ^ nll0O0O)) & (~ ((~ comp_pat[31]) ^ nll0Oii))) & (~ ((~ comp_pat[32]) ^ nll0Oil))) & (~ ((~ comp_pat[33]) ^ nll0OiO))) & (~ ((~ comp_pat[34]) ^ nll0Oli))) & (~ ((~ comp_pat[35]) ^ nll0Oll))) & (~ ((~ comp_pat[36]) ^ nll0OlO))) & (~ ((~ comp_pat[37]) ^ nll0OOi))) & (~ ((~ comp_pat[38]) ^ nll0OOl))) & (~ ((~ comp_pat[39]) ^ nll0OOO))), n101iil = (n1000ll & (((comp_pat_porn & n101ilO) | n101ill) & ((comp_pat_porn & n101ili) | n101iiO))), n101iiO = ((((((((((~ (comp_pat[20] ^ nll0lli)) & (~ (comp_pat[21] ^ nll0lll))) & (~ (comp_pat[22] ^ nll0llO))) & (~ (comp_pat[23] ^ nll0lOi))) & (~ (comp_pat[24] ^ nll0lOl))) & (~ (comp_pat[25] ^ nll0lOO))) & (~ (comp_pat[26] ^ nll0O1i))) & (~ (comp_pat[27] ^ nll0O1l))) & (~ (comp_pat[28] ^ nll0O1O))) & (~ (comp_pat[29] ^ nll0O0i))), n101ili = ((((((((((~ ((~ comp_pat[20]) ^ nll0lli)) & (~ ((~ comp_pat[21]) ^ nll0lll))) & (~ ((~ comp_pat[22]) ^ nll0llO))) & (~ ((~ comp_pat[23]) ^ nll0lOi))) & (~ ((~ comp_pat[24]) ^ nll0lOl))) & (~ ((~ comp_pat[25]) ^ nll0lOO))) & (~ ((~ comp_pat[26]) ^ nll0O1i))) & (~ ((~ comp_pat[27]) ^ nll0O1l))) & (~ ((~ comp_pat[28]) ^ nll0O1O))) & (~ ((~ comp_pat[29]) ^ nll0O0i))), n101ill = ((((((((((~ (comp_pat[30] ^ nll0O0l)) & (~ (comp_pat[31] ^ nll0O0O))) & (~ (comp_pat[32] ^ nll0Oii))) & (~ (comp_pat[33] ^ nll0Oil))) & (~ (comp_pat[34] ^ nll0OiO))) & (~ (comp_pat[35] ^ nll0Oli))) & (~ (comp_pat[36] ^ nll0Oll))) & (~ (comp_pat[37] ^ nll0OlO))) & (~ (comp_pat[38] ^ nll0OOi))) & (~ (comp_pat[39] ^ nll0OOl))), n101ilO = ((((((((((~ ((~ comp_pat[30]) ^ nll0O0l)) & (~ ((~ comp_pat[31]) ^ nll0O0O))) & (~ ((~ comp_pat[32]) ^ nll0Oii))) & (~ ((~ comp_pat[33]) ^ nll0Oil))) & (~ ((~ comp_pat[34]) ^ nll0OiO))) & (~ ((~ comp_pat[35]) ^ nll0Oli))) & (~ ((~ comp_pat[36]) ^ nll0Oll))) & (~ ((~ comp_pat[37]) ^ nll0OlO))) & (~ ((~ comp_pat[38]) ^ nll0OOi))) & (~ ((~ comp_pat[39]) ^ nll0OOl))), n101iOi = (((((((((((((((((((n1000ll | n1000il) | n10000l) | n10001l) | n1001Ol) | n1001ll) | n1001il) | n10010l) | n10011l) | n101OOl) | n101Oll) | n101Oil) | n101O0l) | n101O1l) | n101lOl) | n101lll) | n101lil) | n101l0l) | n101l1l) | n101iOl), n101iOl = (n1000OO & ((comp_pat_porn & n101l1i) | n101iOO)), n101iOO = ((((((((((~ (comp_pat[10] ^ nll0O0i)) & (~ (comp_pat[11] ^ nll0O0l))) & (~ (comp_pat[12] ^ nll0O0O))) & (~ (comp_pat[13] ^ nll0Oii))) & (~ (comp_pat[14] ^ nll0Oil))) & (~ (comp_pat[15] ^ nll0OiO))) & (~ (comp_pat[16] ^ nll0Oli))) & (~ (comp_pat[17] ^ nll0Oll))) & (~ (comp_pat[18] ^ nll0OlO))) & (~ (comp_pat[19] ^ nll0OOi))), n101l0i = ((((((((((~ ((~ comp_pat[10]) ^ nll0O1O)) & (~ ((~ comp_pat[11]) ^ nll0O0i))) & (~ ((~ comp_pat[12]) ^ nll0O0l))) & (~ ((~ comp_pat[13]) ^ nll0O0O))) & (~ ((~ comp_pat[14]) ^ nll0Oii))) & (~ ((~ comp_pat[15]) ^ nll0Oil))) & (~ ((~ comp_pat[16]) ^ nll0OiO))) & (~ ((~ comp_pat[17]) ^ nll0Oli))) & (~ ((~ comp_pat[18]) ^ nll0Oll))) & (~ ((~ comp_pat[19]) ^ nll0OlO))), n101l0l = (n100i0O & ((comp_pat_porn & n101lii) | n101l0O)), n101l0O = ((((((((((~ (comp_pat[10] ^ nll0O1l)) & (~ (comp_pat[11] ^ nll0O1O))) & (~ (comp_pat[12] ^ nll0O0i))) & (~ (comp_pat[13] ^ nll0O0l))) & (~ (comp_pat[14] ^ nll0O0O))) & (~ (comp_pat[15] ^ nll0Oii))) & (~ (comp_pat[16] ^ nll0Oil))) & (~ (comp_pat[17] ^ nll0OiO))) & (~ (comp_pat[18] ^ nll0Oli))) & (~ (comp_pat[19] ^ nll0Oll))), n101l1i = ((((((((((~ ((~ comp_pat[10]) ^ nll0O0i)) & (~ ((~ comp_pat[11]) ^ nll0O0l))) & (~ ((~ comp_pat[12]) ^ nll0O0O))) & (~ ((~ comp_pat[13]) ^ nll0Oii))) & (~ ((~ comp_pat[14]) ^ nll0Oil))) & (~ ((~ comp_pat[15]) ^ nll0OiO))) & (~ ((~ comp_pat[16]) ^ nll0Oli))) & (~ ((~ comp_pat[17]) ^ nll0Oll))) & (~ ((~ comp_pat[18]) ^ nll0OlO))) & (~ ((~ comp_pat[19]) ^ nll0OOi))), n101l1l = (n100i1O & ((comp_pat_porn & n101l0i) | n101l1O)), n101l1O = ((((((((((~ (comp_pat[10] ^ nll0O1O)) & (~ (comp_pat[11] ^ nll0O0i))) & (~ (comp_pat[12] ^ nll0O0l))) & (~ (comp_pat[13] ^ nll0O0O))) & (~ (comp_pat[14] ^ nll0Oii))) & (~ (comp_pat[15] ^ nll0Oil))) & (~ (comp_pat[16] ^ nll0OiO))) & (~ (comp_pat[17] ^ nll0Oli))) & (~ (comp_pat[18] ^ nll0Oll))) & (~ (comp_pat[19] ^ nll0OlO))), n101lii = ((((((((((~ ((~ comp_pat[10]) ^ nll0O1l)) & (~ ((~ comp_pat[11]) ^ nll0O1O))) & (~ ((~ comp_pat[12]) ^ nll0O0i))) & (~ ((~ comp_pat[13]) ^ nll0O0l))) & (~ ((~ comp_pat[14]) ^ nll0O0O))) & (~ ((~ comp_pat[15]) ^ nll0Oii))) & (~ ((~ comp_pat[16]) ^ nll0Oil))) & (~ ((~ comp_pat[17]) ^ nll0OiO))) & (~ ((~ comp_pat[18]) ^ nll0Oli))) & (~ ((~ comp_pat[19]) ^ nll0Oll))), n101lil = (n100iiO & ((comp_pat_porn & n101lli) | n101liO)), n101liO = ((((((((((~ (comp_pat[10] ^ nll0O1i)) & (~ (comp_pat[11] ^ nll0O1l))) & (~ (comp_pat[12] ^ nll0O1O))) & (~ (comp_pat[13] ^ nll0O0i))) & (~ (comp_pat[14] ^ nll0O0l))) & (~ (comp_pat[15] ^ nll0O0O))) & (~ (comp_pat[16] ^ nll0Oii))) & (~ (comp_pat[17] ^ nll0Oil))) & (~ (comp_pat[18] ^ nll0OiO))) & (~ (comp_pat[19] ^ nll0Oli))), n101lli = ((((((((((~ ((~ comp_pat[10]) ^ nll0O1i)) & (~ ((~ comp_pat[11]) ^ nll0O1l))) & (~ ((~ comp_pat[12]) ^ nll0O1O))) & (~ ((~ comp_pat[13]) ^ nll0O0i))) & (~ ((~ comp_pat[14]) ^ nll0O0l))) & (~ ((~ comp_pat[15]) ^ nll0O0O))) & (~ ((~ comp_pat[16]) ^ nll0Oii))) & (~ ((~ comp_pat[17]) ^ nll0Oil))) & (~ ((~ comp_pat[18]) ^ nll0OiO))) & (~ ((~ comp_pat[19]) ^ nll0Oli))), n101lll = (n100ilO & ((comp_pat_porn & n101lOi) | n101llO)), n101llO = ((((((((((~ (comp_pat[10] ^ nll0lOO)) & (~ (comp_pat[11] ^ nll0O1i))) & (~ (comp_pat[12] ^ nll0O1l))) & (~ (comp_pat[13] ^ nll0O1O))) & (~ (comp_pat[14] ^ nll0O0i))) & (~ (comp_pat[15] ^ nll0O0l))) & (~ (comp_pat[16] ^ nll0O0O))) & (~ (comp_pat[17] ^ nll0Oii))) & (~ (comp_pat[18] ^ nll0Oil))) & (~ (comp_pat[19] ^ nll0OiO))), n101lOi = ((((((((((~ ((~ comp_pat[10]) ^ nll0lOO)) & (~ ((~ comp_pat[11]) ^ nll0O1i))) & (~ ((~ comp_pat[12]) ^ nll0O1l))) & (~ ((~ comp_pat[13]) ^ nll0O1O))) & (~ ((~ comp_pat[14]) ^ nll0O0i))) & (~ ((~ comp_pat[15]) ^ nll0O0l))) & (~ ((~ comp_pat[16]) ^ nll0O0O))) & (~ ((~ comp_pat[17]) ^ nll0Oii))) & (~ ((~ comp_pat[18]) ^ nll0Oil))) & (~ ((~ comp_pat[19]) ^ nll0OiO))), n101lOl = (n100iOO & ((comp_pat_porn & n101O1i) | n101lOO)), n101lOO = ((((((((((~ (comp_pat[10] ^ nll0lOl)) & (~ (comp_pat[11] ^ nll0lOO))) & (~ (comp_pat[12] ^ nll0O1i))) & (~ (comp_pat[13] ^ nll0O1l))) & (~ (comp_pat[14] ^ nll0O1O))) & (~ (comp_pat[15] ^ nll0O0i))) & (~ (comp_pat[16] ^ nll0O0l))) & (~ (comp_pat[17] ^ nll0O0O))) & (~ (comp_pat[18] ^ nll0Oii))) & (~ (comp_pat[19] ^ nll0Oil))), n101O0i = ((((((((((~ ((~ comp_pat[10]) ^ nll0lOi)) & (~ ((~ comp_pat[11]) ^ nll0lOl))) & (~ ((~ comp_pat[12]) ^ nll0lOO))) & (~ ((~ comp_pat[13]) ^ nll0O1i))) & (~ ((~ comp_pat[14]) ^ nll0O1l))) & (~ ((~ comp_pat[15]) ^ nll0O1O))) & (~ ((~ comp_pat[16]) ^ nll0O0i))) & (~ ((~ comp_pat[17]) ^ nll0O0l))) & (~ ((~ comp_pat[18]) ^ nll0O0O))) & (~ ((~ comp_pat[19]) ^ nll0Oii))), n101O0l = (n100l0O & ((comp_pat_porn & n101Oii) | n101O0O)), n101O0O = ((((((((((~ (comp_pat[10] ^ nll0llO)) & (~ (comp_pat[11] ^ nll0lOi))) & (~ (comp_pat[12] ^ nll0lOl))) & (~ (comp_pat[13] ^ nll0lOO))) & (~ (comp_pat[14] ^ nll0O1i))) & (~ (comp_pat[15] ^ nll0O1l))) & (~ (comp_pat[16] ^ nll0O1O))) & (~ (comp_pat[17] ^ nll0O0i))) & (~ (comp_pat[18] ^ nll0O0l))) & (~ (comp_pat[19] ^ nll0O0O))), n101O1i = ((((((((((~ ((~ comp_pat[10]) ^ nll0lOl)) & (~ ((~ comp_pat[11]) ^ nll0lOO))) & (~ ((~ comp_pat[12]) ^ nll0O1i))) & (~ ((~ comp_pat[13]) ^ nll0O1l))) & (~ ((~ comp_pat[14]) ^ nll0O1O))) & (~ ((~ comp_pat[15]) ^ nll0O0i))) & (~ ((~ comp_pat[16]) ^ nll0O0l))) & (~ ((~ comp_pat[17]) ^ nll0O0O))) & (~ ((~ comp_pat[18]) ^ nll0Oii))) & (~ ((~ comp_pat[19]) ^ nll0Oil))), n101O1l = (n100l1O & ((comp_pat_porn & n101O0i) | n101O1O)), n101O1O = ((((((((((~ (comp_pat[10] ^ nll0lOi)) & (~ (comp_pat[11] ^ nll0lOl))) & (~ (comp_pat[12] ^ nll0lOO))) & (~ (comp_pat[13] ^ nll0O1i))) & (~ (comp_pat[14] ^ nll0O1l))) & (~ (comp_pat[15] ^ nll0O1O))) & (~ (comp_pat[16] ^ nll0O0i))) & (~ (comp_pat[17] ^ nll0O0l))) & (~ (comp_pat[18] ^ nll0O0O))) & (~ (comp_pat[19] ^ nll0Oii))), n101Oii = ((((((((((~ ((~ comp_pat[10]) ^ nll0llO)) & (~ ((~ comp_pat[11]) ^ nll0lOi))) & (~ ((~ comp_pat[12]) ^ nll0lOl))) & (~ ((~ comp_pat[13]) ^ nll0lOO))) & (~ ((~ comp_pat[14]) ^ nll0O1i))) & (~ ((~ comp_pat[15]) ^ nll0O1l))) & (~ ((~ comp_pat[16]) ^ nll0O1O))) & (~ ((~ comp_pat[17]) ^ nll0O0i))) & (~ ((~ comp_pat[18]) ^ nll0O0l))) & (~ ((~ comp_pat[19]) ^ nll0O0O))), n101Oil = (n100liO & ((comp_pat_porn & n101Oli) | n101OiO)), n101OiO = ((((((((((~ (comp_pat[10] ^ nll0lll)) & (~ (comp_pat[11] ^ nll0llO))) & (~ (comp_pat[12] ^ nll0lOi))) & (~ (comp_pat[13] ^ nll0lOl))) & (~ (comp_pat[14] ^ nll0lOO))) & (~ (comp_pat[15] ^ nll0O1i))) & (~ (comp_pat[16] ^ nll0O1l))) & (~ (comp_pat[17] ^ nll0O1O))) & (~ (comp_pat[18] ^ nll0O0i))) & (~ (comp_pat[19] ^ nll0O0l))), n101Oli = ((((((((((~ ((~ comp_pat[10]) ^ nll0lll)) & (~ ((~ comp_pat[11]) ^ nll0llO))) & (~ ((~ comp_pat[12]) ^ nll0lOi))) & (~ ((~ comp_pat[13]) ^ nll0lOl))) & (~ ((~ comp_pat[14]) ^ nll0lOO))) & (~ ((~ comp_pat[15]) ^ nll0O1i))) & (~ ((~ comp_pat[16]) ^ nll0O1l))) & (~ ((~ comp_pat[17]) ^ nll0O1O))) & (~ ((~ comp_pat[18]) ^ nll0O0i))) & (~ ((~ comp_pat[19]) ^ nll0O0l))), n101Oll = (n100llO & ((comp_pat_porn & n101OOi) | n101OlO)), n101OlO = ((((((((((~ (comp_pat[10] ^ nll0lli)) & (~ (comp_pat[11] ^ nll0lll))) & (~ (comp_pat[12] ^ nll0llO))) & (~ (comp_pat[13] ^ nll0lOi))) & (~ (comp_pat[14] ^ nll0lOl))) & (~ (comp_pat[15] ^ nll0lOO))) & (~ (comp_pat[16] ^ nll0O1i))) & (~ (comp_pat[17] ^ nll0O1l))) & (~ (comp_pat[18] ^ nll0O1O))) & (~ (comp_pat[19] ^ nll0O0i))), n101OOi = ((((((((((~ ((~ comp_pat[10]) ^ nll0lli)) & (~ ((~ comp_pat[11]) ^ nll0lll))) & (~ ((~ comp_pat[12]) ^ nll0llO))) & (~ ((~ comp_pat[13]) ^ nll0lOi))) & (~ ((~ comp_pat[14]) ^ nll0lOl))) & (~ ((~ comp_pat[15]) ^ nll0lOO))) & (~ ((~ comp_pat[16]) ^ nll0O1i))) & (~ ((~ comp_pat[17]) ^ nll0O1l))) & (~ ((~ comp_pat[18]) ^ nll0O1O))) & (~ ((~ comp_pat[19]) ^ nll0O0i))), n101OOl = (n100lOO & ((comp_pat_porn & n10011i) | n101OOO)), n101OOO = ((((((((((~ (comp_pat[10] ^ nll0liO)) & (~ (comp_pat[11] ^ nll0lli))) & (~ (comp_pat[12] ^ nll0lll))) & (~ (comp_pat[13] ^ nll0llO))) & (~ (comp_pat[14] ^ nll0lOi))) & (~ (comp_pat[15] ^ nll0lOl))) & (~ (comp_pat[16] ^ nll0lOO))) & (~ (comp_pat[17] ^ nll0O1i))) & (~ (comp_pat[18] ^ nll0O1l))) & (~ (comp_pat[19] ^ nll0O1O))), n10i00i = ((comp_pat_porn & n10i00O) | n10i00l), n10i00l = (((((((~ (comp_pat[0] ^ nll0lil)) & (~ (comp_pat[1] ^ nll0liO))) & (~ (comp_pat[2] ^ nll0lli))) & (~ (comp_pat[3] ^ nll0lll))) & (~ (comp_pat[4] ^ nll0llO))) & (~ (comp_pat[5] ^ nll0lOi))) & (~ (comp_pat[6] ^ nll0lOl))), n10i00O = (((((((~ ((~ comp_pat[0]) ^ nll0lil)) & (~ ((~ comp_pat[1]) ^ nll0liO))) & (~ ((~ comp_pat[2]) ^ nll0lli))) & (~ ((~ comp_pat[3]) ^ nll0lll))) & (~ ((~ comp_pat[4]) ^ nll0llO))) & (~ ((~ comp_pat[5]) ^ nll0lOi))) & (~ ((~ comp_pat[6]) ^ nll0lOl))), n10i01i = ((comp_pat_porn & n10i01O) | n10i01l), n10i01l = (((((((~ (comp_pat[0] ^ nll0liO)) & (~ (comp_pat[1] ^ nll0lli))) & (~ (comp_pat[2] ^ nll0lll))) & (~ (comp_pat[3] ^ nll0llO))) & (~ (comp_pat[4] ^ nll0lOi))) & (~ (comp_pat[5] ^ nll0lOl))) & (~ (comp_pat[6] ^ nll0lOO))), n10i01O = (((((((~ ((~ comp_pat[0]) ^ nll0liO)) & (~ ((~ comp_pat[1]) ^ nll0lli))) & (~ ((~ comp_pat[2]) ^ nll0lll))) & (~ ((~ comp_pat[3]) ^ nll0llO))) & (~ ((~ comp_pat[4]) ^ nll0lOi))) & (~ ((~ comp_pat[5]) ^ nll0lOl))) & (~ ((~ comp_pat[6]) ^ nll0lOO))), n10i0ii = ((comp_pat_porn & n10i0iO) | n10i0il), n10i0il = (((((((~ (comp_pat[0] ^ nll0lii)) & (~ (comp_pat[1] ^ nll0lil))) & (~ (comp_pat[2] ^ nll0liO))) & (~ (comp_pat[3] ^ nll0lli))) & (~ (comp_pat[4] ^ nll0lll))) & (~ (comp_pat[5] ^ nll0llO))) & (~ (comp_pat[6] ^ nll0lOi))), n10i0iO = (((((((~ ((~ comp_pat[0]) ^ nll0lii)) & (~ ((~ comp_pat[1]) ^ nll0lil))) & (~ ((~ comp_pat[2]) ^ nll0liO))) & (~ ((~ comp_pat[3]) ^ nll0lli))) & (~ ((~ comp_pat[4]) ^ nll0lll))) & (~ ((~ comp_pat[5]) ^ nll0llO))) & (~ ((~ comp_pat[6]) ^ nll0lOi))), n10i0li = ((comp_pat_porn & n10i0lO) | n10i0ll), n10i0ll = (((((((~ (comp_pat[0] ^ nll0l0O)) & (~ (comp_pat[1] ^ nll0lii))) & (~ (comp_pat[2] ^ nll0lil))) & (~ (comp_pat[3] ^ nll0liO))) & (~ (comp_pat[4] ^ nll0lli))) & (~ (comp_pat[5] ^ nll0lll))) & (~ (comp_pat[6] ^ nll0llO))), n10i0lO = (((((((~ ((~ comp_pat[0]) ^ nll0l0O)) & (~ ((~ comp_pat[1]) ^ nll0lii))) & (~ ((~ comp_pat[2]) ^ nll0lil))) & (~ ((~ comp_pat[3]) ^ nll0liO))) & (~ ((~ comp_pat[4]) ^ nll0lli))) & (~ ((~ comp_pat[5]) ^ nll0lll))) & (~ ((~ comp_pat[6]) ^ nll0llO))), n10i0Oi = ((comp_pat_porn & n10i0OO) | n10i0Ol), n10i0Ol = (((((((~ (comp_pat[0] ^ nll0l0l)) & (~ (comp_pat[1] ^ nll0l0O))) & (~ (comp_pat[2] ^ nll0lii))) & (~ (comp_pat[3] ^ nll0lil))) & (~ (comp_pat[4] ^ nll0liO))) & (~ (comp_pat[5] ^ nll0lli))) & (~ (comp_pat[6] ^ nll0lll))), n10i0OO = (((((((~ ((~ comp_pat[0]) ^ nll0l0l)) & (~ ((~ comp_pat[1]) ^ nll0l0O))) & (~ ((~ comp_pat[2]) ^ nll0lii))) & (~ ((~ comp_pat[3]) ^ nll0lil))) & (~ ((~ comp_pat[4]) ^ nll0liO))) & (~ ((~ comp_pat[5]) ^ nll0lli))) & (~ ((~ comp_pat[6]) ^ nll0lll))), n10i10i = ((((((((((~ (comp_pat[0] ^ nll0iil)) & (~ (comp_pat[1] ^ nll0iiO))) & (~ (comp_pat[2] ^ nll0ili))) & (~ (comp_pat[3] ^ nll0ill))) & (~ (comp_pat[4] ^ nll0ilO))) & (~ (comp_pat[5] ^ nll0iOi))) & (~ (comp_pat[6] ^ nll0iOl))) & (~ (comp_pat[7] ^ nll0iOO))) & (~ (comp_pat[8] ^ nll0l1i))) & (~ (comp_pat[9] ^ nll0l1l))), n10i10l = ((((((((((~ ((~ comp_pat[0]) ^ nll0iil)) & (~ ((~ comp_pat[1]) ^ nll0iiO))) & (~ ((~ comp_pat[2]) ^ nll0ili))) & (~ ((~ comp_pat[3]) ^ nll0ill))) & (~ ((~ comp_pat[4]) ^ nll0ilO))) & (~ ((~ comp_pat[5]) ^ nll0iOi))) & (~ ((~ comp_pat[6]) ^ nll0iOl))) & (~ ((~ comp_pat[7]) ^ nll0iOO))) & (~ ((~ comp_pat[8]) ^ nll0l1i))) & (~ ((~ comp_pat[9]) ^ nll0l1l))), n10i10O = ((comp_pat_porn & n10i1il) | n10i1ii), n10i11i = ((((((((((~ (comp_pat[0] ^ nll0iiO)) & (~ (comp_pat[1] ^ nll0ili))) & (~ (comp_pat[2] ^ nll0ill))) & (~ (comp_pat[3] ^ nll0ilO))) & (~ (comp_pat[4] ^ nll0iOi))) & (~ (comp_pat[5] ^ nll0iOl))) & (~ (comp_pat[6] ^ nll0iOO))) & (~ (comp_pat[7] ^ nll0l1i))) & (~ (comp_pat[8] ^ nll0l1l))) & (~ (comp_pat[9] ^ nll0l1O))), n10i11l = ((((((((((~ ((~ comp_pat[0]) ^ nll0iiO)) & (~ ((~ comp_pat[1]) ^ nll0ili))) & (~ ((~ comp_pat[2]) ^ nll0ill))) & (~ ((~ comp_pat[3]) ^ nll0ilO))) & (~ ((~ comp_pat[4]) ^ nll0iOi))) & (~ ((~ comp_pat[5]) ^ nll0iOl))) & (~ ((~ comp_pat[6]) ^ nll0iOO))) & (~ ((~ comp_pat[7]) ^ nll0l1i))) & (~ ((~ comp_pat[8]) ^ nll0l1l))) & (~ ((~ comp_pat[9]) ^ nll0l1O))), n10i11O = ((comp_pat_porn & n10i10l) | n10i10i), n10i1ii = ((((((((((~ (comp_pat[0] ^ nll0iii)) & (~ (comp_pat[1] ^ nll0iil))) & (~ (comp_pat[2] ^ nll0iiO))) & (~ (comp_pat[3] ^ nll0ili))) & (~ (comp_pat[4] ^ nll0ill))) & (~ (comp_pat[5] ^ nll0ilO))) & (~ (comp_pat[6] ^ nll0iOi))) & (~ (comp_pat[7] ^ nll0iOl))) & (~ (comp_pat[8] ^ nll0iOO))) & (~ (comp_pat[9] ^ nll0l1i))), n10i1il = ((((((((((~ ((~ comp_pat[0]) ^ nll0iii)) & (~ ((~ comp_pat[1]) ^ nll0iil))) & (~ ((~ comp_pat[2]) ^ nll0iiO))) & (~ ((~ comp_pat[3]) ^ nll0ili))) & (~ ((~ comp_pat[4]) ^ nll0ill))) & (~ ((~ comp_pat[5]) ^ nll0ilO))) & (~ ((~ comp_pat[6]) ^ nll0iOi))) & (~ ((~ comp_pat[7]) ^ nll0iOl))) & (~ ((~ comp_pat[8]) ^ nll0iOO))) & (~ ((~ comp_pat[9]) ^ nll0l1i))), n10i1iO = ((comp_pat_porn & n10i1ll) | n10i1li), n10i1li = ((((((((((~ (comp_pat[0] ^ nll0i0O)) & (~ (comp_pat[1] ^ nll0iii))) & (~ (comp_pat[2] ^ nll0iil))) & (~ (comp_pat[3] ^ nll0iiO))) & (~ (comp_pat[4] ^ nll0ili))) & (~ (comp_pat[5] ^ nll0ill))) & (~ (comp_pat[6] ^ nll0ilO))) & (~ (comp_pat[7] ^ nll0iOi))) & (~ (comp_pat[8] ^ nll0iOl))) & (~ (comp_pat[9] ^ nll0iOO))), n10i1ll = ((((((((((~ ((~ comp_pat[0]) ^ nll0i0O)) & (~ ((~ comp_pat[1]) ^ nll0iii))) & (~ ((~ comp_pat[2]) ^ nll0iil))) & (~ ((~ comp_pat[3]) ^ nll0iiO))) & (~ ((~ comp_pat[4]) ^ nll0ili))) & (~ ((~ comp_pat[5]) ^ nll0ill))) & (~ ((~ comp_pat[6]) ^ nll0ilO))) & (~ ((~ comp_pat[7]) ^ nll0iOi))) & (~ ((~ comp_pat[8]) ^ nll0iOl))) & (~ ((~ comp_pat[9]) ^ nll0iOO))), n10i1lO = ((comp_pat_porn & n10i1Ol) | n10i1Oi), n10i1Oi = ((((((((((~ (comp_pat[0] ^ nll0i0l)) & (~ (comp_pat[1] ^ nll0i0O))) & (~ (comp_pat[2] ^ nll0iii))) & (~ (comp_pat[3] ^ nll0iil))) & (~ (comp_pat[4] ^ nll0iiO))) & (~ (comp_pat[5] ^ nll0ili))) & (~ (comp_pat[6] ^ nll0ill))) & (~ (comp_pat[7] ^ nll0ilO))) & (~ (comp_pat[8] ^ nll0iOi))) & (~ (comp_pat[9] ^ nll0iOl))), n10i1Ol = ((((((((((~ ((~ comp_pat[0]) ^ nll0i0l)) & (~ ((~ comp_pat[1]) ^ nll0i0O))) & (~ ((~ comp_pat[2]) ^ nll0iii))) & (~ ((~ comp_pat[3]) ^ nll0iil))) & (~ ((~ comp_pat[4]) ^ nll0iiO))) & (~ ((~ comp_pat[5]) ^ nll0ili))) & (~ ((~ comp_pat[6]) ^ nll0ill))) & (~ ((~ comp_pat[7]) ^ nll0ilO))) & (~ ((~ comp_pat[8]) ^ nll0iOi))) & (~ ((~ comp_pat[9]) ^ nll0iOl))), n10i1OO = (((((((((((((((((((n10iOOi | n10iOli) | n10iOii) | n10iO0i) | n10iO1i) | n10ilOi) | n10illi) | n10ilii) | n10il0i) | n10il1i) | n10iiOi) | n10iili) | n10iiii) | n10ii0i) | n10ii1i) | n10i0Oi) | n10i0li) | n10i0ii) | n10i00i) | n10i01i), n10ii0i = ((comp_pat_porn & n10ii0O) | n10ii0l), n10ii0l = (((((((~ (comp_pat[0] ^ nll0l1O)) & (~ (comp_pat[1] ^ nll0l0i))) & (~ (comp_pat[2] ^ nll0l0l))) & (~ (comp_pat[3] ^ nll0l0O))) & (~ (comp_pat[4] ^ nll0lii))) & (~ (comp_pat[5] ^ nll0lil))) & (~ (comp_pat[6] ^ nll0liO))), n10ii0O = (((((((~ ((~ comp_pat[0]) ^ nll0l1O)) & (~ ((~ comp_pat[1]) ^ nll0l0i))) & (~ ((~ comp_pat[2]) ^ nll0l0l))) & (~ ((~ comp_pat[3]) ^ nll0l0O))) & (~ ((~ comp_pat[4]) ^ nll0lii))) & (~ ((~ comp_pat[5]) ^ nll0lil))) & (~ ((~ comp_pat[6]) ^ nll0liO))), n10ii1i = ((comp_pat_porn & n10ii1O) | n10ii1l), n10ii1l = (((((((~ (comp_pat[0] ^ nll0l0i)) & (~ (comp_pat[1] ^ nll0l0l))) & (~ (comp_pat[2] ^ nll0l0O))) & (~ (comp_pat[3] ^ nll0lii))) & (~ (comp_pat[4] ^ nll0lil))) & (~ (comp_pat[5] ^ nll0liO))) & (~ (comp_pat[6] ^ nll0lli))), n10ii1O = (((((((~ ((~ comp_pat[0]) ^ nll0l0i)) & (~ ((~ comp_pat[1]) ^ nll0l0l))) & (~ ((~ comp_pat[2]) ^ nll0l0O))) & (~ ((~ comp_pat[3]) ^ nll0lii))) & (~ ((~ comp_pat[4]) ^ nll0lil))) & (~ ((~ comp_pat[5]) ^ nll0liO))) & (~ ((~ comp_pat[6]) ^ nll0lli))), n10iiii = ((comp_pat_porn & n10iiiO) | n10iiil), n10iiil = (((((((~ (comp_pat[0] ^ nll0l1l)) & (~ (comp_pat[1] ^ nll0l1O))) & (~ (comp_pat[2] ^ nll0l0i))) & (~ (comp_pat[3] ^ nll0l0l))) & (~ (comp_pat[4] ^ nll0l0O))) & (~ (comp_pat[5] ^ nll0lii))) & (~ (comp_pat[6] ^ nll0lil))), n10iiiO = (((((((~ ((~ comp_pat[0]) ^ nll0l1l)) & (~ ((~ comp_pat[1]) ^ nll0l1O))) & (~ ((~ comp_pat[2]) ^ nll0l0i))) & (~ ((~ comp_pat[3]) ^ nll0l0l))) & (~ ((~ comp_pat[4]) ^ nll0l0O))) & (~ ((~ comp_pat[5]) ^ nll0lii))) & (~ ((~ comp_pat[6]) ^ nll0lil))), n10iili = ((comp_pat_porn & n10iilO) | n10iill), n10iill = (((((((~ (comp_pat[0] ^ nll0l1i)) & (~ (comp_pat[1] ^ nll0l1l))) & (~ (comp_pat[2] ^ nll0l1O))) & (~ (comp_pat[3] ^ nll0l0i))) & (~ (comp_pat[4] ^ nll0l0l))) & (~ (comp_pat[5] ^ nll0l0O))) & (~ (comp_pat[6] ^ nll0lii))), n10iilO = (((((((~ ((~ comp_pat[0]) ^ nll0l1i)) & (~ ((~ comp_pat[1]) ^ nll0l1l))) & (~ ((~ comp_pat[2]) ^ nll0l1O))) & (~ ((~ comp_pat[3]) ^ nll0l0i))) & (~ ((~ comp_pat[4]) ^ nll0l0l))) & (~ ((~ comp_pat[5]) ^ nll0l0O))) & (~ ((~ comp_pat[6]) ^ nll0lii))), n10iiOi = ((comp_pat_porn & n10iiOO) | n10iiOl), n10iiOl = (((((((~ (comp_pat[0] ^ nll0iOO)) & (~ (comp_pat[1] ^ nll0l1i))) & (~ (comp_pat[2] ^ nll0l1l))) & (~ (comp_pat[3] ^ nll0l1O))) & (~ (comp_pat[4] ^ nll0l0i))) & (~ (comp_pat[5] ^ nll0l0l))) & (~ (comp_pat[6] ^ nll0l0O))), n10iiOO = (((((((~ ((~ comp_pat[0]) ^ nll0iOO)) & (~ ((~ comp_pat[1]) ^ nll0l1i))) & (~ ((~ comp_pat[2]) ^ nll0l1l))) & (~ ((~ comp_pat[3]) ^ nll0l1O))) & (~ ((~ comp_pat[4]) ^ nll0l0i))) & (~ ((~ comp_pat[5]) ^ nll0l0l))) & (~ ((~ comp_pat[6]) ^ nll0l0O))), n10il0i = ((comp_pat_porn & n10il0O) | n10il0l), n10il0l = (((((((~ (comp_pat[0] ^ nll0iOi)) & (~ (comp_pat[1] ^ nll0iOl))) & (~ (comp_pat[2] ^ nll0iOO))) & (~ (comp_pat[3] ^ nll0l1i))) & (~ (comp_pat[4] ^ nll0l1l))) & (~ (comp_pat[5] ^ nll0l1O))) & (~ (comp_pat[6] ^ nll0l0i))), n10il0O = (((((((~ ((~ comp_pat[0]) ^ nll0iOi)) & (~ ((~ comp_pat[1]) ^ nll0iOl))) & (~ ((~ comp_pat[2]) ^ nll0iOO))) & (~ ((~ comp_pat[3]) ^ nll0l1i))) & (~ ((~ comp_pat[4]) ^ nll0l1l))) & (~ ((~ comp_pat[5]) ^ nll0l1O))) & (~ ((~ comp_pat[6]) ^ nll0l0i))), n10il1i = ((comp_pat_porn & n10il1O) | n10il1l), n10il1l = (((((((~ (comp_pat[0] ^ nll0iOl)) & (~ (comp_pat[1] ^ nll0iOO))) & (~ (comp_pat[2] ^ nll0l1i))) & (~ (comp_pat[3] ^ nll0l1l))) & (~ (comp_pat[4] ^ nll0l1O))) & (~ (comp_pat[5] ^ nll0l0i))) & (~ (comp_pat[6] ^ nll0l0l))), n10il1O = (((((((~ ((~ comp_pat[0]) ^ nll0iOl)) & (~ ((~ comp_pat[1]) ^ nll0iOO))) & (~ ((~ comp_pat[2]) ^ nll0l1i))) & (~ ((~ comp_pat[3]) ^ nll0l1l))) & (~ ((~ comp_pat[4]) ^ nll0l1O))) & (~ ((~ comp_pat[5]) ^ nll0l0i))) & (~ ((~ comp_pat[6]) ^ nll0l0l))), n10ilii = ((comp_pat_porn & n10iliO) | n10ilil), n10ilil = (((((((~ (comp_pat[0] ^ nll0ilO)) & (~ (comp_pat[1] ^ nll0iOi))) & (~ (comp_pat[2] ^ nll0iOl))) & (~ (comp_pat[3] ^ nll0iOO))) & (~ (comp_pat[4] ^ nll0l1i))) & (~ (comp_pat[5] ^ nll0l1l))) & (~ (comp_pat[6] ^ nll0l1O))), n10iliO = (((((((~ ((~ comp_pat[0]) ^ nll0ilO)) & (~ ((~ comp_pat[1]) ^ nll0iOi))) & (~ ((~ comp_pat[2]) ^ nll0iOl))) & (~ ((~ comp_pat[3]) ^ nll0iOO))) & (~ ((~ comp_pat[4]) ^ nll0l1i))) & (~ ((~ comp_pat[5]) ^ nll0l1l))) & (~ ((~ comp_pat[6]) ^ nll0l1O))), n10illi = ((comp_pat_porn & n10illO) | n10illl), n10illl = (((((((~ (comp_pat[0] ^ nll0ill)) & (~ (comp_pat[1] ^ nll0ilO))) & (~ (comp_pat[2] ^ nll0iOi))) & (~ (comp_pat[3] ^ nll0iOl))) & (~ (comp_pat[4] ^ nll0iOO))) & (~ (comp_pat[5] ^ nll0l1i))) & (~ (comp_pat[6] ^ nll0l1l))), n10illO = (((((((~ ((~ comp_pat[0]) ^ nll0ill)) & (~ ((~ comp_pat[1]) ^ nll0ilO))) & (~ ((~ comp_pat[2]) ^ nll0iOi))) & (~ ((~ comp_pat[3]) ^ nll0iOl))) & (~ ((~ comp_pat[4]) ^ nll0iOO))) & (~ ((~ comp_pat[5]) ^ nll0l1i))) & (~ ((~ comp_pat[6]) ^ nll0l1l))), n10ilOi = ((comp_pat_porn & n10ilOO) | n10ilOl), n10ilOl = (((((((~ (comp_pat[0] ^ nll0ili)) & (~ (comp_pat[1] ^ nll0ill))) & (~ (comp_pat[2] ^ nll0ilO))) & (~ (comp_pat[3] ^ nll0iOi))) & (~ (comp_pat[4] ^ nll0iOl))) & (~ (comp_pat[5] ^ nll0iOO))) & (~ (comp_pat[6] ^ nll0l1i))), n10ilOO = (((((((~ ((~ comp_pat[0]) ^ nll0ili)) & (~ ((~ comp_pat[1]) ^ nll0ill))) & (~ ((~ comp_pat[2]) ^ nll0ilO))) & (~ ((~ comp_pat[3]) ^ nll0iOi))) & (~ ((~ comp_pat[4]) ^ nll0iOl))) & (~ ((~ comp_pat[5]) ^ nll0iOO))) & (~ ((~ comp_pat[6]) ^ nll0l1i))), n10iO0i = ((comp_pat_porn & n10iO0O) | n10iO0l), n10iO0l = (((((((~ (comp_pat[0] ^ nll0iil)) & (~ (comp_pat[1] ^ nll0iiO))) & (~ (comp_pat[2] ^ nll0ili))) & (~ (comp_pat[3] ^ nll0ill))) & (~ (comp_pat[4] ^ nll0ilO))) & (~ (comp_pat[5] ^ nll0iOi))) & (~ (comp_pat[6] ^ nll0iOl))), n10iO0O = (((((((~ ((~ comp_pat[0]) ^ nll0iil)) & (~ ((~ comp_pat[1]) ^ nll0iiO))) & (~ ((~ comp_pat[2]) ^ nll0ili))) & (~ ((~ comp_pat[3]) ^ nll0ill))) & (~ ((~ comp_pat[4]) ^ nll0ilO))) & (~ ((~ comp_pat[5]) ^ nll0iOi))) & (~ ((~ comp_pat[6]) ^ nll0iOl))), n10iO1i = ((comp_pat_porn & n10iO1O) | n10iO1l), n10iO1l = (((((((~ (comp_pat[0] ^ nll0iiO)) & (~ (comp_pat[1] ^ nll0ili))) & (~ (comp_pat[2] ^ nll0ill))) & (~ (comp_pat[3] ^ nll0ilO))) & (~ (comp_pat[4] ^ nll0iOi))) & (~ (comp_pat[5] ^ nll0iOl))) & (~ (comp_pat[6] ^ nll0iOO))), n10iO1O = (((((((~ ((~ comp_pat[0]) ^ nll0iiO)) & (~ ((~ comp_pat[1]) ^ nll0ili))) & (~ ((~ comp_pat[2]) ^ nll0ill))) & (~ ((~ comp_pat[3]) ^ nll0ilO))) & (~ ((~ comp_pat[4]) ^ nll0iOi))) & (~ ((~ comp_pat[5]) ^ nll0iOl))) & (~ ((~ comp_pat[6]) ^ nll0iOO))), n10iOii = ((comp_pat_porn & n10iOiO) | n10iOil), n10iOil = (((((((~ (comp_pat[0] ^ nll0iii)) & (~ (comp_pat[1] ^ nll0iil))) & (~ (comp_pat[2] ^ nll0iiO))) & (~ (comp_pat[3] ^ nll0ili))) & (~ (comp_pat[4] ^ nll0ill))) & (~ (comp_pat[5] ^ nll0ilO))) & (~ (comp_pat[6] ^ nll0iOi))), n10iOiO = (((((((~ ((~ comp_pat[0]) ^ nll0iii)) & (~ ((~ comp_pat[1]) ^ nll0iil))) & (~ ((~ comp_pat[2]) ^ nll0iiO))) & (~ ((~ comp_pat[3]) ^ nll0ili))) & (~ ((~ comp_pat[4]) ^ nll0ill))) & (~ ((~ comp_pat[5]) ^ nll0ilO))) & (~ ((~ comp_pat[6]) ^ nll0iOi))), n10iOli = ((comp_pat_porn & n10iOlO) | n10iOll), n10iOll = (((((((~ (comp_pat[0] ^ nll0i0O)) & (~ (comp_pat[1] ^ nll0iii))) & (~ (comp_pat[2] ^ nll0iil))) & (~ (comp_pat[3] ^ nll0iiO))) & (~ (comp_pat[4] ^ nll0ili))) & (~ (comp_pat[5] ^ nll0ill))) & (~ (comp_pat[6] ^ nll0ilO))), n10iOlO = (((((((~ ((~ comp_pat[0]) ^ nll0i0O)) & (~ ((~ comp_pat[1]) ^ nll0iii))) & (~ ((~ comp_pat[2]) ^ nll0iil))) & (~ ((~ comp_pat[3]) ^ nll0iiO))) & (~ ((~ comp_pat[4]) ^ nll0ili))) & (~ ((~ comp_pat[5]) ^ nll0ill))) & (~ ((~ comp_pat[6]) ^ nll0ilO))), n10iOOi = ((comp_pat_porn & n10iOOO) | n10iOOl), n10iOOl = (((((((~ (comp_pat[0] ^ nll0i0l)) & (~ (comp_pat[1] ^ nll0i0O))) & (~ (comp_pat[2] ^ nll0iii))) & (~ (comp_pat[3] ^ nll0iil))) & (~ (comp_pat[4] ^ nll0iiO))) & (~ (comp_pat[5] ^ nll0ili))) & (~ (comp_pat[6] ^ nll0ill))), n10iOOO = (((((((~ ((~ comp_pat[0]) ^ nll0i0l)) & (~ ((~ comp_pat[1]) ^ nll0i0O))) & (~ ((~ comp_pat[2]) ^ nll0iii))) & (~ ((~ comp_pat[3]) ^ nll0iil))) & (~ ((~ comp_pat[4]) ^ nll0iiO))) & (~ ((~ comp_pat[5]) ^ nll0ili))) & (~ ((~ comp_pat[6]) ^ nll0ill))), n10l00i = ((n10ll0i & n10lili) & (~ n10li0O)), n10l00l = (n10ll0i & (~ n10lili)), n10l00O = (n10l0iO & (~ n10l0OO)), n10l01i = ((((wire_nllO0ii_dataout | wire_nllO00i_dataout) | wire_nllO01O_dataout) | wire_nllO01l_dataout) | (~ n10l01l)), n10l01l = (((((wire_nllO0il_dataout | wire_nllO0ii_dataout) | wire_nllO00O_dataout) | wire_nllO00i_dataout) | wire_nllO01O_dataout) | wire_nllO01l_dataout), n10l01O = (n10lili & (~ n10li0O)), n10l0ii = ((wire_nllOO1l_o & n10l0iO) & n10l0OO), n10l0il = ((wire_nlO10Ol_o & n10l0iO) & n10l0OO), n10l0iO = ((~ n10ll0i) & n10lili), n10l0li = ((~ n10ll0i) & (~ n10lili)), n10l0ll = ((n10liil & n10l0lO) & n10l0OO), n10l0lO = ((((((((((~ nlO0i1i) & (~ nlO00OO)) & (~ nlO00Ol)) & (~ nlO00Oi)) & (~ nlO00lO)) & (~ nlO00ll)) & (~ nlO00li)) & (~ nlO00iO)) & (~ nlO00il)) & nlO00ii), n10l0Oi = ((wire_nlO10Ol_o & n10liil) & n10l0OO), n10l0Ol = (n10liil & (~ n10l0OO)), n10l0OO = ((((((((((~ (gnumber[0] ^ nlO01lO)) & (~ (gnumber[1] ^ nlO01Oi))) & (~ (gnumber[2] ^ nlO01Ol))) & (~ (gnumber[3] ^ nlO01OO))) & (~ (gnumber[4] ^ nlO001i))) & (~ (gnumber[5] ^ nlO001l))) & (~ (gnumber[6] ^ nlO001O))) & (~ (gnumber[7] ^ nlO000i))) & (~ (gnumber[8] ^ nlO000l))) & (~ (gnumber[9] ^ nlO000O))), n10l10i = ((n10l1il | (rencdt_rising & nlli0Ol)) & (((((~ resync_badcg_en[0]) & (~ resync_badcg_en[1])) | (resync_badcg_en[0] & resync_badcg_en[1])) | (n10l1ii & (resync_badcg_en[0] & (~ resync_badcg_en[1])))) | ((n10l1ii | (n10l10O | n10l10l)) & ((~ resync_badcg_en[0]) & resync_badcg_en[1])))), n10l10l = (((((~ wire_n1l11lO_dataout) & ((((((nlOO0lOl | nlOO0lOO) | nlOO0lOi) | (nlOO0i0O & nlOO0i0l)) | (nlOO0lil & nlOO0i0i)) | nlOO0O1i) | nlOO0i1O)) | (wire_n1l11lO_dataout & (nlOO0i1l | ((~ wire_nl1llii_o) & nlOO0i1i)))) | ((nlOO0ilO | (nlOO0l0i | nlOO0lll)) & (~ wire_n1lllii_dataout))) | ((nlOO0iOl | (wire_nl1llll_o & (wire_nl1llli_o & nlOO0iOi))) & wire_n1lllii_dataout)), n10l10O = (((((~ nl1liil) & ((((((nlOO010l | nlOO010O) | nlOO010i) | (nlOO1llO & nlOO1lll)) | (nlOO1OOl & nlOO1lli)) | nlOO01ii) | nlOO1liO)) | (nl1liil & (nlOO1lil | ((~ wire_nl1lilO_o) & nlOO1lii)))) | ((nlOO1O1O | (nlOO1Oli | nlOO011l)) & (~ wire_n1iliii_dataout))) | ((nlOO1O0l | (wire_nl1ll1i_o & (wire_nl1liOO_o & nlOO1O0i))) & wire_n1iliii_dataout)), n10l11i = (n10l11O | n10l11l), n10l11l = (nll01ll & (~ nll01li)), n10l11O = ((~ nll01ll) & nll01li), n10l1ii = ((~ wire_n1liO0O_dataout) | (~ wire_n1Ol10O_dataout)), n10l1il = ((~ rencdt_rising) & nllii0i), n10l1iO = ((~ wa_6g_en) | ((~ lpbk_en) & (~ nll01lO))), n10l1li = (((~ nlli0OO) & (wa_6g_en & (lpbk_en | nll01lO))) & n1iiilO), n10l1ll = (wire_nllO0ii_dataout | ((((~ (rosnumber[0] ^ nlO01il)) & (~ (rosnumber[1] ^ nlO01iO))) & (~ (rosnumber[2] ^ nlO01li))) & (~ (rosnumber[3] ^ nlO01ll)))), n10l1lO = (wire_nllO00i_dataout | wire_nllO01O_dataout), n10l1Oi = ((wire_nllO0il_dataout | wire_nllO0ii_dataout) | (~ n10l01l)), n10l1Ol = (((wire_nllO0il_dataout | wire_nllO0ii_dataout) | wire_nllO01l_dataout) | (~ n10l01l)), n10l1OO = ((((wire_nllO00O_dataout | wire_nllO00i_dataout) | wire_nllO01O_dataout) | wire_nllO01l_dataout) | (~ n10l01l)), n10li0i = (rosbased & (~ n10ll0i)), n10li0l = (n10liii & (~ n10li0O)), n10li0O = ((((((((((~ (enumber[0] ^ nlO00ii)) & (~ (enumber[1] ^ nlO00il))) & (~ (enumber[2] ^ nlO00iO))) & (~ (enumber[3] ^ nlO00li))) & (~ (enumber[4] ^ nlO00ll))) & (~ (enumber[5] ^ nlO00lO))) & (~ (enumber[6] ^ nlO00Oi))) & (~ (enumber[7] ^ nlO00Ol))) & (~ (enumber[8] ^ nlO00OO))) & (~ (enumber[9] ^ nlO0i1i))), n10li1i = ((wire_nlO10Ol_o & n10liil) & n10l0OO), n10li1l = (n10liil & (~ n10l0OO)), n10li1O = ((n10liil & n10l0lO) & n10l0OO), n10liii = ((~ rosbased) & n10ll0i), n10liil = ((~ rosbased) & (~ n10ll0i)), n10liiO = (n10liii & n10li0O), n10lili = ((((~ (rosnumber[0] ^ wire_nlO0l0i_o[0])) & (~ (rosnumber[1] ^ wire_nlO0l0i_o[1]))) & (~ (rosnumber[2] ^ wire_nlO0l0i_o[2]))) & (~ (rosnumber[3] ^ wire_nlO0l0i_o[3]))), n10lill = (((~ n10liOl) & niii0l) & ((~ n10ll0O) | n10ll0l)), n10lilO = ((n10liOO | (n10llii & (n10ll0O & n10lili))) & n10liOl), n10liOi = (n10liOO & (~ n10liOl)), n10liOl = ((((((((((~ (knumber[0] ^ nlO0i1l)) & (~ (knumber[1] ^ nlO0i1O))) & (~ (knumber[2] ^ nlO0i0i))) & (~ (knumber[3] ^ nlO0i0l))) & (~ (knumber[4] ^ nlO0i0O))) & (~ (knumber[5] ^ nlO0iii))) & (~ (knumber[6] ^ nlO0iil))) & (~ (knumber[7] ^ nlO0iiO))) & (~ (knumber[8] ^ nlO0ili))) & (~ (knumber[9] ^ nlO0ill))), n10liOO = ((~ n10ll0O) & niii0l), n10ll0i = ((n10ll0O & (((rkchar & niiill) | ((~ rkchar) & niii0l)) & (~ n10ll0l))) | nil1Oi), n10ll0l = ((((~ (rosnumber[0] ^ nlO01il)) & (~ (rosnumber[1] ^ nlO01iO))) & (~ (rosnumber[2] ^ nlO01li))) & (~ (rosnumber[3] ^ nlO01ll))), n10ll0O = (((rosnumber[0] | rosnumber[1]) | rosnumber[2]) | rosnumber[3]), n10ll1i = (((~ n10llii) & n10ll0O) | nil1Oi), n10ll1l = ((~ n10ll0O) & ((~ n10ll1O) & niii0l)), n10ll1O = (((((((((knumber[0] | knumber[1]) | knumber[2]) | knumber[3]) | knumber[4]) | knumber[5]) | knumber[6]) | knumber[7]) | knumber[8]) | knumber[9]), n10llii = ((~ nil1Oi) & (~ niiill)), n10llil = (wire_niOilO_o & wire_niOill_o), n10lliO = ((~ wire_niOilO_o) & (~ wire_niOill_o)), n10llli = (wire_niOilO_o & (~ wire_niOill_o)), n10llll = ((~ wire_niOilO_o) & wire_niOill_o), n10lllO = (n1i000O & n10llOl), n10llOi = ((~ wire_niOiOl_o) & ((~ wire_niOiOi_o) & ((~ wire_niOilO_o) & (~ wire_niOill_o)))), n10llOl = (wire_niOl1i_o & wire_niOiOO_o), n10llOO = (wire_niOiOl_o & (wire_niOiOi_o & (wire_niOilO_o & wire_niOill_o))), n10lO0i = (wire_niOl1O_o & (~ wire_niOl1l_o)), n10lO0l = ((~ wire_niOl1O_o) & wire_niOl1l_o), n10lO0O = (wire_niOl0i_dataout ^ wire_niOl1l_o), n10lO1i = (((((~ wire_niOiOl_o) & (wire_niOiOi_o & n10llil)) | (wire_niOiOl_o & ((~ wire_niOiOi_o) & n10llil))) | (wire_niOiOl_o & (wire_niOiOi_o & ((~ wire_niOilO_o) & wire_niOill_o)))) | (wire_niOiOl_o & (wire_niOiOi_o & (wire_niOilO_o & (~ wire_niOill_o))))), n10lO1l = (wire_niOl1O_o & wire_niOl1l_o), n10lO1O = ((~ wire_niOl1O_o) & (~ wire_niOl1l_o)), n10lOii = (wire_niOilO_o & wire_niOill_o), n10lOil = ((~ wire_niOilO_o) & (~ wire_niOill_o)), n10lOiO = (wire_niOilO_o & (~ wire_niOill_o)), n10lOli = ((~ wire_niOilO_o) & wire_niOill_o), n10lOll = (((((~ wire_niOl0l_dataout) & (wire_niOl0i_dataout & n10lO1l)) | (wire_niOl0l_dataout & ((~ wire_niOl0i_dataout) & n10lO1l))) | (wire_niOl0l_dataout & (wire_niOl0i_dataout & ((~ wire_niOl1O_o) & wire_niOl1l_o)))) | (wire_niOl0l_dataout & (wire_niOl0i_dataout & (wire_niOl1O_o & (~ wire_niOl1l_o))))), n10lOlO = (((~ wire_nlOll0O_dataout) & n10llOl) | (wire_nlOll0O_dataout & n1i00ii)), n10lOOi = (wire_niOl0l_dataout & (wire_niOl0i_dataout & (wire_niOl1O_o & wire_niOl1l_o))), n10lOOl = (n10llOO & n1i000l), n10lOOO = ((n10llOO & n10llOl) | (n10lO1i & n10llOl)), n10O00i = (n1O01l | n1O01i), n10O00l = ((~ n1OOOO) & (~ n1OOOl)), n10O00O = ((~ n1OOOO) & n1OOOl), n10O01i = (n1O1OO | n1O1Ol), n10O01l = ((((n1O01l | n1O01i) | n1O1OO) | n1O1Ol) | n1O1Oi), n10O01O = ((((n1O01l | n1O01i) | n1O1lO) | n1O1ll) | n1l0Oi), n10O0ii = (n1l0lO & n1l0ll), n10O0il = ((~ n010Ol) & (~ n1OOOl)), n10O0iO = ((~ n010Ol) & n1OOOl), n10O0li = ((((max_rlv_sel[0] | max_rlv_sel[1]) | max_rlv_sel[2]) | max_rlv_sel[3]) | max_rlv_sel[4]), n10O0ll = ((((((((~ wire_n1O0ll_dataout) & (~ wire_n1O0li_dataout)) & (~ wire_n1O0iO_dataout)) & (~ wire_n1O0il_dataout)) & (~ wire_n1O0ii_dataout)) & wire_n1O00O_dataout) & (~ wire_n1O00l_dataout)) & (~ wire_n1O00i_dataout)), n10O0lO = ((((((((~ wire_n1O0ll_dataout) & (~ wire_n1O0li_dataout)) & (~ wire_n1O0iO_dataout)) & (~ wire_n1O0il_dataout)) & (~ wire_n1O0ii_dataout)) & wire_n1O00O_dataout) & (~ wire_n1O00l_dataout)) & wire_n1O00i_dataout), n10O0Oi = (((((((pmadwidth[0] | (~ nlil1O)) | (~ nlil1l)) | (~ nlil1i)) | (~ nliiOO)) | (~ nliiOl)) | (~ wire_n1OOOi_dataout)) | (~ n1OiOi)), n10O0Ol = (((((((pmadwidth[0] | (~ nlil0i)) | (~ nlil1O)) | (~ nlil1l)) | (~ nlil1i)) | (~ nliiOO)) | (~ wire_n1OOOi_dataout)) | (~ n1OiOi)), n10O0OO = (((((((pmadwidth[0] | (~ nlil1l)) | (~ nlil1i)) | (~ nliiOO)) | (~ nliiOl)) | (~ nl1lOi)) | (~ wire_n1OOOi_dataout)) | (~ n1OiOi)), n10O10i = ((~ wire_niOl1O_o) & (~ wire_niOl1l_o)), n10O10l = (wire_niOl1O_o & wire_niOl1l_o), n10O10O = ((wire_niOl1i_o & (wire_niOiOO_o & (wire_niOiOl_o & wire_niOiOi_o))) | ((~ wire_niOl1i_o) & ((~ wire_niOiOO_o) & ((~ wire_niOiOl_o) & (~ wire_niOiOi_o))))), n10O11i = (n10llOO & n1i00ii), n10O11l = ((~ wire_niOl0l_dataout) & (~ wire_niOl0i_dataout)), n10O11O = (((((((~ wire_niOiOl_o) & ((~ wire_niOiOi_o) & (wire_niOilO_o & wire_niOill_o))) | ((~ wire_niOiOl_o) & (wire_niOiOi_o & n10lOli))) | ((~ wire_niOiOl_o) & (wire_niOiOi_o & n10lOiO))) | (wire_niOiOl_o & ((~ wire_niOiOi_o) & n10lOli))) | (wire_niOiOl_o & ((~ wire_niOiOi_o) & n10lOiO))) | (wire_niOiOl_o & (wire_niOiOi_o & ((~ wire_niOilO_o) & (~ wire_niOill_o))))), n10O1ii = ((~ wire_niOl1i_o) & wire_niOiOO_o), n10O1il = (wire_niOl1i_o & (~ wire_niOiOO_o)), n10O1iO = (((((~ wire_niOiOl_o) & (wire_niOiOi_o & n10lOii)) | (wire_niOiOl_o & ((~ wire_niOiOi_o) & n10lOii))) | (wire_niOiOl_o & (wire_niOiOi_o & ((~ wire_niOilO_o) & wire_niOill_o)))) | (wire_niOiOl_o & (wire_niOiOi_o & (wire_niOilO_o & (~ wire_niOill_o))))), n10O1li = (((((~ wire_niOiOl_o) & ((~ wire_niOiOi_o) & ((~ wire_niOilO_o) & wire_niOill_o))) | ((~ wire_niOiOl_o) & ((~ wire_niOiOi_o) & (wire_niOilO_o & (~ wire_niOill_o))))) | ((~ wire_niOiOl_o) & (wire_niOiOi_o & n10lOil))) | (wire_niOiOl_o & ((~ wire_niOiOi_o) & n10lOil))), n10O1ll = ((~ wire_niOiOl_o) & ((~ wire_niOiOi_o) & ((~ wire_niOilO_o) & (~ wire_niOill_o)))), n10O1lO = (wire_niOiOl_o & (wire_niOiOi_o & (wire_niOilO_o & wire_niOill_o))), n10O1Oi = ((ib_invalid_code[0] & ((((~ wire_niOl1O_o) & n1i1OlO) & n10lO0O) | ((wire_niOl1O_o & n1i1Oll) & n10lO0O))) | (ib_invalid_code[1] & ((wire_niOl0i_dataout & (wire_niOl1O_o & (n1i1OlO & n1i01ll))) | ((~ wire_niOl0i_dataout) & ((~ wire_niOl1O_o) & (n1i1Oll & n1i01ll)))))), n10O1Ol = (n1O1Oi | n1l0Oi), n10O1OO = (n1O1lO | n1O1ll), n10Oi0i = (((((((((~ pmadwidth[0]) | (~ nlil1O)) | (~ nlil1l)) | (~ nlil1i)) | (~ nliiOO)) | (~ nliiOl)) | (~ nl1lOi)) | (~ wire_n1OOOi_dataout)) | (~ n1OiOi)), n10Oi0l = (((((((pmadwidth[0] | nlil1O) | nlil1l) | nlil1i) | nliiOO) | nliiOl) | (~ wire_n1OOOi_dataout)) | (~ n1OiOi)), n10Oi0O = (((((((pmadwidth[0] | nlil0i) | nlil1O) | nlil1l) | nlil1i) | nliiOO) | (~ wire_n1OOOi_dataout)) | (~ n1OiOi)), n10Oi1i = (((((((((~ pmadwidth[0]) | (~ nlil0O)) | (~ nlil0l)) | (~ nlil0i)) | (~ nlil1O)) | (~ nlil1l)) | (~ nlil1i)) | (~ wire_n1OOOi_dataout)) | (~ n1OiOi)), n10Oi1l = (((((((((~ pmadwidth[0]) | (~ nlil0l)) | (~ nlil0i)) | (~ nlil1O)) | (~ nlil1l)) | (~ nlil1i)) | (~ nliiOO)) | (~ wire_n1OOOi_dataout)) | (~ n1OiOi)), n10Oi1O = (((((((((~ pmadwidth[0]) | (~ nlil0i)) | (~ nlil1O)) | (~ nlil1l)) | (~ nlil1i)) | (~ nliiOO)) | (~ nliiOl)) | (~ wire_n1OOOi_dataout)) | (~ n1OiOi)), n10Oiii = (((((((pmadwidth[0] | nlil1l) | nlil1i) | nliiOO) | nliiOl) | nl1lOi) | (~ wire_n1OOOi_dataout)) | (~ n1OiOi)), n10Oiil = (((((((((~ pmadwidth[0]) | nlil0O) | nlil0l) | nlil0i) | nlil1O) | nlil1l) | nlil1i) | (~ wire_n1OOOi_dataout)) | (~ n1OiOi)), n10OiiO = (((((((((~ pmadwidth[0]) | nlil0l) | nlil0i) | nlil1O) | nlil1l) | nlil1i) | nliiOO) | (~ wire_n1OOOi_dataout)) | (~ n1OiOi)), n10Oili = (((((((((~ pmadwidth[0]) | nlil0i) | nlil1O) | nlil1l) | nlil1i) | nliiOO) | nliiOl) | (~ wire_n1OOOi_dataout)) | (~ n1OiOi)), n10Oill = (((((((((~ pmadwidth[0]) | nlil1O) | nlil1l) | nlil1i) | nliiOO) | nliiOl) | nl1lOi) | (~ wire_n1OOOi_dataout)) | (~ n1OiOi)), n10OilO = (((((~ n10Ol0O) | (~ n10Ol0l)) | (~ n10Ol1O)) | (~ n10Ol1i)) | n10OiOi), n10OiOi = (((((((((nl1lOi & (~ n1i100O)) & (~ n1i11OO)) & (~ n1i11Ol)) & (~ n1i11Oi)) & (~ n1i11lO)) & (~ n1i11ll)) & (~ n1i11li)) & (~ n1i11il)) & (~ n1i11ii)), n10OiOl = ((((n1i11ii | (~ n10Ol0l)) | (~ n10Ol0i)) | (~ n10Ol1i)) | (~ n10OiOO)), n10OiOO = ((((((((n1i100O | (~ n1i11OO)) | n1i11Ol) | n1i11Oi) | n1i11lO) | n1i11ll) | n1i11li) | n1i11il) | n1i11ii), n10Ol0i = ((((n1i100O | (~ n1i11ll)) | n1i11li) | n1i11il) | n1i11ii), n10Ol0l = (((n1i100O | (~ n1i11li)) | n1i11il) | n1i11ii), n10Ol0O = ((~ n1i11il) | n1i11ii), n10Ol1i = (((((((n1i100O | (~ n1i11Ol)) | n1i11Oi) | n1i11lO) | n1i11ll) | n1i11li) | n1i11il) | n1i11ii), n10Ol1l = ((((((n1i100O | (~ n1i11Oi)) | n1i11lO) | n1i11ll) | n1i11li) | n1i11il) | n1i11ii), n10Ol1O = (((((n1i100O | (~ n1i11lO)) | n1i11ll) | n1i11li) | n1i11il) | n1i11ii), n10Olii = (((((~ n10OO1i) | (~ n10OlOO)) | (~ n10OlOi)) | (~ n10Olll)) | n10Olil), n10Olil = ((((((((((n1i1i0O | n1i1i0l) & (~ n1i1i0i)) & (~ n1i1i1O)) & (~ n1i1i1l)) & (~ n1i10Ol)) & (~ n1i10ll)) & (~ n1i10il)) & (~ n1i100l)) & (~ n1i101O)) & (~ n1i101i)), n10OliO = ((((n1i101i | (~ n10OlOO)) | (~ n10OlOl)) | (~ n10Olll)) | (~ n10Olli)), n10Olli = (((((((((~ n1i1i0i) | n1i1i1O) | n1i1i1l) | n1i10Ol) | n1i10ll) | n1i10il) | n1i100l) | n1i101O) | n1i101i), n10Olll = ((((((((~ n1i1i1O) | n1i1i1l) | n1i10Ol) | n1i10ll) | n1i10il) | n1i100l) | n1i101O) | n1i101i), n10OllO = (((((((~ n1i1i1l) | n1i10Ol) | n1i10ll) | n1i10il) | n1i100l) | n1i101O) | n1i101i), n10OlOi = ((((((~ n1i10Ol) | n1i10ll) | n1i10il) | n1i100l) | n1i101O) | n1i101i), n10OlOl = (((((~ n1i10ll) | n1i10il) | n1i100l) | n1i101O) | n1i101i), n10OlOO = ((((~ n1i10il) | n1i100l) | n1i101O) | n1i101i), n10OO0i = ((((n1i1iii | (~ n10OOli)) | (~ n10OOiO)) | (~ n10OO0O)) | (~ n10OO0l)), n10OO0l = (((((((((~ n1i1l0O) | n1i1iOO) | (~ n1i1iOl)) | (~ n1i1iOi)) | (~ n1i1ilO)) | (~ n1i1ill)) | (~ n1i1ili)) | n1i1iil) | n1i1iii), n10OO0O = ((((((((~ n1i1l0O) | n1i1iOl) | (~ n1i1iOi)) | (~ n1i1ilO)) | (~ n1i1ill)) | (~ n1i1ili)) | n1i1iil) | n1i1iii), n10OO1i = ((~ n1i101O) | n1i101i), n10OO1l = (((((~ n10OOll) | (~ n10OOli)) | (~ n10OOil)) | (~ n10OO0O)) | n10OO1O), n10OO1O = ((((((((((~ nl1lOi) & n1i1l0O) & n1i1iOO) & n1i1iOl) & n1i1iOi) & n1i1ilO) & n1i1ill) & n1i1ili) & (~ n1i1iil)) & (~ n1i1iii)), n10OOii = (((((((~ n1i1l0O) | n1i1iOi) | (~ n1i1ilO)) | (~ n1i1ill)) | (~ n1i1ili)) | n1i1iil) | n1i1iii), n10OOil = ((((((~ n1i1l0O) | n1i1ilO) | (~ n1i1ill)) | (~ n1i1ili)) | n1i1iil) | n1i1iii), n10OOiO = (((((~ n1i1l0O) | n1i1ill) | (~ n1i1ili)) | n1i1iil) | n1i1iii), n10OOli = ((((~ n1i1l0O) | n1i1ili) | n1i1iil) | n1i1iii), n10OOll = ((~ n1i1iil) | n1i1iii), n10OOlO = (((((~ n1i110O) | (~ n1i110l)) | (~ n1i111O)) | (~ n1i111i)) | n10OOOi), n10OOOi = (((((((((((pmadwidth[0] & (~ nlilii)) | ((~ pmadwidth[0]) & (~ nlil0l))) & (~ n1i1O0i)) & (~ n1i1O1O)) & (~ n1i1O1l)) & (~ n1i1lOl)) & (~ n1i1lll)) & (~ n1i1lil)) & (~ n1i1l0l)) & (~ n1i1l1O)) & (~ n1i1l1i)), n10OOOl = ((((n1i1l1i | (~ n1i110l)) | (~ n1i110i)) | (~ n1i111i)) | (~ n10OOOO)), n10OOOO = (((((((((~ n1i1O0i) | n1i1O1O) | n1i1O1l) | n1i1lOl) | n1i1lll) | n1i1lil) | n1i1l0l) | n1i1l1O) | n1i1l1i), n11000i = ((((((((((~ ((~ comp_pat[0]) ^ nl01iOi)) & (~ ((~ comp_pat[1]) ^ nl01iOl))) & (~ ((~ comp_pat[2]) ^ nl01iOO))) & (~ ((~ comp_pat[3]) ^ nl01l1i))) & (~ ((~ comp_pat[4]) ^ nl01l1l))) & (~ ((~ comp_pat[5]) ^ nl01l1O))) & (~ ((~ comp_pat[6]) ^ nl01l0i))) & (~ ((~ comp_pat[7]) ^ nl01l0l))) & (~ ((~ comp_pat[8]) ^ nl01l0O))) & (~ ((~ comp_pat[9]) ^ nl01lii))), n11000l = ((comp_pat_porn & n1100ii) | n11000O), n11000O = ((((((((~ (comp_pat[8] ^ nl01l0O)) & (~ (comp_pat[9] ^ nl01lii))) & (~ (comp_pat[10] ^ nl01lil))) & (~ (comp_pat[11] ^ nl01liO))) & (~ (comp_pat[12] ^ nl01lli))) & (~ (comp_pat[13] ^ nl01lll))) & (~ (comp_pat[14] ^ nl01llO))) & (~ (comp_pat[15] ^ nl01lOi))), n11001i = ((((((((((~ ((~ comp_pat[0]) ^ nl01lil)) & (~ ((~ comp_pat[1]) ^ nl01liO))) & (~ ((~ comp_pat[2]) ^ nl01lli))) & (~ ((~ comp_pat[3]) ^ nl01lll))) & (~ ((~ comp_pat[4]) ^ nl01llO))) & (~ ((~ comp_pat[5]) ^ nl01lOi))) & (~ ((~ comp_pat[6]) ^ nl01lOl))) & (~ ((~ comp_pat[7]) ^ nl01lOO))) & (~ ((~ comp_pat[8]) ^ nl01O1i))) & (~ ((~ comp_pat[9]) ^ nl01O1l))), n11001l = ((comp_pat_porn & n11000i) | n11001O), n11001O = ((((((((((~ (comp_pat[0] ^ nl01iOi)) & (~ (comp_pat[1] ^ nl01iOl))) & (~ (comp_pat[2] ^ nl01iOO))) & (~ (comp_pat[3] ^ nl01l1i))) & (~ (comp_pat[4] ^ nl01l1l))) & (~ (comp_pat[5] ^ nl01l1O))) & (~ (comp_pat[6] ^ nl01l0i))) & (~ (comp_pat[7] ^ nl01l0l))) & (~ (comp_pat[8] ^ nl01l0O))) & (~ (comp_pat[9] ^ nl01lii))), n1100ii = ((((((((~ ((~ comp_pat[8]) ^ nl01l0O)) & (~ ((~ comp_pat[9]) ^ nl01lii))) & (~ ((~ comp_pat[10]) ^ nl01lil))) & (~ ((~ comp_pat[11]) ^ nl01liO))) & (~ ((~ comp_pat[12]) ^ nl01lli))) & (~ ((~ comp_pat[13]) ^ nl01lll))) & (~ ((~ comp_pat[14]) ^ nl01llO))) & (~ ((~ comp_pat[15]) ^ nl01lOi))), n1100il = ((comp_pat_porn & n1100li) | n1100iO), n1100iO = ((((((((~ (comp_pat[8] ^ nl01iOi)) & (~ (comp_pat[9] ^ nl01iOl))) & (~ (comp_pat[10] ^ nl01iOO))) & (~ (comp_pat[11] ^ nl01l1i))) & (~ (comp_pat[12] ^ nl01l1l))) & (~ (comp_pat[13] ^ nl01l1O))) & (~ (comp_pat[14] ^ nl01l0i))) & (~ (comp_pat[15] ^ nl01l0l))), n1100li = ((((((((~ ((~ comp_pat[8]) ^ nl01iOi)) & (~ ((~ comp_pat[9]) ^ nl01iOl))) & (~ ((~ comp_pat[10]) ^ nl01iOO))) & (~ ((~ comp_pat[11]) ^ nl01l1i))) & (~ ((~ comp_pat[12]) ^ nl01l1l))) & (~ ((~ comp_pat[13]) ^ nl01l1O))) & (~ ((~ comp_pat[14]) ^ nl01l0i))) & (~ ((~ comp_pat[15]) ^ nl01l0l))), n1100ll = ((comp_pat_porn & n1100Oi) | n1100lO), n1100lO = ((((((((~ (comp_pat[0] ^ nl01l0O)) & (~ (comp_pat[1] ^ nl01lii))) & (~ (comp_pat[2] ^ nl01lil))) & (~ (comp_pat[3] ^ nl01liO))) & (~ (comp_pat[4] ^ nl01lli))) & (~ (comp_pat[5] ^ nl01lll))) & (~ (comp_pat[6] ^ nl01llO))) & (~ (comp_pat[7] ^ nl01lOi))), n1100Oi = ((((((((~ ((~ comp_pat[0]) ^ nl01l0O)) & (~ ((~ comp_pat[1]) ^ nl01lii))) & (~ ((~ comp_pat[2]) ^ nl01lil))) & (~ ((~ comp_pat[3]) ^ nl01liO))) & (~ ((~ comp_pat[4]) ^ nl01lli))) & (~ ((~ comp_pat[5]) ^ nl01lll))) & (~ ((~ comp_pat[6]) ^ nl01llO))) & (~ ((~ comp_pat[7]) ^ nl01lOi))), n1100Ol = ((comp_pat_porn & n110i1i) | n1100OO), n1100OO = ((((((((~ (comp_pat[0] ^ nl01iOi)) & (~ (comp_pat[1] ^ nl01iOl))) & (~ (comp_pat[2] ^ nl01iOO))) & (~ (comp_pat[3] ^ nl01l1i))) & (~ (comp_pat[4] ^ nl01l1l))) & (~ (comp_pat[5] ^ nl01l1O))) & (~ (comp_pat[6] ^ nl01l0i))) & (~ (comp_pat[7] ^ nl01l0l))), n11010i = ((((((((((~ (comp_pat[10] ^ nl01i1O)) & (~ (comp_pat[11] ^ nl01i0i))) & (~ (comp_pat[12] ^ nl01i0l))) & (~ (comp_pat[13] ^ nl01i0O))) & (~ (comp_pat[14] ^ nl01iii))) & (~ (comp_pat[15] ^ nl01iil))) & (~ (comp_pat[16] ^ nl01iiO))) & (~ (comp_pat[17] ^ nl01ili))) & (~ (comp_pat[18] ^ nl01ill))) & (~ (comp_pat[19] ^ nl01ilO))), n11010l = ((((((((((~ ((~ comp_pat[10]) ^ nl01i1O)) & (~ ((~ comp_pat[11]) ^ nl01i0i))) & (~ ((~ comp_pat[12]) ^ nl01i0l))) & (~ ((~ comp_pat[13]) ^ nl01i0O))) & (~ ((~ comp_pat[14]) ^ nl01iii))) & (~ ((~ comp_pat[15]) ^ nl01iil))) & (~ ((~ comp_pat[16]) ^ nl01iiO))) & (~ ((~ comp_pat[17]) ^ nl01ili))) & (~ ((~ comp_pat[18]) ^ nl01ill))) & (~ ((~ comp_pat[19]) ^ nl01ilO))), n11010O = ((n1101Ol | nl1Ol0O) | (n1iiiOi & nl1OiOi)), n11011i = ((((((((((~ (comp_pat[0] ^ nl010il)) & (~ (comp_pat[1] ^ nl010iO))) & (~ (comp_pat[2] ^ nl010li))) & (~ (comp_pat[3] ^ nl010ll))) & (~ (comp_pat[4] ^ nl010lO))) & (~ (comp_pat[5] ^ nl010Oi))) & (~ (comp_pat[6] ^ nl010Ol))) & (~ (comp_pat[7] ^ nl010OO))) & (~ (comp_pat[8] ^ nl01i1i))) & (~ (comp_pat[9] ^ nl01i1l))), n11011l = ((((((((((~ ((~ comp_pat[0]) ^ nl010il)) & (~ ((~ comp_pat[1]) ^ nl010iO))) & (~ ((~ comp_pat[2]) ^ nl010li))) & (~ ((~ comp_pat[3]) ^ nl010ll))) & (~ ((~ comp_pat[4]) ^ nl010lO))) & (~ ((~ comp_pat[5]) ^ nl010Oi))) & (~ ((~ comp_pat[6]) ^ nl010Ol))) & (~ ((~ comp_pat[7]) ^ nl010OO))) & (~ ((~ comp_pat[8]) ^ nl01i1i))) & (~ ((~ comp_pat[9]) ^ nl01i1l))), n11011O = ((comp_pat_porn & n11010l) | n11010i), n1101ii = ((n11001l | nl1Ol0l) | (n1iiiOi & nl1OilO)), n1101il = ((comp_pat_porn & n1101li) | n1101iO), n1101iO = ((((((((((~ (comp_pat[10] ^ nl01lil)) & (~ (comp_pat[11] ^ nl01liO))) & (~ (comp_pat[12] ^ nl01lli))) & (~ (comp_pat[13] ^ nl01lll))) & (~ (comp_pat[14] ^ nl01llO))) & (~ (comp_pat[15] ^ nl01lOi))) & (~ (comp_pat[16] ^ nl01lOl))) & (~ (comp_pat[17] ^ nl01lOO))) & (~ (comp_pat[18] ^ nl01O1i))) & (~ (comp_pat[19] ^ nl01O1l))), n1101li = ((((((((((~ ((~ comp_pat[10]) ^ nl01lil)) & (~ ((~ comp_pat[11]) ^ nl01liO))) & (~ ((~ comp_pat[12]) ^ nl01lli))) & (~ ((~ comp_pat[13]) ^ nl01lll))) & (~ ((~ comp_pat[14]) ^ nl01llO))) & (~ ((~ comp_pat[15]) ^ nl01lOi))) & (~ ((~ comp_pat[16]) ^ nl01lOl))) & (~ ((~ comp_pat[17]) ^ nl01lOO))) & (~ ((~ comp_pat[18]) ^ nl01O1i))) & (~ ((~ comp_pat[19]) ^ nl01O1l))), n1101ll = ((comp_pat_porn & n1101Oi) | n1101lO), n1101lO = ((((((((((~ (comp_pat[10] ^ nl01iOi)) & (~ (comp_pat[11] ^ nl01iOl))) & (~ (comp_pat[12] ^ nl01iOO))) & (~ (comp_pat[13] ^ nl01l1i))) & (~ (comp_pat[14] ^ nl01l1l))) & (~ (comp_pat[15] ^ nl01l1O))) & (~ (comp_pat[16] ^ nl01l0i))) & (~ (comp_pat[17] ^ nl01l0l))) & (~ (comp_pat[18] ^ nl01l0O))) & (~ (comp_pat[19] ^ nl01lii))), n1101Oi = ((((((((((~ ((~ comp_pat[10]) ^ nl01iOi)) & (~ ((~ comp_pat[11]) ^ nl01iOl))) & (~ ((~ comp_pat[12]) ^ nl01iOO))) & (~ ((~ comp_pat[13]) ^ nl01l1i))) & (~ ((~ comp_pat[14]) ^ nl01l1l))) & (~ ((~ comp_pat[15]) ^ nl01l1O))) & (~ ((~ comp_pat[16]) ^ nl01l0i))) & (~ ((~ comp_pat[17]) ^ nl01l0l))) & (~ ((~ comp_pat[18]) ^ nl01l0O))) & (~ ((~ comp_pat[19]) ^ nl01lii))), n1101Ol = ((comp_pat_porn & n11001i) | n1101OO), n1101OO = ((((((((((~ (comp_pat[0] ^ nl01lil)) & (~ (comp_pat[1] ^ nl01liO))) & (~ (comp_pat[2] ^ nl01lli))) & (~ (comp_pat[3] ^ nl01lll))) & (~ (comp_pat[4] ^ nl01llO))) & (~ (comp_pat[5] ^ nl01lOi))) & (~ (comp_pat[6] ^ nl01lOl))) & (~ (comp_pat[7] ^ nl01lOO))) & (~ (comp_pat[8] ^ nl01O1i))) & (~ (comp_pat[9] ^ nl01O1l))), n110i0i = (((~ comp_pat_size[0]) & (~ comp_pat_size[1])) & comp_pat_size[2]), n110i0l = ((comp_pat_size[0] & comp_pat_size[1]) & (~ comp_pat_size[2])), n110i0O = (((~ comp_pat_size[0]) & comp_pat_size[1]) & (~ comp_pat_size[2])), n110i1i = ((((((((~ ((~ comp_pat[0]) ^ nl01iOi)) & (~ ((~ comp_pat[1]) ^ nl01iOl))) & (~ ((~ comp_pat[2]) ^ nl01iOO))) & (~ ((~ comp_pat[3]) ^ nl01l1i))) & (~ ((~ comp_pat[4]) ^ nl01l1l))) & (~ ((~ comp_pat[5]) ^ nl01l1O))) & (~ ((~ comp_pat[6]) ^ nl01l0i))) & (~ ((~ comp_pat[7]) ^ nl01l0l))), n110i1l = (((~ comp_pat_size[0]) & comp_pat_size[1]) & comp_pat_size[2]), n110i1O = ((comp_pat_size[0] & (~ comp_pat_size[1])) & comp_pat_size[2]), n110iii = ((comp_pat_size[0] & (~ comp_pat_size[1])) & (~ comp_pat_size[2])), n110iil = (((~ comp_pat_size[0]) & (~ comp_pat_size[1])) & (~ comp_pat_size[2])), n110iiO = (((((((((wire_nl0OiOl_o | (~ n110O1i)) | (~ n110lOO)) | (~ n110lOi)) | (~ n110lll)) | (~ n110liO)) | (~ n110lii)) | (~ n110l0l)) | (~ n110l1O)) | (~ n110l1i)), n110ili = (((((((((wire_nl0OiOl_o | (~ n110O1l)) | (~ n110lOO)) | (~ n110lOl)) | (~ n110lll)) | (~ n110lli)) | (~ n110lii)) | (~ n110l0O)) | (~ n110l1O)) | (~ n110l1l)), n110ill = (((((((((~ n110lOO) | (~ n110lOl)) | (~ n110lOi)) | (~ n110llO)) | (~ n110lii)) | (~ n110l0O)) | (~ n110l0l)) | (~ n110l0i)) | (~ n110iOl)), n110ilO = (((((((((~ n110lll) | (~ n110lli)) | (~ n110liO)) | (~ n110lil)) | (~ n110lii)) | (~ n110l0O)) | (~ n110l0l)) | (~ n110l0i)) | (~ n110iOl)), n110iOi = (((((~ n110l1O) | (~ n110l1l)) | (~ n110l1i)) | (~ n110iOl)) | n110iOO), n110iOl = (((((((((((((((((((wire_nl0OiOl_o | (~ n110O1l)) | (~ n110O1i)) | (~ ((((~ wire_nl0Ol1l_o) | wire_nl0Ol1i_o) | wire_nl0OiOO_o) | wire_nl0OiOl_o))) | (~ n110lOO)) | (~ n110lOl)) | (~ n110lOi)) | (~ n110llO)) | (~ n110lll)) | (~ n110lli)) | (~ n110liO)) | (~ n110lil)) | (~ n110lii)) | (~ n110l0O)) | (~ n110l0l)) | (~ n110l0i)) | (~ n110l1O)) | (~ n110l1l)) | (~ n110l1i)) | n110iOO), n110iOO = (((((((((((((((((((wire_nl0OO1O_o & (~ wire_nl0OO1l_o)) & (~ wire_nl0OO1i_o)) & (~ wire_nl0OlOO_o)) & (~ wire_nl0OlOl_o)) & (~ wire_nl0OlOi_o)) & (~ wire_nl0OllO_o)) & (~ wire_nl0Olll_o)) & (~ wire_nl0Olli_o)) & (~ wire_nl0OliO_o)) & (~ wire_nl0Olil_o)) & (~ wire_nl0Olii_o)) & (~ wire_nl0Ol0O_o)) & (~ wire_nl0Ol0l_o)) & (~ wire_nl0Ol0i_o)) & (~ wire_nl0Ol1O_o)) & (~ wire_nl0Ol1l_o)) & (~ wire_nl0Ol1i_o)) & (~ wire_nl0OiOO_o)) & (~ wire_nl0OiOl_o)), n110l0i = ((((((((((((((((~ wire_nl0OlOl_o) | wire_nl0OlOi_o) | wire_nl0OllO_o) | wire_nl0Olll_o) | wire_nl0Olli_o) | wire_nl0OliO_o) | wire_nl0Olil_o) | wire_nl0Olii_o) | wire_nl0Ol0O_o) | wire_nl0Ol0l_o) | wire_nl0Ol0i_o) | wire_nl0Ol1O_o) | wire_nl0Ol1l_o) | wire_nl0Ol1i_o) | wire_nl0OiOO_o) | wire_nl0OiOl_o), n110l0l = (((((((((((((((~ wire_nl0OlOi_o) | wire_nl0OllO_o) | wire_nl0Olll_o) | wire_nl0Olli_o) | wire_nl0OliO_o) | wire_nl0Olil_o) | wire_nl0Olii_o) | wire_nl0Ol0O_o) | wire_nl0Ol0l_o) | wire_nl0Ol0i_o) | wire_nl0Ol1O_o) | wire_nl0Ol1l_o) | wire_nl0Ol1i_o) | wire_nl0OiOO_o) | wire_nl0OiOl_o), n110l0O = ((((((((((((((~ wire_nl0OllO_o) | wire_nl0Olll_o) | wire_nl0Olli_o) | wire_nl0OliO_o) | wire_nl0Olil_o) | wire_nl0Olii_o) | wire_nl0Ol0O_o) | wire_nl0Ol0l_o) | wire_nl0Ol0i_o) | wire_nl0Ol1O_o) | wire_nl0Ol1l_o) | wire_nl0Ol1i_o) | wire_nl0OiOO_o) | wire_nl0OiOl_o), n110l1i = (((((((((((((((((((~ wire_nl0OO1l_o) | wire_nl0OO1i_o) | wire_nl0OlOO_o) | wire_nl0OlOl_o) | wire_nl0OlOi_o) | wire_nl0OllO_o) | wire_nl0Olll_o) | wire_nl0Olli_o) | wire_nl0OliO_o) | wire_nl0Olil_o) | wire_nl0Olii_o) | wire_nl0Ol0O_o) | wire_nl0Ol0l_o) | wire_nl0Ol0i_o) | wire_nl0Ol1O_o) | wire_nl0Ol1l_o) | wire_nl0Ol1i_o) | wire_nl0OiOO_o) | wire_nl0OiOl_o), n110l1l = ((((((((((((((((((~ wire_nl0OO1i_o) | wire_nl0OlOO_o) | wire_nl0OlOl_o) | wire_nl0OlOi_o) | wire_nl0OllO_o) | wire_nl0Olll_o) | wire_nl0Olli_o) | wire_nl0OliO_o) | wire_nl0Olil_o) | wire_nl0Olii_o) | wire_nl0Ol0O_o) | wire_nl0Ol0l_o) | wire_nl0Ol0i_o) | wire_nl0Ol1O_o) | wire_nl0Ol1l_o) | wire_nl0Ol1i_o) | wire_nl0OiOO_o) | wire_nl0OiOl_o), n110l1O = (((((((((((((((((~ wire_nl0OlOO_o) | wire_nl0OlOl_o) | wire_nl0OlOi_o) | wire_nl0OllO_o) | wire_nl0Olll_o) | wire_nl0Olli_o) | wire_nl0OliO_o) | wire_nl0Olil_o) | wire_nl0Olii_o) | wire_nl0Ol0O_o) | wire_nl0Ol0l_o) | wire_nl0Ol0i_o) | wire_nl0Ol1O_o) | wire_nl0Ol1l_o) | wire_nl0Ol1i_o) | wire_nl0OiOO_o) | wire_nl0OiOl_o), n110lii = (((((((((((((~ wire_nl0Olll_o) | wire_nl0Olli_o) | wire_nl0OliO_o) | wire_nl0Olil_o) | wire_nl0Olii_o) | wire_nl0Ol0O_o) | wire_nl0Ol0l_o) | wire_nl0Ol0i_o) | wire_nl0Ol1O_o) | wire_nl0Ol1l_o) | wire_nl0Ol1i_o) | wire_nl0OiOO_o) | wire_nl0OiOl_o), n110lil = ((((((((((((~ wire_nl0Olli_o) | wire_nl0OliO_o) | wire_nl0Olil_o) | wire_nl0Olii_o) | wire_nl0Ol0O_o) | wire_nl0Ol0l_o) | wire_nl0Ol0i_o) | wire_nl0Ol1O_o) | wire_nl0Ol1l_o) | wire_nl0Ol1i_o) | wire_nl0OiOO_o) | wire_nl0OiOl_o), n110liO = (((((((((((~ wire_nl0OliO_o) | wire_nl0Olil_o) | wire_nl0Olii_o) | wire_nl0Ol0O_o) | wire_nl0Ol0l_o) | wire_nl0Ol0i_o) | wire_nl0Ol1O_o) | wire_nl0Ol1l_o) | wire_nl0Ol1i_o) | wire_nl0OiOO_o) | wire_nl0OiOl_o), n110lli = ((((((((((~ wire_nl0Olil_o) | wire_nl0Olii_o) | wire_nl0Ol0O_o) | wire_nl0Ol0l_o) | wire_nl0Ol0i_o) | wire_nl0Ol1O_o) | wire_nl0Ol1l_o) | wire_nl0Ol1i_o) | wire_nl0OiOO_o) | wire_nl0OiOl_o), n110lll = (((((((((~ wire_nl0Olii_o) | wire_nl0Ol0O_o) | wire_nl0Ol0l_o) | wire_nl0Ol0i_o) | wire_nl0Ol1O_o) | wire_nl0Ol1l_o) | wire_nl0Ol1i_o) | wire_nl0OiOO_o) | wire_nl0OiOl_o), n110llO = ((((((((~ wire_nl0Ol0O_o) | wire_nl0Ol0l_o) | wire_nl0Ol0i_o) | wire_nl0Ol1O_o) | wire_nl0Ol1l_o) | wire_nl0Ol1i_o) | wire_nl0OiOO_o) | wire_nl0OiOl_o), n110lOi = (((((((~ wire_nl0Ol0l_o) | wire_nl0Ol0i_o) | wire_nl0Ol1O_o) | wire_nl0Ol1l_o) | wire_nl0Ol1i_o) | wire_nl0OiOO_o) | wire_nl0OiOl_o), n110lOl = ((((((~ wire_nl0Ol0i_o) | wire_nl0Ol1O_o) | wire_nl0Ol1l_o) | wire_nl0Ol1i_o) | wire_nl0OiOO_o) | wire_nl0OiOl_o), n110lOO = (((((~ wire_nl0Ol1O_o) | wire_nl0Ol1l_o) | wire_nl0Ol1i_o) | wire_nl0OiOO_o) | wire_nl0OiOl_o), n110O0i = (n11iOli & (((comp_pat_porn & n110Oil) | n110Oii) & ((comp_pat_porn & n110O0O) | n110O0l))), n110O0l = ((((((((~ (comp_pat[16] ^ nll0OOl)) & (~ (comp_pat[17] ^ nll0OOO))) & (~ (comp_pat[18] ^ nlli11i))) & (~ (comp_pat[19] ^ nlli11l))) & (~ (comp_pat[20] ^ nlli11O))) & (~ (comp_pat[21] ^ nlli10i))) & (~ (comp_pat[22] ^ nlli10l))) & (~ (comp_pat[23] ^ nlli10O))), n110O0O = ((((((((~ ((~ comp_pat[16]) ^ nll0OOl)) & (~ ((~ comp_pat[17]) ^ nll0OOO))) & (~ ((~ comp_pat[18]) ^ nlli11i))) & (~ ((~ comp_pat[19]) ^ nlli11l))) & (~ ((~ comp_pat[20]) ^ nlli11O))) & (~ ((~ comp_pat[21]) ^ nlli10i))) & (~ ((~ comp_pat[22]) ^ nlli10l))) & (~ ((~ comp_pat[23]) ^ nlli10O))), n110O1i = (((~ wire_nl0Ol1i_o) | wire_nl0OiOO_o) | wire_nl0OiOl_o), n110O1l = ((~ wire_nl0OiOO_o) | wire_nl0OiOl_o), n110O1O = (((((((((((((((n11iO0i | n11ilOl) | n11iliO) | n11il0i) | n11iiOl) | n11iiiO) | n11ii0i) | n11i0Ol) | n11i0iO) | n11i00i) | n11i1Ol) | n11i1iO) | n11i10i) | n110OOl) | n110OiO) | n110O0i), n110Oii = ((((((((~ (comp_pat[24] ^ nlli1ii)) & (~ (comp_pat[25] ^ nlli1il))) & (~ (comp_pat[26] ^ nlli1iO))) & (~ (comp_pat[27] ^ nlli1li))) & (~ (comp_pat[28] ^ nlli1ll))) & (~ (comp_pat[29] ^ nlli1lO))) & (~ (comp_pat[30] ^ nlli1Oi))) & (~ (comp_pat[31] ^ nlli1Ol))), n110Oil = ((((((((~ ((~ comp_pat[24]) ^ nlli1ii)) & (~ ((~ comp_pat[25]) ^ nlli1il))) & (~ ((~ comp_pat[26]) ^ nlli1iO))) & (~ ((~ comp_pat[27]) ^ nlli1li))) & (~ ((~ comp_pat[28]) ^ nlli1ll))) & (~ ((~ comp_pat[29]) ^ nlli1lO))) & (~ ((~ comp_pat[30]) ^ nlli1Oi))) & (~ ((~ comp_pat[31]) ^ nlli1Ol))), n110OiO = (n11iOOi & (((comp_pat_porn & n110OOi) | n110OlO) & ((comp_pat_porn & n110Oll) | n110Oli))), n110Oli = ((((((((~ (comp_pat[16] ^ nll0OiO)) & (~ (comp_pat[17] ^ nll0OOl))) & (~ (comp_pat[18] ^ nll0OOO))) & (~ (comp_pat[19] ^ nlli11i))) & (~ (comp_pat[20] ^ nlli11l))) & (~ (comp_pat[21] ^ nlli11O))) & (~ (comp_pat[22] ^ nlli10i))) & (~ (comp_pat[23] ^ nlli10l))), n110Oll = ((((((((~ ((~ comp_pat[16]) ^ nll0OiO)) & (~ ((~ comp_pat[17]) ^ nll0OOl))) & (~ ((~ comp_pat[18]) ^ nll0OOO))) & (~ ((~ comp_pat[19]) ^ nlli11i))) & (~ ((~ comp_pat[20]) ^ nlli11l))) & (~ ((~ comp_pat[21]) ^ nlli11O))) & (~ ((~ comp_pat[22]) ^ nlli10i))) & (~ ((~ comp_pat[23]) ^ nlli10l))), n110OlO = ((((((((~ (comp_pat[24] ^ nlli10O)) & (~ (comp_pat[25] ^ nlli1ii))) & (~ (comp_pat[26] ^ nlli1il))) & (~ (comp_pat[27] ^ nlli1iO))) & (~ (comp_pat[28] ^ nlli1li))) & (~ (comp_pat[29] ^ nlli1ll))) & (~ (comp_pat[30] ^ nlli1lO))) & (~ (comp_pat[31] ^ nlli1Oi))), n110OOi = ((((((((~ ((~ comp_pat[24]) ^ nlli10O)) & (~ ((~ comp_pat[25]) ^ nlli1ii))) & (~ ((~ comp_pat[26]) ^ nlli1il))) & (~ ((~ comp_pat[27]) ^ nlli1iO))) & (~ ((~ comp_pat[28]) ^ nlli1li))) & (~ ((~ comp_pat[29]) ^ nlli1ll))) & (~ ((~ comp_pat[30]) ^ nlli1lO))) & (~ ((~ comp_pat[31]) ^ nlli1Oi))), n110OOl = (n11l11i & (((comp_pat_porn & n11i11O) | n11i11l) & ((comp_pat_porn & n11i11i) | n110OOO))), n110OOO = ((((((((~ (comp_pat[16] ^ nll0Oil)) & (~ (comp_pat[17] ^ nll0OiO))) & (~ (comp_pat[18] ^ nll0OOl))) & (~ (comp_pat[19] ^ nll0OOO))) & (~ (comp_pat[20] ^ nlli11i))) & (~ (comp_pat[21] ^ nlli11l))) & (~ (comp_pat[22] ^ nlli11O))) & (~ (comp_pat[23] ^ nlli10i))), n11100i = (((((((((((((((nlli1Ol | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | nlli11O) | nlli11l) | nlli11i) | nll0OOO) | nll0OOl), n11100l = (((((((((((((((nlli01O | nlli01l) | nlli01i) | nlli1OO) | nlli1Ol) | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | nlli11O), n11100O = ((pmadwidth[0] & (~ n1110il)) | ((~ pmadwidth[0]) & (~ n1110ii))), n11101i = (pmadwidth[0] & (~ n11101l)), n11101l = ((((((((((((((((nlli01O | nlli01l) | nlli01i) | nlli1OO) | nlli1Ol) | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | nlli11O) | nlli11l), n11101O = ((pmadwidth[0] & (~ n11100l)) | ((~ pmadwidth[0]) & (~ n11100i))), n1110ii = ((((((((((((((nlli1Ol | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | nlli11O) | nlli11l) | nlli11i) | nll0OOO), n1110il = ((((((((((((((nlli01O | nlli01l) | nlli01i) | nlli1OO) | nlli1Ol) | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i), n1110iO = ((pmadwidth[0] & (~ n1110ll)) | ((~ pmadwidth[0]) & (~ n1110li))), n1110li = (((((((((((((nlli1Ol | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | nlli11O) | nlli11l) | nlli11i), n1110ll = (((((((((((((nlli01O | nlli01l) | nlli01i) | nlli1OO) | nlli1Ol) | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l), n1110lO = ((pmadwidth[0] & (~ n1110Ol)) | ((~ pmadwidth[0]) & (~ n1110Oi))), n1110Oi = ((((((((((((nlli1Ol | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | nlli11O) | nlli11l), n1110Ol = ((((((((((((nlli01O | nlli01l) | nlli01i) | nlli1OO) | nlli1Ol) | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O), n1110OO = ((pmadwidth[0] & (~ n111i1l)) | ((~ pmadwidth[0]) & (~ n111i1i))), n11110i = ((((((nlli10l | nlli10i) | nlli11O) | nlli11l) | nlli11i) | nll0OOO) | nll0OOl), n11110l = (((((nlli10i | nlli11O) | nlli11l) | nlli11i) | nll0OOO) | nll0OOl), n11110O = ((((nlli11O | nlli11l) | nlli11i) | nll0OOO) | nll0OOl), n11111i = (((((((((nlli1il | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | nlli11O) | nlli11l) | nlli11i) | nll0OOO) | nll0OOl), n11111l = ((((((((nlli1ii | nlli10O) | nlli10l) | nlli10i) | nlli11O) | nlli11l) | nlli11i) | nll0OOO) | nll0OOl), n11111O = (((((((nlli10O | nlli10l) | nlli10i) | nlli11O) | nlli11l) | nlli11i) | nll0OOO) | nll0OOl), n1111ii = (((nlli11l | nlli11i) | nll0OOO) | nll0OOl), n1111il = ((nlli11i | nll0OOO) | nll0OOl), n1111iO = (nll0OOO | nll0OOl), n1111li = (pmadwidth[0] & (~ n1111ll)), n1111ll = (((((((((((((((((((nlli01O | nlli01l) | nlli01i) | nlli1OO) | nlli1Ol) | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | nlli11O) | nlli11l) | nlli11i) | nll0OOO) | nll0OOl), n1111lO = (pmadwidth[0] & (~ n1111Oi)), n1111Oi = ((((((((((((((((((nlli01O | nlli01l) | nlli01i) | nlli1OO) | nlli1Ol) | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | nlli11O) | nlli11l) | nlli11i) | nll0OOO), n1111Ol = (pmadwidth[0] & (~ n1111OO)), n1111OO = (((((((((((((((((nlli01O | nlli01l) | nlli01i) | nlli1OO) | nlli1Ol) | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | nlli11O) | nlli11l) | nlli11i), n111i0i = ((((((((((nlli1Ol | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i), n111i0l = ((((((((((nlli01O | nlli01l) | nlli01i) | nlli1OO) | nlli1Ol) | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il), n111i0O = ((pmadwidth[0] & (~ n111iil)) | ((~ pmadwidth[0]) & (~ n111iii))), n111i1i = (((((((((((nlli1Ol | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | nlli11O), n111i1l = (((((((((((nlli01O | nlli01l) | nlli01i) | nlli1OO) | nlli1Ol) | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii), n111i1O = ((pmadwidth[0] & (~ n111i0l)) | ((~ pmadwidth[0]) & (~ n111i0i))), n111iii = (((((((((nlli1Ol | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l), n111iil = (((((((((nlli01O | nlli01l) | nlli01i) | nlli1OO) | nlli1Ol) | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO), n111iiO = ((pmadwidth[0] & (~ n111ill)) | ((~ pmadwidth[0]) & (~ n111ili))), n111ili = ((((((((nlli1Ol | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O), n111ill = ((((((((nlli01O | nlli01l) | nlli01i) | nlli1OO) | nlli1Ol) | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li), n111ilO = ((pmadwidth[0] & (~ n111iOl)) | ((~ pmadwidth[0]) & (~ n111iOi))), n111iOi = (((((((nlli1Ol | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii), n111iOl = (((((((nlli01O | nlli01l) | nlli01i) | nlli1OO) | nlli1Ol) | nlli1Oi) | nlli1lO) | nlli1ll), n111iOO = ((pmadwidth[0] & (~ n111l1l)) | ((~ pmadwidth[0]) & (~ n111l1i))), n111l0i = (((((nlli1Ol | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO), n111l0l = (((((nlli01O | nlli01l) | nlli01i) | nlli1OO) | nlli1Ol) | nlli1Oi), n111l0O = ((pmadwidth[0] & (~ n111lil)) | ((~ pmadwidth[0]) & (~ n111lii))), n111l1i = ((((((nlli1Ol | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il), n111l1l = ((((((nlli01O | nlli01l) | nlli01i) | nlli1OO) | nlli1Ol) | nlli1Oi) | nlli1lO), n111l1O = ((pmadwidth[0] & (~ n111l0l)) | ((~ pmadwidth[0]) & (~ n111l0i))), n111lii = ((((nlli1Ol | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li), n111lil = ((((nlli01O | nlli01l) | nlli01i) | nlli1OO) | nlli1Ol), n111liO = ((pmadwidth[0] & (~ (((nlli01O | nlli01l) | nlli01i) | nlli1OO))) | ((~ pmadwidth[0]) & (~ (((nlli1Ol | nlli1Oi) | nlli1lO) | nlli1ll)))), n111lli = ((pmadwidth[0] & (~ ((nlli01O | nlli01l) | nlli01i))) | ((~ pmadwidth[0]) & (~ ((nlli1Ol | nlli1Oi) | nlli1lO)))), n111lll = ((pmadwidth[0] & (~ (nlli01O | nlli01l))) | ((~ pmadwidth[0]) & (~ (nlli1Ol | nlli1Oi)))), n111llO = ((~ pmadwidth[0]) & pmadwidth[1]), n111lOi = (((((~ (nl0101O ^ nl011Oi)) & (~ (nl0100i ^ nl011Ol))) & (~ (nl0100l ^ nl011OO))) & (~ (nl0100O ^ nl0101i))) & (~ (nl010ii ^ nl0101l))), n111lOl = (comp_pat_size[0] & autobytealign_dis), n111lOO = ((~ comp_pat_size[0]) & autobytealign_dis), n111O0i = (n110i1O | n110i1l), n111O0l = (n110iil | n110i0O), n111O0O = ((((((((~ (comp_pat[0] ^ nl010il)) & (~ (comp_pat[1] ^ nl010iO))) & (~ (comp_pat[2] ^ nl010li))) & (~ (comp_pat[3] ^ nl010ll))) & (~ (comp_pat[4] ^ nl010lO))) & (~ (comp_pat[5] ^ nl010Oi))) & (~ (comp_pat[6] ^ nl010Ol))) & (~ (comp_pat[7] ^ nl010OO))), n111O1i = ((((nl010ii & nl0100O) & nl0100l) & nl0100i) & nl0101O), n111O1l = (wa_6g_en & autobytealign_dis), n111O1O = (wire_nll1lOi_dataout & ((~ autobytealign_dis) & n1iiilO)), n111Oii = (((((((~ (comp_pat[0] ^ nl010il)) & (~ (comp_pat[1] ^ nl010iO))) & (~ (comp_pat[2] ^ nl010li))) & (~ (comp_pat[3] ^ nl010ll))) & (~ (comp_pat[4] ^ nl010lO))) & (~ (comp_pat[5] ^ nl010Oi))) & (~ (comp_pat[6] ^ nl010Ol))), n111Oil = (((((((~ ((~ comp_pat[0]) ^ nl010il)) & (~ ((~ comp_pat[1]) ^ nl010iO))) & (~ ((~ comp_pat[2]) ^ nl010li))) & (~ ((~ comp_pat[3]) ^ nl010ll))) & (~ ((~ comp_pat[4]) ^ nl010lO))) & (~ ((~ comp_pat[5]) ^ nl010Oi))) & (~ ((~ comp_pat[6]) ^ nl010Ol))), n111OiO = ((((((((~ (comp_pat[8] ^ nl01i1i)) & (~ (comp_pat[9] ^ nl01i1l))) & (~ (comp_pat[10] ^ nl01i1O))) & (~ (comp_pat[11] ^ nl01i0i))) & (~ (comp_pat[12] ^ nl01i0l))) & (~ (comp_pat[13] ^ nl01i0O))) & (~ (comp_pat[14] ^ nl01iii))) & (~ (comp_pat[15] ^ nl01iil))), n111Oli = ((((((((((~ (comp_pat[0] ^ nl01i1O)) & (~ (comp_pat[1] ^ nl01i0i))) & (~ (comp_pat[2] ^ nl01i0l))) & (~ (comp_pat[3] ^ nl01i0O))) & (~ (comp_pat[4] ^ nl01iii))) & (~ (comp_pat[5] ^ nl01iil))) & (~ (comp_pat[6] ^ nl01iiO))) & (~ (comp_pat[7] ^ nl01ili))) & (~ (comp_pat[8] ^ nl01ill))) & (~ (comp_pat[9] ^ nl01ilO))), n111Oll = ((((((((((~ ((~ comp_pat[0]) ^ nl01i1O)) & (~ ((~ comp_pat[1]) ^ nl01i0i))) & (~ ((~ comp_pat[2]) ^ nl01i0l))) & (~ ((~ comp_pat[3]) ^ nl01i0O))) & (~ ((~ comp_pat[4]) ^ nl01iii))) & (~ ((~ comp_pat[5]) ^ nl01iil))) & (~ ((~ comp_pat[6]) ^ nl01iiO))) & (~ ((~ comp_pat[7]) ^ nl01ili))) & (~ ((~ comp_pat[8]) ^ nl01ill))) & (~ ((~ comp_pat[9]) ^ nl01ilO))), n111OlO = ((((((((~ (comp_pat[0] ^ nl01i1i)) & (~ (comp_pat[1] ^ nl01i1l))) & (~ (comp_pat[2] ^ nl01i1O))) & (~ (comp_pat[3] ^ nl01i0i))) & (~ (comp_pat[4] ^ nl01i0l))) & (~ (comp_pat[5] ^ nl01i0O))) & (~ (comp_pat[6] ^ nl01iii))) & (~ (comp_pat[7] ^ nl01iil))), n111OOi = (((((((~ (comp_pat[0] ^ nl01i1O)) & (~ (comp_pat[1] ^ nl01i0i))) & (~ (comp_pat[2] ^ nl01i0l))) & (~ (comp_pat[3] ^ nl01i0O))) & (~ (comp_pat[4] ^ nl01iii))) & (~ (comp_pat[5] ^ nl01iil))) & (~ (comp_pat[6] ^ nl01iiO))), n111OOl = (((((((~ ((~ comp_pat[0]) ^ nl01i1O)) & (~ ((~ comp_pat[1]) ^ nl01i0i))) & (~ ((~ comp_pat[2]) ^ nl01i0l))) & (~ ((~ comp_pat[3]) ^ nl01i0O))) & (~ ((~ comp_pat[4]) ^ nl01iii))) & (~ ((~ comp_pat[5]) ^ nl01iil))) & (~ ((~ comp_pat[6]) ^ nl01iiO))), n111OOO = ((comp_pat_porn & n11011l) | n11011i), n11i00i = (n11l1Oi & (((comp_pat_porn & n11i0il) | n11i0ii) & ((comp_pat_porn & n11i00O) | n11i00l))), n11i00l = ((((((((~ (comp_pat[16] ^ nll0O0i)) & (~ (comp_pat[17] ^ nll0O0l))) & (~ (comp_pat[18] ^ nll0O0O))) & (~ (comp_pat[19] ^ nll0Oii))) & (~ (comp_pat[20] ^ nll0Oil))) & (~ (comp_pat[21] ^ nll0OiO))) & (~ (comp_pat[22] ^ nll0OOl))) & (~ (comp_pat[23] ^ nll0OOO))), n11i00O = ((((((((~ ((~ comp_pat[16]) ^ nll0O0i)) & (~ ((~ comp_pat[17]) ^ nll0O0l))) & (~ ((~ comp_pat[18]) ^ nll0O0O))) & (~ ((~ comp_pat[19]) ^ nll0Oii))) & (~ ((~ comp_pat[20]) ^ nll0Oil))) & (~ ((~ comp_pat[21]) ^ nll0OiO))) & (~ ((~ comp_pat[22]) ^ nll0OOl))) & (~ ((~ comp_pat[23]) ^ nll0OOO))), n11i01i = ((((((((~ ((~ comp_pat[16]) ^ nll0O0l)) & (~ ((~ comp_pat[17]) ^ nll0O0O))) & (~ ((~ comp_pat[18]) ^ nll0Oii))) & (~ ((~ comp_pat[19]) ^ nll0Oil))) & (~ ((~ comp_pat[20]) ^ nll0OiO))) & (~ ((~ comp_pat[21]) ^ nll0OOl))) & (~ ((~ comp_pat[22]) ^ nll0OOO))) & (~ ((~ comp_pat[23]) ^ nlli11i))), n11i01l = ((((((((~ (comp_pat[24] ^ nlli11l)) & (~ (comp_pat[25] ^ nlli11O))) & (~ (comp_pat[26] ^ nlli10i))) & (~ (comp_pat[27] ^ nlli10l))) & (~ (comp_pat[28] ^ nlli10O))) & (~ (comp_pat[29] ^ nlli1ii))) & (~ (comp_pat[30] ^ nlli1il))) & (~ (comp_pat[31] ^ nlli1iO))), n11i01O = ((((((((~ ((~ comp_pat[24]) ^ nlli11l)) & (~ ((~ comp_pat[25]) ^ nlli11O))) & (~ ((~ comp_pat[26]) ^ nlli10i))) & (~ ((~ comp_pat[27]) ^ nlli10l))) & (~ ((~ comp_pat[28]) ^ nlli10O))) & (~ ((~ comp_pat[29]) ^ nlli1ii))) & (~ ((~ comp_pat[30]) ^ nlli1il))) & (~ ((~ comp_pat[31]) ^ nlli1iO))), n11i0ii = ((((((((~ (comp_pat[24] ^ nlli11i)) & (~ (comp_pat[25] ^ nlli11l))) & (~ (comp_pat[26] ^ nlli11O))) & (~ (comp_pat[27] ^ nlli10i))) & (~ (comp_pat[28] ^ nlli10l))) & (~ (comp_pat[29] ^ nlli10O))) & (~ (comp_pat[30] ^ nlli1ii))) & (~ (comp_pat[31] ^ nlli1il))), n11i0il = ((((((((~ ((~ comp_pat[24]) ^ nlli11i)) & (~ ((~ comp_pat[25]) ^ nlli11l))) & (~ ((~ comp_pat[26]) ^ nlli11O))) & (~ ((~ comp_pat[27]) ^ nlli10i))) & (~ ((~ comp_pat[28]) ^ nlli10l))) & (~ ((~ comp_pat[29]) ^ nlli10O))) & (~ ((~ comp_pat[30]) ^ nlli1ii))) & (~ ((~ comp_pat[31]) ^ nlli1il))), n11i0iO = (n11l01i & (((comp_pat_porn & n11i0Oi) | n11i0lO) & ((comp_pat_porn & n11i0ll) | n11i0li))), n11i0li = ((((((((~ (comp_pat[16] ^ nll0O1O)) & (~ (comp_pat[17] ^ nll0O0i))) & (~ (comp_pat[18] ^ nll0O0l))) & (~ (comp_pat[19] ^ nll0O0O))) & (~ (comp_pat[20] ^ nll0Oii))) & (~ (comp_pat[21] ^ nll0Oil))) & (~ (comp_pat[22] ^ nll0OiO))) & (~ (comp_pat[23] ^ nll0OOl))), n11i0ll = ((((((((~ ((~ comp_pat[16]) ^ nll0O1O)) & (~ ((~ comp_pat[17]) ^ nll0O0i))) & (~ ((~ comp_pat[18]) ^ nll0O0l))) & (~ ((~ comp_pat[19]) ^ nll0O0O))) & (~ ((~ comp_pat[20]) ^ nll0Oii))) & (~ ((~ comp_pat[21]) ^ nll0Oil))) & (~ ((~ comp_pat[22]) ^ nll0OiO))) & (~ ((~ comp_pat[23]) ^ nll0OOl))), n11i0lO = ((((((((~ (comp_pat[24] ^ nll0OOO)) & (~ (comp_pat[25] ^ nlli11i))) & (~ (comp_pat[26] ^ nlli11l))) & (~ (comp_pat[27] ^ nlli11O))) & (~ (comp_pat[28] ^ nlli10i))) & (~ (comp_pat[29] ^ nlli10l))) & (~ (comp_pat[30] ^ nlli10O))) & (~ (comp_pat[31] ^ nlli1ii))), n11i0Oi = ((((((((~ ((~ comp_pat[24]) ^ nll0OOO)) & (~ ((~ comp_pat[25]) ^ nlli11i))) & (~ ((~ comp_pat[26]) ^ nlli11l))) & (~ ((~ comp_pat[27]) ^ nlli11O))) & (~ ((~ comp_pat[28]) ^ nlli10i))) & (~ ((~ comp_pat[29]) ^ nlli10l))) & (~ ((~ comp_pat[30]) ^ nlli10O))) & (~ ((~ comp_pat[31]) ^ nlli1ii))), n11i0Ol = (n11l00i & (((comp_pat_porn & n11ii1O) | n11ii1l) & ((comp_pat_porn & n11ii1i) | n11i0OO))), n11i0OO = ((((((((~ (comp_pat[16] ^ nll0O1l)) & (~ (comp_pat[17] ^ nll0O1O))) & (~ (comp_pat[18] ^ nll0O0i))) & (~ (comp_pat[19] ^ nll0O0l))) & (~ (comp_pat[20] ^ nll0O0O))) & (~ (comp_pat[21] ^ nll0Oii))) & (~ (comp_pat[22] ^ nll0Oil))) & (~ (comp_pat[23] ^ nll0OiO))), n11i10i = (n11l10i & (((comp_pat_porn & n11i1il) | n11i1ii) & ((comp_pat_porn & n11i10O) | n11i10l))), n11i10l = ((((((((~ (comp_pat[16] ^ nll0Oii)) & (~ (comp_pat[17] ^ nll0Oil))) & (~ (comp_pat[18] ^ nll0OiO))) & (~ (comp_pat[19] ^ nll0OOl))) & (~ (comp_pat[20] ^ nll0OOO))) & (~ (comp_pat[21] ^ nlli11i))) & (~ (comp_pat[22] ^ nlli11l))) & (~ (comp_pat[23] ^ nlli11O))), n11i10O = ((((((((~ ((~ comp_pat[16]) ^ nll0Oii)) & (~ ((~ comp_pat[17]) ^ nll0Oil))) & (~ ((~ comp_pat[18]) ^ nll0OiO))) & (~ ((~ comp_pat[19]) ^ nll0OOl))) & (~ ((~ comp_pat[20]) ^ nll0OOO))) & (~ ((~ comp_pat[21]) ^ nlli11i))) & (~ ((~ comp_pat[22]) ^ nlli11l))) & (~ ((~ comp_pat[23]) ^ nlli11O))), n11i11i = ((((((((~ ((~ comp_pat[16]) ^ nll0Oil)) & (~ ((~ comp_pat[17]) ^ nll0OiO))) & (~ ((~ comp_pat[18]) ^ nll0OOl))) & (~ ((~ comp_pat[19]) ^ nll0OOO))) & (~ ((~ comp_pat[20]) ^ nlli11i))) & (~ ((~ comp_pat[21]) ^ nlli11l))) & (~ ((~ comp_pat[22]) ^ nlli11O))) & (~ ((~ comp_pat[23]) ^ nlli10i))), n11i11l = ((((((((~ (comp_pat[24] ^ nlli10l)) & (~ (comp_pat[25] ^ nlli10O))) & (~ (comp_pat[26] ^ nlli1ii))) & (~ (comp_pat[27] ^ nlli1il))) & (~ (comp_pat[28] ^ nlli1iO))) & (~ (comp_pat[29] ^ nlli1li))) & (~ (comp_pat[30] ^ nlli1ll))) & (~ (comp_pat[31] ^ nlli1lO))), n11i11O = ((((((((~ ((~ comp_pat[24]) ^ nlli10l)) & (~ ((~ comp_pat[25]) ^ nlli10O))) & (~ ((~ comp_pat[26]) ^ nlli1ii))) & (~ ((~ comp_pat[27]) ^ nlli1il))) & (~ ((~ comp_pat[28]) ^ nlli1iO))) & (~ ((~ comp_pat[29]) ^ nlli1li))) & (~ ((~ comp_pat[30]) ^ nlli1ll))) & (~ ((~ comp_pat[31]) ^ nlli1lO))), n11i1ii = ((((((((~ (comp_pat[24] ^ nlli10i)) & (~ (comp_pat[25] ^ nlli10l))) & (~ (comp_pat[26] ^ nlli10O))) & (~ (comp_pat[27] ^ nlli1ii))) & (~ (comp_pat[28] ^ nlli1il))) & (~ (comp_pat[29] ^ nlli1iO))) & (~ (comp_pat[30] ^ nlli1li))) & (~ (comp_pat[31] ^ nlli1ll))), n11i1il = ((((((((~ ((~ comp_pat[24]) ^ nlli10i)) & (~ ((~ comp_pat[25]) ^ nlli10l))) & (~ ((~ comp_pat[26]) ^ nlli10O))) & (~ ((~ comp_pat[27]) ^ nlli1ii))) & (~ ((~ comp_pat[28]) ^ nlli1il))) & (~ ((~ comp_pat[29]) ^ nlli1iO))) & (~ ((~ comp_pat[30]) ^ nlli1li))) & (~ ((~ comp_pat[31]) ^ nlli1ll))), n11i1iO = (n11l1ii & (((comp_pat_porn & n11i1Oi) | n11i1lO) & ((comp_pat_porn & n11i1ll) | n11i1li))), n11i1li = ((((((((~ (comp_pat[16] ^ nll0O0O)) & (~ (comp_pat[17] ^ nll0Oii))) & (~ (comp_pat[18] ^ nll0Oil))) & (~ (comp_pat[19] ^ nll0OiO))) & (~ (comp_pat[20] ^ nll0OOl))) & (~ (comp_pat[21] ^ nll0OOO))) & (~ (comp_pat[22] ^ nlli11i))) & (~ (comp_pat[23] ^ nlli11l))), n11i1ll = ((((((((~ ((~ comp_pat[16]) ^ nll0O0O)) & (~ ((~ comp_pat[17]) ^ nll0Oii))) & (~ ((~ comp_pat[18]) ^ nll0Oil))) & (~ ((~ comp_pat[19]) ^ nll0OiO))) & (~ ((~ comp_pat[20]) ^ nll0OOl))) & (~ ((~ comp_pat[21]) ^ nll0OOO))) & (~ ((~ comp_pat[22]) ^ nlli11i))) & (~ ((~ comp_pat[23]) ^ nlli11l))), n11i1lO = ((((((((~ (comp_pat[24] ^ nlli11O)) & (~ (comp_pat[25] ^ nlli10i))) & (~ (comp_pat[26] ^ nlli10l))) & (~ (comp_pat[27] ^ nlli10O))) & (~ (comp_pat[28] ^ nlli1ii))) & (~ (comp_pat[29] ^ nlli1il))) & (~ (comp_pat[30] ^ nlli1iO))) & (~ (comp_pat[31] ^ nlli1li))), n11i1Oi = ((((((((~ ((~ comp_pat[24]) ^ nlli11O)) & (~ ((~ comp_pat[25]) ^ nlli10i))) & (~ ((~ comp_pat[26]) ^ nlli10l))) & (~ ((~ comp_pat[27]) ^ nlli10O))) & (~ ((~ comp_pat[28]) ^ nlli1ii))) & (~ ((~ comp_pat[29]) ^ nlli1il))) & (~ ((~ comp_pat[30]) ^ nlli1iO))) & (~ ((~ comp_pat[31]) ^ nlli1li))), n11i1Ol = (n11l1li & (((comp_pat_porn & n11i01O) | n11i01l) & ((comp_pat_porn & n11i01i) | n11i1OO))), n11i1OO = ((((((((~ (comp_pat[16] ^ nll0O0l)) & (~ (comp_pat[17] ^ nll0O0O))) & (~ (comp_pat[18] ^ nll0Oii))) & (~ (comp_pat[19] ^ nll0Oil))) & (~ (comp_pat[20] ^ nll0OiO))) & (~ (comp_pat[21] ^ nll0OOl))) & (~ (comp_pat[22] ^ nll0OOO))) & (~ (comp_pat[23] ^ nlli11i))), n11ii0i = (n11l0ii & (((comp_pat_porn & n11iiil) | n11iiii) & ((comp_pat_porn & n11ii0O) | n11ii0l))), n11ii0l = ((((((((~ (comp_pat[16] ^ nll0O1i)) & (~ (comp_pat[17] ^ nll0O1l))) & (~ (comp_pat[18] ^ nll0O1O))) & (~ (comp_pat[19] ^ nll0O0i))) & (~ (comp_pat[20] ^ nll0O0l))) & (~ (comp_pat[21] ^ nll0O0O))) & (~ (comp_pat[22] ^ nll0Oii))) & (~ (comp_pat[23] ^ nll0Oil))), n11ii0O = ((((((((~ ((~ comp_pat[16]) ^ nll0O1i)) & (~ ((~ comp_pat[17]) ^ nll0O1l))) & (~ ((~ comp_pat[18]) ^ nll0O1O))) & (~ ((~ comp_pat[19]) ^ nll0O0i))) & (~ ((~ comp_pat[20]) ^ nll0O0l))) & (~ ((~ comp_pat[21]) ^ nll0O0O))) & (~ ((~ comp_pat[22]) ^ nll0Oii))) & (~ ((~ comp_pat[23]) ^ nll0Oil))), n11ii1i = ((((((((~ ((~ comp_pat[16]) ^ nll0O1l)) & (~ ((~ comp_pat[17]) ^ nll0O1O))) & (~ ((~ comp_pat[18]) ^ nll0O0i))) & (~ ((~ comp_pat[19]) ^ nll0O0l))) & (~ ((~ comp_pat[20]) ^ nll0O0O))) & (~ ((~ comp_pat[21]) ^ nll0Oii))) & (~ ((~ comp_pat[22]) ^ nll0Oil))) & (~ ((~ comp_pat[23]) ^ nll0OiO))), n11ii1l = ((((((((~ (comp_pat[24] ^ nll0OOl)) & (~ (comp_pat[25] ^ nll0OOO))) & (~ (comp_pat[26] ^ nlli11i))) & (~ (comp_pat[27] ^ nlli11l))) & (~ (comp_pat[28] ^ nlli11O))) & (~ (comp_pat[29] ^ nlli10i))) & (~ (comp_pat[30] ^ nlli10l))) & (~ (comp_pat[31] ^ nlli10O))), n11ii1O = ((((((((~ ((~ comp_pat[24]) ^ nll0OOl)) & (~ ((~ comp_pat[25]) ^ nll0OOO))) & (~ ((~ comp_pat[26]) ^ nlli11i))) & (~ ((~ comp_pat[27]) ^ nlli11l))) & (~ ((~ comp_pat[28]) ^ nlli11O))) & (~ ((~ comp_pat[29]) ^ nlli10i))) & (~ ((~ comp_pat[30]) ^ nlli10l))) & (~ ((~ comp_pat[31]) ^ nlli10O))), n11iiii = ((((((((~ (comp_pat[24] ^ nll0OiO)) & (~ (comp_pat[25] ^ nll0OOl))) & (~ (comp_pat[26] ^ nll0OOO))) & (~ (comp_pat[27] ^ nlli11i))) & (~ (comp_pat[28] ^ nlli11l))) & (~ (comp_pat[29] ^ nlli11O))) & (~ (comp_pat[30] ^ nlli10i))) & (~ (comp_pat[31] ^ nlli10l))), n11iiil = ((((((((~ ((~ comp_pat[24]) ^ nll0OiO)) & (~ ((~ comp_pat[25]) ^ nll0OOl))) & (~ ((~ comp_pat[26]) ^ nll0OOO))) & (~ ((~ comp_pat[27]) ^ nlli11i))) & (~ ((~ comp_pat[28]) ^ nlli11l))) & (~ ((~ comp_pat[29]) ^ nlli11O))) & (~ ((~ comp_pat[30]) ^ nlli10i))) & (~ ((~ comp_pat[31]) ^ nlli10l))), n11iiiO = (n11l0li & (((comp_pat_porn & n11iiOi) | n11iilO) & ((comp_pat_porn & n11iill) | n11iili))), n11iili = ((((((((~ (comp_pat[16] ^ nll0lOO)) & (~ (comp_pat[17] ^ nll0O1i))) & (~ (comp_pat[18] ^ nll0O1l))) & (~ (comp_pat[19] ^ nll0O1O))) & (~ (comp_pat[20] ^ nll0O0i))) & (~ (comp_pat[21] ^ nll0O0l))) & (~ (comp_pat[22] ^ nll0O0O))) & (~ (comp_pat[23] ^ nll0Oii))), n11iill = ((((((((~ ((~ comp_pat[16]) ^ nll0lOO)) & (~ ((~ comp_pat[17]) ^ nll0O1i))) & (~ ((~ comp_pat[18]) ^ nll0O1l))) & (~ ((~ comp_pat[19]) ^ nll0O1O))) & (~ ((~ comp_pat[20]) ^ nll0O0i))) & (~ ((~ comp_pat[21]) ^ nll0O0l))) & (~ ((~ comp_pat[22]) ^ nll0O0O))) & (~ ((~ comp_pat[23]) ^ nll0Oii))), n11iilO = ((((((((~ (comp_pat[24] ^ nll0Oil)) & (~ (comp_pat[25] ^ nll0OiO))) & (~ (comp_pat[26] ^ nll0OOl))) & (~ (comp_pat[27] ^ nll0OOO))) & (~ (comp_pat[28] ^ nlli11i))) & (~ (comp_pat[29] ^ nlli11l))) & (~ (comp_pat[30] ^ nlli11O))) & (~ (comp_pat[31] ^ nlli10i))), n11iiOi = ((((((((~ ((~ comp_pat[24]) ^ nll0Oil)) & (~ ((~ comp_pat[25]) ^ nll0OiO))) & (~ ((~ comp_pat[26]) ^ nll0OOl))) & (~ ((~ comp_pat[27]) ^ nll0OOO))) & (~ ((~ comp_pat[28]) ^ nlli11i))) & (~ ((~ comp_pat[29]) ^ nlli11l))) & (~ ((~ comp_pat[30]) ^ nlli11O))) & (~ ((~ comp_pat[31]) ^ nlli10i))), n11iiOl = (n11l0Oi & (((comp_pat_porn & n11il1O) | n11il1l) & ((comp_pat_porn & n11il1i) | n11iiOO))), n11iiOO = ((((((((~ (comp_pat[16] ^ nll0lOl)) & (~ (comp_pat[17] ^ nll0lOO))) & (~ (comp_pat[18] ^ nll0O1i))) & (~ (comp_pat[19] ^ nll0O1l))) & (~ (comp_pat[20] ^ nll0O1O))) & (~ (comp_pat[21] ^ nll0O0i))) & (~ (comp_pat[22] ^ nll0O0l))) & (~ (comp_pat[23] ^ nll0O0O))), n11il0i = (n11li1i & (((comp_pat_porn & n11ilil) | n11ilii) & ((comp_pat_porn & n11il0O) | n11il0l))), n11il0l = ((((((((~ (comp_pat[16] ^ nll0lOi)) & (~ (comp_pat[17] ^ nll0lOl))) & (~ (comp_pat[18] ^ nll0lOO))) & (~ (comp_pat[19] ^ nll0O1i))) & (~ (comp_pat[20] ^ nll0O1l))) & (~ (comp_pat[21] ^ nll0O1O))) & (~ (comp_pat[22] ^ nll0O0i))) & (~ (comp_pat[23] ^ nll0O0l))), n11il0O = ((((((((~ ((~ comp_pat[16]) ^ nll0lOi)) & (~ ((~ comp_pat[17]) ^ nll0lOl))) & (~ ((~ comp_pat[18]) ^ nll0lOO))) & (~ ((~ comp_pat[19]) ^ nll0O1i))) & (~ ((~ comp_pat[20]) ^ nll0O1l))) & (~ ((~ comp_pat[21]) ^ nll0O1O))) & (~ ((~ comp_pat[22]) ^ nll0O0i))) & (~ ((~ comp_pat[23]) ^ nll0O0l))), n11il1i = ((((((((~ ((~ comp_pat[16]) ^ nll0lOl)) & (~ ((~ comp_pat[17]) ^ nll0lOO))) & (~ ((~ comp_pat[18]) ^ nll0O1i))) & (~ ((~ comp_pat[19]) ^ nll0O1l))) & (~ ((~ comp_pat[20]) ^ nll0O1O))) & (~ ((~ comp_pat[21]) ^ nll0O0i))) & (~ ((~ comp_pat[22]) ^ nll0O0l))) & (~ ((~ comp_pat[23]) ^ nll0O0O))), n11il1l = ((((((((~ (comp_pat[24] ^ nll0Oii)) & (~ (comp_pat[25] ^ nll0Oil))) & (~ (comp_pat[26] ^ nll0OiO))) & (~ (comp_pat[27] ^ nll0OOl))) & (~ (comp_pat[28] ^ nll0OOO))) & (~ (comp_pat[29] ^ nlli11i))) & (~ (comp_pat[30] ^ nlli11l))) & (~ (comp_pat[31] ^ nlli11O))), n11il1O = ((((((((~ ((~ comp_pat[24]) ^ nll0Oii)) & (~ ((~ comp_pat[25]) ^ nll0Oil))) & (~ ((~ comp_pat[26]) ^ nll0OiO))) & (~ ((~ comp_pat[27]) ^ nll0OOl))) & (~ ((~ comp_pat[28]) ^ nll0OOO))) & (~ ((~ comp_pat[29]) ^ nlli11i))) & (~ ((~ comp_pat[30]) ^ nlli11l))) & (~ ((~ comp_pat[31]) ^ nlli11O))), n11ilii = ((((((((~ (comp_pat[24] ^ nll0O0O)) & (~ (comp_pat[25] ^ nll0Oii))) & (~ (comp_pat[26] ^ nll0Oil))) & (~ (comp_pat[27] ^ nll0OiO))) & (~ (comp_pat[28] ^ nll0OOl))) & (~ (comp_pat[29] ^ nll0OOO))) & (~ (comp_pat[30] ^ nlli11i))) & (~ (comp_pat[31] ^ nlli11l))), n11ilil = ((((((((~ ((~ comp_pat[24]) ^ nll0O0O)) & (~ ((~ comp_pat[25]) ^ nll0Oii))) & (~ ((~ comp_pat[26]) ^ nll0Oil))) & (~ ((~ comp_pat[27]) ^ nll0OiO))) & (~ ((~ comp_pat[28]) ^ nll0OOl))) & (~ ((~ comp_pat[29]) ^ nll0OOO))) & (~ ((~ comp_pat[30]) ^ nlli11i))) & (~ ((~ comp_pat[31]) ^ nlli11l))), n11iliO = (n11li0i & (((comp_pat_porn & n11ilOi) | n11illO) & ((comp_pat_porn & n11illl) | n11illi))), n11illi = ((((((((~ (comp_pat[16] ^ nll0llO)) & (~ (comp_pat[17] ^ nll0lOi))) & (~ (comp_pat[18] ^ nll0lOl))) & (~ (comp_pat[19] ^ nll0lOO))) & (~ (comp_pat[20] ^ nll0O1i))) & (~ (comp_pat[21] ^ nll0O1l))) & (~ (comp_pat[22] ^ nll0O1O))) & (~ (comp_pat[23] ^ nll0O0i))), n11illl = ((((((((~ ((~ comp_pat[16]) ^ nll0llO)) & (~ ((~ comp_pat[17]) ^ nll0lOi))) & (~ ((~ comp_pat[18]) ^ nll0lOl))) & (~ ((~ comp_pat[19]) ^ nll0lOO))) & (~ ((~ comp_pat[20]) ^ nll0O1i))) & (~ ((~ comp_pat[21]) ^ nll0O1l))) & (~ ((~ comp_pat[22]) ^ nll0O1O))) & (~ ((~ comp_pat[23]) ^ nll0O0i))), n11illO = ((((((((~ (comp_pat[24] ^ nll0O0l)) & (~ (comp_pat[25] ^ nll0O0O))) & (~ (comp_pat[26] ^ nll0Oii))) & (~ (comp_pat[27] ^ nll0Oil))) & (~ (comp_pat[28] ^ nll0OiO))) & (~ (comp_pat[29] ^ nll0OOl))) & (~ (comp_pat[30] ^ nll0OOO))) & (~ (comp_pat[31] ^ nlli11i))), n11ilOi = ((((((((~ ((~ comp_pat[24]) ^ nll0O0l)) & (~ ((~ comp_pat[25]) ^ nll0O0O))) & (~ ((~ comp_pat[26]) ^ nll0Oii))) & (~ ((~ comp_pat[27]) ^ nll0Oil))) & (~ ((~ comp_pat[28]) ^ nll0OiO))) & (~ ((~ comp_pat[29]) ^ nll0OOl))) & (~ ((~ comp_pat[30]) ^ nll0OOO))) & (~ ((~ comp_pat[31]) ^ nlli11i))), n11ilOl = (n11liii & (((comp_pat_porn & n11iO1O) | n11iO1l) & ((comp_pat_porn & n11iO1i) | n11ilOO))), n11ilOO = ((((((((~ (comp_pat[16] ^ nll0lll)) & (~ (comp_pat[17] ^ nll0llO))) & (~ (comp_pat[18] ^ nll0lOi))) & (~ (comp_pat[19] ^ nll0lOl))) & (~ (comp_pat[20] ^ nll0lOO))) & (~ (comp_pat[21] ^ nll0O1i))) & (~ (comp_pat[22] ^ nll0O1l))) & (~ (comp_pat[23] ^ nll0O1O))), n11iO0i = (n11lili & (((comp_pat_porn & n11iOil) | n11iOii) & ((comp_pat_porn & n11iO0O) | n11iO0l))), n11iO0l = ((((((((~ (comp_pat[16] ^ nll0lli)) & (~ (comp_pat[17] ^ nll0lll))) & (~ (comp_pat[18] ^ nll0llO))) & (~ (comp_pat[19] ^ nll0lOi))) & (~ (comp_pat[20] ^ nll0lOl))) & (~ (comp_pat[21] ^ nll0lOO))) & (~ (comp_pat[22] ^ nll0O1i))) & (~ (comp_pat[23] ^ nll0O1l))), n11iO0O = ((((((((~ ((~ comp_pat[16]) ^ nll0lli)) & (~ ((~ comp_pat[17]) ^ nll0lll))) & (~ ((~ comp_pat[18]) ^ nll0llO))) & (~ ((~ comp_pat[19]) ^ nll0lOi))) & (~ ((~ comp_pat[20]) ^ nll0lOl))) & (~ ((~ comp_pat[21]) ^ nll0lOO))) & (~ ((~ comp_pat[22]) ^ nll0O1i))) & (~ ((~ comp_pat[23]) ^ nll0O1l))), n11iO1i = ((((((((~ ((~ comp_pat[16]) ^ nll0lll)) & (~ ((~ comp_pat[17]) ^ nll0llO))) & (~ ((~ comp_pat[18]) ^ nll0lOi))) & (~ ((~ comp_pat[19]) ^ nll0lOl))) & (~ ((~ comp_pat[20]) ^ nll0lOO))) & (~ ((~ comp_pat[21]) ^ nll0O1i))) & (~ ((~ comp_pat[22]) ^ nll0O1l))) & (~ ((~ comp_pat[23]) ^ nll0O1O))), n11iO1l = ((((((((~ (comp_pat[24] ^ nll0O0i)) & (~ (comp_pat[25] ^ nll0O0l))) & (~ (comp_pat[26] ^ nll0O0O))) & (~ (comp_pat[27] ^ nll0Oii))) & (~ (comp_pat[28] ^ nll0Oil))) & (~ (comp_pat[29] ^ nll0OiO))) & (~ (comp_pat[30] ^ nll0OOl))) & (~ (comp_pat[31] ^ nll0OOO))), n11iO1O = ((((((((~ ((~ comp_pat[24]) ^ nll0O0i)) & (~ ((~ comp_pat[25]) ^ nll0O0l))) & (~ ((~ comp_pat[26]) ^ nll0O0O))) & (~ ((~ comp_pat[27]) ^ nll0Oii))) & (~ ((~ comp_pat[28]) ^ nll0Oil))) & (~ ((~ comp_pat[29]) ^ nll0OiO))) & (~ ((~ comp_pat[30]) ^ nll0OOl))) & (~ ((~ comp_pat[31]) ^ nll0OOO))), n11iOii = ((((((((~ (comp_pat[24] ^ nll0O1O)) & (~ (comp_pat[25] ^ nll0O0i))) & (~ (comp_pat[26] ^ nll0O0l))) & (~ (comp_pat[27] ^ nll0O0O))) & (~ (comp_pat[28] ^ nll0Oii))) & (~ (comp_pat[29] ^ nll0Oil))) & (~ (comp_pat[30] ^ nll0OiO))) & (~ (comp_pat[31] ^ nll0OOl))), n11iOil = ((((((((~ ((~ comp_pat[24]) ^ nll0O1O)) & (~ ((~ comp_pat[25]) ^ nll0O0i))) & (~ ((~ comp_pat[26]) ^ nll0O0l))) & (~ ((~ comp_pat[27]) ^ nll0O0O))) & (~ ((~ comp_pat[28]) ^ nll0Oii))) & (~ ((~ comp_pat[29]) ^ nll0Oil))) & (~ ((~ comp_pat[30]) ^ nll0OiO))) & (~ ((~ comp_pat[31]) ^ nll0OOl))), n11iOiO = (((((((((((((((n11lili | n11liii) | n11li0i) | n11li1i) | n11l0Oi) | n11l0li) | n11l0ii) | n11l00i) | n11l01i) | n11l1Oi) | n11l1li) | n11l1ii) | n11l10i) | n11l11i) | n11iOOi) | n11iOli), n11iOli = (n11liOl & ((comp_pat_porn & n11iOlO) | n11iOll)), n11iOll = ((((((((~ (comp_pat[8] ^ nll0O1l)) & (~ (comp_pat[9] ^ nll0O1O))) & (~ (comp_pat[10] ^ nll0O0i))) & (~ (comp_pat[11] ^ nll0O0l))) & (~ (comp_pat[12] ^ nll0O0O))) & (~ (comp_pat[13] ^ nll0Oii))) & (~ (comp_pat[14] ^ nll0Oil))) & (~ (comp_pat[15] ^ nll0OiO))), n11iOlO = ((((((((~ ((~ comp_pat[8]) ^ nll0O1l)) & (~ ((~ comp_pat[9]) ^ nll0O1O))) & (~ ((~ comp_pat[10]) ^ nll0O0i))) & (~ ((~ comp_pat[11]) ^ nll0O0l))) & (~ ((~ comp_pat[12]) ^ nll0O0O))) & (~ ((~ comp_pat[13]) ^ nll0Oii))) & (~ ((~ comp_pat[14]) ^ nll0Oil))) & (~ ((~ comp_pat[15]) ^ nll0OiO))), n11iOOi = (n11ll1l & ((comp_pat_porn & n11iOOO) | n11iOOl)), n11iOOl = ((((((((~ (comp_pat[8] ^ nll0O1i)) & (~ (comp_pat[9] ^ nll0O1l))) & (~ (comp_pat[10] ^ nll0O1O))) & (~ (comp_pat[11] ^ nll0O0i))) & (~ (comp_pat[12] ^ nll0O0l))) & (~ (comp_pat[13] ^ nll0O0O))) & (~ (comp_pat[14] ^ nll0Oii))) & (~ (comp_pat[15] ^ nll0Oil))), n11iOOO = ((((((((~ ((~ comp_pat[8]) ^ nll0O1i)) & (~ ((~ comp_pat[9]) ^ nll0O1l))) & (~ ((~ comp_pat[10]) ^ nll0O1O))) & (~ ((~ comp_pat[11]) ^ nll0O0i))) & (~ ((~ comp_pat[12]) ^ nll0O0l))) & (~ ((~ comp_pat[13]) ^ nll0O0O))) & (~ ((~ comp_pat[14]) ^ nll0Oii))) & (~ ((~ comp_pat[15]) ^ nll0Oil))), n11l00i = (n11lOil & ((comp_pat_porn & n11l00O) | n11l00l)), n11l00l = ((((((((~ (comp_pat[8] ^ nll0liO)) & (~ (comp_pat[9] ^ nll0lli))) & (~ (comp_pat[10] ^ nll0lll))) & (~ (comp_pat[11] ^ nll0llO))) & (~ (comp_pat[12] ^ nll0lOi))) & (~ (comp_pat[13] ^ nll0lOl))) & (~ (comp_pat[14] ^ nll0lOO))) & (~ (comp_pat[15] ^ nll0O1i))), n11l00O = ((((((((~ ((~ comp_pat[8]) ^ nll0liO)) & (~ ((~ comp_pat[9]) ^ nll0lli))) & (~ ((~ comp_pat[10]) ^ nll0lll))) & (~ ((~ comp_pat[11]) ^ nll0llO))) & (~ ((~ comp_pat[12]) ^ nll0lOi))) & (~ ((~ comp_pat[13]) ^ nll0lOl))) & (~ ((~ comp_pat[14]) ^ nll0lOO))) & (~ ((~ comp_pat[15]) ^ nll0O1i))), n11l01i = (n11lO0l & ((comp_pat_porn & n11l01O) | n11l01l)), n11l01l = ((((((((~ (comp_pat[8] ^ nll0lli)) & (~ (comp_pat[9] ^ nll0lll))) & (~ (comp_pat[10] ^ nll0llO))) & (~ (comp_pat[11] ^ nll0lOi))) & (~ (comp_pat[12] ^ nll0lOl))) & (~ (comp_pat[13] ^ nll0lOO))) & (~ (comp_pat[14] ^ nll0O1i))) & (~ (comp_pat[15] ^ nll0O1l))), n11l01O = ((((((((~ ((~ comp_pat[8]) ^ nll0lli)) & (~ ((~ comp_pat[9]) ^ nll0lll))) & (~ ((~ comp_pat[10]) ^ nll0llO))) & (~ ((~ comp_pat[11]) ^ nll0lOi))) & (~ ((~ comp_pat[12]) ^ nll0lOl))) & (~ ((~ comp_pat[13]) ^ nll0lOO))) & (~ ((~ comp_pat[14]) ^ nll0O1i))) & (~ ((~ comp_pat[15]) ^ nll0O1l))), n11l0ii = (n11lOll & ((comp_pat_porn & n11l0iO) | n11l0il)), n11l0il = ((((((((~ (comp_pat[8] ^ nll0l0i)) & (~ (comp_pat[9] ^ nll0liO))) & (~ (comp_pat[10] ^ nll0lli))) & (~ (comp_pat[11] ^ nll0lll))) & (~ (comp_pat[12] ^ nll0llO))) & (~ (comp_pat[13] ^ nll0lOi))) & (~ (comp_pat[14] ^ nll0lOl))) & (~ (comp_pat[15] ^ nll0lOO))), n11l0iO = ((((((((~ ((~ comp_pat[8]) ^ nll0l0i)) & (~ ((~ comp_pat[9]) ^ nll0liO))) & (~ ((~ comp_pat[10]) ^ nll0lli))) & (~ ((~ comp_pat[11]) ^ nll0lll))) & (~ ((~ comp_pat[12]) ^ nll0llO))) & (~ ((~ comp_pat[13]) ^ nll0lOi))) & (~ ((~ comp_pat[14]) ^ nll0lOl))) & (~ ((~ comp_pat[15]) ^ nll0lOO))), n11l0li = (n11lOOl & ((comp_pat_porn & n11l0lO) | n11l0ll)), n11l0ll = ((((((((~ (comp_pat[8] ^ nll0l1O)) & (~ (comp_pat[9] ^ nll0l0i))) & (~ (comp_pat[10] ^ nll0liO))) & (~ (comp_pat[11] ^ nll0lli))) & (~ (comp_pat[12] ^ nll0lll))) & (~ (comp_pat[13] ^ nll0llO))) & (~ (comp_pat[14] ^ nll0lOi))) & (~ (comp_pat[15] ^ nll0lOl))), n11l0lO = ((((((((~ ((~ comp_pat[8]) ^ nll0l1O)) & (~ ((~ comp_pat[9]) ^ nll0l0i))) & (~ ((~ comp_pat[10]) ^ nll0liO))) & (~ ((~ comp_pat[11]) ^ nll0lli))) & (~ ((~ comp_pat[12]) ^ nll0lll))) & (~ ((~ comp_pat[13]) ^ nll0llO))) & (~ ((~ comp_pat[14]) ^ nll0lOi))) & (~ ((~ comp_pat[15]) ^ nll0lOl))), n11l0Oi = (n11O11l & ((comp_pat_porn & n11l0OO) | n11l0Ol)), n11l0Ol = ((((((((~ (comp_pat[8] ^ nll0l1l)) & (~ (comp_pat[9] ^ nll0l1O))) & (~ (comp_pat[10] ^ nll0l0i))) & (~ (comp_pat[11] ^ nll0liO))) & (~ (comp_pat[12] ^ nll0lli))) & (~ (comp_pat[13] ^ nll0lll))) & (~ (comp_pat[14] ^ nll0llO))) & (~ (comp_pat[15] ^ nll0lOi))), n11l0OO = ((((((((~ ((~ comp_pat[8]) ^ nll0l1l)) & (~ ((~ comp_pat[9]) ^ nll0l1O))) & (~ ((~ comp_pat[10]) ^ nll0l0i))) & (~ ((~ comp_pat[11]) ^ nll0liO))) & (~ ((~ comp_pat[12]) ^ nll0lli))) & (~ ((~ comp_pat[13]) ^ nll0lll))) & (~ ((~ comp_pat[14]) ^ nll0llO))) & (~ ((~ comp_pat[15]) ^ nll0lOi))), n11l10i = (n11llil & ((comp_pat_porn & n11l10O) | n11l10l)), n11l10l = ((((((((~ (comp_pat[8] ^ nll0lOl)) & (~ (comp_pat[9] ^ nll0lOO))) & (~ (comp_pat[10] ^ nll0O1i))) & (~ (comp_pat[11] ^ nll0O1l))) & (~ (comp_pat[12] ^ nll0O1O))) & (~ (comp_pat[13] ^ nll0O0i))) & (~ (comp_pat[14] ^ nll0O0l))) & (~ (comp_pat[15] ^ nll0O0O))), n11l10O = ((((((((~ ((~ comp_pat[8]) ^ nll0lOl)) & (~ ((~ comp_pat[9]) ^ nll0lOO))) & (~ ((~ comp_pat[10]) ^ nll0O1i))) & (~ ((~ comp_pat[11]) ^ nll0O1l))) & (~ ((~ comp_pat[12]) ^ nll0O1O))) & (~ ((~ comp_pat[13]) ^ nll0O0i))) & (~ ((~ comp_pat[14]) ^ nll0O0l))) & (~ ((~ comp_pat[15]) ^ nll0O0O))), n11l11i = (n11ll0l & ((comp_pat_porn & n11l11O) | n11l11l)), n11l11l = ((((((((~ (comp_pat[8] ^ nll0lOO)) & (~ (comp_pat[9] ^ nll0O1i))) & (~ (comp_pat[10] ^ nll0O1l))) & (~ (comp_pat[11] ^ nll0O1O))) & (~ (comp_pat[12] ^ nll0O0i))) & (~ (comp_pat[13] ^ nll0O0l))) & (~ (comp_pat[14] ^ nll0O0O))) & (~ (comp_pat[15] ^ nll0Oii))), n11l11O = ((((((((~ ((~ comp_pat[8]) ^ nll0lOO)) & (~ ((~ comp_pat[9]) ^ nll0O1i))) & (~ ((~ comp_pat[10]) ^ nll0O1l))) & (~ ((~ comp_pat[11]) ^ nll0O1O))) & (~ ((~ comp_pat[12]) ^ nll0O0i))) & (~ ((~ comp_pat[13]) ^ nll0O0l))) & (~ ((~ comp_pat[14]) ^ nll0O0O))) & (~ ((~ comp_pat[15]) ^ nll0Oii))), n11l1ii = (n11llll & ((comp_pat_porn & n11l1iO) | n11l1il)), n11l1il = ((((((((~ (comp_pat[8] ^ nll0lOi)) & (~ (comp_pat[9] ^ nll0lOl))) & (~ (comp_pat[10] ^ nll0lOO))) & (~ (comp_pat[11] ^ nll0O1i))) & (~ (comp_pat[12] ^ nll0O1l))) & (~ (comp_pat[13] ^ nll0O1O))) & (~ (comp_pat[14] ^ nll0O0i))) & (~ (comp_pat[15] ^ nll0O0l))), n11l1iO = ((((((((~ ((~ comp_pat[8]) ^ nll0lOi)) & (~ ((~ comp_pat[9]) ^ nll0lOl))) & (~ ((~ comp_pat[10]) ^ nll0lOO))) & (~ ((~ comp_pat[11]) ^ nll0O1i))) & (~ ((~ comp_pat[12]) ^ nll0O1l))) & (~ ((~ comp_pat[13]) ^ nll0O1O))) & (~ ((~ comp_pat[14]) ^ nll0O0i))) & (~ ((~ comp_pat[15]) ^ nll0O0l))), n11l1li = (n11llOl & ((comp_pat_porn & n11l1lO) | n11l1ll)), n11l1ll = ((((((((~ (comp_pat[8] ^ nll0llO)) & (~ (comp_pat[9] ^ nll0lOi))) & (~ (comp_pat[10] ^ nll0lOl))) & (~ (comp_pat[11] ^ nll0lOO))) & (~ (comp_pat[12] ^ nll0O1i))) & (~ (comp_pat[13] ^ nll0O1l))) & (~ (comp_pat[14] ^ nll0O1O))) & (~ (comp_pat[15] ^ nll0O0i))), n11l1lO = ((((((((~ ((~ comp_pat[8]) ^ nll0llO)) & (~ ((~ comp_pat[9]) ^ nll0lOi))) & (~ ((~ comp_pat[10]) ^ nll0lOl))) & (~ ((~ comp_pat[11]) ^ nll0lOO))) & (~ ((~ comp_pat[12]) ^ nll0O1i))) & (~ ((~ comp_pat[13]) ^ nll0O1l))) & (~ ((~ comp_pat[14]) ^ nll0O1O))) & (~ ((~ comp_pat[15]) ^ nll0O0i))), n11l1Oi = (n11lO1l & ((comp_pat_porn & n11l1OO) | n11l1Ol)), n11l1Ol = ((((((((~ (comp_pat[8] ^ nll0lll)) & (~ (comp_pat[9] ^ nll0llO))) & (~ (comp_pat[10] ^ nll0lOi))) & (~ (comp_pat[11] ^ nll0lOl))) & (~ (comp_pat[12] ^ nll0lOO))) & (~ (comp_pat[13] ^ nll0O1i))) & (~ (comp_pat[14] ^ nll0O1l))) & (~ (comp_pat[15] ^ nll0O1O))), n11l1OO = ((((((((~ ((~ comp_pat[8]) ^ nll0lll)) & (~ ((~ comp_pat[9]) ^ nll0llO))) & (~ ((~ comp_pat[10]) ^ nll0lOi))) & (~ ((~ comp_pat[11]) ^ nll0lOl))) & (~ ((~ comp_pat[12]) ^ nll0lOO))) & (~ ((~ comp_pat[13]) ^ nll0O1i))) & (~ ((~ comp_pat[14]) ^ nll0O1l))) & (~ ((~ comp_pat[15]) ^ nll0O1O))), n11li0i = (n11O1il & ((comp_pat_porn & n11li0O) | n11li0l)), n11li0l = ((((((((~ (comp_pat[8] ^ nll0iOO)) & (~ (comp_pat[9] ^ nll0l1i))) & (~ (comp_pat[10] ^ nll0l1l))) & (~ (comp_pat[11] ^ nll0l1O))) & (~ (comp_pat[12] ^ nll0l0i))) & (~ (comp_pat[13] ^ nll0liO))) & (~ (comp_pat[14] ^ nll0lli))) & (~ (comp_pat[15] ^ nll0lll))), n11li0O = ((((((((~ ((~ comp_pat[8]) ^ nll0iOO)) & (~ ((~ comp_pat[9]) ^ nll0l1i))) & (~ ((~ comp_pat[10]) ^ nll0l1l))) & (~ ((~ comp_pat[11]) ^ nll0l1O))) & (~ ((~ comp_pat[12]) ^ nll0l0i))) & (~ ((~ comp_pat[13]) ^ nll0liO))) & (~ ((~ comp_pat[14]) ^ nll0lli))) & (~ ((~ comp_pat[15]) ^ nll0lll))), n11li1i = (n11O10l & ((comp_pat_porn & n11li1O) | n11li1l)), n11li1l = ((((((((~ (comp_pat[8] ^ nll0l1i)) & (~ (comp_pat[9] ^ nll0l1l))) & (~ (comp_pat[10] ^ nll0l1O))) & (~ (comp_pat[11] ^ nll0l0i))) & (~ (comp_pat[12] ^ nll0liO))) & (~ (comp_pat[13] ^ nll0lli))) & (~ (comp_pat[14] ^ nll0lll))) & (~ (comp_pat[15] ^ nll0llO))), n11li1O = ((((((((~ ((~ comp_pat[8]) ^ nll0l1i)) & (~ ((~ comp_pat[9]) ^ nll0l1l))) & (~ ((~ comp_pat[10]) ^ nll0l1O))) & (~ ((~ comp_pat[11]) ^ nll0l0i))) & (~ ((~ comp_pat[12]) ^ nll0liO))) & (~ ((~ comp_pat[13]) ^ nll0lli))) & (~ ((~ comp_pat[14]) ^ nll0lll))) & (~ ((~ comp_pat[15]) ^ nll0llO))), n11liii = (n11O1ll & ((comp_pat_porn & n11liiO) | n11liil)), n11liil = ((((((((~ (comp_pat[8] ^ nll0iOl)) & (~ (comp_pat[9] ^ nll0iOO))) & (~ (comp_pat[10] ^ nll0l1i))) & (~ (comp_pat[11] ^ nll0l1l))) & (~ (comp_pat[12] ^ nll0l1O))) & (~ (comp_pat[13] ^ nll0l0i))) & (~ (comp_pat[14] ^ nll0liO))) & (~ (comp_pat[15] ^ nll0lli))), n11liiO = ((((((((~ ((~ comp_pat[8]) ^ nll0iOl)) & (~ ((~ comp_pat[9]) ^ nll0iOO))) & (~ ((~ comp_pat[10]) ^ nll0l1i))) & (~ ((~ comp_pat[11]) ^ nll0l1l))) & (~ ((~ comp_pat[12]) ^ nll0l1O))) & (~ ((~ comp_pat[13]) ^ nll0l0i))) & (~ ((~ comp_pat[14]) ^ nll0liO))) & (~ ((~ comp_pat[15]) ^ nll0lli))), n11lili = (n11O1Ol & ((comp_pat_porn & n11lilO) | n11lill)), n11lill = ((((((((~ (comp_pat[8] ^ nll0iOi)) & (~ (comp_pat[9] ^ nll0iOl))) & (~ (comp_pat[10] ^ nll0iOO))) & (~ (comp_pat[11] ^ nll0l1i))) & (~ (comp_pat[12] ^ nll0l1l))) & (~ (comp_pat[13] ^ nll0l1O))) & (~ (comp_pat[14] ^ nll0l0i))) & (~ (comp_pat[15] ^ nll0liO))), n11lilO = ((((((((~ ((~ comp_pat[8]) ^ nll0iOi)) & (~ ((~ comp_pat[9]) ^ nll0iOl))) & (~ ((~ comp_pat[10]) ^ nll0iOO))) & (~ ((~ comp_pat[11]) ^ nll0l1i))) & (~ ((~ comp_pat[12]) ^ nll0l1l))) & (~ ((~ comp_pat[13]) ^ nll0l1O))) & (~ ((~ comp_pat[14]) ^ nll0l0i))) & (~ ((~ comp_pat[15]) ^ nll0liO))), n11liOi = (((((((((((((((n11O1Ol | n11O1ll) | n11O1il) | n11O10l) | n11O11l) | n11lOOl) | n11lOll) | n11lOil) | n11lO0l) | n11lO1l) | n11llOl) | n11llll) | n11llil) | n11ll0l) | n11ll1l) | n11liOl), n11liOl = ((comp_pat_porn & n11ll1i) | n11liOO), n11liOO = ((((((((~ (comp_pat[0] ^ nll0liO)) & (~ (comp_pat[1] ^ nll0lli))) & (~ (comp_pat[2] ^ nll0lll))) & (~ (comp_pat[3] ^ nll0llO))) & (~ (comp_pat[4] ^ nll0lOi))) & (~ (comp_pat[5] ^ nll0lOl))) & (~ (comp_pat[6] ^ nll0lOO))) & (~ (comp_pat[7] ^ nll0O1i))), n11ll0i = ((((((((~ ((~ comp_pat[0]) ^ nll0l0i)) & (~ ((~ comp_pat[1]) ^ nll0liO))) & (~ ((~ comp_pat[2]) ^ nll0lli))) & (~ ((~ comp_pat[3]) ^ nll0lll))) & (~ ((~ comp_pat[4]) ^ nll0llO))) & (~ ((~ comp_pat[5]) ^ nll0lOi))) & (~ ((~ comp_pat[6]) ^ nll0lOl))) & (~ ((~ comp_pat[7]) ^ nll0lOO))), n11ll0l = ((comp_pat_porn & n11llii) | n11ll0O), n11ll0O = ((((((((~ (comp_pat[0] ^ nll0l1O)) & (~ (comp_pat[1] ^ nll0l0i))) & (~ (comp_pat[2] ^ nll0liO))) & (~ (comp_pat[3] ^ nll0lli))) & (~ (comp_pat[4] ^ nll0lll))) & (~ (comp_pat[5] ^ nll0llO))) & (~ (comp_pat[6] ^ nll0lOi))) & (~ (comp_pat[7] ^ nll0lOl))), n11ll1i = ((((((((~ ((~ comp_pat[0]) ^ nll0liO)) & (~ ((~ comp_pat[1]) ^ nll0lli))) & (~ ((~ comp_pat[2]) ^ nll0lll))) & (~ ((~ comp_pat[3]) ^ nll0llO))) & (~ ((~ comp_pat[4]) ^ nll0lOi))) & (~ ((~ comp_pat[5]) ^ nll0lOl))) & (~ ((~ comp_pat[6]) ^ nll0lOO))) & (~ ((~ comp_pat[7]) ^ nll0O1i))), n11ll1l = ((comp_pat_porn & n11ll0i) | n11ll1O), n11ll1O = ((((((((~ (comp_pat[0] ^ nll0l0i)) & (~ (comp_pat[1] ^ nll0liO))) & (~ (comp_pat[2] ^ nll0lli))) & (~ (comp_pat[3] ^ nll0lll))) & (~ (comp_pat[4] ^ nll0llO))) & (~ (comp_pat[5] ^ nll0lOi))) & (~ (comp_pat[6] ^ nll0lOl))) & (~ (comp_pat[7] ^ nll0lOO))), n11llii = ((((((((~ ((~ comp_pat[0]) ^ nll0l1O)) & (~ ((~ comp_pat[1]) ^ nll0l0i))) & (~ ((~ comp_pat[2]) ^ nll0liO))) & (~ ((~ comp_pat[3]) ^ nll0lli))) & (~ ((~ comp_pat[4]) ^ nll0lll))) & (~ ((~ comp_pat[5]) ^ nll0llO))) & (~ ((~ comp_pat[6]) ^ nll0lOi))) & (~ ((~ comp_pat[7]) ^ nll0lOl))), n11llil = ((comp_pat_porn & n11llli) | n11lliO), n11lliO = ((((((((~ (comp_pat[0] ^ nll0l1l)) & (~ (comp_pat[1] ^ nll0l1O))) & (~ (comp_pat[2] ^ nll0l0i))) & (~ (comp_pat[3] ^ nll0liO))) & (~ (comp_pat[4] ^ nll0lli))) & (~ (comp_pat[5] ^ nll0lll))) & (~ (comp_pat[6] ^ nll0llO))) & (~ (comp_pat[7] ^ nll0lOi))), n11llli = ((((((((~ ((~ comp_pat[0]) ^ nll0l1l)) & (~ ((~ comp_pat[1]) ^ nll0l1O))) & (~ ((~ comp_pat[2]) ^ nll0l0i))) & (~ ((~ comp_pat[3]) ^ nll0liO))) & (~ ((~ comp_pat[4]) ^ nll0lli))) & (~ ((~ comp_pat[5]) ^ nll0lll))) & (~ ((~ comp_pat[6]) ^ nll0llO))) & (~ ((~ comp_pat[7]) ^ nll0lOi))), n11llll = ((comp_pat_porn & n11llOi) | n11lllO), n11lllO = ((((((((~ (comp_pat[0] ^ nll0l1i)) & (~ (comp_pat[1] ^ nll0l1l))) & (~ (comp_pat[2] ^ nll0l1O))) & (~ (comp_pat[3] ^ nll0l0i))) & (~ (comp_pat[4] ^ nll0liO))) & (~ (comp_pat[5] ^ nll0lli))) & (~ (comp_pat[6] ^ nll0lll))) & (~ (comp_pat[7] ^ nll0llO))), n11llOi = ((((((((~ ((~ comp_pat[0]) ^ nll0l1i)) & (~ ((~ comp_pat[1]) ^ nll0l1l))) & (~ ((~ comp_pat[2]) ^ nll0l1O))) & (~ ((~ comp_pat[3]) ^ nll0l0i))) & (~ ((~ comp_pat[4]) ^ nll0liO))) & (~ ((~ comp_pat[5]) ^ nll0lli))) & (~ ((~ comp_pat[6]) ^ nll0lll))) & (~ ((~ comp_pat[7]) ^ nll0llO))), n11llOl = ((comp_pat_porn & n11lO1i) | n11llOO), n11llOO = ((((((((~ (comp_pat[0] ^ nll0iOO)) & (~ (comp_pat[1] ^ nll0l1i))) & (~ (comp_pat[2] ^ nll0l1l))) & (~ (comp_pat[3] ^ nll0l1O))) & (~ (comp_pat[4] ^ nll0l0i))) & (~ (comp_pat[5] ^ nll0liO))) & (~ (comp_pat[6] ^ nll0lli))) & (~ (comp_pat[7] ^ nll0lll))), n11lO0i = ((((((((~ ((~ comp_pat[0]) ^ nll0iOl)) & (~ ((~ comp_pat[1]) ^ nll0iOO))) & (~ ((~ comp_pat[2]) ^ nll0l1i))) & (~ ((~ comp_pat[3]) ^ nll0l1l))) & (~ ((~ comp_pat[4]) ^ nll0l1O))) & (~ ((~ comp_pat[5]) ^ nll0l0i))) & (~ ((~ comp_pat[6]) ^ nll0liO))) & (~ ((~ comp_pat[7]) ^ nll0lli))), n11lO0l = ((comp_pat_porn & n11lOii) | n11lO0O), n11lO0O = ((((((((~ (comp_pat[0] ^ nll0iOi)) & (~ (comp_pat[1] ^ nll0iOl))) & (~ (comp_pat[2] ^ nll0iOO))) & (~ (comp_pat[3] ^ nll0l1i))) & (~ (comp_pat[4] ^ nll0l1l))) & (~ (comp_pat[5] ^ nll0l1O))) & (~ (comp_pat[6] ^ nll0l0i))) & (~ (comp_pat[7] ^ nll0liO))), n11lO1i = ((((((((~ ((~ comp_pat[0]) ^ nll0iOO)) & (~ ((~ comp_pat[1]) ^ nll0l1i))) & (~ ((~ comp_pat[2]) ^ nll0l1l))) & (~ ((~ comp_pat[3]) ^ nll0l1O))) & (~ ((~ comp_pat[4]) ^ nll0l0i))) & (~ ((~ comp_pat[5]) ^ nll0liO))) & (~ ((~ comp_pat[6]) ^ nll0lli))) & (~ ((~ comp_pat[7]) ^ nll0lll))), n11lO1l = ((comp_pat_porn & n11lO0i) | n11lO1O), n11lO1O = ((((((((~ (comp_pat[0] ^ nll0iOl)) & (~ (comp_pat[1] ^ nll0iOO))) & (~ (comp_pat[2] ^ nll0l1i))) & (~ (comp_pat[3] ^ nll0l1l))) & (~ (comp_pat[4] ^ nll0l1O))) & (~ (comp_pat[5] ^ nll0l0i))) & (~ (comp_pat[6] ^ nll0liO))) & (~ (comp_pat[7] ^ nll0lli))), n11lOii = ((((((((~ ((~ comp_pat[0]) ^ nll0iOi)) & (~ ((~ comp_pat[1]) ^ nll0iOl))) & (~ ((~ comp_pat[2]) ^ nll0iOO))) & (~ ((~ comp_pat[3]) ^ nll0l1i))) & (~ ((~ comp_pat[4]) ^ nll0l1l))) & (~ ((~ comp_pat[5]) ^ nll0l1O))) & (~ ((~ comp_pat[6]) ^ nll0l0i))) & (~ ((~ comp_pat[7]) ^ nll0liO))), n11lOil = ((comp_pat_porn & n11lOli) | n11lOiO), n11lOiO = ((((((((~ (comp_pat[0] ^ nll0ilO)) & (~ (comp_pat[1] ^ nll0iOi))) & (~ (comp_pat[2] ^ nll0iOl))) & (~ (comp_pat[3] ^ nll0iOO))) & (~ (comp_pat[4] ^ nll0l1i))) & (~ (comp_pat[5] ^ nll0l1l))) & (~ (comp_pat[6] ^ nll0l1O))) & (~ (comp_pat[7] ^ nll0l0i))), n11lOli = ((((((((~ ((~ comp_pat[0]) ^ nll0ilO)) & (~ ((~ comp_pat[1]) ^ nll0iOi))) & (~ ((~ comp_pat[2]) ^ nll0iOl))) & (~ ((~ comp_pat[3]) ^ nll0iOO))) & (~ ((~ comp_pat[4]) ^ nll0l1i))) & (~ ((~ comp_pat[5]) ^ nll0l1l))) & (~ ((~ comp_pat[6]) ^ nll0l1O))) & (~ ((~ comp_pat[7]) ^ nll0l0i))), n11lOll = ((comp_pat_porn & n11lOOi) | n11lOlO), n11lOlO = ((((((((~ (comp_pat[0] ^ nll0ill)) & (~ (comp_pat[1] ^ nll0ilO))) & (~ (comp_pat[2] ^ nll0iOi))) & (~ (comp_pat[3] ^ nll0iOl))) & (~ (comp_pat[4] ^ nll0iOO))) & (~ (comp_pat[5] ^ nll0l1i))) & (~ (comp_pat[6] ^ nll0l1l))) & (~ (comp_pat[7] ^ nll0l1O))), n11lOOi = ((((((((~ ((~ comp_pat[0]) ^ nll0ill)) & (~ ((~ comp_pat[1]) ^ nll0ilO))) & (~ ((~ comp_pat[2]) ^ nll0iOi))) & (~ ((~ comp_pat[3]) ^ nll0iOl))) & (~ ((~ comp_pat[4]) ^ nll0iOO))) & (~ ((~ comp_pat[5]) ^ nll0l1i))) & (~ ((~ comp_pat[6]) ^ nll0l1l))) & (~ ((~ comp_pat[7]) ^ nll0l1O))), n11lOOl = ((comp_pat_porn & n11O11i) | n11lOOO), n11lOOO = ((((((((~ (comp_pat[0] ^ nll0ili)) & (~ (comp_pat[1] ^ nll0ill))) & (~ (comp_pat[2] ^ nll0ilO))) & (~ (comp_pat[3] ^ nll0iOi))) & (~ (comp_pat[4] ^ nll0iOl))) & (~ (comp_pat[5] ^ nll0iOO))) & (~ (comp_pat[6] ^ nll0l1i))) & (~ (comp_pat[7] ^ nll0l1l))), n11O00i = ((((((((((~ (comp_pat[20] ^ nll0OOl)) & (~ (comp_pat[21] ^ nll0OOO))) & (~ (comp_pat[22] ^ nlli11i))) & (~ (comp_pat[23] ^ nlli11l))) & (~ (comp_pat[24] ^ nlli11O))) & (~ (comp_pat[25] ^ nlli10i))) & (~ (comp_pat[26] ^ nlli10l))) & (~ (comp_pat[27] ^ nlli10O))) & (~ (comp_pat[28] ^ nlli1ii))) & (~ (comp_pat[29] ^ nlli1il))), n11O00l = ((((((((((~ ((~ comp_pat[20]) ^ nll0OOl)) & (~ ((~ comp_pat[21]) ^ nll0OOO))) & (~ ((~ comp_pat[22]) ^ nlli11i))) & (~ ((~ comp_pat[23]) ^ nlli11l))) & (~ ((~ comp_pat[24]) ^ nlli11O))) & (~ ((~ comp_pat[25]) ^ nlli10i))) & (~ ((~ comp_pat[26]) ^ nlli10l))) & (~ ((~ comp_pat[27]) ^ nlli10O))) & (~ ((~ comp_pat[28]) ^ nlli1ii))) & (~ ((~ comp_pat[29]) ^ nlli1il))), n11O00O = ((((((((((~ (comp_pat[30] ^ nlli1iO)) & (~ (comp_pat[31] ^ nlli1li))) & (~ (comp_pat[32] ^ nlli1ll))) & (~ (comp_pat[33] ^ nlli1lO))) & (~ (comp_pat[34] ^ nlli1Oi))) & (~ (comp_pat[35] ^ nlli1Ol))) & (~ (comp_pat[36] ^ nlli1OO))) & (~ (comp_pat[37] ^ nlli01i))) & (~ (comp_pat[38] ^ nlli01l))) & (~ (comp_pat[39] ^ nlli01O))), n11O01i = ((((((((~ ((~ comp_pat[0]) ^ nll0i0l)) & (~ ((~ comp_pat[1]) ^ nll0i0O))) & (~ ((~ comp_pat[2]) ^ nll0iii))) & (~ ((~ comp_pat[3]) ^ nll0iil))) & (~ ((~ comp_pat[4]) ^ nll0iiO))) & (~ ((~ comp_pat[5]) ^ nll0ili))) & (~ ((~ comp_pat[6]) ^ nll0ill))) & (~ ((~ comp_pat[7]) ^ nll0ilO))), n11O01l = (((((((((((((((((((n101iil | n101i1O) | n1010Oi) | n1010il) | n10101O) | n1011Oi) | n1011il) | n10111O) | n11OOOi) | n11OOil) | n11OO1O) | n11OlOi) | n11Olil) | n11Ol1O) | n11OiOi) | n11Oiil) | n11Oi1O) | n11O0Oi) | n11O0il) | n11O01O), n11O01O = (n101iOl & (((comp_pat_porn & n11O0ii) | n11O00O) & ((comp_pat_porn & n11O00l) | n11O00i))), n11O0ii = ((((((((((~ ((~ comp_pat[30]) ^ nlli1iO)) & (~ ((~ comp_pat[31]) ^ nlli1li))) & (~ ((~ comp_pat[32]) ^ nlli1ll))) & (~ ((~ comp_pat[33]) ^ nlli1lO))) & (~ ((~ comp_pat[34]) ^ nlli1Oi))) & (~ ((~ comp_pat[35]) ^ nlli1Ol))) & (~ ((~ comp_pat[36]) ^ nlli1OO))) & (~ ((~ comp_pat[37]) ^ nlli01i))) & (~ ((~ comp_pat[38]) ^ nlli01l))) & (~ ((~ comp_pat[39]) ^ nlli01O))), n11O0il = (n101l1l & (((comp_pat_porn & n11O0lO) | n11O0ll) & ((comp_pat_porn & n11O0li) | n11O0iO))), n11O0iO = ((((((((((~ (comp_pat[20] ^ nll0OOi)) & (~ (comp_pat[21] ^ nll0OOl))) & (~ (comp_pat[22] ^ nll0OOO))) & (~ (comp_pat[23] ^ nlli11i))) & (~ (comp_pat[24] ^ nlli11l))) & (~ (comp_pat[25] ^ nlli11O))) & (~ (comp_pat[26] ^ nlli10i))) & (~ (comp_pat[27] ^ nlli10l))) & (~ (comp_pat[28] ^ nlli10O))) & (~ (comp_pat[29] ^ nlli1ii))), n11O0li = ((((((((((~ ((~ comp_pat[20]) ^ nll0OOi)) & (~ ((~ comp_pat[21]) ^ nll0OOl))) & (~ ((~ comp_pat[22]) ^ nll0OOO))) & (~ ((~ comp_pat[23]) ^ nlli11i))) & (~ ((~ comp_pat[24]) ^ nlli11l))) & (~ ((~ comp_pat[25]) ^ nlli11O))) & (~ ((~ comp_pat[26]) ^ nlli10i))) & (~ ((~ comp_pat[27]) ^ nlli10l))) & (~ ((~ comp_pat[28]) ^ nlli10O))) & (~ ((~ comp_pat[29]) ^ nlli1ii))), n11O0ll = ((((((((((~ (comp_pat[30] ^ nlli1il)) & (~ (comp_pat[31] ^ nlli1iO))) & (~ (comp_pat[32] ^ nlli1li))) & (~ (comp_pat[33] ^ nlli1ll))) & (~ (comp_pat[34] ^ nlli1lO))) & (~ (comp_pat[35] ^ nlli1Oi))) & (~ (comp_pat[36] ^ nlli1Ol))) & (~ (comp_pat[37] ^ nlli1OO))) & (~ (comp_pat[38] ^ nlli01i))) & (~ (comp_pat[39] ^ nlli01l))), n11O0lO = ((((((((((~ ((~ comp_pat[30]) ^ nlli1il)) & (~ ((~ comp_pat[31]) ^ nlli1iO))) & (~ ((~ comp_pat[32]) ^ nlli1li))) & (~ ((~ comp_pat[33]) ^ nlli1ll))) & (~ ((~ comp_pat[34]) ^ nlli1lO))) & (~ ((~ comp_pat[35]) ^ nlli1Oi))) & (~ ((~ comp_pat[36]) ^ nlli1Ol))) & (~ ((~ comp_pat[37]) ^ nlli1OO))) & (~ ((~ comp_pat[38]) ^ nlli01i))) & (~ ((~ comp_pat[39]) ^ nlli01l))), n11O0Oi = (n101l0l & (((comp_pat_porn & n11Oi1l) | n11Oi1i) & ((comp_pat_porn & n11O0OO) | n11O0Ol))), n11O0Ol = ((((((((((~ (comp_pat[20] ^ nll0OlO)) & (~ (comp_pat[21] ^ nll0OOi))) & (~ (comp_pat[22] ^ nll0OOl))) & (~ (comp_pat[23] ^ nll0OOO))) & (~ (comp_pat[24] ^ nlli11i))) & (~ (comp_pat[25] ^ nlli11l))) & (~ (comp_pat[26] ^ nlli11O))) & (~ (comp_pat[27] ^ nlli10i))) & (~ (comp_pat[28] ^ nlli10l))) & (~ (comp_pat[29] ^ nlli10O))), n11O0OO = ((((((((((~ ((~ comp_pat[20]) ^ nll0OlO)) & (~ ((~ comp_pat[21]) ^ nll0OOi))) & (~ ((~ comp_pat[22]) ^ nll0OOl))) & (~ ((~ comp_pat[23]) ^ nll0OOO))) & (~ ((~ comp_pat[24]) ^ nlli11i))) & (~ ((~ comp_pat[25]) ^ nlli11l))) & (~ ((~ comp_pat[26]) ^ nlli11O))) & (~ ((~ comp_pat[27]) ^ nlli10i))) & (~ ((~ comp_pat[28]) ^ nlli10l))) & (~ ((~ comp_pat[29]) ^ nlli10O))), n11O10i = ((((((((~ ((~ comp_pat[0]) ^ nll0iiO)) & (~ ((~ comp_pat[1]) ^ nll0ili))) & (~ ((~ comp_pat[2]) ^ nll0ill))) & (~ ((~ comp_pat[3]) ^ nll0ilO))) & (~ ((~ comp_pat[4]) ^ nll0iOi))) & (~ ((~ comp_pat[5]) ^ nll0iOl))) & (~ ((~ comp_pat[6]) ^ nll0iOO))) & (~ ((~ comp_pat[7]) ^ nll0l1i))), n11O10l = ((comp_pat_porn & n11O1ii) | n11O10O), n11O10O = ((((((((~ (comp_pat[0] ^ nll0iil)) & (~ (comp_pat[1] ^ nll0iiO))) & (~ (comp_pat[2] ^ nll0ili))) & (~ (comp_pat[3] ^ nll0ill))) & (~ (comp_pat[4] ^ nll0ilO))) & (~ (comp_pat[5] ^ nll0iOi))) & (~ (comp_pat[6] ^ nll0iOl))) & (~ (comp_pat[7] ^ nll0iOO))), n11O11i = ((((((((~ ((~ comp_pat[0]) ^ nll0ili)) & (~ ((~ comp_pat[1]) ^ nll0ill))) & (~ ((~ comp_pat[2]) ^ nll0ilO))) & (~ ((~ comp_pat[3]) ^ nll0iOi))) & (~ ((~ comp_pat[4]) ^ nll0iOl))) & (~ ((~ comp_pat[5]) ^ nll0iOO))) & (~ ((~ comp_pat[6]) ^ nll0l1i))) & (~ ((~ comp_pat[7]) ^ nll0l1l))), n11O11l = ((comp_pat_porn & n11O10i) | n11O11O), n11O11O = ((((((((~ (comp_pat[0] ^ nll0iiO)) & (~ (comp_pat[1] ^ nll0ili))) & (~ (comp_pat[2] ^ nll0ill))) & (~ (comp_pat[3] ^ nll0ilO))) & (~ (comp_pat[4] ^ nll0iOi))) & (~ (comp_pat[5] ^ nll0iOl))) & (~ (comp_pat[6] ^ nll0iOO))) & (~ (comp_pat[7] ^ nll0l1i))), n11O1ii = ((((((((~ ((~ comp_pat[0]) ^ nll0iil)) & (~ ((~ comp_pat[1]) ^ nll0iiO))) & (~ ((~ comp_pat[2]) ^ nll0ili))) & (~ ((~ comp_pat[3]) ^ nll0ill))) & (~ ((~ comp_pat[4]) ^ nll0ilO))) & (~ ((~ comp_pat[5]) ^ nll0iOi))) & (~ ((~ comp_pat[6]) ^ nll0iOl))) & (~ ((~ comp_pat[7]) ^ nll0iOO))), n11O1il = ((comp_pat_porn & n11O1li) | n11O1iO), n11O1iO = ((((((((~ (comp_pat[0] ^ nll0iii)) & (~ (comp_pat[1] ^ nll0iil))) & (~ (comp_pat[2] ^ nll0iiO))) & (~ (comp_pat[3] ^ nll0ili))) & (~ (comp_pat[4] ^ nll0ill))) & (~ (comp_pat[5] ^ nll0ilO))) & (~ (comp_pat[6] ^ nll0iOi))) & (~ (comp_pat[7] ^ nll0iOl))), n11O1li = ((((((((~ ((~ comp_pat[0]) ^ nll0iii)) & (~ ((~ comp_pat[1]) ^ nll0iil))) & (~ ((~ comp_pat[2]) ^ nll0iiO))) & (~ ((~ comp_pat[3]) ^ nll0ili))) & (~ ((~ comp_pat[4]) ^ nll0ill))) & (~ ((~ comp_pat[5]) ^ nll0ilO))) & (~ ((~ comp_pat[6]) ^ nll0iOi))) & (~ ((~ comp_pat[7]) ^ nll0iOl))), n11O1ll = ((comp_pat_porn & n11O1Oi) | n11O1lO), n11O1lO = ((((((((~ (comp_pat[0] ^ nll0i0O)) & (~ (comp_pat[1] ^ nll0iii))) & (~ (comp_pat[2] ^ nll0iil))) & (~ (comp_pat[3] ^ nll0iiO))) & (~ (comp_pat[4] ^ nll0ili))) & (~ (comp_pat[5] ^ nll0ill))) & (~ (comp_pat[6] ^ nll0ilO))) & (~ (comp_pat[7] ^ nll0iOi))), n11O1Oi = ((((((((~ ((~ comp_pat[0]) ^ nll0i0O)) & (~ ((~ comp_pat[1]) ^ nll0iii))) & (~ ((~ comp_pat[2]) ^ nll0iil))) & (~ ((~ comp_pat[3]) ^ nll0iiO))) & (~ ((~ comp_pat[4]) ^ nll0ili))) & (~ ((~ comp_pat[5]) ^ nll0ill))) & (~ ((~ comp_pat[6]) ^ nll0ilO))) & (~ ((~ comp_pat[7]) ^ nll0iOi))), n11O1Ol = ((comp_pat_porn & n11O01i) | n11O1OO), n11O1OO = ((((((((~ (comp_pat[0] ^ nll0i0l)) & (~ (comp_pat[1] ^ nll0i0O))) & (~ (comp_pat[2] ^ nll0iii))) & (~ (comp_pat[3] ^ nll0iil))) & (~ (comp_pat[4] ^ nll0iiO))) & (~ (comp_pat[5] ^ nll0ili))) & (~ (comp_pat[6] ^ nll0ill))) & (~ (comp_pat[7] ^ nll0ilO))), n11Oi0i = ((((((((((~ (comp_pat[20] ^ nll0Oll)) & (~ (comp_pat[21] ^ nll0OlO))) & (~ (comp_pat[22] ^ nll0OOi))) & (~ (comp_pat[23] ^ nll0OOl))) & (~ (comp_pat[24] ^ nll0OOO))) & (~ (comp_pat[25] ^ nlli11i))) & (~ (comp_pat[26] ^ nlli11l))) & (~ (comp_pat[27] ^ nlli11O))) & (~ (comp_pat[28] ^ nlli10i))) & (~ (comp_pat[29] ^ nlli10l))), n11Oi0l = ((((((((((~ ((~ comp_pat[20]) ^ nll0Oll)) & (~ ((~ comp_pat[21]) ^ nll0OlO))) & (~ ((~ comp_pat[22]) ^ nll0OOi))) & (~ ((~ comp_pat[23]) ^ nll0OOl))) & (~ ((~ comp_pat[24]) ^ nll0OOO))) & (~ ((~ comp_pat[25]) ^ nlli11i))) & (~ ((~ comp_pat[26]) ^ nlli11l))) & (~ ((~ comp_pat[27]) ^ nlli11O))) & (~ ((~ comp_pat[28]) ^ nlli10i))) & (~ ((~ comp_pat[29]) ^ nlli10l))), n11Oi0O = ((((((((((~ (comp_pat[30] ^ nlli10O)) & (~ (comp_pat[31] ^ nlli1ii))) & (~ (comp_pat[32] ^ nlli1il))) & (~ (comp_pat[33] ^ nlli1iO))) & (~ (comp_pat[34] ^ nlli1li))) & (~ (comp_pat[35] ^ nlli1ll))) & (~ (comp_pat[36] ^ nlli1lO))) & (~ (comp_pat[37] ^ nlli1Oi))) & (~ (comp_pat[38] ^ nlli1Ol))) & (~ (comp_pat[39] ^ nlli1OO))), n11Oi1i = ((((((((((~ (comp_pat[30] ^ nlli1ii)) & (~ (comp_pat[31] ^ nlli1il))) & (~ (comp_pat[32] ^ nlli1iO))) & (~ (comp_pat[33] ^ nlli1li))) & (~ (comp_pat[34] ^ nlli1ll))) & (~ (comp_pat[35] ^ nlli1lO))) & (~ (comp_pat[36] ^ nlli1Oi))) & (~ (comp_pat[37] ^ nlli1Ol))) & (~ (comp_pat[38] ^ nlli1OO))) & (~ (comp_pat[39] ^ nlli01i))), n11Oi1l = ((((((((((~ ((~ comp_pat[30]) ^ nlli1ii)) & (~ ((~ comp_pat[31]) ^ nlli1il))) & (~ ((~ comp_pat[32]) ^ nlli1iO))) & (~ ((~ comp_pat[33]) ^ nlli1li))) & (~ ((~ comp_pat[34]) ^ nlli1ll))) & (~ ((~ comp_pat[35]) ^ nlli1lO))) & (~ ((~ comp_pat[36]) ^ nlli1Oi))) & (~ ((~ comp_pat[37]) ^ nlli1Ol))) & (~ ((~ comp_pat[38]) ^ nlli1OO))) & (~ ((~ comp_pat[39]) ^ nlli01i))), n11Oi1O = (n101lil & (((comp_pat_porn & n11Oiii) | n11Oi0O) & ((comp_pat_porn & n11Oi0l) | n11Oi0i))), n11Oiii = ((((((((((~ ((~ comp_pat[30]) ^ nlli10O)) & (~ ((~ comp_pat[31]) ^ nlli1ii))) & (~ ((~ comp_pat[32]) ^ nlli1il))) & (~ ((~ comp_pat[33]) ^ nlli1iO))) & (~ ((~ comp_pat[34]) ^ nlli1li))) & (~ ((~ comp_pat[35]) ^ nlli1ll))) & (~ ((~ comp_pat[36]) ^ nlli1lO))) & (~ ((~ comp_pat[37]) ^ nlli1Oi))) & (~ ((~ comp_pat[38]) ^ nlli1Ol))) & (~ ((~ comp_pat[39]) ^ nlli1OO))), n11Oiil = (n101lll & (((comp_pat_porn & n11OilO) | n11Oill) & ((comp_pat_porn & n11Oili) | n11OiiO))), n11OiiO = ((((((((((~ (comp_pat[20] ^ nll0Oli)) & (~ (comp_pat[21] ^ nll0Oll))) & (~ (comp_pat[22] ^ nll0OlO))) & (~ (comp_pat[23] ^ nll0OOi))) & (~ (comp_pat[24] ^ nll0OOl))) & (~ (comp_pat[25] ^ nll0OOO))) & (~ (comp_pat[26] ^ nlli11i))) & (~ (comp_pat[27] ^ nlli11l))) & (~ (comp_pat[28] ^ nlli11O))) & (~ (comp_pat[29] ^ nlli10i))), n11Oili = ((((((((((~ ((~ comp_pat[20]) ^ nll0Oli)) & (~ ((~ comp_pat[21]) ^ nll0Oll))) & (~ ((~ comp_pat[22]) ^ nll0OlO))) & (~ ((~ comp_pat[23]) ^ nll0OOi))) & (~ ((~ comp_pat[24]) ^ nll0OOl))) & (~ ((~ comp_pat[25]) ^ nll0OOO))) & (~ ((~ comp_pat[26]) ^ nlli11i))) & (~ ((~ comp_pat[27]) ^ nlli11l))) & (~ ((~ comp_pat[28]) ^ nlli11O))) & (~ ((~ comp_pat[29]) ^ nlli10i))), n11Oill = ((((((((((~ (comp_pat[30] ^ nlli10l)) & (~ (comp_pat[31] ^ nlli10O))) & (~ (comp_pat[32] ^ nlli1ii))) & (~ (comp_pat[33] ^ nlli1il))) & (~ (comp_pat[34] ^ nlli1iO))) & (~ (comp_pat[35] ^ nlli1li))) & (~ (comp_pat[36] ^ nlli1ll))) & (~ (comp_pat[37] ^ nlli1lO))) & (~ (comp_pat[38] ^ nlli1Oi))) & (~ (comp_pat[39] ^ nlli1Ol))), n11OilO = ((((((((((~ ((~ comp_pat[30]) ^ nlli10l)) & (~ ((~ comp_pat[31]) ^ nlli10O))) & (~ ((~ comp_pat[32]) ^ nlli1ii))) & (~ ((~ comp_pat[33]) ^ nlli1il))) & (~ ((~ comp_pat[34]) ^ nlli1iO))) & (~ ((~ comp_pat[35]) ^ nlli1li))) & (~ ((~ comp_pat[36]) ^ nlli1ll))) & (~ ((~ comp_pat[37]) ^ nlli1lO))) & (~ ((~ comp_pat[38]) ^ nlli1Oi))) & (~ ((~ comp_pat[39]) ^ nlli1Ol))), n11OiOi = (n101lOl & (((comp_pat_porn & n11Ol1l) | n11Ol1i) & ((comp_pat_porn & n11OiOO) | n11OiOl))), n11OiOl = ((((((((((~ (comp_pat[20] ^ nll0OiO)) & (~ (comp_pat[21] ^ nll0Oli))) & (~ (comp_pat[22] ^ nll0Oll))) & (~ (comp_pat[23] ^ nll0OlO))) & (~ (comp_pat[24] ^ nll0OOi))) & (~ (comp_pat[25] ^ nll0OOl))) & (~ (comp_pat[26] ^ nll0OOO))) & (~ (comp_pat[27] ^ nlli11i))) & (~ (comp_pat[28] ^ nlli11l))) & (~ (comp_pat[29] ^ nlli11O))), n11OiOO = ((((((((((~ ((~ comp_pat[20]) ^ nll0OiO)) & (~ ((~ comp_pat[21]) ^ nll0Oli))) & (~ ((~ comp_pat[22]) ^ nll0Oll))) & (~ ((~ comp_pat[23]) ^ nll0OlO))) & (~ ((~ comp_pat[24]) ^ nll0OOi))) & (~ ((~ comp_pat[25]) ^ nll0OOl))) & (~ ((~ comp_pat[26]) ^ nll0OOO))) & (~ ((~ comp_pat[27]) ^ nlli11i))) & (~ ((~ comp_pat[28]) ^ nlli11l))) & (~ ((~ comp_pat[29]) ^ nlli11O))), n11Ol0i = ((((((((((~ (comp_pat[20] ^ nll0Oil)) & (~ (comp_pat[21] ^ nll0OiO))) & (~ (comp_pat[22] ^ nll0Oli))) & (~ (comp_pat[23] ^ nll0Oll))) & (~ (comp_pat[24] ^ nll0OlO))) & (~ (comp_pat[25] ^ nll0OOi))) & (~ (comp_pat[26] ^ nll0OOl))) & (~ (comp_pat[27] ^ nll0OOO))) & (~ (comp_pat[28] ^ nlli11i))) & (~ (comp_pat[29] ^ nlli11l))), n11Ol0l = ((((((((((~ ((~ comp_pat[20]) ^ nll0Oil)) & (~ ((~ comp_pat[21]) ^ nll0OiO))) & (~ ((~ comp_pat[22]) ^ nll0Oli))) & (~ ((~ comp_pat[23]) ^ nll0Oll))) & (~ ((~ comp_pat[24]) ^ nll0OlO))) & (~ ((~ comp_pat[25]) ^ nll0OOi))) & (~ ((~ comp_pat[26]) ^ nll0OOl))) & (~ ((~ comp_pat[27]) ^ nll0OOO))) & (~ ((~ comp_pat[28]) ^ nlli11i))) & (~ ((~ comp_pat[29]) ^ nlli11l))), n11Ol0O = ((((((((((~ (comp_pat[30] ^ nlli11O)) & (~ (comp_pat[31] ^ nlli10i))) & (~ (comp_pat[32] ^ nlli10l))) & (~ (comp_pat[33] ^ nlli10O))) & (~ (comp_pat[34] ^ nlli1ii))) & (~ (comp_pat[35] ^ nlli1il))) & (~ (comp_pat[36] ^ nlli1iO))) & (~ (comp_pat[37] ^ nlli1li))) & (~ (comp_pat[38] ^ nlli1ll))) & (~ (comp_pat[39] ^ nlli1lO))), n11Ol1i = ((((((((((~ (comp_pat[30] ^ nlli10i)) & (~ (comp_pat[31] ^ nlli10l))) & (~ (comp_pat[32] ^ nlli10O))) & (~ (comp_pat[33] ^ nlli1ii))) & (~ (comp_pat[34] ^ nlli1il))) & (~ (comp_pat[35] ^ nlli1iO))) & (~ (comp_pat[36] ^ nlli1li))) & (~ (comp_pat[37] ^ nlli1ll))) & (~ (comp_pat[38] ^ nlli1lO))) & (~ (comp_pat[39] ^ nlli1Oi))), n11Ol1l = ((((((((((~ ((~ comp_pat[30]) ^ nlli10i)) & (~ ((~ comp_pat[31]) ^ nlli10l))) & (~ ((~ comp_pat[32]) ^ nlli10O))) & (~ ((~ comp_pat[33]) ^ nlli1ii))) & (~ ((~ comp_pat[34]) ^ nlli1il))) & (~ ((~ comp_pat[35]) ^ nlli1iO))) & (~ ((~ comp_pat[36]) ^ nlli1li))) & (~ ((~ comp_pat[37]) ^ nlli1ll))) & (~ ((~ comp_pat[38]) ^ nlli1lO))) & (~ ((~ comp_pat[39]) ^ nlli1Oi))), n11Ol1O = (n101O1l & (((comp_pat_porn & n11Olii) | n11Ol0O) & ((comp_pat_porn & n11Ol0l) | n11Ol0i))), n11Olii = ((((((((((~ ((~ comp_pat[30]) ^ nlli11O)) & (~ ((~ comp_pat[31]) ^ nlli10i))) & (~ ((~ comp_pat[32]) ^ nlli10l))) & (~ ((~ comp_pat[33]) ^ nlli10O))) & (~ ((~ comp_pat[34]) ^ nlli1ii))) & (~ ((~ comp_pat[35]) ^ nlli1il))) & (~ ((~ comp_pat[36]) ^ nlli1iO))) & (~ ((~ comp_pat[37]) ^ nlli1li))) & (~ ((~ comp_pat[38]) ^ nlli1ll))) & (~ ((~ comp_pat[39]) ^ nlli1lO))), n11Olil = (n101O0l & (((comp_pat_porn & n11OllO) | n11Olll) & ((comp_pat_porn & n11Olli) | n11OliO))), n11OliO = ((((((((((~ (comp_pat[20] ^ nll0Oii)) & (~ (comp_pat[21] ^ nll0Oil))) & (~ (comp_pat[22] ^ nll0OiO))) & (~ (comp_pat[23] ^ nll0Oli))) & (~ (comp_pat[24] ^ nll0Oll))) & (~ (comp_pat[25] ^ nll0OlO))) & (~ (comp_pat[26] ^ nll0OOi))) & (~ (comp_pat[27] ^ nll0OOl))) & (~ (comp_pat[28] ^ nll0OOO))) & (~ (comp_pat[29] ^ nlli11i))), n11Olli = ((((((((((~ ((~ comp_pat[20]) ^ nll0Oii)) & (~ ((~ comp_pat[21]) ^ nll0Oil))) & (~ ((~ comp_pat[22]) ^ nll0OiO))) & (~ ((~ comp_pat[23]) ^ nll0Oli))) & (~ ((~ comp_pat[24]) ^ nll0Oll))) & (~ ((~ comp_pat[25]) ^ nll0OlO))) & (~ ((~ comp_pat[26]) ^ nll0OOi))) & (~ ((~ comp_pat[27]) ^ nll0OOl))) & (~ ((~ comp_pat[28]) ^ nll0OOO))) & (~ ((~ comp_pat[29]) ^ nlli11i))), n11Olll = ((((((((((~ (comp_pat[30] ^ nlli11l)) & (~ (comp_pat[31] ^ nlli11O))) & (~ (comp_pat[32] ^ nlli10i))) & (~ (comp_pat[33] ^ nlli10l))) & (~ (comp_pat[34] ^ nlli10O))) & (~ (comp_pat[35] ^ nlli1ii))) & (~ (comp_pat[36] ^ nlli1il))) & (~ (comp_pat[37] ^ nlli1iO))) & (~ (comp_pat[38] ^ nlli1li))) & (~ (comp_pat[39] ^ nlli1ll))), n11OllO = ((((((((((~ ((~ comp_pat[30]) ^ nlli11l)) & (~ ((~ comp_pat[31]) ^ nlli11O))) & (~ ((~ comp_pat[32]) ^ nlli10i))) & (~ ((~ comp_pat[33]) ^ nlli10l))) & (~ ((~ comp_pat[34]) ^ nlli10O))) & (~ ((~ comp_pat[35]) ^ nlli1ii))) & (~ ((~ comp_pat[36]) ^ nlli1il))) & (~ ((~ comp_pat[37]) ^ nlli1iO))) & (~ ((~ comp_pat[38]) ^ nlli1li))) & (~ ((~ comp_pat[39]) ^ nlli1ll))), n11OlOi = (n101Oil & (((comp_pat_porn & n11OO1l) | n11OO1i) & ((comp_pat_porn & n11OlOO) | n11OlOl))), n11OlOl = ((((((((((~ (comp_pat[20] ^ nll0O0O)) & (~ (comp_pat[21] ^ nll0Oii))) & (~ (comp_pat[22] ^ nll0Oil))) & (~ (comp_pat[23] ^ nll0OiO))) & (~ (comp_pat[24] ^ nll0Oli))) & (~ (comp_pat[25] ^ nll0Oll))) & (~ (comp_pat[26] ^ nll0OlO))) & (~ (comp_pat[27] ^ nll0OOi))) & (~ (comp_pat[28] ^ nll0OOl))) & (~ (comp_pat[29] ^ nll0OOO))), n11OlOO = ((((((((((~ ((~ comp_pat[20]) ^ nll0O0O)) & (~ ((~ comp_pat[21]) ^ nll0Oii))) & (~ ((~ comp_pat[22]) ^ nll0Oil))) & (~ ((~ comp_pat[23]) ^ nll0OiO))) & (~ ((~ comp_pat[24]) ^ nll0Oli))) & (~ ((~ comp_pat[25]) ^ nll0Oll))) & (~ ((~ comp_pat[26]) ^ nll0OlO))) & (~ ((~ comp_pat[27]) ^ nll0OOi))) & (~ ((~ comp_pat[28]) ^ nll0OOl))) & (~ ((~ comp_pat[29]) ^ nll0OOO))), n11OO0i = ((((((((((~ (comp_pat[20] ^ nll0O0l)) & (~ (comp_pat[21] ^ nll0O0O))) & (~ (comp_pat[22] ^ nll0Oii))) & (~ (comp_pat[23] ^ nll0Oil))) & (~ (comp_pat[24] ^ nll0OiO))) & (~ (comp_pat[25] ^ nll0Oli))) & (~ (comp_pat[26] ^ nll0Oll))) & (~ (comp_pat[27] ^ nll0OlO))) & (~ (comp_pat[28] ^ nll0OOi))) & (~ (comp_pat[29] ^ nll0OOl))), n11OO0l = ((((((((((~ ((~ comp_pat[20]) ^ nll0O0l)) & (~ ((~ comp_pat[21]) ^ nll0O0O))) & (~ ((~ comp_pat[22]) ^ nll0Oii))) & (~ ((~ comp_pat[23]) ^ nll0Oil))) & (~ ((~ comp_pat[24]) ^ nll0OiO))) & (~ ((~ comp_pat[25]) ^ nll0Oli))) & (~ ((~ comp_pat[26]) ^ nll0Oll))) & (~ ((~ comp_pat[27]) ^ nll0OlO))) & (~ ((~ comp_pat[28]) ^ nll0OOi))) & (~ ((~ comp_pat[29]) ^ nll0OOl))), n11OO0O = ((((((((((~ (comp_pat[30] ^ nll0OOO)) & (~ (comp_pat[31] ^ nlli11i))) & (~ (comp_pat[32] ^ nlli11l))) & (~ (comp_pat[33] ^ nlli11O))) & (~ (comp_pat[34] ^ nlli10i))) & (~ (comp_pat[35] ^ nlli10l))) & (~ (comp_pat[36] ^ nlli10O))) & (~ (comp_pat[37] ^ nlli1ii))) & (~ (comp_pat[38] ^ nlli1il))) & (~ (comp_pat[39] ^ nlli1iO))), n11OO1i = ((((((((((~ (comp_pat[30] ^ nlli11i)) & (~ (comp_pat[31] ^ nlli11l))) & (~ (comp_pat[32] ^ nlli11O))) & (~ (comp_pat[33] ^ nlli10i))) & (~ (comp_pat[34] ^ nlli10l))) & (~ (comp_pat[35] ^ nlli10O))) & (~ (comp_pat[36] ^ nlli1ii))) & (~ (comp_pat[37] ^ nlli1il))) & (~ (comp_pat[38] ^ nlli1iO))) & (~ (comp_pat[39] ^ nlli1li))), n11OO1l = ((((((((((~ ((~ comp_pat[30]) ^ nlli11i)) & (~ ((~ comp_pat[31]) ^ nlli11l))) & (~ ((~ comp_pat[32]) ^ nlli11O))) & (~ ((~ comp_pat[33]) ^ nlli10i))) & (~ ((~ comp_pat[34]) ^ nlli10l))) & (~ ((~ comp_pat[35]) ^ nlli10O))) & (~ ((~ comp_pat[36]) ^ nlli1ii))) & (~ ((~ comp_pat[37]) ^ nlli1il))) & (~ ((~ comp_pat[38]) ^ nlli1iO))) & (~ ((~ comp_pat[39]) ^ nlli1li))), n11OO1O = (n101Oll & (((comp_pat_porn & n11OOii) | n11OO0O) & ((comp_pat_porn & n11OO0l) | n11OO0i))), n11OOii = ((((((((((~ ((~ comp_pat[30]) ^ nll0OOO)) & (~ ((~ comp_pat[31]) ^ nlli11i))) & (~ ((~ comp_pat[32]) ^ nlli11l))) & (~ ((~ comp_pat[33]) ^ nlli11O))) & (~ ((~ comp_pat[34]) ^ nlli10i))) & (~ ((~ comp_pat[35]) ^ nlli10l))) & (~ ((~ comp_pat[36]) ^ nlli10O))) & (~ ((~ comp_pat[37]) ^ nlli1ii))) & (~ ((~ comp_pat[38]) ^ nlli1il))) & (~ ((~ comp_pat[39]) ^ nlli1iO))), n11OOil = (n101OOl & (((comp_pat_porn & n11OOlO) | n11OOll) & ((comp_pat_porn & n11OOli) | n11OOiO))), n11OOiO = ((((((((((~ (comp_pat[20] ^ nll0O0i)) & (~ (comp_pat[21] ^ nll0O0l))) & (~ (comp_pat[22] ^ nll0O0O))) & (~ (comp_pat[23] ^ nll0Oii))) & (~ (comp_pat[24] ^ nll0Oil))) & (~ (comp_pat[25] ^ nll0OiO))) & (~ (comp_pat[26] ^ nll0Oli))) & (~ (comp_pat[27] ^ nll0Oll))) & (~ (comp_pat[28] ^ nll0OlO))) & (~ (comp_pat[29] ^ nll0OOi))), n11OOli = ((((((((((~ ((~ comp_pat[20]) ^ nll0O0i)) & (~ ((~ comp_pat[21]) ^ nll0O0l))) & (~ ((~ comp_pat[22]) ^ nll0O0O))) & (~ ((~ comp_pat[23]) ^ nll0Oii))) & (~ ((~ comp_pat[24]) ^ nll0Oil))) & (~ ((~ comp_pat[25]) ^ nll0OiO))) & (~ ((~ comp_pat[26]) ^ nll0Oli))) & (~ ((~ comp_pat[27]) ^ nll0Oll))) & (~ ((~ comp_pat[28]) ^ nll0OlO))) & (~ ((~ comp_pat[29]) ^ nll0OOi))), n11OOll = ((((((((((~ (comp_pat[30] ^ nll0OOl)) & (~ (comp_pat[31] ^ nll0OOO))) & (~ (comp_pat[32] ^ nlli11i))) & (~ (comp_pat[33] ^ nlli11l))) & (~ (comp_pat[34] ^ nlli11O))) & (~ (comp_pat[35] ^ nlli10i))) & (~ (comp_pat[36] ^ nlli10l))) & (~ (comp_pat[37] ^ nlli10O))) & (~ (comp_pat[38] ^ nlli1ii))) & (~ (comp_pat[39] ^ nlli1il))), n11OOlO = ((((((((((~ ((~ comp_pat[30]) ^ nll0OOl)) & (~ ((~ comp_pat[31]) ^ nll0OOO))) & (~ ((~ comp_pat[32]) ^ nlli11i))) & (~ ((~ comp_pat[33]) ^ nlli11l))) & (~ ((~ comp_pat[34]) ^ nlli11O))) & (~ ((~ comp_pat[35]) ^ nlli10i))) & (~ ((~ comp_pat[36]) ^ nlli10l))) & (~ ((~ comp_pat[37]) ^ nlli10O))) & (~ ((~ comp_pat[38]) ^ nlli1ii))) & (~ ((~ comp_pat[39]) ^ nlli1il))), n11OOOi = (n10011l & (((comp_pat_porn & n10111l) | n10111i) & ((comp_pat_porn & n11OOOO) | n11OOOl))), n11OOOl = ((((((((((~ (comp_pat[20] ^ nll0O1O)) & (~ (comp_pat[21] ^ nll0O0i))) & (~ (comp_pat[22] ^ nll0O0l))) & (~ (comp_pat[23] ^ nll0O0O))) & (~ (comp_pat[24] ^ nll0Oii))) & (~ (comp_pat[25] ^ nll0Oil))) & (~ (comp_pat[26] ^ nll0OiO))) & (~ (comp_pat[27] ^ nll0Oli))) & (~ (comp_pat[28] ^ nll0Oll))) & (~ (comp_pat[29] ^ nll0OlO))), n11OOOO = ((((((((((~ ((~ comp_pat[20]) ^ nll0O1O)) & (~ ((~ comp_pat[21]) ^ nll0O0i))) & (~ ((~ comp_pat[22]) ^ nll0O0l))) & (~ ((~ comp_pat[23]) ^ nll0O0O))) & (~ ((~ comp_pat[24]) ^ nll0Oii))) & (~ ((~ comp_pat[25]) ^ nll0Oil))) & (~ ((~ comp_pat[26]) ^ nll0OiO))) & (~ ((~ comp_pat[27]) ^ nll0Oli))) & (~ ((~ comp_pat[28]) ^ nll0Oll))) & (~ ((~ comp_pat[29]) ^ nll0OlO))), n1i000i = (n10llOi & n10llOl), n1i000l = (((~ wire_niOl1i_o) & wire_niOiOO_o) | (wire_niOl1i_o & (~ wire_niOiOO_o))), n1i000O = (((((~ wire_niOiOl_o) & ((~ wire_niOiOi_o) & ((~ wire_niOilO_o) & wire_niOill_o))) | ((~ wire_niOiOl_o) & ((~ wire_niOiOi_o) & (wire_niOilO_o & (~ wire_niOill_o))))) | ((~ wire_niOiOl_o) & (wire_niOiOi_o & n10lliO))) | (wire_niOiOl_o & ((~ wire_niOiOi_o) & n10lliO))), n1i001i = (n10lO1i & n1i00ii), n1i001l = ((((n10lOOO | (n1i00il & n10llOl)) | (n10lO1i & n1i000l)) | n10lOOl) | n10O11i), n1i001O = (wire_niOiOl_o & n10lllO), n1i00ii = ((~ wire_niOl1i_o) & (~ wire_niOiOO_o)), n1i00il = (((((((~ wire_niOiOl_o) & ((~ wire_niOiOi_o) & (wire_niOilO_o & wire_niOill_o))) | ((~ wire_niOiOl_o) & (wire_niOiOi_o & n10llll))) | ((~ wire_niOiOl_o) & (wire_niOiOi_o & n10llli))) | (wire_niOiOl_o & ((~ wire_niOiOi_o) & n10llll))) | (wire_niOiOl_o & ((~ wire_niOiOi_o) & n10llli))) | (wire_niOiOl_o & (wire_niOiOi_o & ((~ wire_niOilO_o) & (~ wire_niOill_o))))), n1i00iO = (n1i000O & n1i00ii), n1i00li = (n10llOi & n1i000l), n1i00ll = (n10llOi & n1i00ii), n1i00lO = (n1i00Ol | n1i00Oi), n1i00Oi = (pmadwidth[0] & nill0l), n1i00Ol = ((~ pmadwidth[0]) & nill0l), n1i010i = ((((((((~ (comp_pat[0] ^ wire_nilllO_dataout)) & (~ (comp_pat[1] ^ wire_nillOi_dataout))) & (~ (comp_pat[2] ^ wire_nillOl_dataout))) & (~ (comp_pat[3] ^ wire_nillOO_dataout))) & (~ (comp_pat[4] ^ wire_nilO1i_dataout))) & (~ (comp_pat[5] ^ wire_nilO1l_dataout))) & (~ (comp_pat[6] ^ wire_nilO1O_dataout))) & (~ (comp_pat[7] ^ wire_nilO0i_dataout))), n1i010l = ((~ pmadwidth[0]) & (~ n1i01ii)), n1i010O = (nl1l1l & ((~ pmadwidth[0]) & nl1lii)), n1i011i = (((((((~ ((~ comp_pat[0]) ^ wire_nilllO_dataout)) & (~ ((~ comp_pat[1]) ^ wire_nillOi_dataout))) & (~ ((~ comp_pat[2]) ^ wire_nillOl_dataout))) & (~ ((~ comp_pat[3]) ^ wire_nillOO_dataout))) & (~ ((~ comp_pat[4]) ^ wire_nilO1i_dataout))) & (~ ((~ comp_pat[5]) ^ wire_nilO1l_dataout))) & (~ ((~ comp_pat[6]) ^ wire_nilO1O_dataout))), n1i011l = (((((((~ (comp_pat[0] ^ wire_nilllO_dataout)) & (~ (comp_pat[1] ^ wire_nillOi_dataout))) & (~ (comp_pat[2] ^ wire_nillOl_dataout))) & (~ (comp_pat[3] ^ wire_nillOO_dataout))) & (~ (comp_pat[4] ^ wire_nilO1i_dataout))) & (~ (comp_pat[5] ^ wire_nilO1l_dataout))) & (~ (comp_pat[6] ^ wire_nilO1O_dataout))), n1i011O = ((((((((~ (comp_pat[8] ^ wire_nilllO_dataout)) & (~ (comp_pat[9] ^ wire_nillOi_dataout))) & (~ (comp_pat[10] ^ wire_nillOl_dataout))) & (~ (comp_pat[11] ^ wire_nillOO_dataout))) & (~ (comp_pat[12] ^ wire_nilO1i_dataout))) & (~ (comp_pat[13] ^ wire_nilO1l_dataout))) & (~ (comp_pat[14] ^ wire_nilO1O_dataout))) & (~ (comp_pat[15] ^ wire_nilO0i_dataout))), n1i01ii = (nl1lii & nl1l1l), n1i01il = (n1i01li | n1i01iO), n1i01iO = (nl1lii & (~ nl1l1l)), n1i01li = (nl1lii & nl1l1l), n1i01ll = (((((((~ wire_niOl0l_dataout) & ((~ wire_niOl0i_dataout) & (wire_niOl1O_o & wire_niOl1l_o))) | ((~ wire_niOl0l_dataout) & (wire_niOl0i_dataout & n10lO0l))) | ((~ wire_niOl0l_dataout) & (wire_niOl0i_dataout & n10lO0i))) | (wire_niOl0l_dataout & ((~ wire_niOl0i_dataout) & n10lO0l))) | (wire_niOl0l_dataout & ((~ wire_niOl0i_dataout) & n10lO0i))) | (wire_niOl0l_dataout & (wire_niOl0i_dataout & ((~ wire_niOl1O_o) & (~ wire_niOl1l_o))))), n1i01lO = (n10lOll | n10lOOi), n1i01Oi = ((~ wire_niOl0l_dataout) & ((~ wire_niOl0i_dataout) & ((~ wire_niOl1O_o) & (~ wire_niOl1l_o)))), n1i01Ol = (((((~ wire_niOl0l_dataout) & ((~ wire_niOl0i_dataout) & ((~ wire_niOl1O_o) & wire_niOl1l_o))) | ((~ wire_niOl0l_dataout) & ((~ wire_niOl0i_dataout) & (wire_niOl1O_o & (~ wire_niOl1l_o))))) | ((~ wire_niOl0l_dataout) & (wire_niOl0i_dataout & n10lO1O))) | (wire_niOl0l_dataout & ((~ wire_niOl0i_dataout) & n10lO1O))), n1i01OO = ((~ wire_niOl1O_o) & ((~ wire_niOl1l_o) & n1i01ll)), n1i0i0i = (((((((((wire_nl011O_dataout | (~ n1i0iOi)) | (~ n1i0ilO)) | (~ n1i0ill)) | (~ n1i0ili)) | (~ n1i0iiO)) | (~ n1i0iil)) | (~ n1i0iii)) | (~ n1i0i0O)) | n1i0i0l), n1i0i0l = (((((((((wire_nl00Oi_dataout & (~ wire_nl00li_dataout)) & (~ wire_nl00ii_dataout)) & (~ wire_nl000i_dataout)) & (~ wire_nl001i_dataout)) & (~ wire_nl01Oi_dataout)) & (~ wire_nl01li_dataout)) & (~ wire_nl01ii_dataout)) & (~ wire_nl010l_dataout)) & (~ wire_nl011O_dataout)), n1i0i0O = (((((((((~ wire_nl00li_dataout) | wire_nl00ii_dataout) | wire_nl000i_dataout) | wire_nl001i_dataout) | wire_nl01Oi_dataout) | wire_nl01li_dataout) | wire_nl01ii_dataout) | wire_nl010l_dataout) | wire_nl011O_dataout), n1i0i1i = ((~ pmadwidth[0]) & n1i0i1O), n1i0i1l = (pmadwidth[0] & n1i0i1O), n1i0i1O = ((((~ nl10Oi) & (~ nl10ll)) & (~ nl10li)) & (~ nl10il)), n1i0iii = ((((((((~ wire_nl00ii_dataout) | wire_nl000i_dataout) | wire_nl001i_dataout) | wire_nl01Oi_dataout) | wire_nl01li_dataout) | wire_nl01ii_dataout) | wire_nl010l_dataout) | wire_nl011O_dataout), n1i0iil = (((((((~ wire_nl000i_dataout) | wire_nl001i_dataout) | wire_nl01Oi_dataout) | wire_nl01li_dataout) | wire_nl01ii_dataout) | wire_nl010l_dataout) | wire_nl011O_dataout), n1i0iiO = ((((((~ wire_nl001i_dataout) | wire_nl01Oi_dataout) | wire_nl01li_dataout) | wire_nl01ii_dataout) | wire_nl010l_dataout) | wire_nl011O_dataout), n1i0ili = (((((~ wire_nl01Oi_dataout) | wire_nl01li_dataout) | wire_nl01ii_dataout) | wire_nl010l_dataout) | wire_nl011O_dataout), n1i0ill = ((((~ wire_nl01li_dataout) | wire_nl01ii_dataout) | wire_nl010l_dataout) | wire_nl011O_dataout), n1i0ilO = (((~ wire_nl01ii_dataout) | wire_nl010l_dataout) | wire_nl011O_dataout), n1i0iOi = ((~ wire_nl010l_dataout) | wire_nl011O_dataout), n1i0iOl = ((((((((((~ (wire_nli00i_dataout ^ wire_nl0i1i_dataout)) & (~ (wire_nli00l_dataout ^ wire_nl0i1l_dataout))) & (~ (wire_nli00O_dataout ^ wire_nl0i1O_dataout))) & (~ (wire_nli0ii_dataout ^ wire_nl0i0i_dataout))) & (~ (wire_nli0il_dataout ^ wire_nl0i0l_dataout))) & (~ (wire_nli0iO_dataout ^ wire_nl0i0O_dataout))) & (~ (wire_nli0li_dataout ^ wire_nl0iii_dataout))) & (~ (wire_nli0ll_dataout ^ wire_nl0iil_dataout))) & (~ (wire_nli0lO_dataout ^ wire_nl0iiO_dataout))) & (~ (wire_nli0Oi_dataout ^ wire_nl0ili_dataout))), n1i0iOO = ((((((((((~ (comp_pat[0] ^ wire_nl0i1i_dataout)) & (~ (comp_pat[1] ^ wire_nl0i1l_dataout))) & (~ (comp_pat[2] ^ wire_nl0i1O_dataout))) & (~ (comp_pat[3] ^ wire_nl0i0i_dataout))) & (~ (comp_pat[4] ^ wire_nl0i0l_dataout))) & (~ (comp_pat[5] ^ wire_nl0i0O_dataout))) & (~ (comp_pat[6] ^ wire_nl0iii_dataout))) & (~ (wire_nliiiO_dataout ^ wire_nl0iil_dataout))) & (~ (wire_nliili_dataout ^ wire_nl0iiO_dataout))) & (~ (wire_nliill_dataout ^ wire_nl0ili_dataout))), n1i0l0i = ((((((((((~ (comp_pat[0] ^ nliO0l)) & (~ (comp_pat[1] ^ nliO0O))) & (~ (comp_pat[2] ^ nliOii))) & (~ (comp_pat[3] ^ nliOil))) & (~ (comp_pat[4] ^ nliOiO))) & (~ (comp_pat[5] ^ nliOli))) & (~ (comp_pat[6] ^ nliOll))) & (~ (wire_nliiiO_dataout ^ wire_nl0O1l_dataout))) & (~ (wire_nliili_dataout ^ wire_nl0O1O_dataout))) & (~ (wire_nliill_dataout ^ wire_nl0O0i_dataout))), n1i0l0l = ((((((((((~ (nliO0O ^ wire_nli00i_dataout)) & (~ (nliOii ^ wire_nli00l_dataout))) & (~ (nliOil ^ wire_nli00O_dataout))) & (~ (nliOiO ^ wire_nli0ii_dataout))) & (~ (nliOli ^ wire_nli0il_dataout))) & (~ (nliOll ^ wire_nli0iO_dataout))) & (~ (nliOlO ^ wire_nli0li_dataout))) & (~ (wire_nli0ll_dataout ^ wire_nl0O0O_dataout))) & (~ (wire_nli0lO_dataout ^ wire_nl0Oii_dataout))) & (~ (wire_nli0Oi_dataout ^ wire_nl0Oil_dataout))), n1i0l0O = ((((((((((~ (comp_pat[0] ^ nliO0O)) & (~ (comp_pat[1] ^ nliOii))) & (~ (comp_pat[2] ^ nliOil))) & (~ (comp_pat[3] ^ nliOiO))) & (~ (comp_pat[4] ^ nliOli))) & (~ (comp_pat[5] ^ nliOll))) & (~ (comp_pat[6] ^ nliOlO))) & (~ (wire_nliiiO_dataout ^ wire_nl0O0O_dataout))) & (~ (wire_nliili_dataout ^ wire_nl0Oii_dataout))) & (~ (wire_nliill_dataout ^ wire_nl0Oil_dataout))), n1i0l1i = ((((((((((~ (wire_nli00i_dataout ^ wire_nl0l0O_dataout)) & (~ (wire_nli00l_dataout ^ wire_nl0lii_dataout))) & (~ (wire_nli00O_dataout ^ wire_nl0lil_dataout))) & (~ (wire_nli0ii_dataout ^ wire_nl0liO_dataout))) & (~ (wire_nli0il_dataout ^ wire_nl0lli_dataout))) & (~ (wire_nli0iO_dataout ^ wire_nl0lll_dataout))) & (~ (wire_nli0li_dataout ^ wire_nl0llO_dataout))) & (~ (wire_nli0ll_dataout ^ wire_nl0lOi_dataout))) & (~ (wire_nli0lO_dataout ^ wire_nl0lOl_dataout))) & (~ (wire_nli0Oi_dataout ^ wire_nl0lOO_dataout))), n1i0l1l = ((((((((((~ (comp_pat[0] ^ wire_nl0l0O_dataout)) & (~ (comp_pat[1] ^ wire_nl0lii_dataout))) & (~ (comp_pat[2] ^ wire_nl0lil_dataout))) & (~ (comp_pat[3] ^ wire_nl0liO_dataout))) & (~ (comp_pat[4] ^ wire_nl0lli_dataout))) & (~ (comp_pat[5] ^ wire_nl0lll_dataout))) & (~ (comp_pat[6] ^ wire_nl0llO_dataout))) & (~ (wire_nliiiO_dataout ^ wire_nl0lOi_dataout))) & (~ (wire_nliili_dataout ^ wire_nl0lOl_dataout))) & (~ (wire_nliill_dataout ^ wire_nl0lOO_dataout))), n1i0l1O = ((((((((((~ (nliO0l ^ wire_nli00i_dataout)) & (~ (nliO0O ^ wire_nli00l_dataout))) & (~ (nliOii ^ wire_nli00O_dataout))) & (~ (nliOil ^ wire_nli0ii_dataout))) & (~ (nliOiO ^ wire_nli0il_dataout))) & (~ (nliOli ^ wire_nli0iO_dataout))) & (~ (nliOll ^ wire_nli0li_dataout))) & (~ (wire_nli0ll_dataout ^ wire_nl0O1l_dataout))) & (~ (wire_nli0lO_dataout ^ wire_nl0O1O_dataout))) & (~ (wire_nli0Oi_dataout ^ wire_nl0O0i_dataout))), n1i0lii = ((((((((((~ (nliOii ^ wire_nli00i_dataout)) & (~ (nliOil ^ wire_nli00l_dataout))) & (~ (nliOiO ^ wire_nli00O_dataout))) & (~ (nliOli ^ wire_nli0ii_dataout))) & (~ (nliOll ^ wire_nli0il_dataout))) & (~ (nliOlO ^ wire_nli0iO_dataout))) & (~ (nliOOi ^ wire_nli0li_dataout))) & (~ (wire_nli0ll_dataout ^ wire_nl0Oli_dataout))) & (~ (wire_nli0lO_dataout ^ wire_nl0Oll_dataout))) & (~ (wire_nli0Oi_dataout ^ wire_nl0OlO_dataout))), n1i0lil = ((((((((((~ (comp_pat[0] ^ nliOii)) & (~ (comp_pat[1] ^ nliOil))) & (~ (comp_pat[2] ^ nliOiO))) & (~ (comp_pat[3] ^ nliOli))) & (~ (comp_pat[4] ^ nliOll))) & (~ (comp_pat[5] ^ nliOlO))) & (~ (comp_pat[6] ^ nliOOi))) & (~ (wire_nliiiO_dataout ^ wire_nl0Oli_dataout))) & (~ (wire_nliili_dataout ^ wire_nl0Oll_dataout))) & (~ (wire_nliill_dataout ^ wire_nl0OlO_dataout))), n1i0liO = ((((((((((~ (nliOil ^ wire_nli00i_dataout)) & (~ (nliOiO ^ wire_nli00l_dataout))) & (~ (nliOli ^ wire_nli00O_dataout))) & (~ (nliOll ^ wire_nli0ii_dataout))) & (~ (nliOlO ^ wire_nli0il_dataout))) & (~ (nliOOi ^ wire_nli0iO_dataout))) & (~ (nliOOl ^ wire_nli0li_dataout))) & (~ (wire_nli0ll_dataout ^ wire_nl0OOl_dataout))) & (~ (wire_nli0lO_dataout ^ wire_nl0OOO_dataout))) & (~ (wire_nli0Oi_dataout ^ wire_nli11i_dataout))), n1i0lli = ((((((((((~ (comp_pat[0] ^ nliOil)) & (~ (comp_pat[1] ^ nliOiO))) & (~ (comp_pat[2] ^ nliOli))) & (~ (comp_pat[3] ^ nliOll))) & (~ (comp_pat[4] ^ nliOlO))) & (~ (comp_pat[5] ^ nliOOi))) & (~ (comp_pat[6] ^ nliOOl))) & (~ (wire_nliiiO_dataout ^ wire_nl0OOl_dataout))) & (~ (wire_nliili_dataout ^ wire_nl0OOO_dataout))) & (~ (wire_nliill_dataout ^ wire_nli11i_dataout))), n1i0lll = ((((((((((~ (nliOiO ^ wire_nli00i_dataout)) & (~ (nliOli ^ wire_nli00l_dataout))) & (~ (nliOll ^ wire_nli00O_dataout))) & (~ (nliOlO ^ wire_nli0ii_dataout))) & (~ (nliOOi ^ wire_nli0il_dataout))) & (~ (nliOOl ^ wire_nli0iO_dataout))) & (~ (nliOOO ^ wire_nli0li_dataout))) & (~ (wire_nli0ll_dataout ^ wire_nli11O_dataout))) & (~ (wire_nli0lO_dataout ^ wire_nli10i_dataout))) & (~ (wire_nli0Oi_dataout ^ wire_nli10l_dataout))), n1i0llO = ((((((((((~ (comp_pat[0] ^ nliOiO)) & (~ (comp_pat[1] ^ nliOli))) & (~ (comp_pat[2] ^ nliOll))) & (~ (comp_pat[3] ^ nliOlO))) & (~ (comp_pat[4] ^ nliOOi))) & (~ (comp_pat[5] ^ nliOOl))) & (~ (comp_pat[6] ^ nliOOO))) & (~ (wire_nliiiO_dataout ^ wire_nli11O_dataout))) & (~ (wire_nliili_dataout ^ wire_nli10i_dataout))) & (~ (wire_nliill_dataout ^ wire_nli10l_dataout))), n1i0lOO = ((((((((((~ (nliOli ^ wire_nli00i_dataout)) & (~ (nliOll ^ wire_nli00l_dataout))) & (~ (nliOlO ^ wire_nli00O_dataout))) & (~ (nliOOi ^ wire_nli0ii_dataout))) & (~ (nliOOl ^ wire_nli0il_dataout))) & (~ (nliOOO ^ wire_nli0iO_dataout))) & (~ (nll11i ^ wire_nli0li_dataout))) & (~ (wire_nli0ll_dataout ^ wire_nli1ii_dataout))) & (~ (wire_nli0lO_dataout ^ wire_nli1il_dataout))) & (~ (wire_nli0Oi_dataout ^ wire_nli1iO_dataout))), n1i0O0O = ((((((((((~ (nliOll ^ wire_nli00i_dataout)) & (~ (nliOlO ^ wire_nli00l_dataout))) & (~ (nliOOi ^ wire_nli00O_dataout))) & (~ (nliOOl ^ wire_nli0ii_dataout))) & (~ (nliOOO ^ wire_nli0il_dataout))) & (~ (nll11i ^ wire_nli0iO_dataout))) & (~ (nll11l ^ wire_nli0li_dataout))) & (~ (wire_nli0ll_dataout ^ wire_nli1ll_dataout))) & (~ (wire_nli0lO_dataout ^ wire_nli1lO_dataout))) & (~ (wire_nli0Oi_dataout ^ wire_nli1Oi_dataout))), n1i0O1i = ((((((((((~ (comp_pat[0] ^ nliOli)) & (~ (comp_pat[1] ^ nliOll))) & (~ (comp_pat[2] ^ nliOlO))) & (~ (comp_pat[3] ^ nliOOi))) & (~ (comp_pat[4] ^ nliOOl))) & (~ (comp_pat[5] ^ nliOOO))) & (~ (comp_pat[6] ^ nll11i))) & (~ (wire_nliiiO_dataout ^ wire_nli1ii_dataout))) & (~ (wire_nliili_dataout ^ wire_nli1il_dataout))) & (~ (wire_nliill_dataout ^ wire_nli1iO_dataout))), n1i0Oii = ((((((((((~ (comp_pat[0] ^ nliOll)) & (~ (comp_pat[1] ^ nliOlO))) & (~ (comp_pat[2] ^ nliOOi))) & (~ (comp_pat[3] ^ nliOOl))) & (~ (comp_pat[4] ^ nliOOO))) & (~ (comp_pat[5] ^ nll11i))) & (~ (comp_pat[6] ^ nll11l))) & (~ (wire_nliiiO_dataout ^ wire_nli1ll_dataout))) & (~ (wire_nliili_dataout ^ wire_nli1lO_dataout))) & (~ (wire_nliill_dataout ^ wire_nli1Oi_dataout))), n1i100i = ((((((((nlilii & nlil0O) & nlil0l) & nlil0i) & nlil1O) & nlil1l) & nlil1i) & nliiOO) & nliiOl), n1i100l = ((pmadwidth[0] & n1i10ii) | ((~ pmadwidth[0]) & n1i100O)), n1i100O = (((((((nlil0l & nlil0i) & nlil1O) & nlil1l) & nlil1i) & nliiOO) & nliiOl) & nl1lOi), n1i101i = (pmadwidth[0] & n1i101l), n1i101l = (((((((((nlilii & nlil0O) & nlil0l) & nlil0i) & nlil1O) & nlil1l) & nlil1i) & nliiOO) & nliiOl) & nl1lOi), n1i101O = (pmadwidth[0] & n1i100i), n1i10ii = (((((((nlilii & nlil0O) & nlil0l) & nlil0i) & nlil1O) & nlil1l) & nlil1i) & nliiOO), n1i10il = ((pmadwidth[0] & n1i10li) | ((~ pmadwidth[0]) & n1i10iO)), n1i10iO = ((((((nlil0l & nlil0i) & nlil1O) & nlil1l) & nlil1i) & nliiOO) & nliiOl), n1i10li = ((((((nlilii & nlil0O) & nlil0l) & nlil0i) & nlil1O) & nlil1l) & nlil1i), n1i10ll = ((pmadwidth[0] & n1i10Oi) | ((~ pmadwidth[0]) & n1i10lO)), n1i10lO = (((((nlil0l & nlil0i) & nlil1O) & nlil1l) & nlil1i) & nliiOO), n1i10Oi = (((((nlilii & nlil0O) & nlil0l) & nlil0i) & nlil1O) & nlil1l), n1i10Ol = ((pmadwidth[0] & n1i1i1i) | ((~ pmadwidth[0]) & n1i10OO)), n1i10OO = ((((nlil0l & nlil0i) & nlil1O) & nlil1l) & nlil1i), n1i110i = (((((~ n1i1lll) | n1i1lil) | n1i1l0l) | n1i1l1O) | n1i1l1i), n1i110l = ((((~ n1i1lil) | n1i1l0l) | n1i1l1O) | n1i1l1i), n1i110O = ((~ n1i1l1O) | n1i1l1i), n1i111i = ((((((((~ n1i1O1O) | n1i1O1l) | n1i1lOl) | n1i1lll) | n1i1lil) | n1i1l0l) | n1i1l1O) | n1i1l1i), n1i111l = (((((((~ n1i1O1l) | n1i1lOl) | n1i1lll) | n1i1lil) | n1i1l0l) | n1i1l1O) | n1i1l1i), n1i111O = ((((((~ n1i1lOl) | n1i1lll) | n1i1lil) | n1i1l0l) | n1i1l1O) | n1i1l1i), n1i11ii = (pmadwidth[0] & n1i101l), n1i11il = (pmadwidth[0] & n1i11iO), n1i11iO = ((((((((nlil0O & nlil0l) & nlil0i) & nlil1O) & nlil1l) & nlil1i) & nliiOO) & nliiOl) & nl1lOi), n1i11li = ((((((nlil0i & nlil1O) & nlil1l) & nlil1i) & nliiOO) & nliiOl) & nl1lOi), n1i11ll = (((((nlil1O & nlil1l) & nlil1i) & nliiOO) & nliiOl) & nl1lOi), n1i11lO = ((((nlil1l & nlil1i) & nliiOO) & nliiOl) & nl1lOi), n1i11Oi = (((nlil1i & nliiOO) & nliiOl) & nl1lOi), n1i11Ol = ((nliiOO & nliiOl) & nl1lOi), n1i11OO = (nliiOl & nl1lOi), n1i1i0i = ((pmadwidth[0] & (nlilii & nlil0O)) | ((~ pmadwidth[0]) & (nlil0l & nlil0i))), n1i1i0l = ((~ pmadwidth[0]) & nlil0l), n1i1i0O = (pmadwidth[0] & nlilii), n1i1i1i = ((((nlilii & nlil0O) & nlil0l) & nlil0i) & nlil1O), n1i1i1l = ((pmadwidth[0] & (((nlilii & nlil0O) & nlil0l) & nlil0i)) | ((~ pmadwidth[0]) & (((nlil0l & nlil0i) & nlil1O) & nlil1l))), n1i1i1O = ((pmadwidth[0] & ((nlilii & nlil0O) & nlil0l)) | ((~ pmadwidth[0]) & ((nlil0l & nlil0i) & nlil1O))), n1i1iii = (pmadwidth[0] & (~ n1i1l1l)), n1i1iil = (pmadwidth[0] & (~ n1i1iiO)), n1i1iiO = ((((((((nlil0O | nlil0l) | nlil0i) | nlil1O) | nlil1l) | nlil1i) | nliiOO) | nliiOl) | nl1lOi), n1i1ili = ((((((nlil0i | nlil1O) | nlil1l) | nlil1i) | nliiOO) | nliiOl) | nl1lOi), n1i1ill = (((((nlil1O | nlil1l) | nlil1i) | nliiOO) | nliiOl) | nl1lOi), n1i1ilO = ((((nlil1l | nlil1i) | nliiOO) | nliiOl) | nl1lOi), n1i1iOi = (((nlil1i | nliiOO) | nliiOl) | nl1lOi), n1i1iOl = ((nliiOO | nliiOl) | nl1lOi), n1i1iOO = (nliiOl | nl1lOi), n1i1l0i = ((((((((nlilii | nlil0O) | nlil0l) | nlil0i) | nlil1O) | nlil1l) | nlil1i) | nliiOO) | nliiOl), n1i1l0l = ((pmadwidth[0] & (~ n1i1lii)) | ((~ pmadwidth[0]) & (~ n1i1l0O))), n1i1l0O = (((((((nlil0l | nlil0i) | nlil1O) | nlil1l) | nlil1i) | nliiOO) | nliiOl) | nl1lOi), n1i1l1i = (pmadwidth[0] & (~ n1i1l1l)), n1i1l1l = (((((((((nlilii | nlil0O) | nlil0l) | nlil0i) | nlil1O) | nlil1l) | nlil1i) | nliiOO) | nliiOl) | nl1lOi), n1i1l1O = (pmadwidth[0] & (~ n1i1l0i)), n1i1lii = (((((((nlilii | nlil0O) | nlil0l) | nlil0i) | nlil1O) | nlil1l) | nlil1i) | nliiOO), n1i1lil = ((pmadwidth[0] & (~ n1i1lli)) | ((~ pmadwidth[0]) & (~ n1i1liO))), n1i1liO = ((((((nlil0l | nlil0i) | nlil1O) | nlil1l) | nlil1i) | nliiOO) | nliiOl), n1i1lli = ((((((nlilii | nlil0O) | nlil0l) | nlil0i) | nlil1O) | nlil1l) | nlil1i), n1i1lll = ((pmadwidth[0] & (~ n1i1lOi)) | ((~ pmadwidth[0]) & (~ n1i1llO))), n1i1llO = (((((nlil0l | nlil0i) | nlil1O) | nlil1l) | nlil1i) | nliiOO), n1i1lOi = (((((nlilii | nlil0O) | nlil0l) | nlil0i) | nlil1O) | nlil1l), n1i1lOl = ((pmadwidth[0] & (~ n1i1O1i)) | ((~ pmadwidth[0]) & (~ n1i1lOO))), n1i1lOO = ((((nlil0l | nlil0i) | nlil1O) | nlil1l) | nlil1i), n1i1O0i = ((pmadwidth[0] & (~ (nlilii | nlil0O))) | ((~ pmadwidth[0]) & (~ (nlil0l | nlil0i)))), n1i1O0l = (((((((~ (wire_niOill_o ^ (~ wire_niiO1i_dataout))) & (~ (wire_niOilO_o ^ (~ wire_niiO1l_dataout)))) & (~ (wire_niOiOi_o ^ (~ wire_niiO1O_dataout)))) & (~ (wire_niOiOl_o ^ (~ wire_niiO0i_dataout)))) & (~ (wire_niOiOO_o ^ (~ wire_niiO0l_dataout)))) & (~ (wire_niOl1i_o ^ (~ wire_niiO0O_dataout)))) & (~ (wire_niOl1l_o ^ (~ wire_niiOii_dataout)))), n1i1O0O = (((((((~ (wire_niOill_o ^ wire_niiO1i_dataout)) & (~ (wire_niOilO_o ^ wire_niiO1l_dataout))) & (~ (wire_niOiOi_o ^ wire_niiO1O_dataout))) & (~ (wire_niOiOl_o ^ wire_niiO0i_dataout))) & (~ (wire_niOiOO_o ^ wire_niiO0l_dataout))) & (~ (wire_niOl1i_o ^ wire_niiO0O_dataout))) & (~ (wire_niOl1l_o ^ wire_niiOii_dataout))), n1i1O1i = ((((nlilii | nlil0O) | nlil0l) | nlil0i) | nlil1O), n1i1O1l = ((pmadwidth[0] & (~ (((nlilii | nlil0O) | nlil0l) | nlil0i))) | ((~ pmadwidth[0]) & (~ (((nlil0l | nlil0i) | nlil1O) | nlil1l)))), n1i1O1O = ((pmadwidth[0] & (~ ((nlilii | nlil0O) | nlil0l))) | ((~ pmadwidth[0]) & (~ ((nlil0l | nlil0i) | nlil1O)))), n1i1Oii = ((((((((((~ (wire_niOill_o ^ (~ wire_niiO1i_dataout))) & (~ (wire_niOilO_o ^ (~ wire_niiO1l_dataout)))) & (~ (wire_niOiOi_o ^ (~ wire_niiO1O_dataout)))) & (~ (wire_niOiOl_o ^ (~ wire_niiO0i_dataout)))) & (~ (wire_niOiOO_o ^ (~ wire_niiO0l_dataout)))) & (~ (wire_niOl1i_o ^ (~ wire_niiO0O_dataout)))) & (~ (wire_niOl1l_o ^ (~ wire_niiOii_dataout)))) & (~ (wire_niOl1O_o ^ (~ wire_niiOil_dataout)))) & (~ (wire_niOl0i_dataout ^ (~ wire_niiOiO_dataout)))) & (~ (wire_niOl0l_dataout ^ (~ wire_niiOli_dataout)))), n1i1Oil = ((((((((((~ (wire_niOill_o ^ wire_niiO1i_dataout)) & (~ (wire_niOilO_o ^ wire_niiO1l_dataout))) & (~ (wire_niOiOi_o ^ wire_niiO1O_dataout))) & (~ (wire_niOiOl_o ^ wire_niiO0i_dataout))) & (~ (wire_niOiOO_o ^ wire_niiO0l_dataout))) & (~ (wire_niOl1i_o ^ wire_niiO0O_dataout))) & (~ (wire_niOl1l_o ^ wire_niiOii_dataout))) & (~ (wire_niOl1O_o ^ wire_niiOil_dataout))) & (~ (wire_niOl0i_dataout ^ wire_niiOiO_dataout))) & (~ (wire_niOl0l_dataout ^ wire_niiOli_dataout))), n1i1OiO = (wire_niOl1i_o & ((~ wire_niOiOO_o) & n1i000O)), n1i1Oli = ((~ wire_niOl1i_o) & (wire_niOiOO_o & n10lO1i)), n1i1Oll = ((~ wire_niOl1i_o) & ((~ wire_niOiOO_o) & ((~ wire_niOiOl_o) & ((~ wire_niOiOi_o) & (wire_niOilO_o & wire_niOill_o))))), n1i1OlO = (wire_niOl1i_o & (wire_niOiOO_o & (wire_niOiOl_o & (wire_niOiOi_o & ((~ wire_niOilO_o) & (~ wire_niOill_o)))))), n1i1OOi = ((~ comp_pat_size[0]) & comp_pat_size[1]), n1i1OOl = ((((((((((~ ((~ comp_pat[0]) ^ wire_nilllO_dataout)) & (~ ((~ comp_pat[1]) ^ wire_nillOi_dataout))) & (~ ((~ comp_pat[2]) ^ wire_nillOl_dataout))) & (~ ((~ comp_pat[3]) ^ wire_nillOO_dataout))) & (~ ((~ comp_pat[4]) ^ wire_nilO1i_dataout))) & (~ ((~ comp_pat[5]) ^ wire_nilO1l_dataout))) & (~ ((~ comp_pat[6]) ^ wire_nilO1O_dataout))) & (~ ((~ comp_pat[7]) ^ wire_nilO0i_dataout))) & (~ ((~ comp_pat[8]) ^ wire_nilO0l_dataout))) & (~ ((~ comp_pat[9]) ^ wire_nilO0O_dataout))), n1i1OOO = ((((((((((~ (comp_pat[0] ^ wire_nilllO_dataout)) & (~ (comp_pat[1] ^ wire_nillOi_dataout))) & (~ (comp_pat[2] ^ wire_nillOl_dataout))) & (~ (comp_pat[3] ^ wire_nillOO_dataout))) & (~ (comp_pat[4] ^ wire_nilO1i_dataout))) & (~ (comp_pat[5] ^ wire_nilO1l_dataout))) & (~ (comp_pat[6] ^ wire_nilO1O_dataout))) & (~ (comp_pat[7] ^ wire_nilO0i_dataout))) & (~ (comp_pat[8] ^ wire_nilO0l_dataout))) & (~ (comp_pat[9] ^ wire_nilO0O_dataout))), n1ii00i = (nlO0l1l & n1ii00l), n1ii00l = (((n1ii01O & n1ii01l) & n1ii01i) & (~ n1ii1OO)), n1ii01i = (((((~ n1i0ilO) | (~ n1i0ill)) | (~ n1i0iil)) | (~ n1i0iii)) | (~ n1i0i0i)), n1ii01l = (((((~ n1i0ilO) | (~ n1i0ill)) | (~ n1i0ili)) | (~ n1i0iiO)) | (~ n1i0i0i)), n1ii01O = ((wire_nl011O_dataout | (~ n1i0iOi)) | (~ n1i0i0i)), n1ii0iO = ((~ disable_rx_disp) & (((((~ niii0i) & ((((((n1i00ll | n1i00li) | n1i00iO) | (n1i00il & n1i00ii)) | (n1i000O & n1i000l)) | n1i000i) | n1i001O)) | (niii0i & (n1i001l | ((~ wire_niOiOl_o) & n1i001i)))) | ((n1i01OO | (n1i01Ol | n1i01Oi)) & (~ wire_nlOll0O_dataout))) | ((n1i01lO | (wire_niOl1O_o & (wire_niOl1l_o & n1i01ll))) & wire_nlOll0O_dataout))), n1ii0li = ((~ sync_sm_dis) & nlO01ii), n1ii0Oi = ((~ pmadwidth[0]) & (sync_sm_dis & nil1Ol)), n1ii0Ol = (sync_sm_dis & nl10Ol), n1ii10i = (comp_pat_size[0] & (~ comp_pat_size[1])), n1ii10O = (wire_nllliil_dataout & (~ (((n1ii01O & n1ii01l) & n1ii01i) & (~ n1ii1OO)))), n1ii11i = ((((((((((~ (nliOlO ^ wire_nli00i_dataout)) & (~ (nliOOi ^ wire_nli00l_dataout))) & (~ (nliOOl ^ wire_nli00O_dataout))) & (~ (nliOOO ^ wire_nli0ii_dataout))) & (~ (nll11i ^ wire_nli0il_dataout))) & (~ (nll11l ^ wire_nli0iO_dataout))) & (~ (nll11O ^ wire_nli0li_dataout))) & (~ (wire_nli0ll_dataout ^ wire_nli1OO_dataout))) & (~ (wire_nli0lO_dataout ^ wire_nli01i_dataout))) & (~ (wire_nli0Oi_dataout ^ wire_nli01l_dataout))), n1ii11l = ((((((((((~ (comp_pat[0] ^ nliOlO)) & (~ (comp_pat[1] ^ nliOOi))) & (~ (comp_pat[2] ^ nliOOl))) & (~ (comp_pat[3] ^ nliOOO))) & (~ (comp_pat[4] ^ nll11i))) & (~ (comp_pat[5] ^ nll11l))) & (~ (comp_pat[6] ^ nll11O))) & (~ (wire_nliiiO_dataout ^ wire_nli1OO_dataout))) & (~ (wire_nliili_dataout ^ wire_nli01i_dataout))) & (~ (wire_nliill_dataout ^ wire_nli01l_dataout))), n1ii11O = ((~ comp_pat_size[0]) & (~ comp_pat_size[1])), n1ii1lO = ((nlO0l1l & (~ n1ii00l)) & (n1ii1Oi22 ^ n1ii1Oi21)), n1ii1OO = (((((~ n1i0iOi) | (~ n1i0ill)) | (~ n1i0iiO)) | (~ n1i0iii)) | n1i0i0l), n1iii1i = 1'b0, n1iii1l = (((~ pmadwidth[0]) & pmadwidth[1]) & (n1ii0ii18 ^ n1ii0ii17)), n1iii1O = ((~ pmadwidth[0]) & pmadwidth[1]), n1iiili = (n1OO0lO | n1OO0ll), n1iiill = (n1Oi0O | n1Oi0l), n1iiilO = (((((((n10i1OO & n110iil) | (n11liOi & n110iii)) | (n1000Ol & n110i0O)) | (n11iOiO & n110i0l)) | (n101iOi & n110i0i)) | (n110O1O & n110i1O)) | (n11O01l & n110i1l)), n1iiiOi = (((((rauto_speed_ena & (~ rfreq_sel)) & (n1iil1i4 ^ n1iil1i3)) & ni0OO) | dwidth) | (~ (n1iiiOl6 ^ n1iiiOl5))), n1iil0i = 1'b1, nlOO000i = (((((~ wire_nl1lilO_o) & ((~ wire_nl1lill_o) & ((~ wire_nl1lili_o) & wire_nl1liiO_o))) | ((~ wire_nl1lilO_o) & ((~ wire_nl1lill_o) & (wire_nl1lili_o & (~ wire_nl1liiO_o))))) | ((~ wire_nl1lilO_o) & (wire_nl1lill_o & nlOO1Oii))) | (wire_nl1lilO_o & ((~ wire_nl1lill_o) & nlOO1Oii))), nlOO000l = ((~ wire_nl1lilO_o) & ((~ wire_nl1lill_o) & ((~ wire_nl1lili_o) & (~ wire_nl1liiO_o)))), nlOO000O = (wire_nl1lilO_o & (wire_nl1lill_o & (wire_nl1lili_o & wire_nl1liiO_o))), nlOO001i = ((~ wire_nl1liOl_o) & wire_nl1liOi_o), nlOO001l = (wire_nl1liOl_o & (~ wire_nl1liOi_o)), nlOO001O = (((((~ wire_nl1lilO_o) & (wire_nl1lill_o & nlOO1O0O)) | (wire_nl1lilO_o & ((~ wire_nl1lill_o) & nlOO1O0O))) | (wire_nl1lilO_o & (wire_nl1lill_o & ((~ wire_nl1lili_o) & wire_nl1liiO_o)))) | (wire_nl1lilO_o & (wire_nl1lill_o & (wire_nl1lili_o & (~ wire_nl1liiO_o))))), nlOO00ii = ((ib_invalid_code[0] & ((((~ wire_nl1ll1i_o) & nlOO011i) & nlOO1O1l) | ((wire_nl1ll1i_o & nlOO1OOO) & nlOO1O1l))) | (ib_invalid_code[1] & ((wire_nl1ll1l_o & (wire_nl1ll1i_o & (nlOO011i & nlOO1O0i))) | ((~ wire_nl1ll1l_o) & ((~ wire_nl1ll1i_o) & (nlOO1OOO & nlOO1O0i)))))), nlOO00il = (wire_nl1ll0l_o & wire_nl1ll0i_o), nlOO00iO = ((~ wire_nl1ll0l_o) & (~ wire_nl1ll0i_o)), nlOO00li = (wire_nl1ll0l_o & (~ wire_nl1ll0i_o)), nlOO00ll = ((~ wire_nl1ll0l_o) & wire_nl1ll0i_o), nlOO00lO = (nlOO0lil & nlOO00Ol), nlOO00Oi = ((~ wire_nl1llii_o) & ((~ wire_nl1ll0O_o) & ((~ wire_nl1ll0l_o) & (~ wire_nl1ll0i_o)))), nlOO00Ol = (wire_nl1lliO_o & wire_nl1llil_o), nlOO00OO = (wire_nl1llii_o & (wire_nl1ll0O_o & (wire_nl1ll0l_o & wire_nl1ll0i_o))), nlOO010i = (nlOO1OOl & nlOO1lll), nlOO010l = (nlOO1l0i & nlOO1lll), nlOO010O = (nlOO1l0i & nlOO1lli), nlOO011i = (wire_nl1liOl_o & (wire_nl1liOi_o & (wire_nl1lilO_o & (wire_nl1lill_o & ((~ wire_nl1lili_o) & (~ wire_nl1liiO_o)))))), nlOO011l = ((~ wire_nl1ll1O_o) & ((~ wire_nl1ll1l_o) & ((~ wire_nl1ll1i_o) & (~ wire_nl1liOO_o)))), nlOO011O = (wire_nl1ll1O_o & (wire_nl1ll1l_o & (wire_nl1ll1i_o & wire_nl1liOO_o))), nlOO01ii = (nlOO1l0i & nlOO1l0l), nlOO01il = (nlOO1l0O & nlOO1lli), nlOO01iO = ((nlOO1l0O & nlOO1l0l) | (nlOO1OOi & nlOO1l0l)), nlOO01li = (nlOO1l0O & nlOO1lll), nlOO01ll = ((~ wire_nl1ll1O_o) & (~ wire_nl1ll1l_o)), nlOO01lO = (((((((~ wire_nl1lilO_o) & ((~ wire_nl1lill_o) & (wire_nl1lili_o & wire_nl1liiO_o))) | ((~ wire_nl1lilO_o) & (wire_nl1lill_o & nlOO1OiO))) | ((~ wire_nl1lilO_o) & (wire_nl1lill_o & nlOO1Oil))) | (wire_nl1lilO_o & ((~ wire_nl1lill_o) & nlOO1OiO))) | (wire_nl1lilO_o & ((~ wire_nl1lill_o) & nlOO1Oil))) | (wire_nl1lilO_o & (wire_nl1lill_o & ((~ wire_nl1lili_o) & (~ wire_nl1liiO_o))))), nlOO01Oi = ((~ wire_nl1ll1i_o) & (~ wire_nl1liOO_o)), nlOO01Ol = (wire_nl1ll1i_o & wire_nl1liOO_o), nlOO01OO = ((wire_nl1liOl_o & (wire_nl1liOi_o & (wire_nl1lilO_o & wire_nl1lill_o))) | ((~ wire_nl1liOl_o) & ((~ wire_nl1liOi_o) & ((~ wire_nl1lilO_o) & (~ wire_nl1lill_o))))), nlOO0i0i = (((~ wire_nl1lliO_o) & wire_nl1llil_o) | (wire_nl1lliO_o & (~ wire_nl1llil_o))), nlOO0i0l = ((~ wire_nl1lliO_o) & (~ wire_nl1llil_o)), nlOO0i0O = (((((((~ wire_nl1llii_o) & ((~ wire_nl1ll0O_o) & (wire_nl1ll0l_o & wire_nl1ll0i_o))) | ((~ wire_nl1llii_o) & (wire_nl1ll0O_o & nlOO00ll))) | ((~ wire_nl1llii_o) & (wire_nl1ll0O_o & nlOO00li))) | (wire_nl1llii_o & ((~ wire_nl1ll0O_o) & nlOO00ll))) | (wire_nl1llii_o & ((~ wire_nl1ll0O_o) & nlOO00li))) | (wire_nl1llii_o & (wire_nl1ll0O_o & ((~ wire_nl1ll0l_o) & (~ wire_nl1ll0i_o))))), nlOO0i1i = (nlOO0lii & nlOO0i0l), nlOO0i1l = ((((nlOO0O1O | (nlOO0i0O & nlOO00Ol)) | (nlOO0lii & nlOO0i0i)) | nlOO0O1l) | nlOO0O0i), nlOO0i1O = (wire_nl1llii_o & nlOO00lO), nlOO0iii = (wire_nl1llll_o & wire_nl1llli_o), nlOO0iil = ((~ wire_nl1llll_o) & (~ wire_nl1llli_o)), nlOO0iiO = (wire_nl1llll_o & (~ wire_nl1llli_o)), nlOO0ili = ((~ wire_nl1llll_o) & wire_nl1llli_o), nlOO0ill = (wire_nl1lllO_o ^ wire_nl1llli_o), nlOO0ilO = ((~ wire_nl1llll_o) & ((~ wire_nl1llli_o) & nlOO0iOi)), nlOO0iOi = (((((((~ wire_nl1llOi_o) & ((~ wire_nl1lllO_o) & (wire_nl1llll_o & wire_nl1llli_o))) | ((~ wire_nl1llOi_o) & (wire_nl1lllO_o & nlOO0ili))) | ((~ wire_nl1llOi_o) & (wire_nl1lllO_o & nlOO0iiO))) | (wire_nl1llOi_o & ((~ wire_nl1lllO_o) & nlOO0ili))) | (wire_nl1llOi_o & ((~ wire_nl1lllO_o) & nlOO0iiO))) | (wire_nl1llOi_o & (wire_nl1lllO_o & ((~ wire_nl1llll_o) & (~ wire_nl1llli_o))))), nlOO0iOl = (nlOO0l0l | nlOO0llO), nlOO0iOO = (wire_nl1ll0l_o & wire_nl1ll0i_o), nlOO0l0i = (((((~ wire_nl1llOi_o) & ((~ wire_nl1lllO_o) & ((~ wire_nl1llll_o) & wire_nl1llli_o))) | ((~ wire_nl1llOi_o) & ((~ wire_nl1lllO_o) & (wire_nl1llll_o & (~ wire_nl1llli_o))))) | ((~ wire_nl1llOi_o) & (wire_nl1lllO_o & nlOO0iil))) | (wire_nl1llOi_o & ((~ wire_nl1lllO_o) & nlOO0iil))), nlOO0l0l = (((((~ wire_nl1llOi_o) & (wire_nl1lllO_o & nlOO0iii)) | (wire_nl1llOi_o & ((~ wire_nl1lllO_o) & nlOO0iii))) | (wire_nl1llOi_o & (wire_nl1lllO_o & ((~ wire_nl1llll_o) & wire_nl1llli_o)))) | (wire_nl1llOi_o & (wire_nl1lllO_o & (wire_nl1llll_o & (~ wire_nl1llli_o))))), nlOO0l0O = (((~ wire_n1lllii_dataout) & nlOO00Ol) | (wire_n1lllii_dataout & nlOO0i0l)), nlOO0l1i = ((~ wire_nl1ll0l_o) & (~ wire_nl1ll0i_o)), nlOO0l1l = (wire_nl1ll0l_o & (~ wire_nl1ll0i_o)), nlOO0l1O = ((~ wire_nl1ll0l_o) & wire_nl1ll0i_o), nlOO0lii = (((((~ wire_nl1llii_o) & (wire_nl1ll0O_o & nlOO00il)) | (wire_nl1llii_o & ((~ wire_nl1ll0O_o) & nlOO00il))) | (wire_nl1llii_o & (wire_nl1ll0O_o & ((~ wire_nl1ll0l_o) & wire_nl1ll0i_o)))) | (wire_nl1llii_o & (wire_nl1ll0O_o & (wire_nl1ll0l_o & (~ wire_nl1ll0i_o))))), nlOO0lil = (((((~ wire_nl1llii_o) & ((~ wire_nl1ll0O_o) & ((~ wire_nl1ll0l_o) & wire_nl1ll0i_o))) | ((~ wire_nl1llii_o) & ((~ wire_nl1ll0O_o) & (wire_nl1ll0l_o & (~ wire_nl1ll0i_o))))) | ((~ wire_nl1llii_o) & (wire_nl1ll0O_o & nlOO00iO))) | (wire_nl1llii_o & ((~ wire_nl1ll0O_o) & nlOO00iO))), nlOO0liO = ((~ wire_nl1lliO_o) & ((~ wire_nl1llil_o) & ((~ wire_nl1llii_o) & ((~ wire_nl1ll0O_o) & (wire_nl1ll0l_o & wire_nl1ll0i_o))))), nlOO0lli = (wire_nl1lliO_o & (wire_nl1llil_o & (wire_nl1llii_o & (wire_nl1ll0O_o & ((~ wire_nl1ll0l_o) & (~ wire_nl1ll0i_o)))))), nlOO0lll = ((~ wire_nl1llOi_o) & ((~ wire_nl1lllO_o) & ((~ wire_nl1llll_o) & (~ wire_nl1llli_o)))), nlOO0llO = (wire_nl1llOi_o & (wire_nl1lllO_o & (wire_nl1llll_o & wire_nl1llli_o))), nlOO0lOi = (nlOO0lil & nlOO0i0l), nlOO0lOl = (nlOO00Oi & nlOO0i0l), nlOO0lOO = (nlOO00Oi & nlOO0i0i), nlOO0O0i = (nlOO00OO & nlOO0i0l), nlOO0O0l = ((~ wire_nl1llOi_o) & (~ wire_nl1lllO_o)), nlOO0O0O = (((((((~ wire_nl1llii_o) & ((~ wire_nl1ll0O_o) & (wire_nl1ll0l_o & wire_nl1ll0i_o))) | ((~ wire_nl1llii_o) & (wire_nl1ll0O_o & nlOO0l1O))) | ((~ wire_nl1llii_o) & (wire_nl1ll0O_o & nlOO0l1l))) | (wire_nl1llii_o & ((~ wire_nl1ll0O_o) & nlOO0l1O))) | (wire_nl1llii_o & ((~ wire_nl1ll0O_o) & nlOO0l1l))) | (wire_nl1llii_o & (wire_nl1ll0O_o & ((~ wire_nl1ll0l_o) & (~ wire_nl1ll0i_o))))), nlOO0O1i = (nlOO00Oi & nlOO00Ol), nlOO0O1l = (nlOO00OO & nlOO0i0i), nlOO0O1O = ((nlOO00OO & nlOO00Ol) | (nlOO0lii & nlOO00Ol)), nlOO0Oii = ((~ wire_nl1llll_o) & (~ wire_nl1llli_o)), nlOO0Oil = (wire_nl1llll_o & wire_nl1llli_o), nlOO0OiO = ((wire_nl1lliO_o & (wire_nl1llil_o & (wire_nl1llii_o & wire_nl1ll0O_o))) | ((~ wire_nl1lliO_o) & ((~ wire_nl1llil_o) & ((~ wire_nl1llii_o) & (~ wire_nl1ll0O_o))))), nlOO0Oli = ((~ wire_nl1lliO_o) & wire_nl1llil_o), nlOO0Oll = (wire_nl1lliO_o & (~ wire_nl1llil_o)), nlOO0OlO = (((((~ wire_nl1llii_o) & (wire_nl1ll0O_o & nlOO0iOO)) | (wire_nl1llii_o & ((~ wire_nl1ll0O_o) & nlOO0iOO))) | (wire_nl1llii_o & (wire_nl1ll0O_o & ((~ wire_nl1ll0l_o) & wire_nl1ll0i_o)))) | (wire_nl1llii_o & (wire_nl1ll0O_o & (wire_nl1ll0l_o & (~ wire_nl1ll0i_o))))), nlOO0OOi = (((((~ wire_nl1llii_o) & ((~ wire_nl1ll0O_o) & ((~ wire_nl1ll0l_o) & wire_nl1ll0i_o))) | ((~ wire_nl1llii_o) & ((~ wire_nl1ll0O_o) & (wire_nl1ll0l_o & (~ wire_nl1ll0i_o))))) | ((~ wire_nl1llii_o) & (wire_nl1ll0O_o & nlOO0l1i))) | (wire_nl1llii_o & ((~ wire_nl1ll0O_o) & nlOO0l1i))), nlOO0OOl = ((~ wire_nl1llii_o) & ((~ wire_nl1ll0O_o) & ((~ wire_nl1ll0l_o) & (~ wire_nl1ll0i_o)))), nlOO0OOO = (wire_nl1llii_o & (wire_nl1ll0O_o & (wire_nl1ll0l_o & wire_nl1ll0i_o))), nlOO1iOl = (wire_nl1lili_o & wire_nl1liiO_o), nlOO1iOO = ((~ wire_nl1lili_o) & (~ wire_nl1liiO_o)), nlOO1l0i = ((~ wire_nl1lilO_o) & ((~ wire_nl1lill_o) & ((~ wire_nl1lili_o) & (~ wire_nl1liiO_o)))), nlOO1l0l = (wire_nl1liOl_o & wire_nl1liOi_o), nlOO1l0O = (wire_nl1lilO_o & (wire_nl1lill_o & (wire_nl1lili_o & wire_nl1liiO_o))), nlOO1l1i = (wire_nl1lili_o & (~ wire_nl1liiO_o)), nlOO1l1l = ((~ wire_nl1lili_o) & wire_nl1liiO_o), nlOO1l1O = (nlOO1OOl & nlOO1l0l), nlOO1lii = (nlOO1OOi & nlOO1lll), nlOO1lil = ((((nlOO01iO | (nlOO1llO & nlOO1l0l)) | (nlOO1OOi & nlOO1lli)) | nlOO01il) | nlOO01li), nlOO1liO = (wire_nl1lilO_o & nlOO1l1O), nlOO1lli = (((~ wire_nl1liOl_o) & wire_nl1liOi_o) | (wire_nl1liOl_o & (~ wire_nl1liOi_o))), nlOO1lll = ((~ wire_nl1liOl_o) & (~ wire_nl1liOi_o)), nlOO1llO = (((((((~ wire_nl1lilO_o) & ((~ wire_nl1lill_o) & (wire_nl1lili_o & wire_nl1liiO_o))) | ((~ wire_nl1lilO_o) & (wire_nl1lill_o & nlOO1l1l))) | ((~ wire_nl1lilO_o) & (wire_nl1lill_o & nlOO1l1i))) | (wire_nl1lilO_o & ((~ wire_nl1lill_o) & nlOO1l1l))) | (wire_nl1lilO_o & ((~ wire_nl1lill_o) & nlOO1l1i))) | (wire_nl1lilO_o & (wire_nl1lill_o & ((~ wire_nl1lili_o) & (~ wire_nl1liiO_o))))), nlOO1lOi = (wire_nl1ll1i_o & wire_nl1liOO_o), nlOO1lOl = ((~ wire_nl1ll1i_o) & (~ wire_nl1liOO_o)), nlOO1lOO = (wire_nl1ll1i_o & (~ wire_nl1liOO_o)), nlOO1O0i = (((((((~ wire_nl1ll1O_o) & ((~ wire_nl1ll1l_o) & (wire_nl1ll1i_o & wire_nl1liOO_o))) | ((~ wire_nl1ll1O_o) & (wire_nl1ll1l_o & nlOO1O1i))) | ((~ wire_nl1ll1O_o) & (wire_nl1ll1l_o & nlOO1lOO))) | (wire_nl1ll1O_o & ((~ wire_nl1ll1l_o) & nlOO1O1i))) | (wire_nl1ll1O_o & ((~ wire_nl1ll1l_o) & nlOO1lOO))) | (wire_nl1ll1O_o & (wire_nl1ll1l_o & ((~ wire_nl1ll1i_o) & (~ wire_nl1liOO_o))))), nlOO1O0l = (nlOO1Oll | nlOO011O), nlOO1O0O = (wire_nl1lili_o & wire_nl1liiO_o), nlOO1O1i = ((~ wire_nl1ll1i_o) & wire_nl1liOO_o), nlOO1O1l = (wire_nl1ll1l_o ^ wire_nl1liOO_o), nlOO1O1O = ((~ wire_nl1ll1i_o) & ((~ wire_nl1liOO_o) & nlOO1O0i)), nlOO1Oii = ((~ wire_nl1lili_o) & (~ wire_nl1liiO_o)), nlOO1Oil = (wire_nl1lili_o & (~ wire_nl1liiO_o)), nlOO1OiO = ((~ wire_nl1lili_o) & wire_nl1liiO_o), nlOO1Oli = (((((~ wire_nl1ll1O_o) & ((~ wire_nl1ll1l_o) & ((~ wire_nl1ll1i_o) & wire_nl1liOO_o))) | ((~ wire_nl1ll1O_o) & ((~ wire_nl1ll1l_o) & (wire_nl1ll1i_o & (~ wire_nl1liOO_o))))) | ((~ wire_nl1ll1O_o) & (wire_nl1ll1l_o & nlOO1lOl))) | (wire_nl1ll1O_o & ((~ wire_nl1ll1l_o) & nlOO1lOl))), nlOO1Oll = (((((~ wire_nl1ll1O_o) & (wire_nl1ll1l_o & nlOO1lOi)) | (wire_nl1ll1O_o & ((~ wire_nl1ll1l_o) & nlOO1lOi))) | (wire_nl1ll1O_o & (wire_nl1ll1l_o & ((~ wire_nl1ll1i_o) & wire_nl1liOO_o)))) | (wire_nl1ll1O_o & (wire_nl1ll1l_o & (wire_nl1ll1i_o & (~ wire_nl1liOO_o))))), nlOO1OlO = (((~ wire_n1iliii_dataout) & nlOO1l0l) | (wire_n1iliii_dataout & nlOO1lll)), nlOO1OOi = (((((~ wire_nl1lilO_o) & (wire_nl1lill_o & nlOO1iOl)) | (wire_nl1lilO_o & ((~ wire_nl1lill_o) & nlOO1iOl))) | (wire_nl1lilO_o & (wire_nl1lill_o & ((~ wire_nl1lili_o) & wire_nl1liiO_o)))) | (wire_nl1lilO_o & (wire_nl1lill_o & (wire_nl1lili_o & (~ wire_nl1liiO_o))))), nlOO1OOl = (((((~ wire_nl1lilO_o) & ((~ wire_nl1lill_o) & ((~ wire_nl1lili_o) & wire_nl1liiO_o))) | ((~ wire_nl1lilO_o) & ((~ wire_nl1lill_o) & (wire_nl1lili_o & (~ wire_nl1liiO_o))))) | ((~ wire_nl1lilO_o) & (wire_nl1lill_o & nlOO1iOO))) | (wire_nl1lilO_o & ((~ wire_nl1lill_o) & nlOO1iOO))), nlOO1OOO = ((~ wire_nl1liOl_o) & ((~ wire_nl1liOi_o) & ((~ wire_nl1lilO_o) & ((~ wire_nl1lill_o) & (wire_nl1lili_o & wire_nl1liiO_o))))), nlOOi00i = (((((((((((pmadwidth[0] | (~ nlli0lO)) | (~ nlli1li)) | (~ nlli1iO)) | (~ nlli1il)) | (~ nlli1ii)) | (~ nlli10O)) | (~ nlli10l)) | (~ nlli10i)) | (~ nlli11O)) | (~ nlli11l)) | (~ wire_n0110il_dataout)), nlOOi00l = (((((((((((pmadwidth[0] | (~ nlli0lO)) | (~ nlli1iO)) | (~ nlli1il)) | (~ nlli1ii)) | (~ nlli10O)) | (~ nlli10l)) | (~ nlli10i)) | (~ nlli11O)) | (~ nlli11l)) | (~ nlli11i)) | (~ wire_n0110il_dataout)), nlOOi00O = (((((((((((pmadwidth[0] | (~ nlli0lO)) | (~ nlli1il)) | (~ nlli1ii)) | (~ nlli10O)) | (~ nlli10l)) | (~ nlli10i)) | (~ nlli11O)) | (~ nlli11l)) | (~ nlli11i)) | (~ nll0OOO)) | (~ wire_n0110il_dataout)), nlOOi01i = (((((((((((pmadwidth[0] | (~ nlli0lO)) | (~ nlli1lO)) | (~ nlli1ll)) | (~ nlli1li)) | (~ nlli1iO)) | (~ nlli1il)) | (~ nlli1ii)) | (~ nlli10O)) | (~ nlli10l)) | (~ nlli10i)) | (~ wire_n0110il_dataout)), nlOOi01l = (((((((((((pmadwidth[0] | (~ nlli0lO)) | (~ nlli1Oi)) | (~ nlli1lO)) | (~ nlli1ll)) | (~ nlli1li)) | (~ nlli1iO)) | (~ nlli1il)) | (~ nlli1ii)) | (~ nlli10O)) | (~ nlli10l)) | (~ wire_n0110il_dataout)), nlOOi01O = (((((((((((pmadwidth[0] | (~ nlli0lO)) | (~ nlli1ll)) | (~ nlli1li)) | (~ nlli1iO)) | (~ nlli1il)) | (~ nlli1ii)) | (~ nlli10O)) | (~ nlli10l)) | (~ nlli10i)) | (~ nlli11O)) | (~ wire_n0110il_dataout)), nlOOi0ii = (((((((((((pmadwidth[0] | (~ nlli0lO)) | (~ nlli1ii)) | (~ nlli10O)) | (~ nlli10l)) | (~ nlli10i)) | (~ nlli11O)) | (~ nlli11l)) | (~ nlli11i)) | (~ nll0OOO)) | (~ nll0OOl)) | (~ wire_n0110il_dataout)), nlOOi0il = ((((((((((((((~ pmadwidth[0]) | (~ nlli0lO)) | (~ nlli01l)) | (~ nlli01i)) | (~ nlli1OO)) | (~ nlli1Ol)) | (~ nlli1Oi)) | (~ nlli1lO)) | (~ nlli1ll)) | (~ nlli1li)) | (~ nlli1iO)) | (~ nlli1il)) | (~ nlli1ii)) | (~ wire_n0110il_dataout)), nlOOi0iO = ((((((((((((((~ pmadwidth[0]) | (~ nlli0lO)) | (~ nlli01i)) | (~ nlli1OO)) | (~ nlli1Ol)) | (~ nlli1Oi)) | (~ nlli1lO)) | (~ nlli1ll)) | (~ nlli1li)) | (~ nlli1iO)) | (~ nlli1il)) | (~ nlli1ii)) | (~ nlli10O)) | (~ wire_n0110il_dataout)), nlOOi0li = ((((((((((((((~ pmadwidth[0]) | (~ nlli0lO)) | (~ nlli1OO)) | (~ nlli1Ol)) | (~ nlli1Oi)) | (~ nlli1lO)) | (~ nlli1ll)) | (~ nlli1li)) | (~ nlli1iO)) | (~ nlli1il)) | (~ nlli1ii)) | (~ nlli10O)) | (~ nlli10l)) | (~ wire_n0110il_dataout)), nlOOi0ll = ((((((((((((((~ pmadwidth[0]) | (~ nlli0lO)) | (~ nlli1Ol)) | (~ nlli1Oi)) | (~ nlli1lO)) | (~ nlli1ll)) | (~ nlli1li)) | (~ nlli1iO)) | (~ nlli1il)) | (~ nlli1ii)) | (~ nlli10O)) | (~ nlli10l)) | (~ nlli10i)) | (~ wire_n0110il_dataout)), nlOOi0lO = ((((((((((((((~ pmadwidth[0]) | (~ nlli0lO)) | (~ nlli1Oi)) | (~ nlli1lO)) | (~ nlli1ll)) | (~ nlli1li)) | (~ nlli1iO)) | (~ nlli1il)) | (~ nlli1ii)) | (~ nlli10O)) | (~ nlli10l)) | (~ nlli10i)) | (~ nlli11O)) | (~ wire_n0110il_dataout)), nlOOi0Oi = ((((((((((((((~ pmadwidth[0]) | (~ nlli0lO)) | (~ nlli1lO)) | (~ nlli1ll)) | (~ nlli1li)) | (~ nlli1iO)) | (~ nlli1il)) | (~ nlli1ii)) | (~ nlli10O)) | (~ nlli10l)) | (~ nlli10i)) | (~ nlli11O)) | (~ nlli11l)) | (~ wire_n0110il_dataout)), nlOOi0Ol = ((((((((((((((~ pmadwidth[0]) | (~ nlli0lO)) | (~ nlli1ll)) | (~ nlli1li)) | (~ nlli1iO)) | (~ nlli1il)) | (~ nlli1ii)) | (~ nlli10O)) | (~ nlli10l)) | (~ nlli10i)) | (~ nlli11O)) | (~ nlli11l)) | (~ nlli11i)) | (~ wire_n0110il_dataout)), nlOOi0OO = ((((((((((((((~ pmadwidth[0]) | (~ nlli0lO)) | (~ nlli1li)) | (~ nlli1iO)) | (~ nlli1il)) | (~ nlli1ii)) | (~ nlli10O)) | (~ nlli10l)) | (~ nlli10i)) | (~ nlli11O)) | (~ nlli11l)) | (~ nlli11i)) | (~ nll0OOO)) | (~ wire_n0110il_dataout)), nlOOi10i = (n1OO01i | n1OO1OO), nlOOi10l = ((((n1OO01O | n1OO01l) | n1OO01i) | n1OO1OO) | n1OO1Ol), nlOOi10O = ((((n1OO01O | n1OO01l) | n1OO1Oi) | n1OO1lO) | n1Ol0il), nlOOi11i = ((ib_invalid_code[0] & ((((~ wire_nl1llll_o) & nlOO0lli) & nlOO0ill) | ((wire_nl1llll_o & nlOO0liO) & nlOO0ill))) | (ib_invalid_code[1] & ((wire_nl1lllO_o & (wire_nl1llll_o & (nlOO0lli & nlOO0iOi))) | ((~ wire_nl1lllO_o) & ((~ wire_nl1llll_o) & (nlOO0liO & nlOO0iOi)))))), nlOOi11l = (n1OO1Ol | n1Ol0il), nlOOi11O = (n1OO1Oi | n1OO1lO), nlOOi1ii = (n1OO01O | n1OO01l), nlOOi1il = ((~ n011l1O) & (~ n011l1l)), nlOOi1iO = ((~ n011l1O) & n011l1l), nlOOi1li = (n1Ol0ii & n1Ol00O), nlOOi1ll = ((~ n0101il) & (~ n011l1l)), nlOOi1lO = ((~ n0101il) & n011l1l), nlOOi1Oi = (((((((((~ wire_n011i1l_dataout) & (~ wire_n011i1i_dataout)) & (~ wire_n0110OO_dataout)) & (~ wire_n0110Ol_dataout)) & (~ wire_n0110Oi_dataout)) & (~ wire_n0110lO_dataout)) & wire_n0110ll_dataout) & (~ wire_n0110li_dataout)) & (~ wire_n0110iO_dataout)), nlOOi1Ol = (((((((((~ wire_n011i1l_dataout) & (~ wire_n011i1i_dataout)) & (~ wire_n0110OO_dataout)) & (~ wire_n0110Ol_dataout)) & (~ wire_n0110Oi_dataout)) & (~ wire_n0110lO_dataout)) & wire_n0110ll_dataout) & (~ wire_n0110li_dataout)) & wire_n0110iO_dataout), nlOOi1OO = ((((((~ max_rlv_sel[0]) & (~ max_rlv_sel[1])) & (~ max_rlv_sel[2])) & (~ max_rlv_sel[3])) & (~ max_rlv_sel[4])) & (~ max_rlv_sel[5])), nlOOii0i = (((((((((((pmadwidth[0] | (~ nlli0lO)) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | nlli11O) | (~ wire_n0110il_dataout)), nlOOii0l = (((((((((((pmadwidth[0] | (~ nlli0lO)) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | nlli11O) | nlli11l) | (~ wire_n0110il_dataout)), nlOOii0O = (((((((((((pmadwidth[0] | (~ nlli0lO)) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | nlli11O) | nlli11l) | nlli11i) | (~ wire_n0110il_dataout)), nlOOii1i = ((((((((((((((~ pmadwidth[0]) | (~ nlli0lO)) | (~ nlli1iO)) | (~ nlli1il)) | (~ nlli1ii)) | (~ nlli10O)) | (~ nlli10l)) | (~ nlli10i)) | (~ nlli11O)) | (~ nlli11l)) | (~ nlli11i)) | (~ nll0OOO)) | (~ nll0OOl)) | (~ wire_n0110il_dataout)), nlOOii1l = (((((((((((pmadwidth[0] | (~ nlli0lO)) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | (~ wire_n0110il_dataout)), nlOOii1O = (((((((((((pmadwidth[0] | (~ nlli0lO)) | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | (~ wire_n0110il_dataout)), nlOOiiii = (((((((((((pmadwidth[0] | (~ nlli0lO)) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | nlli11O) | nlli11l) | nlli11i) | nll0OOO) | (~ wire_n0110il_dataout)), nlOOiiil = (((((((((((pmadwidth[0] | (~ nlli0lO)) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | nlli11O) | nlli11l) | nlli11i) | nll0OOO) | nll0OOl) | (~ wire_n0110il_dataout)), nlOOiiiO = ((((((((((((((~ pmadwidth[0]) | (~ nlli0lO)) | nlli01l) | nlli01i) | nlli1OO) | nlli1Ol) | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | (~ wire_n0110il_dataout)), nlOOiili = ((((((((((((((~ pmadwidth[0]) | (~ nlli0lO)) | nlli01i) | nlli1OO) | nlli1Ol) | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | (~ wire_n0110il_dataout)), nlOOiill = ((((((((((((((~ pmadwidth[0]) | (~ nlli0lO)) | nlli1OO) | nlli1Ol) | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | (~ wire_n0110il_dataout)), nlOOiilO = ((((((((((((((~ pmadwidth[0]) | (~ nlli0lO)) | nlli1Ol) | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | (~ wire_n0110il_dataout)), nlOOiiOi = ((((((((((((((~ pmadwidth[0]) | (~ nlli0lO)) | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | nlli11O) | (~ wire_n0110il_dataout)), nlOOiiOl = ((((((((((((((~ pmadwidth[0]) | (~ nlli0lO)) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | nlli11O) | nlli11l) | (~ wire_n0110il_dataout)), nlOOiiOO = ((((((((((((((~ pmadwidth[0]) | (~ nlli0lO)) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | nlli11O) | nlli11l) | nlli11i) | (~ wire_n0110il_dataout)), nlOOil0i = (((((((((((((((((((nll0OOl & (~ nlOOO0iO)) & (~ nlOOO1Ol)) & (~ nlOOO1Oi)) & (~ nlOOO1lO)) & (~ nlOOO1ll)) & (~ nlOOO1li)) & (~ nlOOO1iO)) & (~ nlOOO1il)) & (~ nlOOO1ii)) & (~ nlOOO10O)) & (~ nlOOO10l)) & (~ nlOOO10i)) & (~ nlOOO11O)) & (~ nlOOO11l)) & (~ nlOOO11i)) & (~ nlOOlOOl)) & (~ nlOOlOlO)) & (~ nlOOlOli)) & (~ nlOOlOiO)), nlOOil0l = ((((((((((~ nlOOiOll) | (~ nlOOiOli)) | (~ nlOOiOii)) | (~ nlOOiO0O)) | (~ nlOOiO1O)) | (~ nlOOiO1l)) | (~ nlOOilOl)) | (~ nlOOilOi)) | (~ nlOOilli)) | (~ nlOOiliO)), nlOOil0O = ((((((((nlOOlOiO | (~ nlOOiOii)) | (~ nlOOiO0O)) | (~ nlOOiO0l)) | (~ nlOOiO0i)) | (~ nlOOilOl)) | (~ nlOOilOi)) | (~ nlOOillO)) | (~ nlOOilll)), nlOOil1i = ((((((((((((((~ pmadwidth[0]) | (~ nlli0lO)) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | nlli11O) | nlli11l) | nlli11i) | nll0OOO) | (~ wire_n0110il_dataout)), nlOOil1l = ((((((((((((((~ pmadwidth[0]) | (~ nlli0lO)) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | nlli11O) | nlli11l) | nlli11i) | nll0OOO) | nll0OOl) | (~ wire_n0110il_dataout)), nlOOil1O = ((((((((((~ nlOOiOll) | (~ nlOOiOiO)) | (~ nlOOiOii)) | (~ nlOOiO0l)) | (~ nlOOiO1O)) | (~ nlOOiO1i)) | (~ nlOOilOl)) | (~ nlOOillO)) | (~ nlOOilli)) | nlOOil0i), nlOOilii = ((((((((~ nlOOiOii) | (~ nlOOiO0O)) | (~ nlOOiO0l)) | (~ nlOOiO0i)) | (~ nlOOiO1O)) | (~ nlOOiO1l)) | (~ nlOOiO1i)) | (~ nlOOilOO)), nlOOilil = ((((nlOOlOiO | (~ nlOOiOll)) | (~ nlOOiOli)) | (~ nlOOiOiO)) | (~ nlOOiOil)), nlOOiliO = ((((((((((((((((((nlOOO0iO | (~ nlOOO1Ol)) | nlOOO1Oi) | nlOOO1lO) | nlOOO1ll) | nlOOO1li) | nlOOO1iO) | nlOOO1il) | nlOOO1ii) | nlOOO10O) | nlOOO10l) | nlOOO10i) | nlOOO11O) | nlOOO11l) | nlOOO11i) | nlOOlOOl) | nlOOlOlO) | nlOOlOli) | nlOOlOiO), nlOOilli = (((((((((((((((((nlOOO0iO | (~ nlOOO1Oi)) | nlOOO1lO) | nlOOO1ll) | nlOOO1li) | nlOOO1iO) | nlOOO1il) | nlOOO1ii) | nlOOO10O) | nlOOO10l) | nlOOO10i) | nlOOO11O) | nlOOO11l) | nlOOO11i) | nlOOlOOl) | nlOOlOlO) | nlOOlOli) | nlOOlOiO), nlOOilll = ((((((((((((((((nlOOO0iO | (~ nlOOO1lO)) | nlOOO1ll) | nlOOO1li) | nlOOO1iO) | nlOOO1il) | nlOOO1ii) | nlOOO10O) | nlOOO10l) | nlOOO10i) | nlOOO11O) | nlOOO11l) | nlOOO11i) | nlOOlOOl) | nlOOlOlO) | nlOOlOli) | nlOOlOiO), nlOOillO = (((((((((((((((nlOOO0iO | (~ nlOOO1ll)) | nlOOO1li) | nlOOO1iO) | nlOOO1il) | nlOOO1ii) | nlOOO10O) | nlOOO10l) | nlOOO10i) | nlOOO11O) | nlOOO11l) | nlOOO11i) | nlOOlOOl) | nlOOlOlO) | nlOOlOli) | nlOOlOiO), nlOOilOi = ((((((((((((((nlOOO0iO | (~ nlOOO1li)) | nlOOO1iO) | nlOOO1il) | nlOOO1ii) | nlOOO10O) | nlOOO10l) | nlOOO10i) | nlOOO11O) | nlOOO11l) | nlOOO11i) | nlOOlOOl) | nlOOlOlO) | nlOOlOli) | nlOOlOiO), nlOOilOl = (((((((((((((nlOOO0iO | (~ nlOOO1iO)) | nlOOO1il) | nlOOO1ii) | nlOOO10O) | nlOOO10l) | nlOOO10i) | nlOOO11O) | nlOOO11l) | nlOOO11i) | nlOOlOOl) | nlOOlOlO) | nlOOlOli) | nlOOlOiO), nlOOilOO = ((((((((((((nlOOO0iO | (~ nlOOO1il)) | nlOOO1ii) | nlOOO10O) | nlOOO10l) | nlOOO10i) | nlOOO11O) | nlOOO11l) | nlOOO11i) | nlOOlOOl) | nlOOlOlO) | nlOOlOli) | nlOOlOiO), nlOOiO0i = ((((((((nlOOO0iO | (~ nlOOO10i)) | nlOOO11O) | nlOOO11l) | nlOOO11i) | nlOOlOOl) | nlOOlOlO) | nlOOlOli) | nlOOlOiO), nlOOiO0l = (((((((nlOOO0iO | (~ nlOOO11O)) | nlOOO11l) | nlOOO11i) | nlOOlOOl) | nlOOlOlO) | nlOOlOli) | nlOOlOiO), nlOOiO0O = ((((((nlOOO0iO | (~ nlOOO11l)) | nlOOO11i) | nlOOlOOl) | nlOOlOlO) | nlOOlOli) | nlOOlOiO), nlOOiO1i = (((((((((((nlOOO0iO | (~ nlOOO1ii)) | nlOOO10O) | nlOOO10l) | nlOOO10i) | nlOOO11O) | nlOOO11l) | nlOOO11i) | nlOOlOOl) | nlOOlOlO) | nlOOlOli) | nlOOlOiO), nlOOiO1l = ((((((((((nlOOO0iO | (~ nlOOO10O)) | nlOOO10l) | nlOOO10i) | nlOOO11O) | nlOOO11l) | nlOOO11i) | nlOOlOOl) | nlOOlOlO) | nlOOlOli) | nlOOlOiO), nlOOiO1O = (((((((((nlOOO0iO | (~ nlOOO10l)) | nlOOO10i) | nlOOO11O) | nlOOO11l) | nlOOO11i) | nlOOlOOl) | nlOOlOlO) | nlOOlOli) | nlOOlOiO), nlOOiOii = (((((nlOOO0iO | (~ nlOOO11i)) | nlOOlOOl) | nlOOlOlO) | nlOOlOli) | nlOOlOiO), nlOOiOil = (((((~ nlOOO0iO) | nlOOlOOl) | nlOOlOlO) | nlOOlOli) | nlOOlOiO), nlOOiOiO = ((((~ nlOOlOOl) | nlOOlOlO) | nlOOlOli) | nlOOlOiO), nlOOiOli = (((~ nlOOlOlO) | nlOOlOli) | nlOOlOiO), nlOOiOll = ((~ nlOOlOli) | nlOOlOiO), nlOOiOlO = ((((((((((~ nlOOl00l) | (~ nlOOl01O)) | (~ nlOOl01i)) | (~ nlOOl1Ol)) | (~ nlOOl1lO)) | (~ nlOOl1li)) | (~ nlOOl1il)) | (~ nlOOl10O)) | (~ nlOOl10i)) | nlOOiOOi), nlOOiOOi = ((((((((((((((((((((nlOOOO1O | nlOOOO1l) & (~ nlOOOO1i)) & (~ nlOOOlOO)) & (~ nlOOOlOl)) & (~ nlOOOlll)) & (~ nlOOOlil)) & (~ nlOOOl0l)) & (~ nlOOOl1l)) & (~ nlOOOiOl)) & (~ nlOOOill)) & (~ nlOOOiil)) & (~ nlOOOi0l)) & (~ nlOOOi1l)) & (~ nlOOO0Ol)) & (~ nlOOO0ll)) & (~ nlOOO0il)) & (~ nlOOO00O)) & (~ nlOOO00i)) & (~ nlOOO01l)) & (~ nlOOO1OO)), nlOOiOOl = ((((((((((~ nlOOl00l) | (~ nlOOl00i)) | (~ nlOOl01i)) | (~ nlOOl1OO)) | (~ nlOOl1lO)) | (~ nlOOl1ll)) | (~ nlOOl1il)) | (~ nlOOl1ii)) | (~ nlOOl10i)) | (~ nlOOl11O)), nlOOiOOO = ((((((((nlOOO1OO | (~ nlOOl01i)) | (~ nlOOl1OO)) | (~ nlOOl1Ol)) | (~ nlOOl1Oi)) | (~ nlOOl1il)) | (~ nlOOl1ii)) | (~ nlOOl10O)) | (~ nlOOl10l)), nlOOl00i = (((~ nlOOO00i) | nlOOO01l) | nlOOO1OO), nlOOl00l = ((~ nlOOO01l) | nlOOO1OO), nlOOl00O = ((((((((((~ nlOOliOl) | (~ nlOOlilO)) | (~ nlOOlili)) | (~ nlOOliil)) | (~ nlOOli0O)) | (~ nlOOli0i)) | (~ nlOOli1l)) | (~ nlOOl0OO)) | (~ nlOOl0Oi)) | nlOOl0ii), nlOOl01i = ((((((~ nlOOO0ll) | nlOOO0il) | nlOOO00O) | nlOOO00i) | nlOOO01l) | nlOOO1OO), nlOOl01l = (((((~ nlOOO0il) | nlOOO00O) | nlOOO00i) | nlOOO01l) | nlOOO1OO), nlOOl01O = ((((~ nlOOO00O) | nlOOO00i) | nlOOO01l) | nlOOO1OO), nlOOl0ii = ((((((((((((((((((((~ nll0OOl) & n11100i) & n1111iO) & n1111il) & n1111ii) & n11110O) & n11110l) & n11110i) & n11111O) & n11111l) & n11111i) & nlOOOOOO) & nlOOOOOl) & nlOOOOOi) & nlOOOOlO) & nlOOOOll) & (~ nlOOOOiO)) & (~ nlOOOOii)) & (~ nlOOOO0l)) & (~ nlOOOO0i)), nlOOl0il = ((((((((((~ nlOOliOl) | (~ nlOOliOi)) | (~ nlOOlili)) | (~ nlOOliiO)) | (~ nlOOli0O)) | (~ nlOOli0l)) | (~ nlOOli1l)) | (~ nlOOli1i)) | (~ nlOOl0Oi)) | (~ nlOOl0lO)), nlOOl0iO = ((((((((nlOOOO0i | (~ nlOOlili)) | (~ nlOOliiO)) | (~ nlOOliil)) | (~ nlOOliii)) | (~ nlOOli1l)) | (~ nlOOli1i)) | (~ nlOOl0OO)) | (~ nlOOl0Ol)), nlOOl0li = ((((((((~ nlOOlili) | (~ nlOOliiO)) | (~ nlOOliil)) | (~ nlOOliii)) | (~ nlOOli0O)) | (~ nlOOli0l)) | (~ nlOOli0i)) | (~ nlOOli1O)), nlOOl0ll = ((((nlOOOO0i | (~ nlOOliOl)) | (~ nlOOliOi)) | (~ nlOOlilO)) | (~ nlOOlill)), nlOOl0lO = (((((((((((((((((((~ n11100i) | n1111iO) | (~ n1111il)) | (~ n1111ii)) | (~ n11110O)) | (~ n11110l)) | (~ n11110i)) | (~ n11111O)) | (~ n11111l)) | (~ n11111i)) | (~ nlOOOOOO)) | (~ nlOOOOOl)) | (~ nlOOOOOi)) | (~ nlOOOOlO)) | (~ nlOOOOll)) | nlOOOOiO) | nlOOOOii) | nlOOOO0l) | nlOOOO0i), nlOOl0Oi = ((((((((((((((((((~ n11100i) | n1111il) | (~ n1111ii)) | (~ n11110O)) | (~ n11110l)) | (~ n11110i)) | (~ n11111O)) | (~ n11111l)) | (~ n11111i)) | (~ nlOOOOOO)) | (~ nlOOOOOl)) | (~ nlOOOOOi)) | (~ nlOOOOlO)) | (~ nlOOOOll)) | nlOOOOiO) | nlOOOOii) | nlOOOO0l) | nlOOOO0i), nlOOl0Ol = (((((((((((((((((~ n11100i) | n1111ii) | (~ n11110O)) | (~ n11110l)) | (~ n11110i)) | (~ n11111O)) | (~ n11111l)) | (~ n11111i)) | (~ nlOOOOOO)) | (~ nlOOOOOl)) | (~ nlOOOOOi)) | (~ nlOOOOlO)) | (~ nlOOOOll)) | nlOOOOiO) | nlOOOOii) | nlOOOO0l) | nlOOOO0i), nlOOl0OO = ((((((((((((((((~ n11100i) | n11110O) | (~ n11110l)) | (~ n11110i)) | (~ n11111O)) | (~ n11111l)) | (~ n11111i)) | (~ nlOOOOOO)) | (~ nlOOOOOl)) | (~ nlOOOOOi)) | (~ nlOOOOlO)) | (~ nlOOOOll)) | nlOOOOiO) | nlOOOOii) | nlOOOO0l) | nlOOOO0i), nlOOl10i = ((((((((((((((((((~ nlOOOlOO) | nlOOOlOl) | nlOOOlll) | nlOOOlil) | nlOOOl0l) | nlOOOl1l) | nlOOOiOl) | nlOOOill) | nlOOOiil) | nlOOOi0l) | nlOOOi1l) | nlOOO0Ol) | nlOOO0ll) | nlOOO0il) | nlOOO00O) | nlOOO00i) | nlOOO01l) | nlOOO1OO), nlOOl10l = (((((((((((((((((~ nlOOOlOl) | nlOOOlll) | nlOOOlil) | nlOOOl0l) | nlOOOl1l) | nlOOOiOl) | nlOOOill) | nlOOOiil) | nlOOOi0l) | nlOOOi1l) | nlOOO0Ol) | nlOOO0ll) | nlOOO0il) | nlOOO00O) | nlOOO00i) | nlOOO01l) | nlOOO1OO), nlOOl10O = ((((((((((((((((~ nlOOOlll) | nlOOOlil) | nlOOOl0l) | nlOOOl1l) | nlOOOiOl) | nlOOOill) | nlOOOiil) | nlOOOi0l) | nlOOOi1l) | nlOOO0Ol) | nlOOO0ll) | nlOOO0il) | nlOOO00O) | nlOOO00i) | nlOOO01l) | nlOOO1OO), nlOOl11i = ((((((((~ nlOOl01i) | (~ nlOOl1OO)) | (~ nlOOl1Ol)) | (~ nlOOl1Oi)) | (~ nlOOl1lO)) | (~ nlOOl1ll)) | (~ nlOOl1li)) | (~ nlOOl1iO)), nlOOl11l = ((((nlOOO1OO | (~ nlOOl00l)) | (~ nlOOl00i)) | (~ nlOOl01O)) | (~ nlOOl01l)), nlOOl11O = (((((((((((((((((((~ nlOOOO1i) | nlOOOlOO) | nlOOOlOl) | nlOOOlll) | nlOOOlil) | nlOOOl0l) | nlOOOl1l) | nlOOOiOl) | nlOOOill) | nlOOOiil) | nlOOOi0l) | nlOOOi1l) | nlOOO0Ol) | nlOOO0ll) | nlOOO0il) | nlOOO00O) | nlOOO00i) | nlOOO01l) | nlOOO1OO), nlOOl1ii = (((((((((((((((~ nlOOOlil) | nlOOOl0l) | nlOOOl1l) | nlOOOiOl) | nlOOOill) | nlOOOiil) | nlOOOi0l) | nlOOOi1l) | nlOOO0Ol) | nlOOO0ll) | nlOOO0il) | nlOOO00O) | nlOOO00i) | nlOOO01l) | nlOOO1OO), nlOOl1il = ((((((((((((((~ nlOOOl0l) | nlOOOl1l) | nlOOOiOl) | nlOOOill) | nlOOOiil) | nlOOOi0l) | nlOOOi1l) | nlOOO0Ol) | nlOOO0ll) | nlOOO0il) | nlOOO00O) | nlOOO00i) | nlOOO01l) | nlOOO1OO), nlOOl1iO = (((((((((((((~ nlOOOl1l) | nlOOOiOl) | nlOOOill) | nlOOOiil) | nlOOOi0l) | nlOOOi1l) | nlOOO0Ol) | nlOOO0ll) | nlOOO0il) | nlOOO00O) | nlOOO00i) | nlOOO01l) | nlOOO1OO), nlOOl1li = ((((((((((((~ nlOOOiOl) | nlOOOill) | nlOOOiil) | nlOOOi0l) | nlOOOi1l) | nlOOO0Ol) | nlOOO0ll) | nlOOO0il) | nlOOO00O) | nlOOO00i) | nlOOO01l) | nlOOO1OO), nlOOl1ll = (((((((((((~ nlOOOill) | nlOOOiil) | nlOOOi0l) | nlOOOi1l) | nlOOO0Ol) | nlOOO0ll) | nlOOO0il) | nlOOO00O) | nlOOO00i) | nlOOO01l) | nlOOO1OO), nlOOl1lO = ((((((((((~ nlOOOiil) | nlOOOi0l) | nlOOOi1l) | nlOOO0Ol) | nlOOO0ll) | nlOOO0il) | nlOOO00O) | nlOOO00i) | nlOOO01l) | nlOOO1OO), nlOOl1Oi = (((((((((~ nlOOOi0l) | nlOOOi1l) | nlOOO0Ol) | nlOOO0ll) | nlOOO0il) | nlOOO00O) | nlOOO00i) | nlOOO01l) | nlOOO1OO), nlOOl1Ol = ((((((((~ nlOOOi1l) | nlOOO0Ol) | nlOOO0ll) | nlOOO0il) | nlOOO00O) | nlOOO00i) | nlOOO01l) | nlOOO1OO), nlOOl1OO = (((((((~ nlOOO0Ol) | nlOOO0ll) | nlOOO0il) | nlOOO00O) | nlOOO00i) | nlOOO01l) | nlOOO1OO), nlOOli0i = ((((((((((((~ n11100i) | n11111l) | (~ n11111i)) | (~ nlOOOOOO)) | (~ nlOOOOOl)) | (~ nlOOOOOi)) | (~ nlOOOOlO)) | (~ nlOOOOll)) | nlOOOOiO) | nlOOOOii) | nlOOOO0l) | nlOOOO0i), nlOOli0l = (((((((((((~ n11100i) | n11111i) | (~ nlOOOOOO)) | (~ nlOOOOOl)) | (~ nlOOOOOi)) | (~ nlOOOOlO)) | (~ nlOOOOll)) | nlOOOOiO) | nlOOOOii) | nlOOOO0l) | nlOOOO0i), nlOOli0O = ((((((((((~ n11100i) | nlOOOOOO) | (~ nlOOOOOl)) | (~ nlOOOOOi)) | (~ nlOOOOlO)) | (~ nlOOOOll)) | nlOOOOiO) | nlOOOOii) | nlOOOO0l) | nlOOOO0i), nlOOli1i = (((((((((((((((~ n11100i) | n11110l) | (~ n11110i)) | (~ n11111O)) | (~ n11111l)) | (~ n11111i)) | (~ nlOOOOOO)) | (~ nlOOOOOl)) | (~ nlOOOOOi)) | (~ nlOOOOlO)) | (~ nlOOOOll)) | nlOOOOiO) | nlOOOOii) | nlOOOO0l) | nlOOOO0i), nlOOli1l = ((((((((((((((~ n11100i) | n11110i) | (~ n11111O)) | (~ n11111l)) | (~ n11111i)) | (~ nlOOOOOO)) | (~ nlOOOOOl)) | (~ nlOOOOOi)) | (~ nlOOOOlO)) | (~ nlOOOOll)) | nlOOOOiO) | nlOOOOii) | nlOOOO0l) | nlOOOO0i), nlOOli1O = (((((((((((((~ n11100i) | n11111O) | (~ n11111l)) | (~ n11111i)) | (~ nlOOOOOO)) | (~ nlOOOOOl)) | (~ nlOOOOOi)) | (~ nlOOOOlO)) | (~ nlOOOOll)) | nlOOOOiO) | nlOOOOii) | nlOOOO0l) | nlOOOO0i), nlOOliii = (((((((((~ n11100i) | nlOOOOOl) | (~ nlOOOOOi)) | (~ nlOOOOlO)) | (~ nlOOOOll)) | nlOOOOiO) | nlOOOOii) | nlOOOO0l) | nlOOOO0i), nlOOliil = ((((((((~ n11100i) | nlOOOOOi) | (~ nlOOOOlO)) | (~ nlOOOOll)) | nlOOOOiO) | nlOOOOii) | nlOOOO0l) | nlOOOO0i), nlOOliiO = (((((((~ n11100i) | nlOOOOlO) | (~ nlOOOOll)) | nlOOOOiO) | nlOOOOii) | nlOOOO0l) | nlOOOO0i), nlOOlili = ((((((~ n11100i) | nlOOOOll) | nlOOOOiO) | nlOOOOii) | nlOOOO0l) | nlOOOO0i), nlOOlill = ((((n11100i | nlOOOOiO) | nlOOOOii) | nlOOOO0l) | nlOOOO0i), nlOOlilO = ((((~ nlOOOOiO) | nlOOOOii) | nlOOOO0l) | nlOOOO0i), nlOOliOi = (((~ nlOOOOii) | nlOOOO0l) | nlOOOO0i), nlOOliOl = ((~ nlOOOO0l) | nlOOOO0i), nlOOliOO = ((((((((((~ nlOOlOil) | (~ nlOOlO0O)) | (~ nlOOlO0i)) | (~ nlOOlO1l)) | (~ nlOOllOO)) | (~ nlOOllOi)) | (~ nlOOllll)) | (~ nlOOlliO)) | (~ nlOOllii)) | nlOOll1i), nlOOll0i = ((((((((~ nlOOlO0i) | (~ nlOOlO1O)) | (~ nlOOlO1l)) | (~ nlOOlO1i)) | (~ nlOOllOO)) | (~ nlOOllOl)) | (~ nlOOllOi)) | (~ nlOOlllO)), nlOOll0l = ((((n1111li | (~ nlOOlOil)) | (~ nlOOlOii)) | (~ nlOOlO0O)) | (~ nlOOlO0l)), nlOOll0O = (((((((((((((((((((~ n111lll) | n111lli) | n111liO) | n111l0O) | n111l1O) | n111iOO) | n111ilO) | n111iiO) | n111i0O) | n111i1O) | n1110OO) | n1110lO) | n1110iO) | n11100O) | n11101O) | n11101i) | n1111Ol) | n1111lO) | n1111li), nlOOll1i = (((((((((((((((((((((pmadwidth[0] & (~ nlli01O)) | ((~ pmadwidth[0]) & (~ nlli1Ol))) & (~ n111lll)) & (~ n111lli)) & (~ n111liO)) & (~ n111l0O)) & (~ n111l1O)) & (~ n111iOO)) & (~ n111ilO)) & (~ n111iiO)) & (~ n111i0O)) & (~ n111i1O)) & (~ n1110OO)) & (~ n1110lO)) & (~ n1110iO)) & (~ n11100O)) & (~ n11101O)) & (~ n11101i)) & (~ n1111Ol)) & (~ n1111lO)) & (~ n1111li)), nlOOll1l = ((((((((((~ nlOOlOil) | (~ nlOOlOii)) | (~ nlOOlO0i)) | (~ nlOOlO1O)) | (~ nlOOllOO)) | (~ nlOOllOl)) | (~ nlOOllll)) | (~ nlOOllli)) | (~ nlOOllii)) | (~ nlOOll0O)), nlOOll1O = ((((((((n1111li | (~ nlOOlO0i)) | (~ nlOOlO1O)) | (~ nlOOlO1l)) | (~ nlOOlO1i)) | (~ nlOOllll)) | (~ nlOOllli)) | (~ nlOOlliO)) | (~ nlOOllil)), nlOOllii = ((((((((((((((((((~ n111lli) | n111liO) | n111l0O) | n111l1O) | n111iOO) | n111ilO) | n111iiO) | n111i0O) | n111i1O) | n1110OO) | n1110lO) | n1110iO) | n11100O) | n11101O) | n11101i) | n1111Ol) | n1111lO) | n1111li), nlOOllil = (((((((((((((((((~ n111liO) | n111l0O) | n111l1O) | n111iOO) | n111ilO) | n111iiO) | n111i0O) | n111i1O) | n1110OO) | n1110lO) | n1110iO) | n11100O) | n11101O) | n11101i) | n1111Ol) | n1111lO) | n1111li), nlOOlliO = ((((((((((((((((~ n111l0O) | n111l1O) | n111iOO) | n111ilO) | n111iiO) | n111i0O) | n111i1O) | n1110OO) | n1110lO) | n1110iO) | n11100O) | n11101O) | n11101i) | n1111Ol) | n1111lO) | n1111li), nlOOllli = (((((((((((((((~ n111l1O) | n111iOO) | n111ilO) | n111iiO) | n111i0O) | n111i1O) | n1110OO) | n1110lO) | n1110iO) | n11100O) | n11101O) | n11101i) | n1111Ol) | n1111lO) | n1111li), nlOOllll = ((((((((((((((~ n111iOO) | n111ilO) | n111iiO) | n111i0O) | n111i1O) | n1110OO) | n1110lO) | n1110iO) | n11100O) | n11101O) | n11101i) | n1111Ol) | n1111lO) | n1111li), nlOOlllO = (((((((((((((~ n111ilO) | n111iiO) | n111i0O) | n111i1O) | n1110OO) | n1110lO) | n1110iO) | n11100O) | n11101O) | n11101i) | n1111Ol) | n1111lO) | n1111li), nlOOllOi = ((((((((((((~ n111iiO) | n111i0O) | n111i1O) | n1110OO) | n1110lO) | n1110iO) | n11100O) | n11101O) | n11101i) | n1111Ol) | n1111lO) | n1111li), nlOOllOl = (((((((((((~ n111i0O) | n111i1O) | n1110OO) | n1110lO) | n1110iO) | n11100O) | n11101O) | n11101i) | n1111Ol) | n1111lO) | n1111li), nlOOllOO = ((((((((((~ n111i1O) | n1110OO) | n1110lO) | n1110iO) | n11100O) | n11101O) | n11101i) | n1111Ol) | n1111lO) | n1111li), nlOOlO0i = ((((((~ n11100O) | n11101O) | n11101i) | n1111Ol) | n1111lO) | n1111li), nlOOlO0l = (((((~ n11101O) | n11101i) | n1111Ol) | n1111lO) | n1111li), nlOOlO0O = ((((~ n11101i) | n1111Ol) | n1111lO) | n1111li), nlOOlO1i = (((((((((~ n1110OO) | n1110lO) | n1110iO) | n11100O) | n11101O) | n11101i) | n1111Ol) | n1111lO) | n1111li), nlOOlO1l = ((((((((~ n1110lO) | n1110iO) | n11100O) | n11101O) | n11101i) | n1111Ol) | n1111lO) | n1111li), nlOOlO1O = (((((((~ n1110iO) | n11100O) | n11101O) | n11101i) | n1111Ol) | n1111lO) | n1111li), nlOOlOii = (((~ n1111Ol) | n1111lO) | n1111li), nlOOlOil = ((~ n1111lO) | n1111li), nlOOlOiO = (pmadwidth[0] & nlOOO01i), nlOOlOli = (pmadwidth[0] & nlOOlOll), nlOOlOll = ((((((((((((((((((nlli01l & nlli01i) & nlli1OO) & nlli1Ol) & nlli1Oi) & nlli1lO) & nlli1ll) & nlli1li) & nlli1iO) & nlli1il) & nlli1ii) & nlli10O) & nlli10l) & nlli10i) & nlli11O) & nlli11l) & nlli11i) & nll0OOO) & nll0OOl), nlOOlOlO = (pmadwidth[0] & nlOOlOOi), nlOOlOOi = (((((((((((((((((nlli01i & nlli1OO) & nlli1Ol) & nlli1Oi) & nlli1lO) & nlli1ll) & nlli1li) & nlli1iO) & nlli1il) & nlli1ii) & nlli10O) & nlli10l) & nlli10i) & nlli11O) & nlli11l) & nlli11i) & nll0OOO) & nll0OOl), nlOOlOOl = (pmadwidth[0] & nlOOlOOO), nlOOlOOO = ((((((((((((((((nlli1OO & nlli1Ol) & nlli1Oi) & nlli1lO) & nlli1ll) & nlli1li) & nlli1iO) & nlli1il) & nlli1ii) & nlli10O) & nlli10l) & nlli10i) & nlli11O) & nlli11l) & nlli11i) & nll0OOO) & nll0OOl), nlOOO00i = (pmadwidth[0] & nlOOO00l), nlOOO00l = (((((((((((((((((nlli01O & nlli01l) & nlli01i) & nlli1OO) & nlli1Ol) & nlli1Oi) & nlli1lO) & nlli1ll) & nlli1li) & nlli1iO) & nlli1il) & nlli1ii) & nlli10O) & nlli10l) & nlli10i) & nlli11O) & nlli11l) & nlli11i), nlOOO00O = (pmadwidth[0] & nlOOO0ii), nlOOO01i = (((((((((((((((((((nlli01O & nlli01l) & nlli01i) & nlli1OO) & nlli1Ol) & nlli1Oi) & nlli1lO) & nlli1ll) & nlli1li) & nlli1iO) & nlli1il) & nlli1ii) & nlli10O) & nlli10l) & nlli10i) & nlli11O) & nlli11l) & nlli11i) & nll0OOO) & nll0OOl), nlOOO01l = (pmadwidth[0] & nlOOO01O), nlOOO01O = ((((((((((((((((((nlli01O & nlli01l) & nlli01i) & nlli1OO) & nlli1Ol) & nlli1Oi) & nlli1lO) & nlli1ll) & nlli1li) & nlli1iO) & nlli1il) & nlli1ii) & nlli10O) & nlli10l) & nlli10i) & nlli11O) & nlli11l) & nlli11i) & nll0OOO), nlOOO0ii = ((((((((((((((((nlli01O & nlli01l) & nlli01i) & nlli1OO) & nlli1Ol) & nlli1Oi) & nlli1lO) & nlli1ll) & nlli1li) & nlli1iO) & nlli1il) & nlli1ii) & nlli10O) & nlli10l) & nlli10i) & nlli11O) & nlli11l), nlOOO0il = ((pmadwidth[0] & nlOOO0li) | ((~ pmadwidth[0]) & nlOOO0iO)), nlOOO0iO = (((((((((((((((nlli1Ol & nlli1Oi) & nlli1lO) & nlli1ll) & nlli1li) & nlli1iO) & nlli1il) & nlli1ii) & nlli10O) & nlli10l) & nlli10i) & nlli11O) & nlli11l) & nlli11i) & nll0OOO) & nll0OOl), nlOOO0li = (((((((((((((((nlli01O & nlli01l) & nlli01i) & nlli1OO) & nlli1Ol) & nlli1Oi) & nlli1lO) & nlli1ll) & nlli1li) & nlli1iO) & nlli1il) & nlli1ii) & nlli10O) & nlli10l) & nlli10i) & nlli11O), nlOOO0ll = ((pmadwidth[0] & nlOOO0Oi) | ((~ pmadwidth[0]) & nlOOO0lO)), nlOOO0lO = ((((((((((((((nlli1Ol & nlli1Oi) & nlli1lO) & nlli1ll) & nlli1li) & nlli1iO) & nlli1il) & nlli1ii) & nlli10O) & nlli10l) & nlli10i) & nlli11O) & nlli11l) & nlli11i) & nll0OOO), nlOOO0Oi = ((((((((((((((nlli01O & nlli01l) & nlli01i) & nlli1OO) & nlli1Ol) & nlli1Oi) & nlli1lO) & nlli1ll) & nlli1li) & nlli1iO) & nlli1il) & nlli1ii) & nlli10O) & nlli10l) & nlli10i), nlOOO0Ol = ((pmadwidth[0] & nlOOOi1i) | ((~ pmadwidth[0]) & nlOOO0OO)), nlOOO0OO = (((((((((((((nlli1Ol & nlli1Oi) & nlli1lO) & nlli1ll) & nlli1li) & nlli1iO) & nlli1il) & nlli1ii) & nlli10O) & nlli10l) & nlli10i) & nlli11O) & nlli11l) & nlli11i), nlOOO10i = (((((((((((nlli1li & nlli1iO) & nlli1il) & nlli1ii) & nlli10O) & nlli10l) & nlli10i) & nlli11O) & nlli11l) & nlli11i) & nll0OOO) & nll0OOl), nlOOO10l = ((((((((((nlli1iO & nlli1il) & nlli1ii) & nlli10O) & nlli10l) & nlli10i) & nlli11O) & nlli11l) & nlli11i) & nll0OOO) & nll0OOl), nlOOO10O = (((((((((nlli1il & nlli1ii) & nlli10O) & nlli10l) & nlli10i) & nlli11O) & nlli11l) & nlli11i) & nll0OOO) & nll0OOl), nlOOO11i = ((((((((((((((nlli1Oi & nlli1lO) & nlli1ll) & nlli1li) & nlli1iO) & nlli1il) & nlli1ii) & nlli10O) & nlli10l) & nlli10i) & nlli11O) & nlli11l) & nlli11i) & nll0OOO) & nll0OOl), nlOOO11l = (((((((((((((nlli1lO & nlli1ll) & nlli1li) & nlli1iO) & nlli1il) & nlli1ii) & nlli10O) & nlli10l) & nlli10i) & nlli11O) & nlli11l) & nlli11i) & nll0OOO) & nll0OOl), nlOOO11O = ((((((((((((nlli1ll & nlli1li) & nlli1iO) & nlli1il) & nlli1ii) & nlli10O) & nlli10l) & nlli10i) & nlli11O) & nlli11l) & nlli11i) & nll0OOO) & nll0OOl), nlOOO1ii = ((((((((nlli1ii & nlli10O) & nlli10l) & nlli10i) & nlli11O) & nlli11l) & nlli11i) & nll0OOO) & nll0OOl), nlOOO1il = (((((((nlli10O & nlli10l) & nlli10i) & nlli11O) & nlli11l) & nlli11i) & nll0OOO) & nll0OOl), nlOOO1iO = ((((((nlli10l & nlli10i) & nlli11O) & nlli11l) & nlli11i) & nll0OOO) & nll0OOl), nlOOO1li = (((((nlli10i & nlli11O) & nlli11l) & nlli11i) & nll0OOO) & nll0OOl), nlOOO1ll = ((((nlli11O & nlli11l) & nlli11i) & nll0OOO) & nll0OOl), nlOOO1lO = (((nlli11l & nlli11i) & nll0OOO) & nll0OOl), nlOOO1Oi = ((nlli11i & nll0OOO) & nll0OOl), nlOOO1Ol = (nll0OOO & nll0OOl), nlOOO1OO = (pmadwidth[0] & nlOOO01i), nlOOOi0i = ((((((((((((nlli01O & nlli01l) & nlli01i) & nlli1OO) & nlli1Ol) & nlli1Oi) & nlli1lO) & nlli1ll) & nlli1li) & nlli1iO) & nlli1il) & nlli1ii) & nlli10O), nlOOOi0l = ((pmadwidth[0] & nlOOOiii) | ((~ pmadwidth[0]) & nlOOOi0O)), nlOOOi0O = (((((((((((nlli1Ol & nlli1Oi) & nlli1lO) & nlli1ll) & nlli1li) & nlli1iO) & nlli1il) & nlli1ii) & nlli10O) & nlli10l) & nlli10i) & nlli11O), nlOOOi1i = (((((((((((((nlli01O & nlli01l) & nlli01i) & nlli1OO) & nlli1Ol) & nlli1Oi) & nlli1lO) & nlli1ll) & nlli1li) & nlli1iO) & nlli1il) & nlli1ii) & nlli10O) & nlli10l), nlOOOi1l = ((pmadwidth[0] & nlOOOi0i) | ((~ pmadwidth[0]) & nlOOOi1O)), nlOOOi1O = ((((((((((((nlli1Ol & nlli1Oi) & nlli1lO) & nlli1ll) & nlli1li) & nlli1iO) & nlli1il) & nlli1ii) & nlli10O) & nlli10l) & nlli10i) & nlli11O) & nlli11l), nlOOOiii = (((((((((((nlli01O & nlli01l) & nlli01i) & nlli1OO) & nlli1Ol) & nlli1Oi) & nlli1lO) & nlli1ll) & nlli1li) & nlli1iO) & nlli1il) & nlli1ii), nlOOOiil = ((pmadwidth[0] & nlOOOili) | ((~ pmadwidth[0]) & nlOOOiiO)), nlOOOiiO = ((((((((((nlli1Ol & nlli1Oi) & nlli1lO) & nlli1ll) & nlli1li) & nlli1iO) & nlli1il) & nlli1ii) & nlli10O) & nlli10l) & nlli10i), nlOOOili = ((((((((((nlli01O & nlli01l) & nlli01i) & nlli1OO) & nlli1Ol) & nlli1Oi) & nlli1lO) & nlli1ll) & nlli1li) & nlli1iO) & nlli1il), nlOOOill = ((pmadwidth[0] & nlOOOiOi) | ((~ pmadwidth[0]) & nlOOOilO)), nlOOOilO = (((((((((nlli1Ol & nlli1Oi) & nlli1lO) & nlli1ll) & nlli1li) & nlli1iO) & nlli1il) & nlli1ii) & nlli10O) & nlli10l), nlOOOiOi = (((((((((nlli01O & nlli01l) & nlli01i) & nlli1OO) & nlli1Ol) & nlli1Oi) & nlli1lO) & nlli1ll) & nlli1li) & nlli1iO), nlOOOiOl = ((pmadwidth[0] & nlOOOl1i) | ((~ pmadwidth[0]) & nlOOOiOO)), nlOOOiOO = ((((((((nlli1Ol & nlli1Oi) & nlli1lO) & nlli1ll) & nlli1li) & nlli1iO) & nlli1il) & nlli1ii) & nlli10O), nlOOOl0i = (((((((nlli01O & nlli01l) & nlli01i) & nlli1OO) & nlli1Ol) & nlli1Oi) & nlli1lO) & nlli1ll), nlOOOl0l = ((pmadwidth[0] & nlOOOlii) | ((~ pmadwidth[0]) & nlOOOl0O)), nlOOOl0O = ((((((nlli1Ol & nlli1Oi) & nlli1lO) & nlli1ll) & nlli1li) & nlli1iO) & nlli1il), nlOOOl1i = ((((((((nlli01O & nlli01l) & nlli01i) & nlli1OO) & nlli1Ol) & nlli1Oi) & nlli1lO) & nlli1ll) & nlli1li), nlOOOl1l = ((pmadwidth[0] & nlOOOl0i) | ((~ pmadwidth[0]) & nlOOOl1O)), nlOOOl1O = (((((((nlli1Ol & nlli1Oi) & nlli1lO) & nlli1ll) & nlli1li) & nlli1iO) & nlli1il) & nlli1ii), nlOOOlii = ((((((nlli01O & nlli01l) & nlli01i) & nlli1OO) & nlli1Ol) & nlli1Oi) & nlli1lO), nlOOOlil = ((pmadwidth[0] & nlOOOlli) | ((~ pmadwidth[0]) & nlOOOliO)), nlOOOliO = (((((nlli1Ol & nlli1Oi) & nlli1lO) & nlli1ll) & nlli1li) & nlli1iO), nlOOOlli = (((((nlli01O & nlli01l) & nlli01i) & nlli1OO) & nlli1Ol) & nlli1Oi), nlOOOlll = ((pmadwidth[0] & nlOOOlOi) | ((~ pmadwidth[0]) & nlOOOllO)), nlOOOllO = ((((nlli1Ol & nlli1Oi) & nlli1lO) & nlli1ll) & nlli1li), nlOOOlOi = ((((nlli01O & nlli01l) & nlli01i) & nlli1OO) & nlli1Ol), nlOOOlOl = ((pmadwidth[0] & (((nlli01O & nlli01l) & nlli01i) & nlli1OO)) | ((~ pmadwidth[0]) & (((nlli1Ol & nlli1Oi) & nlli1lO) & nlli1ll))), nlOOOlOO = ((pmadwidth[0] & ((nlli01O & nlli01l) & nlli01i)) | ((~ pmadwidth[0]) & ((nlli1Ol & nlli1Oi) & nlli1lO))), nlOOOO0i = (pmadwidth[0] & (~ n1111ll)), nlOOOO0l = (pmadwidth[0] & (~ nlOOOO0O)), nlOOOO0O = ((((((((((((((((((nlli01l | nlli01i) | nlli1OO) | nlli1Ol) | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | nlli11O) | nlli11l) | nlli11i) | nll0OOO) | nll0OOl), nlOOOO1i = ((pmadwidth[0] & (nlli01O & nlli01l)) | ((~ pmadwidth[0]) & (nlli1Ol & nlli1Oi))), nlOOOO1l = ((~ pmadwidth[0]) & nlli1Ol), nlOOOO1O = (pmadwidth[0] & nlli01O), nlOOOOii = (pmadwidth[0] & (~ nlOOOOil)), nlOOOOil = (((((((((((((((((nlli01i | nlli1OO) | nlli1Ol) | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | nlli11O) | nlli11l) | nlli11i) | nll0OOO) | nll0OOl), nlOOOOiO = (pmadwidth[0] & (~ nlOOOOli)), nlOOOOli = ((((((((((((((((nlli1OO | nlli1Ol) | nlli1Oi) | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | nlli11O) | nlli11l) | nlli11i) | nll0OOO) | nll0OOl), nlOOOOll = ((((((((((((((nlli1Oi | nlli1lO) | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | nlli11O) | nlli11l) | nlli11i) | nll0OOO) | nll0OOl), nlOOOOlO = (((((((((((((nlli1lO | nlli1ll) | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | nlli11O) | nlli11l) | nlli11i) | nll0OOO) | nll0OOl), nlOOOOOi = ((((((((((((nlli1ll | nlli1li) | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | nlli11O) | nlli11l) | nlli11i) | nll0OOO) | nll0OOl), nlOOOOOl = (((((((((((nlli1li | nlli1iO) | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | nlli11O) | nlli11l) | nlli11i) | nll0OOO) | nll0OOl), nlOOOOOO = ((((((((((nlli1iO | nlli1il) | nlli1ii) | nlli10O) | nlli10l) | nlli10i) | nlli11O) | nlli11l) | nlli11i) | nll0OOO) | nll0OOl), rlv = wire_n0il_dataout, rlv_lt = wire_n0ii_dataout, rst1 = wire_ni0lO_dataout, signal_detect_rcvdclk = signal_detect, sudi = {wire_nlll_dataout, wire_nlli_dataout, wire_nliO_dataout, wire_nlil_dataout, wire_nlii_dataout, wire_nl0O_dataout, wire_nl0l_dataout, wire_nl0i_dataout, wire_nl1O_dataout, wire_nl1l_dataout, wire_nl1i_dataout, wire_niOO_dataout, wire_niOl_dataout, wire_niOi_dataout, wire_nilO_dataout, wire_nill_dataout, wire_nili_dataout, wire_niiO_dataout, wire_niil_dataout, wire_niii_dataout, wire_ni0O_dataout, wire_ni0l_dataout, wire_ni0i_dataout, wire_ni1O_dataout, wire_ni1l_dataout, wire_ni1i_dataout, wire_n0OO_dataout, wire_n0Ol_dataout, wire_n0Oi_dataout, wire_n0lO_dataout, wire_n0ll_dataout, wire_n0li_dataout}, sudi_pre = {wire_n110ll_dataout, n1ii0iO, ((((pmadwidth[0] & n1ii0Ol) | n1ii0Oi) | (~ (n1ii0ll16 ^ n1ii0ll15))) | n1ii0li), (~ wire_n1l1Ol_dataout), wire_niOl0l_dataout, wire_niOl0i_dataout, wire_niOl1O_o, wire_niOl1l_o, wire_niOl1i_o, wire_niOiOO_o, wire_niOiOl_o, wire_niOiOi_o, wire_niOilO_o, wire_niOill_o}, sync_status = wire_n0iO_dataout, testbus = {wire_nil_dataout, wire_nii_dataout, wire_n0O_dataout, wire_n0l_dataout, wire_n0i_dataout, wire_n1O_dataout, wire_n1l_dataout, wire_n1i_dataout, wire_nlOO_dataout, wire_nlOl_dataout}, wa_boundary = {wire_nii0l_dataout, wire_nii0i_dataout, wire_nii1O_dataout, wire_nii1l_dataout, wire_nii1i_dataout}; endmodule //stratixiv_hssi_rx_digi_wordalign //synopsys translate_on //VALID FILE `timescale 1 ps / 1 ps module stratixiv_hssi_rx_digi ( hard_reset, rxpcs_rst, rxpma_rst, cmpfifourst, phfifourst_rx, scan_mode, encdt, a1a2_size, bitslip, rdenable_rmf, wrenable_rmf, pld_rx_clk, soft_reset_rclk1, polinv_rx, bitloc_rev_en, byte_rev_en, rcvd_clk_pma, pudi, sigdetni, fifo_rst_rd_qd, fifo_rst_rd_gp, en_dskw_qd, en_dskw_gp, is_lane0, align_status, align_status_sync_0, align_status_sync_2, // S. Park 3/21/08 - Removed following ports // disable_fifo_rd_0, // disable_fifo_wr_0, // disable_fifo_rd, // disable_fifo_wr, rx_data_rs, rx_control_rs, rcvd_clk0_pma, fifo_rd_in_comp_0, fifo_rd_in_comp_2, txlp20b, refclk_pma, tx_pma_clk, fref, clklow, bytordpld, wrdisable_rx, rdenable_rx, pma_testbus, encoder_testbus, tx_ctrl_testbus, phystatus_int,rxvalid_int,rxstatus_int,powerdown, fifo_rd_out_comp, rxd, rev_loop_data, rx_clk, bisterr, cg_comma, clk_2_b, rcvd_clk_pma_b, sync_status, align_status_sync, dec_data_valid, dec_data, dec_ctl, running_disp, selftest_done, selftest_err, err_data, err_ctl, prbs_done, prbs_err_lt, signal_detect_out, align_det_sync, rd_align, bistdone, rlv, rlv_lt, almost_fl_rmf, full_rmf, almost_mt_rmf, empty_rmf, freq_lock, full_rx, empty_rx, a1a2_k1k2_flag, byteord_flag, rx_pipe_clk, chnl_test_bus_out, rx_pipe_soft_reset, phystatus, rxvalid, rxstatus,pipe_data, rskpsetbased, rtruebac2bac, rcmpfifourst, rphfifourstrx, rcomp_size, rcomp_pat, rrundisp, rib_inv_cd, rrlv_en, rsync_sm_dis, rautobtalg_dis, rdis_rx_disp, rmatchen, rgenericfifo, rendec_rx, rdwidth_rx, rlp20ben, rrxfifo_dis, rpmadwidth_rx, rpma_doublewidth_rx, renumber, rknumber, renpolinv_rx, rgnumber, rclkcmpsqmd, rclkcmpsq1p, rclkcmpsq1n, rclkcmp_pipe_en, rosnumber, rosbased, rkchar, rcascaded_8b10b_en_rx, resync_badcg_en, rencdt_rising, rcomp_pat_porn, rprbsen_rx, rprbs_clr_rslt_rx, rbisten_rx, rbist_clr_rx, rwa_6g_en, rbytord_2sym_en, rbysync_polinv_en, rbytord_6g_mask_en,rbytord_s2gx, rbitloc_rev_en, rbyte_rev_en, rbyteorden, rbytordplden, rphfifopldenrx, rautoinsdis, rppmsel, rforce0_freqdet, rforce1_freqdet, rbytordpat, rbytordpad, rforce_sig_det_pcs, rfreerun_rx, rrcvd_clk_sel, rclk_1_sel, rclk_2_sel, rrx_rd_clk_sel, rall_one_dect_only, rtest_bus_sel, r8b10b_dec_ibm_en, rrxfifo_lowlatency_en, rppm_cnt_reset, sel_gp_md, rclkcmpinsertpad, rindv_rx, dskwclksel, rdskposdisp, rdskchrp, rendec_data_sel_rx, rprbs_sel, rbist_sel, rcxpat_chnl_en, rstart_threshold, rins_threshold, rdel_threshold, rfull_threshold, rempty_threshold, rinvalid_code_err_only,rrx_pipe_enable, rrxpcsbypass_en, rfts_count, rpcs_wrapback_en, rcid_pattern_rx, rcid_len_rx, //new for auto-nego rauto_speed_ena, rphfifo_regmode_rx, rfreq_sel, rate, gen2ngen1, gen2ngen1_bundle, speed_change, rx_div2_sync_in_centrl, rx_div2_sync_in_quad_up, rx_div2_sync_in_quad_down, reset_pc_ptrs_in_centrl, reset_pc_ptrs_in_quad_up, reset_pc_ptrs_in_quad_down, wr_enable_in_centrl, wr_enable_in_quad_up, wr_enable_in_quad_down, rd_enable_in_centrl, rd_enable_in_quad_up, rd_enable_in_quad_down, rx_we_in_centrl, rx_we_in_quad_up, rx_we_in_quad_down, speed_change_in_centrl, rx_div2_sync_in_pipe_quad_up, rx_div2_sync_in_pipe_quad_down, reset_pc_ptrs_in_pipe_quad_up, reset_pc_ptrs_in_pipe_quad_down, wr_enable_in_pipe_quad_up, wr_enable_in_pipe_quad_down, rd_enable_in_pipe_quad_up, rd_enable_in_pipe_quad_down, rx_we_in_pipe_quad_up, rx_we_in_pipe_quad_down, speed_change_in_pipe_quad_up, speed_change_in_pipe_quad_down, config_sel_centrl, config_sel_quad_up, config_sel_quad_down, // new MDIO inputs for bundling and auto speed rmaster_rx, rmaster_up_rx, rpipeline_bypass_rx, rauto_deassert_pc_rst_cnt, rauto_pc_en_cnt, rself_sw_en_rx, // new outputs for bundling and auto speed rx_div2_sync_out_pipe_up, rx_we_out_pipe_up, wr_enable_out_pipe_up, rd_enable_out_pipe_up, reset_pc_ptrs_out_pipe_up, speed_change_out_pipe_up, rx_div2_sync_out_pipe_down, rx_we_out_pipe_down, wr_enable_out_pipe_down, rd_enable_out_pipe_down, reset_pc_ptrs_out_pipe_down, speed_change_out_pipe_down, dis_pc_byte, reset_pc_ptrs, pcie_switch, //new for Eidle inference reidleinferenable, reidle_com_detect, eidleinfersel, pipe_loopbk, rxelecidle_int, rpma_done_count, riei_eios_priority_dis, rgen1_sigdet_ena, rerr_flags_sel, rrxpcsclkpwdn, // CDR control rcdr_ctrl_en, rcid_en, rrxvalid_mask, rwait_count, rmask_count, pld_ltr, early_eios, ltr, prbs_cid_en, wa_boundary, tx_div2_sync_out_pipe_up, fifo_select_out_pipe_up, tx_wr_enable_out_pipe_up, tx_rd_enable_out_pipe_up, tx_div2_sync_out_pipe_down, fifo_select_out_pipe_down, tx_wr_enable_out_pipe_down, tx_rd_enable_out_pipe_down, rwait_for_phfifo_cnt, rppm_post_eidle_del, rppm_gen1_2xcnt_en, // S. Park 3/13/08 - Added for XAUI compliance cg_comp_rd_d_ch0, cg_comp_rd_d_ch1, cg_comp_rd_d_ch2, cg_comp_rd_d_ch3, cg_comp_wr_ch0, cg_comp_wr_ch1, cg_comp_wr_ch2, cg_comp_wr_ch3, cg_comp_rd_d_out, cg_comp_wr_out, // S. Park 3/21/08 - Added for XAUI compliance del_cond_met_0, fifo_ovr_0, latency_comp_0, insert_incomplete_0, del_cond_met_out, fifo_ovr_out, latency_comp_out, insert_incomplete_out, pcs_wrapback_in ); // Reset inputs input hard_reset; // From MDIO_REG.V Complex function of NPOR, ENTEST etc., input rxpcs_rst; // RX PCS resets input rxpma_rst; // RX PMA reset for PPM Detect input cmpfifourst; // User reset exclusive to comp_chnl_top & below input phfifourst_rx; // User reset exclusive to rx_ctrl & below // Scan inputs input scan_mode; // 1'b1 = scan mode active; // 1'b0 = normal mode // RX PCS channel inputs/outputs input encdt; // Comma Detect enable control signal from PLD input a1a2_size; // A1A2 size control signal for byte sync block input bitslip; // Bitslip control signal from PLD input rdenable_rmf; // Read enable control signal for CompFIFO input wrenable_rmf; // Write enable control signal for CompFIFO input pld_rx_clk; // Parallel receive clock from PLD output soft_reset_rclk1; // Synchronized reset input polinv_rx; // RX polarity inversion dynamic control signal input bitloc_rev_en; // RX bit reversal dynamic control signal input byte_rev_en; // RX byte swap dynamic control signal input rcvd_clk_pma; input [19:0] pudi; // RX 10-bit code group bus from RX PMA input sigdetni; // rx signal detected from PMA input fifo_rst_rd_qd; // from master deskew sm input fifo_rst_rd_gp; // from grouping deskew sm input en_dskw_qd; // from master deskew sm input en_dskw_gp; // from grouping deskew sm input is_lane0; // This is lane 0 if 1'b1. Hard-wired // when chnl_top is instantiated input align_status; // Indicate that four lanes are now // aligned in dskw_top input align_status_sync_0; // Synced to clk_2 from channel 0 input align_status_sync_2; // Synced to clk_2 from channel 2 // S. Park 3/21/08 - Removed below two ports // input disable_fifo_rd_0; // disable_fifo_rd from channel 0 // input disable_fifo_wr_0; // disable_fifo_wr from channel 0 input [7:0] rx_data_rs; // rx data from 10G ethernet rx state machine input rx_control_rs; // rx control from 10G ethernet rx state machine input rcvd_clk0_pma; // Recovered clock from PMA channel0 input fifo_rd_in_comp_0; // fifo_rd_in_comp from channel 0 input fifo_rd_in_comp_2; // fifo_rd_in_comp from channel 2 input [19:0] txlp20b; // tx 20-bit code group bus to PMA input refclk_pma; // Global parallel TX PLL clock input tx_pma_clk; // Per channel TX PMA clock input fref; // Reference clock for FREQDET module input clklow; // Divided clock for FREQDET module input bytordpld; // Byte ordering dynamic control signal from PLD input wrdisable_rx; // RX phase comp. FIFO write disable control signal input rdenable_rx; // RX phase comp. FIFO read enable control signal input [7:0] pma_testbus; // PMA digital testbus output input [9:0] encoder_testbus; // Test bus from 8B10B encoder input [9:0] tx_ctrl_testbus; // Test bus from TX FIFO // Removed old bundling mode inputs // input [3:0] rxfifo_shared_sig_in_ch0; // TX FIFO shared signal from channel 0 // input [3:0] rxfifo_shared_sig_in_q0_ch0; // TX FIFO shared signal from channel 0 of Quad 0 input phystatus_int; input rxvalid_int; input [2:0] rxstatus_int; input [1:0] powerdown; input rate; // rate change output from upper layers. input gen2ngen1; // frequency switch done from PMA (rising edge of old clock to rising edge of new clock) input gen2ngen1_bundle; // for bundle input [2:0] eidleinfersel; // Electrical Idle inference mechanism select input pipe_loopbk; // reverse parallel loopback requires 4 EIOS to be transmitted up to the upper layer. Used in the CDR // control block and electrical idle inference module // LMC 01/21/08 input rerr_flags_sel; input rrxpcsclkpwdn; // CDR control input pld_ltr; // PLD control of the CDR when rcdr_ctrl_en = 1'b0 input prbs_cid_en; // PLD control of PRBS-CID enable input tx_div2_sync_out_pipe_up; input fifo_select_out_pipe_up; input tx_wr_enable_out_pipe_up; input tx_rd_enable_out_pipe_up; input tx_div2_sync_out_pipe_down; input fifo_select_out_pipe_down; input tx_wr_enable_out_pipe_down; input tx_rd_enable_out_pipe_down; // S. Park 3/13/08 - Added for XAUI compliance input cg_comp_rd_d_ch0; input cg_comp_rd_d_ch1; input cg_comp_rd_d_ch2; input cg_comp_rd_d_ch3; input cg_comp_wr_ch0; input cg_comp_wr_ch1; input cg_comp_wr_ch2; input cg_comp_wr_ch3; // S. Park 3/21/08 - Added for XAUI compliance input del_cond_met_0; input fifo_ovr_0; input latency_comp_0; input insert_incomplete_0; // removed old bundling mode outputs // output [3:0] rxfifo_shared_sig_out; // TX FIFO shared signal output output fifo_rd_out_comp; output [63:0] rxd; // XGMII rx data to PLD output [19:0] rev_loop_data; // 10 bit data from RX rate matching // FIFO, reverse loopback output rx_clk; // XGMII rx clock to PLD output bisterr; // BIST or PRBS done status signal output [1:0] cg_comma; // comma is detected in sync_chnl_top to PMA output clk_2_b; // clk_2 to rcv_sm output rcvd_clk_pma_b; output sync_status; // Indicate that this lane is now synchronized // S. Park 3/21/08 - Removed below two ports // output disable_fifo_rd; // disable_fifo_rd from this lane // output disable_fifo_wr; // disable_fifo_wr from this lane output align_status_sync; // synced to clk_2 output dec_data_valid; output [7:0] dec_data; // decoded 8-bit RX data to XAUI RX SM output dec_ctl; // decoded RX control to XAUI RX SM output [1:0] running_disp; // indicate that dec_data/dec_ctl is // either not valid or having disparity error output selftest_done; // Status shows that the self test checking is done output selftest_err; // Status shows that the selftest is successful output [15:0] err_data; // When the self test fails, this records // the first byte that error occurs to. output [1:0] err_ctl; // When the self test fails, this records // the first byte that error occurs to. output prbs_done; // Indicate that prbs verification is done output prbs_err_lt; // Indicate that prbs verification is OK // - latched version, cleared when reset output signal_detect_out; // SIGDET out to PLD output align_det_sync; // Channel is aligned, present for 10 clocks output rd_align; // Read data has an Align code group output bistdone; output rlv; output rlv_lt; // RLV status signal to PLD output almost_fl_rmf; // Comp FIFO almost full flag output full_rmf; // Comp FIFO full flag output almost_mt_rmf; // Comp FIFO almost empty flag output empty_rmf; // Comp FIFO empty flag output freq_lock; // Frequency lock output flag for PMA output full_rx; // RX Phase comp. FIFO full flag output empty_rx; // RX Phase comp. FIFO empty flag output [3:0] a1a2_k1k2_flag; // A1A2K1K2 output flag output byteord_flag; // Byte ordering successfull output flag output rx_pipe_clk; // Output clock for RX PIPE interface output [9:0] chnl_test_bus_out; // Channel digital testbus output output rx_pipe_soft_reset; // RX PIPE soft reset output phystatus; output rxvalid; output [2:0] rxstatus; output [63:0] pipe_data; output speed_change; // speed change done to PIPE interface (i.e. auto negotiation done) output rxelecidle_int; // Asserted when Electrical Idle is detected output [4:0] wa_boundary; //describes word boundary // CDR control output early_eios; // Asserted when K_I or K_X_I is detected on the incoming data output ltr; // force CDR to LTR mode // RX PCS CRAMs input rskpsetbased; // Enable rate matching for PCI-E/PIPE-or // other standards based on COMMA DEL DEL.. input rtruebac2bac; // Should be high for all standards // except PIPE. Back to back rate matching enable. input rcmpfifourst; // Enable cmpfifourst input rphfifourstrx; // Enable phfifourst_rx input [2:0] rcomp_size; // Pattern comparision length CRAMs input [39:0] rcomp_pat; // Sync pattern CRAMs input [5:0] rrundisp; // Run lengh violation setting CRAMs input [1:0] rib_inv_cd; // Invalid code setting CRAMs for IB input rrlv_en; // RLV enable CRAM input rsync_sm_dis; // GIGE/XAUI Sync SM disable CRAM input rautobtalg_dis; // BITSLIP mode enable CRAM input rdis_rx_disp; // Receive running disparity calculation disable CRAM input rmatchen; // Clock compensation enable CRAM input rgenericfifo; // GenericFIFO mode enable CRAM input rendec_rx; // 10B/8B decoder enable CRAM input rdwidth_rx; // RX parallel interface data width selection CRAM input rlp20ben; // 20-b loopback enable CRAM input rrxfifo_dis; // RX FIFO bypassing CRAM input rpmadwidth_rx; // RX PMA to RX PCS data width selection CRAM input rpma_doublewidth_rx; // RX PMA/PCS double width (16/20) sel CRAM input [5:0] renumber; // Number of consecutive errors without // valid data to goto LOSS_OF_SYNC input [7:0] rknumber; // Number of consecutive commas to reach // SYNC_ACQ from LOSS_OF_SYNC input renpolinv_rx; // Allow polarity inversion input [7:0] rgnumber; // Number of consecutive good data to approach SYNC_ACQ input rclkcmpsqmd; // How many characters to match input [19:0] rclkcmpsq1p; // Programmable 20-bit encoded comp sequence pos. disp. input [19:0] rclkcmpsq1n; // Programmable 20-bit encoded comp sequence neg. disp. input rclkcmp_pipe_en; // RM PIPE-compatible mode enable input [1:0] rosnumber; // Length of the ordered set input rosbased; // Enable ordered-set based algorithm input rkchar; // use kchar at cg_bad logic calculation input rcascaded_8b10b_en_rx; // Cascaded 8B/10B decoder enable CRAM input [1:0] resync_badcg_en; // input rencdt_rising; // encdt on rising edge enable CRAM input rcomp_pat_porn; // Positive and negative match enable CRAM input rprbsen_rx; // PRBS Verifier enable CRAM input rprbs_clr_rslt_rx; // PRBS pass/fail flag clear CRAM input rbisten_rx; // BIST Verifier enable CRAM input rbist_clr_rx; // BIST pass/fail flag clear CRAM input rwa_6g_en; // 6G word alignment enable CRAM input rbytord_2sym_en; // Enable 2 symbols byte orderring CRAM input rbysync_polinv_en; // Word alignment polarity inversion enable CRAM input rbytord_6g_mask_en; // Mask out upper byte in 6G 2 symbol comparison input rbytord_s2gx; // Byte ordering like s2gx, only once per PCS reset input rbitloc_rev_en; // Bit reversal enable CRAM input rbyte_rev_en; // Byte swap enable CRAM input [1:0] rbyteorden; // Byte ordering enable CRAM input rbytordplden; // PLD control signal BYTEORDPLD enable CRAM input rphfifopldenrx; // RX phase comp. FIFO read/write enable CRAM input rautoinsdis; // Disable CRAM for auto insertion of 8'h9C input [5:0] rppmsel; // Programmable PPM ajustment CRAM input rforce0_freqdet; // Forcing FREQDET signal to low CRAM input rforce1_freqdet; // Forcing FREQDET signal to high CRAM input [19:0] rbytordpat; // Byte ordering pattern CRAM input [9:0] rbytordpad; // Byte ordering pad pattern CRAM input rforce_sig_det_pcs; // Forcing sigdet to high in PCS CRAM input rfreerun_rx; // RX_CLK out free running during RX PCS reset enable CRAM input [1:0] rrcvd_clk_sel; // RCVD_CLK domain selection CRAM input [1:0] rclk_1_sel; // CLK_1 domain selection CRAM input [1:0] rclk_2_sel; // CLK_2 domain selection CRAM input rrx_rd_clk_sel; // RX FIFO read clock selection CRAM input rall_one_dect_only; // PRBS Verifier detect all one only enable CRAM input [3:0] rtest_bus_sel; // Per channel test bus selection CRAMs input [1:0] r8b10b_dec_ibm_en; // 8B10B Decoder fix enable CRAM input rrxfifo_lowlatency_en; // RX FIFO low latency enable CRAM input rppm_cnt_reset; // PPM counter reset CRAM (latched version on Test bus) input sel_gp_md; // Select Quad or Group Mode input rclkcmpinsertpad; // Rate matching pad insertion enable CRAM input [2:0] rstart_threshold; input [4:0] rins_threshold; input [4:0] rdel_threshold; input [4:0] rfull_threshold; input [2:0] rempty_threshold; input rinvalid_code_err_only; input rrx_pipe_enable; input rrxpcsbypass_en; // CRAM for enable low-latency PCS bypass mode input [9:0] rfts_count; // Programmable 4 us (Gen1) of 2 us (Gen2) timer during which CDR control block controls the PPM detector. input rpcs_wrapback_en; // Enables PCS Wrapback mode input rcid_pattern_rx; // CID pattern to be 0 or 1 input [7:0] rcid_len_rx; // Length of CID pattern in cycles input [69:0] pcs_wrapback_in; // Common PCS CRAMs input rindv_rx; // RX SM bypassing CRAM input [1:0] dskwclksel; // Select Deskew Clock input rdskposdisp; // Match the programmed de-skew pattern only input [9:0] rdskchrp; // Programmable Deskew Char. Pos. Disp. input rendec_data_sel_rx; // RX 8B10B decoder data out selection CRAM // Removed old bundling mode MDIOs // input rphfifo_master_sel_rx; // TX Phase comp. FIFO pointers selection CRAM // Common TX RX CRAM for BIST/PRBS input [2:0] rprbs_sel; // PRBS selection CRAM input [1:0] rbist_sel; // BIST selection CRAM input [1:0] rcxpat_chnl_en; // CRPAT or CJPAT selection CRAM // CRAM for auto negotiation module input rauto_speed_ena; input rphfifo_regmode_rx; input rfreq_sel; input [17:0] rpma_done_count; // Programmable counter threshold for pma_done_int (1ms) input riei_eios_priority_dis; // disable EIOS priority over eidle inference input rgen1_sigdet_ena; // enable usage of signal detect under gen1 conditions when eidle // is enabled, eidle inference when gen2 is enabled // CRAM for Eidle Inference input reidleinferenable; // Enable/disable Electrical Idle Inference module input [1:0] reidle_com_detect; // The number of COMs required to enter/exit Eidle // values greater than 2 entails that syncstatus is used // CDR control CRAMS input rcdr_ctrl_en; // Enable/Disable CDR control block input rcid_en; // Enable CID mode (CDR) input rrxvalid_mask; // Enable masking of rxvalid logic input [7:0] rwait_count; // Minimum programmable period of time that LTR is asserted when the CDR control block is enabled. input [9:0] rmask_count; // Masking period of data upon exiting EIdle; for high BER period // new signal inputs for bundling input rx_div2_sync_in_centrl; input rx_div2_sync_in_quad_up; input rx_div2_sync_in_quad_down; input reset_pc_ptrs_in_centrl; input reset_pc_ptrs_in_quad_up; input reset_pc_ptrs_in_quad_down; input wr_enable_in_centrl; input wr_enable_in_quad_up; input wr_enable_in_quad_down; input rd_enable_in_centrl; input rd_enable_in_quad_up; input rd_enable_in_quad_down; input rx_we_in_centrl; input rx_we_in_quad_up; input rx_we_in_quad_down; input speed_change_in_centrl; // pipeline inputs for bundling input rx_div2_sync_in_pipe_quad_up; input rx_div2_sync_in_pipe_quad_down; input reset_pc_ptrs_in_pipe_quad_up; input reset_pc_ptrs_in_pipe_quad_down; input wr_enable_in_pipe_quad_up; input wr_enable_in_pipe_quad_down; input rd_enable_in_pipe_quad_up; input rd_enable_in_pipe_quad_down; input rx_we_in_pipe_quad_up; input rx_we_in_pipe_quad_down; input speed_change_in_pipe_quad_up; input speed_change_in_pipe_quad_down; // Bundle Mode Inputs for config_sel input config_sel_centrl; input config_sel_quad_up; input config_sel_quad_down; // new MDIO inputs for bundling and auto speed input rmaster_rx; input rmaster_up_rx; input rpipeline_bypass_rx; input [3:0] rauto_deassert_pc_rst_cnt; input [4:0] rauto_pc_en_cnt; input rself_sw_en_rx; // S. Park 2/8/08 - New CRAM inputs for PPM Detector input rppm_post_eidle_del; input rppm_gen1_2xcnt_en; // new outputs for bundling and auto speed output rx_div2_sync_out_pipe_up; output rx_we_out_pipe_up; output wr_enable_out_pipe_up; output rd_enable_out_pipe_up; output reset_pc_ptrs_out_pipe_up; output speed_change_out_pipe_up; output rx_div2_sync_out_pipe_down; output rx_we_out_pipe_down; output wr_enable_out_pipe_down; output rd_enable_out_pipe_down; output reset_pc_ptrs_out_pipe_down; output speed_change_out_pipe_down; output dis_pc_byte; output reset_pc_ptrs; // S. Park 3/13/08 - Added for XAUI compliance output cg_comp_rd_d_out; output cg_comp_wr_out; // S. Park 3/21/08 - Added for XAUI compliance output del_cond_met_out; output fifo_ovr_out; output latency_comp_out; output insert_incomplete_out; input [5:0] rwait_for_phfifo_cnt; // PMA rate change control output pcie_switch; // new signals in this module for bundling and auto speed wire clk_2_b_raw; wire rx_wr_clk_raw; wire rx_rd_clk_raw; wire nc_new_bundle1; wire nc_new_bundle2; wire nc_new_bundle3; wire rx_we_out_testbus; wire config_sel_nc; // Wiring Section wire clk_2_b; // to rcv_sm in centrl_macro wire rcvd_clk; // Recovered data clock wire rx_rd_clk; wire [1:0] rx_data_9_rc; // rx data bit 9 from rx_ctrl // when 10-bit code-group is passing // over XGMII wire [1:0] rx_data_19_rc; // rx data bit 19 from rx_ctrl // when 10-bit code-group is passing // over XGMII wire [3:0] rx_control_rc_16; // XGMII rx control from rx_ctrl wire sync_status_st; // Indicate that this lane is // now synchronized wire [31:0] sudi; // Synchronized code group + parity // error status from sync_chnl_top wire [13:0] sudi_pre; // 13-bit data one cycle earlier wire [31:0] cudi; // Clock-compensated code group // + parity // error status from sync_chnl_top wire [15:0] rx_data_dt; // 2 decoded 8-bit rx data wire [1:0] rx_ctl_dt; // 2 decoded rx controls wire [19:0] tenb_data; // rx 20-bit code group bus used when // ENDEC is 1'b0 wire [13:0] audi; // Aligned code group + parity error // status from dskw_top wire [13:0] audi_pre; wire [63:0] rxd; wire [1:0] cg_comma; // comma is detected in sync_chnl_top wire disable_fifo_rd; // disable_fifo_rd from this lane wire disable_fifo_wr; // disable_fifo_wr from this lane wire sync_status; // Indicate that this lane is now // synchronized wire [7:0] dec_data; // decoded 8-bit rx data wire dec_ctl; // decoded rx control wire [1:0] running_disp; // indicate that dec_data/dec_ctl // is either not valid or having // disparity error wire [1:0] invalid_code_delay; // indicate that dec_data/dec_ctl is // having diparity error wire selftest_done; // Status shows that the self test // checking is done wire selftest_err; // Status shows that the selftest is // successful wire [15:0] err_data; // When the self test fails, this // records the first byte that error // occurs to. wire [1:0] err_ctl; // When the self test fails, this // records the first byte that error // occurs to. wire prbs_done; // Indicate that prbs verification is // done wire prbs_err_lt; // Indicate that prbs verification is // OK - latched version, cleared when // ENBIST is cleared. wire prbs_err; wire signal_detect_out; // signal_detect to status pin/bit for // PMA-only operation wire signal_detect; wire [1:0] disp_err_delay; wire [1:0] disp_val_delay; wire [1:0] sync_resync_delay; wire dec_data_valid; wire high_dec_data_valid; wire soft_reset_int; wire cudi_valid; wire encdet_prbs; wire [3:0] ovr_undflow; // Signals over or underflow // Merged to save bit in the synchronous // datapath wire clk_1_b; wire [19:0] rev_loop_data; // 10 bit data from RX rate matching // FIFO, reverse loopback wire [39:0] rxd_lpbk; wire rx_wr_clk; wire fref_muxed, clklow_muxed; wire skposdetect; wire [3:0] ausm_cs; // Wire for test bus wire prbs_verify_on; wire [9:0] word_align_testbus; wire [4:0] bist_cur_state; wire wr_enable2; wire rd_enable2; wire [2:0] wptr_bin; wire [2:0] rptr_bin; wire [4:0] comp_fifo_cnt; wire [7:0] ppm_cnt; wire [1:0] comp_curr_st; wire [9:0] kcount; wire [17:0] rpma_done_count; //shawn: unused wire to fix open connections () wire [19:0] rev_loop_data_enc; // unused from encoder wire signal_detect_rcvdclk_dummy; //shawn: implicit declaration wire rst1; // S. Park 3/13/08 - New wires added for connectivity to comp_chnl_top wire cg_comp_rd_d_ch0; wire cg_comp_rd_d_ch1; wire cg_comp_rd_d_ch2; wire cg_comp_rd_d_ch3; wire cg_comp_wr_ch0; wire cg_comp_wr_ch1; wire cg_comp_wr_ch2; wire cg_comp_wr_ch3; wire cg_comp_rd_d_out; wire cg_comp_wr_out; // S. Park 3/21/08 - Added wires for XAUI compliance wire del_cond_met_out; wire fifo_ovr_out; wire latency_comp_out; wire insert_incomplete_out; assign dec_data = rx_data_dt[7:0]; assign dec_ctl = rx_ctl_dt[0]; assign sync_status = sync_status_st; assign signal_detect = sigdetni; //assign soft_reset_int = (scan_mode) ? 1'b0 : rxpcs_rst ; assign soft_reset_int = rxpcs_rst ; // WA wire [9:0] adata; wire adata_valid; wire kchar; // CDR control block wire eiosdetect_int; wire inferred_rxvalid; wire eidle_exit; wire [1 :0] dec_data_valid_temp; //shawn - VHDL translation // S. Park 2/8/08 - New wires for new PPM Detector CRAMs wire rppm_post_eidle_del; wire rppm_gen1_2xcnt_en; // RX PIPE interface clock //assign rx_pipe_clk = rx_rd_clk; assign rx_pipe_clk = rx_wr_clk; // Clock selection module stratixiv_hssi_rx_digi_rxclk_ctl rxclk_ctl_1 ( .pld_rx_clk(pld_rx_clk), .rcvd_clk_pma(rcvd_clk_pma), .rcvd_clk0_pma(rcvd_clk0_pma), .tx_pma_clk(tx_pma_clk), .refclk_pma(refclk_pma), .fref(fref), .clklow(clklow), .scan_mode(scan_mode), .gen2ngen1(gen2ngen1), .gen2ngen1_bundle(gen2ngen1_bundle), .rx_div2_sync_centrl(rx_div2_sync_in_centrl), .rx_div2_sync_quad_up(rx_div2_sync_in_quad_up), .rx_div2_sync_quad_down(rx_div2_sync_in_quad_down), .rrcvd_clk_sel(rrcvd_clk_sel), .rclk_1_sel(rclk_1_sel), .rclk_2_sel(rclk_2_sel), .rrx_rd_clk_sel(rrx_rd_clk_sel), .rxrst(rxpcs_rst), .rindv_rx(rindv_rx), .rdwidth_rx(rdwidth_rx), .rfreerun_rx(rfreerun_rx), .rauto_speed_ena(rauto_speed_ena), .rfreq_sel(rfreq_sel), .rrxpcsclkpwdn(rrxpcsclkpwdn), .rmaster_rx(rmaster_rx), .rmaster_up_rx(rmaster_up_rx), .rself_sw_en_rx(rself_sw_en_rx), .fref_muxed(fref_muxed), .clklow_muxed(clklow_muxed), .rcvd_clk(rcvd_clk), .clk_1_b(clk_1_b), .clk_2_b(clk_2_b), .rx_wr_clk(rx_wr_clk), .rx_rd_clk(rx_rd_clk), .rx_clk(rx_clk), .rcvd_clk_pma_b(rcvd_clk_pma_b), .clk_2_b_raw(clk_2_b_raw), .rx_wr_clk_raw(rx_wr_clk_raw), .rx_rd_clk_raw(rx_rd_clk_raw), .rx_div2_sync_out(nc_new_bundle1) ); // Word alignment module stratixiv_hssi_rx_digi_wordalign wordalign_1 ( .rst(soft_reset_int), .clk(rcvd_clk), .scan_mode(scan_mode), .wa_6g_en(rwa_6g_en), .signal_detect(signal_detect), .rforce_sig_det_pcs(rforce_sig_det_pcs), .lpbk_en(rlp20ben), .pmadwidth({rpma_doublewidth_rx,rpmadwidth_rx}), .dwidth(rdwidth_rx), .gen2ngen1(gen2ngen1), .gen2ngen1_bundle(gen2ngen1_bundle), .rauto_speed_ena(rauto_speed_ena), .rfreq_sel(rfreq_sel), .rindv_rx(rindv_rx), .pudi(pudi), .pudr(txlp20b), .rencdt_rising(rencdt_rising), .encdt(encdt), .comp_pat_porn(rcomp_pat_porn), .comp_pat(rcomp_pat), .comp_pat_size(rcomp_size), .resync_badcg_en(resync_badcg_en), .r8b10b_dec_ibm_en(r8b10b_dec_ibm_en), .autobytealign_dis(rautobtalg_dis), .bitslip(bitslip), .rlv_en(rrlv_en), .max_rlv_sel(rrundisp), .disable_rx_disp(rdis_rx_disp), .ib_invalid_code(rib_inv_cd), .rpolinv_en(rbysync_polinv_en), .rbitloc_rev_en(rbitloc_rev_en), .rbyte_rev_en(rbyte_rev_en), .polinv_en(polinv_rx), .bitloc_rev_en(bitloc_rev_en), .byte_rev_en(byte_rev_en), .sync_sm_dis(rsync_sm_dis), .prbs_en(rprbsen_rx), .encdet_prbs(encdet_prbs), .a1a2_size(a1a2_size), .knumber({2'b00,rknumber}), .gnumber({2'b00,rgnumber}), .enumber({4'b0000,renumber}), .rosnumber({2'b00,rosnumber}), .rosbased(rosbased), .rkchar(rkchar), .kchar(kchar), .signal_detect_rcvdclk(signal_detect_rcvdclk_dummy), .sudi(sudi), .sync_status(sync_status_st), .cg_syncpat(cg_comma), .rlv(rlv), .rlv_lt(rlv_lt), .a1a2_k1k2_flag(a1a2_k1k2_flag), .sudi_pre(sudi_pre), .testbus(word_align_testbus), .kcount(kcount), //new brought out from PIPE sync SM .rrxpcsbypass_en(rrxpcsbypass_en), .adata (adata), // CDR control .adata_valid(adata_valid), .rst1(rst1), .pipe_loose_sync(pcs_wrapback_in[60]), //07/02/2008 by K.Kankipa ECO to bring down sync_status by glue logic in PLD when sync_status does not go lwo because of PMA being stukc at 1010101010101 .wa_boundary(wa_boundary) ); // De-skew FIFO module stratixiv_hssi_rx_digi_dskw_fifo dskw_fifo_1 ( .rcvd_clk (rcvd_clk), // 01/07/05 VC: Increased bus width from 13 to 14 // .sudi (sudi[12:0]), .sudi (sudi[13:0]), .soft_reset (soft_reset_int), .fifo_rst_rd_qd (fifo_rst_rd_qd), .fifo_rst_rd_gp (fifo_rst_rd_gp), .clk_1 (clk_1_b), .en_dskw_qd (en_dskw_qd), .en_dskw_gp (en_dskw_gp), .sel_gp_md (sel_gp_md), .rdskposdisp (rdskposdisp), .rdskchrp (rdskchrp), .align_det_sync (align_det_sync), .rd_align (rd_align), .audi (audi), .audi_pre (audi_pre) ); // PRBS verifier module stratixiv_hssi_rx_digi_prbs_ver prbs_ver_1 ( .rcvd_clk(rcvd_clk), .soft_reset(soft_reset_int), .scan_mode(scan_mode), .rprbs_clr_rslt_rx(rprbs_clr_rslt_rx), .rprbs_en_rx(rprbsen_rx), .rpmadwidth_rx(rpmadwidth_rx), .rpma_doublewidth_rx(rpma_doublewidth_rx), .rprbs_sel(rprbs_sel), .rall_one_dect_only(rall_one_dect_only), .verify_on(prbs_verify_on), .cid_en(prbs_cid_en), .rcid_len(rcid_len_rx), .rcid_pattern(rcid_pattern_rx), .sync_status(sudi[11]), .data_in({sudi[25:16],sudi[9:0]}), .prbs_done(prbs_done), .prbs_err(prbs_err), .encdet_prbs(encdet_prbs), .prbs_err_lt(prbs_err_lt) ); // Rate matching module stratixiv_hssi_rx_digi_comp_chnl_top comp_chnl_top_1 ( .hard_reset (hard_reset), .soft_reset (soft_reset_int), .cmpfifourst (cmpfifourst), .rcmpfifourst (rcmpfifourst), .scan_mode(scan_mode), .clk_1 (clk_1_b), .clk_2 (clk_2_b), // 01/07/05 VC: Increased bus width from 26 to 28 // to pass running disparity polarity bits // .sudi ({sudi[28:16], sudi[12:0]}), .sudi ({sudi[29:16], sudi[13:0]}), .sudi_pre (sudi_pre), .audi (audi), .audi_pre (audi_pre), .align_status (align_status), .align_status_sync_0 (align_status_sync_0), .align_status_sync_2 (align_status_sync_2), .sync_status (sync_status_st), .inferred_rxvalid(inferred_rxvalid), // S. Park 3/21/08 - Removed below two ports // .disable_fifo_rd_0 (disable_fifo_rd_0), // .disable_fifo_wr_0 (disable_fifo_wr_0), .is_lane0 (is_lane0), .rdfifo_almost_full (almost_fl_rmf), .rdfifo_full (full_rmf), .rdfifo_almost_empty (almost_mt_rmf), .rdfifo_empty (empty_rmf), .dskwclksel (dskwclksel), .rmatchen (rmatchen), .rwa_6g_en(rwa_6g_en), .rgenericfifo (rgenericfifo), .rdenable (rdenable_rmf), .wrenable (wrenable_rmf), .fifo_rd_in_comp_0 (fifo_rd_in_comp_0), .fifo_rd_in_comp_2 (fifo_rd_in_comp_2), .rskpsetbased (rskpsetbased), .rtruebac2bac (rtruebac2bac), .rclkcmpsqmd (rclkcmpsqmd), .rclkcmpsq1p (rclkcmpsq1p), .rclkcmpsq1n (rclkcmpsq1n), .rclkcmpinsertpad(rclkcmpinsertpad), .rrx_pipe_enable(rclkcmp_pipe_en), .rdwidth_rx(rdwidth_rx), .gen2ngen1(gen2ngen1), .gen2ngen1_bundle(gen2ngen1_bundle), .rauto_speed_ena(rauto_speed_ena), .rfreq_sel(rfreq_sel), .rindv_rx(rindv_rx), .fifo_rd_out_comp(fifo_rd_out_comp), // S. Park 3/21/08 - Removed below two ports // .disable_fifo_rd (disable_fifo_rd), // .disable_fifo_wr (disable_fifo_wr), .align_status_sync (align_status_sync), .cudi (cudi), .rev_loop_data (rev_loop_data_enc), .comp_curr_st (comp_curr_st), .cudi_valid (cudi_valid), .fifo_cnt(comp_fifo_cnt), .rstart_threshold(rstart_threshold), .rins_threshold(rins_threshold), .rdel_threshold(rdel_threshold), .rfull_threshold(rfull_threshold), .rempty_threshold(rempty_threshold), //Eidle Infer .skpos_det(skposdetect), // S. Park 3/13/08 - Added new ports for XAUI compliance .cg_comp_rd_d_ch0 (cg_comp_rd_d_ch0), .cg_comp_rd_d_ch1 (cg_comp_rd_d_ch1), .cg_comp_rd_d_ch2 (cg_comp_rd_d_ch2), .cg_comp_rd_d_ch3 (cg_comp_rd_d_ch3), .cg_comp_wr_ch0 (cg_comp_wr_ch0), .cg_comp_wr_ch1 (cg_comp_wr_ch1), .cg_comp_wr_ch2 (cg_comp_wr_ch2), .cg_comp_wr_ch3 (cg_comp_wr_ch3), .cg_comp_rd_d_out (cg_comp_rd_d_out), .cg_comp_wr_out (cg_comp_wr_out), // S. Park 3/21/08 - Added new ports for XAUI compliance .del_cond_met_0 (del_cond_met_0), .fifo_ovr_0 (fifo_ovr_0), .latency_comp_0 (latency_comp_0), .insert_incomplete_0 (insert_incomplete_0), .del_cond_met_out (del_cond_met_out), .fifo_ovr_out (fifo_ovr_out), .latency_comp_out (latency_comp_out), .insert_incomplete_out (insert_incomplete_out) ); // 10B-8B Decoder module stratixiv_hssi_rx_digi_dec_chnl_top dec_chnl_top_1 ( .rst(soft_reset_int), .clk_2(clk_2_b), .cascaded_8b10b_en(rcascaded_8b10b_en_rx), .r8b10b_dec_ibm_en(r8b10b_dec_ibm_en), // 01/07/05 VC: Increased bus width of cudi from 30 to 32 // to pass running disp polarity bit // .data_in({cudi[29:28],1'b0,cudi[27:15], // cudi[14:13],1'b0,cudi[12:0]}), .data_in(cudi), .data_in_valid({cudi_valid,cudi_valid}), .renpolinv(renpolinv_rx), .rerr_flags_sel(rerr_flags_sel), .polinv(polinv_rx), .dec_data(rx_data_dt), .disp_err_delay(disp_err_delay), .disp_val_delay(disp_val_delay), .sync_resync_delay(sync_resync_delay), .dec_data_valid(dec_data_valid_temp), .dec_ctl(rx_ctl_dt), .invalid_code_delay(invalid_code_delay), .ovr_undflow(ovr_undflow), .tenb_data(tenb_data), .rlb_data(rev_loop_data), .rrxpcsbypass_en(rrxpcsbypass_en) ); assign high_dec_data_valid = dec_data_valid_temp[1]; assign dec_data_valid = dec_data_valid_temp[0]; // BIST Verifier module stratixiv_hssi_rx_digi_bist_ver selftest_ver_1 ( .clk_2(rx_rd_clk), .soft_reset(soft_reset_rclk1), .sync_status(sync_status_st), .rbisten_rx(rbisten_rx), .rpmadwidth_rx(rpmadwidth_rx), .rpma_doublewidth_rx(rpma_doublewidth_rx), .rdwidth_rx(rdwidth_rx), .rbist_sel(rbist_sel), .rcxpat_chnl_sel(rcxpat_chnl_en), .rbist_clr_rx(rbist_clr_rx), .rxd(rxd), .rxc(rx_control_rc_16), .prbs_done(prbs_done), .prbs_err(prbs_err), .cur_state(bist_cur_state), .selftest_err(selftest_err), .selftest_done(selftest_done), .bisterr(bisterr), .bistdone(bistdone), .err_data(err_data), .err_ctl(err_ctl) ); // RX Phase compensation FIFO module stratixiv_hssi_rx_digi_rx_ctrl rx_ctrl_1 ( .soft_reset (soft_reset_int), .clk_2 (clk_2_b), .rx_wr_clk(rx_wr_clk), .rx_rd_clk (rx_rd_clk), .scan_mode(scan_mode), // S. Park 11/29/07 - Phase FIFO bypass feature removed // .rrxfifo_dis (rrxfifo_dis), .rrxfifo_dis (1'b0), .rindv_rx (rindv_rx), .rendec_data_sel_rx (rendec_data_sel_rx), .rwa_6g_en(rwa_6g_en), .rrxfifo_lowlatency_en(rrxfifo_lowlatency_en), .endec_rx (rendec_rx), .rinvalid_code_err_only (rinvalid_code_err_only), .rrx_pipe_enable(rrx_pipe_enable), .rpmadatawidth (rpmadwidth_rx), .rdwidth (rdwidth_rx), .rautoinsdis(rautoinsdis), .rbytorden(rbyteorden), .rbytord_2sym_en(rbytord_2sym_en), .rbytordpat(rbytordpat), .rbytordpadval(rbytordpad), .rbytordplden(rbytordplden), .bytordplden(bytordpld), .rbytord_6g_mask_en(rbytord_6g_mask_en), .rbytord_s2gx(rbytord_s2gx), .rsync_comp_size (rcomp_size), .rsync_comp_pat (rcomp_pat), .rsync_comp_porn(rcomp_pat_porn), .rsync_sm_dis (rsync_sm_dis), .rclkcmpinsertpad(rclkcmpinsertpad), .invalid_code_delay (invalid_code_delay), .sigdetni (sigdetni), .dec_data_valid_pre({cudi_valid,cudi_valid}), .dec_data_valid ({high_dec_data_valid, dec_data_valid}), .rx_data_rs (rx_data_rs), .rx_control_rs (rx_control_rs), .rx_data_dt (rx_data_dt), .rx_control_dt (rx_ctl_dt), .tenb_data (tenb_data), .sync_resync_pre({cudi[27],cudi[11]}), .sync_resync_delay (sync_resync_delay), .disp_err_delay (disp_err_delay), .disp_val_delay(disp_val_delay), .ovr_undflow (ovr_undflow), .rrxfifo_urst_en (rphfifourstrx), .rxfifo_urst (phfifourst_rx), .rrxphfifopldctl_en(rphfifopldenrx), .pld_wr_dis(wrdisable_rx), .pld_re(rdenable_rx), // PIPE signals .phystatus_int (phystatus_int), .rxvalid_int(rxvalid_int), .rxstatus_int(rxstatus_int), .powerdown(powerdown), .rxd (rxd), .rxd_9 (rx_data_9_rc), .rxd_19 (rx_data_19_rc), .rxc (rx_control_rc_16), .running_disp (running_disp), .signal_detect_out (signal_detect_out), .rxd_lpbk (rxd_lpbk), .ph_fifo_empty(empty_rx), .ph_fifo_full(full_rx), .wr_enable_out(nc_new_bundle2), .rd_enable_out(nc_new_bundle3), .rx_we_out (rx_we_out_testbus), .bytord_valid_out(byteord_flag), .soft_reset_rclk1(soft_reset_rclk1), .soft_reset_wclk1(rx_pipe_soft_reset), // PIPE signals .phystatus(phystatus), .rxvalid(rxvalid), .rxstatus(rxstatus), .pipe_data(pipe_data), .wr_enable2(wr_enable2), .wptr_bin(wptr_bin), .rd_enable2(rd_enable2), .rptr_bin(rptr_bin), .rrxpcsbypass_en(rrxpcsbypass_en), .reset_pc_ptrs(reset_pc_ptrs), .reset_pc_ptrs_centrl(reset_pc_ptrs_in_centrl), .reset_pc_ptrs_quad_up(reset_pc_ptrs_in_quad_up), .reset_pc_ptrs_quad_down(reset_pc_ptrs_in_quad_down), .gen2ngen1(gen2ngen1), .gen2ngen1_bundle(gen2ngen1_bundle), .dis_pc_byte(dis_pc_byte), .wr_enable_centrl(wr_enable_in_centrl), .wr_enable_quad_up(wr_enable_in_quad_up), .wr_enable_quad_down(wr_enable_in_quad_down), .rd_enable_centrl(rd_enable_in_centrl), .rd_enable_quad_up(rd_enable_in_quad_up), .rd_enable_quad_down(rd_enable_in_quad_down), .rx_we_in_centrl(rx_we_in_centrl), .rx_we_in_quad_up(rx_we_in_quad_up), .rx_we_in_quad_down(rx_we_in_quad_down), // New MDIO for new bundling scheme and new PCIE features like autospeed .rauto_speed_ena(rauto_speed_ena), .rfreq_sel(rfreq_sel), .rphfifo_regmode_rx(rphfifo_regmode_rx), .rmaster_rx(rmaster_rx), .rmaster_up_rx(rmaster_up_rx), .pcs_wrapback_in(pcs_wrapback_in), .rpcs_wrapback_en(rpcs_wrapback_en) ); // PCS channel test bus stratixiv_hssi_rx_digi_pcs_channel_testbus pcs_channel_testbus_1 ( .test_bus_in0({bistdone,bisterr,bist_cur_state, prbs_verify_on,encdet_prbs, prbs_err_lt}), .test_bus_in1(word_align_testbus), .test_bus_in2(encoder_testbus), .test_bus_in3(tx_ctrl_testbus), .test_bus_in4({1'b0,rx_we_out_testbus, wr_enable2,wptr_bin,rd_enable2, rptr_bin}), .test_bus_in5({2'b00,skposdetect,comp_curr_st, comp_fifo_cnt}), .test_bus_in6({1'b0,freq_lock,ppm_cnt}), .test_bus_in7({2'b00,pma_testbus}), .test_bus_in10({ausm_cs, reset_pc_ptrs, dis_pc_byte, speed_change, pcie_switch, gen2ngen1, rate}), .test_bus_in11({5'b00000,inferred_rxvalid, ltr, eidle_exit,early_eios, eiosdetect_int}), .test_bus_in13({tx_rd_enable_out_pipe_up, tx_wr_enable_out_pipe_up, fifo_select_out_pipe_up, tx_div2_sync_out_pipe_up, reset_pc_ptrs_out_pipe_up, speed_change_out_pipe_up, rd_enable_out_pipe_up, wr_enable_out_pipe_up, rx_we_out_pipe_up, rx_div2_sync_out_pipe_up}), .test_bus_in14({tx_rd_enable_out_pipe_down, tx_wr_enable_out_pipe_down, fifo_select_out_pipe_down, tx_div2_sync_out_pipe_down, reset_pc_ptrs_out_pipe_down, speed_change_out_pipe_down, rd_enable_out_pipe_down, wr_enable_out_pipe_down, rx_we_out_pipe_down, rx_div2_sync_out_pipe_down}), .rtest_bus_sel(rtest_bus_sel), .chnl_test_bus_out(chnl_test_bus_out) ); // Frequency detector module stratixiv_hssi_rx_digi_freqdet freq_det_1 (.scan_mode(scan_mode), .ppmsel (rppmsel), .fref(fref_muxed), .fvcobyn (clklow_muxed), .pd (1'b0), .rforcehigh(rforce1_freqdet), .rforcelow(rforce0_freqdet), .hard_reset(rxpma_rst), .ppm_cnt_reset(rppm_cnt_reset), .gen2ngen1_indv(gen2ngen1), .gen2ngen1_bundle(gen2ngen1_bundle), .rindv_rx(rindv_rx), .rauto_speed_ena(rauto_speed_ena), .rppm_gen1_2xcnt_en(rppm_gen1_2xcnt_en), .eidle_exit(eidle_exit), .rppm_post_eidle_del(rppm_post_eidle_del), .freq_lock(freq_lock), .ppm_cnt_latch(ppm_cnt) ); // Auto negotiation module stratixiv_hssi_rx_digi_auto_speed_neg auto_speed_neg_1 ( .refclk(clk_2_b), .rxpcs_rst_int(soft_reset_int), .rauto_speed_ena(rauto_speed_ena), .singleorbundle(rindv_rx), .config_sel_centrl(config_sel_centrl), .config_sel_quad_up(config_sel_quad_up), .config_sel_quad_down(config_sel_quad_down), .rindv_rx(rindv_rx), .rmaster_rx(rmaster_rx), .rmaster_up_rx(rmaster_up_rx), .rphfifo_regmode_rx(rphfifo_regmode_rx), .rate(rate), .cs(ausm_cs), .gen2ngen1(gen2ngen1), //from PMA .speed_change(speed_change), //to RX PIPE, phystatus gen. .rpma_done_count(rpma_done_count), .rauto_deassert_pc_rst_cnt(rauto_deassert_pc_rst_cnt), .rauto_pc_en_cnt(rauto_pc_en_cnt), .rwait_for_phfifo_cnt(rwait_for_phfifo_cnt), .config_sel(config_sel_nc), .pcie_switch(pcie_switch), .dis_pc_byte(dis_pc_byte), .reset_pc_ptrs(reset_pc_ptrs) ); stratixiv_hssi_rx_digi_eii_module electrical_idle_inference_module_1 ( .rcvd_clk(rcvd_clk), .rxpcsrst(rst1), // synchronized reset in rcvd_clk domain from wordalign block .reidleinferenable(reidleinferenable), .reidle_com_detect(reidle_com_detect), .rindv_rx(rindv_rx), .riei_eios_priority_dis(riei_eios_priority_dis), .rgen1_sigdet_ena (rgen1_sigdet_ena), .eidleinfersel(eidleinfersel), // .skposdetect(skposdetect), .syncstatus(sync_status_st), .sudi(sudi[15:0]), .kflag(kchar), .kcount(kcount[1:0]), //new brought out from PIPE sync SM .eiosdetect_int(eiosdetect_int), //CDR control .inferred_rxvalid(inferred_rxvalid), .signaldetect(sigdetni), .gen2ngen1(gen2ngen1), .gen2ngen1_bundle(gen2ngen1_bundle), .pipe_loopbk(pipe_loopbk), .rwait_count(rwait_count), .rxelecidle_int(rxelecidle_int) ); stratixiv_hssi_rx_digi_cdr_ctrl cdr_ctrl_1( // General signals .rcvd_clk (rcvd_clk), .rxpcs_reset_int (rst1), // synchronized reset in rcvd_clk domain from wordalign block // CRAM .rcdr_ctrl_en (rcdr_ctrl_en), .rcid_en (rcid_en), .rrxvalid_mask (rrxvalid_mask), .rwait_count (rwait_count), .rmask_count (rmask_count[9:0]), .rindv_rx (rindv_rx), // PLD interface .pld_ltr (pld_ltr), .pipe_loopbk (pipe_loopbk), // Word aligner .adata (adata), .adata_valid (adata_valid), .inferred_rxvalid (inferred_rxvalid), // EIdle Inference .eiosdetect_int (eiosdetect_int), // Auto Speed .gen2ngen1 (gen2ngen1), .gen2ngen1_bundle (gen2ngen1_bundle), // PPM detector .eidle_exit (eidle_exit), // PMA .sigdet (sigdetni), .early_eios (early_eios), .ltr (ltr) ); stratixiv_hssi_rx_digi_iq_pipe_rx iqp_out_up( .clk_2_b_raw(clk_2_b_raw), .rx_wr_clk_raw(rx_wr_clk_raw), .rx_rd_clk_raw(rx_rd_clk_raw), .rxrst(rxpcs_rst), .soft_reset_rclk1(soft_reset_rclk1), .soft_reset_wclk1(rx_pipe_soft_reset), .rmaster_rx(rmaster_rx), .rmaster_up_rx(rmaster_up_rx), .rpipeline_bypass_rx(rpipeline_bypass_rx), .rfreerun_rx(rfreerun_rx), .rx_div2_sync_in_centrl(rx_div2_sync_in_centrl), .rx_div2_sync_in_pipe_quad_up(1'b0), .rx_div2_sync_in_pipe_quad_down(rx_div2_sync_in_pipe_quad_down), .reset_pc_ptrs_in_centrl(reset_pc_ptrs_in_centrl), .reset_pc_ptrs_in_pipe_quad_up(1'b0), .reset_pc_ptrs_in_pipe_quad_down(reset_pc_ptrs_in_pipe_quad_down), .wr_enable_in_centrl(wr_enable_in_centrl), .wr_enable_in_pipe_quad_up(1'b0), .wr_enable_in_pipe_quad_down(wr_enable_in_pipe_quad_down), .rd_enable_in_centrl(rd_enable_in_centrl), .rd_enable_in_pipe_quad_up(1'b0), .rd_enable_in_pipe_quad_down(rd_enable_in_pipe_quad_down), .rx_we_in_centrl(rx_we_in_centrl), .rx_we_in_pipe_quad_up(1'b0), .rx_we_in_pipe_quad_down(rx_we_in_pipe_quad_down), .speed_change_in_centrl(speed_change_in_centrl), .speed_change_in_pipe_quad_up(1'b0), .speed_change_in_pipe_quad_down(speed_change_in_pipe_quad_down), .rx_div2_sync_out_pipe(rx_div2_sync_out_pipe_up), .rx_we_out_pipe(rx_we_out_pipe_up), .wr_enable_out_pipe(wr_enable_out_pipe_up), .rd_enable_out_pipe(rd_enable_out_pipe_up), .reset_pc_ptrs_out_pipe(reset_pc_ptrs_out_pipe_up), .speed_change_out_pipe(speed_change_out_pipe_up) ); stratixiv_hssi_rx_digi_iq_pipe_rx iqp_out_down( .clk_2_b_raw(clk_2_b_raw), .rx_wr_clk_raw(rx_wr_clk_raw), .rx_rd_clk_raw(rx_rd_clk_raw), .rxrst(rxpcs_rst), .soft_reset_rclk1(soft_reset_rclk1), .soft_reset_wclk1(rx_pipe_soft_reset), .rmaster_rx(rmaster_rx), .rmaster_up_rx(rmaster_up_rx), .rpipeline_bypass_rx(rpipeline_bypass_rx), .rfreerun_rx(rfreerun_rx), .rx_div2_sync_in_centrl(rx_div2_sync_in_centrl), .rx_div2_sync_in_pipe_quad_up(rx_div2_sync_in_pipe_quad_up), .rx_div2_sync_in_pipe_quad_down(1'b0), .reset_pc_ptrs_in_centrl(reset_pc_ptrs_in_centrl), .reset_pc_ptrs_in_pipe_quad_up(reset_pc_ptrs_in_pipe_quad_up), .reset_pc_ptrs_in_pipe_quad_down(1'b0), .wr_enable_in_centrl(wr_enable_in_centrl), .wr_enable_in_pipe_quad_up(wr_enable_in_pipe_quad_up), .wr_enable_in_pipe_quad_down(1'b0), .rd_enable_in_centrl(rd_enable_in_centrl), .rd_enable_in_pipe_quad_up(rd_enable_in_pipe_quad_up), .rd_enable_in_pipe_quad_down(1'b0), .rx_we_in_centrl(rx_we_in_centrl), .rx_we_in_pipe_quad_up(rx_we_in_pipe_quad_up), .rx_we_in_pipe_quad_down(1'b0), .speed_change_in_centrl(speed_change_in_centrl), .speed_change_in_pipe_quad_up(speed_change_in_pipe_quad_up), .speed_change_in_pipe_quad_down(1'b0), .rx_div2_sync_out_pipe(rx_div2_sync_out_pipe_down), .rx_we_out_pipe(rx_we_out_pipe_down), .wr_enable_out_pipe(wr_enable_out_pipe_down), .rd_enable_out_pipe(rd_enable_out_pipe_down), .reset_pc_ptrs_out_pipe(reset_pc_ptrs_out_pipe_down), .speed_change_out_pipe(speed_change_out_pipe_down) ); endmodule // digi_rx //////////////////////////////////////////////////////////////////////////////// // hssi_module: receiver *****************************************************// //////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////// // DPRIO INDEX TABLE --------------------------------------------------------// /////////////////////////////////////////////////////////////////////////////// // Table5: PCS Per Channel RX Control Register 1 for Channel 0 `define rrxpcsbypass_en_RXPCS_IDX_0 0 `define rall_one_dect_only_RXPCS_IDX_0 1 `define rbist_clr_rx_RXPCS_IDX_0 2 `define rbisten_rx_RXPCS_IDX_0 3 `define rprbs_clr_rslt_rx_RXPCS_IDX_0 4 `define rprbsen_rx_RXPCS_IDX_0 5 `define rrx_rd_clk_sel_RXPCS_IDX_0 6 `define rclk_2_sel_RXPCS_IDX_0 7 `define rclk_2_sel_RXPCS_IDX_1 8 `define rclk_1_sel_RXPCS_IDX_0 9 `define rclk_1_sel_RXPCS_IDX_1 10 `define rrcvd_clk_sel_RXPCS_IDX_0 11 `define rrcvd_clk_sel_RXPCS_IDX_1 12 `define rfreerun_rx_RXPCS_IDX_0 13 `define rrxurstpcs_RXPCS_IDX_0 14 `define reserved_0_TB5_RXPCS_IDX_0 15 // Table6: PCS Per Channel RX Control Register 2 for Channel 0 `define rcomp_pat_32_RXPCS_IDX_0 16 `define rcomp_pat_33_RXPCS_IDX_0 17 `define rcomp_pat_34_RXPCS_IDX_0 18 `define rcomp_pat_35_RXPCS_IDX_0 19 `define rcomp_pat_36_RXPCS_IDX_0 20 `define rcomp_pat_37_RXPCS_IDX_0 21 `define rcomp_pat_38_RXPCS_IDX_0 22 `define rcomp_pat_39_RXPCS_IDX_0 23 `define rcomp_size_RXPCS_IDX_0 24 `define rcomp_size_RXPCS_IDX_1 25 `define rcomp_size_RXPCS_IDX_2 26 `define rcomp_pat_porn_RXPCS_IDX_0 27 `define rdis_rx_disp_RXPCS_IDX_0 28 `define rencdt_rising_RXPCS_IDX_0 29 `define resync_badcg_en_RXPCS_IDX_0 30 `define resync_badcg_en_RXPCS_IDX_1 31 // Table7: PCS Per Channel RX Control Register 3 for Channel 0 `define rcomp_pat_16_RXPCS_IDX_0 32 `define rcomp_pat_17_RXPCS_IDX_0 33 `define rcomp_pat_18_RXPCS_IDX_0 34 `define rcomp_pat_19_RXPCS_IDX_0 35 `define rcomp_pat_20_RXPCS_IDX_0 36 `define rcomp_pat_21_RXPCS_IDX_0 37 `define rcomp_pat_22_RXPCS_IDX_0 38 `define rcomp_pat_23_RXPCS_IDX_0 39 `define rcomp_pat_24_RXPCS_IDX_0 40 `define rcomp_pat_25_RXPCS_IDX_0 41 `define rcomp_pat_26_RXPCS_IDX_0 42 `define rcomp_pat_27_RXPCS_IDX_0 43 `define rcomp_pat_28_RXPCS_IDX_0 44 `define rcomp_pat_29_RXPCS_IDX_0 45 `define rcomp_pat_30_RXPCS_IDX_0 46 `define rcomp_pat_31_RXPCS_IDX_0 47 // Table8: PCS Per Channel RX Control Register 4 for Channel 0 `define rcomp_pat_0_RXPCS_IDX_0 48 `define rcomp_pat_1_RXPCS_IDX_0 49 `define rcomp_pat_2_RXPCS_IDX_0 50 `define rcomp_pat_3_RXPCS_IDX_0 51 `define rcomp_pat_4_RXPCS_IDX_0 52 `define rcomp_pat_5_RXPCS_IDX_0 53 `define rcomp_pat_6_RXPCS_IDX_0 54 `define rcomp_pat_7_RXPCS_IDX_0 55 `define rcomp_pat_8_RXPCS_IDX_0 56 `define rcomp_pat_9_RXPCS_IDX_0 57 `define rcomp_pat_10_RXPCS_IDX_0 58 `define rcomp_pat_11_RXPCS_IDX_0 59 `define rcomp_pat_12_RXPCS_IDX_0 60 `define rcomp_pat_13_RXPCS_IDX_0 61 `define rcomp_pat_14_RXPCS_IDX_0 62 `define rcomp_pat_15_RXPCS_IDX_0 63 // Table9: PCS Per Channel RX Control Register 5 for Channel 0 `define rbitloc_rev_en_RXPCS_IDX_0 64 `define rbysync_polinv_en_RXPCS_IDX_0 65 `define rwa_6g_en_RXPCS_IDX_0 66 `define rosnumber_RXPCS_IDX_0 67 `define rosnumber_RXPCS_IDX_1 68 `define rosbased_RXPCS_IDX_0 69 `define rkchar_RXPCS_IDX_0 70 `define renumber_RXPCS_IDX_0 71 `define renumber_RXPCS_IDX_1 72 `define renumber_RXPCS_IDX_2 73 `define renumber_RXPCS_IDX_3 74 `define renumber_RXPCS_IDX_4 75 `define renumber_RXPCS_IDX_5 76 `define rib_inv_cd_RXPCS_IDX_0 77 `define rib_inv_cd_RXPCS_IDX_1 78 `define rsync_sm_dis_RXPCS_IDX_0 79 // Table10: PCS Per Channel RX Control Register 6 for Channel 0 `define rknumber_RXPCS_IDX_0 80 `define rknumber_RXPCS_IDX_1 81 `define rknumber_RXPCS_IDX_2 82 `define rknumber_RXPCS_IDX_3 83 `define rknumber_RXPCS_IDX_4 84 `define rknumber_RXPCS_IDX_5 85 `define rknumber_RXPCS_IDX_6 86 `define rknumber_RXPCS_IDX_7 87 `define rgnumber_RXPCS_IDX_0 88 `define rgnumber_RXPCS_IDX_1 89 `define rgnumber_RXPCS_IDX_2 90 `define rgnumber_RXPCS_IDX_3 91 `define rgnumber_RXPCS_IDX_4 92 `define rgnumber_RXPCS_IDX_5 93 `define rgnumber_RXPCS_IDX_6 94 `define rgnumber_RXPCS_IDX_7 95 // Table11: PCS Per Channel RX Control Register 7 for Channel 0 `define renpolinv_rx_RXPCS_IDX_0 96 `define rcascaded_8b10b_en_rx_RXPCS_IDX_0 97 `define r8b10b_dec_ibm_en_RXPCS_IDX_0 98 `define r8b10b_dec_ibm_en_RXPCS_IDX_1 99 `define rendec_rx_RXPCS_IDX_0 100 `define rautobtalg_dis_RXPCS_IDX_0 101 `define rrlv_en_RXPCS_IDX_0 102 `define rlp20ben_RXPCS_IDX_0 103 `define rforce_sig_det_pcs_RXPCS_IDX_0 104 `define rbyte_rev_en_RXPCS_IDX_0 105 `define rrundisp_RXPCS_IDX_0 106 `define rrundisp_RXPCS_IDX_1 107 `define rrundisp_RXPCS_IDX_2 108 `define rrundisp_RXPCS_IDX_3 109 `define rrundisp_RXPCS_IDX_4 110 `define rrundisp_RXPCS_IDX_5 111 // Table12: PCS Per Channel RX Control Register 8 for Channel 0 `define rclkcmpsq1p_0_RXPCS_IDX_0 112 `define rclkcmpsq1p_1_RXPCS_IDX_0 113 `define rclkcmpsq1p_2_RXPCS_IDX_0 114 `define rclkcmpsq1p_3_RXPCS_IDX_0 115 `define rclkcmpsq1p_4_RXPCS_IDX_0 116 `define rclkcmpsq1p_5_RXPCS_IDX_0 117 `define rclkcmpsq1p_6_RXPCS_IDX_0 118 `define rclkcmpsq1p_7_RXPCS_IDX_0 119 `define rclkcmpsq1p_8_RXPCS_IDX_0 120 `define rclkcmpsq1p_9_RXPCS_IDX_0 121 `define rclkcmpsqmd_RXPCS_IDX_0 122 `define rclkcmpinsertpad_RXPCS_IDX_0 123 `define rtruebac2bac_RXPCS_IDX_0 124 `define rskpsetbased_RXPCS_IDX_0 125 `define rgenericfifo_RXPCS_IDX_0 126 `define rmatchen_RXPCS_IDX_0 127 // Table13: PCS Per Channel RX Control Register 9 for Channel 0 `define rclkcmpsq1p_10_RXPCS_IDX_0 128 `define rclkcmpsq1p_11_RXPCS_IDX_0 129 `define rclkcmpsq1p_12_RXPCS_IDX_0 130 `define rclkcmpsq1p_13_RXPCS_IDX_0 131 `define rclkcmpsq1p_14_RXPCS_IDX_0 132 `define rclkcmpsq1p_15_RXPCS_IDX_0 133 `define rclkcmpsq1p_16_RXPCS_IDX_0 134 `define rclkcmpsq1p_17_RXPCS_IDX_0 135 `define rclkcmpsq1p_18_RXPCS_IDX_0 136 `define rclkcmpsq1p_19_RXPCS_IDX_0 137 `define reserved_0_TB13_RXPCS_IDX_0 138 `define rclkcmpsq1n_15_RXPCS_IDX_0 139 `define rclkcmpsq1n_16_RXPCS_IDX_0 140 `define rclkcmpsq1n_17_RXPCS_IDX_0 141 `define rclkcmpsq1n_18_RXPCS_IDX_0 142 `define rclkcmpsq1n_19_RXPCS_IDX_0 143 // Table14: PCS Per Channel RX Control Register 10 for Channel 0 `define rclkcmpsq1n_0_RXPCS_IDX_0 144 `define rclkcmpsq1n_1_RXPCS_IDX_0 145 `define rclkcmpsq1n_2_RXPCS_IDX_0 146 `define rclkcmpsq1n_3_RXPCS_IDX_0 147 `define rclkcmpsq1n_4_RXPCS_IDX_0 148 `define rclkcmpsq1n_5_RXPCS_IDX_0 149 `define rclkcmpsq1n_6_RXPCS_IDX_0 150 `define rclkcmpsq1n_7_RXPCS_IDX_0 151 `define rclkcmpsq1n_8_RXPCS_IDX_0 152 `define rclkcmpsq1n_9_RXPCS_IDX_0 153 `define reserved_0_TB14_RXPCS_IDX_0 154 `define rclkcmpsq1n_10_RXPCS_IDX_0 155 `define rclkcmpsq1n_11_RXPCS_IDX_0 156 `define rclkcmpsq1n_12_RXPCS_IDX_0 157 `define rclkcmpsq1n_13_RXPCS_IDX_0 158 `define rclkcmpsq1n_14_RXPCS_IDX_0 159 // Table15: PCS Per Channel RX Control Register 11 for Channel 0 `define rfull_threshold_RXPCS_IDX_0 160 `define rfull_threshold_RXPCS_IDX_1 161 `define rfull_threshold_RXPCS_IDX_2 162 `define rfull_threshold_RXPCS_IDX_3 163 `define rfull_threshold_RXPCS_IDX_4 164 `define rdel_threshold_RXPCS_IDX_0 165 `define rdel_threshold_RXPCS_IDX_1 166 `define rdel_threshold_RXPCS_IDX_2 167 `define rdel_threshold_RXPCS_IDX_3 168 `define rdel_threshold_RXPCS_IDX_4 169 `define rins_threshold_RXPCS_IDX_0 170 `define rins_threshold_RXPCS_IDX_1 171 `define rins_threshold_RXPCS_IDX_2 172 `define rins_threshold_RXPCS_IDX_3 173 `define rins_threshold_RXPCS_IDX_4 174 `define rclkcmp_pipe_en_RXPCS_IDX_0 175 // Table16: PCS Per Channel RX Control Register 12 for Channel 0 `define rfreq_sel_RXPCS_IDX_0 176 `define rauto_speed_ena_RXPCS_IDX_0 177 `define rhip_ena_RXPCS_IDX_0 178 `define rpma_done_gen_ena_RXPCS_IDX_0 179 `define rpma_done_count_16_RXPCS_IDX_0 180 `define rpma_done_count_17_RXPCS_IDX_0 181 `define reserved_0_TB16_RXPCS_IDX_0 182 `define reserved_0_TB16_RXPCS_IDX_1 183 `define reserved_0_TB16_RXPCS_IDX_2 184 `define reserved_0_TB16_RXPCS_IDX_3 185 `define rstart_threshold_RXPCS_IDX_0 186 `define rstart_threshold_RXPCS_IDX_1 187 `define rstart_threshold_RXPCS_IDX_2 188 `define rempty_threshold_RXPCS_IDX_0 189 `define rempty_threshold_RXPCS_IDX_1 190 `define rempty_threshold_RXPCS_IDX_2 191 // Table17: PCS Per Channel RX Control Register 13 for Channel 0 `define rtest_bus_sel_RXPCS_IDX_0 192 `define rtest_bus_sel_RXPCS_IDX_1 193 `define rtest_bus_sel_RXPCS_IDX_2 194 `define rtest_bus_sel_RXPCS_IDX_3 195 `define rautoinsdis_RXPCS_IDX_0 196 `define rphfifopldenrx_RXPCS_IDX_0 197 `define rbytordplden_RXPCS_IDX_0 198 `define rbyteorden_RXPCS_IDX_0 199 `define rbyteorden_RXPCS_IDX_1 200 `define rbytord_2sym_en_RXPCS_IDX_0 201 `define rinvalid_code_err_only_RXPCS_IDX_0 202 `define rcmpfifourst_RXPCS_IDX_0 203 `define rphfifourstrx_RXPCS_IDX_0 204 `define rdwidth_rx_RXPCS_IDX_0 205 `define rrxfifo_lowlatency_en_RXPCS_IDX_0 206 `define rrxfifo_dis_RXPCS_IDX_0 207 // Table18: PCS Per Channel RX Control Register 14 for Channel 0 `define rbytordpat_0_RXPCS_IDX_0 208 `define rbytordpat_1_RXPCS_IDX_0 209 `define rbytordpat_2_RXPCS_IDX_0 210 `define rbytordpat_3_RXPCS_IDX_0 211 `define rbytordpat_4_RXPCS_IDX_0 212 `define rbytordpat_5_RXPCS_IDX_0 213 `define rbytordpat_6_RXPCS_IDX_0 214 `define rbytordpat_7_RXPCS_IDX_0 215 `define rbytordpat_8_RXPCS_IDX_0 216 `define rbytordpat_9_RXPCS_IDX_0 217 `define reserved_0_TB18_RXPCS_IDX_0 218 `define reserved_0_TB18_RXPCS_IDX_1 219 `define reserved_0_TB18_RXPCS_IDX_2 220 `define reserved_0_TB18_RXPCS_IDX_3 221 `define reserved_0_TB18_RXPCS_IDX_4 222 `define reserved_0_TB18_RXPCS_IDX_5 223 // Table19: PCS Per Channel RX Control Register 15 for Channel 0 `define rbytordpad_RXPCS_IDX_0 224 `define rbytordpad_RXPCS_IDX_1 225 `define rbytordpad_RXPCS_IDX_2 226 `define rbytordpad_RXPCS_IDX_3 227 `define rbytordpad_RXPCS_IDX_4 228 `define rbytordpad_RXPCS_IDX_5 229 `define rbytordpad_RXPCS_IDX_6 230 `define rbytordpad_RXPCS_IDX_7 231 `define rbytordpad_RXPCS_IDX_8 232 `define rbytordpad_RXPCS_IDX_9 233 `define reserved_0_TB19_RXPCS_IDX_0 234 `define reserved_0_TB19_RXPCS_IDX_1 235 `define reserved_0_TB19_RXPCS_IDX_2 236 `define reserved_0_TB19_RXPCS_IDX_3 237 `define reserved_0_TB19_RXPCS_IDX_4 238 `define reserved_0_TB19_RXPCS_IDX_5 239 // Table20: PCS Per Channel RX Control Register 16 for Channel 0 `define rload_shreg_del_RXPCS_IDX_0 240 `define rload_shreg_del_RXPCS_IDX_1 241 `define rload_shreg_del_RXPCS_IDX_2 242 `define rload_shreg_del_RXPCS_IDX_3 243 `define rload_shreg_del_RXPCS_IDX_4 244 `define rphystatus_rst_toggle_RXPCS_IDX_0 245 `define reidle_com_detect_RXPCS_IDX_0 246 `define reidle_com_detect_RXPCS_IDX_1 247 `define rk285detect_RXPCS_IDX_0 248 `define reidleinferenable_RXPCS_IDX_0 249 `define rphystatus_delay_RXPCS_IDX_0 250 `define rphystatus_delay_RXPCS_IDX_1 251 `define rphystatus_delay_RXPCS_IDX_2 252 `define rind_error_reporting_RXPCS_IDX_0 253 `define rrx_detect_bypass_RXPCS_IDX_0 254 `define rrx_pipe_enable_RXPCS_IDX_0 255 // Table21: PCS Per Channel RX Control Register 17 for Channel 0 `define rpma_done_count_0_RXPCS_IDX_0 256 `define rpma_done_count_1_RXPCS_IDX_0 257 `define rpma_done_count_2_RXPCS_IDX_0 258 `define rpma_done_count_3_RXPCS_IDX_0 259 `define rpma_done_count_4_RXPCS_IDX_0 260 `define rpma_done_count_5_RXPCS_IDX_0 261 `define rpma_done_count_6_RXPCS_IDX_0 262 `define rpma_done_count_7_RXPCS_IDX_0 263 `define rpma_done_count_8_RXPCS_IDX_0 264 `define rpma_done_count_9_RXPCS_IDX_0 265 `define rpma_done_count_10_RXPCS_IDX_0 266 `define rpma_done_count_11_RXPCS_IDX_0 267 `define rpma_done_count_12_RXPCS_IDX_0 268 `define rpma_done_count_13_RXPCS_IDX_0 269 `define rpma_done_count_14_RXPCS_IDX_0 270 `define rpma_done_count_15_RXPCS_IDX_0 271 // Table22: PCS Per Channel RX Control Register 18 for Channel 0 `define rbytordpat_10_RXPCS_IDX_0 272 `define rbytordpat_11_RXPCS_IDX_0 273 `define rbytordpat_12_RXPCS_IDX_0 274 `define rbytordpat_13_RXPCS_IDX_0 275 `define rbytordpat_14_RXPCS_IDX_0 276 `define rbytordpat_15_RXPCS_IDX_0 277 `define rbytordpat_16_RXPCS_IDX_0 278 `define rbytordpat_17_RXPCS_IDX_0 279 `define rbytordpat_18_RXPCS_IDX_0 280 `define rbytordpat_19_RXPCS_IDX_0 281 `define rbytord_6g_mask_en_RXPCS_IDX_0 282 `define rbytord_s2gx_RXPCS_IDX_0 283 `define reserved_0_TB22_RXPCS_IDX_0 284 `define rcdr_ctrl_en_RXPCS_IDX_0 285 `define rrxpcsclkpwdn_RXPCS_IDX_0 286 `define rerr_flags_sel_RXPCS_IDX_0 287 // Table23: PCS Per Channel RX Control Register 19 for Channel 0 `define rwait_count_RXPCS_IDX_0 288 `define rwait_count_RXPCS_IDX_1 289 `define rwait_count_RXPCS_IDX_2 290 `define rwait_count_RXPCS_IDX_3 291 `define rwait_count_RXPCS_IDX_4 292 `define rwait_count_RXPCS_IDX_5 293 `define rwait_count_RXPCS_IDX_6 294 `define rwait_count_RXPCS_IDX_7 295 `define reserved_0_TB23_RXPCS_IDX_0 296 `define reserved_0_TB23_RXPCS_IDX_1 297 `define reserved_0_TB23_RXPCS_IDX_2 298 `define reserved_0_TB23_RXPCS_IDX_3 299 `define reserved_0_TB23_RXPCS_IDX_4 300 `define reserved_0_TB23_RXPCS_IDX_5 301 `define reserved_0_TB23_RXPCS_IDX_6 302 `define reserved_0_TB23_RXPCS_IDX_7 303 // Table24: PCS Per Channel RX Control Register 20 for Channel 0 `define rfts_count_RXPCS_IDX_0 304 `define rfts_count_RXPCS_IDX_1 305 `define rfts_count_RXPCS_IDX_2 306 `define rfts_count_RXPCS_IDX_3 307 `define rfts_count_RXPCS_IDX_4 308 `define rfts_count_RXPCS_IDX_5 309 `define rfts_count_RXPCS_IDX_6 310 `define rfts_count_RXPCS_IDX_7 311 `define rfts_count_RXPCS_IDX_8 312 `define rfts_count_RXPCS_IDX_9 313 `define rwait_for_phfifo_cnt_RXPCS_IDX_0 314 `define rwait_for_phfifo_cnt_RXPCS_IDX_1 315 `define rwait_for_phfifo_cnt_RXPCS_IDX_2 316 `define rwait_for_phfifo_cnt_RXPCS_IDX_3 317 `define rwait_for_phfifo_cnt_RXPCS_IDX_4 318 `define rwait_for_phfifo_cnt_RXPCS_IDX_5 319 // Table25: PCS Per Channel RX Control Register 21 for Channel 0 `define rppm_meas_delay_RXPCS_IDX_0 320 `define rcid_len_rx_RXPCS_IDX_0 321 `define rcid_len_rx_RXPCS_IDX_1 322 `define rcid_len_rx_RXPCS_IDX_2 323 `define rcid_len_rx_RXPCS_IDX_3 324 `define rcid_len_rx_RXPCS_IDX_4 325 `define rcid_len_rx_RXPCS_IDX_5 326 `define rcid_len_rx_RXPCS_IDX_6 327 `define rcid_len_rx_RXPCS_IDX_7 328 `define rcid_pattern_rx_RXPCS_IDX_0 329 `define rpcs_wrapback_en_RXPCS_IDX_0 330 `define reserved_0_TB25_RXPCS_IDX_0 331 `define reserved_0_TB25_RXPCS_IDX_1 332 `define reserved_0_TB25_RXPCS_IDX_2 333 `define reserved_0_TB25_RXPCS_IDX_3 334 `define reserved_0_TB25_RXPCS_IDX_4 335 // Table26: PCS Per Channel RX Control Register 22 for Channel 0 `define rauto_pc_en_cnt_RXPCS_IDX_0 336 `define rauto_pc_en_cnt_RXPCS_IDX_1 337 `define rauto_pc_en_cnt_RXPCS_IDX_2 338 `define rauto_pc_en_cnt_RXPCS_IDX_3 339 `define rauto_pc_en_cnt_RXPCS_IDX_4 340 `define reserved_1_TB26_RXPCS_IDX_0 341 `define rauto_deassert_pc_rst_cnt_RXPCS_IDX_0 342 `define rauto_deassert_pc_rst_cnt_RXPCS_IDX_1 343 `define rauto_deassert_pc_rst_cnt_RXPCS_IDX_2 344 `define rauto_deassert_pc_rst_cnt_RXPCS_IDX_3 345 `define reserved_0_TB26_RXPCS_IDX_0 346 `define rpipeline_bypass_rx_RXPCS_IDX_0 347 `define rself_sw_en_rx_RXPCS_IDX_0 348 `define rrxvalid_mask_RXPCS_IDX_0 349 `define rcid_en_RXPCS_IDX_0 350 `define rphfifo_regmode_rx_RXPCS_IDX_0 351 // Table27: PCS Per Channel RX Control Register 23 for Channel 0 `define rmask_count_RXPCS_IDX_0 352 `define rmask_count_RXPCS_IDX_1 353 `define rmask_count_RXPCS_IDX_2 354 `define rmask_count_RXPCS_IDX_3 355 `define rmask_count_RXPCS_IDX_4 356 `define rmask_count_RXPCS_IDX_5 357 `define rmask_count_RXPCS_IDX_6 358 `define rmask_count_RXPCS_IDX_7 359 `define rmask_count_RXPCS_IDX_8 360 `define rmask_count_RXPCS_IDX_9 361 `define rgen1_sigdet_ena_RXPCS_IDX_0 362 `define riei_eios_priority_dis_RXPCS_IDX_0 363 `define reserved_0_TB27_RXPCS_IDX_0 364 `define reserved_0_TB27_RXPCS_IDX_1 365 `define reserved_0_TB27_RXPCS_IDX_2 366 `define reserved_0_TB27_RXPCS_IDX_3 367 // Manual section ---------------------------------- `define rpmadwidth_rx_RX_IDX 368 `define rpma_doublewidth_rx_RX_IDX 369 // RX portion of global_ctrl 1 //`define rphfifo_master_sel_rx_TX_IDX `define rendec_data_sel_rx_RX_IDX 370 `define rdeskewen_RX_IDX 371 `define rindv_rx_RX_IDX 372 // RX portion of global_ctrl 2 `define rdskposdisp_RX_IDX 373 //`define ralgnopt_RX_IDX //`define rdskchrp[9:0] // RX portion of global_ctrl 3 `define rmaster_rx_RX_IDX 374 `define rmaster_up_rx_RX_IDX 375 // not used - legacy from rx_pcs.v `define rdwidth_rx_RX_IDX 380 `define rtx_idle_delay_RX_IDX_0 381 `define rtx_idle_delay_RX_IDX_1 382 `define rclkcmppos_RX_IDX 383 `define rppmsel_RX_IDX_0 384 `define rppmsel_RX_IDX_5 389 `define rforce0_freqdet_RX_IDX 390 `define rforce1_freqdet_RX_IDX 391 `define rs_lpbk_RX_IDX 392 `define rrx_revlb_sw_RX_IDX 393 `timescale 1 ps / 1 ps module stratixiv_hssi_rx_pcs ( a1a2size, alignstatus, alignstatussync, autospdxnconfigsel, autospdxnspdchg, bitslip, cdrctrllocktorefcl, coreclk, datain, digitalreset, disablefifordin, disablefifowrin, dpriodisable, dprioin, elecidleinfersel, enabledeskew, enabyteord, enapatternalign, fifordin, fiforesetrd, grayelecidleinferselfromtx, hip8b10binvpolarity, hipelecidleinfersel, hippowerdown, hiprateswitch, invpol, iqpautospdxnspgchg, iqpphfifoxnbytesel, iqpphfifoxnptrsreset, iqpphfifoxnrdenable, iqpphfifoxnwrclk, iqpphfifoxnwrenable, localrefclk, masterclk, parallelfdbk, phfifordenable, phfiforeset, phfifowrdisable, phfifox4bytesel, phfifox4rdenable, phfifox4wrclk, phfifox4wrenable, phfifox8bytesel, phfifox8rdenable, phfifox8wrclk, phfifox8wrenable, phfifoxnbytesel, phfifoxnptrsreset, phfifoxnrdenable, phfifoxnwrclk, phfifoxnwrenable, pipe8b10binvpolarity, pipeenrevparallellpbkfromtx, pipepowerdown, pipepowerstate, pmatestbusin, powerdn, ppmdetectdividedclk, ppmdetectrefclk, prbscidenable, quadreset, rateswitch, rateswitchisdone, rateswitchxndone, recoveredclk, refclk, revbitorderwa, revbyteorderwa, rmfifordena, rmfiforeset, rmfifowrena, rxdetectvalid, rxelecidlerateswitch, rxfound, signaldetected, wareset, xauidelcondmet, xauififoovr, xauiinsertincomplete, xauilatencycomp, xgmctrlin, xgmdatain, a1a2sizeout, a1detect, a2detect, adetectdeskew, alignstatussyncout, autospdrateswitchout, autospdspdchgout, bistdone, bisterr, bitslipboundaryselectout, byteorderalignstatus, cdrctrlearlyeios, cdrctrllocktorefclkout, clkout, coreclkout, ctrldetect, dataout, dataoutfull, digitaltestout, disablefifordout, disablefifowrout, disperr, dprioout, errdetect, fifordout, hipdataout, hipdatavalid, hipelecidle, hipphydonestatus, hipstatus, iqpphfifobyteselout, iqpphfifoptrsresetout, iqpphfifordenableout, iqpphfifowrclkout, iqpphfifowrenableout, k1detect, k2detect, patterndetect, phfifobyteselout, phfifobyteserdisableout, phfifooverflow, phfifoptrsresetout, phfifordenableout, phfiforesetout, phfifounderflow, phfifowrclkout, phfifowrdisableout, phfifowrenableout, // old bundle ptr to remove pipebufferstat, pipedatavalid, pipeelecidle, pipephydonestatus, pipestatus, pipestatetransdoneout, rateswitchout, rdalign, revparallelfdbkdata, rlv, rmfifoalmostempty, rmfifoalmostfull, rmfifodatadeleted, rmfifodatainserted, rmfifoempty, rmfifofull, runningdisp, signaldetect, syncstatus, syncstatusdeskew, xauidelcondmetout, xauififoovrout, xauiinsertincompleteout, xauilatencycompout, xgmctrldet, xgmdataout, xgmdatavalid, xgmrunningdisp ); parameter lpm_type = "stratixiv_hssi_rx_pcs"; parameter align_ordered_set_based = "false"; parameter align_pattern = "0101111100"; // word align: size of align_pattern_length; parameter align_pattern_length = 10; // <7, 8, 10, 16, 20, 32, 40>; parameter align_to_deskew_pattern_pos_disp_only = "false"; parameter allow_align_polarity_inversion = "false"; parameter allow_pipe_polarity_inversion = "false"; parameter auto_spd_deassert_ph_fifo_rst_count = 0 ; parameter auto_spd_phystatus_notify_count = 0 ; parameter auto_spd_self_switch_enable = "false"; parameter bit_slip_enable = "false"; parameter byte_order_back_compat_enable = "false"; parameter byte_order_double_data_mode_mask_enable = "false"; parameter byte_order_invalid_code_or_run_disp_error = "false"; parameter byte_order_mode = "none"; //NEW_PARAM_replace byte_ordering_mode parameter byte_order_pad_pattern = "0101111100";// <10-bit binary string>; parameter byte_order_pattern = "0101111100";// <10-bit binary string>; parameter byte_order_pld_ctrl_enable = "false"; parameter cdrctrl_bypass_ppm_detector_cycle = 0 ; parameter cdrctrl_cid_mode_enable = "false"; parameter cdrctrl_enable = "false"; parameter cdrctrl_mask_cycle = 0 ; parameter cdrctrl_min_lock_to_ref_cycle = 0 ; parameter cdrctrl_rxvalid_mask = "false"; parameter channel_bonding = "none"; // ; parameter channel_number = 0; // ; parameter channel_width = 10; // ; parameter clk1_mux_select = "recvd_clk"; // ; parameter clk2_mux_select = "recvd_clk"; // ; parameter clk_pd_enable = "false"; parameter core_clock_0ppm = "false"; parameter datapath_low_latency_mode = "false"; parameter datapath_protocol = "basic"; // ; parameter dec_8b_10b_compatibility_mode = "true"; parameter dec_8b_10b_mode = "none"; // ; parameter dec_8b_10b_polarity_inv_enable = "false"; parameter deskew_pattern = "1100111100";// K28.3 parameter disable_auto_idle_insertion = "false"; parameter disable_running_disp_in_word_align = "false"; parameter disallow_kchar_after_pattern_ordered_set = "false"; parameter dprio_config_mode = 6'h00; parameter elec_idle_eios_detect_priority_over_eidle_disable = "false"; parameter elec_idle_gen1_sigdet_enable = "false"; parameter elec_idle_infer_enable = "false"; parameter elec_idle_k_detect = "false"; parameter elec_idle_num_com_detect = 0 ; parameter enable_bit_reversal = "false"; parameter enable_deep_align = "false"; parameter enable_deep_align_byte_swap = "false"; parameter enable_self_test_mode = "false"; parameter enable_true_complement_match_in_word_align = "true"; parameter error_from_wa_or_8b_10b_select = "false"; parameter force_signal_detect_dig = "false"; parameter hip_enable = "false"; parameter infiniband_invalid_code = 0; // ; parameter insert_pad_on_underflow = "false"; parameter iqp_bypass = "false"; parameter iqp_ph_fifo_xn_select = 9999 ; parameter logical_channel_address = 0 ; parameter num_align_code_groups_in_ordered_set = 1; // ; parameter num_align_cons_good_data = 3; // wordalign; parameter num_align_cons_pat = 4; // ; parameter num_align_loss_sync_error = 1; //NEW_PARAM_replace align_loss_sync_error_num parameter ph_fifo_disable = "false"; parameter ph_fifo_low_latency_enable = "false"; parameter ph_fifo_reg_mode = "false"; parameter ph_fifo_reset_enable = "false"; parameter ph_fifo_user_ctrl_enable = "false"; parameter ph_fifo_xn_mapping0 = "none"; parameter ph_fifo_xn_mapping1 = "none"; parameter ph_fifo_xn_mapping2 = "none"; parameter ph_fifo_xn_select = 9999 ; parameter phystatus_delay = 0 ; parameter phystatus_reset_toggle = "false"; parameter pipe_auto_speed_nego_enable = "false"; parameter pipe_freq_scale_mode = "Data width"; parameter pipe_hip_enable = "false"; //NEW_PARAM todo: remove still in wys but not used parameter pma_done_count = 53392 ; parameter prbs_all_one_detect = "false"; parameter prbs_cid_pattern = "false"; parameter prbs_cid_pattern_length = 0 ; parameter protocol_hint = "basic"; parameter rate_match_almost_empty_threshold = 11; //todo: remove ; still in wys but not used parameter rate_match_almost_full_threshold = 13; // todo: remove ; still in wys but not used parameter rate_match_back_to_back = "false"; parameter rate_match_delete_threshold = 13 ; parameter rate_match_empty_threshold = 5 ; parameter rate_match_fifo_mode = "false"; // in s2gx, bool in s4gx; parameter rate_match_full_threshold = 20 ; parameter rate_match_insert_threshold = 11 ; parameter rate_match_ordered_set_based = "false"; // ; parameter rate_match_pattern1 = "00000000000010111100"; // <20-bit binary string>; parameter rate_match_pattern2 = "00000000000010111100"; // <20-bit binary string>; parameter rate_match_pattern_size = 10; // ; parameter rate_match_pipe_enable = "false"; parameter rate_match_reset_enable = "true"; //NEW_PARAM - default diff from atom parameter rate_match_skip_set_based = "false"; parameter rate_match_start_threshold = 0 ; parameter rd_clk_mux_select = "int_clk"; // ; parameter recovered_clk_mux_select = "recvd_clk"; // ; parameter reset_clock_output_during_digital_reset = "false"; parameter run_length = 200; // <5-320 or 4-254 depending on the deserialization factor>; parameter run_length_enable = "false"; parameter rx_detect_bypass = "false"; parameter rx_phfifo_wait_cnt = 32 ; parameter rxstatus_error_report_mode = 0 ; parameter self_test_mode = "incremental"; // ; parameter test_bus_sel = 0 ; parameter use_alignment_state_machine = "false"; parameter use_deserializer_double_data_mode = "false"; parameter use_deskew_fifo = "false"; parameter use_double_data_mode = "false"; parameter use_parallel_loopback = "false"; parameter use_rising_edge_triggered_pattern_align = "false"; //83 para: new=23 rem=40 // POF ONLY parameters parameter enable_phfifo_bypass = "false"; // SIMULATION_ONLY_PARAMETERS_BEGIN parameter migrated_from_prev_family = "false"; // b165 // SIMULATION_ONLY_PARAMETERS_END // LOCAL_PARAMETERS_BEGIN parameter BASIC_WIDTH = (channel_width % 10 == 0) ? 10 : 8; parameter NUM_OF_BASIC = channel_width / BASIC_WIDTH; parameter mph_fifo_xn_mapping = (ph_fifo_xn_select == 0) ? ph_fifo_xn_mapping0 :(ph_fifo_xn_select == 1) ? ph_fifo_xn_mapping1 :(ph_fifo_xn_select == 2) ? ph_fifo_xn_mapping2 : "none"; parameter MPHFIFO_INDEX = (ph_fifo_xn_select == 0 || ph_fifo_xn_select == 1 || ph_fifo_xn_select == 2) ? ph_fifo_xn_select : 0; parameter MIQP_PHFIFO_INDEX = (ph_fifo_xn_select == 0 || ph_fifo_xn_select == 1) ? ph_fifo_xn_select : 0; // LOCAL_PARAMETERS_END input a1a2size; input alignstatus; input alignstatussync; input [2 : 0] autospdxnconfigsel; // config_sel_centrl, quad_up, quad_down input [2 : 0] autospdxnspdchg; // From CMU.spped-change_centrl, rx3(up), rx0(down) input bitslip; input cdrctrllocktorefcl; // pld_ltr input coreclk; input [19:0] datain; //NEW: updated width input digitalreset; input disablefifordin; //todo: wys removal (old rx0 fifo pointers) still in wys but not used input disablefifowrin; //todo: wys removal (old rx0 fifo pointers) still in wys but not used input dpriodisable; input [399: 0] dprioin; input [2 : 0] elecidleinfersel; input enabledeskew; input enabyteord; input enapatternalign; input fifordin; input fiforesetrd; input [2 : 0] grayelecidleinferselfromtx; // eidleinfersel input hip8b10binvpolarity; // hip_rxpolarity input [2 : 0] hipelecidleinfersel; // hip_eidleinfersel_ch input [1 : 0] hippowerdown; // hip_powerdown_ch input hiprateswitch; // hip_rate input invpol; input [1 : 0] iqpautospdxnspgchg; // speed_change_in_pipe_quad_up, down input [1 : 0] iqpphfifoxnbytesel; // wr_enable_ptrs_in_pipe_quad_up, down input [1 : 0] iqpphfifoxnptrsreset; // reset_pc_ptrs_in_pipe_quad_up, down input [1 : 0] iqpphfifoxnrdenable; // rd_enable_ptrs_in_pipe_quad_up, down input [1 : 0] iqpphfifoxnwrclk; // rx_div2_sync_in_pipe_quad_up, down input [1 : 0] iqpphfifoxnwrenable; // wr_enable_ptrs_in_pipe_quad_up, down input localrefclk; input masterclk; input [19:0] parallelfdbk; input phfifordenable; input phfiforeset; input phfifowrdisable; input phfifox4bytesel; input phfifox4rdenable; input phfifox4wrclk; input phfifox4wrenable; input phfifox8bytesel; input phfifox8rdenable; input phfifox8wrclk; input phfifox8wrenable; input [2 : 0] phfifoxnbytesel; // rx_we_in_centrl, quad_up, quad_down input [2 : 0] phfifoxnptrsreset; // ph fifo. From CMU to both RX & TX. input [2 : 0] phfifoxnrdenable; // rd_enable_in_centrl, quad_up, quad_down input [2 : 0] phfifoxnwrclk; // ph fifo. From CMU to RX. input [2 : 0] phfifoxnwrenable; // wr_enable_in_centrl, quad_up, quad_down input pipe8b10binvpolarity; input pipeenrevparallellpbkfromtx; // pipe_loopbk input [1:0] pipepowerdown; input [3:0] pipepowerstate; input [7:0] pmatestbusin; // new 9.0 ww47 input [1:0] powerdn; input ppmdetectdividedclk; input ppmdetectrefclk; input prbscidenable; // prbs_cid_en input quadreset; input rateswitch; input rateswitchisdone; input rateswitchxndone; input recoveredclk; input refclk; input revbitorderwa; input revbyteorderwa; input rmfifordena; input rmfiforeset; input rmfifowrena; input rxdetectvalid; input rxelecidlerateswitch; input [1:0] rxfound; input signaldetected; input wareset; // new 9.1 input xauidelcondmet; // del_cond_met_0 input xauififoovr; // fifo_over_0 input xauiinsertincomplete; // insert_incomplete_0 input xauilatencycomp; // latency_comp_0 input xgmctrlin; input [7:0] xgmdatain; //54 ins --- output [3:0] a1a2sizeout; output [1:0] a1detect; output [1:0] a2detect; output adetectdeskew; output alignstatussyncout; output autospdrateswitchout; output autospdspdchgout;//speed_chang_out_pipe output bistdone; output bisterr; output [4 : 0] bitslipboundaryselectout;//wa_boundary output byteorderalignstatus; output cdrctrlearlyeios;// Asserted when K_I or K_X_I is detected on the incoming data. To PMA and/or PLD? output cdrctrllocktorefclkout;// Force CDR(RX PLL) to LTR. output clkout; output coreclkout; //Sim Only. From RX Ch0 to CMU output [3:0] ctrldetect; output [39:0] dataout; output [63:0] dataoutfull; // new in 6.1 output [9:0] digitaltestout; // new 90 ww47 output disablefifordout; //todo: WYS removal - old rx0 fifo ptr:still in wys not used output disablefifowrout; //todo: WYS removal - old rx0 fifo ptr:still in wys not used output [3:0] disperr; output [399:0] dprioout; output [3:0] errdetect; output fifordout; output [8 : 0] hipdataout; //hip_rxd_ch(8:0) output hipdatavalid; // hip_rxvalid output hipelecidle; // hip_rxelecidle output hipphydonestatus; // hip_phystatus output [2 : 0] hipstatus; // hip_rxstatus_ch(2:0) output iqpphfifobyteselout; // rx_we_out_pipe output iqpphfifoptrsresetout;// reset_pc_pters_out_pipe output iqpphfifordenableout; // rd_enable_pipe_out output iqpphfifowrclkout; // rx_div2_sync_out_pipe output iqpphfifowrenableout; // wr_enable_out_pipe output [1:0] k1detect; output [1:0] k2detect; output [3:0] patterndetect; output phfifobyteselout; output phfifobyteserdisableout; //From Auto Speed Neg to TX output phfifooverflow; output phfifoptrsresetout; //From Auto Speed Neg to TX output phfifordenableout; output phfiforesetout; //Sim Only. From RX Ch0 to CMU output phfifounderflow; output phfifowrclkout; output phfifowrdisableout; //Sim Only. From RX Ch0 to CMU output phfifowrenableout; output [3:0] pipebufferstat; output pipedatavalid; output pipeelecidle; output pipephydonestatus; output pipestatetransdoneout; output [2:0] pipestatus; output rateswitchout; output rdalign; output [19:0] revparallelfdbkdata; output rlv; output rmfifoalmostempty; output rmfifoalmostfull; output [3:0] rmfifodatadeleted; output [3:0] rmfifodatainserted; output rmfifoempty; output rmfifofull; output [3:0] runningdisp; output signaldetect; output [3:0] syncstatus; output syncstatusdeskew; output xauidelcondmetout; // del_cond_met_out output xauififoovrout; // fifo_over_out output xauiinsertincompleteout;// insert_incomplete_out output xauilatencycompout; // latency_comp_out output xgmctrldet; output [7:0] xgmdataout; output xgmdatavalid; output xgmrunningdisp; // 49 outs //////////////////////////////////////////////////////////////////////////////// // Temp registers to resolve fixed width ==> varaiable width output transfer -// //////////////////////////////////////////////////////////////////////////////// reg [3:0] a1a2sizeout_reg; reg [1:0] a1detect_reg; reg [1:0] a2detect_reg; reg [3:0] ctrldetect_reg; reg [39:0] dataout_reg; reg [3:0] disperr_reg; reg [3:0] errdetect_reg; reg [1:0] k1detect_reg; reg [1:0] k2detect_reg; reg [3:0] patterndetect_reg; reg [3:0] rmfifodatadeleted_reg; reg [3:0] rmfifodatainserted_reg; reg [3:0] runningdisp_reg; reg [3:0] syncstatus_reg; //////////////////////////////////////////////////////////////////////////////// // atom level initial CRAM --------------------------------------------------// //////////////////////////////////////////////////////////////////////////////// // Manual sections reg init_rpmadwidth_rx; reg init_rpma_doublewidth_rx; reg init_rendec_data_sel_rx; reg init_rdeskewen; reg init_rindv_rx; reg init_rdskposdisp; reg [1:0] init_dskwclksel; // not used in DPRIO reg init_is_lane0; reg [1:0] init_rbist_sel; reg [1:0] init_rbitslip_size; reg init_rclkcmppos; reg [1:0] init_rcxpat_chnl_en; reg [9:0] init_rdskchrp; reg init_renpolinv_en; reg init_rforce0_freqdet; reg init_rforce1_freqdet; reg init_rphfifo_master_sel_rx; reg init_rppm_cnt_reset; reg [5:0] init_rppmsel; reg [2:0] init_rprbs_sel; reg init_rrdwidth_rx; // rx only reg init_rrx_revlb_sw; reg init_rs_lpbk; reg [1:0] init_rtx_elec_idle_delay; // rx only reg init_rtx_pipe_enable; // tx pipe reg init_scan_mode; reg init_sel_gp_md; reg init_rmaster_rx; reg init_rmaster_up_rx; reg init_rphfifourstenrx; //0: PPM Detector counts to 32K in PIPE Gen1 operation //1: PPM Detector counts to 64K in PIPE Gen1 operation (default) reg init_rppm_gen1_2xcnt_en; //0: PPM Detector re-starts measurement 200 cycles after eidle exit (default) //1: PPM Detector re-starts measurement 400 cycles after eilde exit reg init_rppm_post_eidle_del; reg init_rrx_fifo_dis; // ignoring crams wire [2:0] tmp_cram_rtx_elec_idle_delay; // tx_only wire tmp_cram_rtxswing_sel_ena; // tx_only // --------------------------------------------------------------------------- // Initial CRAM // --------------------------------------------------------------------------- // PCS Per Channel RX Control Register 1 for Channel 0 reg init_rrxpcsbypass_en; reg init_rall_one_dect_only; reg init_rbist_clr_rx; reg init_rbisten_rx; reg init_rprbs_clr_rslt_rx; reg init_rprbsen_rx; reg init_rrx_rd_clk_sel; reg [1:0] init_rclk_2_sel; reg [1:0] init_rclk_1_sel; reg [1:0] init_rrcvd_clk_sel; reg init_rfreerun_rx; reg init_rrxurstpcs; reg init_reserved_0_TB5; // PCS Per Channel RX Control Register 2 for Channel 0 reg init_rcomp_pat_32; reg init_rcomp_pat_33; reg init_rcomp_pat_34; reg init_rcomp_pat_35; reg init_rcomp_pat_36; reg init_rcomp_pat_37; reg init_rcomp_pat_38; reg init_rcomp_pat_39; reg [2:0] init_rcomp_size; reg init_rcomp_pat_porn; reg init_rdis_rx_disp; reg init_rencdt_rising; reg [1:0] init_resync_badcg_en; // PCS Per Channel RX Control Register 3 for Channel 0 reg init_rcomp_pat_16; reg init_rcomp_pat_17; reg init_rcomp_pat_18; reg init_rcomp_pat_19; reg init_rcomp_pat_20; reg init_rcomp_pat_21; reg init_rcomp_pat_22; reg init_rcomp_pat_23; reg init_rcomp_pat_24; reg init_rcomp_pat_25; reg init_rcomp_pat_26; reg init_rcomp_pat_27; reg init_rcomp_pat_28; reg init_rcomp_pat_29; reg init_rcomp_pat_30; reg init_rcomp_pat_31; // PCS Per Channel RX Control Register 4 for Channel 0 reg init_rcomp_pat_0; reg init_rcomp_pat_1; reg init_rcomp_pat_2; reg init_rcomp_pat_3; reg init_rcomp_pat_4; reg init_rcomp_pat_5; reg init_rcomp_pat_6; reg init_rcomp_pat_7; reg init_rcomp_pat_8; reg init_rcomp_pat_9; reg init_rcomp_pat_10; reg init_rcomp_pat_11; reg init_rcomp_pat_12; reg init_rcomp_pat_13; reg init_rcomp_pat_14; reg init_rcomp_pat_15; reg [39:0] init_rcomp_pat; // PCS Per Channel RX Control Register 5 for Channel 0 reg init_rbitloc_rev_en; reg init_rbysync_polinv_en; reg init_rwa_6g_en; reg [1:0] init_rosnumber; reg init_rosbased; reg init_rkchar; reg [5:0] init_renumber; reg [1:0] init_rib_inv_cd; reg init_rsync_sm_dis; // PCS Per Channel RX Control Register 6 for Channel 0 reg [7:0] init_rknumber; reg [7:0] init_rgnumber; // PCS Per Channel RX Control Register 7 for Channel 0 reg init_renpolinv_rx; reg init_rcascaded_8b10b_en_rx; reg [1:0] init_r8b10b_dec_ibm_en; reg init_rendec_rx; reg init_rautobtalg_dis; reg init_rrlv_en; reg init_rlp20ben; reg init_rforce_sig_det_pcs; reg init_rbyte_rev_en; reg [5:0] init_rrundisp; // PCS Per Channel RX Control Register 8 for Channel 0 reg init_rclkcmpsq1p_0; reg init_rclkcmpsq1p_1; reg init_rclkcmpsq1p_2; reg init_rclkcmpsq1p_3; reg init_rclkcmpsq1p_4; reg init_rclkcmpsq1p_5; reg init_rclkcmpsq1p_6; reg init_rclkcmpsq1p_7; reg init_rclkcmpsq1p_8; reg init_rclkcmpsq1p_9; reg init_rclkcmpsqmd; reg init_rclkcmpinsertpad; reg init_rtruebac2bac; reg init_rskpsetbased; reg init_rgenericfifo; reg init_rmatchen; // PCS Per Channel RX Control Register 9 for Channel 0 reg init_rclkcmpsq1p_10; reg init_rclkcmpsq1p_11; reg init_rclkcmpsq1p_12; reg init_rclkcmpsq1p_13; reg init_rclkcmpsq1p_14; reg init_rclkcmpsq1p_15; reg init_rclkcmpsq1p_16; reg init_rclkcmpsq1p_17; reg init_rclkcmpsq1p_18; reg init_rclkcmpsq1p_19; reg init_reserved_0_TB13; reg init_rclkcmpsq1n_15; reg init_rclkcmpsq1n_16; reg init_rclkcmpsq1n_17; reg init_rclkcmpsq1n_18; reg init_rclkcmpsq1n_19; reg [19:0] init_rclkcmpsq1p; // PCS Per Channel RX Control Register 10 for Channel 0 reg init_rclkcmpsq1n_0; reg init_rclkcmpsq1n_1; reg init_rclkcmpsq1n_2; reg init_rclkcmpsq1n_3; reg init_rclkcmpsq1n_4; reg init_rclkcmpsq1n_5; reg init_rclkcmpsq1n_6; reg init_rclkcmpsq1n_7; reg init_rclkcmpsq1n_8; reg init_rclkcmpsq1n_9; reg init_reserved_0_TB14; reg init_rclkcmpsq1n_10; reg init_rclkcmpsq1n_11; reg init_rclkcmpsq1n_12; reg init_rclkcmpsq1n_13; reg init_rclkcmpsq1n_14; reg [19:0] init_rclkcmpsq1n; // PCS Per Channel RX Control Register 11 for Channel 0 reg [4:0] init_rfull_threshold; reg [4:0] init_rdel_threshold; reg [4:0] init_rins_threshold; reg init_rclkcmp_pipe_en; // PCS Per Channel RX Control Register 12 for Channel 0 reg init_rfreq_sel; reg init_rauto_speed_ena; reg init_rhip_ena; reg init_rpma_done_gen_ena; reg init_rpma_done_count_16; reg init_rpma_done_count_17; reg [3:0] init_reserved_0_TB16; reg [2:0] init_rstart_threshold; reg [2:0] init_rempty_threshold; // PCS Per Channel RX Control Register 13 for Channel 0 reg [3:0] init_rtest_bus_sel; reg init_rautoinsdis; reg init_rphfifopldenrx; reg init_rbytordplden; reg [1:0] init_rbyteorden; reg init_rbytord_2sym_en; reg init_rinvalid_code_err_only; reg init_rcmpfifourst; reg init_rphfifourstrx; reg init_rdwidth_rx; reg init_rrxfifo_lowlatency_en; reg init_rrxfifo_dis; // PCS Per Channel RX Control Register 14 for Channel 0 reg init_rbytordpat_0; reg init_rbytordpat_1; reg init_rbytordpat_2; reg init_rbytordpat_3; reg init_rbytordpat_4; reg init_rbytordpat_5; reg init_rbytordpat_6; reg init_rbytordpat_7; reg init_rbytordpat_8; reg init_rbytordpat_9; reg [5:0] init_reserved_0_TB18; reg [19:0] init_rbytordpat; // PCS Per Channel RX Control Register 15 for Channel 0 reg [9:0] init_rbytordpad; reg [5:0] init_reserved_0_TB19; // PCS Per Channel RX Control Register 16 for Channel 0 reg [4:0] init_rload_shreg_del; reg init_rphystatus_rst_toggle; reg [1:0] init_reidle_com_detect; reg init_rk285detect; reg init_reidleinferenable; reg [2:0] init_rphystatus_delay; reg init_rind_error_reporting; reg init_rrx_detect_bypass; reg init_rrx_pipe_enable; // PCS Per Channel RX Control Register 17 for Channel 0 reg init_rpma_done_count_0; reg init_rpma_done_count_1; reg init_rpma_done_count_2; reg init_rpma_done_count_3; reg init_rpma_done_count_4; reg init_rpma_done_count_5; reg init_rpma_done_count_6; reg init_rpma_done_count_7; reg init_rpma_done_count_8; reg init_rpma_done_count_9; reg init_rpma_done_count_10; reg init_rpma_done_count_11; reg init_rpma_done_count_12; reg init_rpma_done_count_13; reg init_rpma_done_count_14; reg init_rpma_done_count_15; reg [17:0] init_rpma_done_count; // PCS Per Channel RX Control Register 18 for Channel 0 reg init_rbytordpat_10; reg init_rbytordpat_11; reg init_rbytordpat_12; reg init_rbytordpat_13; reg init_rbytordpat_14; reg init_rbytordpat_15; reg init_rbytordpat_16; reg init_rbytordpat_17; reg init_rbytordpat_18; reg init_rbytordpat_19; reg init_rbytord_6g_mask_en; reg init_rbytord_s2gx; reg init_reserved_0_TB22; reg init_rcdr_ctrl_en; reg init_rrxpcsclkpwdn; reg init_rerr_flags_sel; // PCS Per Channel RX Control Register 19 for Channel 0 reg [7:0] init_rwait_count; reg [7:0] init_reserved_0_TB23; // PCS Per Channel RX Control Register 20 for Channel 0 reg [9:0] init_rfts_count; reg [5:0] init_rwait_for_phfifo_cnt; // PCS Per Channel RX Control Register 21 for Channel 0 reg init_rppm_meas_delay; reg [7:0] init_rcid_len_rx; reg init_rcid_pattern_rx; reg init_rpcs_wrapback_en; reg [4:0] init_reserved_0_TB25; // PCS Per Channel RX Control Register 22 for Channel 0 reg [4:0] init_rauto_pc_en_cnt; reg init_reserved_1_TB26; reg [3:0] init_rauto_deassert_pc_rst_cnt; reg init_reserved_0_TB26; reg init_rpipeline_bypass_rx; reg init_rself_sw_en_rx; reg init_rrxvalid_mask; reg init_rcid_en; reg init_rphfifo_regmode_rx; // PCS Per Channel RX Control Register 23 for Channel 0 reg [9:0] init_rmask_count; reg init_rgen1_sigdet_ena; reg init_riei_eios_priority_dis; reg [3:0] init_reserved_0_TB27; //////////////////////////////////////////////////////////////////////////////// // sub-block interface: pcs_reset (pr) --------------------------------------// //////////////////////////////////////////////////////////////////////////////// wire pr_in_hard_reset; wire pr_in_clk_2_b; wire pr_in_refclk_b_in; wire pr_in_scan_mode; wire pr_in_rxpcs_rst; wire pr_in_txpcs_rst; wire pr_out_rxrst_int; wire pr_out_txrst_int; //////////////////////////////////////////////////////////////////////////////// // sub-block interface: chnl_hip_spt ----------------------------------------// //////////////////////////////////////////////////////////////////////////////// wire [2:0] hs_in_eidleinfersel_ch; wire [2:0] hs_in_hip_eidleinfersel_ch; wire [1:0] hs_in_hip_powerdown_ch; wire hs_in_hip_rate; wire hs_in_hip_rxpolarity; wire [9:0] hs_in_hip_txd_ch; wire hs_in_hip_txdeemph; wire hs_in_hip_txdetectrxloopback; wire hs_in_hip_txelecidle; wire [2:0] hs_in_hip_txmargin_ch; wire hs_in_pcs_phystatus; wire [8:0] hs_in_pcs_rxd_ch; wire hs_in_pcs_rxelecidle; wire [2:0] hs_in_pcs_rxstatus_ch; wire hs_in_pcs_rxvalid; wire [1:0] hs_in_powerdown_ch; wire hs_in_rate; wire hs_in_rhip_ena; wire hs_in_rxpolarity; wire [10:0] hs_in_txd_ch; wire hs_in_txdeemph; wire hs_in_txdetectrxloopback; wire [2:0] hs_in_txmargin_ch; wire hs_in_txpma_local_clk; wire hs_out_hip_phystatus; wire [8:0] hs_out_hip_rxd_ch; wire hs_out_hip_rxelecidle; wire [2:0] hs_out_hip_rxstatus_ch; wire hs_out_hip_rxvalid; wire hs_out_hip_tx_clk; wire [2:0] hs_out_pcs_eidleinfersel_ch; wire [1:0] hs_out_pcs_powerdown_ch; wire hs_out_pcs_rate; //feed rx0.pcs_rate to cmu wire hs_out_pcs_rxpolarity; wire [10:0] hs_out_pcs_txd_ch; wire hs_out_pcs_txdeemph; wire hs_out_pcs_txdetectrxloopback; wire [2:0] hs_out_pcs_txmargin_ch; wire hs_out_phystatus; wire [8:0] hs_out_rxd_ch; wire hs_out_rxelecidle; wire [2:0] hs_out_rxstatus_ch; wire hs_out_rxvalid; //////////////////////////////////////////////////////////////////////////////// // sub-block interface: pipe_interface (pi) ---------------------------------// //////////////////////////////////////////////////////////////////////////////// wire pi_in_pipe_rx_clk; // beginning input wire pi_in_pipe_tx_clk; wire pi_in_polinv_rx; wire pi_in_power_state_transition_done; wire pi_in_power_state_transition_done_ena; wire [1:0] pi_in_powerdown; wire pi_in_refclk_b; wire pi_in_refclk_b_reset; wire pi_in_revloopback; wire pi_in_rx_detect_valid; wire pi_in_rx_found; wire pi_in_rx_pipe_reset; wire pi_in_rxbeacon; wire [63:0] pi_in_rxd; wire pi_in_rxelectricalidle; wire pi_in_rxpolarity; wire pi_in_tx_elec_idle_comp; wire pi_in_tx_pipe_reset; wire pi_in_txcompliance; wire [43:0] pi_in_txd_ch; wire pi_in_txdetectrxloopback; wire pi_in_txelecidle; wire [3:0] pi_in_powerstatein; wire pi_in_txdetectrxin; // new stratixiv input interfaces - ww26.5 wire pi_in_speed_change; // from rx_digi - Auto Speed Negotiation Module wire pi_in_txdeemph; // tx_only wire [2:0] pi_in_txmargin; // tx only wire pi_in_txswing; // tx only // ww47 input interfaces wire pi_in_speed_change_centrl; wire pi_in_speed_change_quad_up; wire pi_in_speed_change_quad_down; // ww25.2008 wire pi_in_sigdetni; wire pi_out_phystatus; // beginning output wire pi_out_sim_state_transition_done; wire pi_out_polinv_rx_int; wire [3:0] pi_out_powerstate; // to both cmu and rx wire pi_out_rev_loopbk; wire [63:0] pi_out_rxd_ch; wire pi_out_rxelecidle; wire [2:0] pi_out_rxstatus; wire pi_out_rxvalid; wire pi_out_tx_elec_idle; wire pi_out_txbeacon; wire [43:0] pi_out_txd; wire pi_out_txdetectrx; // new stratixiv output interfaces - ww26.5 wire pi_out_txdeemph_int; //tx only wire [2:0] pi_out_txmargin_int; //tx only wire pi_out_txswing_int; //tx only //////////////////////////////////////////////////////////////////////////////// // sub-block interface: rx_digi (rd) ----------------------------------------// //////////////////////////////////////////////////////////////////////////////// wire rd_in_a1a2_size; // begin input wire rd_in_align_status; wire rd_in_align_status_sync_0; wire rd_in_align_status_sync_2; wire rd_in_bitloc_rev_en; wire rd_in_bitslip; wire rd_in_byte_rev_en; wire rd_in_bytordpld; wire rd_in_clklow; wire rd_in_cmpfifourst; wire rd_in_en_dskw_gp; wire rd_in_en_dskw_qd; wire rd_in_encdt; wire [9:0] rd_in_encoder_testbus; wire rd_in_fifo_rd_in_comp_0; wire rd_in_fifo_rd_in_comp_2; wire rd_in_fifo_rst_rd_gp; wire rd_in_fifo_rst_rd_qd; wire rd_in_fref; wire rd_in_hard_reset; wire rd_in_phfifourst_rx; wire rd_in_pld_rx_clk; wire [7:0] rd_in_pma_testbus; wire rd_in_polinv_rx; wire [19:0] rd_in_pudi; wire rd_in_rcvd_clk_pma; wire rd_in_rcvd_clk0_pma; wire rd_in_rdenable_rmf; wire rd_in_rdenable_rx; wire rd_in_refclk_pma; wire rd_in_rx_control_rs; wire [7:0] rd_in_rx_data_rs; wire rd_in_rxpma_rst; wire rd_in_rxpcs_rst; wire rd_in_sigdetni; wire [9:0] rd_in_tx_ctrl_testbus; wire [19:0] rd_in_txlp20b; wire rd_in_txpma_local_clk; wire rd_in_wrdisable_rx; wire rd_in_wrenable_rmf; // new input interfaces in STRATIXIV - ww26.5 // WYS (eidleinfersel) wire [2:0] rd_in_eidleinfersel; // Electrical Idle inference mechanism select // WYS (rateswitchdone) wire rd_in_gen2ngen1; // frequency switch done from PMA (rising edge of old clock to rising edge of new clock) // WYS (rateswitchxndone) wire rd_in_gen2ngen1_bundle; // for bundle //to rx_ctrl and grouped with rxstatus_int,rxvalid_int as pipe_status_in //impact the out phystatus //from: rx_pipe wire rd_in_phystatus_int; //from pma to auto_negotiation //from top feeding to both rx and tx_pcs. wire [1:0] rd_in_powerdown; //from tx_ctrl - WYS (rateswitch) // WYS (rxelecidlerateswitch) //from rx_pipe feeding to rx_ctrl wire [2:0] rd_in_rxstatus_int; //from rx_pipe feeding to rx_ctrl wire rd_in_rxvalid_int; // ww47 RTL update - input interfaces ------------------------------------ wire rd_in_rate; // rate change output from upper layers. // from digi_chnl_support // CDR control wire rd_in_pld_ltr; // PLD control of the CDR when rcdr_ctrl_en = 1'b0 wire rd_in_prbs_cid_en; // PLD control of PRBS-CID enable // new signal inputs for bundling wire rd_in_rx_div2_sync_in_centrl; wire rd_in_rx_div2_sync_in_quad_up; wire rd_in_rx_div2_sync_in_quad_down; wire rd_in_reset_pc_ptrs_in_centrl; wire rd_in_reset_pc_ptrs_in_quad_up; wire rd_in_reset_pc_ptrs_in_quad_down; wire rd_in_wr_enable_in_centrl; wire rd_in_wr_enable_in_quad_up; wire rd_in_wr_enable_in_quad_down; wire rd_in_rd_enable_in_centrl; wire rd_in_rd_enable_in_quad_up; wire rd_in_rd_enable_in_quad_down; wire rd_in_rx_we_in_centrl; wire rd_in_rx_we_in_quad_up; wire rd_in_rx_we_in_quad_down; wire rd_in_speed_change_in_centrl;// up/down signals are in pipe_top_interface // pipeline inputs for bundling wire rd_in_rx_div2_sync_in_pipe_quad_up; wire rd_in_rx_div2_sync_in_pipe_quad_down; wire rd_in_reset_pc_ptrs_in_pipe_quad_up; wire rd_in_reset_pc_ptrs_in_pipe_quad_down; wire rd_in_wr_enable_in_pipe_quad_up; wire rd_in_wr_enable_in_pipe_quad_down; wire rd_in_rd_enable_in_pipe_quad_up; wire rd_in_rd_enable_in_pipe_quad_down; wire rd_in_rx_we_in_pipe_quad_up; wire rd_in_rx_we_in_pipe_quad_down; wire rd_in_speed_change_in_pipe_quad_up; wire rd_in_speed_change_in_pipe_quad_down; // Bundle Mode Inputs for config_sel wire rd_in_config_sel_centrl; wire rd_in_config_sel_quad_up; wire rd_in_config_sel_quad_down; // output interfaces ----------------------------------------------------- wire [3:0] rd_out_a1a2_k1k2_flag; // begin output wire rd_out_align_det_sync; wire rd_out_align_status_sync; wire rd_out_almost_fl_rmf; wire rd_out_almost_mt_rmf; wire rd_out_bistdone; wire rd_out_bisterr; wire rd_out_byteord_flag; wire [1:0] rd_out_cg_comma; wire [9:0] rd_out_chnl_test_bus_out; wire rd_out_clk_2_b; wire rd_out_dec_ctl; wire [7:0] rd_out_dec_data; wire rd_out_dec_data_valid; wire rd_out_empty_rmf; wire rd_out_empty_rx; wire [1:0] rd_out_err_ctl; wire [15:0] rd_out_err_data; wire rd_out_fifo_rd_out_comp; wire rd_out_freq_lock; wire rd_out_full_rmf; wire rd_out_full_rx; wire rd_out_prbs_done; wire rd_out_prbs_err_lt; wire rd_out_rcvd_clk_pma_b; wire rd_out_rd_align; wire [19:0] rd_out_rev_loop_data; wire rd_out_rlv; wire rd_out_rlv_lt; wire [1:0] rd_out_running_disp; wire rd_out_rx_clk; wire rd_out_rx_pipe_clk; wire rd_out_rx_pipe_soft_reset; wire [63:0] rd_out_rxd; wire rd_out_selftest_done; wire rd_out_selftest_err; wire rd_out_signal_detect_out; wire rd_out_sync_status; // new output interfaces - ww26.5 //from auto_speed_neg to nowhere //from auto_speed_neg to nowhere to tx_digi (tx_ctrl) // to PLD wire rd_out_phystatus; //to PIPE's rxd (UPDATE) wire [63:0] rd_out_pipe_data; // from rx_ctrl to:nowhere wire rd_out_soft_reset_rclk1; // Synchronized reset //from auto_speed_neg to nowhere to rx_pipe wire rd_out_speed_change; // speed change done to PIPE interface (i.e. auto negotiation done) //from electrial_idle_inference_module to PCS_TOP //from electrial_idle_inference_module to rx_pipe wire rd_out_rxelecidle_int; // Asserted when Electrical Idle is detected //to PLD wire [2:0] rd_out_rxstatus; wire rd_out_rxvalid; // values greater than 2 entails that syncstatus is used // ww47 RTL output interfaces ------------------------------------------------- // to PLD and then back to tx_boundary_sel of tx_pcs wire [4:0] rd_out_wa_boundary; //describes word boundary // CDR control wire rd_out_early_eios; // Asserted when K_I or K_X_I is detected on the incoming data // to PLD wire rd_out_ltr; // force CDR to LTR mode - to RX_PMA? // new outputs for bundling and auto speed wire rd_out_rx_div2_sync_out_pipe; wire rd_out_rx_we_out_pipe; wire rd_out_wr_enable_out_pipe; wire rd_out_rd_enable_out_pipe; wire rd_out_reset_pc_ptrs_out_pipe; wire rd_out_speed_change_out_pipe; wire rd_out_dis_pc_byte; // from auto_speed_neg and feed to digi_tx wire rd_out_reset_pc_ptrs; // from auto_speed_neg and feed to digi_tx wire rd_out_pcie_switch; // ww12 interfaces -------------------------------------------------------- //feeding to cdr_ctrl and eii_module //from rev_loopbk of tx_pipe_interface; //tx_digi.rev_loopbk <= tx_pipe_interface.rev_loopback; (ww12 WYS: adding rev_loopback output port at tx_pcs) //rx_digi.pipe_loopbk <= tx_pipe_interface.rev_loopback; (ww12 WYS: adding pipe_loopback input port at rx_pcs) // parallel loopback requires 4 EIOS to be transmitted up to the upper layer. //Used in the CDR control block and electrical idle inference module wire rd_in_pipe_loopbk; // XAUI related ports // from rate_match to rate_match to achieve all channel rd/wr at same time // Full connection rx[i].cg_comp_rd_d_chj <= rx[j].cg_comp_rd_out // for Quartus simulation: using its own ptrs since we do not model delays wire rd_out_cg_comp_rd_d_out; wire rd_out_cg_comp_wr_out; wire rd_in_cg_comp_rd_d_ch0; wire rd_in_cg_comp_rd_d_ch1; wire rd_in_cg_comp_rd_d_ch2; wire rd_in_cg_comp_rd_d_ch3; wire rd_in_cg_comp_wr_ch0; wire rd_in_cg_comp_wr_ch1; wire rd_in_cg_comp_wr_ch2; wire rd_in_cg_comp_wr_ch3; // XAUI related channel 0 to rest channels in ICD // in Quartus sim: using its own ptrs wire rd_out_del_cond_met_out; wire rd_out_fifo_ovr_out; wire rd_out_latency_comp_out; wire rd_out_insert_incomplete_out; wire rd_in_del_cond_met_0; wire rd_in_fifo_ovr_0; wire rd_in_latency_comp_0; wire rd_in_insert_incomplete_0; // ww12 - splitting IQP into pipe_up/_down wire rd_out_rx_div2_sync_out_pipe_up; wire rd_out_rx_we_out_pipe_up; wire rd_out_wr_enable_out_pipe_up; wire rd_out_rd_enable_out_pipe_up; wire rd_out_reset_pc_ptrs_out_pipe_up; wire rd_out_speed_change_out_pipe_up; wire rd_out_rx_div2_sync_out_pipe_down; wire rd_out_rx_we_out_pipe_down; wire rd_out_wr_enable_out_pipe_down; wire rd_out_rd_enable_out_pipe_down; wire rd_out_reset_pc_ptrs_out_pipe_down; wire rd_out_speed_change_out_pipe_down; // ww12 - spliting inputs because tx_side's iqp output split // from corresponding tx channels output *_out_pipe wire rd_in_tx_div2_sync_out_pipe_up; wire rd_in_fifo_select_out_pipe_up; wire rd_in_tx_wr_enable_out_pipe_up; wire rd_in_tx_rd_enable_out_pipe_up; wire rd_in_tx_div2_sync_out_pipe_down; wire rd_in_fifo_select_out_pipe_down; wire rd_in_tx_wr_enable_out_pipe_down; wire rd_in_tx_rd_enable_out_pipe_down; // ww25.2008 interfaces -------------------------------------------------------- wire [69:0] rd_in_pcs_wrapback_in; //////////////////////////////////////////////////////////////////////////////// // Atom level DPRIO input CRAM ----------------------------------------------// //////////////////////////////////////////////////////////////////////////////// // Manual section wire dprioin_rpmadwidth_rx; wire dprioin_rpma_doublewidth_rx; wire dprioin_rendec_data_sel_rx; wire dprioin_rdeskewen; wire dprioin_rindv_rx; wire dprioin_rmaster_rx; wire dprioin_rmaster_up_rx; wire dprioin_rdskposdisp; wire [1:0] dprioin_dskwclksel; // not used in DPRIO wire dprioin_is_lane0; wire [1:0] dprioin_rbist_sel; wire [1:0] dprioin_rbitslip_size; wire dprioin_rclkcmppos; wire [1:0] dprioin_rcxpat_chnl_en; wire [9:0] dprioin_rdskchrp; wire dprioin_rforce0_freqdet; wire dprioin_rforce1_freqdet; wire dprioin_rphfifo_master_sel_rx; wire dprioin_rppm_cnt_reset; wire [5:0] dprioin_rppmsel; wire [2:0] dprioin_rprbs_sel; wire dprioin_rrdwidth_rx; // rx only wire dprioin_rrx_revlb_sw; wire dprioin_rs_lpbk; wire [1:0] dprioin_rtx_elec_idle_delay; // rx only wire dprioin_rtx_pipe_enable; wire dprioin_scan_mode; wire dprioin_sel_gp_md; wire dprioin_renpolinv_en; wire dprioin_rphfifourstenrx; wire dprioin_rppm_gen1_2xcnt_en; wire dprioin_rppm_post_eidle_del; wire dprioin_rrx_fifo_dis; // --------------------------------------------------------------------------- // DPRIO input CRAM // --------------------------------------------------------------------------- // PCS Per Channel RX Control Register 1 for Channel 0 wire dprioin_rrxpcsbypass_en; wire dprioin_rall_one_dect_only; wire dprioin_rbist_clr_rx; wire dprioin_rbisten_rx; wire dprioin_rprbs_clr_rslt_rx; wire dprioin_rprbsen_rx; wire dprioin_rrx_rd_clk_sel; wire [1:0] dprioin_rclk_2_sel; wire [1:0] dprioin_rclk_1_sel; wire [1:0] dprioin_rrcvd_clk_sel; wire dprioin_rfreerun_rx; wire dprioin_rrxurstpcs; wire dprioin_reserved_0_TB5; // PCS Per Channel RX Control Register 2 for Channel 0 wire dprioin_rcomp_pat_32; wire dprioin_rcomp_pat_33; wire dprioin_rcomp_pat_34; wire dprioin_rcomp_pat_35; wire dprioin_rcomp_pat_36; wire dprioin_rcomp_pat_37; wire dprioin_rcomp_pat_38; wire dprioin_rcomp_pat_39; wire [2:0] dprioin_rcomp_size; wire dprioin_rcomp_pat_porn; wire dprioin_rdis_rx_disp; wire dprioin_rencdt_rising; wire [1:0] dprioin_resync_badcg_en; // PCS Per Channel RX Control Register 3 for Channel 0 wire dprioin_rcomp_pat_16; wire dprioin_rcomp_pat_17; wire dprioin_rcomp_pat_18; wire dprioin_rcomp_pat_19; wire dprioin_rcomp_pat_20; wire dprioin_rcomp_pat_21; wire dprioin_rcomp_pat_22; wire dprioin_rcomp_pat_23; wire dprioin_rcomp_pat_24; wire dprioin_rcomp_pat_25; wire dprioin_rcomp_pat_26; wire dprioin_rcomp_pat_27; wire dprioin_rcomp_pat_28; wire dprioin_rcomp_pat_29; wire dprioin_rcomp_pat_30; wire dprioin_rcomp_pat_31; // PCS Per Channel RX Control Register 4 for Channel 0 wire dprioin_rcomp_pat_0; wire dprioin_rcomp_pat_1; wire dprioin_rcomp_pat_2; wire dprioin_rcomp_pat_3; wire dprioin_rcomp_pat_4; wire dprioin_rcomp_pat_5; wire dprioin_rcomp_pat_6; wire dprioin_rcomp_pat_7; wire dprioin_rcomp_pat_8; wire dprioin_rcomp_pat_9; wire dprioin_rcomp_pat_10; wire dprioin_rcomp_pat_11; wire dprioin_rcomp_pat_12; wire dprioin_rcomp_pat_13; wire dprioin_rcomp_pat_14; wire dprioin_rcomp_pat_15; // PCS Per Channel RX Control Register 5 for Channel 0 wire dprioin_rbitloc_rev_en; wire dprioin_rbysync_polinv_en; wire dprioin_rwa_6g_en; wire [1:0] dprioin_rosnumber; wire dprioin_rosbased; wire dprioin_rkchar; wire [5:0] dprioin_renumber; wire [1:0] dprioin_rib_inv_cd; wire dprioin_rsync_sm_dis; // PCS Per Channel RX Control Register 6 for Channel 0 wire [7:0] dprioin_rknumber; wire [7:0] dprioin_rgnumber; // PCS Per Channel RX Control Register 7 for Channel 0 wire dprioin_renpolinv_rx; wire dprioin_rcascaded_8b10b_en_rx; wire [1:0] dprioin_r8b10b_dec_ibm_en; wire dprioin_rendec_rx; wire dprioin_rautobtalg_dis; wire dprioin_rrlv_en; wire dprioin_rlp20ben; wire dprioin_rforce_sig_det_pcs; wire dprioin_rbyte_rev_en; wire [5:0] dprioin_rrundisp; // PCS Per Channel RX Control Register 8 for Channel 0 wire dprioin_rclkcmpsq1p_0; wire dprioin_rclkcmpsq1p_1; wire dprioin_rclkcmpsq1p_2; wire dprioin_rclkcmpsq1p_3; wire dprioin_rclkcmpsq1p_4; wire dprioin_rclkcmpsq1p_5; wire dprioin_rclkcmpsq1p_6; wire dprioin_rclkcmpsq1p_7; wire dprioin_rclkcmpsq1p_8; wire dprioin_rclkcmpsq1p_9; wire dprioin_rclkcmpsqmd; wire dprioin_rclkcmpinsertpad; wire dprioin_rtruebac2bac; wire dprioin_rskpsetbased; wire dprioin_rgenericfifo; wire dprioin_rmatchen; // PCS Per Channel RX Control Register 9 for Channel 0 wire dprioin_rclkcmpsq1p_10; wire dprioin_rclkcmpsq1p_11; wire dprioin_rclkcmpsq1p_12; wire dprioin_rclkcmpsq1p_13; wire dprioin_rclkcmpsq1p_14; wire dprioin_rclkcmpsq1p_15; wire dprioin_rclkcmpsq1p_16; wire dprioin_rclkcmpsq1p_17; wire dprioin_rclkcmpsq1p_18; wire dprioin_rclkcmpsq1p_19; wire dprioin_reserved_0_TB13; wire dprioin_rclkcmpsq1n_15; wire dprioin_rclkcmpsq1n_16; wire dprioin_rclkcmpsq1n_17; wire dprioin_rclkcmpsq1n_18; wire dprioin_rclkcmpsq1n_19; // PCS Per Channel RX Control Register 10 for Channel 0 wire dprioin_rclkcmpsq1n_0; wire dprioin_rclkcmpsq1n_1; wire dprioin_rclkcmpsq1n_2; wire dprioin_rclkcmpsq1n_3; wire dprioin_rclkcmpsq1n_4; wire dprioin_rclkcmpsq1n_5; wire dprioin_rclkcmpsq1n_6; wire dprioin_rclkcmpsq1n_7; wire dprioin_rclkcmpsq1n_8; wire dprioin_rclkcmpsq1n_9; wire dprioin_reserved_0_TB14; wire dprioin_rclkcmpsq1n_10; wire dprioin_rclkcmpsq1n_11; wire dprioin_rclkcmpsq1n_12; wire dprioin_rclkcmpsq1n_13; wire dprioin_rclkcmpsq1n_14; // PCS Per Channel RX Control Register 11 for Channel 0 wire [4:0] dprioin_rfull_threshold; wire [4:0] dprioin_rdel_threshold; wire [4:0] dprioin_rins_threshold; wire dprioin_rclkcmp_pipe_en; // PCS Per Channel RX Control Register 12 for Channel 0 wire dprioin_rfreq_sel; wire dprioin_rauto_speed_ena; wire dprioin_rhip_ena; wire dprioin_rpma_done_gen_ena; wire dprioin_rpma_done_count_16; wire dprioin_rpma_done_count_17; wire [3:0] dprioin_reserved_0_TB16; wire [2:0] dprioin_rstart_threshold; wire [2:0] dprioin_rempty_threshold; // PCS Per Channel RX Control Register 13 for Channel 0 wire [3:0] dprioin_rtest_bus_sel; wire dprioin_rautoinsdis; wire dprioin_rphfifopldenrx; wire dprioin_rbytordplden; wire [1:0] dprioin_rbyteorden; wire dprioin_rbytord_2sym_en; wire dprioin_rinvalid_code_err_only; wire dprioin_rcmpfifourst; wire dprioin_rphfifourstrx; wire dprioin_rdwidth_rx; wire dprioin_rrxfifo_lowlatency_en; wire dprioin_rrxfifo_dis; // PCS Per Channel RX Control Register 14 for Channel 0 wire dprioin_rbytordpat_0; wire dprioin_rbytordpat_1; wire dprioin_rbytordpat_2; wire dprioin_rbytordpat_3; wire dprioin_rbytordpat_4; wire dprioin_rbytordpat_5; wire dprioin_rbytordpat_6; wire dprioin_rbytordpat_7; wire dprioin_rbytordpat_8; wire dprioin_rbytordpat_9; wire [5:0] dprioin_reserved_0_TB18; // PCS Per Channel RX Control Register 15 for Channel 0 wire [9:0] dprioin_rbytordpad; wire [5:0] dprioin_reserved_0_TB19; // PCS Per Channel RX Control Register 16 for Channel 0 wire [4:0] dprioin_rload_shreg_del; wire dprioin_rphystatus_rst_toggle; wire [1:0] dprioin_reidle_com_detect; wire dprioin_rk285detect; wire dprioin_reidleinferenable; wire [2:0] dprioin_rphystatus_delay; wire dprioin_rind_error_reporting; wire dprioin_rrx_detect_bypass; wire dprioin_rrx_pipe_enable; // PCS Per Channel RX Control Register 17 for Channel 0 wire dprioin_rpma_done_count_0; wire dprioin_rpma_done_count_1; wire dprioin_rpma_done_count_2; wire dprioin_rpma_done_count_3; wire dprioin_rpma_done_count_4; wire dprioin_rpma_done_count_5; wire dprioin_rpma_done_count_6; wire dprioin_rpma_done_count_7; wire dprioin_rpma_done_count_8; wire dprioin_rpma_done_count_9; wire dprioin_rpma_done_count_10; wire dprioin_rpma_done_count_11; wire dprioin_rpma_done_count_12; wire dprioin_rpma_done_count_13; wire dprioin_rpma_done_count_14; wire dprioin_rpma_done_count_15; // PCS Per Channel RX Control Register 18 for Channel 0 wire dprioin_rbytordpat_10; wire dprioin_rbytordpat_11; wire dprioin_rbytordpat_12; wire dprioin_rbytordpat_13; wire dprioin_rbytordpat_14; wire dprioin_rbytordpat_15; wire dprioin_rbytordpat_16; wire dprioin_rbytordpat_17; wire dprioin_rbytordpat_18; wire dprioin_rbytordpat_19; wire dprioin_rbytord_6g_mask_en; wire dprioin_rbytord_s2gx; wire dprioin_reserved_0_TB22; wire dprioin_rcdr_ctrl_en; wire dprioin_rrxpcsclkpwdn; wire dprioin_rerr_flags_sel; // PCS Per Channel RX Control Register 19 for Channel 0 wire [7:0] dprioin_rwait_count; wire [7:0] dprioin_reserved_0_TB23; // PCS Per Channel RX Control Register 20 for Channel 0 wire [9:0] dprioin_rfts_count; wire [5:0] dprioin_rwait_for_phfifo_cnt; // PCS Per Channel RX Control Register 21 for Channel 0 wire dprioin_rppm_meas_delay; wire [7:0] dprioin_rcid_len_rx; wire dprioin_rcid_pattern_rx; wire dprioin_rpcs_wrapback_en; wire [4:0] dprioin_reserved_0_TB25; // PCS Per Channel RX Control Register 22 for Channel 0 wire [4:0] dprioin_rauto_pc_en_cnt; wire dprioin_reserved_1_TB26; wire [3:0] dprioin_rauto_deassert_pc_rst_cnt; wire dprioin_reserved_0_TB26; wire dprioin_rpipeline_bypass_rx; wire dprioin_rself_sw_en_rx; wire dprioin_rrxvalid_mask; wire dprioin_rcid_en; wire dprioin_rphfifo_regmode_rx; // PCS Per Channel RX Control Register 23 for Channel 0 wire [9:0] dprioin_rmask_count; wire dprioin_rgen1_sigdet_ena; wire dprioin_riei_eios_priority_dis; wire [3:0] dprioin_reserved_0_TB27; //////////////////////////////////////////////////////////////////////////////// // Final CRAM to pass to RTL ------------------------------------------------// //////////////////////////////////////////////////////////////////////////////// // Manual section wire cram_rpmadwidth_rx; wire cram_rpma_doublewidth_rx; wire cram_rendec_data_sel_rx; wire cram_rdeskewen; wire cram_rindv_rx; wire cram_rdskposdisp; wire cram_rmaster_rx; wire cram_rmaster_up_rx; wire [1:0] cram_dskwclksel; // not used in DPRIO wire cram_is_lane0; wire [1:0] cram_rbist_sel; wire [1:0] cram_rbitslip_size; wire cram_rclkcmppos; wire [1:0] cram_rcxpat_chnl_en; wire [9:0] cram_rdskchrp; wire cram_rforce0_freqdet; wire cram_rforce1_freqdet; wire cram_rphfifo_master_sel_rx; wire cram_rppm_cnt_reset; wire [5:0] cram_rppmsel; wire [2:0] cram_rprbs_sel; wire cram_rrdwidth_rx; // rx only wire cram_rrx_revlb_sw; wire cram_rs_lpbk; wire [1:0] cram_rtx_elec_idle_delay; // rx only wire cram_rtx_pipe_enable; wire cram_scan_mode; wire cram_sel_gp_md; wire cram_renpolinv_en; wire cram_rphfifourstenrx; wire cram_rppm_gen1_2xcnt_en; wire cram_rppm_post_eidle_del; wire cram_rrx_fifo_dis; // PCS Per Channel RX Control Register 1 for Channel 0 wire cram_rrxpcsbypass_en; wire cram_rall_one_dect_only; wire cram_rbist_clr_rx; wire cram_rbisten_rx; wire cram_rprbs_clr_rslt_rx; wire cram_rprbsen_rx; wire cram_rrx_rd_clk_sel; wire [1:0] cram_rclk_2_sel; wire [1:0] cram_rclk_1_sel; wire [1:0] cram_rrcvd_clk_sel; wire cram_rfreerun_rx; wire cram_rrxurstpcs; wire cram_reserved_0_TB5; // PCS Per Channel RX Control Register 2 for Channel 0 wire cram_rcomp_pat_32; wire cram_rcomp_pat_33; wire cram_rcomp_pat_34; wire cram_rcomp_pat_35; wire cram_rcomp_pat_36; wire cram_rcomp_pat_37; wire cram_rcomp_pat_38; wire cram_rcomp_pat_39; wire [2:0] cram_rcomp_size; wire cram_rcomp_pat_porn; wire cram_rdis_rx_disp; wire cram_rencdt_rising; wire [1:0] cram_resync_badcg_en; // PCS Per Channel RX Control Register 3 for Channel 0 wire cram_rcomp_pat_16; wire cram_rcomp_pat_17; wire cram_rcomp_pat_18; wire cram_rcomp_pat_19; wire cram_rcomp_pat_20; wire cram_rcomp_pat_21; wire cram_rcomp_pat_22; wire cram_rcomp_pat_23; wire cram_rcomp_pat_24; wire cram_rcomp_pat_25; wire cram_rcomp_pat_26; wire cram_rcomp_pat_27; wire cram_rcomp_pat_28; wire cram_rcomp_pat_29; wire cram_rcomp_pat_30; wire cram_rcomp_pat_31; // PCS Per Channel RX Control Register 4 for Channel 0 wire cram_rcomp_pat_0; wire cram_rcomp_pat_1; wire cram_rcomp_pat_2; wire cram_rcomp_pat_3; wire cram_rcomp_pat_4; wire cram_rcomp_pat_5; wire cram_rcomp_pat_6; wire cram_rcomp_pat_7; wire cram_rcomp_pat_8; wire cram_rcomp_pat_9; wire cram_rcomp_pat_10; wire cram_rcomp_pat_11; wire cram_rcomp_pat_12; wire cram_rcomp_pat_13; wire cram_rcomp_pat_14; wire cram_rcomp_pat_15; wire [39:0] cram_rcomp_pat; assign cram_rcomp_pat = {cram_rcomp_pat_39, cram_rcomp_pat_38, cram_rcomp_pat_37, cram_rcomp_pat_36, cram_rcomp_pat_35, cram_rcomp_pat_34, cram_rcomp_pat_33, cram_rcomp_pat_32, cram_rcomp_pat_31, cram_rcomp_pat_30, cram_rcomp_pat_29, cram_rcomp_pat_28, cram_rcomp_pat_27, cram_rcomp_pat_26, cram_rcomp_pat_25, cram_rcomp_pat_24, cram_rcomp_pat_23, cram_rcomp_pat_22, cram_rcomp_pat_21, cram_rcomp_pat_20, cram_rcomp_pat_19, cram_rcomp_pat_18, cram_rcomp_pat_17, cram_rcomp_pat_16, cram_rcomp_pat_15, cram_rcomp_pat_14, cram_rcomp_pat_13, cram_rcomp_pat_12, cram_rcomp_pat_11, cram_rcomp_pat_10, cram_rcomp_pat_9, cram_rcomp_pat_8, cram_rcomp_pat_7, cram_rcomp_pat_6, cram_rcomp_pat_5, cram_rcomp_pat_4, cram_rcomp_pat_3, cram_rcomp_pat_2, cram_rcomp_pat_1, cram_rcomp_pat_0}; // PCS Per Channel RX Control Register 5 for Channel 0 wire cram_rbitloc_rev_en; wire cram_rbysync_polinv_en; wire cram_rwa_6g_en; wire [1:0] cram_rosnumber; wire cram_rosbased; wire cram_rkchar; wire [5:0] cram_renumber; wire [1:0] cram_rib_inv_cd; wire cram_rsync_sm_dis; // PCS Per Channel RX Control Register 6 for Channel 0 wire [7:0] cram_rknumber; wire [7:0] cram_rgnumber; // PCS Per Channel RX Control Register 7 for Channel 0 wire cram_renpolinv_rx; wire cram_rcascaded_8b10b_en_rx; wire [1:0] cram_r8b10b_dec_ibm_en; wire cram_rendec_rx; wire cram_rautobtalg_dis; wire cram_rrlv_en; wire cram_rlp20ben; wire cram_rforce_sig_det_pcs; wire cram_rbyte_rev_en; wire [5:0] cram_rrundisp; // PCS Per Channel RX Control Register 8 for Channel 0 wire cram_rclkcmpsq1p_0; wire cram_rclkcmpsq1p_1; wire cram_rclkcmpsq1p_2; wire cram_rclkcmpsq1p_3; wire cram_rclkcmpsq1p_4; wire cram_rclkcmpsq1p_5; wire cram_rclkcmpsq1p_6; wire cram_rclkcmpsq1p_7; wire cram_rclkcmpsq1p_8; wire cram_rclkcmpsq1p_9; wire cram_rclkcmpsqmd; wire cram_rclkcmpinsertpad; wire cram_rtruebac2bac; wire cram_rskpsetbased; wire cram_rgenericfifo; wire cram_rmatchen; // PCS Per Channel RX Control Register 9 for Channel 0 wire cram_rclkcmpsq1p_10; wire cram_rclkcmpsq1p_11; wire cram_rclkcmpsq1p_12; wire cram_rclkcmpsq1p_13; wire cram_rclkcmpsq1p_14; wire cram_rclkcmpsq1p_15; wire cram_rclkcmpsq1p_16; wire cram_rclkcmpsq1p_17; wire cram_rclkcmpsq1p_18; wire cram_rclkcmpsq1p_19; wire cram_reserved_0_TB13; wire cram_rclkcmpsq1n_15; wire cram_rclkcmpsq1n_16; wire cram_rclkcmpsq1n_17; wire cram_rclkcmpsq1n_18; wire cram_rclkcmpsq1n_19; wire [19:0] cram_rclkcmpsq1p; assign cram_rclkcmpsq1p = {cram_rclkcmpsq1p_19, cram_rclkcmpsq1p_18, cram_rclkcmpsq1p_17, cram_rclkcmpsq1p_16, cram_rclkcmpsq1p_15, cram_rclkcmpsq1p_14, cram_rclkcmpsq1p_13, cram_rclkcmpsq1p_12, cram_rclkcmpsq1p_11, cram_rclkcmpsq1p_10, cram_rclkcmpsq1p_9, cram_rclkcmpsq1p_8, cram_rclkcmpsq1p_7, cram_rclkcmpsq1p_6, cram_rclkcmpsq1p_5, cram_rclkcmpsq1p_4, cram_rclkcmpsq1p_3, cram_rclkcmpsq1p_2, cram_rclkcmpsq1p_1, cram_rclkcmpsq1p_0}; // PCS Per Channel RX Control Register 10 for Channel 0 wire cram_rclkcmpsq1n_0; wire cram_rclkcmpsq1n_1; wire cram_rclkcmpsq1n_2; wire cram_rclkcmpsq1n_3; wire cram_rclkcmpsq1n_4; wire cram_rclkcmpsq1n_5; wire cram_rclkcmpsq1n_6; wire cram_rclkcmpsq1n_7; wire cram_rclkcmpsq1n_8; wire cram_rclkcmpsq1n_9; wire cram_reserved_0_TB14; wire cram_rclkcmpsq1n_10; wire cram_rclkcmpsq1n_11; wire cram_rclkcmpsq1n_12; wire cram_rclkcmpsq1n_13; wire cram_rclkcmpsq1n_14; wire [19:0] cram_rclkcmpsq1n; assign cram_rclkcmpsq1n = {cram_rclkcmpsq1n_19, cram_rclkcmpsq1n_18, cram_rclkcmpsq1n_17, cram_rclkcmpsq1n_16, cram_rclkcmpsq1n_15, cram_rclkcmpsq1n_14, cram_rclkcmpsq1n_13, cram_rclkcmpsq1n_12, cram_rclkcmpsq1n_11, cram_rclkcmpsq1n_10, cram_rclkcmpsq1n_9, cram_rclkcmpsq1n_8, cram_rclkcmpsq1n_7, cram_rclkcmpsq1n_6, cram_rclkcmpsq1n_5, cram_rclkcmpsq1n_4, cram_rclkcmpsq1n_3, cram_rclkcmpsq1n_2, cram_rclkcmpsq1n_1, cram_rclkcmpsq1n_0}; // PCS Per Channel RX Control Register 11 for Channel 0 wire [4:0] cram_rfull_threshold; wire [4:0] cram_rdel_threshold; wire [4:0] cram_rins_threshold; wire cram_rclkcmp_pipe_en; // PCS Per Channel RX Control Register 12 for Channel 0 wire cram_rfreq_sel; wire cram_rauto_speed_ena; wire cram_rhip_ena; wire cram_rpma_done_gen_ena; wire cram_rpma_done_count_16; wire cram_rpma_done_count_17; wire [3:0] cram_reserved_0_TB16; wire [2:0] cram_rstart_threshold; wire [2:0] cram_rempty_threshold; // PCS Per Channel RX Control Register 13 for Channel 0 wire [3:0] cram_rtest_bus_sel; wire cram_rautoinsdis; wire cram_rphfifopldenrx; wire cram_rbytordplden; wire [1:0] cram_rbyteorden; wire cram_rbytord_2sym_en; wire cram_rinvalid_code_err_only; wire cram_rcmpfifourst; wire cram_rphfifourstrx; wire cram_rdwidth_rx; wire cram_rrxfifo_lowlatency_en; wire cram_rrxfifo_dis; // PCS Per Channel RX Control Register 14 for Channel 0 wire cram_rbytordpat_0; wire cram_rbytordpat_1; wire cram_rbytordpat_2; wire cram_rbytordpat_3; wire cram_rbytordpat_4; wire cram_rbytordpat_5; wire cram_rbytordpat_6; wire cram_rbytordpat_7; wire cram_rbytordpat_8; wire cram_rbytordpat_9; wire [5:0] cram_reserved_0_TB18; // PCS Per Channel RX Control Register 15 for Channel 0 wire [9:0] cram_rbytordpad; wire [5:0] cram_reserved_0_TB19; // PCS Per Channel RX Control Register 16 for Channel 0 wire [4:0] cram_rload_shreg_del; wire cram_rphystatus_rst_toggle; wire [1:0] cram_reidle_com_detect; wire cram_rk285detect; wire cram_reidleinferenable; wire [2:0] cram_rphystatus_delay; wire cram_rind_error_reporting; wire cram_rrx_detect_bypass; wire cram_rrx_pipe_enable; // PCS Per Channel RX Control Register 17 for Channel 0 wire cram_rpma_done_count_0; wire cram_rpma_done_count_1; wire cram_rpma_done_count_2; wire cram_rpma_done_count_3; wire cram_rpma_done_count_4; wire cram_rpma_done_count_5; wire cram_rpma_done_count_6; wire cram_rpma_done_count_7; wire cram_rpma_done_count_8; wire cram_rpma_done_count_9; wire cram_rpma_done_count_10; wire cram_rpma_done_count_11; wire cram_rpma_done_count_12; wire cram_rpma_done_count_13; wire cram_rpma_done_count_14; wire cram_rpma_done_count_15; wire [17:0] cram_rpma_done_count; assign cram_rpma_done_count = {cram_rpma_done_count_17, cram_rpma_done_count_16, cram_rpma_done_count_15, cram_rpma_done_count_14, cram_rpma_done_count_13, cram_rpma_done_count_12, cram_rpma_done_count_11, cram_rpma_done_count_10, cram_rpma_done_count_9, cram_rpma_done_count_8, cram_rpma_done_count_7, cram_rpma_done_count_6, cram_rpma_done_count_5, cram_rpma_done_count_4, cram_rpma_done_count_3, cram_rpma_done_count_2, cram_rpma_done_count_1, cram_rpma_done_count_0}; // PCS Per Channel RX Control Register 18 for Channel 0 wire cram_rbytordpat_10; wire cram_rbytordpat_11; wire cram_rbytordpat_12; wire cram_rbytordpat_13; wire cram_rbytordpat_14; wire cram_rbytordpat_15; wire cram_rbytordpat_16; wire cram_rbytordpat_17; wire cram_rbytordpat_18; wire cram_rbytordpat_19; wire cram_rbytord_6g_mask_en; wire cram_rbytord_s2gx; wire cram_reserved_0_TB22; wire cram_rcdr_ctrl_en; wire cram_rrxpcsclkpwdn; wire cram_rerr_flags_sel; wire [19:0] cram_rbytordpat; assign cram_rbytordpat = {cram_rbytordpat_19, cram_rbytordpat_18, cram_rbytordpat_17, cram_rbytordpat_16, cram_rbytordpat_15, cram_rbytordpat_14, cram_rbytordpat_13, cram_rbytordpat_12, cram_rbytordpat_11, cram_rbytordpat_10, cram_rbytordpat_9, cram_rbytordpat_8, cram_rbytordpat_7, cram_rbytordpat_6, cram_rbytordpat_5, cram_rbytordpat_4, cram_rbytordpat_3, cram_rbytordpat_2, cram_rbytordpat_1, cram_rbytordpat_0}; // PCS Per Channel RX Control Register 19 for Channel 0 wire [7:0] cram_rwait_count; wire [7:0] cram_reserved_0_TB23; // PCS Per Channel RX Control Register 20 for Channel 0 wire [9:0] cram_rfts_count; wire [5:0] cram_rwait_for_phfifo_cnt; // PCS Per Channel RX Control Register 21 for Channel 0 wire cram_rppm_meas_delay; wire [7:0] cram_rcid_len_rx; wire cram_rcid_pattern_rx; wire cram_rpcs_wrapback_en; wire [4:0] cram_reserved_0_TB25; // PCS Per Channel RX Control Register 22 for Channel 0 wire [4:0] cram_rauto_pc_en_cnt; wire cram_reserved_1_TB26; wire [3:0] cram_rauto_deassert_pc_rst_cnt; wire cram_reserved_0_TB26; wire cram_rpipeline_bypass_rx; wire cram_rself_sw_en_rx; wire cram_rrxvalid_mask; wire cram_rcid_en; wire cram_rphfifo_regmode_rx; // PCS Per Channel RX Control Register 23 for Channel 0 wire [9:0] cram_rmask_count; wire cram_rgen1_sigdet_ena; wire cram_riei_eios_priority_dis; wire [3:0] cram_reserved_0_TB27; //////////////////////////////////////////////////////////////////////////////// // Internal Variables -------------------------------------------------------// //////////////////////////////////////////////////////////////////////////////// integer i; integer j; reg [39:0] tmp_reg40; reg [2:0] tmp_rcomp_size; //////////////////////////////////////////////////////////////////////////////// // Internal Functions -------------------------------------------------------// //////////////////////////////////////////////////////////////////////////////// // function to convert at most 40-bit long string to binary function [39 : 0] m_str_to_bin; input [40*8 : 1] s; reg [40*8 : 1] reg_s; reg [7 : 0] tmp; reg [40:1] res; integer m; begin reg_s = s; for (m = 40; m > 0; m = m-1 ) begin tmp = reg_s[320 : 313]; res[m] = tmp & 8'b00000001; reg_s = reg_s << 8; end m_str_to_bin = res; end endfunction function [2:0] compute_rprbs_sel_rx; input pma_doublewidth; input pma_width; input test_mode; reg [8*20:1] test_mode; reg [2:0] res; begin case ({pma_doublewidth, pma_width}) 2'b00 : begin if (test_mode == "prbs_8" || test_mode == "prbs8") res = 3'b000; else if (test_mode == "prbs7") res = 3'b010; else if (test_mode == "prbs23") res = 3'b100; else if (test_mode == "high frequency") res = 3'b001; else res = 3'b000; // default end 2'b01 : begin if (test_mode == "prbs_10" || test_mode == "prbs10") res = 3'b000; else if (test_mode == "high frequency") res = 3'b001; else if (test_mode == "low frequency") res = 3'b010; else if (test_mode == "mixed frequency") res = 3'b011; else res = 3'b000; // default end 2'b10 : begin if (test_mode == "prbs_7" || test_mode == "prbs7") res = 3'b000; else if (test_mode == "prbs_23" || test_mode == "prbs23") res = 3'b001; else if (test_mode == "high frequency") res = 3'b010; else res = 3'b000; // default end 2'b11 : begin if (test_mode == "prbs_7" || test_mode == "prbs7") res = 3'b000; else if (test_mode == "prbs_23" || test_mode == "prbs23") res = 3'b001; else if (test_mode == "high frequency") res = 3'b010; else if (test_mode == "low frequency") res = 3'b011; else if (test_mode == "mixed frequency") res = 3'b100; else res = 3'b000; // default end default : begin $display("Invalid pma_doublewidth and pma_width selection"); $display("Time: %0t Instance: %m", $time); end endcase compute_rprbs_sel_rx = res; end endfunction function [5:0] compute_rrundisp; input pma_doublewidth; input pma_width; input run_len; integer run_len; // without this - it is assumed 1 bit. integer run_len_stepped; reg [5:0] res; begin case ({pma_doublewidth, pma_width}) // 8-bit 2'b00 : begin run_len_stepped = run_len / 4; if (run_len_stepped == 32) res = 6'b000000; else res = run_len_stepped; end 2'b01 : // 10-bit begin run_len_stepped = run_len / 5; if (run_len_stepped == 32) res = 6'b000000; else res = run_len_stepped; end 2'b10 : // 16-bit begin run_len_stepped = run_len / 8; if (run_len_stepped == 64) res = 6'b000000; else res = run_len_stepped; end 2'b11 : // 20-bit begin run_len_stepped = run_len / 10; if (run_len_stepped == 64) res = 6'b000000; else res = run_len_stepped; end default : begin $display("Invalid pma_doublewidth and pma_width selection"); $display("Time: %0t Instance: %m", $time); end endcase compute_rrundisp = res; end endfunction //////////////////////////////////////////////////////////////////////////////// // INPUT FILTERING ----------------------------------------------------------// //////////////////////////////////////////////////////////////////////////////// wire a1a2size_in; wire alignstatus_in; wire alignstatussync_in; wire bitslip_in; wire coreclk_in; wire [19:0] datain_in; //NEW: updated width wire digitalreset_in; wire [399:0] dprioin_in; // tmp width wire [2:0] elecidleinfersel_in; wire enabledeskew_in; wire enabyteord_in; wire enapatternalign_in; wire fifordin_in; wire fiforesetrd_in; wire invpol_in; wire localrefclk_in; wire masterclk_in; wire [19:0] parallelfdbk_in; wire phfifordenable_in; wire phfiforeset_in; wire phfifowrdisable_in; wire phfifox4bytesel_in; wire phfifox4rdenable_in; wire phfifox4wrclk_in; wire phfifox4wrenable_in; wire phfifox8bytesel_in; wire phfifox8rdenable_in; wire phfifox8wrclk_in; wire phfifox8wrenable_in; wire pipe8b10binvpolarity_in; wire [1:0] pipepowerdown_in; wire [3:0] pipepowerstate_in; wire ppmdetectdividedclk_in; wire ppmdetectrefclk_in; wire quadreset_in; wire rateswitch_in; wire rateswitchisdone_in; wire rateswitchxndone_in; wire recoveredclk_in; wire refclk_in; wire revbitorderwa_in; wire revbyteorderwa_in; wire rmfifordena_in; wire rmfiforeset_in; wire rmfifowrena_in; wire rxdetectvalid_in; wire rxelecidlerateswitch_in; wire [1:0] rxfound_in; wire signaldetected_in; wire xgmctrlin_in; wire [7:0] xgmdatain_in; //54 ins --- wire [2 : 0] autospdxnconfigsel_in; // config_sel_centrl, quad_up, quad_down wire [2 : 0] autospdxnspdchg_in; // From CMU.spped-change_centrl, rx3(up), rx0(down) wire cdrctrllocktorefcl_in; // pld_ltr wire hip8b10binvpolarity_in; // hip_rxpolarity wire [2 : 0] hipelecidleinfersel_in; // hip_eidleinfersel_ch wire [1 : 0] hippowerdown_in; // hip_powerdown_ch wire hiprateswitch_in; // hip_rate wire [1 : 0] iqpautospdxnspgchg_in; // speed_change_in_pipe_quad_up, down wire [1 : 0] iqpphfifoxnbytesel_in; // wr_enable_ptrs_in_pipe_quad_up, down wire [1 : 0] iqpphfifoxnptrsreset_in; // reset_pc_ptrs_in_pipe_quad_up, down wire [1 : 0] iqpphfifoxnrdenable_in; // rd_enable_ptrs_in_pipe_quad_up, down wire [1 : 0] iqpphfifoxnwrclk_in; // rx_div2_sync_in_pipe_quad_up, down wire [1 : 0] iqpphfifoxnwrenable_in; // wr_enable_ptrs_in_pipe_quad_up, down wire [2 : 0] phfifoxnbytesel_in; // rx_we_in_centrl, quad_up, quad_down wire [2 : 0] phfifoxnptrsreset_in; // ph fifo. From CMU to both RX & TX. wire [2 : 0] phfifoxnrdenable_in; // rd_enable_in_centrl, quad_up, quad_down wire [2 : 0] phfifoxnwrclk_in; // ph fifo. From CMU to RX. wire [2 : 0] phfifoxnwrenable_in; // wr_enable_in_centrl, quad_up, quad_down wire [1 : 0] powerdn_in; wire prbscidenable_in; // prbs_cid_en wire [2 : 0] grayelecidleinferselfromtx_in; wire pipeenrevparallellpbkfromtx_in; assign a1a2size_in = (a1a2size === 1'b1) ? 1'b1 : 1'b0; assign alignstatus_in = (alignstatus === 1'b1) ? 1'b1 : 1'b0; assign alignstatussync_in = (alignstatussync === 1'b1) ? 1'b1 : 1'b0; assign bitslip_in = (bitslip === 1'b1) ? 1'b1 : 1'b0; assign coreclk_in = (coreclk === 1'b1) ? 1'b1 : 1'b0; assign datain_in = datain; //NEW: updated width assign digitalreset_in = (digitalreset === 1'b1) ? 1'b1 : 1'b0; assign dprioin_in = dprioin; assign elecidleinfersel_in= (elecidleinfersel === 1'b1)? 1'b1 : 1'b0; assign enabledeskew_in = (enabledeskew === 1'b1) ? 1'b1 : 1'b0; assign enabyteord_in = (enabyteord === 1'b1) ? 1'b1 : 1'b0; assign enapatternalign_in = (enapatternalign === 1'b1) ? 1'b1 : 1'b0; assign fifordin_in = (fifordin === 1'b1) ? 1'b1 : 1'b0; assign fiforesetrd_in = (fiforesetrd === 1'b1) ? 1'b1 : 1'b0; assign invpol_in = (invpol === 1'b1) ? 1'b1 : 1'b0; assign localrefclk_in = (localrefclk === 1'b1) ? 1'b1 : 1'b0; assign masterclk_in = (masterclk === 1'b1) ? 1'b1 : 1'b0; assign parallelfdbk_in = parallelfdbk; assign phfifordenable_in = (phfifordenable === 1'b0) ? 1'b0 : 1'b1; // default enable assign phfiforeset_in = (phfiforeset === 1'b1) ? 1'b1 : 1'b0; assign phfifowrdisable_in = (phfifowrdisable === 1'b1) ? 1'b1 : 1'b0; // default enable assign phfifox4bytesel_in = (phfifox4bytesel === 1'b1) ? 1'b1 : 1'b0; assign phfifox4rdenable_in = (phfifox4rdenable === 1'b1)? 1'b1 : 1'b0; assign phfifox4wrclk_in = (phfifox4wrclk === 1'b1) ? 1'b1 : 1'b0; assign phfifox4wrenable_in = (phfifox4wrenable === 1'b1) ? 1'b1 : 1'b0; assign phfifox8bytesel_in = (phfifox8bytesel === 1'b1) ? 1'b1 : 1'b0; assign phfifox8rdenable_in = (phfifox8rdenable === 1'b1) ? 1'b1 : 1'b0; assign phfifox8wrclk_in = (phfifox8wrclk === 1'b1) ? 1'b1 : 1'b0; assign phfifox8wrenable_in = (phfifox8wrenable === 1'b1) ? 1'b1 : 1'b0; assign pipe8b10binvpolarity_in = (pipe8b10binvpolarity === 1'b1) ? 1'b1 : 1'b0; assign pipepowerdown_in = pipepowerdown; assign pipepowerstate_in = pipepowerstate; assign ppmdetectdividedclk_in = (ppmdetectdividedclk === 1'b1) ? 1'b1 : 1'b0; assign ppmdetectrefclk_in = (ppmdetectrefclk === 1'b1) ? 1'b1 : 1'b0; assign quadreset_in = (quadreset === 1'b1) ? 1'b1 : 1'b0; assign rateswitch_in = (rateswitch === 1'b1) ? 1'b1 : 1'b0; assign rateswitchisdone_in = (rateswitchisdone === 1'b1) ? 1'b1 : 1'b0; assign rateswitchxndone_in = (rateswitchxndone === 1'b1) ? 1'b1 : 1'b0; assign recoveredclk_in = (recoveredclk === 1'b1) ? 1'b1 : 1'b0; assign refclk_in = (refclk === 1'b1) ? 1'b1 : 1'b0; assign revbitorderwa_in = (revbitorderwa === 1'b1) ? 1'b1 : 1'b0; assign revbyteorderwa_in = (revbyteorderwa === 1'b1) ? 1'b1 : 1'b0; assign rmfifordena_in = (rmfifordena === 1'b1) ? 1'b1 : 1'b0; assign rmfiforeset_in = (rmfiforeset === 1'b1) ? 1'b1 : 1'b0; assign rmfifowrena_in = (rmfifowrena === 1'b1) ? 1'b1 : 1'b0; assign rxdetectvalid_in = (rxdetectvalid === 1'b1) ? 1'b1 : 1'b0; assign rxelecidlerateswitch_in = (rxelecidlerateswitch === 1'b1) ? 1'b1 : 1'b0; assign rxfound_in = rxfound; assign signaldetected_in = (signaldetected === 1'b1) ? 1'b1 : 1'b0; assign xgmctrlin_in = (xgmctrlin === 1'b1) ? 1'b1 : 1'b0; assign xgmdatain_in = xgmdatain; assign autospdxnconfigsel_in = autospdxnconfigsel; assign autospdxnspdchg_in = autospdxnspdchg; assign cdrctrllocktorefcl_in = cdrctrllocktorefcl; assign hip8b10binvpolarity_in = hip8b10binvpolarity; assign hipelecidleinfersel_in = hipelecidleinfersel; assign hippowerdown_in = hippowerdown; assign hiprateswitch_in = hiprateswitch; assign iqpautospdxnspgchg_in = iqpautospdxnspgchg; assign iqpphfifoxnbytesel_in = iqpphfifoxnbytesel; assign iqpphfifoxnptrsreset_in = iqpphfifoxnptrsreset; assign iqpphfifoxnrdenable_in = iqpphfifoxnrdenable; assign iqpphfifoxnwrclk_in = iqpphfifoxnwrclk; assign iqpphfifoxnwrenable_in = iqpphfifoxnwrenable; assign phfifoxnbytesel_in = phfifoxnbytesel; assign phfifoxnptrsreset_in = phfifoxnptrsreset; assign phfifoxnrdenable_in = phfifoxnrdenable; assign phfifoxnwrclk_in = phfifoxnwrclk; assign phfifoxnwrenable_in = phfifoxnwrenable; assign powerdn_in = powerdn; assign prbscidenable_in = prbscidenable; assign grayelecidleinferselfromtx_in[0] = (grayelecidleinferselfromtx[0] === 1'b1) ? 1'b1 : 1'b0; assign grayelecidleinferselfromtx_in[1] = (grayelecidleinferselfromtx[1] === 1'b1) ? 1'b1 : 1'b0; assign grayelecidleinferselfromtx_in[2] = (grayelecidleinferselfromtx[2] === 1'b1) ? 1'b1 : 1'b0; assign pipeenrevparallellpbkfromtx_in = (pipeenrevparallellpbkfromtx === 1'b1) ? 1'b1 : 1'b0; //////////////////////////////////////////////////////////////////////////////// // TIMING -- TCO/TSU/HOLD // //////////////////////////////////////////////////////////////////////////////// specify (posedge coreclk => (a1a2sizeout +: a1a2sizeout_reg)) = (0, 0); (posedge coreclk => (ctrldetect +: ctrldetect_reg)) = (0, 0); (posedge coreclk => (dataout +: dataout_reg)) = (0, 0); (posedge coreclk => (disperr +: disperr_reg)) = (0, 0); (posedge coreclk => (errdetect +: errdetect_reg)) = (0, 0); (posedge coreclk => (patterndetect +: patterndetect_reg)) = (0, 0); (posedge coreclk => (rmfifodatadeleted +: rmfifodatadeleted_reg)) = (0, 0); (posedge coreclk => (rmfifodatainserted +: rmfifodatainserted_reg))= (0, 0); (posedge coreclk => (runningdisp +: runningdisp_reg)) = (0, 0); (posedge coreclk => (syncstatus +: syncstatus_reg)) = (0, 0); (posedge coreclk => (pipebufferstat[0] +: rd_out_rxd[13])) = (0, 0); (posedge coreclk => (pipebufferstat[1] +: rd_out_rxd[14])) = (0, 0); (posedge coreclk => (pipebufferstat[2] +: rd_out_rxd[45])) = (0, 0); (posedge coreclk => (pipebufferstat[3] +: rd_out_rxd[46])) = (0, 0); (posedge coreclk => (byteorderalignstatus +: rd_out_byteord_flag))= (0, 0); (posedge coreclk => (phfifooverflow +: rd_out_full_rx)) = (0, 0); (posedge coreclk => (phfifounderflow +: rd_out_empty_rx)) = (0, 0); (posedge coreclk => (pipestatus +: hs_out_rxstatus_ch)) = (0, 0); (posedge coreclk => (pipephydonestatus +: hs_out_phystatus)) = (0, 0); (posedge coreclk => (pipedatavalid +: hs_out_rxvalid)) = (0, 0); $setuphold(posedge coreclk, phfifordenable, 0, 0); endspecify //////////////////////////////////////////////////////////////////////////////// // dprio outputs // //////////////////////////////////////////////////////////////////////////////// //wire [399:0] wire_dprioout; //////////////////////////////////////////////////////////////////////////////// // inital CRAMs from parameters - CRAM_TABLE 1 ------------------------------// //////////////////////////////////////////////////////////////////////////////// initial begin // Existing // moved up as they can be used by other parameter initialization init_rpma_doublewidth_rx = (use_deserializer_double_data_mode == "true") ? 1'b1 : 1'b0; init_rpmadwidth_rx = ((dec_8b_10b_mode == "none") && ((channel_width == 8) || (channel_width == 16) || (channel_width == 32))) ? 1'b0 : 1'b1; // 0 = 8 bit, 1 = 10 bit; init_rdeskewen = (use_deskew_fifo == "true") ? 1'b1 : 1'b0; init_dskwclksel[1] = (use_deskew_fifo == "true") ? 1'b1 : 1'b0; init_dskwclksel[0] = 1'b0; init_is_lane0 = (channel_number == 0) ? 1'b1 : 1'b0; init_rbist_sel = (self_test_mode == "cjpat") ? 2'b01 : (self_test_mode == "crpat") ? 2'b10 : 2'b00; init_rcxpat_chnl_en = (channel_number == 1) ? 2'b01 : // bist_gen (channel_number == 2) ? 2'b10 : (channel_number == 3) ? 2'b11 : 2'b00; tmp_reg40 = m_str_to_bin(deskew_pattern); // must move this to exiting section as well init_rdskchrp = tmp_reg40[9:0]; // convert deskew_pattern init_rdskposdisp = (align_to_deskew_pattern_pos_disp_only == "true") ? 1'b1 : 1'b0; init_rendec_data_sel_rx = (protocol_hint == "xaui") ? 1'b0 : 1'b1; // rx_ctrl init_renpolinv_en = (dec_8b_10b_polarity_inv_enable == "true") ? 1'b1 : 1'b0; init_rforce0_freqdet = 1'b0; // defaults to rx_digi init_rforce1_freqdet = 1'b0; // defaults to rx_digi init_rindv_rx = (channel_bonding == "x4" || channel_bonding == "x8" || protocol_hint == "xaui") ? 1'b0 : 1'b1; init_rmaster_rx = (mph_fifo_xn_mapping == "central" || channel_bonding != "x8") ? 1'b1 : 1'b0; init_rmaster_up_rx = (mph_fifo_xn_mapping == "down") ? 1'b1 : 1'b0; // as is: flip init_rphfifourstenrx = (ph_fifo_reset_enable == "true") ? 1'b1 : 1'b0; init_rppm_gen1_2xcnt_en = 1'b0; // PPM moved to rx_pma: ppm_gen1_2_xcnt_en - setting to 0 to speed up sim init_rppm_post_eidle_del= 1'b0; // PPM moved to rx_pma: ppm_post_eidle init_rppmsel = 6'b000000; // for the sake of connection even though PPM detect moved to PMA init_rprbs_sel = compute_rprbs_sel_rx(init_rpma_doublewidth_rx,init_rpmadwidth_rx,self_test_mode); init_rrdwidth_rx = (use_double_data_mode == "true") ? 1'b1 : 1'b0; init_rrx_fifo_dis = (ph_fifo_disable == "true") ? 1'b1 : 1'b0; init_rtx_elec_idle_delay = 2'b00; // not modeled - delay numbers init_rtx_pipe_enable = 1'b0; init_scan_mode = 1'b0; init_sel_gp_md = 1'b0; // 1=group, 0=quad - hard wired in centrl_chnl.v // Existing (end) // moved up as they can be used by other parameter initialization init_r8b10b_dec_ibm_en[0] = (dec_8b_10b_compatibility_mode == "true") ? 1'b1 : 1'b0; init_r8b10b_dec_ibm_en[1] = 1'b0; // Existingd init_rall_one_dect_only = (prbs_all_one_detect == "true") ? 1'b1 : 1'b0; init_rautobtalg_dis = (bit_slip_enable == "true") ? 1'b1 : 1'b0 ; init_rautoinsdis = (disable_auto_idle_insertion == "true") ? 1'b1 : 1'b0; init_rbist_clr_rx = 1'b0; // used in bist_ver - not provided to users init_rbisten_rx = ((enable_self_test_mode == "true") && (self_test_mode == "cjpat" || self_test_mode == "crpat" || self_test_mode == "incremental")) ? 1'b1 : 1'b0; init_rbitloc_rev_en = (enable_bit_reversal == "true") ? 1'b1 : 1'b0; init_rbysync_polinv_en = (allow_align_polarity_inversion == "true") ? 1'b1 : 1'b0; init_rbyte_rev_en = (enable_deep_align_byte_swap == "true") ? 1'b1 : 1'b0; init_rbyteorden = (byte_order_mode == "none") ? 2'b00 : (byte_order_mode == "8" || byte_order_mode == "16") ? 2'b01 : (byte_order_mode == "10" || byte_order_mode == "20") ? 2'b11 : (byte_order_mode == "9" || byte_order_mode == "18") ? 2'b10 : 2'bzz; init_rbytord_2sym_en = (byte_order_mode == "16" || byte_order_mode == "18" || byte_order_mode == "20") ? 1'b1 : 1'b0; tmp_reg40 = m_str_to_bin(byte_order_pad_pattern); init_rbytordpad = tmp_reg40[9:0]; // byte_order_pad_pattern into 10'b format tmp_reg40 = m_str_to_bin(byte_order_pattern); init_rbytordpat[9:0] = tmp_reg40[9:0]; // byte_order_pattern into 20'b format init_rbytordpat[19:10] = (byte_order_mode == "16") ? {2'b00, tmp_reg40[15:8]} : (byte_order_mode == "18") ? {1'b0, tmp_reg40[17:9]} : tmp_reg40[19:10]; init_rbytordplden = (byte_order_pld_ctrl_enable == "true") ? 1'b1 : 1'b0; init_rcascaded_8b10b_en_rx = (dec_8b_10b_mode == "cascaded") ? 1'b1 : 1'b0; init_rclk_1_sel = (clk1_mux_select == "recvd_clk" || clk1_mux_select == "recovered clock") ? 2'b00 : (clk1_mux_select == "digital_refclk" || clk1_mux_select == "digital reference clock") ? 2'b01 : (clk1_mux_select == "local_refclk" || clk1_mux_select == "local reference clock") ? 2'b10 : (clk1_mux_select == "master_clk" || clk1_mux_select == "master clock") ? 2'b11 : 2'bzz; init_rclk_2_sel = (clk2_mux_select == "recvd_clk" || clk2_mux_select == "recovered clock") ? 2'b00 : (clk2_mux_select == "digital_refclk" || clk2_mux_select == "digital reference clock") ? 2'b10 : (clk2_mux_select == "local_refclk" || clk2_mux_select == "local reference clock") ? 2'b01 : (clk2_mux_select == "core_clk" || clk2_mux_select == "core clk" || clk2_mux_select == "core clock") ? 2'b11 : 2'bzz; init_rclkcmpinsertpad = (insert_pad_on_underflow == "true") ? 1'b1 : 1'b0; tmp_reg40 = m_str_to_bin(rate_match_pattern2); init_rclkcmpsq1n = tmp_reg40[19:0]; // convert from rate_match_pattern2 tmp_reg40 = m_str_to_bin(rate_match_pattern1); init_rclkcmpsq1p = tmp_reg40[19:0]; // convert from rate_match_pattern1 init_rclkcmpsqmd = (rate_match_ordered_set_based == "true") ? 1'b1 : 1'b0; // 2 word deletion for GIGE init_rcmpfifourst = (rate_match_reset_enable == "true") ? 1'b1 : 1'b0; init_rcomp_pat = m_str_to_bin(align_pattern); //40bit from align_pattern with align_pattern_size init_rcomp_pat_porn = (enable_true_complement_match_in_word_align == "true") ? 1'b1 : 1'b0; // when J=8 (3G), pattern is 16-bit but hardware pattern len is 8. We fixed it in software tmp_rcomp_size = (align_pattern_length == 16) ? ((init_rpmadwidth_rx == 1'b0 && init_rpma_doublewidth_rx == 1'b0) ? 3'b001 : 3'b011) : 3'bzzz; init_rcomp_size = (align_pattern_length == 7) ? 3'b000 : (align_pattern_length == 8) ? 3'b001 : (align_pattern_length == 10) ? 3'b010 : (align_pattern_length == 16) ? tmp_rcomp_size : // 3'b011 (align_pattern_length == 20) ? 3'b100 : (align_pattern_length == 32) ? 3'b101 : (align_pattern_length == 40) ? 3'b110 : 3'bzzz; init_rdis_rx_disp = (disable_running_disp_in_word_align == "true") ? 1'b1 : 1'b0; init_rdwidth_rx = (use_double_data_mode == "true") ? 1'b1 : 1'b0; init_rencdt_rising = (use_rising_edge_triggered_pattern_align == "true") ? 1'b1 : 1'b0; init_rendec_rx = (dec_8b_10b_mode != "none") ? 1'b1 : 1'b0; init_renpolinv_rx = (allow_pipe_polarity_inversion == "true") ? 1'b1 : 1'b0; init_renumber = num_align_loss_sync_error - 1; init_resync_badcg_en = 2'b00; // Existingd - 6G only init_rforce_sig_det_pcs = (force_signal_detect_dig == "true") ? 1'b1 : 1'b0; init_rfreerun_rx = (reset_clock_output_during_digital_reset == "false") ? 1'b1 : 1'b0; init_rgenericfifo = 1'b0; init_rgnumber = (num_align_cons_good_data - 1); // int to 8-bit conversion init_rib_inv_cd = infiniband_invalid_code; // int to 2-bit conversion init_rkchar = (disallow_kchar_after_pattern_ordered_set == "true") ? 1'b1 : 1'b0; init_rknumber = (num_align_code_groups_in_ordered_set == 0) ? (num_align_cons_pat - 1) : num_align_cons_pat; // int to 8-bit conversion init_rlp20ben = (use_parallel_loopback == "true") ? 1'b1 : 1'b0; init_rmatchen = (rate_match_fifo_mode == "none" || rate_match_fifo_mode == "false" ) ? 1'b0 : (rate_match_fifo_mode == "true" || rate_match_fifo_mode == "normal") ? 1'b1 : 1'bz; init_rosbased = (align_ordered_set_based == "true") ? 1'b1 : 1'b0; init_rosnumber = num_align_code_groups_in_ordered_set; // 2-bit init_rphfifopldenrx = 1'b1; // internal mode - enable PLD write/read ** enabled to match ASM init_rphfifourstrx = 1'b1; // internal mode - enabled for POF init_rppm_cnt_reset = 1'b0; // internal mode init_rprbs_clr_rslt_rx = 1'b0; // default init_rprbsen_rx = ((enable_self_test_mode == "true") && (self_test_mode != "incremental") && (self_test_mode != "cjpat") && (self_test_mode != "crpat")) ? 1'b1 : 1'b0; init_rrcvd_clk_sel = (recovered_clk_mux_select == "recvd_clk" || recovered_clk_mux_select == "recovered clock") ? 2'b00 : (recovered_clk_mux_select == "digital_refclk" || recovered_clk_mux_select == "digital reference clock") ? 2'b01 : (recovered_clk_mux_select == "local_refclk" || recovered_clk_mux_select == "local reference clock") ? 2'b10 : 2'bzz; init_rrlv_en = (run_length_enable == "true") ? 1'b1 : 1'b0; init_rrundisp = compute_rrundisp(init_rpma_doublewidth_rx,init_rpmadwidth_rx,run_length); // convert int to 6-bit init_rrx_rd_clk_sel = (rd_clk_mux_select == "core_clk" || rd_clk_mux_select == "core clk" || rd_clk_mux_select == "core clock") ? 1'b1 : 1'b0; init_rrxfifo_dis = (enable_phfifo_bypass == "true") ? 1'b1 : 1'b0; // cannot bypass init_rrxfifo_lowlatency_en=(ph_fifo_low_latency_enable == "true") ? 1'b1 : 1'b0; init_rskpsetbased = (rate_match_skip_set_based == "true") ? 1'b1 : 1'b0; init_rsync_sm_dis = (use_alignment_state_machine == "false") ? 1'b1 : 1'b0; init_rtruebac2bac = (rate_match_back_to_back == "true") ? 1'b1 : 1'b0; init_rwa_6g_en = (enable_deep_align == "true") ? 1'b1 : 1'b0; //======= pipe ===== init_rphystatus_rst_toggle = (phystatus_reset_toggle == "true") ? 1'b1 : 1'b0; // default 0 init_rrx_detect_bypass = (rx_detect_bypass == "true") ? 1'b1 : 1'b0; init_rrx_pipe_enable = (protocol_hint == "pcie" || protocol_hint == "pcie2") ? 1'b1 : 1'b0; //STRATIXIV new CRAMs init_rauto_speed_ena = (pipe_auto_speed_nego_enable == "true") ? 1'b1 : 1'b0; init_rbytord_6g_mask_en = (byte_order_double_data_mode_mask_enable == "true") ? 1'b1 : 1'b0; init_rbytord_s2gx = (byte_order_back_compat_enable == "true") ? 1'b1 : 1'b0; init_rclkcmp_pipe_en = (rate_match_pipe_enable == "true") ? 1'b1 : 1'b0; init_rdel_threshold = rate_match_delete_threshold; init_reidle_com_detect = elec_idle_num_com_detect; // 2-bit init_reidleinferenable = (elec_idle_infer_enable == "true") ? 1'b1 : 1'b0; init_rempty_threshold = rate_match_empty_threshold; init_rfreq_sel = (pipe_freq_scale_mode == "data width") ? 1'b0 : 1'b1; // default is Frequency init_rfull_threshold = rate_match_full_threshold; init_rind_error_reporting = (rxstatus_error_report_mode == 0) ? 1'b0 : 1'b1; init_rins_threshold = rate_match_insert_threshold; init_rinvalid_code_err_only = (byte_order_invalid_code_or_run_disp_error == "true") ? 1'b1 : 1'b0; init_rphystatus_delay = phystatus_delay; //3-bit init_rrxpcsbypass_en =(datapath_low_latency_mode == "true") ? 1'b1 : 1'b0; init_rstart_threshold = rate_match_start_threshold; // STRATIXIV WW47 ---------------------------------------------------------- init_rauto_deassert_pc_rst_cnt = auto_spd_deassert_ph_fifo_rst_count; init_rauto_pc_en_cnt = auto_spd_phystatus_notify_count; init_rcdr_ctrl_en = (cdrctrl_enable == "true") ? 1'b1 : 1'b0; init_rcid_en = (cdrctrl_cid_mode_enable == "true") ? 1'b1 : 1'b0; init_rcid_len_rx = prbs_cid_pattern_length; init_rcid_pattern_rx = (prbs_cid_pattern == "true") ? 1'b1 : 1'b0; init_rfts_count = cdrctrl_bypass_ppm_detector_cycle; init_rhip_ena = (hip_enable == "true") ? 1'b1 : 1'b0; init_rmask_count = cdrctrl_mask_cycle; // ----------------------------------------------------------------------------- // megafuncton gets rmaster_up opposite as input mux but still in simulation input as // I connect the input (from master channel) into both in_up and in_down // The reason I care now is due to ww12 RTL: I use the cram to mux iqp <= (up, down) // ----------------------------------------------------------------------------- init_rphfifo_regmode_rx = (ph_fifo_reg_mode == "true") ? 1'b1 : 1'b0; init_rpipeline_bypass_rx = (iqp_bypass == "true") ? 1'b1 : 1'b0; init_rpma_done_count = 18'd15; // short it in simulations - pma_done_count; init_rrxpcsclkpwdn = (clk_pd_enable == "true") ? 1'b1 : 1'b0; init_rrxvalid_mask = (cdrctrl_rxvalid_mask == "true") ? 1'b1 : 1'b0; init_rself_sw_en_rx = (auto_spd_self_switch_enable == "true") ? 1'b1 : 1'b0; init_rtest_bus_sel = test_bus_sel; init_rwait_count = cdrctrl_min_lock_to_ref_cycle; // STRATIXIV WW12 ---------------------------------------------------------- init_rwait_for_phfifo_cnt = rx_phfifo_wait_cnt; // 6'b100000; 295112 init_riei_eios_priority_dis = (elec_idle_eios_detect_priority_over_eidle_disable == "true") ? 1'b1 : 1'b0; init_rgen1_sigdet_ena = (elec_idle_gen1_sigdet_enable == "true") ? 1'b1: 1'b0; // STRATIXIV WW25.2008 ----------------------------------------------------- init_rerr_flags_sel = (error_from_wa_or_8b_10b_select == "true") ? 1'b1 : 1'b0; init_rpcs_wrapback_en = 1'b0; // test-only: WYS end initial begin // init_rcomp_pat init_rcomp_pat_0 = init_rcomp_pat[0]; init_rcomp_pat_1 = init_rcomp_pat[1]; init_rcomp_pat_2 = init_rcomp_pat[2]; init_rcomp_pat_3 = init_rcomp_pat[3]; init_rcomp_pat_4 = init_rcomp_pat[4]; init_rcomp_pat_5 = init_rcomp_pat[5]; init_rcomp_pat_6 = init_rcomp_pat[6]; init_rcomp_pat_7 = init_rcomp_pat[7]; init_rcomp_pat_8 = init_rcomp_pat[8]; init_rcomp_pat_9 = init_rcomp_pat[9]; init_rcomp_pat_10 = init_rcomp_pat[10]; init_rcomp_pat_11 = init_rcomp_pat[11]; init_rcomp_pat_12 = init_rcomp_pat[12]; init_rcomp_pat_13 = init_rcomp_pat[13]; init_rcomp_pat_14 = init_rcomp_pat[14]; init_rcomp_pat_15 = init_rcomp_pat[15]; init_rcomp_pat_16 = init_rcomp_pat[16]; init_rcomp_pat_17 = init_rcomp_pat[17]; init_rcomp_pat_18 = init_rcomp_pat[18]; init_rcomp_pat_19 = init_rcomp_pat[19]; init_rcomp_pat_20 = init_rcomp_pat[20]; init_rcomp_pat_21 = init_rcomp_pat[21]; init_rcomp_pat_22 = init_rcomp_pat[22]; init_rcomp_pat_23 = init_rcomp_pat[23]; init_rcomp_pat_24 = init_rcomp_pat[24]; init_rcomp_pat_25 = init_rcomp_pat[25]; init_rcomp_pat_26 = init_rcomp_pat[26]; init_rcomp_pat_27 = init_rcomp_pat[27]; init_rcomp_pat_28 = init_rcomp_pat[28]; init_rcomp_pat_29 = init_rcomp_pat[29]; init_rcomp_pat_30 = init_rcomp_pat[30]; init_rcomp_pat_31 = init_rcomp_pat[31]; init_rcomp_pat_32 = init_rcomp_pat[32]; init_rcomp_pat_33 = init_rcomp_pat[33]; init_rcomp_pat_34 = init_rcomp_pat[34]; init_rcomp_pat_35 = init_rcomp_pat[35]; init_rcomp_pat_36 = init_rcomp_pat[36]; init_rcomp_pat_37 = init_rcomp_pat[37]; init_rcomp_pat_38 = init_rcomp_pat[38]; init_rcomp_pat_39 = init_rcomp_pat[39]; //init_rclkcmpsq1p init_rclkcmpsq1p_0 = init_rclkcmpsq1p[0]; init_rclkcmpsq1p_1 = init_rclkcmpsq1p[1]; init_rclkcmpsq1p_2 = init_rclkcmpsq1p[2]; init_rclkcmpsq1p_3 = init_rclkcmpsq1p[3]; init_rclkcmpsq1p_4 = init_rclkcmpsq1p[4]; init_rclkcmpsq1p_5 = init_rclkcmpsq1p[5]; init_rclkcmpsq1p_6 = init_rclkcmpsq1p[6]; init_rclkcmpsq1p_7 = init_rclkcmpsq1p[7]; init_rclkcmpsq1p_8 = init_rclkcmpsq1p[8]; init_rclkcmpsq1p_9 = init_rclkcmpsq1p[9]; init_rclkcmpsq1p_10 = init_rclkcmpsq1p[10]; init_rclkcmpsq1p_11 = init_rclkcmpsq1p[11]; init_rclkcmpsq1p_12 = init_rclkcmpsq1p[12]; init_rclkcmpsq1p_13 = init_rclkcmpsq1p[13]; init_rclkcmpsq1p_14 = init_rclkcmpsq1p[14]; init_rclkcmpsq1p_15 = init_rclkcmpsq1p[15]; init_rclkcmpsq1p_16 = init_rclkcmpsq1p[16]; init_rclkcmpsq1p_17 = init_rclkcmpsq1p[17]; init_rclkcmpsq1p_18 = init_rclkcmpsq1p[18]; init_rclkcmpsq1p_19 = init_rclkcmpsq1p[19]; //init_rclkcmpsq1n init_rclkcmpsq1n_0 = init_rclkcmpsq1n[0]; init_rclkcmpsq1n_1 = init_rclkcmpsq1n[1]; init_rclkcmpsq1n_2 = init_rclkcmpsq1n[2]; init_rclkcmpsq1n_3 = init_rclkcmpsq1n[3]; init_rclkcmpsq1n_4 = init_rclkcmpsq1n[4]; init_rclkcmpsq1n_5 = init_rclkcmpsq1n[5]; init_rclkcmpsq1n_6 = init_rclkcmpsq1n[6]; init_rclkcmpsq1n_7 = init_rclkcmpsq1n[7]; init_rclkcmpsq1n_8 = init_rclkcmpsq1n[8]; init_rclkcmpsq1n_9 = init_rclkcmpsq1n[9]; init_rclkcmpsq1n_10 = init_rclkcmpsq1n[10]; init_rclkcmpsq1n_11 = init_rclkcmpsq1n[11]; init_rclkcmpsq1n_12 = init_rclkcmpsq1n[12]; init_rclkcmpsq1n_13 = init_rclkcmpsq1n[13]; init_rclkcmpsq1n_14 = init_rclkcmpsq1n[14]; init_rclkcmpsq1n_15 = init_rclkcmpsq1n[15]; init_rclkcmpsq1n_16 = init_rclkcmpsq1n[16]; init_rclkcmpsq1n_17 = init_rclkcmpsq1n[17]; init_rclkcmpsq1n_18 = init_rclkcmpsq1n[18]; init_rclkcmpsq1n_19 = init_rclkcmpsq1n[19]; //init_rpma_done_count init_rpma_done_count_0 = init_rpma_done_count[0]; init_rpma_done_count_1 = init_rpma_done_count[1]; init_rpma_done_count_2 = init_rpma_done_count[2]; init_rpma_done_count_3 = init_rpma_done_count[3]; init_rpma_done_count_4 = init_rpma_done_count[4]; init_rpma_done_count_5 = init_rpma_done_count[5]; init_rpma_done_count_6 = init_rpma_done_count[6]; init_rpma_done_count_7 = init_rpma_done_count[7]; init_rpma_done_count_8 = init_rpma_done_count[8]; init_rpma_done_count_9 = init_rpma_done_count[9]; init_rpma_done_count_10 = init_rpma_done_count[10]; init_rpma_done_count_11 = init_rpma_done_count[11]; init_rpma_done_count_12 = init_rpma_done_count[12]; init_rpma_done_count_13 = init_rpma_done_count[13]; init_rpma_done_count_14 = init_rpma_done_count[14]; init_rpma_done_count_15 = init_rpma_done_count[15]; init_rpma_done_count_16 = init_rpma_done_count[16]; init_rpma_done_count_17 = init_rpma_done_count[17]; //init_rbytordpat init_rbytordpat_0 = init_rbytordpat[0]; init_rbytordpat_1 = init_rbytordpat[1]; init_rbytordpat_2 = init_rbytordpat[2]; init_rbytordpat_3 = init_rbytordpat[3]; init_rbytordpat_4 = init_rbytordpat[4]; init_rbytordpat_5 = init_rbytordpat[5]; init_rbytordpat_6 = init_rbytordpat[6]; init_rbytordpat_7 = init_rbytordpat[7]; init_rbytordpat_8 = init_rbytordpat[8]; init_rbytordpat_9 = init_rbytordpat[9]; init_rbytordpat_10 = init_rbytordpat[10]; init_rbytordpat_11 = init_rbytordpat[11]; init_rbytordpat_12 = init_rbytordpat[12]; init_rbytordpat_13 = init_rbytordpat[13]; init_rbytordpat_14 = init_rbytordpat[14]; init_rbytordpat_15 = init_rbytordpat[15]; init_rbytordpat_16 = init_rbytordpat[16]; init_rbytordpat_17 = init_rbytordpat[17]; init_rbytordpat_18 = init_rbytordpat[18]; init_rbytordpat_19 = init_rbytordpat[19]; end //////////////////////////////////////////////////////////////////////////////// // Set DPRIO input CRAM from dprioin - CRAM_Table 2A ------------------------// //////////////////////////////////////////////////////////////////////////////// // Manual section assign dprioin_rpma_doublewidth_rx = dprioin_in[`rpma_doublewidth_rx_RX_IDX]; assign dprioin_rpmadwidth_rx = dprioin_in[`rpmadwidth_rx_RX_IDX]; assign dprioin_rendec_data_sel_rx = dprioin_in[`rendec_data_sel_rx_RX_IDX]; assign dprioin_rdeskewen = dprioin_in[`rdeskewen_RX_IDX]; assign dprioin_rindv_rx = dprioin_in[`rindv_rx_RX_IDX]; assign dprioin_rmaster_rx = dprioin_in[`rmaster_rx_RX_IDX]; assign dprioin_rmaster_up_rx = dprioin_in[`rmaster_up_rx_RX_IDX]; assign dprioin_rdskposdisp = dprioin_in[`rdskposdisp_RX_IDX]; assign dprioin_dskwclksel[1] = dprioin_rdeskewen; assign dprioin_dskwclksel[0] = 1'b0; assign dprioin_is_lane0 = init_is_lane0; assign dprioin_rbist_sel = init_rbist_sel; assign dprioin_rclkcmppos = dprioin_in[`rclkcmppos_RX_IDX]; assign dprioin_rcxpat_chnl_en = init_rcxpat_chnl_en; assign dprioin_rdskchrp = init_rdskchrp; assign dprioin_rforce0_freqdet = dprioin_in[`rforce0_freqdet_RX_IDX]; assign dprioin_rforce1_freqdet = dprioin_in[`rforce1_freqdet_RX_IDX]; assign dprioin_rppmsel = 6'b000000; // dprioin_in[`rppmsel_RX_IDX_5 : `rppmsel_RX_IDX_0]; assign dprioin_rprbs_sel = init_rprbs_sel; assign dprioin_rrdwidth_rx = dprioin_in[`rdwidth_rx_RX_IDX]; assign dprioin_rrx_revlb_sw = dprioin_in[`rrx_revlb_sw_RX_IDX]; assign dprioin_rs_lpbk = dprioin_in[`rs_lpbk_RX_IDX]; assign dprioin_rtx_elec_idle_delay = dprioin_in[`rtx_idle_delay_RX_IDX_1 : `rtx_idle_delay_RX_IDX_0]; assign dprioin_rtx_pipe_enable = init_rtx_pipe_enable; assign dprioin_scan_mode = init_scan_mode; assign dprioin_sel_gp_md = init_sel_gp_md; // --------------------------------------------------------------------------- // Set DPRIO CRAM input from dprioin // --------------------------------------------------------------------------- // PCS Per Channel RX Control Register 1 for Channel 0 assign dprioin_rrxpcsbypass_en = dprioin[`rrxpcsbypass_en_RXPCS_IDX_0]; assign dprioin_rall_one_dect_only = dprioin[`rall_one_dect_only_RXPCS_IDX_0]; assign dprioin_rbist_clr_rx = dprioin[`rbist_clr_rx_RXPCS_IDX_0]; assign dprioin_rbisten_rx = dprioin[`rbisten_rx_RXPCS_IDX_0]; assign dprioin_rprbs_clr_rslt_rx = dprioin[`rprbs_clr_rslt_rx_RXPCS_IDX_0]; assign dprioin_rprbsen_rx = dprioin[`rprbsen_rx_RXPCS_IDX_0]; assign dprioin_rrx_rd_clk_sel = dprioin[`rrx_rd_clk_sel_RXPCS_IDX_0]; assign dprioin_rclk_2_sel = dprioin[`rclk_2_sel_RXPCS_IDX_1 : `rclk_2_sel_RXPCS_IDX_0]; assign dprioin_rclk_1_sel = dprioin[`rclk_1_sel_RXPCS_IDX_1 : `rclk_1_sel_RXPCS_IDX_0]; assign dprioin_rrcvd_clk_sel = dprioin[`rrcvd_clk_sel_RXPCS_IDX_1 : `rrcvd_clk_sel_RXPCS_IDX_0]; assign dprioin_rfreerun_rx = dprioin[`rfreerun_rx_RXPCS_IDX_0]; assign dprioin_rrxurstpcs = dprioin[`rrxurstpcs_RXPCS_IDX_0]; assign dprioin_reserved_0_TB5 = dprioin[`reserved_0_TB5_RXPCS_IDX_0]; // PCS Per Channel RX Control Register 2 for Channel 0 assign dprioin_rcomp_pat_32 = dprioin[`rcomp_pat_32_RXPCS_IDX_0]; assign dprioin_rcomp_pat_33 = dprioin[`rcomp_pat_33_RXPCS_IDX_0]; assign dprioin_rcomp_pat_34 = dprioin[`rcomp_pat_34_RXPCS_IDX_0]; assign dprioin_rcomp_pat_35 = dprioin[`rcomp_pat_35_RXPCS_IDX_0]; assign dprioin_rcomp_pat_36 = dprioin[`rcomp_pat_36_RXPCS_IDX_0]; assign dprioin_rcomp_pat_37 = dprioin[`rcomp_pat_37_RXPCS_IDX_0]; assign dprioin_rcomp_pat_38 = dprioin[`rcomp_pat_38_RXPCS_IDX_0]; assign dprioin_rcomp_pat_39 = dprioin[`rcomp_pat_39_RXPCS_IDX_0]; assign dprioin_rcomp_size = dprioin[`rcomp_size_RXPCS_IDX_2 : `rcomp_size_RXPCS_IDX_0]; assign dprioin_rcomp_pat_porn = dprioin[`rcomp_pat_porn_RXPCS_IDX_0]; assign dprioin_rdis_rx_disp = dprioin[`rdis_rx_disp_RXPCS_IDX_0]; assign dprioin_rencdt_rising = dprioin[`rencdt_rising_RXPCS_IDX_0]; assign dprioin_resync_badcg_en = dprioin[`resync_badcg_en_RXPCS_IDX_1 : `resync_badcg_en_RXPCS_IDX_0]; // PCS Per Channel RX Control Register 3 for Channel 0 assign dprioin_rcomp_pat_16 = dprioin[`rcomp_pat_16_RXPCS_IDX_0]; assign dprioin_rcomp_pat_17 = dprioin[`rcomp_pat_17_RXPCS_IDX_0]; assign dprioin_rcomp_pat_18 = dprioin[`rcomp_pat_18_RXPCS_IDX_0]; assign dprioin_rcomp_pat_19 = dprioin[`rcomp_pat_19_RXPCS_IDX_0]; assign dprioin_rcomp_pat_20 = dprioin[`rcomp_pat_20_RXPCS_IDX_0]; assign dprioin_rcomp_pat_21 = dprioin[`rcomp_pat_21_RXPCS_IDX_0]; assign dprioin_rcomp_pat_22 = dprioin[`rcomp_pat_22_RXPCS_IDX_0]; assign dprioin_rcomp_pat_23 = dprioin[`rcomp_pat_23_RXPCS_IDX_0]; assign dprioin_rcomp_pat_24 = dprioin[`rcomp_pat_24_RXPCS_IDX_0]; assign dprioin_rcomp_pat_25 = dprioin[`rcomp_pat_25_RXPCS_IDX_0]; assign dprioin_rcomp_pat_26 = dprioin[`rcomp_pat_26_RXPCS_IDX_0]; assign dprioin_rcomp_pat_27 = dprioin[`rcomp_pat_27_RXPCS_IDX_0]; assign dprioin_rcomp_pat_28 = dprioin[`rcomp_pat_28_RXPCS_IDX_0]; assign dprioin_rcomp_pat_29 = dprioin[`rcomp_pat_29_RXPCS_IDX_0]; assign dprioin_rcomp_pat_30 = dprioin[`rcomp_pat_30_RXPCS_IDX_0]; assign dprioin_rcomp_pat_31 = dprioin[`rcomp_pat_31_RXPCS_IDX_0]; // PCS Per Channel RX Control Register 4 for Channel 0 assign dprioin_rcomp_pat_0 = dprioin[`rcomp_pat_0_RXPCS_IDX_0]; assign dprioin_rcomp_pat_1 = dprioin[`rcomp_pat_1_RXPCS_IDX_0]; assign dprioin_rcomp_pat_2 = dprioin[`rcomp_pat_2_RXPCS_IDX_0]; assign dprioin_rcomp_pat_3 = dprioin[`rcomp_pat_3_RXPCS_IDX_0]; assign dprioin_rcomp_pat_4 = dprioin[`rcomp_pat_4_RXPCS_IDX_0]; assign dprioin_rcomp_pat_5 = dprioin[`rcomp_pat_5_RXPCS_IDX_0]; assign dprioin_rcomp_pat_6 = dprioin[`rcomp_pat_6_RXPCS_IDX_0]; assign dprioin_rcomp_pat_7 = dprioin[`rcomp_pat_7_RXPCS_IDX_0]; assign dprioin_rcomp_pat_8 = dprioin[`rcomp_pat_8_RXPCS_IDX_0]; assign dprioin_rcomp_pat_9 = dprioin[`rcomp_pat_9_RXPCS_IDX_0]; assign dprioin_rcomp_pat_10 = dprioin[`rcomp_pat_10_RXPCS_IDX_0]; assign dprioin_rcomp_pat_11 = dprioin[`rcomp_pat_11_RXPCS_IDX_0]; assign dprioin_rcomp_pat_12 = dprioin[`rcomp_pat_12_RXPCS_IDX_0]; assign dprioin_rcomp_pat_13 = dprioin[`rcomp_pat_13_RXPCS_IDX_0]; assign dprioin_rcomp_pat_14 = dprioin[`rcomp_pat_14_RXPCS_IDX_0]; assign dprioin_rcomp_pat_15 = dprioin[`rcomp_pat_15_RXPCS_IDX_0]; // PCS Per Channel RX Control Register 5 for Channel 0 assign dprioin_rbitloc_rev_en = dprioin[`rbitloc_rev_en_RXPCS_IDX_0]; assign dprioin_rbysync_polinv_en = dprioin[`rbysync_polinv_en_RXPCS_IDX_0]; assign dprioin_rwa_6g_en = dprioin[`rwa_6g_en_RXPCS_IDX_0]; assign dprioin_rosnumber = dprioin[`rosnumber_RXPCS_IDX_1 : `rosnumber_RXPCS_IDX_0]; assign dprioin_rosbased = dprioin[`rosbased_RXPCS_IDX_0]; assign dprioin_rkchar = dprioin[`rkchar_RXPCS_IDX_0]; assign dprioin_renumber = dprioin[`renumber_RXPCS_IDX_5 : `renumber_RXPCS_IDX_0]; assign dprioin_rib_inv_cd = dprioin[`rib_inv_cd_RXPCS_IDX_1 : `rib_inv_cd_RXPCS_IDX_0]; assign dprioin_rsync_sm_dis = dprioin[`rsync_sm_dis_RXPCS_IDX_0]; // PCS Per Channel RX Control Register 6 for Channel 0 assign dprioin_rknumber = dprioin[`rknumber_RXPCS_IDX_7 : `rknumber_RXPCS_IDX_0]; assign dprioin_rgnumber = dprioin[`rgnumber_RXPCS_IDX_7 : `rgnumber_RXPCS_IDX_0]; // PCS Per Channel RX Control Register 7 for Channel 0 assign dprioin_renpolinv_rx = dprioin[`renpolinv_rx_RXPCS_IDX_0]; assign dprioin_rcascaded_8b10b_en_rx = dprioin[`rcascaded_8b10b_en_rx_RXPCS_IDX_0]; assign dprioin_r8b10b_dec_ibm_en = dprioin[`r8b10b_dec_ibm_en_RXPCS_IDX_1 : `r8b10b_dec_ibm_en_RXPCS_IDX_0]; assign dprioin_rendec_rx = dprioin[`rendec_rx_RXPCS_IDX_0]; assign dprioin_rautobtalg_dis = dprioin[`rautobtalg_dis_RXPCS_IDX_0]; assign dprioin_rrlv_en = dprioin[`rrlv_en_RXPCS_IDX_0]; assign dprioin_rlp20ben = dprioin[`rlp20ben_RXPCS_IDX_0]; assign dprioin_rforce_sig_det_pcs = dprioin[`rforce_sig_det_pcs_RXPCS_IDX_0]; assign dprioin_rbyte_rev_en = dprioin[`rbyte_rev_en_RXPCS_IDX_0]; assign dprioin_rrundisp = dprioin[`rrundisp_RXPCS_IDX_5 : `rrundisp_RXPCS_IDX_0]; // PCS Per Channel RX Control Register 8 for Channel 0 assign dprioin_rclkcmpsq1p_0 = dprioin[`rclkcmpsq1p_0_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1p_1 = dprioin[`rclkcmpsq1p_1_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1p_2 = dprioin[`rclkcmpsq1p_2_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1p_3 = dprioin[`rclkcmpsq1p_3_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1p_4 = dprioin[`rclkcmpsq1p_4_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1p_5 = dprioin[`rclkcmpsq1p_5_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1p_6 = dprioin[`rclkcmpsq1p_6_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1p_7 = dprioin[`rclkcmpsq1p_7_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1p_8 = dprioin[`rclkcmpsq1p_8_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1p_9 = dprioin[`rclkcmpsq1p_9_RXPCS_IDX_0]; assign dprioin_rclkcmpsqmd = dprioin[`rclkcmpsqmd_RXPCS_IDX_0]; assign dprioin_rclkcmpinsertpad = dprioin[`rclkcmpinsertpad_RXPCS_IDX_0]; assign dprioin_rtruebac2bac = dprioin[`rtruebac2bac_RXPCS_IDX_0]; assign dprioin_rskpsetbased = dprioin[`rskpsetbased_RXPCS_IDX_0]; assign dprioin_rgenericfifo = dprioin[`rgenericfifo_RXPCS_IDX_0]; assign dprioin_rmatchen = dprioin[`rmatchen_RXPCS_IDX_0]; // PCS Per Channel RX Control Register 9 for Channel 0 assign dprioin_rclkcmpsq1p_10 = dprioin[`rclkcmpsq1p_10_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1p_11 = dprioin[`rclkcmpsq1p_11_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1p_12 = dprioin[`rclkcmpsq1p_12_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1p_13 = dprioin[`rclkcmpsq1p_13_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1p_14 = dprioin[`rclkcmpsq1p_14_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1p_15 = dprioin[`rclkcmpsq1p_15_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1p_16 = dprioin[`rclkcmpsq1p_16_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1p_17 = dprioin[`rclkcmpsq1p_17_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1p_18 = dprioin[`rclkcmpsq1p_18_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1p_19 = dprioin[`rclkcmpsq1p_19_RXPCS_IDX_0]; assign dprioin_reserved_0_TB13 = dprioin[`reserved_0_TB13_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1n_15 = dprioin[`rclkcmpsq1n_15_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1n_16 = dprioin[`rclkcmpsq1n_16_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1n_17 = dprioin[`rclkcmpsq1n_17_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1n_18 = dprioin[`rclkcmpsq1n_18_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1n_19 = dprioin[`rclkcmpsq1n_19_RXPCS_IDX_0]; // PCS Per Channel RX Control Register 10 for Channel 0 assign dprioin_rclkcmpsq1n_0 = dprioin[`rclkcmpsq1n_0_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1n_1 = dprioin[`rclkcmpsq1n_1_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1n_2 = dprioin[`rclkcmpsq1n_2_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1n_3 = dprioin[`rclkcmpsq1n_3_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1n_4 = dprioin[`rclkcmpsq1n_4_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1n_5 = dprioin[`rclkcmpsq1n_5_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1n_6 = dprioin[`rclkcmpsq1n_6_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1n_7 = dprioin[`rclkcmpsq1n_7_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1n_8 = dprioin[`rclkcmpsq1n_8_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1n_9 = dprioin[`rclkcmpsq1n_9_RXPCS_IDX_0]; assign dprioin_reserved_0_TB14 = dprioin[`reserved_0_TB14_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1n_10 = dprioin[`rclkcmpsq1n_10_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1n_11 = dprioin[`rclkcmpsq1n_11_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1n_12 = dprioin[`rclkcmpsq1n_12_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1n_13 = dprioin[`rclkcmpsq1n_13_RXPCS_IDX_0]; assign dprioin_rclkcmpsq1n_14 = dprioin[`rclkcmpsq1n_14_RXPCS_IDX_0]; // PCS Per Channel RX Control Register 11 for Channel 0 assign dprioin_rfull_threshold = dprioin[`rfull_threshold_RXPCS_IDX_4 : `rfull_threshold_RXPCS_IDX_0]; assign dprioin_rdel_threshold = dprioin[`rdel_threshold_RXPCS_IDX_4 : `rdel_threshold_RXPCS_IDX_0]; assign dprioin_rins_threshold = dprioin[`rins_threshold_RXPCS_IDX_4 : `rins_threshold_RXPCS_IDX_0]; assign dprioin_rclkcmp_pipe_en = dprioin[`rclkcmp_pipe_en_RXPCS_IDX_0]; // PCS Per Channel RX Control Register 12 for Channel 0 assign dprioin_rfreq_sel = dprioin[`rfreq_sel_RXPCS_IDX_0]; assign dprioin_rauto_speed_ena = dprioin[`rauto_speed_ena_RXPCS_IDX_0]; assign dprioin_rhip_ena = dprioin[`rhip_ena_RXPCS_IDX_0]; assign dprioin_rpma_done_gen_ena = dprioin[`rpma_done_gen_ena_RXPCS_IDX_0]; assign dprioin_rpma_done_count_16 = dprioin[`rpma_done_count_16_RXPCS_IDX_0]; assign dprioin_rpma_done_count_17 = dprioin[`rpma_done_count_17_RXPCS_IDX_0]; assign dprioin_reserved_0_TB16 = dprioin[`reserved_0_TB16_RXPCS_IDX_3 : `reserved_0_TB16_RXPCS_IDX_0]; assign dprioin_rstart_threshold = dprioin[`rstart_threshold_RXPCS_IDX_2 : `rstart_threshold_RXPCS_IDX_0]; assign dprioin_rempty_threshold = dprioin[`rempty_threshold_RXPCS_IDX_2 : `rempty_threshold_RXPCS_IDX_0]; // PCS Per Channel RX Control Register 13 for Channel 0 assign dprioin_rtest_bus_sel = dprioin[`rtest_bus_sel_RXPCS_IDX_3 : `rtest_bus_sel_RXPCS_IDX_0]; assign dprioin_rautoinsdis = dprioin[`rautoinsdis_RXPCS_IDX_0]; assign dprioin_rphfifopldenrx = dprioin[`rphfifopldenrx_RXPCS_IDX_0]; assign dprioin_rbytordplden = dprioin[`rbytordplden_RXPCS_IDX_0]; assign dprioin_rbyteorden = dprioin[`rbyteorden_RXPCS_IDX_1 : `rbyteorden_RXPCS_IDX_0]; assign dprioin_rbytord_2sym_en = dprioin[`rbytord_2sym_en_RXPCS_IDX_0]; assign dprioin_rinvalid_code_err_only = dprioin[`rinvalid_code_err_only_RXPCS_IDX_0]; assign dprioin_rcmpfifourst = dprioin[`rcmpfifourst_RXPCS_IDX_0]; assign dprioin_rphfifourstrx = dprioin[`rphfifourstrx_RXPCS_IDX_0]; assign dprioin_rdwidth_rx = dprioin[`rdwidth_rx_RXPCS_IDX_0]; assign dprioin_rrxfifo_lowlatency_en = dprioin[`rrxfifo_lowlatency_en_RXPCS_IDX_0]; assign dprioin_rrxfifo_dis = dprioin[`rrxfifo_dis_RXPCS_IDX_0]; // PCS Per Channel RX Control Register 14 for Channel 0 assign dprioin_rbytordpat_0 = dprioin[`rbytordpat_0_RXPCS_IDX_0]; assign dprioin_rbytordpat_1 = dprioin[`rbytordpat_1_RXPCS_IDX_0]; assign dprioin_rbytordpat_2 = dprioin[`rbytordpat_2_RXPCS_IDX_0]; assign dprioin_rbytordpat_3 = dprioin[`rbytordpat_3_RXPCS_IDX_0]; assign dprioin_rbytordpat_4 = dprioin[`rbytordpat_4_RXPCS_IDX_0]; assign dprioin_rbytordpat_5 = dprioin[`rbytordpat_5_RXPCS_IDX_0]; assign dprioin_rbytordpat_6 = dprioin[`rbytordpat_6_RXPCS_IDX_0]; assign dprioin_rbytordpat_7 = dprioin[`rbytordpat_7_RXPCS_IDX_0]; assign dprioin_rbytordpat_8 = dprioin[`rbytordpat_8_RXPCS_IDX_0]; assign dprioin_rbytordpat_9 = dprioin[`rbytordpat_9_RXPCS_IDX_0]; assign dprioin_reserved_0_TB18 = dprioin[`reserved_0_TB18_RXPCS_IDX_5 : `reserved_0_TB18_RXPCS_IDX_0]; // PCS Per Channel RX Control Register 15 for Channel 0 assign dprioin_rbytordpad = dprioin[`rbytordpad_RXPCS_IDX_9 : `rbytordpad_RXPCS_IDX_0]; assign dprioin_reserved_0_TB19 = dprioin[`reserved_0_TB19_RXPCS_IDX_5 : `reserved_0_TB19_RXPCS_IDX_0]; // PCS Per Channel RX Control Register 16 for Channel 0 assign dprioin_rload_shreg_del = dprioin[`rload_shreg_del_RXPCS_IDX_4 : `rload_shreg_del_RXPCS_IDX_0]; assign dprioin_rphystatus_rst_toggle = dprioin[`rphystatus_rst_toggle_RXPCS_IDX_0]; assign dprioin_reidle_com_detect = dprioin[`reidle_com_detect_RXPCS_IDX_1 : `reidle_com_detect_RXPCS_IDX_0]; assign dprioin_rk285detect = dprioin[`rk285detect_RXPCS_IDX_0]; assign dprioin_reidleinferenable = dprioin[`reidleinferenable_RXPCS_IDX_0]; assign dprioin_rphystatus_delay = dprioin[`rphystatus_delay_RXPCS_IDX_2 : `rphystatus_delay_RXPCS_IDX_0]; assign dprioin_rind_error_reporting = dprioin[`rind_error_reporting_RXPCS_IDX_0]; assign dprioin_rrx_detect_bypass = dprioin[`rrx_detect_bypass_RXPCS_IDX_0]; assign dprioin_rrx_pipe_enable = dprioin[`rrx_pipe_enable_RXPCS_IDX_0]; // PCS Per Channel RX Control Register 17 for Channel 0 assign dprioin_rpma_done_count_0 = dprioin[`rpma_done_count_0_RXPCS_IDX_0]; assign dprioin_rpma_done_count_1 = dprioin[`rpma_done_count_1_RXPCS_IDX_0]; assign dprioin_rpma_done_count_2 = dprioin[`rpma_done_count_2_RXPCS_IDX_0]; assign dprioin_rpma_done_count_3 = dprioin[`rpma_done_count_3_RXPCS_IDX_0]; assign dprioin_rpma_done_count_4 = dprioin[`rpma_done_count_4_RXPCS_IDX_0]; assign dprioin_rpma_done_count_5 = dprioin[`rpma_done_count_5_RXPCS_IDX_0]; assign dprioin_rpma_done_count_6 = dprioin[`rpma_done_count_6_RXPCS_IDX_0]; assign dprioin_rpma_done_count_7 = dprioin[`rpma_done_count_7_RXPCS_IDX_0]; assign dprioin_rpma_done_count_8 = dprioin[`rpma_done_count_8_RXPCS_IDX_0]; assign dprioin_rpma_done_count_9 = dprioin[`rpma_done_count_9_RXPCS_IDX_0]; assign dprioin_rpma_done_count_10 = dprioin[`rpma_done_count_10_RXPCS_IDX_0]; assign dprioin_rpma_done_count_11 = dprioin[`rpma_done_count_11_RXPCS_IDX_0]; assign dprioin_rpma_done_count_12 = dprioin[`rpma_done_count_12_RXPCS_IDX_0]; assign dprioin_rpma_done_count_13 = dprioin[`rpma_done_count_13_RXPCS_IDX_0]; assign dprioin_rpma_done_count_14 = dprioin[`rpma_done_count_14_RXPCS_IDX_0]; assign dprioin_rpma_done_count_15 = dprioin[`rpma_done_count_15_RXPCS_IDX_0]; // PCS Per Channel RX Control Register 18 for Channel 0 assign dprioin_rbytordpat_10 = dprioin[`rbytordpat_10_RXPCS_IDX_0]; assign dprioin_rbytordpat_11 = dprioin[`rbytordpat_11_RXPCS_IDX_0]; assign dprioin_rbytordpat_12 = dprioin[`rbytordpat_12_RXPCS_IDX_0]; assign dprioin_rbytordpat_13 = dprioin[`rbytordpat_13_RXPCS_IDX_0]; assign dprioin_rbytordpat_14 = dprioin[`rbytordpat_14_RXPCS_IDX_0]; assign dprioin_rbytordpat_15 = dprioin[`rbytordpat_15_RXPCS_IDX_0]; assign dprioin_rbytordpat_16 = dprioin[`rbytordpat_16_RXPCS_IDX_0]; assign dprioin_rbytordpat_17 = dprioin[`rbytordpat_17_RXPCS_IDX_0]; assign dprioin_rbytordpat_18 = dprioin[`rbytordpat_18_RXPCS_IDX_0]; assign dprioin_rbytordpat_19 = dprioin[`rbytordpat_19_RXPCS_IDX_0]; assign dprioin_rbytord_6g_mask_en = dprioin[`rbytord_6g_mask_en_RXPCS_IDX_0]; assign dprioin_rbytord_s2gx = dprioin[`rbytord_s2gx_RXPCS_IDX_0]; assign dprioin_reserved_0_TB22 = dprioin[`reserved_0_TB22_RXPCS_IDX_0]; assign dprioin_rcdr_ctrl_en = dprioin[`rcdr_ctrl_en_RXPCS_IDX_0]; assign dprioin_rrxpcsclkpwdn = dprioin[`rrxpcsclkpwdn_RXPCS_IDX_0]; assign dprioin_rerr_flags_sel = dprioin[`rerr_flags_sel_RXPCS_IDX_0]; // PCS Per Channel RX Control Register 19 for Channel 0 assign dprioin_rwait_count = dprioin[`rwait_count_RXPCS_IDX_7 : `rwait_count_RXPCS_IDX_0]; assign dprioin_reserved_0_TB23 = dprioin[`reserved_0_TB23_RXPCS_IDX_7 : `reserved_0_TB23_RXPCS_IDX_0]; // PCS Per Channel RX Control Register 20 for Channel 0 assign dprioin_rfts_count = dprioin[`rfts_count_RXPCS_IDX_9 : `rfts_count_RXPCS_IDX_0]; assign dprioin_rwait_for_phfifo_cnt = dprioin[`rwait_for_phfifo_cnt_RXPCS_IDX_5 : `rwait_for_phfifo_cnt_RXPCS_IDX_0]; // PCS Per Channel RX Control Register 21 for Channel 0 assign dprioin_rppm_meas_delay = dprioin[`rppm_meas_delay_RXPCS_IDX_0]; assign dprioin_rcid_len_rx = dprioin[`rcid_len_rx_RXPCS_IDX_7 : `rcid_len_rx_RXPCS_IDX_0]; assign dprioin_rcid_pattern_rx = dprioin[`rcid_pattern_rx_RXPCS_IDX_0]; assign dprioin_rpcs_wrapback_en = dprioin[`rpcs_wrapback_en_RXPCS_IDX_0]; assign dprioin_reserved_0_TB25 = dprioin[`reserved_0_TB25_RXPCS_IDX_4 : `reserved_0_TB25_RXPCS_IDX_0]; // PCS Per Channel RX Control Register 22 for Channel 0 assign dprioin_rauto_pc_en_cnt = dprioin[`rauto_pc_en_cnt_RXPCS_IDX_4 : `rauto_pc_en_cnt_RXPCS_IDX_0]; assign dprioin_reserved_1_TB26 = dprioin[`reserved_1_TB26_RXPCS_IDX_0]; assign dprioin_rauto_deassert_pc_rst_cnt = dprioin[`rauto_deassert_pc_rst_cnt_RXPCS_IDX_3 : `rauto_deassert_pc_rst_cnt_RXPCS_IDX_0]; assign dprioin_reserved_0_TB26 = dprioin[`reserved_0_TB26_RXPCS_IDX_0]; assign dprioin_rpipeline_bypass_rx = dprioin[`rpipeline_bypass_rx_RXPCS_IDX_0]; assign dprioin_rself_sw_en_rx = dprioin[`rself_sw_en_rx_RXPCS_IDX_0]; assign dprioin_rrxvalid_mask = dprioin[`rrxvalid_mask_RXPCS_IDX_0]; assign dprioin_rcid_en = dprioin[`rcid_en_RXPCS_IDX_0]; assign dprioin_rphfifo_regmode_rx = dprioin[`rphfifo_regmode_rx_RXPCS_IDX_0]; // PCS Per Channel RX Control Register 23 for Channel 0 assign dprioin_rmask_count = dprioin[`rmask_count_RXPCS_IDX_9 : `rmask_count_RXPCS_IDX_0]; assign dprioin_rgen1_sigdet_ena = dprioin[`rgen1_sigdet_ena_RXPCS_IDX_0]; assign dprioin_riei_eios_priority_dis = dprioin[`riei_eios_priority_dis_RXPCS_IDX_0]; assign dprioin_reserved_0_TB27 = dprioin[`reserved_0_TB27_RXPCS_IDX_3 : `reserved_0_TB27_RXPCS_IDX_0]; //////////////////////////////////////////////////////////////////////////////// // Set DPRIO reg with initial parameters - CRAM_Table 2B --------------------// //////////////////////////////////////////////////////////////////////////////// // Index based for PCS // make sure left is wire_dprioout *** // Manual section assign dprioout[`rpma_doublewidth_rx_RX_IDX] = init_rpma_doublewidth_rx; assign dprioout[`rpmadwidth_rx_RX_IDX] = init_rpmadwidth_rx; assign dprioout[`rendec_data_sel_rx_RX_IDX] = init_rendec_data_sel_rx; assign dprioout[`rdeskewen_RX_IDX] = init_rdeskewen; assign dprioout[`rindv_rx_RX_IDX] = init_rindv_rx; assign dprioout[`rmaster_rx_RX_IDX] = init_rmaster_rx; assign dprioout[`rmaster_up_rx_RX_IDX] = init_rmaster_up_rx; assign dprioout[`rdskposdisp_RX_IDX] = init_rdskposdisp; assign dprioout[`rclkcmppos_RX_IDX] = init_rclkcmppos; assign dprioout[`rforce0_freqdet_RX_IDX] = init_rforce0_freqdet; assign dprioout[`rforce1_freqdet_RX_IDX] = init_rforce1_freqdet; assign dprioout[`rindv_rx_RX_IDX] = init_rindv_rx; assign dprioout[`rppmsel_RX_IDX_5 : `rppmsel_RX_IDX_0] = init_rppmsel; assign dprioout[`rdwidth_rx_RX_IDX] = init_rrdwidth_rx; assign dprioout[`rtx_idle_delay_RX_IDX_1 :`rtx_idle_delay_RX_IDX_0] = init_rtx_elec_idle_delay; // --------------------------------------------------------------------------- // Set DPRIO output from initial CRAM // --------------------------------------------------------------------------- // PCS Per Channel RX Control Register 1 for Channel 0 assign dprioout[`rrxpcsbypass_en_RXPCS_IDX_0] = init_rrxpcsbypass_en; assign dprioout[`rall_one_dect_only_RXPCS_IDX_0] = init_rall_one_dect_only; assign dprioout[`rbist_clr_rx_RXPCS_IDX_0] = init_rbist_clr_rx; assign dprioout[`rbisten_rx_RXPCS_IDX_0] = init_rbisten_rx; assign dprioout[`rprbs_clr_rslt_rx_RXPCS_IDX_0] = init_rprbs_clr_rslt_rx; assign dprioout[`rprbsen_rx_RXPCS_IDX_0] = init_rprbsen_rx; assign dprioout[`rrx_rd_clk_sel_RXPCS_IDX_0] = init_rrx_rd_clk_sel; assign dprioout[`rclk_2_sel_RXPCS_IDX_1 : `rclk_2_sel_RXPCS_IDX_0] = init_rclk_2_sel; assign dprioout[`rclk_1_sel_RXPCS_IDX_1 : `rclk_1_sel_RXPCS_IDX_0] = init_rclk_1_sel; assign dprioout[`rrcvd_clk_sel_RXPCS_IDX_1 : `rrcvd_clk_sel_RXPCS_IDX_0] = init_rrcvd_clk_sel; assign dprioout[`rfreerun_rx_RXPCS_IDX_0] = init_rfreerun_rx; assign dprioout[`rrxurstpcs_RXPCS_IDX_0] = init_rrxurstpcs; assign dprioout[`reserved_0_TB5_RXPCS_IDX_0] = init_reserved_0_TB5; // PCS Per Channel RX Control Register 2 for Channel 0 assign dprioout[`rcomp_pat_32_RXPCS_IDX_0] = init_rcomp_pat_32; assign dprioout[`rcomp_pat_33_RXPCS_IDX_0] = init_rcomp_pat_33; assign dprioout[`rcomp_pat_34_RXPCS_IDX_0] = init_rcomp_pat_34; assign dprioout[`rcomp_pat_35_RXPCS_IDX_0] = init_rcomp_pat_35; assign dprioout[`rcomp_pat_36_RXPCS_IDX_0] = init_rcomp_pat_36; assign dprioout[`rcomp_pat_37_RXPCS_IDX_0] = init_rcomp_pat_37; assign dprioout[`rcomp_pat_38_RXPCS_IDX_0] = init_rcomp_pat_38; assign dprioout[`rcomp_pat_39_RXPCS_IDX_0] = init_rcomp_pat_39; assign dprioout[`rcomp_size_RXPCS_IDX_2 : `rcomp_size_RXPCS_IDX_0] = init_rcomp_size; assign dprioout[`rcomp_pat_porn_RXPCS_IDX_0] = init_rcomp_pat_porn; assign dprioout[`rdis_rx_disp_RXPCS_IDX_0] = init_rdis_rx_disp; assign dprioout[`rencdt_rising_RXPCS_IDX_0] = init_rencdt_rising; assign dprioout[`resync_badcg_en_RXPCS_IDX_1 : `resync_badcg_en_RXPCS_IDX_0] = init_resync_badcg_en; // PCS Per Channel RX Control Register 3 for Channel 0 assign dprioout[`rcomp_pat_16_RXPCS_IDX_0] = init_rcomp_pat_16; assign dprioout[`rcomp_pat_17_RXPCS_IDX_0] = init_rcomp_pat_17; assign dprioout[`rcomp_pat_18_RXPCS_IDX_0] = init_rcomp_pat_18; assign dprioout[`rcomp_pat_19_RXPCS_IDX_0] = init_rcomp_pat_19; assign dprioout[`rcomp_pat_20_RXPCS_IDX_0] = init_rcomp_pat_20; assign dprioout[`rcomp_pat_21_RXPCS_IDX_0] = init_rcomp_pat_21; assign dprioout[`rcomp_pat_22_RXPCS_IDX_0] = init_rcomp_pat_22; assign dprioout[`rcomp_pat_23_RXPCS_IDX_0] = init_rcomp_pat_23; assign dprioout[`rcomp_pat_24_RXPCS_IDX_0] = init_rcomp_pat_24; assign dprioout[`rcomp_pat_25_RXPCS_IDX_0] = init_rcomp_pat_25; assign dprioout[`rcomp_pat_26_RXPCS_IDX_0] = init_rcomp_pat_26; assign dprioout[`rcomp_pat_27_RXPCS_IDX_0] = init_rcomp_pat_27; assign dprioout[`rcomp_pat_28_RXPCS_IDX_0] = init_rcomp_pat_28; assign dprioout[`rcomp_pat_29_RXPCS_IDX_0] = init_rcomp_pat_29; assign dprioout[`rcomp_pat_30_RXPCS_IDX_0] = init_rcomp_pat_30; assign dprioout[`rcomp_pat_31_RXPCS_IDX_0] = init_rcomp_pat_31; // PCS Per Channel RX Control Register 4 for Channel 0 assign dprioout[`rcomp_pat_0_RXPCS_IDX_0] = init_rcomp_pat_0; assign dprioout[`rcomp_pat_1_RXPCS_IDX_0] = init_rcomp_pat_1; assign dprioout[`rcomp_pat_2_RXPCS_IDX_0] = init_rcomp_pat_2; assign dprioout[`rcomp_pat_3_RXPCS_IDX_0] = init_rcomp_pat_3; assign dprioout[`rcomp_pat_4_RXPCS_IDX_0] = init_rcomp_pat_4; assign dprioout[`rcomp_pat_5_RXPCS_IDX_0] = init_rcomp_pat_5; assign dprioout[`rcomp_pat_6_RXPCS_IDX_0] = init_rcomp_pat_6; assign dprioout[`rcomp_pat_7_RXPCS_IDX_0] = init_rcomp_pat_7; assign dprioout[`rcomp_pat_8_RXPCS_IDX_0] = init_rcomp_pat_8; assign dprioout[`rcomp_pat_9_RXPCS_IDX_0] = init_rcomp_pat_9; assign dprioout[`rcomp_pat_10_RXPCS_IDX_0] = init_rcomp_pat_10; assign dprioout[`rcomp_pat_11_RXPCS_IDX_0] = init_rcomp_pat_11; assign dprioout[`rcomp_pat_12_RXPCS_IDX_0] = init_rcomp_pat_12; assign dprioout[`rcomp_pat_13_RXPCS_IDX_0] = init_rcomp_pat_13; assign dprioout[`rcomp_pat_14_RXPCS_IDX_0] = init_rcomp_pat_14; assign dprioout[`rcomp_pat_15_RXPCS_IDX_0] = init_rcomp_pat_15; // PCS Per Channel RX Control Register 5 for Channel 0 assign dprioout[`rbitloc_rev_en_RXPCS_IDX_0] = init_rbitloc_rev_en; assign dprioout[`rbysync_polinv_en_RXPCS_IDX_0] = init_rbysync_polinv_en; assign dprioout[`rwa_6g_en_RXPCS_IDX_0] = init_rwa_6g_en; assign dprioout[`rosnumber_RXPCS_IDX_1 : `rosnumber_RXPCS_IDX_0] = init_rosnumber; assign dprioout[`rosbased_RXPCS_IDX_0] = init_rosbased; assign dprioout[`rkchar_RXPCS_IDX_0] = init_rkchar; assign dprioout[`renumber_RXPCS_IDX_5 : `renumber_RXPCS_IDX_0] = init_renumber; assign dprioout[`rib_inv_cd_RXPCS_IDX_1 : `rib_inv_cd_RXPCS_IDX_0] = init_rib_inv_cd; assign dprioout[`rsync_sm_dis_RXPCS_IDX_0] = init_rsync_sm_dis; // PCS Per Channel RX Control Register 6 for Channel 0 assign dprioout[`rknumber_RXPCS_IDX_7 : `rknumber_RXPCS_IDX_0] = init_rknumber; assign dprioout[`rgnumber_RXPCS_IDX_7 : `rgnumber_RXPCS_IDX_0] = init_rgnumber; // PCS Per Channel RX Control Register 7 for Channel 0 assign dprioout[`renpolinv_rx_RXPCS_IDX_0] = init_renpolinv_rx; assign dprioout[`rcascaded_8b10b_en_rx_RXPCS_IDX_0] = init_rcascaded_8b10b_en_rx; assign dprioout[`r8b10b_dec_ibm_en_RXPCS_IDX_1 : `r8b10b_dec_ibm_en_RXPCS_IDX_0] = init_r8b10b_dec_ibm_en; assign dprioout[`rendec_rx_RXPCS_IDX_0] = init_rendec_rx; assign dprioout[`rautobtalg_dis_RXPCS_IDX_0] = init_rautobtalg_dis; assign dprioout[`rrlv_en_RXPCS_IDX_0] = init_rrlv_en; assign dprioout[`rlp20ben_RXPCS_IDX_0] = init_rlp20ben; assign dprioout[`rforce_sig_det_pcs_RXPCS_IDX_0] = init_rforce_sig_det_pcs; assign dprioout[`rbyte_rev_en_RXPCS_IDX_0] = init_rbyte_rev_en; assign dprioout[`rrundisp_RXPCS_IDX_5 : `rrundisp_RXPCS_IDX_0] = init_rrundisp; // PCS Per Channel RX Control Register 8 for Channel 0 assign dprioout[`rclkcmpsq1p_0_RXPCS_IDX_0] = init_rclkcmpsq1p_0; assign dprioout[`rclkcmpsq1p_1_RXPCS_IDX_0] = init_rclkcmpsq1p_1; assign dprioout[`rclkcmpsq1p_2_RXPCS_IDX_0] = init_rclkcmpsq1p_2; assign dprioout[`rclkcmpsq1p_3_RXPCS_IDX_0] = init_rclkcmpsq1p_3; assign dprioout[`rclkcmpsq1p_4_RXPCS_IDX_0] = init_rclkcmpsq1p_4; assign dprioout[`rclkcmpsq1p_5_RXPCS_IDX_0] = init_rclkcmpsq1p_5; assign dprioout[`rclkcmpsq1p_6_RXPCS_IDX_0] = init_rclkcmpsq1p_6; assign dprioout[`rclkcmpsq1p_7_RXPCS_IDX_0] = init_rclkcmpsq1p_7; assign dprioout[`rclkcmpsq1p_8_RXPCS_IDX_0] = init_rclkcmpsq1p_8; assign dprioout[`rclkcmpsq1p_9_RXPCS_IDX_0] = init_rclkcmpsq1p_9; assign dprioout[`rclkcmpsqmd_RXPCS_IDX_0] = init_rclkcmpsqmd; assign dprioout[`rclkcmpinsertpad_RXPCS_IDX_0] = init_rclkcmpinsertpad; assign dprioout[`rtruebac2bac_RXPCS_IDX_0] = init_rtruebac2bac; assign dprioout[`rskpsetbased_RXPCS_IDX_0] = init_rskpsetbased; assign dprioout[`rgenericfifo_RXPCS_IDX_0] = init_rgenericfifo; assign dprioout[`rmatchen_RXPCS_IDX_0] = init_rmatchen; // PCS Per Channel RX Control Register 9 for Channel 0 assign dprioout[`rclkcmpsq1p_10_RXPCS_IDX_0] = init_rclkcmpsq1p_10; assign dprioout[`rclkcmpsq1p_11_RXPCS_IDX_0] = init_rclkcmpsq1p_11; assign dprioout[`rclkcmpsq1p_12_RXPCS_IDX_0] = init_rclkcmpsq1p_12; assign dprioout[`rclkcmpsq1p_13_RXPCS_IDX_0] = init_rclkcmpsq1p_13; assign dprioout[`rclkcmpsq1p_14_RXPCS_IDX_0] = init_rclkcmpsq1p_14; assign dprioout[`rclkcmpsq1p_15_RXPCS_IDX_0] = init_rclkcmpsq1p_15; assign dprioout[`rclkcmpsq1p_16_RXPCS_IDX_0] = init_rclkcmpsq1p_16; assign dprioout[`rclkcmpsq1p_17_RXPCS_IDX_0] = init_rclkcmpsq1p_17; assign dprioout[`rclkcmpsq1p_18_RXPCS_IDX_0] = init_rclkcmpsq1p_18; assign dprioout[`rclkcmpsq1p_19_RXPCS_IDX_0] = init_rclkcmpsq1p_19; assign dprioout[`reserved_0_TB13_RXPCS_IDX_0] = init_reserved_0_TB13; assign dprioout[`rclkcmpsq1n_15_RXPCS_IDX_0] = init_rclkcmpsq1n_15; assign dprioout[`rclkcmpsq1n_16_RXPCS_IDX_0] = init_rclkcmpsq1n_16; assign dprioout[`rclkcmpsq1n_17_RXPCS_IDX_0] = init_rclkcmpsq1n_17; assign dprioout[`rclkcmpsq1n_18_RXPCS_IDX_0] = init_rclkcmpsq1n_18; assign dprioout[`rclkcmpsq1n_19_RXPCS_IDX_0] = init_rclkcmpsq1n_19; // PCS Per Channel RX Control Register 10 for Channel 0 assign dprioout[`rclkcmpsq1n_0_RXPCS_IDX_0] = init_rclkcmpsq1n_0; assign dprioout[`rclkcmpsq1n_1_RXPCS_IDX_0] = init_rclkcmpsq1n_1; assign dprioout[`rclkcmpsq1n_2_RXPCS_IDX_0] = init_rclkcmpsq1n_2; assign dprioout[`rclkcmpsq1n_3_RXPCS_IDX_0] = init_rclkcmpsq1n_3; assign dprioout[`rclkcmpsq1n_4_RXPCS_IDX_0] = init_rclkcmpsq1n_4; assign dprioout[`rclkcmpsq1n_5_RXPCS_IDX_0] = init_rclkcmpsq1n_5; assign dprioout[`rclkcmpsq1n_6_RXPCS_IDX_0] = init_rclkcmpsq1n_6; assign dprioout[`rclkcmpsq1n_7_RXPCS_IDX_0] = init_rclkcmpsq1n_7; assign dprioout[`rclkcmpsq1n_8_RXPCS_IDX_0] = init_rclkcmpsq1n_8; assign dprioout[`rclkcmpsq1n_9_RXPCS_IDX_0] = init_rclkcmpsq1n_9; assign dprioout[`reserved_0_TB14_RXPCS_IDX_0] = init_reserved_0_TB14; assign dprioout[`rclkcmpsq1n_10_RXPCS_IDX_0] = init_rclkcmpsq1n_10; assign dprioout[`rclkcmpsq1n_11_RXPCS_IDX_0] = init_rclkcmpsq1n_11; assign dprioout[`rclkcmpsq1n_12_RXPCS_IDX_0] = init_rclkcmpsq1n_12; assign dprioout[`rclkcmpsq1n_13_RXPCS_IDX_0] = init_rclkcmpsq1n_13; assign dprioout[`rclkcmpsq1n_14_RXPCS_IDX_0] = init_rclkcmpsq1n_14; // PCS Per Channel RX Control Register 11 for Channel 0 assign dprioout[`rfull_threshold_RXPCS_IDX_4 : `rfull_threshold_RXPCS_IDX_0] = init_rfull_threshold; assign dprioout[`rdel_threshold_RXPCS_IDX_4 : `rdel_threshold_RXPCS_IDX_0] = init_rdel_threshold; assign dprioout[`rins_threshold_RXPCS_IDX_4 : `rins_threshold_RXPCS_IDX_0] = init_rins_threshold; assign dprioout[`rclkcmp_pipe_en_RXPCS_IDX_0] = init_rclkcmp_pipe_en; // PCS Per Channel RX Control Register 12 for Channel 0 assign dprioout[`rfreq_sel_RXPCS_IDX_0] = init_rfreq_sel; assign dprioout[`rauto_speed_ena_RXPCS_IDX_0] = init_rauto_speed_ena; assign dprioout[`rhip_ena_RXPCS_IDX_0] = init_rhip_ena; assign dprioout[`rpma_done_gen_ena_RXPCS_IDX_0] = init_rpma_done_gen_ena; assign dprioout[`rpma_done_count_16_RXPCS_IDX_0] = init_rpma_done_count_16; assign dprioout[`rpma_done_count_17_RXPCS_IDX_0] = init_rpma_done_count_17; assign dprioout[`reserved_0_TB16_RXPCS_IDX_3 : `reserved_0_TB16_RXPCS_IDX_0] = init_reserved_0_TB16; assign dprioout[`rstart_threshold_RXPCS_IDX_2 : `rstart_threshold_RXPCS_IDX_0] = init_rstart_threshold; assign dprioout[`rempty_threshold_RXPCS_IDX_2 : `rempty_threshold_RXPCS_IDX_0] = init_rempty_threshold; // PCS Per Channel RX Control Register 13 for Channel 0 assign dprioout[`rtest_bus_sel_RXPCS_IDX_3 : `rtest_bus_sel_RXPCS_IDX_0] = init_rtest_bus_sel; assign dprioout[`rautoinsdis_RXPCS_IDX_0] = init_rautoinsdis; assign dprioout[`rphfifopldenrx_RXPCS_IDX_0] = init_rphfifopldenrx; assign dprioout[`rbytordplden_RXPCS_IDX_0] = init_rbytordplden; assign dprioout[`rbyteorden_RXPCS_IDX_1 : `rbyteorden_RXPCS_IDX_0] = init_rbyteorden; assign dprioout[`rbytord_2sym_en_RXPCS_IDX_0] = init_rbytord_2sym_en; assign dprioout[`rinvalid_code_err_only_RXPCS_IDX_0] = init_rinvalid_code_err_only; assign dprioout[`rcmpfifourst_RXPCS_IDX_0] = init_rcmpfifourst; assign dprioout[`rphfifourstrx_RXPCS_IDX_0] = init_rphfifourstrx; assign dprioout[`rdwidth_rx_RXPCS_IDX_0] = init_rdwidth_rx; assign dprioout[`rrxfifo_lowlatency_en_RXPCS_IDX_0] = init_rrxfifo_lowlatency_en; assign dprioout[`rrxfifo_dis_RXPCS_IDX_0] = init_rrxfifo_dis; // PCS Per Channel RX Control Register 14 for Channel 0 assign dprioout[`rbytordpat_0_RXPCS_IDX_0] = init_rbytordpat_0; assign dprioout[`rbytordpat_1_RXPCS_IDX_0] = init_rbytordpat_1; assign dprioout[`rbytordpat_2_RXPCS_IDX_0] = init_rbytordpat_2; assign dprioout[`rbytordpat_3_RXPCS_IDX_0] = init_rbytordpat_3; assign dprioout[`rbytordpat_4_RXPCS_IDX_0] = init_rbytordpat_4; assign dprioout[`rbytordpat_5_RXPCS_IDX_0] = init_rbytordpat_5; assign dprioout[`rbytordpat_6_RXPCS_IDX_0] = init_rbytordpat_6; assign dprioout[`rbytordpat_7_RXPCS_IDX_0] = init_rbytordpat_7; assign dprioout[`rbytordpat_8_RXPCS_IDX_0] = init_rbytordpat_8; assign dprioout[`rbytordpat_9_RXPCS_IDX_0] = init_rbytordpat_9; assign dprioout[`reserved_0_TB18_RXPCS_IDX_5 : `reserved_0_TB18_RXPCS_IDX_0] = init_reserved_0_TB18; // PCS Per Channel RX Control Register 15 for Channel 0 assign dprioout[`rbytordpad_RXPCS_IDX_9 : `rbytordpad_RXPCS_IDX_0] = init_rbytordpad; assign dprioout[`reserved_0_TB19_RXPCS_IDX_5 : `reserved_0_TB19_RXPCS_IDX_0] = init_reserved_0_TB19; // PCS Per Channel RX Control Register 16 for Channel 0 assign dprioout[`rload_shreg_del_RXPCS_IDX_4 : `rload_shreg_del_RXPCS_IDX_0] = init_rload_shreg_del; assign dprioout[`rphystatus_rst_toggle_RXPCS_IDX_0] = init_rphystatus_rst_toggle; assign dprioout[`reidle_com_detect_RXPCS_IDX_1 : `reidle_com_detect_RXPCS_IDX_0] = init_reidle_com_detect; assign dprioout[`rk285detect_RXPCS_IDX_0] = init_rk285detect; assign dprioout[`reidleinferenable_RXPCS_IDX_0] = init_reidleinferenable; assign dprioout[`rphystatus_delay_RXPCS_IDX_2 : `rphystatus_delay_RXPCS_IDX_0] = init_rphystatus_delay; assign dprioout[`rind_error_reporting_RXPCS_IDX_0] = init_rind_error_reporting; assign dprioout[`rrx_detect_bypass_RXPCS_IDX_0] = init_rrx_detect_bypass; assign dprioout[`rrx_pipe_enable_RXPCS_IDX_0] = init_rrx_pipe_enable; // PCS Per Channel RX Control Register 17 for Channel 0 assign dprioout[`rpma_done_count_0_RXPCS_IDX_0] = init_rpma_done_count_0; assign dprioout[`rpma_done_count_1_RXPCS_IDX_0] = init_rpma_done_count_1; assign dprioout[`rpma_done_count_2_RXPCS_IDX_0] = init_rpma_done_count_2; assign dprioout[`rpma_done_count_3_RXPCS_IDX_0] = init_rpma_done_count_3; assign dprioout[`rpma_done_count_4_RXPCS_IDX_0] = init_rpma_done_count_4; assign dprioout[`rpma_done_count_5_RXPCS_IDX_0] = init_rpma_done_count_5; assign dprioout[`rpma_done_count_6_RXPCS_IDX_0] = init_rpma_done_count_6; assign dprioout[`rpma_done_count_7_RXPCS_IDX_0] = init_rpma_done_count_7; assign dprioout[`rpma_done_count_8_RXPCS_IDX_0] = init_rpma_done_count_8; assign dprioout[`rpma_done_count_9_RXPCS_IDX_0] = init_rpma_done_count_9; assign dprioout[`rpma_done_count_10_RXPCS_IDX_0] = init_rpma_done_count_10; assign dprioout[`rpma_done_count_11_RXPCS_IDX_0] = init_rpma_done_count_11; assign dprioout[`rpma_done_count_12_RXPCS_IDX_0] = init_rpma_done_count_12; assign dprioout[`rpma_done_count_13_RXPCS_IDX_0] = init_rpma_done_count_13; assign dprioout[`rpma_done_count_14_RXPCS_IDX_0] = init_rpma_done_count_14; assign dprioout[`rpma_done_count_15_RXPCS_IDX_0] = init_rpma_done_count_15; // PCS Per Channel RX Control Register 18 for Channel 0 assign dprioout[`rbytordpat_10_RXPCS_IDX_0] = init_rbytordpat_10; assign dprioout[`rbytordpat_11_RXPCS_IDX_0] = init_rbytordpat_11; assign dprioout[`rbytordpat_12_RXPCS_IDX_0] = init_rbytordpat_12; assign dprioout[`rbytordpat_13_RXPCS_IDX_0] = init_rbytordpat_13; assign dprioout[`rbytordpat_14_RXPCS_IDX_0] = init_rbytordpat_14; assign dprioout[`rbytordpat_15_RXPCS_IDX_0] = init_rbytordpat_15; assign dprioout[`rbytordpat_16_RXPCS_IDX_0] = init_rbytordpat_16; assign dprioout[`rbytordpat_17_RXPCS_IDX_0] = init_rbytordpat_17; assign dprioout[`rbytordpat_18_RXPCS_IDX_0] = init_rbytordpat_18; assign dprioout[`rbytordpat_19_RXPCS_IDX_0] = init_rbytordpat_19; assign dprioout[`rbytord_6g_mask_en_RXPCS_IDX_0] = init_rbytord_6g_mask_en; assign dprioout[`rbytord_s2gx_RXPCS_IDX_0] = init_rbytord_s2gx; assign dprioout[`reserved_0_TB22_RXPCS_IDX_0] = init_reserved_0_TB22; assign dprioout[`rcdr_ctrl_en_RXPCS_IDX_0] = init_rcdr_ctrl_en; assign dprioout[`rrxpcsclkpwdn_RXPCS_IDX_0] = init_rrxpcsclkpwdn; assign dprioout[`rerr_flags_sel_RXPCS_IDX_0] = init_rerr_flags_sel; // PCS Per Channel RX Control Register 19 for Channel 0 assign dprioout[`rwait_count_RXPCS_IDX_7 : `rwait_count_RXPCS_IDX_0] = init_rwait_count; assign dprioout[`reserved_0_TB23_RXPCS_IDX_7 : `reserved_0_TB23_RXPCS_IDX_0] = init_reserved_0_TB23; // PCS Per Channel RX Control Register 20 for Channel 0 assign dprioout[`rfts_count_RXPCS_IDX_9 : `rfts_count_RXPCS_IDX_0] = init_rfts_count; assign dprioout[`rwait_for_phfifo_cnt_RXPCS_IDX_5 : `rwait_for_phfifo_cnt_RXPCS_IDX_0] = init_rwait_for_phfifo_cnt; // PCS Per Channel RX Control Register 21 for Channel 0 assign dprioout[`rppm_meas_delay_RXPCS_IDX_0] = init_rppm_meas_delay; assign dprioout[`rcid_len_rx_RXPCS_IDX_7 : `rcid_len_rx_RXPCS_IDX_0] = init_rcid_len_rx; assign dprioout[`rcid_pattern_rx_RXPCS_IDX_0] = init_rcid_pattern_rx; assign dprioout[`rpcs_wrapback_en_RXPCS_IDX_0] = init_rpcs_wrapback_en; assign dprioout[`reserved_0_TB25_RXPCS_IDX_4 : `reserved_0_TB25_RXPCS_IDX_0] = init_reserved_0_TB25; // PCS Per Channel RX Control Register 22 for Channel 0 assign dprioout[`rauto_pc_en_cnt_RXPCS_IDX_4 : `rauto_pc_en_cnt_RXPCS_IDX_0] = init_rauto_pc_en_cnt; assign dprioout[`reserved_1_TB26_RXPCS_IDX_0] = init_reserved_1_TB26; assign dprioout[`rauto_deassert_pc_rst_cnt_RXPCS_IDX_3 : `rauto_deassert_pc_rst_cnt_RXPCS_IDX_0] = init_rauto_deassert_pc_rst_cnt; assign dprioout[`reserved_0_TB26_RXPCS_IDX_0] = init_reserved_0_TB26; assign dprioout[`rpipeline_bypass_rx_RXPCS_IDX_0] = init_rpipeline_bypass_rx; assign dprioout[`rself_sw_en_rx_RXPCS_IDX_0] = init_rself_sw_en_rx; assign dprioout[`rrxvalid_mask_RXPCS_IDX_0] = init_rrxvalid_mask; assign dprioout[`rcid_en_RXPCS_IDX_0] = init_rcid_en; assign dprioout[`rphfifo_regmode_rx_RXPCS_IDX_0] = init_rphfifo_regmode_rx; // PCS Per Channel RX Control Register 23 for Channel 0 assign dprioout[`rmask_count_RXPCS_IDX_9 : `rmask_count_RXPCS_IDX_0] = init_rmask_count; assign dprioout[`rgen1_sigdet_ena_RXPCS_IDX_0] = init_rgen1_sigdet_ena; assign dprioout[`riei_eios_priority_dis_RXPCS_IDX_0] = init_riei_eios_priority_dis; assign dprioout[`reserved_0_TB27_RXPCS_IDX_3 : `reserved_0_TB27_RXPCS_IDX_0] = init_reserved_0_TB27; //////////////////////////////////////////////////////////////////////////////// // select CRAMs between DPIRO vs. parameters --------------------------------// //////////////////////////////////////////////////////////////////////////////// wire dpriodisable_in; assign dpriodisable_in = (dpriodisable === 1'b0) ? 1'b0 : 1'b1; // Manual Section assign cram_rpma_doublewidth_rx = (dpriodisable_in == 1'b1) ? init_rpma_doublewidth_rx : dprioin_rpma_doublewidth_rx; // enabled assign cram_rpmadwidth_rx = (dpriodisable_in == 1'b1) ? init_rpmadwidth_rx : dprioin_rpmadwidth_rx; // enabled assign cram_rendec_data_sel_rx = (dpriodisable_in == 1'b1) ? init_rendec_data_sel_rx : dprioin_rendec_data_sel_rx; assign cram_rindv_rx = (dpriodisable_in == 1'b1) ? init_rindv_rx : dprioin_rindv_rx; assign cram_rdeskewen = (dpriodisable_in == 1'b1) ? init_rdeskewen : dprioin_rdeskewen; assign cram_rmaster_rx = (dpriodisable_in == 1'b1) ? init_rmaster_rx : dprioin_rmaster_rx; assign cram_rmaster_up_rx = (dpriodisable_in == 1'b1) ? init_rmaster_up_rx : dprioin_rmaster_up_rx; assign cram_rdskposdisp = (dpriodisable_in == 1'b1) ? init_rdskposdisp : dprioin_rdskposdisp; assign cram_dskwclksel = (dpriodisable_in == 1'b1) ? init_dskwclksel : dprioin_dskwclksel; assign cram_is_lane0 = (dpriodisable_in == 1'b1) ? init_is_lane0 : dprioin_is_lane0; assign cram_rbist_sel = (dpriodisable_in == 1'b1) ? init_rbist_sel : dprioin_rbist_sel; assign cram_rclkcmppos = (dpriodisable_in == 1'b1) ? init_rclkcmppos : dprioin_rclkcmppos; assign cram_rcxpat_chnl_en = (dpriodisable_in == 1'b1) ? init_rcxpat_chnl_en : dprioin_rcxpat_chnl_en; assign cram_rdskchrp = (dpriodisable_in == 1'b1) ? init_rdskchrp : dprioin_rdskchrp; assign cram_renpolinv_en = (dpriodisable_in == 1'b1) ? init_renpolinv_en : dprioin_renpolinv_en; assign cram_rforce0_freqdet = (dpriodisable_in == 1'b1) ? init_rforce0_freqdet : dprioin_rforce0_freqdet; assign cram_rforce1_freqdet = (dpriodisable_in == 1'b1) ? init_rforce1_freqdet : dprioin_rforce1_freqdet; assign cram_rphfifourstenrx = (dpriodisable_in == 1'b1) ? init_rphfifourstenrx : dprioin_rphfifourstenrx; assign cram_rppm_gen1_2xcnt_en = (dpriodisable_in == 1'b1) ? init_rppm_gen1_2xcnt_en : dprioin_rppm_gen1_2xcnt_en; assign cram_rppm_post_eidle_del = (dpriodisable_in == 1'b1) ? init_rppm_post_eidle_del : dprioin_rppm_post_eidle_del; assign cram_rppmsel = (dpriodisable_in == 1'b1) ? init_rppmsel : dprioin_rppmsel; assign cram_rprbs_sel = (dpriodisable_in == 1'b1) ? init_rprbs_sel : dprioin_rprbs_sel; assign cram_rrdwidth_rx = (dpriodisable_in == 1'b1) ? init_rrdwidth_rx : dprioin_rrdwidth_rx; assign cram_rrx_fifo_dis = (dpriodisable_in == 1'b1) ? init_rrx_fifo_dis : dprioin_rrx_fifo_dis; assign cram_rtx_elec_idle_delay = (dpriodisable_in == 1'b1) ? init_rtx_elec_idle_delay : dprioin_rtx_elec_idle_delay; assign cram_rtx_pipe_enable = (dpriodisable_in == 1'b1) ? init_rtx_pipe_enable : dprioin_rtx_pipe_enable; assign cram_scan_mode = (dpriodisable_in == 1'b1) ? init_scan_mode : dprioin_scan_mode; assign cram_sel_gp_md = (dpriodisable_in == 1'b1) ? init_sel_gp_md : dprioin_sel_gp_md; // --------------------------------------------------------------------------- // Set DPRIO CRAM // --------------------------------------------------------------------------- // PCS Per Channel RX Control Register 1 for Channel 0 assign cram_rrxpcsbypass_en = (dpriodisable_in == 1'b1) ? init_rrxpcsbypass_en : dprioin_rrxpcsbypass_en; assign cram_rall_one_dect_only = (dpriodisable_in == 1'b1) ? init_rall_one_dect_only : dprioin_rall_one_dect_only; assign cram_rbist_clr_rx = (dpriodisable_in == 1'b1) ? init_rbist_clr_rx : dprioin_rbist_clr_rx; assign cram_rbisten_rx = (dpriodisable_in == 1'b1) ? init_rbisten_rx : dprioin_rbisten_rx; assign cram_rprbs_clr_rslt_rx = (dpriodisable_in == 1'b1) ? init_rprbs_clr_rslt_rx : dprioin_rprbs_clr_rslt_rx; assign cram_rprbsen_rx = (dpriodisable_in == 1'b1) ? init_rprbsen_rx : dprioin_rprbsen_rx; assign cram_rrx_rd_clk_sel = (dpriodisable_in == 1'b1) ? init_rrx_rd_clk_sel : dprioin_rrx_rd_clk_sel; assign cram_rclk_2_sel = (dpriodisable_in == 1'b1) ? init_rclk_2_sel : dprioin_rclk_2_sel; assign cram_rclk_1_sel = (dpriodisable_in == 1'b1) ? init_rclk_1_sel : dprioin_rclk_1_sel; assign cram_rrcvd_clk_sel = (dpriodisable_in == 1'b1) ? init_rrcvd_clk_sel : dprioin_rrcvd_clk_sel; assign cram_rfreerun_rx = (dpriodisable_in == 1'b1) ? init_rfreerun_rx : dprioin_rfreerun_rx; assign cram_rrxurstpcs = (dpriodisable_in == 1'b1) ? init_rrxurstpcs : dprioin_rrxurstpcs; assign cram_reserved_0_TB5 = (dpriodisable_in == 1'b1) ? init_reserved_0_TB5 : dprioin_reserved_0_TB5; // PCS Per Channel RX Control Register 2 for Channel 0 assign cram_rcomp_pat_32 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_32 : dprioin_rcomp_pat_32; assign cram_rcomp_pat_33 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_33 : dprioin_rcomp_pat_33; assign cram_rcomp_pat_34 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_34 : dprioin_rcomp_pat_34; assign cram_rcomp_pat_35 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_35 : dprioin_rcomp_pat_35; assign cram_rcomp_pat_36 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_36 : dprioin_rcomp_pat_36; assign cram_rcomp_pat_37 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_37 : dprioin_rcomp_pat_37; assign cram_rcomp_pat_38 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_38 : dprioin_rcomp_pat_38; assign cram_rcomp_pat_39 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_39 : dprioin_rcomp_pat_39; assign cram_rcomp_size = (dpriodisable_in == 1'b1) ? init_rcomp_size : dprioin_rcomp_size; assign cram_rcomp_pat_porn = (dpriodisable_in == 1'b1) ? init_rcomp_pat_porn : dprioin_rcomp_pat_porn; assign cram_rdis_rx_disp = (dpriodisable_in == 1'b1) ? init_rdis_rx_disp : dprioin_rdis_rx_disp; assign cram_rencdt_rising = (dpriodisable_in == 1'b1) ? init_rencdt_rising : dprioin_rencdt_rising; assign cram_resync_badcg_en = (dpriodisable_in == 1'b1) ? init_resync_badcg_en : dprioin_resync_badcg_en; // PCS Per Channel RX Control Register 3 for Channel 0 assign cram_rcomp_pat_16 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_16 : dprioin_rcomp_pat_16; assign cram_rcomp_pat_17 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_17 : dprioin_rcomp_pat_17; assign cram_rcomp_pat_18 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_18 : dprioin_rcomp_pat_18; assign cram_rcomp_pat_19 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_19 : dprioin_rcomp_pat_19; assign cram_rcomp_pat_20 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_20 : dprioin_rcomp_pat_20; assign cram_rcomp_pat_21 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_21 : dprioin_rcomp_pat_21; assign cram_rcomp_pat_22 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_22 : dprioin_rcomp_pat_22; assign cram_rcomp_pat_23 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_23 : dprioin_rcomp_pat_23; assign cram_rcomp_pat_24 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_24 : dprioin_rcomp_pat_24; assign cram_rcomp_pat_25 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_25 : dprioin_rcomp_pat_25; assign cram_rcomp_pat_26 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_26 : dprioin_rcomp_pat_26; assign cram_rcomp_pat_27 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_27 : dprioin_rcomp_pat_27; assign cram_rcomp_pat_28 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_28 : dprioin_rcomp_pat_28; assign cram_rcomp_pat_29 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_29 : dprioin_rcomp_pat_29; assign cram_rcomp_pat_30 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_30 : dprioin_rcomp_pat_30; assign cram_rcomp_pat_31 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_31 : dprioin_rcomp_pat_31; // PCS Per Channel RX Control Register 4 for Channel 0 assign cram_rcomp_pat_0 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_0 : dprioin_rcomp_pat_0; assign cram_rcomp_pat_1 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_1 : dprioin_rcomp_pat_1; assign cram_rcomp_pat_2 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_2 : dprioin_rcomp_pat_2; assign cram_rcomp_pat_3 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_3 : dprioin_rcomp_pat_3; assign cram_rcomp_pat_4 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_4 : dprioin_rcomp_pat_4; assign cram_rcomp_pat_5 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_5 : dprioin_rcomp_pat_5; assign cram_rcomp_pat_6 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_6 : dprioin_rcomp_pat_6; assign cram_rcomp_pat_7 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_7 : dprioin_rcomp_pat_7; assign cram_rcomp_pat_8 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_8 : dprioin_rcomp_pat_8; assign cram_rcomp_pat_9 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_9 : dprioin_rcomp_pat_9; assign cram_rcomp_pat_10 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_10 : dprioin_rcomp_pat_10; assign cram_rcomp_pat_11 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_11 : dprioin_rcomp_pat_11; assign cram_rcomp_pat_12 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_12 : dprioin_rcomp_pat_12; assign cram_rcomp_pat_13 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_13 : dprioin_rcomp_pat_13; assign cram_rcomp_pat_14 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_14 : dprioin_rcomp_pat_14; assign cram_rcomp_pat_15 = (dpriodisable_in == 1'b1) ? init_rcomp_pat_15 : dprioin_rcomp_pat_15; // PCS Per Channel RX Control Register 5 for Channel 0 assign cram_rbitloc_rev_en = (dpriodisable_in == 1'b1) ? init_rbitloc_rev_en : dprioin_rbitloc_rev_en; assign cram_rbysync_polinv_en = (dpriodisable_in == 1'b1) ? init_rbysync_polinv_en : dprioin_rbysync_polinv_en; assign cram_rwa_6g_en = (dpriodisable_in == 1'b1) ? init_rwa_6g_en : dprioin_rwa_6g_en; assign cram_rosnumber = (dpriodisable_in == 1'b1) ? init_rosnumber : dprioin_rosnumber; assign cram_rosbased = (dpriodisable_in == 1'b1) ? init_rosbased : dprioin_rosbased; assign cram_rkchar = (dpriodisable_in == 1'b1) ? init_rkchar : dprioin_rkchar; assign cram_renumber = (dpriodisable_in == 1'b1) ? init_renumber : dprioin_renumber; assign cram_rib_inv_cd = (dpriodisable_in == 1'b1) ? init_rib_inv_cd : dprioin_rib_inv_cd; assign cram_rsync_sm_dis = (dpriodisable_in == 1'b1) ? init_rsync_sm_dis : dprioin_rsync_sm_dis; // PCS Per Channel RX Control Register 6 for Channel 0 assign cram_rknumber = (dpriodisable_in == 1'b1) ? init_rknumber : dprioin_rknumber; assign cram_rgnumber = (dpriodisable_in == 1'b1) ? init_rgnumber : dprioin_rgnumber; // PCS Per Channel RX Control Register 7 for Channel 0 assign cram_renpolinv_rx = (dpriodisable_in == 1'b1) ? init_renpolinv_rx : dprioin_renpolinv_rx; assign cram_rcascaded_8b10b_en_rx = (dpriodisable_in == 1'b1) ? init_rcascaded_8b10b_en_rx : dprioin_rcascaded_8b10b_en_rx; assign cram_r8b10b_dec_ibm_en = (dpriodisable_in == 1'b1) ? init_r8b10b_dec_ibm_en : dprioin_r8b10b_dec_ibm_en; assign cram_rendec_rx = (dpriodisable_in == 1'b1) ? init_rendec_rx : dprioin_rendec_rx; assign cram_rautobtalg_dis = (dpriodisable_in == 1'b1) ? init_rautobtalg_dis : dprioin_rautobtalg_dis; assign cram_rrlv_en = (dpriodisable_in == 1'b1) ? init_rrlv_en : dprioin_rrlv_en; assign cram_rlp20ben = (dpriodisable_in == 1'b1) ? init_rlp20ben : dprioin_rlp20ben; assign cram_rforce_sig_det_pcs = (dpriodisable_in == 1'b1) ? init_rforce_sig_det_pcs : dprioin_rforce_sig_det_pcs; assign cram_rbyte_rev_en = (dpriodisable_in == 1'b1) ? init_rbyte_rev_en : dprioin_rbyte_rev_en; assign cram_rrundisp = (dpriodisable_in == 1'b1) ? init_rrundisp : dprioin_rrundisp; // PCS Per Channel RX Control Register 8 for Channel 0 assign cram_rclkcmpsq1p_0 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1p_0 : dprioin_rclkcmpsq1p_0; assign cram_rclkcmpsq1p_1 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1p_1 : dprioin_rclkcmpsq1p_1; assign cram_rclkcmpsq1p_2 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1p_2 : dprioin_rclkcmpsq1p_2; assign cram_rclkcmpsq1p_3 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1p_3 : dprioin_rclkcmpsq1p_3; assign cram_rclkcmpsq1p_4 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1p_4 : dprioin_rclkcmpsq1p_4; assign cram_rclkcmpsq1p_5 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1p_5 : dprioin_rclkcmpsq1p_5; assign cram_rclkcmpsq1p_6 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1p_6 : dprioin_rclkcmpsq1p_6; assign cram_rclkcmpsq1p_7 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1p_7 : dprioin_rclkcmpsq1p_7; assign cram_rclkcmpsq1p_8 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1p_8 : dprioin_rclkcmpsq1p_8; assign cram_rclkcmpsq1p_9 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1p_9 : dprioin_rclkcmpsq1p_9; assign cram_rclkcmpsqmd = (dpriodisable_in == 1'b1) ? init_rclkcmpsqmd : dprioin_rclkcmpsqmd; assign cram_rclkcmpinsertpad = (dpriodisable_in == 1'b1) ? init_rclkcmpinsertpad : dprioin_rclkcmpinsertpad; assign cram_rtruebac2bac = (dpriodisable_in == 1'b1) ? init_rtruebac2bac : dprioin_rtruebac2bac; assign cram_rskpsetbased = (dpriodisable_in == 1'b1) ? init_rskpsetbased : dprioin_rskpsetbased; assign cram_rgenericfifo = (dpriodisable_in == 1'b1) ? init_rgenericfifo : dprioin_rgenericfifo; assign cram_rmatchen = (dpriodisable_in == 1'b1) ? init_rmatchen : dprioin_rmatchen; // PCS Per Channel RX Control Register 9 for Channel 0 assign cram_rclkcmpsq1p_10 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1p_10 : dprioin_rclkcmpsq1p_10; assign cram_rclkcmpsq1p_11 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1p_11 : dprioin_rclkcmpsq1p_11; assign cram_rclkcmpsq1p_12 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1p_12 : dprioin_rclkcmpsq1p_12; assign cram_rclkcmpsq1p_13 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1p_13 : dprioin_rclkcmpsq1p_13; assign cram_rclkcmpsq1p_14 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1p_14 : dprioin_rclkcmpsq1p_14; assign cram_rclkcmpsq1p_15 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1p_15 : dprioin_rclkcmpsq1p_15; assign cram_rclkcmpsq1p_16 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1p_16 : dprioin_rclkcmpsq1p_16; assign cram_rclkcmpsq1p_17 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1p_17 : dprioin_rclkcmpsq1p_17; assign cram_rclkcmpsq1p_18 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1p_18 : dprioin_rclkcmpsq1p_18; assign cram_rclkcmpsq1p_19 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1p_19 : dprioin_rclkcmpsq1p_19; assign cram_reserved_0_TB13 = (dpriodisable_in == 1'b1) ? init_reserved_0_TB13 : dprioin_reserved_0_TB13; assign cram_rclkcmpsq1n_15 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1n_15 : dprioin_rclkcmpsq1n_15; assign cram_rclkcmpsq1n_16 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1n_16 : dprioin_rclkcmpsq1n_16; assign cram_rclkcmpsq1n_17 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1n_17 : dprioin_rclkcmpsq1n_17; assign cram_rclkcmpsq1n_18 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1n_18 : dprioin_rclkcmpsq1n_18; assign cram_rclkcmpsq1n_19 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1n_19 : dprioin_rclkcmpsq1n_19; // PCS Per Channel RX Control Register 10 for Channel 0 assign cram_rclkcmpsq1n_0 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1n_0 : dprioin_rclkcmpsq1n_0; assign cram_rclkcmpsq1n_1 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1n_1 : dprioin_rclkcmpsq1n_1; assign cram_rclkcmpsq1n_2 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1n_2 : dprioin_rclkcmpsq1n_2; assign cram_rclkcmpsq1n_3 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1n_3 : dprioin_rclkcmpsq1n_3; assign cram_rclkcmpsq1n_4 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1n_4 : dprioin_rclkcmpsq1n_4; assign cram_rclkcmpsq1n_5 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1n_5 : dprioin_rclkcmpsq1n_5; assign cram_rclkcmpsq1n_6 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1n_6 : dprioin_rclkcmpsq1n_6; assign cram_rclkcmpsq1n_7 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1n_7 : dprioin_rclkcmpsq1n_7; assign cram_rclkcmpsq1n_8 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1n_8 : dprioin_rclkcmpsq1n_8; assign cram_rclkcmpsq1n_9 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1n_9 : dprioin_rclkcmpsq1n_9; assign cram_reserved_0_TB14 = (dpriodisable_in == 1'b1) ? init_reserved_0_TB14 : dprioin_reserved_0_TB14; assign cram_rclkcmpsq1n_10 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1n_10 : dprioin_rclkcmpsq1n_10; assign cram_rclkcmpsq1n_11 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1n_11 : dprioin_rclkcmpsq1n_11; assign cram_rclkcmpsq1n_12 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1n_12 : dprioin_rclkcmpsq1n_12; assign cram_rclkcmpsq1n_13 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1n_13 : dprioin_rclkcmpsq1n_13; assign cram_rclkcmpsq1n_14 = (dpriodisable_in == 1'b1) ? init_rclkcmpsq1n_14 : dprioin_rclkcmpsq1n_14; // PCS Per Channel RX Control Register 11 for Channel 0 assign cram_rfull_threshold = (dpriodisable_in == 1'b1) ? init_rfull_threshold : dprioin_rfull_threshold; assign cram_rdel_threshold = (dpriodisable_in == 1'b1) ? init_rdel_threshold : dprioin_rdel_threshold; assign cram_rins_threshold = (dpriodisable_in == 1'b1) ? init_rins_threshold : dprioin_rins_threshold; assign cram_rclkcmp_pipe_en = (dpriodisable_in == 1'b1) ? init_rclkcmp_pipe_en : dprioin_rclkcmp_pipe_en; // PCS Per Channel RX Control Register 12 for Channel 0 assign cram_rfreq_sel = (dpriodisable_in == 1'b1) ? init_rfreq_sel : dprioin_rfreq_sel; assign cram_rauto_speed_ena = (dpriodisable_in == 1'b1) ? init_rauto_speed_ena : dprioin_rauto_speed_ena; assign cram_rhip_ena = (dpriodisable_in == 1'b1) ? init_rhip_ena : dprioin_rhip_ena; assign cram_rpma_done_gen_ena = (dpriodisable_in == 1'b1) ? init_rpma_done_gen_ena : dprioin_rpma_done_gen_ena; assign cram_rpma_done_count_16 = init_rpma_done_count_16; // harden it to speed up sim (spr319896) - hw setting is 250000 assign cram_rpma_done_count_17 = init_rpma_done_count_17; // harden it - init_rpma_done_count_17 : dprioin_rpma_done_count_17; assign cram_reserved_0_TB16 = (dpriodisable_in == 1'b1) ? init_reserved_0_TB16 : dprioin_reserved_0_TB16; assign cram_rstart_threshold = (dpriodisable_in == 1'b1) ? init_rstart_threshold : dprioin_rstart_threshold; assign cram_rempty_threshold = (dpriodisable_in == 1'b1) ? init_rempty_threshold : dprioin_rempty_threshold; // PCS Per Channel RX Control Register 13 for Channel 0 assign cram_rtest_bus_sel = (dpriodisable_in == 1'b1) ? init_rtest_bus_sel : dprioin_rtest_bus_sel; assign cram_rautoinsdis = (dpriodisable_in == 1'b1) ? init_rautoinsdis : dprioin_rautoinsdis; assign cram_rphfifopldenrx = (dpriodisable_in == 1'b1) ? init_rphfifopldenrx : dprioin_rphfifopldenrx; assign cram_rbytordplden = (dpriodisable_in == 1'b1) ? init_rbytordplden : dprioin_rbytordplden; assign cram_rbyteorden = (dpriodisable_in == 1'b1) ? init_rbyteorden : dprioin_rbyteorden; assign cram_rbytord_2sym_en = (dpriodisable_in == 1'b1) ? init_rbytord_2sym_en : dprioin_rbytord_2sym_en; assign cram_rinvalid_code_err_only = (dpriodisable_in == 1'b1) ? init_rinvalid_code_err_only : dprioin_rinvalid_code_err_only; assign cram_rcmpfifourst = (dpriodisable_in == 1'b1) ? init_rcmpfifourst : dprioin_rcmpfifourst; assign cram_rphfifourstrx = (dpriodisable_in == 1'b1) ? init_rphfifourstrx : dprioin_rphfifourstrx; assign cram_rdwidth_rx = (dpriodisable_in == 1'b1) ? init_rdwidth_rx : dprioin_rdwidth_rx; assign cram_rrxfifo_lowlatency_en = (dpriodisable_in == 1'b1) ? init_rrxfifo_lowlatency_en : dprioin_rrxfifo_lowlatency_en; assign cram_rrxfifo_dis = (dpriodisable_in == 1'b1) ? init_rrxfifo_dis : dprioin_rrxfifo_dis; // PCS Per Channel RX Control Register 14 for Channel 0 assign cram_rbytordpat_0 = (dpriodisable_in == 1'b1) ? init_rbytordpat_0 : dprioin_rbytordpat_0; assign cram_rbytordpat_1 = (dpriodisable_in == 1'b1) ? init_rbytordpat_1 : dprioin_rbytordpat_1; assign cram_rbytordpat_2 = (dpriodisable_in == 1'b1) ? init_rbytordpat_2 : dprioin_rbytordpat_2; assign cram_rbytordpat_3 = (dpriodisable_in == 1'b1) ? init_rbytordpat_3 : dprioin_rbytordpat_3; assign cram_rbytordpat_4 = (dpriodisable_in == 1'b1) ? init_rbytordpat_4 : dprioin_rbytordpat_4; assign cram_rbytordpat_5 = (dpriodisable_in == 1'b1) ? init_rbytordpat_5 : dprioin_rbytordpat_5; assign cram_rbytordpat_6 = (dpriodisable_in == 1'b1) ? init_rbytordpat_6 : dprioin_rbytordpat_6; assign cram_rbytordpat_7 = (dpriodisable_in == 1'b1) ? init_rbytordpat_7 : dprioin_rbytordpat_7; assign cram_rbytordpat_8 = (dpriodisable_in == 1'b1) ? init_rbytordpat_8 : dprioin_rbytordpat_8; assign cram_rbytordpat_9 = (dpriodisable_in == 1'b1) ? init_rbytordpat_9 : dprioin_rbytordpat_9; assign cram_reserved_0_TB18 = (dpriodisable_in == 1'b1) ? init_reserved_0_TB18 : dprioin_reserved_0_TB18; // PCS Per Channel RX Control Register 15 for Channel 0 assign cram_rbytordpad = (dpriodisable_in == 1'b1) ? init_rbytordpad : dprioin_rbytordpad; assign cram_reserved_0_TB19 = (dpriodisable_in == 1'b1) ? init_reserved_0_TB19 : dprioin_reserved_0_TB19; // PCS Per Channel RX Control Register 16 for Channel 0 assign cram_rload_shreg_del = (dpriodisable_in == 1'b1) ? init_rload_shreg_del : dprioin_rload_shreg_del; assign cram_rphystatus_rst_toggle = (dpriodisable_in == 1'b1) ? init_rphystatus_rst_toggle : dprioin_rphystatus_rst_toggle; assign cram_reidle_com_detect = (dpriodisable_in == 1'b1) ? init_reidle_com_detect : dprioin_reidle_com_detect; assign cram_rk285detect = (dpriodisable_in == 1'b1) ? init_rk285detect : dprioin_rk285detect; assign cram_reidleinferenable = (dpriodisable_in == 1'b1) ? init_reidleinferenable : dprioin_reidleinferenable; assign cram_rphystatus_delay = (dpriodisable_in == 1'b1) ? init_rphystatus_delay : dprioin_rphystatus_delay; assign cram_rind_error_reporting = (dpriodisable_in == 1'b1) ? init_rind_error_reporting : dprioin_rind_error_reporting; assign cram_rrx_detect_bypass = (dpriodisable_in == 1'b1) ? init_rrx_detect_bypass : dprioin_rrx_detect_bypass; assign cram_rrx_pipe_enable = (dpriodisable_in == 1'b1) ? init_rrx_pipe_enable : dprioin_rrx_pipe_enable; // PCS Per Channel RX Control Register 17 for Channel 0 // harden it to speed up sim (spr319896) assign cram_rpma_done_count_0 = init_rpma_done_count_0; assign cram_rpma_done_count_1 = init_rpma_done_count_1; assign cram_rpma_done_count_2 = init_rpma_done_count_2; assign cram_rpma_done_count_3 = init_rpma_done_count_3; assign cram_rpma_done_count_4 = init_rpma_done_count_4; assign cram_rpma_done_count_5 = init_rpma_done_count_5; assign cram_rpma_done_count_6 = init_rpma_done_count_6; assign cram_rpma_done_count_7 = init_rpma_done_count_7; assign cram_rpma_done_count_8 = init_rpma_done_count_8; assign cram_rpma_done_count_9 = init_rpma_done_count_9; assign cram_rpma_done_count_10 = init_rpma_done_count_10; assign cram_rpma_done_count_11 = init_rpma_done_count_11; assign cram_rpma_done_count_12 = init_rpma_done_count_12; assign cram_rpma_done_count_13 = init_rpma_done_count_13; assign cram_rpma_done_count_14 = init_rpma_done_count_14; assign cram_rpma_done_count_15 = init_rpma_done_count_15; // PCS Per Channel RX Control Register 18 for Channel 0 assign cram_rbytordpat_10 = (dpriodisable_in == 1'b1) ? init_rbytordpat_10 : dprioin_rbytordpat_10; assign cram_rbytordpat_11 = (dpriodisable_in == 1'b1) ? init_rbytordpat_11 : dprioin_rbytordpat_11; assign cram_rbytordpat_12 = (dpriodisable_in == 1'b1) ? init_rbytordpat_12 : dprioin_rbytordpat_12; assign cram_rbytordpat_13 = (dpriodisable_in == 1'b1) ? init_rbytordpat_13 : dprioin_rbytordpat_13; assign cram_rbytordpat_14 = (dpriodisable_in == 1'b1) ? init_rbytordpat_14 : dprioin_rbytordpat_14; assign cram_rbytordpat_15 = (dpriodisable_in == 1'b1) ? init_rbytordpat_15 : dprioin_rbytordpat_15; assign cram_rbytordpat_16 = (dpriodisable_in == 1'b1) ? init_rbytordpat_16 : dprioin_rbytordpat_16; assign cram_rbytordpat_17 = (dpriodisable_in == 1'b1) ? init_rbytordpat_17 : dprioin_rbytordpat_17; assign cram_rbytordpat_18 = (dpriodisable_in == 1'b1) ? init_rbytordpat_18 : dprioin_rbytordpat_18; assign cram_rbytordpat_19 = (dpriodisable_in == 1'b1) ? init_rbytordpat_19 : dprioin_rbytordpat_19; assign cram_rbytord_6g_mask_en = (dpriodisable_in == 1'b1) ? init_rbytord_6g_mask_en : dprioin_rbytord_6g_mask_en; assign cram_rbytord_s2gx = (dpriodisable_in == 1'b1) ? init_rbytord_s2gx : dprioin_rbytord_s2gx; assign cram_reserved_0_TB22 = (dpriodisable_in == 1'b1) ? init_reserved_0_TB22 : dprioin_reserved_0_TB22; assign cram_rcdr_ctrl_en = (dpriodisable_in == 1'b1) ? init_rcdr_ctrl_en : dprioin_rcdr_ctrl_en; assign cram_rrxpcsclkpwdn = (dpriodisable_in == 1'b1) ? init_rrxpcsclkpwdn : dprioin_rrxpcsclkpwdn; assign cram_rerr_flags_sel = (dpriodisable_in == 1'b1) ? init_rerr_flags_sel : dprioin_rerr_flags_sel; // PCS Per Channel RX Control Register 19 for Channel 0 assign cram_rwait_count = (dpriodisable_in == 1'b1) ? init_rwait_count : dprioin_rwait_count; assign cram_reserved_0_TB23 = (dpriodisable_in == 1'b1) ? init_reserved_0_TB23 : dprioin_reserved_0_TB23; // PCS Per Channel RX Control Register 20 for Channel 0 assign cram_rfts_count = (dpriodisable_in == 1'b1) ? init_rfts_count : dprioin_rfts_count; assign cram_rwait_for_phfifo_cnt = (dpriodisable_in == 1'b1) ? init_rwait_for_phfifo_cnt : dprioin_rwait_for_phfifo_cnt; // PCS Per Channel RX Control Register 21 for Channel 0 assign cram_rppm_meas_delay = (dpriodisable_in == 1'b1) ? init_rppm_meas_delay : dprioin_rppm_meas_delay; assign cram_rcid_len_rx = (dpriodisable_in == 1'b1) ? init_rcid_len_rx : dprioin_rcid_len_rx; assign cram_rcid_pattern_rx = (dpriodisable_in == 1'b1) ? init_rcid_pattern_rx : dprioin_rcid_pattern_rx; assign cram_rpcs_wrapback_en = (dpriodisable_in == 1'b1) ? init_rpcs_wrapback_en : dprioin_rpcs_wrapback_en; assign cram_reserved_0_TB25 = (dpriodisable_in == 1'b1) ? init_reserved_0_TB25 : dprioin_reserved_0_TB25; // PCS Per Channel RX Control Register 22 for Channel 0 assign cram_rauto_pc_en_cnt = (dpriodisable_in == 1'b1) ? init_rauto_pc_en_cnt : dprioin_rauto_pc_en_cnt; assign cram_reserved_1_TB26 = (dpriodisable_in == 1'b1) ? init_reserved_1_TB26 : dprioin_reserved_1_TB26; assign cram_rauto_deassert_pc_rst_cnt = (dpriodisable_in == 1'b1) ? init_rauto_deassert_pc_rst_cnt : dprioin_rauto_deassert_pc_rst_cnt; assign cram_reserved_0_TB26 = (dpriodisable_in == 1'b1) ? init_reserved_0_TB26 : dprioin_reserved_0_TB26; assign cram_rpipeline_bypass_rx = (dpriodisable_in == 1'b1) ? init_rpipeline_bypass_rx : dprioin_rpipeline_bypass_rx; assign cram_rself_sw_en_rx = (dpriodisable_in == 1'b1) ? init_rself_sw_en_rx : dprioin_rself_sw_en_rx; assign cram_rrxvalid_mask = (dpriodisable_in == 1'b1) ? init_rrxvalid_mask : dprioin_rrxvalid_mask; assign cram_rcid_en = (dpriodisable_in == 1'b1) ? init_rcid_en : dprioin_rcid_en; assign cram_rphfifo_regmode_rx = (dpriodisable_in == 1'b1) ? init_rphfifo_regmode_rx : dprioin_rphfifo_regmode_rx; // PCS Per Channel RX Control Register 23 for Channel 0 assign cram_rmask_count = (dpriodisable_in == 1'b1) ? init_rmask_count : dprioin_rmask_count; assign cram_rgen1_sigdet_ena = (dpriodisable_in == 1'b1) ? init_rgen1_sigdet_ena : dprioin_rgen1_sigdet_ena; assign cram_riei_eios_priority_dis = (dpriodisable_in == 1'b1) ? init_riei_eios_priority_dis : dprioin_riei_eios_priority_dis; assign cram_reserved_0_TB27 = (dpriodisable_in == 1'b1) ? init_reserved_0_TB27 : dprioin_reserved_0_TB27; //////////////////////////////////////////////////////////////////////////////// // Connect top level output -------------------------------------------------// //////////////////////////////////////////////////////////////////////////////// assign a1a2sizeout = a1a2sizeout_reg; assign a1detect = a1detect_reg; assign a2detect = a2detect_reg; assign ctrldetect = ctrldetect_reg; assign dataout = dataout_reg; assign dataoutfull = rd_out_rxd; // diff from s2gx: pi_out_rxd_ch; assign disperr = disperr_reg; assign errdetect = errdetect_reg; assign k1detect = k1detect_reg; assign k2detect = k2detect_reg; assign patterndetect = patterndetect_reg; assign rmfifodatadeleted = rmfifodatadeleted_reg; assign rmfifodatainserted = rmfifodatainserted_reg; assign runningdisp = runningdisp_reg; assign syncstatus = syncstatus_reg; // a1a2sizeout; - used in SONET mode always @(rd_out_rxd[8] or rd_out_rxd[24] or rd_out_rxd[40] or rd_out_rxd[56]) begin if (cram_rpma_doublewidth_rx == 1'b0 && cram_rdwidth_rx == 1'b1) begin for (i=0; (i < 4) && (i < 2); i=i+1) a1a2sizeout_reg[i] = rd_out_rxd[8 + 32*i]; end else begin for (i=0; i < 4; i=i+1) a1a2sizeout_reg[i] = rd_out_rxd[8 + 16*i]; end end // a1detect; [1:0] - Async from Word align, not going BYTE SERDES always @(rd_out_a1a2_k1k2_flag[0] or rd_out_a1a2_k1k2_flag[2]) for (i=0; i < 2; i=i+1) a1detect_reg[i] = rd_out_a1a2_k1k2_flag[2*i]; // a2detect; [0] = detecting A2 on datain[7:0]; [1] = on datain[15:8] always @(rd_out_a1a2_k1k2_flag[1] or rd_out_a1a2_k1k2_flag[3]) for (i=0; i < 2; i=i+1) a2detect_reg[i] = rd_out_a1a2_k1k2_flag[1+2*i]; // some outputs assign adetectdeskew = rd_out_align_det_sync; assign alignstatussyncout = rd_out_align_status_sync; assign bistdone = rd_out_bistdone; assign bisterr = rd_out_bisterr; assign byteorderalignstatus = rd_out_byteord_flag; assign clkout = rd_out_rx_clk; //assign dprioout = wire_dprioout; always @(rd_out_rxd[8] or rd_out_rxd[24] or rd_out_rxd[40] or rd_out_rxd[56]) begin if (cram_rpma_doublewidth_rx == 1'b0 && cram_rdwidth_rx == 1'b1) begin for (i=0; (i < 4) && (i < 2); i=i+1) ctrldetect_reg[i] = rd_out_rxd[8 + 32*i]; end else begin for (i=0; i < 4; i=i+1) ctrldetect_reg[i] = rd_out_rxd[8 + 16*i]; end end // dataout; - 40 => [7:0]/[9:0], [23:16]/[25:16], [39:32]/[41:32], [55:48]/[57:48] always @(rd_out_rxd) begin if (cram_rpma_doublewidth_rx == 1'b0 && cram_rdwidth_rx == 1'b1) begin for (i=0; (i < NUM_OF_BASIC) && (i < 2); i=i+1) for (j=0; jnl0ll35_event; always @(nl0ll35_event) nl0ll35 <= {1{1'b1}}; initial nl0ll36 = 0; always @ ( posedge clk_1) nl0ll36 <= nl0ll35; initial nl0lO33 = 0; always @ ( posedge clk_1) nl0lO33 <= nl0lO34; event nl0lO33_event; initial #1 ->nl0lO33_event; always @(nl0lO33_event) nl0lO33 <= {1{1'b1}}; initial nl0lO34 = 0; always @ ( posedge clk_1) nl0lO34 <= nl0lO33; initial nl0Oi31 = 0; always @ ( posedge clk_1) nl0Oi31 <= nl0Oi32; event nl0Oi31_event; initial #1 ->nl0Oi31_event; always @(nl0Oi31_event) nl0Oi31 <= {1{1'b1}}; initial nl0Oi32 = 0; always @ ( posedge clk_1) nl0Oi32 <= nl0Oi31; initial nl0Ol29 = 0; always @ ( posedge clk_1) nl0Ol29 <= nl0Ol30; event nl0Ol29_event; initial #1 ->nl0Ol29_event; always @(nl0Ol29_event) nl0Ol29 <= {1{1'b1}}; initial nl0Ol30 = 0; always @ ( posedge clk_1) nl0Ol30 <= nl0Ol29; initial nl0OO27 = 0; always @ ( posedge clk_1) nl0OO27 <= nl0OO28; event nl0OO27_event; initial #1 ->nl0OO27_event; always @(nl0OO27_event) nl0OO27 <= {1{1'b1}}; initial nl0OO28 = 0; always @ ( posedge clk_1) nl0OO28 <= nl0OO27; initial nli0i19 = 0; always @ ( posedge clk_1) nli0i19 <= nli0i20; event nli0i19_event; initial #1 ->nli0i19_event; always @(nli0i19_event) nli0i19 <= {1{1'b1}}; initial nli0i20 = 0; always @ ( posedge clk_1) nli0i20 <= nli0i19; initial nli0l17 = 0; always @ ( posedge clk_1) nli0l17 <= nli0l18; event nli0l17_event; initial #1 ->nli0l17_event; always @(nli0l17_event) nli0l17 <= {1{1'b1}}; initial nli0l18 = 0; always @ ( posedge clk_1) nli0l18 <= nli0l17; initial nli1i25 = 0; always @ ( posedge clk_1) nli1i25 <= nli1i26; event nli1i25_event; initial #1 ->nli1i25_event; always @(nli1i25_event) nli1i25 <= {1{1'b1}}; initial nli1i26 = 0; always @ ( posedge clk_1) nli1i26 <= nli1i25; initial nli1l23 = 0; always @ ( posedge clk_1) nli1l23 <= nli1l24; event nli1l23_event; initial #1 ->nli1l23_event; always @(nli1l23_event) nli1l23 <= {1{1'b1}}; initial nli1l24 = 0; always @ ( posedge clk_1) nli1l24 <= nli1l23; initial nli1O21 = 0; always @ ( posedge clk_1) nli1O21 <= nli1O22; event nli1O21_event; initial #1 ->nli1O21_event; always @(nli1O21_event) nli1O21 <= {1{1'b1}}; initial nli1O22 = 0; always @ ( posedge clk_1) nli1O22 <= nli1O21; initial nliii15 = 0; always @ ( posedge clk_1) nliii15 <= nliii16; event nliii15_event; initial #1 ->nliii15_event; always @(nliii15_event) nliii15 <= {1{1'b1}}; initial nliii16 = 0; always @ ( posedge clk_1) nliii16 <= nliii15; initial nliOi13 = 0; always @ ( posedge clk_1) nliOi13 <= nliOi14; event nliOi13_event; initial #1 ->nliOi13_event; always @(nliOi13_event) nliOi13 <= {1{1'b1}}; initial nliOi14 = 0; always @ ( posedge clk_1) nliOi14 <= nliOi13; initial nll0i10 = 0; always @ ( posedge clk_1) nll0i10 <= nll0i9; initial nll0i9 = 0; always @ ( posedge clk_1) nll0i9 <= nll0i10; event nll0i9_event; initial #1 ->nll0i9_event; always @(nll0i9_event) nll0i9 <= {1{1'b1}}; initial nll0O7 = 0; always @ ( posedge clk_1) nll0O7 <= nll0O8; event nll0O7_event; initial #1 ->nll0O7_event; always @(nll0O7_event) nll0O7 <= {1{1'b1}}; initial nll0O8 = 0; always @ ( posedge clk_1) nll0O8 <= nll0O7; initial nll1i11 = 0; always @ ( posedge clk_1) nll1i11 <= nll1i12; event nll1i11_event; initial #1 ->nll1i11_event; always @(nll1i11_event) nll1i11 <= {1{1'b1}}; initial nll1i12 = 0; always @ ( posedge clk_1) nll1i12 <= nll1i11; initial nlliO5 = 0; always @ ( posedge clk_1) nlliO5 <= nlliO6; event nlliO5_event; initial #1 ->nlliO5_event; always @(nlliO5_event) nlliO5 <= {1{1'b1}}; initial nlliO6 = 0; always @ ( posedge clk_1) nlliO6 <= nlliO5; initial nllll3 = 0; always @ ( posedge clk_1) nllll3 <= nllll4; event nllll3_event; initial #1 ->nllll3_event; always @(nllll3_event) nllll3 <= {1{1'b1}}; initial nllll4 = 0; always @ ( posedge clk_1) nllll4 <= nllll3; initial nlO1i1 = 0; always @ ( posedge clk_1) nlO1i1 <= nlO1i2; event nlO1i1_event; initial #1 ->nlO1i1_event; always @(nlO1i1_event) nlO1i1 <= {1{1'b1}}; initial nlO1i2 = 0; always @ ( posedge clk_1) nlO1i2 <= nlO1i1; initial begin n0il = 0; nii = 0; nil = 0; nli = 0; nllO = 0; nlOi = 0; nlOl = 0; end always @ ( posedge clk_1 or negedge wire_niO_CLRN) begin if (wire_niO_CLRN == 1'b0) begin n0il <= 0; nii <= 0; nil <= 0; nli <= 0; nllO <= 0; nlOi <= 0; nlOl <= 0; end else begin n0il <= wire_n0lO_o; nii <= wire_n0ll_o; nil <= nli; nli <= wire_nll_dataout; nllO <= wire_n0Oi_o; nlOi <= wire_n0Ol_o; nlOl <= nii; end end assign wire_niO_CLRN = ((nlliO6 ^ nlliO5) & (~ soft_reset)); initial begin n00O = 0; n0ii = 0; nO = 0; end always @ (clk_1 or soft_reset or wire_nl_CLRN) begin if (soft_reset == 1'b1) begin n00O <= 1; n0ii <= 1; nO <= 1; end else if (wire_nl_CLRN == 1'b0) begin n00O <= 0; n0ii <= 0; nO <= 0; end else if (clk_1 != nl_clk_prev && clk_1 == 1'b1) begin n00O <= n0ii; n0ii <= wire_n0li_o; nO <= n00O; end nl_clk_prev <= clk_1; end assign wire_nl_CLRN = (nlO1i2 ^ nlO1i1); event n00O_event; event n0ii_event; event nO_event; initial #1 ->n00O_event; initial #1 ->n0ii_event; initial #1 ->nO_event; always @(n00O_event) n00O <= 1; always @(n0ii_event) n0ii <= 1; always @(nO_event) nO <= 1; assign wire_n0i_dataout = (octal_mode === 1'b1) ? nllil : ((((rd_align[0] & rd_align[1]) & rd_align[2]) & rd_align[3]) & (nll0O8 ^ nll0O7)); or(wire_n0OO_dataout, n0ii, nli0O); assign wire_n1i_dataout = (octal_mode === 1'b1) ? (~ nll1O) : (~ ((((rd_align[0] | rd_align[1]) | rd_align[2]) | rd_align[3]) | (~ (nll1i12 ^ nll1i11)))); or(wire_ni0i_dataout, n0ii, (~ nil)); and(wire_ni0l_dataout, nii, ~((~ nil))); and(wire_ni0O_dataout, wire_niil_dataout, ~((~ nil))); and(wire_ni1i_dataout, nii, ~(nli0O)); and(wire_ni1l_dataout, (~ wire_n0i_dataout), ~(nli0O)); and(wire_niii_dataout, wire_niiO_dataout, ~((~ nil))); or(wire_niil_dataout, wire_n0i_dataout, nliOO); or(wire_niiO_dataout, (~ wire_n0i_dataout), nliOO); and(wire_nili_dataout, wire_nilO_dataout, ~((~ nil))); and(wire_nill_dataout, nliOO, ~((~ nil))); and(wire_nilO_dataout, (~ wire_n0i_dataout), ~(nliOO)); assign wire_niOi_dataout = (nliiO === 1'b1) ? nii : wire_nl1l_dataout; or(wire_niOl_dataout, n0ii, nliiO); and(wire_niOO_dataout, (~ wire_n0i_dataout), ~(nliiO)); and(wire_nl0i_dataout, (~ nlili), ~(nliiO)); and(wire_nl0l_dataout, nlili, ~(nliiO)); and(wire_nl1i_dataout, wire_n0i_dataout, ~(nliiO)); or(wire_nl1l_dataout, nii, wire_n0i_dataout); and(wire_nlii_dataout, n0ii, ~(nlill)); assign wire_nliO_dataout = (octal_mode === 1'b1) ? nlilO : (((align_det_sync[0] & align_det_sync[1]) & align_det_sync[2]) & align_det_sync[3]); assign wire_nll_dataout = (octal_mode === 1'b1) ? nllli : (((sync_status[0] & sync_status[1]) & sync_status[2]) & sync_status[3]); oper_mux n0li ( .data({((nl0ll36 ^ nl0ll35) & wire_n0OO_dataout), {3{wire_ni0i_dataout}}, {3{wire_niOl_dataout}}, wire_nlii_dataout, {8{1'b0}}}), .o(wire_n0li_o), .sel({1'b1, nlOi, nllO, n0il})); defparam n0li.width_data = 16, n0li.width_sel = 4; oper_mux n0ll ( .data({wire_ni1i_dataout, {2{wire_ni0l_dataout}}, ((nl0lO34 ^ nl0lO33) & wire_ni0l_dataout), wire_niOi_dataout, nii, ((nl0Oi32 ^ nl0Oi31) & nii), nii, {8{1'b0}}}), .o(wire_n0ll_o), .sel({1'b1, nlOi, nllO, n0il})); defparam n0ll.width_data = 16, n0ll.width_sel = 4; oper_mux n0lO ( .data({wire_ni1l_dataout, wire_ni0O_dataout, ((nl0Ol30 ^ nl0Ol29) & wire_nili_dataout), ((nl0OO28 ^ nl0OO27) & wire_nill_dataout), wire_niOO_dataout, wire_nl1i_dataout, wire_nl0i_dataout, nlill, {8{1'b0}}}), .o(wire_n0lO_o), .sel({1'b1, nlOi, nllO, n0il})); defparam n0lO.width_data = 16, n0lO.width_sel = 4; oper_mux n0Oi ( .data({((nli1i26 ^ nli1i25) & (~ nli0O)), wire_niii_dataout, wire_nill_dataout, 1'b0, wire_niOO_dataout, (~ nliiO), wire_nl0l_dataout, {9{1'b0}}}), .o(wire_n0Oi_o), .sel({1'b1, nlOi, ((nli1l24 ^ nli1l23) & nllO), ((nli1O22 ^ nli1O21) & n0il)})); defparam n0Oi.width_data = 16, n0Oi.width_sel = 4; oper_mux n0Ol ( .data({(~ nli0O), {2{nil}}, ((nli0i20 ^ nli0i19) & nil), wire_nl1i_dataout, {11{1'b0}}}), .o(wire_n0Ol_o), .sel({1'b1, nlOi, nllO, ((nli0l18 ^ nli0l17) & n0il)})); defparam n0Ol.width_data = 16, n0Ol.width_sel = 4; assign align_status = nlOl, curr_state = {1'b0, nlOi, nllO, n0il}, enable_deskew = n0ii, fifo_reset_rd = (n0ii & (~ n00O)), nli0O = ((~ nil) | nliOO), nliiO = (((~ nil) | nliOO) | (~ (nliii16 ^ nliii15))), nlili = ((~ nO) & wire_n0i_dataout), nlill = (nil & wire_nliO_dataout), nlilO = ((((((((align_det_sync[0] & align_det_sync[1]) & align_det_sync[2]) & align_det_sync[3]) & align_det_sync[4]) & align_det_sync[5]) & align_det_sync[6]) & align_det_sync[7]) & (nliOi14 ^ nliOi13)), nliOO = ((~ wire_n0i_dataout) & (~ wire_n1i_dataout)), nll1O = ((((((((rd_align[0] | rd_align[1]) | rd_align[2]) | rd_align[3]) | rd_align[4]) | rd_align[5]) | rd_align[6]) | rd_align[7]) | (~ (nll0i10 ^ nll0i9))), nllil = (((((((rd_align[0] & rd_align[1]) & rd_align[2]) & rd_align[3]) & rd_align[4]) & rd_align[5]) & rd_align[6]) & rd_align[7]), nllli = ((((((((sync_status[0] & sync_status[1]) & sync_status[2]) & sync_status[3]) & sync_status[4]) & sync_status[5]) & sync_status[6]) & sync_status[7]) & (nllll4 ^ nllll3)), nllOl = 1'b1; endmodule //stratixiv_hssi_dskw_sm //synopsys translate_on //VALID FILE //IP Functional Simulation Model //VERSION_BEGIN 12.0 cbx_mgl 2012:05:31:20:09:47:SJ cbx_simgen 2012:05:31:20:08:35:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 // Copyright (C) 1991-2012 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // You may only use these simulation model output files for simulation // purposes and expressly not for synthesis or any other purposes (in which // event Altera disclaims all warranties of any kind). //synopsys translate_off //synthesis_resources = lut 143 mux21 336 oper_add 1 oper_decoder 1 oper_less_than 1 oper_mux 39 `timescale 1 ps / 1 ps module stratixiv_hssi_tx_sm ( curr_state, indv, rd_enable_sync, rxaui_s2gx_en, sm_ctl, sm_data, soft_reset, tx_clk, tx_ctl, tx_data, tx_local_fault, tx_local_fault_clr, tx_local_fault_det) /* synthesis synthesis_clearbox=1 */; output [3:0] curr_state; input indv; input rd_enable_sync; input rxaui_s2gx_en; output [3:0] sm_ctl; output [31:0] sm_data; input soft_reset; input tx_clk; input [3:0] tx_ctl; input [31:0] tx_data; output tx_local_fault; input tx_local_fault_clr; output tx_local_fault_det; reg nil00i49; reg nil00i50; reg nil00l47; reg nil00l48; reg nili0i41; reg nili0i42; reg nili1i45; reg nili1i46; reg nili1O43; reg nili1O44; reg nilOll39; reg nilOll40; reg niO01l25; reg niO01l26; reg niO0il23; reg niO0il24; reg niO0ll21; reg niO0ll22; reg niO10l35; reg niO10l36; reg niO11i37; reg niO11i38; reg niO1iO33; reg niO1iO34; reg niO1ll31; reg niO1ll32; reg niO1Oi29; reg niO1Oi30; reg niO1OO27; reg niO1OO28; reg niOi0i17; reg niOi0i18; reg niOi1i19; reg niOi1i20; reg niOili15; reg niOili16; reg niOl0l13; reg niOl0l14; reg niOlli11; reg niOlli12; reg niOlOi10; reg niOlOi9; reg niOO1l7; reg niOO1l8; reg niOOii5; reg niOOii6; reg niOOll3; reg niOOll4; reg niOOOO1; reg niOOOO2; reg nlii0l; reg nlii0O; reg nliiii; reg nliili; reg nlilOl; reg nlilOi_clk_prev; wire wire_nlilOi_CLRN; reg nlii0i; reg nlii1l; reg nliiil; reg nliiiO; reg nliill; reg nliilO; reg nliiOi; reg nliiOl; reg nliiOO; reg nlil0i; reg nlil0l; reg nlil0O; reg nlil1i; reg nlil1l; reg nlil1O; reg nlilii; reg nlilil; reg nliliO; reg nlilli; reg nlilll; reg nlillO; reg nlilOO; reg nliO0i; reg nliO0O; reg nliO1i; reg nliO1l; reg nliO1O; wire wire_nliO0l_CLRN; reg n0l0O; reg n0lii; reg n0llO; reg n0lOl; reg n1i0i; reg n1i0l; reg n1ili; reg nilOi; reg nilOl; reg niOil; reg niOiO; reg niOOi; reg nli00i; reg nli10i; reg nli10l; reg nli10O; reg nliOii; reg nliOll; reg nliOlO; reg nliOO; reg nll0i; reg nll0O; reg nll11l; reg nlO01l; reg nlO01O; reg nlO0il; reg nll0l_clk_prev; wire wire_nll0l_CLRN; wire wire_nll0l_PRN; reg n0lil; reg n0liO; reg n0lli; reg n0lll; reg n0lOi; reg n1i0O; reg n1iii; reg n1iil; reg n1iiO; reg n1ill; reg n1ilO; reg niOli; reg nli0ll; reg nli0lO; reg nli0Oi; reg nli0Ol; reg nli0OO; reg nli1ii; reg nli1il; reg nlii1i; reg nliOil; reg nliOOi; reg nliOOl; reg nliOOO; reg nll10i; reg nll11i; reg nll11O; reg nll1i; reg nll1O; reg nlO00i; reg nlO00l; reg nlO00O; reg nlO0ii; reg nlO0iO; reg nlO0li; reg nll1l_clk_prev; wire wire_nll1l_CLRN; wire wire_n000i_dataout; wire wire_n000l_dataout; wire wire_n000O_dataout; wire wire_n001i_dataout; wire wire_n001l_dataout; wire wire_n001O_dataout; wire wire_n00ii_dataout; wire wire_n00il_dataout; wire wire_n00iO_dataout; wire wire_n00li_dataout; wire wire_n00ll_dataout; wire wire_n00lO_dataout; wire wire_n00Oi_dataout; wire wire_n00Ol_dataout; wire wire_n00OO_dataout; wire wire_n010i_dataout; wire wire_n010l_dataout; wire wire_n010O_dataout; wire wire_n011i_dataout; wire wire_n011l_dataout; wire wire_n011O_dataout; wire wire_n01ii_dataout; wire wire_n01il_dataout; wire wire_n01iO_dataout; wire wire_n01li_dataout; wire wire_n01ll_dataout; wire wire_n01lO_dataout; wire wire_n01Oi_dataout; wire wire_n01Ol_dataout; wire wire_n01OO_dataout; wire wire_n0i0i_dataout; wire wire_n0i0l_dataout; wire wire_n0i0O_dataout; wire wire_n0i1i_dataout; wire wire_n0i1l_dataout; wire wire_n0i1O_dataout; wire wire_n0iii_dataout; wire wire_n0iil_dataout; wire wire_n0iiO_dataout; wire wire_n0ili_dataout; wire wire_n0ill_dataout; wire wire_n0ilO_dataout; wire wire_n0iOi_dataout; wire wire_n0iOl_dataout; wire wire_n0iOO_dataout; wire wire_n0l0i_dataout; wire wire_n0l0l_dataout; wire wire_n0l1i_dataout; wire wire_n0l1l_dataout; wire wire_n0l1O_dataout; wire wire_n0lOO_dataout; wire wire_n0O0i_dataout; wire wire_n0O0l_dataout; wire wire_n0O0O_dataout; wire wire_n0O1i_dataout; wire wire_n0O1l_dataout; wire wire_n0O1O_dataout; wire wire_n0Oii_dataout; wire wire_n0Oil_dataout; wire wire_n100i_dataout; wire wire_n100l_dataout; wire wire_n100O_dataout; wire wire_n101i_dataout; wire wire_n101l_dataout; wire wire_n101O_dataout; wire wire_n10ii_dataout; wire wire_n10il_dataout; wire wire_n10iO_dataout; wire wire_n10li_dataout; wire wire_n10ll_dataout; wire wire_n10lO_dataout; wire wire_n10Oi_dataout; wire wire_n10Ol_dataout; wire wire_n10OO_dataout; wire wire_n110i_dataout; wire wire_n110l_dataout; wire wire_n110O_dataout; wire wire_n111i_dataout; wire wire_n111l_dataout; wire wire_n111O_dataout; wire wire_n11ii_dataout; wire wire_n11il_dataout; wire wire_n11iO_dataout; wire wire_n11li_dataout; wire wire_n11ll_dataout; wire wire_n11lO_dataout; wire wire_n11Oi_dataout; wire wire_n11Ol_dataout; wire wire_n11OO_dataout; wire wire_n1i1i_dataout; wire wire_n1i1l_dataout; wire wire_n1i1O_dataout; wire wire_n1iOi_dataout; wire wire_n1iOl_dataout; wire wire_n1iOO_dataout; wire wire_n1l0i_dataout; wire wire_n1l0l_dataout; wire wire_n1l0O_dataout; wire wire_n1l1i_dataout; wire wire_n1l1l_dataout; wire wire_n1l1O_dataout; wire wire_n1O0i_dataout; wire wire_n1O0l_dataout; wire wire_n1O0O_dataout; wire wire_n1O1i_dataout; wire wire_n1O1l_dataout; wire wire_n1O1O_dataout; wire wire_n1Oii_dataout; wire wire_n1Oil_dataout; wire wire_n1OiO_dataout; wire wire_n1Oli_dataout; wire wire_n1Oll_dataout; wire wire_n1OlO_dataout; wire wire_n1OOi_dataout; wire wire_n1OOl_dataout; wire wire_n1OOO_dataout; wire wire_ni00i_dataout; wire wire_ni00l_dataout; wire wire_ni00O_dataout; wire wire_ni01i_dataout; wire wire_ni01l_dataout; wire wire_ni01O_dataout; wire wire_ni0ii_dataout; wire wire_ni0il_dataout; wire wire_ni0iO_dataout; wire wire_ni0li_dataout; wire wire_ni0ll_dataout; wire wire_ni0lO_dataout; wire wire_ni0Oi_dataout; wire wire_ni0Ol_dataout; wire wire_ni0OO_dataout; wire wire_ni10i_dataout; wire wire_ni10l_dataout; wire wire_ni10O_dataout; wire wire_ni11O_dataout; wire wire_ni1ii_dataout; wire wire_ni1il_dataout; wire wire_ni1iO_dataout; wire wire_ni1li_dataout; wire wire_ni1ll_dataout; wire wire_ni1lO_dataout; wire wire_ni1Oi_dataout; wire wire_ni1Ol_dataout; wire wire_ni1OO_dataout; wire wire_nii0i_dataout; wire wire_nii0l_dataout; wire wire_nii0O_dataout; wire wire_nii1i_dataout; wire wire_nii1l_dataout; wire wire_nii1O_dataout; wire wire_niiii_dataout; wire wire_niiil_dataout; wire wire_niiiO_dataout; wire wire_niili_dataout; wire wire_niill_dataout; wire wire_niilO_dataout; wire wire_niiOi_dataout; wire wire_niiOl_dataout; wire wire_niiOO_dataout; wire wire_nil0i_dataout; wire wire_nil0l_dataout; wire wire_nil0O_dataout; wire wire_nil1i_dataout; wire wire_nil1l_dataout; wire wire_nil1O_dataout; wire wire_nilii_dataout; wire wire_nilil_dataout; wire wire_niliO_dataout; wire wire_nilli_dataout; wire wire_nilll_dataout; wire wire_nillO_dataout; wire wire_nilOO_dataout; wire wire_niO1i_dataout; wire wire_niO1l_dataout; wire wire_niOll_dataout; wire wire_niOlO_dataout; wire wire_niOOl_dataout; wire wire_niOOO_dataout; wire wire_nl00i_dataout; wire wire_nl00l_dataout; wire wire_nl00O_dataout; wire wire_nl01l_dataout; wire wire_nl01O_dataout; wire wire_nl0ii_dataout; wire wire_nl0il_dataout; wire wire_nl0iO_dataout; wire wire_nl0li_dataout; wire wire_nl0ll_dataout; wire wire_nl0lO_dataout; wire wire_nl0Oi_dataout; wire wire_nl0Ol_dataout; wire wire_nl0OO_dataout; wire wire_nl1OO_dataout; wire wire_nli01i_dataout; wire wire_nli01l_dataout; wire wire_nli01O_dataout; wire wire_nli0i_dataout; wire wire_nli0l_dataout; wire wire_nli0O_dataout; wire wire_nli1i_dataout; wire wire_nli1iO_dataout; wire wire_nli1l_dataout; wire wire_nli1li_dataout; wire wire_nli1ll_dataout; wire wire_nli1lO_dataout; wire wire_nli1O_dataout; wire wire_nli1Oi_dataout; wire wire_nli1Ol_dataout; wire wire_nli1OO_dataout; wire wire_nliii_dataout; wire wire_nliil_dataout; wire wire_nliiO_dataout; wire wire_nlili_dataout; wire wire_nlill_dataout; wire wire_nlilO_dataout; wire wire_nliOi_dataout; wire wire_nliOiO_dataout; wire wire_nliOl_dataout; wire wire_nliOli_dataout; wire wire_nll0il_dataout; wire wire_nll0iO_dataout; wire wire_nll0li_dataout; wire wire_nll0ll_dataout; wire wire_nll0lO_dataout; wire wire_nll0Oi_dataout; wire wire_nll0Ol_dataout; wire wire_nll0OO_dataout; wire wire_nll10l_dataout; wire wire_nll10O_dataout; wire wire_nll1ii_dataout; wire wire_nll1il_dataout; wire wire_nll1iO_dataout; wire wire_nll1li_dataout; wire wire_nll1ll_dataout; wire wire_nll1lO_dataout; wire wire_nll1Oi_dataout; wire wire_nlli0i_dataout; wire wire_nlli0l_dataout; wire wire_nlli0O_dataout; wire wire_nlli1i_dataout; wire wire_nlli1l_dataout; wire wire_nlli1O_dataout; wire wire_nlliii_dataout; wire wire_nlliil_dataout; wire wire_nlliiO_dataout; wire wire_nllili_dataout; wire wire_nllill_dataout; wire wire_nllilO_dataout; wire wire_nlliOi_dataout; wire wire_nlliOl_dataout; wire wire_nlliOO_dataout; wire wire_nlll0i_dataout; wire wire_nlll0O_dataout; wire wire_nlll1i_dataout; wire wire_nlll1l_dataout; wire wire_nlll1O_dataout; wire wire_nlllii_dataout; wire wire_nlllil_dataout; wire wire_nllliO_dataout; wire wire_nlllli_dataout; wire wire_nlllll_dataout; wire wire_nllllO_dataout; wire wire_nlllOi_dataout; wire wire_nlllOl_dataout; wire wire_nlllOO_dataout; wire wire_nllO0i_dataout; wire wire_nllO0l_dataout; wire wire_nllO0O_dataout; wire wire_nllO1i_dataout; wire wire_nllO1l_dataout; wire wire_nllO1O_dataout; wire wire_nllOii_dataout; wire wire_nllOil_dataout; wire wire_nllOiO_dataout; wire wire_nllOli_dataout; wire wire_nllOll_dataout; wire wire_nllOlO_dataout; wire wire_nllOOi_dataout; wire wire_nllOOl_dataout; wire wire_nllOOO_dataout; wire wire_nlO01i_dataout; wire wire_nlO0ll_dataout; wire wire_nlO0lO_dataout; wire wire_nlO0Oi_dataout; wire wire_nlO0Ol_dataout; wire wire_nlO0OO_dataout; wire wire_nlO10i_dataout; wire wire_nlO10l_dataout; wire wire_nlO10O_dataout; wire wire_nlO11i_dataout; wire wire_nlO11l_dataout; wire wire_nlO11O_dataout; wire wire_nlO1il_dataout; wire wire_nlO1iO_dataout; wire wire_nlO1li_dataout; wire wire_nlO1ll_dataout; wire wire_nlO1lO_dataout; wire wire_nlO1Oi_dataout; wire wire_nlO1Ol_dataout; wire wire_nlO1OO_dataout; wire wire_nlOi0i_dataout; wire wire_nlOi1i_dataout; wire wire_nlOi1l_dataout; wire wire_nlOi1O_dataout; wire wire_nlOiOl_dataout; wire wire_nlOiOO_dataout; wire wire_nlOl0i_dataout; wire wire_nlOl0l_dataout; wire wire_nlOl0O_dataout; wire wire_nlOl1i_dataout; wire wire_nlOl1l_dataout; wire wire_nlOl1O_dataout; wire wire_nlOlii_dataout; wire wire_nlOlil_dataout; wire wire_nlOliO_dataout; wire wire_nlOlli_dataout; wire wire_nlOlll_dataout; wire wire_nlOllO_dataout; wire wire_nlOlOi_dataout; wire wire_nlOlOl_dataout; wire wire_nlOlOO_dataout; wire wire_nlOO0i_dataout; wire wire_nlOO0l_dataout; wire wire_nlOO0O_dataout; wire wire_nlOO1i_dataout; wire wire_nlOO1l_dataout; wire wire_nlOO1O_dataout; wire wire_nlOOii_dataout; wire wire_nlOOil_dataout; wire wire_nlOOiO_dataout; wire wire_nlOOli_dataout; wire wire_nlOOll_dataout; wire wire_nlOOlO_dataout; wire wire_nlOOOi_dataout; wire wire_nlOOOl_dataout; wire wire_nlOOOO_dataout; wire [5:0] wire_nli00l_o; wire [15:0] wire_nl01i_o; wire wire_nl1li_o; wire wire_n0OiO_o; wire wire_n0Oli_o; wire wire_n0Oll_o; wire wire_n0OlO_o; wire wire_n0OOi_o; wire wire_n0OOl_o; wire wire_n0OOO_o; wire wire_n1lii_o; wire wire_n1lil_o; wire wire_n1liO_o; wire wire_n1lli_o; wire wire_n1lll_o; wire wire_n1llO_o; wire wire_n1lOi_o; wire wire_n1lOl_o; wire wire_n1lOO_o; wire wire_ni11i_o; wire wire_ni11l_o; wire wire_nl1lO_o; wire wire_nl1Oi_o; wire wire_nl1Ol_o; wire wire_nll00i_o; wire wire_nll00l_o; wire wire_nll00O_o; wire wire_nll01i_o; wire wire_nll01l_o; wire wire_nll01O_o; wire wire_nll0ii_o; wire wire_nll1Ol_o; wire wire_nll1OO_o; wire wire_nlOi0l_o; wire wire_nlOi0O_o; wire wire_nlOiii_o; wire wire_nlOiil_o; wire wire_nlOiiO_o; wire wire_nlOili_o; wire wire_nlOill_o; wire wire_nlOilO_o; wire wire_nlOiOi_o; wire nil00O; wire nil01O; wire nil0ii; wire nil0il; wire nil0iO; wire nil0li; wire nil0ll; wire nil0lO; wire nil0Oi; wire nil0Ol; wire nil0OO; wire nili0l; wire nili0O; wire nili1l; wire niliii; wire niliil; wire niliiO; wire nilili; wire nilill; wire nililO; wire niliOi; wire niliOl; wire niliOO; wire nill0i; wire nill0l; wire nill0O; wire nill1i; wire nill1l; wire nill1O; wire nillii; wire nillil; wire nilliO; wire nillli; wire nillll; wire nilllO; wire nillOi; wire nillOl; wire nillOO; wire nilO0i; wire nilO0l; wire nilO0O; wire nilO1i; wire nilO1l; wire nilO1O; wire nilOii; wire nilOil; wire nilOiO; wire nilOli; wire nilOOi; wire nilOOl; wire nilOOO; wire niO00i; wire niO00l; wire niO00O; wire niO0ii; wire niO0li; wire niO0Oi; wire niO0Ol; wire niO0OO; wire niO10i; wire niO11O; wire niO1ii; wire niO1il; wire niOi0O; wire niOi1O; wire niOiii; wire niOiil; wire niOiiO; wire niOilO; wire niOiOi; wire niOiOl; wire niOiOO; wire niOl0i; wire niOl1i; wire niOl1l; wire niOl1O; wire niOlii; wire niOlil; wire niOliO; wire niOllO; wire niOlOO; wire niOO0i; wire niOO0l; wire niOO0O; wire niOO1i; wire niOOiO; wire niOOli; wire niOOOi; wire niOOOl; initial nil00i49 = 0; always @ ( posedge tx_clk) nil00i49 <= nil00i50; event nil00i49_event; initial #1 ->nil00i49_event; always @(nil00i49_event) nil00i49 <= {1{1'b1}}; initial nil00i50 = 0; always @ ( posedge tx_clk) nil00i50 <= nil00i49; initial nil00l47 = 0; always @ ( posedge tx_clk) nil00l47 <= nil00l48; event nil00l47_event; initial #1 ->nil00l47_event; always @(nil00l47_event) nil00l47 <= {1{1'b1}}; initial nil00l48 = 0; always @ ( posedge tx_clk) nil00l48 <= nil00l47; initial nili0i41 = 0; always @ ( posedge tx_clk) nili0i41 <= nili0i42; event nili0i41_event; initial #1 ->nili0i41_event; always @(nili0i41_event) nili0i41 <= {1{1'b1}}; initial nili0i42 = 0; always @ ( posedge tx_clk) nili0i42 <= nili0i41; initial nili1i45 = 0; always @ ( posedge tx_clk) nili1i45 <= nili1i46; event nili1i45_event; initial #1 ->nili1i45_event; always @(nili1i45_event) nili1i45 <= {1{1'b1}}; initial nili1i46 = 0; always @ ( posedge tx_clk) nili1i46 <= nili1i45; initial nili1O43 = 0; always @ ( posedge tx_clk) nili1O43 <= nili1O44; event nili1O43_event; initial #1 ->nili1O43_event; always @(nili1O43_event) nili1O43 <= {1{1'b1}}; initial nili1O44 = 0; always @ ( posedge tx_clk) nili1O44 <= nili1O43; initial nilOll39 = 0; always @ ( posedge tx_clk) nilOll39 <= nilOll40; event nilOll39_event; initial #1 ->nilOll39_event; always @(nilOll39_event) nilOll39 <= {1{1'b1}}; initial nilOll40 = 0; always @ ( posedge tx_clk) nilOll40 <= nilOll39; initial niO01l25 = 0; always @ ( posedge tx_clk) niO01l25 <= niO01l26; event niO01l25_event; initial #1 ->niO01l25_event; always @(niO01l25_event) niO01l25 <= {1{1'b1}}; initial niO01l26 = 0; always @ ( posedge tx_clk) niO01l26 <= niO01l25; initial niO0il23 = 0; always @ ( posedge tx_clk) niO0il23 <= niO0il24; event niO0il23_event; initial #1 ->niO0il23_event; always @(niO0il23_event) niO0il23 <= {1{1'b1}}; initial niO0il24 = 0; always @ ( posedge tx_clk) niO0il24 <= niO0il23; initial niO0ll21 = 0; always @ ( posedge tx_clk) niO0ll21 <= niO0ll22; event niO0ll21_event; initial #1 ->niO0ll21_event; always @(niO0ll21_event) niO0ll21 <= {1{1'b1}}; initial niO0ll22 = 0; always @ ( posedge tx_clk) niO0ll22 <= niO0ll21; initial niO10l35 = 0; always @ ( posedge tx_clk) niO10l35 <= niO10l36; event niO10l35_event; initial #1 ->niO10l35_event; always @(niO10l35_event) niO10l35 <= {1{1'b1}}; initial niO10l36 = 0; always @ ( posedge tx_clk) niO10l36 <= niO10l35; initial niO11i37 = 0; always @ ( posedge tx_clk) niO11i37 <= niO11i38; event niO11i37_event; initial #1 ->niO11i37_event; always @(niO11i37_event) niO11i37 <= {1{1'b1}}; initial niO11i38 = 0; always @ ( posedge tx_clk) niO11i38 <= niO11i37; initial niO1iO33 = 0; always @ ( posedge tx_clk) niO1iO33 <= niO1iO34; event niO1iO33_event; initial #1 ->niO1iO33_event; always @(niO1iO33_event) niO1iO33 <= {1{1'b1}}; initial niO1iO34 = 0; always @ ( posedge tx_clk) niO1iO34 <= niO1iO33; initial niO1ll31 = 0; always @ ( posedge tx_clk) niO1ll31 <= niO1ll32; event niO1ll31_event; initial #1 ->niO1ll31_event; always @(niO1ll31_event) niO1ll31 <= {1{1'b1}}; initial niO1ll32 = 0; always @ ( posedge tx_clk) niO1ll32 <= niO1ll31; initial niO1Oi29 = 0; always @ ( posedge tx_clk) niO1Oi29 <= niO1Oi30; event niO1Oi29_event; initial #1 ->niO1Oi29_event; always @(niO1Oi29_event) niO1Oi29 <= {1{1'b1}}; initial niO1Oi30 = 0; always @ ( posedge tx_clk) niO1Oi30 <= niO1Oi29; initial niO1OO27 = 0; always @ ( posedge tx_clk) niO1OO27 <= niO1OO28; event niO1OO27_event; initial #1 ->niO1OO27_event; always @(niO1OO27_event) niO1OO27 <= {1{1'b1}}; initial niO1OO28 = 0; always @ ( posedge tx_clk) niO1OO28 <= niO1OO27; initial niOi0i17 = 0; always @ ( posedge tx_clk) niOi0i17 <= niOi0i18; event niOi0i17_event; initial #1 ->niOi0i17_event; always @(niOi0i17_event) niOi0i17 <= {1{1'b1}}; initial niOi0i18 = 0; always @ ( posedge tx_clk) niOi0i18 <= niOi0i17; initial niOi1i19 = 0; always @ ( posedge tx_clk) niOi1i19 <= niOi1i20; event niOi1i19_event; initial #1 ->niOi1i19_event; always @(niOi1i19_event) niOi1i19 <= {1{1'b1}}; initial niOi1i20 = 0; always @ ( posedge tx_clk) niOi1i20 <= niOi1i19; initial niOili15 = 0; always @ ( posedge tx_clk) niOili15 <= niOili16; event niOili15_event; initial #1 ->niOili15_event; always @(niOili15_event) niOili15 <= {1{1'b1}}; initial niOili16 = 0; always @ ( posedge tx_clk) niOili16 <= niOili15; initial niOl0l13 = 0; always @ ( posedge tx_clk) niOl0l13 <= niOl0l14; event niOl0l13_event; initial #1 ->niOl0l13_event; always @(niOl0l13_event) niOl0l13 <= {1{1'b1}}; initial niOl0l14 = 0; always @ ( posedge tx_clk) niOl0l14 <= niOl0l13; initial niOlli11 = 0; always @ ( posedge tx_clk) niOlli11 <= niOlli12; event niOlli11_event; initial #1 ->niOlli11_event; always @(niOlli11_event) niOlli11 <= {1{1'b1}}; initial niOlli12 = 0; always @ ( posedge tx_clk) niOlli12 <= niOlli11; initial niOlOi10 = 0; always @ ( posedge tx_clk) niOlOi10 <= niOlOi9; initial niOlOi9 = 0; always @ ( posedge tx_clk) niOlOi9 <= niOlOi10; event niOlOi9_event; initial #1 ->niOlOi9_event; always @(niOlOi9_event) niOlOi9 <= {1{1'b1}}; initial niOO1l7 = 0; always @ ( posedge tx_clk) niOO1l7 <= niOO1l8; event niOO1l7_event; initial #1 ->niOO1l7_event; always @(niOO1l7_event) niOO1l7 <= {1{1'b1}}; initial niOO1l8 = 0; always @ ( posedge tx_clk) niOO1l8 <= niOO1l7; initial niOOii5 = 0; always @ ( posedge tx_clk) niOOii5 <= niOOii6; event niOOii5_event; initial #1 ->niOOii5_event; always @(niOOii5_event) niOOii5 <= {1{1'b1}}; initial niOOii6 = 0; always @ ( posedge tx_clk) niOOii6 <= niOOii5; initial niOOll3 = 0; always @ ( posedge tx_clk) niOOll3 <= niOOll4; event niOOll3_event; initial #1 ->niOOll3_event; always @(niOOll3_event) niOOll3 <= {1{1'b1}}; initial niOOll4 = 0; always @ ( posedge tx_clk) niOOll4 <= niOOll3; initial niOOOO1 = 0; always @ ( posedge tx_clk) niOOOO1 <= niOOOO2; event niOOOO1_event; initial #1 ->niOOOO1_event; always @(niOOOO1_event) niOOOO1 <= {1{1'b1}}; initial niOOOO2 = 0; always @ ( posedge tx_clk) niOOOO2 <= niOOOO1; initial begin nlii0l = 0; nlii0O = 0; nliiii = 0; nliili = 0; nlilOl = 0; end always @ (tx_clk or soft_reset or wire_nlilOi_CLRN) begin if (soft_reset == 1'b1) begin nlii0l <= 1; nlii0O <= 1; nliiii <= 1; nliili <= 1; nlilOl <= 1; end else if (wire_nlilOi_CLRN == 1'b0) begin nlii0l <= 0; nlii0O <= 0; nliiii <= 0; nliili <= 0; nlilOl <= 0; end else if (niOlil == 1'b1) if (tx_clk != nlilOi_clk_prev && tx_clk == 1'b1) begin nlii0l <= tx_data[2]; nlii0O <= tx_data[3]; nliiii <= tx_data[4]; nliili <= tx_data[7]; nlilOl <= tx_data[25]; end nlilOi_clk_prev <= tx_clk; end assign wire_nlilOi_CLRN = (nil00i50 ^ nil00i49); event nlii0l_event; event nlii0O_event; event nliiii_event; event nliili_event; event nlilOl_event; initial #1 ->nlii0l_event; initial #1 ->nlii0O_event; initial #1 ->nliiii_event; initial #1 ->nliili_event; initial #1 ->nlilOl_event; always @(nlii0l_event) nlii0l <= 1; always @(nlii0O_event) nlii0O <= 1; always @(nliiii_event) nliiii <= 1; always @(nliili_event) nliili <= 1; always @(nlilOl_event) nlilOl <= 1; initial begin nlii0i = 0; nlii1l = 0; nliiil = 0; nliiiO = 0; nliill = 0; nliilO = 0; nliiOi = 0; nliiOl = 0; nliiOO = 0; nlil0i = 0; nlil0l = 0; nlil0O = 0; nlil1i = 0; nlil1l = 0; nlil1O = 0; nlilii = 0; nlilil = 0; nliliO = 0; nlilli = 0; nlilll = 0; nlillO = 0; nlilOO = 0; nliO0i = 0; nliO0O = 0; nliO1i = 0; nliO1l = 0; nliO1O = 0; end always @ ( posedge tx_clk or negedge wire_nliO0l_CLRN) begin if (wire_nliO0l_CLRN == 1'b0) begin nlii0i <= 0; nlii1l <= 0; nliiil <= 0; nliiiO <= 0; nliill <= 0; nliilO <= 0; nliiOi <= 0; nliiOl <= 0; nliiOO <= 0; nlil0i <= 0; nlil0l <= 0; nlil0O <= 0; nlil1i <= 0; nlil1l <= 0; nlil1O <= 0; nlilii <= 0; nlilil <= 0; nliliO <= 0; nlilli <= 0; nlilll <= 0; nlillO <= 0; nlilOO <= 0; nliO0i <= 0; nliO0O <= 0; nliO1i <= 0; nliO1l <= 0; nliO1O <= 0; end else if (niOlil == 1'b1) begin nlii0i <= tx_data[1]; nlii1l <= tx_data[0]; nliiil <= tx_data[5]; nliiiO <= tx_data[6]; nliill <= tx_data[8]; nliilO <= tx_data[9]; nliiOi <= tx_data[10]; nliiOl <= tx_data[11]; nliiOO <= tx_data[12]; nlil0i <= tx_data[16]; nlil0l <= tx_data[17]; nlil0O <= tx_data[18]; nlil1i <= tx_data[13]; nlil1l <= tx_data[14]; nlil1O <= tx_data[15]; nlilii <= tx_data[19]; nlilil <= tx_data[20]; nliliO <= tx_data[21]; nlilli <= tx_data[22]; nlilll <= tx_data[23]; nlillO <= tx_data[24]; nlilOO <= tx_data[26]; nliO0i <= tx_data[30]; nliO0O <= tx_data[31]; nliO1i <= tx_data[27]; nliO1l <= tx_data[28]; nliO1O <= tx_data[29]; end end assign wire_nliO0l_CLRN = ((nil00l48 ^ nil00l47) & (~ soft_reset)); initial begin n0l0O = 0; n0lii = 0; n0llO = 0; n0lOl = 0; n1i0i = 0; n1i0l = 0; n1ili = 0; nilOi = 0; nilOl = 0; niOil = 0; niOiO = 0; niOOi = 0; nli00i = 0; nli10i = 0; nli10l = 0; nli10O = 0; nliOii = 0; nliOll = 0; nliOlO = 0; nliOO = 0; nll0i = 0; nll0O = 0; nll11l = 0; nlO01l = 0; nlO01O = 0; nlO0il = 0; end always @ (tx_clk or wire_nll0l_PRN or wire_nll0l_CLRN) begin if (wire_nll0l_PRN == 1'b0) begin n0l0O <= 1; n0lii <= 1; n0llO <= 1; n0lOl <= 1; n1i0i <= 1; n1i0l <= 1; n1ili <= 1; nilOi <= 1; nilOl <= 1; niOil <= 1; niOiO <= 1; niOOi <= 1; nli00i <= 1; nli10i <= 1; nli10l <= 1; nli10O <= 1; nliOii <= 1; nliOll <= 1; nliOlO <= 1; nliOO <= 1; nll0i <= 1; nll0O <= 1; nll11l <= 1; nlO01l <= 1; nlO01O <= 1; nlO0il <= 1; end else if (wire_nll0l_CLRN == 1'b0) begin n0l0O <= 0; n0lii <= 0; n0llO <= 0; n0lOl <= 0; n1i0i <= 0; n1i0l <= 0; n1ili <= 0; nilOi <= 0; nilOl <= 0; niOil <= 0; niOiO <= 0; niOOi <= 0; nli00i <= 0; nli10i <= 0; nli10l <= 0; nli10O <= 0; nliOii <= 0; nliOll <= 0; nliOlO <= 0; nliOO <= 0; nll0i <= 0; nll0O <= 0; nll11l <= 0; nlO01l <= 0; nlO01O <= 0; nlO0il <= 0; end else if (tx_clk != nll0l_clk_prev && tx_clk == 1'b1) begin n0l0O <= wire_n0O1i_dataout; n0lii <= wire_n0O1l_dataout; n0llO <= wire_n0Oii_dataout; n0lOl <= wire_nilOO_dataout; n1i0i <= wire_n1iOl_dataout; n1i0l <= wire_n1iOO_dataout; n1ili <= wire_n1l0l_dataout; nilOi <= wire_niO1i_dataout; nilOl <= niOil; niOil <= tx_local_fault_clr; niOiO <= wire_niOll_dataout; niOOi <= nliOO; nli00i <= wire_nli1iO_dataout; nli10i <= wire_nli1li_dataout; nli10l <= wire_nli1ll_dataout; nli10O <= wire_nli1lO_dataout; nliOii <= wire_nliOiO_dataout; nliOll <= wire_nll10O_dataout; nliOlO <= wire_nll1ii_dataout; nliOO <= indv; nll0i <= wire_nl1Ol_o; nll0O <= wire_nl1OO_dataout; nll11l <= wire_nll1lO_dataout; nlO01l <= wire_nlO0lO_dataout; nlO01O <= wire_nlO0Oi_dataout; nlO0il <= wire_nlOi1O_dataout; end nll0l_clk_prev <= tx_clk; end assign wire_nll0l_CLRN = ((nili0i42 ^ nili0i41) & (~ soft_reset)), wire_nll0l_PRN = (nili1O44 ^ nili1O43); initial begin n0lil = 0; n0liO = 0; n0lli = 0; n0lll = 0; n0lOi = 0; n1i0O = 0; n1iii = 0; n1iil = 0; n1iiO = 0; n1ill = 0; n1ilO = 0; niOli = 0; nli0ll = 0; nli0lO = 0; nli0Oi = 0; nli0Ol = 0; nli0OO = 0; nli1ii = 0; nli1il = 0; nlii1i = 0; nliOil = 0; nliOOi = 0; nliOOl = 0; nliOOO = 0; nll10i = 0; nll11i = 0; nll11O = 0; nll1i = 0; nll1O = 0; nlO00i = 0; nlO00l = 0; nlO00O = 0; nlO0ii = 0; nlO0iO = 0; nlO0li = 0; end always @ (tx_clk or soft_reset or wire_nll1l_CLRN) begin if (soft_reset == 1'b1) begin n0lil <= 1; n0liO <= 1; n0lli <= 1; n0lll <= 1; n0lOi <= 1; n1i0O <= 1; n1iii <= 1; n1iil <= 1; n1iiO <= 1; n1ill <= 1; n1ilO <= 1; niOli <= 1; nli0ll <= 1; nli0lO <= 1; nli0Oi <= 1; nli0Ol <= 1; nli0OO <= 1; nli1ii <= 1; nli1il <= 1; nlii1i <= 1; nliOil <= 1; nliOOi <= 1; nliOOl <= 1; nliOOO <= 1; nll10i <= 1; nll11i <= 1; nll11O <= 1; nll1i <= 1; nll1O <= 1; nlO00i <= 1; nlO00l <= 1; nlO00O <= 1; nlO0ii <= 1; nlO0iO <= 1; nlO0li <= 1; end else if (wire_nll1l_CLRN == 1'b0) begin n0lil <= 0; n0liO <= 0; n0lli <= 0; n0lll <= 0; n0lOi <= 0; n1i0O <= 0; n1iii <= 0; n1iil <= 0; n1iiO <= 0; n1ill <= 0; n1ilO <= 0; niOli <= 0; nli0ll <= 0; nli0lO <= 0; nli0Oi <= 0; nli0Ol <= 0; nli0OO <= 0; nli1ii <= 0; nli1il <= 0; nlii1i <= 0; nliOil <= 0; nliOOi <= 0; nliOOl <= 0; nliOOO <= 0; nll10i <= 0; nll11i <= 0; nll11O <= 0; nll1i <= 0; nll1O <= 0; nlO00i <= 0; nlO00l <= 0; nlO00O <= 0; nlO0ii <= 0; nlO0iO <= 0; nlO0li <= 0; end else if (tx_clk != nll1l_clk_prev && tx_clk == 1'b1) begin n0lil <= wire_n0O1O_dataout; n0liO <= wire_n0O0i_dataout; n0lli <= wire_n0O0l_dataout; n0lll <= wire_n0O0O_dataout; n0lOi <= wire_n0Oil_dataout; n1i0O <= wire_n1l1i_dataout; n1iii <= wire_n1l1l_dataout; n1iil <= wire_n1l1O_dataout; n1iiO <= wire_n1l0i_dataout; n1ill <= wire_n1l0O_dataout; n1ilO <= wire_n0lOO_dataout; niOli <= wire_niOOl_dataout; nli0ll <= nli1il; nli0lO <= nli0ll; nli0Oi <= nli0lO; nli0Ol <= nli0Oi; nli0OO <= nli0Ol; nli1ii <= wire_nli1Oi_dataout; nli1il <= (nlii1i ^ nli0OO); nlii1i <= nli0OO; nliOil <= wire_nll10l_dataout; nliOOi <= wire_nll1il_dataout; nliOOl <= wire_nll1iO_dataout; nliOOO <= wire_nll1li_dataout; nll10i <= wire_nlO0ll_dataout; nll11i <= wire_nll1ll_dataout; nll11O <= wire_nll1Oi_dataout; nll1i <= wire_nl1lO_o; nll1O <= wire_nl1Oi_o; nlO00i <= wire_nlO0Ol_dataout; nlO00l <= wire_nlO0OO_dataout; nlO00O <= wire_nlOi1i_dataout; nlO0ii <= wire_nlOi1l_dataout; nlO0iO <= wire_nlOi0i_dataout; nlO0li <= wire_n1iOi_dataout; end nll1l_clk_prev <= tx_clk; end assign wire_nll1l_CLRN = (nili1i46 ^ nili1i45); event n0lil_event; event n0liO_event; event n0lli_event; event n0lll_event; event n0lOi_event; event n1i0O_event; event n1iii_event; event n1iil_event; event n1iiO_event; event n1ill_event; event n1ilO_event; event niOli_event; event nli0ll_event; event nli0lO_event; event nli0Oi_event; event nli0Ol_event; event nli0OO_event; event nli1ii_event; event nli1il_event; event nlii1i_event; event nliOil_event; event nliOOi_event; event nliOOl_event; event nliOOO_event; event nll10i_event; event nll11i_event; event nll11O_event; event nll1i_event; event nll1O_event; event nlO00i_event; event nlO00l_event; event nlO00O_event; event nlO0ii_event; event nlO0iO_event; event nlO0li_event; initial #1 ->n0lil_event; initial #1 ->n0liO_event; initial #1 ->n0lli_event; initial #1 ->n0lll_event; initial #1 ->n0lOi_event; initial #1 ->n1i0O_event; initial #1 ->n1iii_event; initial #1 ->n1iil_event; initial #1 ->n1iiO_event; initial #1 ->n1ill_event; initial #1 ->n1ilO_event; initial #1 ->niOli_event; initial #1 ->nli0ll_event; initial #1 ->nli0lO_event; initial #1 ->nli0Oi_event; initial #1 ->nli0Ol_event; initial #1 ->nli0OO_event; initial #1 ->nli1ii_event; initial #1 ->nli1il_event; initial #1 ->nlii1i_event; initial #1 ->nliOil_event; initial #1 ->nliOOi_event; initial #1 ->nliOOl_event; initial #1 ->nliOOO_event; initial #1 ->nll10i_event; initial #1 ->nll11i_event; initial #1 ->nll11O_event; initial #1 ->nll1i_event; initial #1 ->nll1O_event; initial #1 ->nlO00i_event; initial #1 ->nlO00l_event; initial #1 ->nlO00O_event; initial #1 ->nlO0ii_event; initial #1 ->nlO0iO_event; initial #1 ->nlO0li_event; always @(n0lil_event) n0lil <= 1; always @(n0liO_event) n0liO <= 1; always @(n0lli_event) n0lli <= 1; always @(n0lll_event) n0lll <= 1; always @(n0lOi_event) n0lOi <= 1; always @(n1i0O_event) n1i0O <= 1; always @(n1iii_event) n1iii <= 1; always @(n1iil_event) n1iil <= 1; always @(n1iiO_event) n1iiO <= 1; always @(n1ill_event) n1ill <= 1; always @(n1ilO_event) n1ilO <= 1; always @(niOli_event) niOli <= 1; always @(nli0ll_event) nli0ll <= 1; always @(nli0lO_event) nli0lO <= 1; always @(nli0Oi_event) nli0Oi <= 1; always @(nli0Ol_event) nli0Ol <= 1; always @(nli0OO_event) nli0OO <= 1; always @(nli1ii_event) nli1ii <= 1; always @(nli1il_event) nli1il <= 1; always @(nlii1i_event) nlii1i <= 1; always @(nliOil_event) nliOil <= 1; always @(nliOOi_event) nliOOi <= 1; always @(nliOOl_event) nliOOl <= 1; always @(nliOOO_event) nliOOO <= 1; always @(nll10i_event) nll10i <= 1; always @(nll11i_event) nll11i <= 1; always @(nll11O_event) nll11O <= 1; always @(nll1i_event) nll1i <= 1; always @(nll1O_event) nll1O <= 1; always @(nlO00i_event) nlO00i <= 1; always @(nlO00l_event) nlO00l <= 1; always @(nlO00O_event) nlO00O <= 1; always @(nlO0ii_event) nlO0ii <= 1; always @(nlO0iO_event) nlO0iO <= 1; always @(nlO0li_event) nlO0li <= 1; assign wire_n000i_dataout = (nil0OO === 1'b1) ? wire_n011i_dataout : wire_n00lO_dataout; assign wire_n000l_dataout = (nil0OO === 1'b1) ? wire_n011l_dataout : wire_n00Oi_dataout; assign wire_n000O_dataout = (nil0OO === 1'b1) ? wire_n011O_dataout : wire_n00Ol_dataout; assign wire_n001i_dataout = (nil0OO === 1'b1) ? wire_n1OOi_dataout : wire_n00iO_dataout; assign wire_n001l_dataout = (nil0OO === 1'b1) ? wire_n1OOl_dataout : wire_n00li_dataout; assign wire_n001O_dataout = (nil0OO === 1'b1) ? wire_n1OOO_dataout : wire_n00ll_dataout; and(wire_n00ii_dataout, nliill, nliOii); and(wire_n00il_dataout, nliilO, nliOii); or(wire_n00iO_dataout, nliiOi, ~(nliOii)); or(wire_n00li_dataout, nliiOl, ~(nliOii)); or(wire_n00ll_dataout, nliiOO, ~(nliOii)); assign wire_n00lO_dataout = (nliOii === 1'b1) ? nlil1i : (~ nli1il); and(wire_n00Oi_dataout, nlil1l, nliOii); assign wire_n00Ol_dataout = (nliOii === 1'b1) ? nlil1O : (~ nli1il); assign wire_n00OO_dataout = (nil0OO === 1'b1) ? wire_n011i_dataout : wire_nllOll_dataout; or(wire_n010i_dataout, tx_ctl[1], niOO0l); or(wire_n010l_dataout, tx_data[8], niOO0l); and(wire_n010O_dataout, tx_data[9], ~(niOO0l)); or(wire_n011i_dataout, wire_n01li_dataout, niliiO); and(wire_n011l_dataout, wire_n01ll_dataout, ~(niliiO)); or(wire_n011O_dataout, wire_n01lO_dataout, niliiO); or(wire_n01ii_dataout, tx_data[10], niOO0l); or(wire_n01il_dataout, tx_data[11], niOO0l); or(wire_n01iO_dataout, tx_data[12], niOO0l); or(wire_n01li_dataout, tx_data[13], niOO0l); or(wire_n01ll_dataout, tx_data[14], niOO0l); or(wire_n01lO_dataout, tx_data[15], niOO0l); assign wire_n01Oi_dataout = (nil0OO === 1'b1) ? wire_n1Oli_dataout : (~ nliOii); assign wire_n01Ol_dataout = (nil0OO === 1'b1) ? wire_n1Oll_dataout : wire_n00ii_dataout; assign wire_n01OO_dataout = (nil0OO === 1'b1) ? wire_n1OlO_dataout : wire_n00il_dataout; and(wire_n0i0i_dataout, wire_n011O_dataout, nil0OO); assign wire_n0i0l_dataout = (nil0OO === 1'b1) ? wire_n011i_dataout : wire_n0iii_dataout; assign wire_n0i0O_dataout = (nil0OO === 1'b1) ? wire_n011O_dataout : wire_n0iil_dataout; assign wire_n0i1i_dataout = (nil0OO === 1'b1) ? wire_n011l_dataout : (~ nil0Oi); assign wire_n0i1l_dataout = (nil0OO === 1'b1) ? wire_n011O_dataout : wire_nllOlO_dataout; and(wire_n0i1O_dataout, wire_n011i_dataout, nil0OO); and(wire_n0iii_dataout, nlil1i, nliOii); and(wire_n0iil_dataout, nlil1O, nliOii); or(wire_n0iiO_dataout, wire_n011i_dataout, ~(nil0OO)); assign wire_n0ili_dataout = (nil0OO === 1'b1) ? wire_n011l_dataout : nil0Ol; assign wire_n0ill_dataout = (nil0OO === 1'b1) ? wire_n011O_dataout : (~ nil0Ol); or(wire_n0ilO_dataout, wire_n1O1i_dataout, ~(rd_enable_sync)); and(wire_n0iOi_dataout, wire_n1O1l_dataout, rd_enable_sync); and(wire_n0iOl_dataout, wire_n1O1O_dataout, rd_enable_sync); or(wire_n0iOO_dataout, wire_n1O0i_dataout, ~(rd_enable_sync)); and(wire_n0l0i_dataout, wire_n1Oil_dataout, rd_enable_sync); or(wire_n0l0l_dataout, wire_n0i0i_dataout, ~(rd_enable_sync)); or(wire_n0l1i_dataout, wire_n1O0l_dataout, ~(rd_enable_sync)); or(wire_n0l1l_dataout, wire_n1O0O_dataout, ~(rd_enable_sync)); or(wire_n0l1O_dataout, wire_n0i1O_dataout, ~(rd_enable_sync)); or(wire_n0lOO_dataout, wire_n0OiO_o, niO1il); or(wire_n0O0i_dataout, wire_n0OOi_o, niO1il); or(wire_n0O0l_dataout, wire_n0OOl_o, niO1il); or(wire_n0O0O_dataout, wire_n0OOO_o, niO1il); and(wire_n0O1i_dataout, wire_n0Oli_o, ~(niO1il)); or(wire_n0O1l_dataout, wire_n0Oll_o, niO1il); or(wire_n0O1O_dataout, wire_n0OlO_o, niO1il); or(wire_n0Oii_dataout, wire_ni11i_o, niO1il); or(wire_n0Oil_dataout, wire_ni11l_o, niO1il); assign wire_n100i_dataout = (nil0OO === 1'b1) ? wire_nlOO1i_dataout : wire_n100O_dataout; and(wire_n100l_dataout, nliliO, nliOii); and(wire_n100O_dataout, nlilll, nliOii); and(wire_n101i_dataout, wire_nlOlOl_dataout, nil0OO); and(wire_n101l_dataout, wire_nlOO1i_dataout, nil0OO); assign wire_n101O_dataout = (nil0OO === 1'b1) ? wire_nlOlOl_dataout : wire_n100l_dataout; or(wire_n10ii_dataout, wire_nlOlOl_dataout, ~(nil0OO)); assign wire_n10il_dataout = (nil0OO === 1'b1) ? wire_nlOlOO_dataout : nil0Ol; assign wire_n10iO_dataout = (nil0OO === 1'b1) ? wire_nlOO1i_dataout : (~ nil0Ol); or(wire_n10li_dataout, wire_nlOiOl_dataout, ~(rd_enable_sync)); and(wire_n10ll_dataout, wire_nlOiOO_dataout, rd_enable_sync); and(wire_n10lO_dataout, wire_nlOl1i_dataout, rd_enable_sync); or(wire_n10Oi_dataout, wire_nlOl1l_dataout, ~(rd_enable_sync)); or(wire_n10Ol_dataout, wire_nlOl1O_dataout, ~(rd_enable_sync)); or(wire_n10OO_dataout, wire_nlOl0i_dataout, ~(rd_enable_sync)); assign wire_n110i_dataout = (nil0OO === 1'b1) ? wire_nlOO1i_dataout : wire_n11lO_dataout; and(wire_n110l_dataout, nlil0i, nliOii); and(wire_n110O_dataout, nlil0l, nliOii); assign wire_n111i_dataout = (nil0OO === 1'b1) ? wire_nlOlOi_dataout : wire_n11iO_dataout; assign wire_n111l_dataout = (nil0OO === 1'b1) ? wire_nlOlOl_dataout : wire_n11li_dataout; assign wire_n111O_dataout = (nil0OO === 1'b1) ? wire_nlOlOO_dataout : wire_n11ll_dataout; or(wire_n11ii_dataout, nlil0O, ~(nliOii)); or(wire_n11il_dataout, nlilii, ~(nliOii)); or(wire_n11iO_dataout, nlilil, ~(nliOii)); assign wire_n11li_dataout = (nliOii === 1'b1) ? nliliO : (~ nli1il); and(wire_n11ll_dataout, nlilli, nliOii); assign wire_n11lO_dataout = (nliOii === 1'b1) ? nlilll : (~ nli1il); assign wire_n11Oi_dataout = (nil0OO === 1'b1) ? wire_nlOlOl_dataout : wire_nllOll_dataout; assign wire_n11Ol_dataout = (nil0OO === 1'b1) ? wire_nlOlOO_dataout : (~ nil0Oi); assign wire_n11OO_dataout = (nil0OO === 1'b1) ? wire_nlOO1i_dataout : wire_nllOlO_dataout; or(wire_n1i1i_dataout, wire_n101i_dataout, ~(rd_enable_sync)); and(wire_n1i1l_dataout, wire_nlOl0O_dataout, rd_enable_sync); or(wire_n1i1O_dataout, wire_n101l_dataout, ~(rd_enable_sync)); or(wire_n1iOi_dataout, wire_n1lii_o, nilO0l); and(wire_n1iOl_dataout, wire_n1lil_o, ~(nilO0l)); or(wire_n1iOO_dataout, wire_n1liO_o, nilO0l); or(wire_n1l0i_dataout, wire_n1lOi_o, nilO0l); or(wire_n1l0l_dataout, wire_n1lOl_o, nilO0l); or(wire_n1l0O_dataout, wire_n1lOO_o, nilO0l); or(wire_n1l1i_dataout, wire_n1lli_o, nilO0l); or(wire_n1l1l_dataout, wire_n1lll_o, nilO0l); or(wire_n1l1O_dataout, wire_n1llO_o, nilO0l); or(wire_n1O0i_dataout, wire_n1OOi_dataout, ~(nil0OO)); or(wire_n1O0l_dataout, wire_n1OOl_dataout, ~(nil0OO)); or(wire_n1O0O_dataout, wire_n1OOO_dataout, ~(nil0OO)); or(wire_n1O1i_dataout, wire_n1Oli_dataout, ~(nil0OO)); and(wire_n1O1l_dataout, wire_n1Oll_dataout, nil0OO); and(wire_n1O1O_dataout, wire_n1OlO_dataout, nil0OO); assign wire_n1Oii_dataout = (nil0OO === 1'b1) ? wire_n011i_dataout : (~ nli1il); and(wire_n1Oil_dataout, wire_n011l_dataout, nil0OO); assign wire_n1OiO_dataout = (nil0OO === 1'b1) ? wire_n011O_dataout : (~ nli1il); or(wire_n1Oli_dataout, wire_n010i_dataout, niliiO); and(wire_n1Oll_dataout, wire_n010l_dataout, ~(niliiO)); and(wire_n1OlO_dataout, wire_n010O_dataout, ~(niliiO)); or(wire_n1OOi_dataout, wire_n01ii_dataout, niliiO); or(wire_n1OOl_dataout, wire_n01il_dataout, niliiO); or(wire_n1OOO_dataout, wire_n01iO_dataout, niliiO); or(wire_ni00i_dataout, tx_data[6], nilili); or(wire_ni00l_dataout, tx_data[7], nilili); assign wire_ni00O_dataout = (nil0OO === 1'b1) ? wire_ni1Oi_dataout : wire_ni0Ol_dataout; or(wire_ni01i_dataout, tx_data[3], nilili); or(wire_ni01l_dataout, tx_data[4], nilili); or(wire_ni01O_dataout, tx_data[5], nilili); assign wire_ni0ii_dataout = (nil0OO === 1'b1) ? wire_ni1Ol_dataout : wire_ni0OO_dataout; assign wire_ni0il_dataout = (nil0OO === 1'b1) ? wire_ni1OO_dataout : wire_nii1i_dataout; assign wire_ni0iO_dataout = (nil0OO === 1'b1) ? wire_ni01i_dataout : wire_nii1l_dataout; assign wire_ni0li_dataout = (nil0OO === 1'b1) ? wire_ni01l_dataout : wire_nii1O_dataout; assign wire_ni0ll_dataout = (nil0OO === 1'b1) ? wire_ni01O_dataout : wire_nii0i_dataout; assign wire_ni0lO_dataout = (nil0OO === 1'b1) ? wire_ni00i_dataout : wire_nii0l_dataout; assign wire_ni0Oi_dataout = (nil0OO === 1'b1) ? wire_ni00l_dataout : wire_nii0O_dataout; and(wire_ni0Ol_dataout, nlii1l, nliOii); and(wire_ni0OO_dataout, nlii0i, nliOii); and(wire_ni10i_dataout, wire_ni1Oi_dataout, nil0OO); and(wire_ni10l_dataout, wire_ni1Ol_dataout, nil0OO); or(wire_ni10O_dataout, wire_ni1OO_dataout, ~(nil0OO)); or(wire_ni11O_dataout, wire_ni1lO_dataout, ~(nil0OO)); or(wire_ni1ii_dataout, wire_ni01i_dataout, ~(nil0OO)); or(wire_ni1il_dataout, wire_ni01l_dataout, ~(nil0OO)); assign wire_ni1iO_dataout = (nil0OO === 1'b1) ? wire_ni01O_dataout : (~ nli1il); and(wire_ni1li_dataout, wire_ni00i_dataout, nil0OO); assign wire_ni1ll_dataout = (nil0OO === 1'b1) ? wire_ni00l_dataout : (~ nli1il); or(wire_ni1lO_dataout, tx_ctl[0], nilili); or(wire_ni1Oi_dataout, tx_data[0], nilili); and(wire_ni1Ol_dataout, tx_data[1], ~(nilili)); or(wire_ni1OO_dataout, tx_data[2], nilili); assign wire_nii0i_dataout = (nliOii === 1'b1) ? nliiil : (~ nli1il); and(wire_nii0l_dataout, nliiiO, nliOii); assign wire_nii0O_dataout = (nliOii === 1'b1) ? nliili : (~ nli1il); or(wire_nii1i_dataout, nlii0l, ~(nliOii)); or(wire_nii1l_dataout, nlii0O, ~(nliOii)); or(wire_nii1O_dataout, nliiii, ~(nliOii)); assign wire_niiii_dataout = (nil0OO === 1'b1) ? wire_ni01O_dataout : wire_nllOll_dataout; assign wire_niiil_dataout = (nil0OO === 1'b1) ? wire_ni00i_dataout : (~ nil0Oi); assign wire_niiiO_dataout = (nil0OO === 1'b1) ? wire_ni00l_dataout : wire_nllOlO_dataout; and(wire_niili_dataout, wire_ni01O_dataout, nil0OO); and(wire_niill_dataout, wire_ni00l_dataout, nil0OO); assign wire_niilO_dataout = (nil0OO === 1'b1) ? wire_ni01O_dataout : wire_niiOl_dataout; assign wire_niiOi_dataout = (nil0OO === 1'b1) ? wire_ni00l_dataout : wire_niiOO_dataout; and(wire_niiOl_dataout, nliiil, nliOii); and(wire_niiOO_dataout, nliili, nliOii); or(wire_nil0i_dataout, wire_ni11O_dataout, ~(rd_enable_sync)); and(wire_nil0l_dataout, wire_ni10i_dataout, rd_enable_sync); and(wire_nil0O_dataout, wire_ni10l_dataout, rd_enable_sync); or(wire_nil1i_dataout, wire_ni01O_dataout, ~(nil0OO)); assign wire_nil1l_dataout = (nil0OO === 1'b1) ? wire_ni00i_dataout : nil0Ol; assign wire_nil1O_dataout = (nil0OO === 1'b1) ? wire_ni00l_dataout : (~ nil0Ol); or(wire_nilii_dataout, wire_ni10O_dataout, ~(rd_enable_sync)); or(wire_nilil_dataout, wire_ni1ii_dataout, ~(rd_enable_sync)); or(wire_niliO_dataout, wire_ni1il_dataout, ~(rd_enable_sync)); or(wire_nilli_dataout, wire_niili_dataout, ~(rd_enable_sync)); and(wire_nilll_dataout, wire_ni1li_dataout, rd_enable_sync); or(wire_nillO_dataout, wire_niill_dataout, ~(rd_enable_sync)); and(wire_nilOO_dataout, wire_niO1l_dataout, nil0il); and(wire_niO1i_dataout, nil00O, nil0il); or(wire_niO1l_dataout, (nilOi & n0lOl), nil00O); and(wire_niOll_dataout, wire_niOlO_dataout, ~(nilOl)); or(wire_niOlO_dataout, niOiO, nilOi); or(wire_niOOl_dataout, wire_niOOO_dataout, (((((~ rd_enable_sync) & nil0iO) | wire_nl1li_o) | ((rd_enable_sync & nil0iO) & nil0lO)) | (((~ niOli) | nil0Oi) & nil0li))); and(wire_niOOO_dataout, niOli, ~((nil0li & nil0Ol))); and(wire_nl00i_dataout, (~ nil0OO), ~(niOOi)); or(wire_nl00l_dataout, nli1il, nil0OO); and(wire_nl00O_dataout, (~ nli1il), ~(nil0OO)); or(wire_nl01l_dataout, wire_nl00l_dataout, niOOi); or(wire_nl01O_dataout, wire_nl00O_dataout, niOOi); or(wire_nl0ii_dataout, wire_nl0ll_dataout, niOOi); or(wire_nl0il_dataout, wire_nl0lO_dataout, niOOi); and(wire_nl0iO_dataout, wire_nl0Oi_dataout, ~(niOOi)); and(wire_nl0li_dataout, wire_nl0Ol_dataout, ~(niOOi)); or(wire_nl0ll_dataout, wire_nl0OO_dataout, nil0OO); and(wire_nl0lO_dataout, wire_nli1i_dataout, ~(nil0OO)); and(wire_nl0Oi_dataout, (~ nliOii), ~(nil0OO)); and(wire_nl0Ol_dataout, nliOii, ~(nil0OO)); and(wire_nl0OO_dataout, nli1il, ~(nliOii)); and(wire_nl1OO_dataout, wire_nl0li_dataout, wire_nl01i_o[7]); assign wire_nli01i_dataout = (nil0Oi === 1'b1) ? wire_nli00l_o[3] : nli10l; assign wire_nli01l_dataout = (nil0Oi === 1'b1) ? wire_nli00l_o[4] : nli10O; assign wire_nli01O_dataout = (nil0Oi === 1'b1) ? wire_nli00l_o[5] : nli1ii; or(wire_nli0i_dataout, wire_nli0O_dataout, nil0OO); and(wire_nli0l_dataout, wire_nllOll_dataout, ~(nil0OO)); or(wire_nli0O_dataout, nli1il, (~ nil0Oi)); and(wire_nli1i_dataout, (~ nli1il), ~(nliOii)); assign wire_nli1iO_dataout = (nil01O === 1'b1) ? nli1il : wire_nli1Ol_dataout; or(wire_nli1l_dataout, wire_nli0i_dataout, niOOi); assign wire_nli1li_dataout = (nil01O === 1'b1) ? nli0ll : wire_nli1OO_dataout; assign wire_nli1ll_dataout = (nil01O === 1'b1) ? nli0lO : wire_nli01i_dataout; assign wire_nli1lO_dataout = (nil01O === 1'b1) ? nli0Oi : wire_nli01l_dataout; or(wire_nli1O_dataout, wire_nli0l_dataout, niOOi); or(wire_nli1Oi_dataout, wire_nli01O_dataout, nil01O); assign wire_nli1Ol_dataout = (nil0Oi === 1'b1) ? wire_nli00l_o[1] : nli00i; assign wire_nli1OO_dataout = (nil0Oi === 1'b1) ? wire_nli00l_o[2] : nli10i; or(wire_nliii_dataout, wire_nliil_dataout, niOOi); or(wire_nliil_dataout, (~ nliOii), nil0OO); or(wire_nliiO_dataout, wire_nlill_dataout, niOOi); or(wire_nlili_dataout, (~ nil0OO), niOOi); or(wire_nlill_dataout, (~ nil0Ol), nil0OO); or(wire_nlilO_dataout, (~ rd_enable_sync), niOOi); and(wire_nliOi_dataout, wire_nliOl_dataout, ~(niOOi)); or(wire_nliOiO_dataout, wire_nliOli_dataout, niOlil); and(wire_nliOl_dataout, (~ nil0OO), rd_enable_sync); and(wire_nliOli_dataout, nliOii, ~(nil0il)); or(wire_nll0il_dataout, wire_nlli1l_dataout, ~(nil0OO)); and(wire_nll0iO_dataout, wire_nlli1O_dataout, nil0OO); and(wire_nll0li_dataout, wire_nlli0i_dataout, nil0OO); or(wire_nll0ll_dataout, wire_nlli0l_dataout, ~(nil0OO)); or(wire_nll0lO_dataout, wire_nlli0O_dataout, ~(nil0OO)); or(wire_nll0Oi_dataout, wire_nlliii_dataout, ~(nil0OO)); assign wire_nll0Ol_dataout = (nil0OO === 1'b1) ? wire_nlliil_dataout : (~ nli1il); and(wire_nll0OO_dataout, wire_nlliiO_dataout, nil0OO); or(wire_nll10l_dataout, wire_nll1Ol_o, nililO); and(wire_nll10O_dataout, wire_nll1OO_o, ~(nililO)); or(wire_nll1ii_dataout, wire_nll01i_o, nililO); or(wire_nll1il_dataout, wire_nll01l_o, nililO); or(wire_nll1iO_dataout, wire_nll01O_o, nililO); or(wire_nll1li_dataout, wire_nll00i_o, nililO); or(wire_nll1ll_dataout, wire_nll00l_o, nililO); or(wire_nll1lO_dataout, wire_nll00O_o, nililO); or(wire_nll1Oi_dataout, wire_nll0ii_o, nililO); and(wire_nlli0i_dataout, wire_nlliOi_dataout, ~(nili0l)); or(wire_nlli0l_dataout, wire_nlliOl_dataout, nili0l); or(wire_nlli0O_dataout, wire_nlliOO_dataout, nili0l); assign wire_nlli1i_dataout = (nil0OO === 1'b1) ? wire_nllili_dataout : (~ nli1il); or(wire_nlli1l_dataout, wire_nllill_dataout, nili0l); and(wire_nlli1O_dataout, wire_nllilO_dataout, ~(nili0l)); or(wire_nlliii_dataout, wire_nlll1i_dataout, nili0l); or(wire_nlliil_dataout, wire_nlll1l_dataout, nili0l); and(wire_nlliiO_dataout, wire_nlll1O_dataout, ~(nili0l)); or(wire_nllili_dataout, wire_nlll0i_dataout, nili0l); or(wire_nllill_dataout, tx_ctl[3], niOllO); or(wire_nllilO_dataout, tx_data[24], niOllO); and(wire_nlliOi_dataout, tx_data[25], ~(niOllO)); or(wire_nlliOl_dataout, tx_data[26], niOllO); or(wire_nlliOO_dataout, tx_data[27], niOllO); or(wire_nlll0i_dataout, tx_data[31], niOllO); assign wire_nlll0O_dataout = (nil0OO === 1'b1) ? wire_nlli1l_dataout : (~ nliOii); or(wire_nlll1i_dataout, tx_data[28], niOllO); or(wire_nlll1l_dataout, tx_data[29], niOllO); or(wire_nlll1O_dataout, tx_data[30], niOllO); assign wire_nlllii_dataout = (nil0OO === 1'b1) ? wire_nlli1O_dataout : wire_nlllOO_dataout; assign wire_nlllil_dataout = (nil0OO === 1'b1) ? wire_nlli0i_dataout : wire_nllO1i_dataout; assign wire_nllliO_dataout = (nil0OO === 1'b1) ? wire_nlli0l_dataout : wire_nllO1l_dataout; assign wire_nlllli_dataout = (nil0OO === 1'b1) ? wire_nlli0O_dataout : wire_nllO1O_dataout; assign wire_nlllll_dataout = (nil0OO === 1'b1) ? wire_nlliii_dataout : wire_nllO0i_dataout; assign wire_nllllO_dataout = (nil0OO === 1'b1) ? wire_nlliil_dataout : wire_nllO0l_dataout; assign wire_nlllOi_dataout = (nil0OO === 1'b1) ? wire_nlliiO_dataout : wire_nllO0O_dataout; assign wire_nlllOl_dataout = (nil0OO === 1'b1) ? wire_nllili_dataout : wire_nllOii_dataout; and(wire_nlllOO_dataout, nlillO, nliOii); or(wire_nllO0i_dataout, nliO1l, ~(nliOii)); assign wire_nllO0l_dataout = (nliOii === 1'b1) ? nliO1O : (~ nli1il); and(wire_nllO0O_dataout, nliO0i, nliOii); and(wire_nllO1i_dataout, nlilOl, nliOii); or(wire_nllO1l_dataout, nlilOO, ~(nliOii)); or(wire_nllO1O_dataout, nliO1i, ~(nliOii)); assign wire_nllOii_dataout = (nliOii === 1'b1) ? nliO0O : (~ nli1il); assign wire_nllOil_dataout = (nil0OO === 1'b1) ? wire_nlliil_dataout : wire_nllOll_dataout; assign wire_nllOiO_dataout = (nil0OO === 1'b1) ? wire_nlliiO_dataout : (~ nil0Oi); assign wire_nllOli_dataout = (nil0OO === 1'b1) ? wire_nllili_dataout : wire_nllOlO_dataout; or(wire_nllOll_dataout, (~ nli1il), (~ nil0Oi)); and(wire_nllOlO_dataout, (~ nli1il), ~((~ nil0Oi))); and(wire_nllOOi_dataout, wire_nlliil_dataout, nil0OO); and(wire_nllOOl_dataout, wire_nllili_dataout, nil0OO); assign wire_nllOOO_dataout = (nil0OO === 1'b1) ? wire_nlliil_dataout : wire_nlO11l_dataout; or(wire_nlO01i_dataout, wire_nllOOl_dataout, ~(rd_enable_sync)); or(wire_nlO0ll_dataout, wire_nlOi0l_o, nillil); and(wire_nlO0lO_dataout, wire_nlOi0O_o, ~(nillil)); or(wire_nlO0Oi_dataout, wire_nlOiii_o, nillil); or(wire_nlO0Ol_dataout, wire_nlOiil_o, nillil); or(wire_nlO0OO_dataout, wire_nlOiiO_o, nillil); or(wire_nlO10i_dataout, wire_nlliil_dataout, ~(nil0OO)); assign wire_nlO10l_dataout = (nil0OO === 1'b1) ? wire_nlliiO_dataout : nil0Ol; assign wire_nlO10O_dataout = (nil0OO === 1'b1) ? wire_nllili_dataout : (~ nil0Ol); assign wire_nlO11i_dataout = (nil0OO === 1'b1) ? wire_nllili_dataout : wire_nlO11O_dataout; and(wire_nlO11l_dataout, nliO1O, nliOii); and(wire_nlO11O_dataout, nliO0O, nliOii); or(wire_nlO1il_dataout, wire_nll0il_dataout, ~(rd_enable_sync)); and(wire_nlO1iO_dataout, wire_nll0iO_dataout, rd_enable_sync); and(wire_nlO1li_dataout, wire_nll0li_dataout, rd_enable_sync); or(wire_nlO1ll_dataout, wire_nll0ll_dataout, ~(rd_enable_sync)); or(wire_nlO1lO_dataout, wire_nll0lO_dataout, ~(rd_enable_sync)); or(wire_nlO1Oi_dataout, wire_nll0Oi_dataout, ~(rd_enable_sync)); or(wire_nlO1Ol_dataout, wire_nllOOi_dataout, ~(rd_enable_sync)); and(wire_nlO1OO_dataout, wire_nll0OO_dataout, rd_enable_sync); or(wire_nlOi0i_dataout, wire_nlOiOi_o, nillil); or(wire_nlOi1i_dataout, wire_nlOili_o, nillil); or(wire_nlOi1l_dataout, wire_nlOill_o, nillil); or(wire_nlOi1O_dataout, wire_nlOilO_o, nillil); or(wire_nlOiOl_dataout, wire_nlOlil_dataout, ~(nil0OO)); and(wire_nlOiOO_dataout, wire_nlOliO_dataout, nil0OO); or(wire_nlOl0i_dataout, wire_nlOlOi_dataout, ~(nil0OO)); assign wire_nlOl0l_dataout = (nil0OO === 1'b1) ? wire_nlOlOl_dataout : (~ nli1il); and(wire_nlOl0O_dataout, wire_nlOlOO_dataout, nil0OO); and(wire_nlOl1i_dataout, wire_nlOlli_dataout, nil0OO); or(wire_nlOl1l_dataout, wire_nlOlll_dataout, ~(nil0OO)); or(wire_nlOl1O_dataout, wire_nlOllO_dataout, ~(nil0OO)); assign wire_nlOlii_dataout = (nil0OO === 1'b1) ? wire_nlOO1i_dataout : (~ nli1il); or(wire_nlOlil_dataout, wire_nlOO1l_dataout, nili0O); and(wire_nlOliO_dataout, wire_nlOO1O_dataout, ~(nili0O)); and(wire_nlOlli_dataout, wire_nlOO0i_dataout, ~(nili0O)); or(wire_nlOlll_dataout, wire_nlOO0l_dataout, nili0O); or(wire_nlOllO_dataout, wire_nlOO0O_dataout, nili0O); or(wire_nlOlOi_dataout, wire_nlOOii_dataout, nili0O); or(wire_nlOlOl_dataout, wire_nlOOil_dataout, nili0O); and(wire_nlOlOO_dataout, wire_nlOOiO_dataout, ~(nili0O)); and(wire_nlOO0i_dataout, tx_data[17], ~(niOO1i)); or(wire_nlOO0l_dataout, tx_data[18], niOO1i); or(wire_nlOO0O_dataout, tx_data[19], niOO1i); or(wire_nlOO1i_dataout, wire_nlOOli_dataout, nili0O); or(wire_nlOO1l_dataout, tx_ctl[2], niOO1i); or(wire_nlOO1O_dataout, tx_data[16], niOO1i); or(wire_nlOOii_dataout, tx_data[20], niOO1i); or(wire_nlOOil_dataout, tx_data[21], niOO1i); or(wire_nlOOiO_dataout, tx_data[22], niOO1i); or(wire_nlOOli_dataout, tx_data[23], niOO1i); assign wire_nlOOll_dataout = (nil0OO === 1'b1) ? wire_nlOlil_dataout : (~ nliOii); assign wire_nlOOlO_dataout = (nil0OO === 1'b1) ? wire_nlOliO_dataout : wire_n110l_dataout; assign wire_nlOOOi_dataout = (nil0OO === 1'b1) ? wire_nlOlli_dataout : wire_n110O_dataout; assign wire_nlOOOl_dataout = (nil0OO === 1'b1) ? wire_nlOlll_dataout : wire_n11ii_dataout; assign wire_nlOOOO_dataout = (nil0OO === 1'b1) ? wire_nlOllO_dataout : wire_n11il_dataout; oper_add nli00l ( .a({nli1ii, nli10O, nli10l, nli10i, nli00i, 1'b1}), .b({{4{1'b1}}, 1'b0, 1'b1}), .cin(1'b0), .cout(), .o(wire_nli00l_o)); defparam nli00l.sgate_representation = 0, nli00l.width_a = 6, nli00l.width_b = 6, nli00l.width_o = 6; oper_decoder nl01i ( .i({nll0O, nll0i, nll1O, nll1i}), .o(wire_nl01i_o)); defparam nl01i.width_i = 4, nl01i.width_o = 16; oper_less_than nl1li ( .a({1'b1, {3{1'b0}}}), .b({nll0O, nll0i, nll1O, nll1i}), .cin(1'b0), .o(wire_nl1li_o)); defparam nl1li.sgate_representation = 0, nl1li.width_a = 4, nl1li.width_b = 4; oper_mux n0OiO ( .data({{7{1'b1}}, {5{wire_ni11O_dataout}}, wire_nil0i_dataout, {2{wire_ni11O_dataout}}, 1'b1}), .o(wire_n0OiO_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam n0OiO.width_data = 16, n0OiO.width_sel = 4; oper_mux n0Oli ( .data({{7{1'b0}}, wire_ni10i_dataout, wire_ni00O_dataout, {3{wire_ni10i_dataout}}, wire_nil0l_dataout, wire_ni00O_dataout, wire_ni10i_dataout, 1'b0}), .o(wire_n0Oli_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam n0Oli.width_data = 16, n0Oli.width_sel = 4; oper_mux n0Oll ( .data({{7{1'b0}}, wire_ni10l_dataout, wire_ni0ii_dataout, {3{wire_ni10l_dataout}}, wire_nil0O_dataout, wire_ni0ii_dataout, wire_ni10l_dataout, 1'b0}), .o(wire_n0Oll_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam n0Oll.width_data = 16, n0Oll.width_sel = 4; oper_mux n0OlO ( .data({{7{1'b1}}, wire_ni10O_dataout, wire_ni0il_dataout, {3{wire_ni10O_dataout}}, wire_nilii_dataout, wire_ni0il_dataout, wire_ni10O_dataout, 1'b1}), .o(wire_n0OlO_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam n0OlO.width_data = 16, n0OlO.width_sel = 4; oper_mux n0OOi ( .data({{7{1'b1}}, wire_ni1ii_dataout, wire_ni0iO_dataout, {3{wire_ni1ii_dataout}}, wire_nilil_dataout, wire_ni0iO_dataout, wire_ni1ii_dataout, 1'b1}), .o(wire_n0OOi_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam n0OOi.width_data = 16, n0OOi.width_sel = 4; oper_mux n0OOl ( .data({{7{1'b1}}, wire_ni1il_dataout, wire_ni0li_dataout, {3{wire_ni1il_dataout}}, wire_niliO_dataout, wire_ni0li_dataout, wire_ni1il_dataout, 1'b1}), .o(wire_n0OOl_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam n0OOl.width_data = 16, n0OOl.width_sel = 4; oper_mux n0OOO ( .data({{7{1'b1}}, wire_ni1iO_dataout, wire_ni0ll_dataout, {2{wire_niiii_dataout}}, wire_niili_dataout, wire_nilli_dataout, wire_niilO_dataout, wire_nil1i_dataout, 1'b1}), .o(wire_n0OOO_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam n0OOO.width_data = 16, n0OOO.width_sel = 4; oper_mux n1lii ( .data({{7{1'b1}}, wire_n1O1i_dataout, wire_n01Oi_dataout, {3{wire_n1O1i_dataout}}, wire_n0ilO_dataout, wire_n01Oi_dataout, wire_n1O1i_dataout, 1'b1}), .o(wire_n1lii_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam n1lii.width_data = 16, n1lii.width_sel = 4; oper_mux n1lil ( .data({{7{1'b0}}, wire_n1O1l_dataout, wire_n01Ol_dataout, {3{wire_n1O1l_dataout}}, wire_n0iOi_dataout, wire_n01Ol_dataout, wire_n1O1l_dataout, 1'b0}), .o(wire_n1lil_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam n1lil.width_data = 16, n1lil.width_sel = 4; oper_mux n1liO ( .data({{7{1'b0}}, wire_n1O1O_dataout, wire_n01OO_dataout, {3{wire_n1O1O_dataout}}, wire_n0iOl_dataout, wire_n01OO_dataout, wire_n1O1O_dataout, 1'b0}), .o(wire_n1liO_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam n1liO.width_data = 16, n1liO.width_sel = 4; oper_mux n1lli ( .data({{7{1'b1}}, wire_n1O0i_dataout, wire_n001i_dataout, {3{wire_n1O0i_dataout}}, wire_n0iOO_dataout, wire_n001i_dataout, wire_n1O0i_dataout, 1'b1}), .o(wire_n1lli_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam n1lli.width_data = 16, n1lli.width_sel = 4; oper_mux n1lll ( .data({{7{1'b1}}, wire_n1O0l_dataout, wire_n001l_dataout, {3{wire_n1O0l_dataout}}, wire_n0l1i_dataout, wire_n001l_dataout, wire_n1O0l_dataout, 1'b1}), .o(wire_n1lll_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam n1lll.width_data = 16, n1lll.width_sel = 4; oper_mux n1llO ( .data({{7{1'b1}}, wire_n1O0O_dataout, wire_n001O_dataout, {3{wire_n1O0O_dataout}}, wire_n0l1l_dataout, wire_n001O_dataout, wire_n1O0O_dataout, 1'b1}), .o(wire_n1llO_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam n1llO.width_data = 16, n1llO.width_sel = 4; oper_mux n1lOi ( .data({{7{1'b1}}, wire_n1Oii_dataout, wire_n000i_dataout, {2{wire_n00OO_dataout}}, wire_n0i1O_dataout, wire_n0l1O_dataout, wire_n0i0l_dataout, wire_n0iiO_dataout, 1'b1}), .o(wire_n1lOi_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam n1lOi.width_data = 16, n1lOi.width_sel = 4; oper_mux n1lOl ( .data({{7{1'b0}}, wire_n1Oil_dataout, wire_n000l_dataout, {2{wire_n0i1i_dataout}}, wire_n1Oil_dataout, wire_n0l0i_dataout, wire_n000l_dataout, wire_n0ili_dataout, 1'b0}), .o(wire_n1lOl_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam n1lOl.width_data = 16, n1lOl.width_sel = 4; oper_mux n1lOO ( .data({{7{1'b1}}, wire_n1OiO_dataout, wire_n000O_dataout, {2{wire_n0i1l_dataout}}, wire_n0i0i_dataout, wire_n0l0l_dataout, wire_n0i0O_dataout, wire_n0ill_dataout, 1'b1}), .o(wire_n1lOO_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam n1lOO.width_data = 16, n1lOO.width_sel = 4; oper_mux ni11i ( .data({{7{1'b0}}, wire_ni1li_dataout, wire_ni0lO_dataout, {2{wire_niiil_dataout}}, wire_ni1li_dataout, wire_nilll_dataout, wire_ni0lO_dataout, wire_nil1l_dataout, 1'b0}), .o(wire_ni11i_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam ni11i.width_data = 16, ni11i.width_sel = 4; oper_mux ni11l ( .data({{7{1'b1}}, wire_ni1ll_dataout, wire_ni0Oi_dataout, {2{wire_niiiO_dataout}}, wire_niill_dataout, wire_nillO_dataout, wire_niiOi_dataout, wire_nil1O_dataout, 1'b1}), .o(wire_ni11l_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam ni11l.width_data = 16, ni11l.width_sel = 4; oper_mux nl1lO ( .data({{7{1'b1}}, wire_nl01l_dataout, wire_nl0ii_dataout, {2{wire_nli1l_dataout}}, {2{1'b1}}, wire_nliii_dataout, wire_nliiO_dataout, 1'b1}), .o(wire_nl1lO_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam nl1lO.width_data = 16, nl1lO.width_sel = 4; oper_mux nl1Oi ( .data({{7{1'b1}}, wire_nl01O_dataout, wire_nl0il_dataout, {2{wire_nli1O_dataout}}, niOOi, wire_nlilO_dataout, niOOi, wire_nlili_dataout, 1'b1}), .o(wire_nl1Oi_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam nl1Oi.width_data = 16, nl1Oi.width_sel = 4; oper_mux nl1Ol ( .data({{7{1'b0}}, wire_nl00i_dataout, wire_nl0iO_dataout, {3{wire_nl00i_dataout}}, wire_nliOi_dataout, wire_nl00i_dataout, {2{1'b0}}}), .o(wire_nl1Ol_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam nl1Ol.width_data = 16, nl1Ol.width_sel = 4; oper_mux nll00i ( .data({{7{1'b1}}, wire_nll0Oi_dataout, wire_nlllll_dataout, {3{wire_nll0Oi_dataout}}, wire_nlO1Oi_dataout, wire_nlllll_dataout, wire_nll0Oi_dataout, 1'b1}), .o(wire_nll00i_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam nll00i.width_data = 16, nll00i.width_sel = 4; oper_mux nll00l ( .data({{7{1'b1}}, wire_nll0Ol_dataout, wire_nllllO_dataout, {2{wire_nllOil_dataout}}, wire_nllOOi_dataout, wire_nlO1Ol_dataout, wire_nllOOO_dataout, wire_nlO10i_dataout, 1'b1}), .o(wire_nll00l_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam nll00l.width_data = 16, nll00l.width_sel = 4; oper_mux nll00O ( .data({{7{1'b0}}, wire_nll0OO_dataout, wire_nlllOi_dataout, {2{wire_nllOiO_dataout}}, wire_nll0OO_dataout, wire_nlO1OO_dataout, wire_nlllOi_dataout, wire_nlO10l_dataout, 1'b0}), .o(wire_nll00O_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam nll00O.width_data = 16, nll00O.width_sel = 4; oper_mux nll01i ( .data({{7{1'b0}}, wire_nll0li_dataout, wire_nlllil_dataout, {3{wire_nll0li_dataout}}, wire_nlO1li_dataout, wire_nlllil_dataout, wire_nll0li_dataout, 1'b0}), .o(wire_nll01i_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam nll01i.width_data = 16, nll01i.width_sel = 4; oper_mux nll01l ( .data({{7{1'b1}}, wire_nll0ll_dataout, wire_nllliO_dataout, {3{wire_nll0ll_dataout}}, wire_nlO1ll_dataout, wire_nllliO_dataout, wire_nll0ll_dataout, 1'b1}), .o(wire_nll01l_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam nll01l.width_data = 16, nll01l.width_sel = 4; oper_mux nll01O ( .data({{7{1'b1}}, wire_nll0lO_dataout, wire_nlllli_dataout, {3{wire_nll0lO_dataout}}, wire_nlO1lO_dataout, wire_nlllli_dataout, wire_nll0lO_dataout, 1'b1}), .o(wire_nll01O_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam nll01O.width_data = 16, nll01O.width_sel = 4; oper_mux nll0ii ( .data({{7{1'b1}}, wire_nlli1i_dataout, wire_nlllOl_dataout, {2{wire_nllOli_dataout}}, wire_nllOOl_dataout, wire_nlO01i_dataout, wire_nlO11i_dataout, wire_nlO10O_dataout, 1'b1}), .o(wire_nll0ii_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam nll0ii.width_data = 16, nll0ii.width_sel = 4; oper_mux nll1Ol ( .data({{7{1'b1}}, wire_nll0il_dataout, wire_nlll0O_dataout, {3{wire_nll0il_dataout}}, wire_nlO1il_dataout, wire_nlll0O_dataout, wire_nll0il_dataout, 1'b1}), .o(wire_nll1Ol_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam nll1Ol.width_data = 16, nll1Ol.width_sel = 4; oper_mux nll1OO ( .data({{7{1'b0}}, wire_nll0iO_dataout, wire_nlllii_dataout, {3{wire_nll0iO_dataout}}, wire_nlO1iO_dataout, wire_nlllii_dataout, wire_nll0iO_dataout, 1'b0}), .o(wire_nll1OO_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam nll1OO.width_data = 16, nll1OO.width_sel = 4; oper_mux nlOi0l ( .data({{7{1'b1}}, wire_nlOiOl_dataout, wire_nlOOll_dataout, {3{wire_nlOiOl_dataout}}, wire_n10li_dataout, wire_nlOOll_dataout, wire_nlOiOl_dataout, 1'b1}), .o(wire_nlOi0l_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam nlOi0l.width_data = 16, nlOi0l.width_sel = 4; oper_mux nlOi0O ( .data({{7{1'b0}}, wire_nlOiOO_dataout, wire_nlOOlO_dataout, {3{wire_nlOiOO_dataout}}, wire_n10ll_dataout, wire_nlOOlO_dataout, wire_nlOiOO_dataout, 1'b0}), .o(wire_nlOi0O_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam nlOi0O.width_data = 16, nlOi0O.width_sel = 4; oper_mux nlOiii ( .data({{7{1'b0}}, wire_nlOl1i_dataout, wire_nlOOOi_dataout, {3{wire_nlOl1i_dataout}}, wire_n10lO_dataout, wire_nlOOOi_dataout, wire_nlOl1i_dataout, 1'b0}), .o(wire_nlOiii_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam nlOiii.width_data = 16, nlOiii.width_sel = 4; oper_mux nlOiil ( .data({{7{1'b1}}, wire_nlOl1l_dataout, wire_nlOOOl_dataout, {3{wire_nlOl1l_dataout}}, wire_n10Oi_dataout, wire_nlOOOl_dataout, wire_nlOl1l_dataout, 1'b1}), .o(wire_nlOiil_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam nlOiil.width_data = 16, nlOiil.width_sel = 4; oper_mux nlOiiO ( .data({{7{1'b1}}, wire_nlOl1O_dataout, wire_nlOOOO_dataout, {3{wire_nlOl1O_dataout}}, wire_n10Ol_dataout, wire_nlOOOO_dataout, wire_nlOl1O_dataout, 1'b1}), .o(wire_nlOiiO_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam nlOiiO.width_data = 16, nlOiiO.width_sel = 4; oper_mux nlOili ( .data({{7{1'b1}}, wire_nlOl0i_dataout, wire_n111i_dataout, {3{wire_nlOl0i_dataout}}, wire_n10OO_dataout, wire_n111i_dataout, wire_nlOl0i_dataout, 1'b1}), .o(wire_nlOili_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam nlOili.width_data = 16, nlOili.width_sel = 4; oper_mux nlOill ( .data({{7{1'b1}}, wire_nlOl0l_dataout, wire_n111l_dataout, {2{wire_n11Oi_dataout}}, wire_n101i_dataout, wire_n1i1i_dataout, wire_n101O_dataout, wire_n10ii_dataout, 1'b1}), .o(wire_nlOill_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam nlOill.width_data = 16, nlOill.width_sel = 4; oper_mux nlOilO ( .data({{7{1'b0}}, wire_nlOl0O_dataout, wire_n111O_dataout, {2{wire_n11Ol_dataout}}, wire_nlOl0O_dataout, wire_n1i1l_dataout, wire_n111O_dataout, wire_n10il_dataout, 1'b0}), .o(wire_nlOilO_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam nlOilO.width_data = 16, nlOilO.width_sel = 4; oper_mux nlOiOi ( .data({{7{1'b1}}, wire_nlOlii_dataout, wire_n110i_dataout, {2{wire_n11OO_dataout}}, wire_n101l_dataout, wire_n1i1O_dataout, wire_n100i_dataout, wire_n10iO_dataout, 1'b1}), .o(wire_nlOiOi_o), .sel({nll0O, nll0i, nll1O, nll1i})); defparam nlOiOi.width_data = 16, nlOiOi.width_sel = 4; assign curr_state = {nll0O, nll0i, nll1O, nll1i}, nil00O = (nil0ii & ((~ nilOi) & (~ n0lOl))), nil01O = ((nil0lO & (~ nil0Oi)) & ((((((~ nll0O) & nll0i) & nll1O) & (~ nll1i)) | ((((~ nll0O) & nll0i) & (~ nll1O)) & nll1i)) | (niOli & nil0ll))), nil0ii = ((((((((((((((((((((((((~ nliO0O) & (~ nliO0i)) & (~ nliO1O)) & (~ nliO1l)) & (~ nliO1i)) & (~ nlilOO)) & (~ nlilOl)) & nlillO) & (~ nlilll)) & (~ nlilli)) & (~ nliliO)) & (~ nlilil)) & (~ nlilii)) & (~ nlil0O)) & (~ nlil0l)) & (~ nlil0i)) & (~ nlil1O)) & (~ nlil1l)) & (~ nlil1i)) & (~ nliiOO)) & (~ nliiOl)) & (~ nliiOi)) & (~ nliilO)) & (~ nliill)), nil0il = (((((((~ nll0O) & (~ nll0i)) & nll1O) & (~ nll1i)) | ((((~ nll0O) & nll0i) & nll1O) & nll1i)) & nil0lO) & nliOii), nil0iO = ((((~ nll0O) & (~ nll0i)) & nll1O) & nll1i), nil0li = (nil0lO & nil0ll), nil0ll = ((((~ nll0O) & (~ nll0i)) & (~ nll1O)) & nll1i), nil0lO = (niOOOi | niOlil), nil0Oi = ((((nli00i | nli1ii) | nli10O) | nli10l) | nli10i), nil0Ol = (niOli & (~ nil0Oi)), nil0OO = ((~ niOOOi) & (~ niOlil)), nili0l = (((niOO1i | niliil) & rxaui_s2gx_en) | ((niOiii & (niOiOO | niliii)) & (~ rxaui_s2gx_en))), nili0O = ((niliil & rxaui_s2gx_en) | ((niOiiO & niliii) & (~ rxaui_s2gx_en))), nili1l = 1'b1, niliii = (niOl0i | niOl1l), niliil = (niOOiO | niOO0l), niliiO = (nilill | ((niOl0i & niOiOi) & (~ rxaui_s2gx_en))), nilili = ((niOl0i & (~ rxaui_s2gx_en)) | nilill), nilill = (niOOiO & rxaui_s2gx_en), nililO = (((((((((((tx_ctl[3] & (~ niOiil)) & (~ nillii)) & (~ nill0O)) & (~ niOlOO)) & (~ nill0l)) & (~ nill0i)) & (~ nill1O)) & (~ nill1l)) & (~ nill1i)) & ((((~ niliOO) & (~ niliOl)) & (~ niliOi)) | rxaui_s2gx_en)) | ((niOiii & (~ (niOiOO | nilliO))) & (~ rxaui_s2gx_en))), niliOi = ((((((((~ tx_data[24]) & (~ tx_data[25])) & tx_data[26]) & tx_data[27]) & tx_data[28]) & tx_data[29]) & (~ tx_data[30])) & tx_data[31]), niliOl = ((((((((~ tx_data[24]) & (~ tx_data[25])) & tx_data[26]) & tx_data[27]) & tx_data[28]) & tx_data[29]) & tx_data[30]) & (~ tx_data[31])), niliOO = ((((((((~ tx_data[24]) & (~ tx_data[25])) & tx_data[26]) & tx_data[27]) & tx_data[28]) & (~ tx_data[29])) & (~ tx_data[30])) & (~ tx_data[31])), nill0i = ((((((((~ tx_data[24]) & (~ tx_data[25])) & tx_data[26]) & tx_data[27]) & tx_data[28]) & (~ tx_data[29])) & tx_data[30]) & (~ tx_data[31])), nill0l = ((((((((~ tx_data[24]) & (~ tx_data[25])) & tx_data[26]) & tx_data[27]) & tx_data[28]) & tx_data[29]) & (~ tx_data[30])) & (~ tx_data[31])), nill0O = (((((((tx_data[24] & tx_data[25]) & (~ tx_data[26])) & tx_data[27]) & tx_data[28]) & tx_data[29]) & tx_data[30]) & tx_data[31]), nill1i = (((((((tx_data[24] & tx_data[25]) & tx_data[26]) & (~ tx_data[27])) & tx_data[28]) & tx_data[29]) & tx_data[30]) & tx_data[31]), nill1l = ((((((((~ tx_data[24]) & (~ tx_data[25])) & tx_data[26]) & tx_data[27]) & tx_data[28]) & tx_data[29]) & tx_data[30]) & tx_data[31]), nill1O = ((((((((~ tx_data[24]) & (~ tx_data[25])) & tx_data[26]) & tx_data[27]) & tx_data[28]) & (~ tx_data[29])) & tx_data[30]) & tx_data[31]), nillii = ((((((((~ tx_data[24]) & (~ tx_data[25])) & tx_data[26]) & tx_data[27]) & tx_data[28]) & (~ tx_data[29])) & (~ tx_data[30])) & tx_data[31]), nillil = (((((((((((tx_ctl[2] & (~ niOilO)) & (~ nilO0i)) & (~ nilO1O)) & (~ niOl1i)) & (~ nilO1l)) & (~ nilO1i)) & (~ nillOO)) & (~ nillOl)) & (~ nillOi)) & ((((~ nilllO) & (~ nillll)) & (~ nillli)) | rxaui_s2gx_en)) | ((niOiiO & (~ nilliO)) & (~ rxaui_s2gx_en))), nilliO = (niOl1l | nilO0O), nillli = ((((((((~ tx_data[16]) & (~ tx_data[17])) & tx_data[18]) & tx_data[19]) & tx_data[20]) & tx_data[21]) & (~ tx_data[22])) & tx_data[23]), nillll = ((((((((~ tx_data[16]) & (~ tx_data[17])) & tx_data[18]) & tx_data[19]) & tx_data[20]) & tx_data[21]) & tx_data[22]) & (~ tx_data[23])), nilllO = ((((((((~ tx_data[16]) & (~ tx_data[17])) & tx_data[18]) & tx_data[19]) & tx_data[20]) & (~ tx_data[21])) & (~ tx_data[22])) & (~ tx_data[23])), nillOi = (((((((tx_data[16] & tx_data[17]) & tx_data[18]) & (~ tx_data[19])) & tx_data[20]) & tx_data[21]) & tx_data[22]) & tx_data[23]), nillOl = ((((((((~ tx_data[16]) & (~ tx_data[17])) & tx_data[18]) & tx_data[19]) & tx_data[20]) & tx_data[21]) & tx_data[22]) & tx_data[23]), nillOO = ((((((((~ tx_data[16]) & (~ tx_data[17])) & tx_data[18]) & tx_data[19]) & tx_data[20]) & (~ tx_data[21])) & tx_data[22]) & tx_data[23]), nilO0i = ((((((((~ tx_data[16]) & (~ tx_data[17])) & tx_data[18]) & tx_data[19]) & tx_data[20]) & (~ tx_data[21])) & (~ tx_data[22])) & tx_data[23]), nilO0l = ((((((((((((((tx_ctl[1] & (~ niOiOl)) & (~ niO1ii)) & (niO10l36 ^ niO10l35)) & (~ niO10i)) & (~ niOl1O)) & (~ niO11O)) & (niO11i38 ^ niO11i37)) & (~ nilOOO)) & (~ nilOOl)) & (~ nilOOi)) & (nilOll40 ^ nilOll39)) & (~ nilOli)) & ((((~ nilOiO) & (~ nilOil)) & (~ nilOii)) | rxaui_s2gx_en)) | ((niOiOi & (~ nilO0O)) & (~ rxaui_s2gx_en))), nilO0O = (niOOOi | niOl0i), nilO1i = ((((((((~ tx_data[16]) & (~ tx_data[17])) & tx_data[18]) & tx_data[19]) & tx_data[20]) & (~ tx_data[21])) & tx_data[22]) & (~ tx_data[23])), nilO1l = ((((((((~ tx_data[16]) & (~ tx_data[17])) & tx_data[18]) & tx_data[19]) & tx_data[20]) & tx_data[21]) & (~ tx_data[22])) & (~ tx_data[23])), nilO1O = (((((((tx_data[16] & tx_data[17]) & (~ tx_data[18])) & tx_data[19]) & tx_data[20]) & tx_data[21]) & tx_data[22]) & tx_data[23]), nilOii = ((((((((~ tx_data[8]) & (~ tx_data[9])) & tx_data[10]) & tx_data[11]) & tx_data[12]) & tx_data[13]) & (~ tx_data[14])) & tx_data[15]), nilOil = ((((((((~ tx_data[8]) & (~ tx_data[9])) & tx_data[10]) & tx_data[11]) & tx_data[12]) & tx_data[13]) & tx_data[14]) & (~ tx_data[15])), nilOiO = ((((((((~ tx_data[8]) & (~ tx_data[9])) & tx_data[10]) & tx_data[11]) & tx_data[12]) & (~ tx_data[13])) & (~ tx_data[14])) & (~ tx_data[15])), nilOli = (((((((tx_data[8] & tx_data[9]) & tx_data[10]) & (~ tx_data[11])) & tx_data[12]) & tx_data[13]) & tx_data[14]) & tx_data[15]), nilOOi = ((((((((~ tx_data[8]) & (~ tx_data[9])) & tx_data[10]) & tx_data[11]) & tx_data[12]) & tx_data[13]) & tx_data[14]) & tx_data[15]), nilOOl = ((((((((~ tx_data[8]) & (~ tx_data[9])) & tx_data[10]) & tx_data[11]) & tx_data[12]) & (~ tx_data[13])) & tx_data[14]) & tx_data[15]), nilOOO = ((((((((~ tx_data[8]) & (~ tx_data[9])) & tx_data[10]) & tx_data[11]) & tx_data[12]) & (~ tx_data[13])) & tx_data[14]) & (~ tx_data[15])), niO00i = ((((((((~ tx_data[0]) & (~ tx_data[1])) & tx_data[2]) & tx_data[3]) & tx_data[4]) & tx_data[5]) & (~ tx_data[6])) & tx_data[7]), niO00l = ((((((((~ tx_data[0]) & (~ tx_data[1])) & tx_data[2]) & tx_data[3]) & tx_data[4]) & tx_data[5]) & tx_data[6]) & (~ tx_data[7])), niO00O = ((((((((~ tx_data[0]) & (~ tx_data[1])) & tx_data[2]) & tx_data[3]) & tx_data[4]) & (~ tx_data[5])) & (~ tx_data[6])) & (~ tx_data[7])), niO0ii = (((((((tx_data[0] & tx_data[1]) & tx_data[2]) & (~ tx_data[3])) & tx_data[4]) & tx_data[5]) & tx_data[6]) & tx_data[7]), niO0li = ((((((((~ tx_data[0]) & (~ tx_data[1])) & tx_data[2]) & tx_data[3]) & tx_data[4]) & tx_data[5]) & tx_data[6]) & tx_data[7]), niO0Oi = ((((((((~ tx_data[0]) & (~ tx_data[1])) & tx_data[2]) & tx_data[3]) & tx_data[4]) & (~ tx_data[5])) & tx_data[6]) & tx_data[7]), niO0Ol = ((((((((~ tx_data[0]) & (~ tx_data[1])) & tx_data[2]) & tx_data[3]) & tx_data[4]) & (~ tx_data[5])) & tx_data[6]) & (~ tx_data[7])), niO0OO = ((((((((~ tx_data[0]) & (~ tx_data[1])) & tx_data[2]) & tx_data[3]) & tx_data[4]) & tx_data[5]) & (~ tx_data[6])) & (~ tx_data[7])), niO10i = (((((((tx_data[8] & tx_data[9]) & (~ tx_data[10])) & tx_data[11]) & tx_data[12]) & tx_data[13]) & tx_data[14]) & tx_data[15]), niO11O = ((((((((~ tx_data[8]) & (~ tx_data[9])) & tx_data[10]) & tx_data[11]) & tx_data[12]) & tx_data[13]) & (~ tx_data[14])) & (~ tx_data[15])), niO1ii = ((((((((~ tx_data[8]) & (~ tx_data[9])) & tx_data[10]) & tx_data[11]) & tx_data[12]) & (~ tx_data[13])) & (~ tx_data[14])) & tx_data[15]), niO1il = (((((((((((((((((tx_ctl[0] & (~ niOi0O)) & (~ niOliO)) & (niOi0i18 ^ niOi0i17)) & (~ niOi1O)) & (niOi1i20 ^ niOi1i19)) & (~ niOlii)) & (~ niO0OO)) & (~ niO0Ol)) & (~ niO0Oi)) & (niO0ll22 ^ niO0ll21)) & (~ niO0li)) & (niO0il24 ^ niO0il23)) & (~ niO0ii)) & (((((~ niO00O) & (~ niO00l)) & (~ niO00i)) & (niO01l26 ^ niO01l25)) | rxaui_s2gx_en)) & (niO1OO28 ^ niO1OO27)) | ((((~ niOOOi) & ((tx_ctl[0] & niOi0O) & (niO1Oi30 ^ niO1Oi29))) & (niO1ll32 ^ niO1ll31)) & (~ rxaui_s2gx_en))) | (~ (niO1iO34 ^ niO1iO33))), niOi0O = (((((((tx_data[0] & tx_data[1]) & tx_data[2]) & (~ tx_data[3])) & (~ tx_data[4])) & (~ tx_data[5])) & (~ tx_data[6])) & (~ tx_data[7])), niOi1O = (((((((tx_data[0] & tx_data[1]) & (~ tx_data[2])) & tx_data[3]) & tx_data[4]) & tx_data[5]) & tx_data[6]) & tx_data[7]), niOiii = (tx_ctl[3] & niOiil), niOiil = (((((((tx_data[24] & tx_data[25]) & tx_data[26]) & (~ tx_data[27])) & (~ tx_data[28])) & (~ tx_data[29])) & (~ tx_data[30])) & (~ tx_data[31])), niOiiO = ((tx_ctl[2] & niOilO) & (niOili16 ^ niOili15)), niOilO = (((((((tx_data[16] & tx_data[17]) & tx_data[18]) & (~ tx_data[19])) & (~ tx_data[20])) & (~ tx_data[21])) & (~ tx_data[22])) & (~ tx_data[23])), niOiOi = (tx_ctl[1] & niOiOl), niOiOl = (((((((tx_data[8] & tx_data[9]) & tx_data[10]) & (~ tx_data[11])) & (~ tx_data[12])) & (~ tx_data[13])) & (~ tx_data[14])) & (~ tx_data[15])), niOiOO = (tx_ctl[2] & niOl1i), niOl0i = ((tx_ctl[0] & niOlii) & (niOl0l14 ^ niOl0l13)), niOl1i = (((((((tx_data[16] & (~ tx_data[17])) & tx_data[18]) & tx_data[19]) & tx_data[20]) & tx_data[21]) & tx_data[22]) & tx_data[23]), niOl1l = (tx_ctl[1] & niOl1O), niOl1O = (((((((tx_data[8] & (~ tx_data[9])) & tx_data[10]) & tx_data[11]) & tx_data[12]) & tx_data[13]) & tx_data[14]) & tx_data[15]), niOlii = (((((((tx_data[0] & (~ tx_data[1])) & tx_data[2]) & tx_data[3]) & tx_data[4]) & tx_data[5]) & tx_data[6]) & tx_data[7]), niOlil = (((((tx_ctl[0] & (~ tx_ctl[1])) & (~ tx_ctl[2])) & (~ tx_ctl[3])) & (niOlli12 ^ niOlli11)) & niOliO), niOliO = ((((((((~ tx_data[0]) & (~ tx_data[1])) & tx_data[2]) & tx_data[3]) & tx_data[4]) & (~ tx_data[5])) & (~ tx_data[6])) & tx_data[7]), niOllO = ((tx_ctl[3] & niOlOO) & (niOlOi10 ^ niOlOi9)), niOlOO = (((((((tx_data[24] & (~ tx_data[25])) & tx_data[26]) & tx_data[27]) & tx_data[28]) & tx_data[29]) & tx_data[30]) & tx_data[31]), niOO0i = (((((((((((((((tx_data[16] & (~ tx_data[17])) & tx_data[18]) & tx_data[19]) & tx_data[20]) & tx_data[21]) & tx_data[22]) & tx_data[23]) & tx_data[24]) & tx_data[25]) & tx_data[26]) & (~ tx_data[27])) & (~ tx_data[28])) & (~ tx_data[29])) & (~ tx_data[30])) & (~ tx_data[31])), niOO0l = ((((tx_ctl[1] & tx_ctl[2]) & tx_ctl[3]) & (niOOii6 ^ niOOii5)) & niOO0O), niOO0O = (((((((((((((((((((((((tx_data[8] & (~ tx_data[9])) & tx_data[10]) & tx_data[11]) & tx_data[12]) & tx_data[13]) & tx_data[14]) & tx_data[15]) & tx_data[16]) & tx_data[17]) & tx_data[18]) & (~ tx_data[19])) & (~ tx_data[20])) & (~ tx_data[21])) & (~ tx_data[22])) & (~ tx_data[23])) & tx_data[24]) & tx_data[25]) & tx_data[26]) & (~ tx_data[27])) & (~ tx_data[28])) & (~ tx_data[29])) & (~ tx_data[30])) & (~ tx_data[31])), niOO1i = (((tx_ctl[2] & tx_ctl[3]) & niOO0i) & (niOO1l8 ^ niOO1l7)), niOOiO = (((((tx_ctl[0] & tx_ctl[1]) & tx_ctl[2]) & tx_ctl[3]) & (niOOll4 ^ niOOll3)) & niOOli), niOOli = (((((((((((((((((((((((((((((((tx_data[0] & (~ tx_data[1])) & tx_data[2]) & tx_data[3]) & tx_data[4]) & tx_data[5]) & tx_data[6]) & tx_data[7]) & tx_data[8]) & tx_data[9]) & tx_data[10]) & (~ tx_data[11])) & (~ tx_data[12])) & (~ tx_data[13])) & (~ tx_data[14])) & (~ tx_data[15])) & tx_data[16]) & tx_data[17]) & tx_data[18]) & (~ tx_data[19])) & (~ tx_data[20])) & (~ tx_data[21])) & (~ tx_data[22])) & (~ tx_data[23])) & tx_data[24]) & tx_data[25]) & tx_data[26]) & (~ tx_data[27])) & (~ tx_data[28])) & (~ tx_data[29])) & (~ tx_data[30])) & (~ tx_data[31])), niOOOi = (((((tx_ctl[0] & tx_ctl[1]) & tx_ctl[2]) & tx_ctl[3]) & (niOOOO2 ^ niOOOO1)) & niOOOl), niOOOl = (((((((((((((((((((((((((((((((tx_data[0] & tx_data[1]) & tx_data[2]) & (~ tx_data[3])) & (~ tx_data[4])) & (~ tx_data[5])) & (~ tx_data[6])) & (~ tx_data[7])) & tx_data[8]) & tx_data[9]) & tx_data[10]) & (~ tx_data[11])) & (~ tx_data[12])) & (~ tx_data[13])) & (~ tx_data[14])) & (~ tx_data[15])) & tx_data[16]) & tx_data[17]) & tx_data[18]) & (~ tx_data[19])) & (~ tx_data[20])) & (~ tx_data[21])) & (~ tx_data[22])) & (~ tx_data[23])) & tx_data[24]) & tx_data[25]) & tx_data[26]) & (~ tx_data[27])) & (~ tx_data[28])) & (~ tx_data[29])) & (~ tx_data[30])) & (~ tx_data[31])), sm_ctl = {nliOil, nll10i, nlO0li, n1ilO}, sm_data = {nll11O, nll11l, nll11i, nliOOO, nliOOl, nliOOi, nliOlO, nliOll, nlO0iO, nlO0il, nlO0ii, nlO00O, nlO00l, nlO00i, nlO01O, nlO01l, n1ill, n1ili, n1iiO, n1iil, n1iii, n1i0O, n1i0l, n1i0i, n0lOi, n0llO, n0lll, n0lli, n0liO, n0lil, n0lii, n0l0O}, tx_local_fault = niOiO, tx_local_fault_det = n0lOl; endmodule //stratixiv_hssi_tx_sm //synopsys translate_on //VALID FILE //IP Functional Simulation Model //VERSION_BEGIN 12.0 cbx_mgl 2012:05:31:20:09:47:SJ cbx_simgen 2012:05:31:20:08:35:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 // Copyright (C) 1991-2012 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // You may only use these simulation model output files for simulation // purposes and expressly not for synthesis or any other purposes (in which // event Altera disclaims all warranties of any kind). //synopsys translate_off //synthesis_resources = lut 170 mux21 775 oper_mux 3 `timescale 1 ps / 1 ps module stratixiv_hssi_rcv_sm ( clk_2, curr_state, dec_ctl, dec_data, dec_data_valid, indv, running_disp, rx_ctl_rs, rx_data_rs, rx_local_fault, rx_local_fault_clr, rxaui_s2gx_en, soft_reset, tx_local_fault_det, xs_link_status, xs_link_status_set) /* synthesis synthesis_clearbox=1 */; input clk_2; output [1:0] curr_state; input [3:0] dec_ctl; input [31:0] dec_data; input [3:0] dec_data_valid; input indv; input [3:0] running_disp; output [3:0] rx_ctl_rs; output [31:0] rx_data_rs; output rx_local_fault; input rx_local_fault_clr; input rxaui_s2gx_en; input soft_reset; input tx_local_fault_det; output xs_link_status; input xs_link_status_set; reg n0Olli45; reg n0Olli46; reg n0OlOl43; reg n0OlOl44; reg n0OO0l39; reg n0OO0l40; reg n0OO1l41; reg n0OO1l42; reg n0OOil37; reg n0OOil38; reg n0OOiO35; reg n0OOiO36; reg n0OOli33; reg n0OOli34; reg n0OOlO31; reg n0OOlO32; reg n0OOOl29; reg n0OOOl30; reg n0OOOO27; reg n0OOOO28; reg ni100l15; reg ni100l16; reg ni10OO13; reg ni10OO14; reg ni110l23; reg ni110l24; reg ni111l25; reg ni111l26; reg ni11ii21; reg ni11ii22; reg ni11Oi19; reg ni11Oi20; reg ni11OO17; reg ni11OO18; reg ni1i0O11; reg ni1i0O12; reg ni1ili10; reg ni1ili9; reg ni1ilO7; reg ni1ilO8; reg ni1l1O5; reg ni1l1O6; reg ni1lil3; reg ni1lil4; reg ni1lli1; reg ni1lli2; reg n000i; reg n001O; reg n00ii; reg n01Ol; reg n0liO; reg n0lli; reg n0lll; reg n0llO; reg n0lOi; reg n0lOl; reg n0lOO; reg n0O1i; reg n0O1l; reg n10il; reg n10iO; reg n10li; reg n10ll; reg n10lO; reg n10Oi; reg n10Ol; reg n10OO; reg n11l; reg n1i1i; reg nii00i; reg nii00l; reg nii00O; reg nii0ii; reg nii0il; reg nii0lO; reg nii0Oi; reg niiii; reg niiil; reg niiiO; reg niili; reg niill; reg niilO; reg niiOi; reg niiOl; reg nill0i; reg nill1l; reg nill1O; reg nillil; reg nilliO; reg nillll; reg niO00i; reg niO00l; reg niO00O; reg niO01O; reg niO0ii; reg niO0il; reg niO0iO; reg niO0li; reg niO0ll; reg nl00i; reg nl00l; reg nl00O; reg nl0ii; reg nl0iiO; reg nl0il; reg nl0ili; reg nl0ill; reg nl0ilO; reg nl0iO; reg nl0iOi; reg nl0iOl; reg nl0iOO; reg nl0l1i; reg nl0l1l; reg nl0li; reg nl0ll; reg nl0lO; reg nl1l0O; reg nl1lii; reg nl1lil; reg nl1liO; reg nl1lli; reg nl1lll; reg nl1llO; reg nl1lOi; reg nl1lOl; reg nliOlO; reg nliOOi; reg nliOOl; reg nliOOO; reg nll10i; reg nll11i; reg nll11l; reg nll11O; reg nlllOO; reg nllO0i; reg nllO0l; reg nllO0O; reg nllO1i; reg nllO1l; reg nllO1O; reg nllOii; reg nlO0i; reg nlO0l; reg nlO0O; reg nlOii; reg nlOil; reg nlOiO; reg nlOli; reg nlOll; reg nlOlO; reg n11i_clk_prev; wire wire_n11i_CLRN; wire wire_n11i_PRN; reg n000l; reg n000O; reg n001i; reg n001l; reg n01OO; reg n10i; reg nii0iO; reg nii0li; reg nii0ll; reg nii0Ol; reg nii0OO; reg niii1i; reg niiOO; reg nill0l; reg nill0O; reg nillii; reg nillli; reg nll10l; reg nllOil; reg n11O_clk_prev; wire wire_n11O_CLRN; wire wire_n00il_dataout; wire wire_n00iO_dataout; wire wire_n00li_dataout; wire wire_n00ll_dataout; wire wire_n00lO_dataout; wire wire_n00Oi_dataout; wire wire_n00Ol_dataout; wire wire_n00OO_dataout; wire wire_n010i_dataout; wire wire_n010l_dataout; wire wire_n010O_dataout; wire wire_n011i_dataout; wire wire_n011l_dataout; wire wire_n011O_dataout; wire wire_n01ii_dataout; wire wire_n01il_dataout; wire wire_n01iO_dataout; wire wire_n01li_dataout; wire wire_n0i_dataout; wire wire_n0i0i_dataout; wire wire_n0i0l_dataout; wire wire_n0i0O_dataout; wire wire_n0i1i_dataout; wire wire_n0i1l_dataout; wire wire_n0i1O_dataout; wire wire_n0iii_dataout; wire wire_n0iil_dataout; wire wire_n0iiO_dataout; wire wire_n0ili_dataout; wire wire_n0ill_dataout; wire wire_n0ilO_dataout; wire wire_n0iOi_dataout; wire wire_n0iOl_dataout; wire wire_n0iOO_dataout; wire wire_n0l_dataout; wire wire_n0l0i_dataout; wire wire_n0l1i_dataout; wire wire_n0l1l_dataout; wire wire_n0l1O_dataout; wire wire_n0O_dataout; wire wire_n0O0i_dataout; wire wire_n0O0l_dataout; wire wire_n0O0O_dataout; wire wire_n0O1O_dataout; wire wire_n0Oii_dataout; wire wire_n0Oil_dataout; wire wire_n0OiO_dataout; wire wire_n0Oli_dataout; wire wire_n0Oll_dataout; wire wire_n0OlO_dataout; wire wire_n0OOi_dataout; wire wire_n0OOl_dataout; wire wire_n0OOO_dataout; wire wire_n100i_dataout; wire wire_n100l_dataout; wire wire_n101i_dataout; wire wire_n101l_dataout; wire wire_n101O_dataout; wire wire_n10l_dataout; wire wire_n10O_dataout; wire wire_n110i_dataout; wire wire_n110l_dataout; wire wire_n110O_dataout; wire wire_n111i_dataout; wire wire_n111l_dataout; wire wire_n111O_dataout; wire wire_n11ii_dataout; wire wire_n11il_dataout; wire wire_n11iO_dataout; wire wire_n11li_dataout; wire wire_n11lO_dataout; wire wire_n11Oi_dataout; wire wire_n11Ol_dataout; wire wire_n11OO_dataout; wire wire_n1i_dataout; wire wire_n1i0i_dataout; wire wire_n1i0l_dataout; wire wire_n1i0O_dataout; wire wire_n1i1l_dataout; wire wire_n1i1O_dataout; wire wire_n1iii_dataout; wire wire_n1iil_dataout; wire wire_n1iiO_dataout; wire wire_n1ili_dataout; wire wire_n1ill_dataout; wire wire_n1ilO_dataout; wire wire_n1iOi_dataout; wire wire_n1iOl_dataout; wire wire_n1iOO_dataout; wire wire_n1l_dataout; wire wire_n1l0i_dataout; wire wire_n1l0l_dataout; wire wire_n1l0O_dataout; wire wire_n1l1i_dataout; wire wire_n1l1l_dataout; wire wire_n1l1O_dataout; wire wire_n1lii_dataout; wire wire_n1lil_dataout; wire wire_n1liO_dataout; wire wire_n1lli_dataout; wire wire_n1lll_dataout; wire wire_n1llO_dataout; wire wire_n1lOi_dataout; wire wire_n1lOl_dataout; wire wire_n1lOO_dataout; wire wire_n1O_dataout; wire wire_n1O0i_dataout; wire wire_n1O0l_dataout; wire wire_n1O0O_dataout; wire wire_n1O1i_dataout; wire wire_n1O1l_dataout; wire wire_n1O1O_dataout; wire wire_n1Oii_dataout; wire wire_n1Oil_dataout; wire wire_n1OiO_dataout; wire wire_n1Oli_dataout; wire wire_n1Oll_dataout; wire wire_n1OlO_dataout; wire wire_n1OOi_dataout; wire wire_n1OOl_dataout; wire wire_n1OOO_dataout; wire wire_ni_dataout; wire wire_ni00i_dataout; wire wire_ni00l_dataout; wire wire_ni00O_dataout; wire wire_ni01i_dataout; wire wire_ni01l_dataout; wire wire_ni01O_dataout; wire wire_ni0i_dataout; wire wire_ni0ii_dataout; wire wire_ni0il_dataout; wire wire_ni0l_dataout; wire wire_ni0lO_dataout; wire wire_ni0O_dataout; wire wire_ni0Oi_dataout; wire wire_ni0Ol_dataout; wire wire_ni0OO_dataout; wire wire_ni10i_dataout; wire wire_ni10l_dataout; wire wire_ni10O_dataout; wire wire_ni11i_dataout; wire wire_ni11l_dataout; wire wire_ni11O_dataout; wire wire_ni1ii_dataout; wire wire_ni1il_dataout; wire wire_ni1iO_dataout; wire wire_ni1li_dataout; wire wire_ni1ll_dataout; wire wire_ni1lO_dataout; wire wire_ni1O_dataout; wire wire_ni1Oi_dataout; wire wire_ni1Ol_dataout; wire wire_ni1OO_dataout; wire wire_nii_dataout; wire wire_nii0i_dataout; wire wire_nii0l_dataout; wire wire_nii1i_dataout; wire wire_nii1l_dataout; wire wire_nii1O_dataout; wire wire_niii0i_dataout; wire wire_niii0l_dataout; wire wire_niii0O_dataout; wire wire_niii1l_dataout; wire wire_niii1O_dataout; wire wire_niiiii_dataout; wire wire_niiiil_dataout; wire wire_niiiiO_dataout; wire wire_niiili_dataout; wire wire_niiill_dataout; wire wire_niiilO_dataout; wire wire_niiiOi_dataout; wire wire_niiiOl_dataout; wire wire_niiiOO_dataout; wire wire_niil0i_dataout; wire wire_niil0l_dataout; wire wire_niil0O_dataout; wire wire_niil1i_dataout; wire wire_niil1l_dataout; wire wire_niil1O_dataout; wire wire_niilii_dataout; wire wire_niilil_dataout; wire wire_niiliO_dataout; wire wire_niilli_dataout; wire wire_niilll_dataout; wire wire_niillO_dataout; wire wire_niilOi_dataout; wire wire_niilOl_dataout; wire wire_niilOO_dataout; wire wire_niiO0i_dataout; wire wire_niiO0l_dataout; wire wire_niiO0O_dataout; wire wire_niiO1i_dataout; wire wire_niiO1l_dataout; wire wire_niiO1O_dataout; wire wire_niiOii_dataout; wire wire_niiOil_dataout; wire wire_niiOiO_dataout; wire wire_niiOli_dataout; wire wire_niiOll_dataout; wire wire_niiOlO_dataout; wire wire_niiOOi_dataout; wire wire_niiOOl_dataout; wire wire_niiOOO_dataout; wire wire_nil_dataout; wire wire_nil00i_dataout; wire wire_nil00l_dataout; wire wire_nil00O_dataout; wire wire_nil01i_dataout; wire wire_nil01l_dataout; wire wire_nil01O_dataout; wire wire_nil0i_dataout; wire wire_nil0ii_dataout; wire wire_nil0il_dataout; wire wire_nil0iO_dataout; wire wire_nil0l_dataout; wire wire_nil0li_dataout; wire wire_nil0ll_dataout; wire wire_nil0lO_dataout; wire wire_nil0O_dataout; wire wire_nil0Oi_dataout; wire wire_nil0Ol_dataout; wire wire_nil0OO_dataout; wire wire_nil10i_dataout; wire wire_nil10l_dataout; wire wire_nil10O_dataout; wire wire_nil11i_dataout; wire wire_nil11l_dataout; wire wire_nil11O_dataout; wire wire_nil1i_dataout; wire wire_nil1ii_dataout; wire wire_nil1il_dataout; wire wire_nil1iO_dataout; wire wire_nil1l_dataout; wire wire_nil1li_dataout; wire wire_nil1ll_dataout; wire wire_nil1lO_dataout; wire wire_nil1O_dataout; wire wire_nil1Oi_dataout; wire wire_nil1Ol_dataout; wire wire_nil1OO_dataout; wire wire_nili_dataout; wire wire_nili0i_dataout; wire wire_nili0l_dataout; wire wire_nili0O_dataout; wire wire_nili1i_dataout; wire wire_nili1l_dataout; wire wire_nili1O_dataout; wire wire_nilii_dataout; wire wire_niliii_dataout; wire wire_niliil_dataout; wire wire_niliiO_dataout; wire wire_nilil_dataout; wire wire_nilili_dataout; wire wire_nilill_dataout; wire wire_nililO_dataout; wire wire_niliO_dataout; wire wire_niliOi_dataout; wire wire_niliOl_dataout; wire wire_niliOO_dataout; wire wire_nill_dataout; wire wire_nill1i_dataout; wire wire_nilli_dataout; wire wire_nilll_dataout; wire wire_nilllO_dataout; wire wire_nillO_dataout; wire wire_nillOi_dataout; wire wire_nillOl_dataout; wire wire_nillOO_dataout; wire wire_nilO_dataout; wire wire_nilO0i_dataout; wire wire_nilO0l_dataout; wire wire_nilO0O_dataout; wire wire_nilO1i_dataout; wire wire_nilO1l_dataout; wire wire_nilO1O_dataout; wire wire_nilOi_dataout; wire wire_nilOii_dataout; wire wire_nilOil_dataout; wire wire_nilOiO_dataout; wire wire_nilOl_dataout; wire wire_nilOli_dataout; wire wire_nilOll_dataout; wire wire_nilOlO_dataout; wire wire_nilOO_dataout; wire wire_nilOOi_dataout; wire wire_nilOOl_dataout; wire wire_nilOOO_dataout; wire wire_niO_dataout; wire wire_niO01i_dataout; wire wire_niO01l_dataout; wire wire_niO0i_dataout; wire wire_niO0l_dataout; wire wire_niO0lO_dataout; wire wire_niO0O_dataout; wire wire_niO0Oi_dataout; wire wire_niO0Ol_dataout; wire wire_niO0OO_dataout; wire wire_niO10i_dataout; wire wire_niO10l_dataout; wire wire_niO10O_dataout; wire wire_niO11i_dataout; wire wire_niO11l_dataout; wire wire_niO11O_dataout; wire wire_niO1i_dataout; wire wire_niO1ii_dataout; wire wire_niO1il_dataout; wire wire_niO1iO_dataout; wire wire_niO1l_dataout; wire wire_niO1li_dataout; wire wire_niO1ll_dataout; wire wire_niO1lO_dataout; wire wire_niO1O_dataout; wire wire_niO1Oi_dataout; wire wire_niO1Ol_dataout; wire wire_niO1OO_dataout; wire wire_niOi_dataout; wire wire_niOi0i_dataout; wire wire_niOi0l_dataout; wire wire_niOi0O_dataout; wire wire_niOi1i_dataout; wire wire_niOi1l_dataout; wire wire_niOi1O_dataout; wire wire_niOii_dataout; wire wire_niOiii_dataout; wire wire_niOiil_dataout; wire wire_niOiiO_dataout; wire wire_niOil_dataout; wire wire_niOili_dataout; wire wire_niOill_dataout; wire wire_niOilO_dataout; wire wire_niOiO_dataout; wire wire_niOiOi_dataout; wire wire_niOiOl_dataout; wire wire_niOiOO_dataout; wire wire_niOl_dataout; wire wire_niOl0i_dataout; wire wire_niOl0l_dataout; wire wire_niOl0O_dataout; wire wire_niOl1i_dataout; wire wire_niOl1l_dataout; wire wire_niOl1O_dataout; wire wire_niOli_dataout; wire wire_niOlii_dataout; wire wire_niOlil_dataout; wire wire_niOliO_dataout; wire wire_niOll_dataout; wire wire_niOlli_dataout; wire wire_niOlll_dataout; wire wire_niOllO_dataout; wire wire_niOlO_dataout; wire wire_niOlOi_dataout; wire wire_niOlOl_dataout; wire wire_niOlOO_dataout; wire wire_niOO_dataout; wire wire_niOO0i_dataout; wire wire_niOO0l_dataout; wire wire_niOO0O_dataout; wire wire_niOO1i_dataout; wire wire_niOO1l_dataout; wire wire_niOO1O_dataout; wire wire_niOOi_dataout; wire wire_niOOii_dataout; wire wire_niOOil_dataout; wire wire_niOOiO_dataout; wire wire_niOOl_dataout; wire wire_niOOli_dataout; wire wire_niOOll_dataout; wire wire_niOOlO_dataout; wire wire_niOOO_dataout; wire wire_niOOOi_dataout; wire wire_niOOOl_dataout; wire wire_niOOOO_dataout; wire wire_nl_dataout; wire wire_nl000i_dataout; wire wire_nl000l_dataout; wire wire_nl000O_dataout; wire wire_nl001i_dataout; wire wire_nl001l_dataout; wire wire_nl001O_dataout; wire wire_nl00ii_dataout; wire wire_nl00il_dataout; wire wire_nl00iO_dataout; wire wire_nl00li_dataout; wire wire_nl00ll_dataout; wire wire_nl00lO_dataout; wire wire_nl00Oi_dataout; wire wire_nl00Ol_dataout; wire wire_nl00OO_dataout; wire wire_nl010i_dataout; wire wire_nl010l_dataout; wire wire_nl010O_dataout; wire wire_nl011i_dataout; wire wire_nl011l_dataout; wire wire_nl011O_dataout; wire wire_nl01i_dataout; wire wire_nl01ii_dataout; wire wire_nl01il_dataout; wire wire_nl01iO_dataout; wire wire_nl01l_dataout; wire wire_nl01li_dataout; wire wire_nl01ll_dataout; wire wire_nl01lO_dataout; wire wire_nl01Oi_dataout; wire wire_nl01Ol_dataout; wire wire_nl01OO_dataout; wire wire_nl0i_dataout; wire wire_nl0i0i_dataout; wire wire_nl0i0l_dataout; wire wire_nl0i0O_dataout; wire wire_nl0i1i_dataout; wire wire_nl0i1l_dataout; wire wire_nl0i1O_dataout; wire wire_nl0iii_dataout; wire wire_nl0iil_dataout; wire wire_nl0l_dataout; wire wire_nl0l0i_dataout; wire wire_nl0l0l_dataout; wire wire_nl0l0O_dataout; wire wire_nl0l1O_dataout; wire wire_nl0lii_dataout; wire wire_nl0lil_dataout; wire wire_nl0liO_dataout; wire wire_nl0lli_dataout; wire wire_nl0lll_dataout; wire wire_nl0llO_dataout; wire wire_nl0lOi_dataout; wire wire_nl0lOl_dataout; wire wire_nl0lOO_dataout; wire wire_nl0O_dataout; wire wire_nl0O0i_dataout; wire wire_nl0O0l_dataout; wire wire_nl0O0O_dataout; wire wire_nl0O1i_dataout; wire wire_nl0O1l_dataout; wire wire_nl0O1O_dataout; wire wire_nl0Oi_dataout; wire wire_nl0Oii_dataout; wire wire_nl0Oil_dataout; wire wire_nl0OiO_dataout; wire wire_nl0Ol_dataout; wire wire_nl0Oli_dataout; wire wire_nl0Oll_dataout; wire wire_nl0OlO_dataout; wire wire_nl0OO_dataout; wire wire_nl0OOi_dataout; wire wire_nl0OOl_dataout; wire wire_nl0OOO_dataout; wire wire_nl100i_dataout; wire wire_nl100l_dataout; wire wire_nl100O_dataout; wire wire_nl101i_dataout; wire wire_nl101l_dataout; wire wire_nl101O_dataout; wire wire_nl10i_dataout; wire wire_nl10ii_dataout; wire wire_nl10il_dataout; wire wire_nl10iO_dataout; wire wire_nl10l_dataout; wire wire_nl10li_dataout; wire wire_nl10ll_dataout; wire wire_nl10lO_dataout; wire wire_nl10O_dataout; wire wire_nl10Oi_dataout; wire wire_nl10Ol_dataout; wire wire_nl10OO_dataout; wire wire_nl110i_dataout; wire wire_nl110l_dataout; wire wire_nl110O_dataout; wire wire_nl111i_dataout; wire wire_nl111l_dataout; wire wire_nl111O_dataout; wire wire_nl11i_dataout; wire wire_nl11ii_dataout; wire wire_nl11il_dataout; wire wire_nl11iO_dataout; wire wire_nl11l_dataout; wire wire_nl11li_dataout; wire wire_nl11ll_dataout; wire wire_nl11lO_dataout; wire wire_nl11O_dataout; wire wire_nl11Oi_dataout; wire wire_nl11Ol_dataout; wire wire_nl11OO_dataout; wire wire_nl1i_dataout; wire wire_nl1i0i_dataout; wire wire_nl1i0l_dataout; wire wire_nl1i0O_dataout; wire wire_nl1i1i_dataout; wire wire_nl1i1l_dataout; wire wire_nl1i1O_dataout; wire wire_nl1iii_dataout; wire wire_nl1iil_dataout; wire wire_nl1iiO_dataout; wire wire_nl1ili_dataout; wire wire_nl1ill_dataout; wire wire_nl1ilO_dataout; wire wire_nl1iO_dataout; wire wire_nl1iOi_dataout; wire wire_nl1iOl_dataout; wire wire_nl1iOO_dataout; wire wire_nl1l_dataout; wire wire_nl1l0i_dataout; wire wire_nl1l0l_dataout; wire wire_nl1l1i_dataout; wire wire_nl1l1l_dataout; wire wire_nl1l1O_dataout; wire wire_nl1li_dataout; wire wire_nl1ll_dataout; wire wire_nl1lO_dataout; wire wire_nl1lOO_dataout; wire wire_nl1O_dataout; wire wire_nl1O0i_dataout; wire wire_nl1O0l_dataout; wire wire_nl1O0O_dataout; wire wire_nl1O1i_dataout; wire wire_nl1O1l_dataout; wire wire_nl1O1O_dataout; wire wire_nl1Oi_dataout; wire wire_nl1Oii_dataout; wire wire_nl1Oil_dataout; wire wire_nl1OiO_dataout; wire wire_nl1Ol_dataout; wire wire_nl1Oli_dataout; wire wire_nl1Oll_dataout; wire wire_nl1OlO_dataout; wire wire_nl1OO_dataout; wire wire_nl1OOi_dataout; wire wire_nl1OOl_dataout; wire wire_nl1OOO_dataout; wire wire_nli_dataout; wire wire_nli00i_dataout; wire wire_nli00l_dataout; wire wire_nli00O_dataout; wire wire_nli01i_dataout; wire wire_nli01l_dataout; wire wire_nli01O_dataout; wire wire_nli0i_dataout; wire wire_nli0ii_dataout; wire wire_nli0il_dataout; wire wire_nli0iO_dataout; wire wire_nli0l_dataout; wire wire_nli0li_dataout; wire wire_nli0ll_dataout; wire wire_nli0lO_dataout; wire wire_nli0O_dataout; wire wire_nli0Oi_dataout; wire wire_nli0Ol_dataout; wire wire_nli0OO_dataout; wire wire_nli10i_dataout; wire wire_nli10l_dataout; wire wire_nli10O_dataout; wire wire_nli11i_dataout; wire wire_nli11l_dataout; wire wire_nli11O_dataout; wire wire_nli1i_dataout; wire wire_nli1ii_dataout; wire wire_nli1il_dataout; wire wire_nli1iO_dataout; wire wire_nli1l_dataout; wire wire_nli1li_dataout; wire wire_nli1ll_dataout; wire wire_nli1lO_dataout; wire wire_nli1O_dataout; wire wire_nli1Oi_dataout; wire wire_nli1Ol_dataout; wire wire_nli1OO_dataout; wire wire_nlii_dataout; wire wire_nlii0i_dataout; wire wire_nlii0l_dataout; wire wire_nlii0O_dataout; wire wire_nlii1i_dataout; wire wire_nlii1l_dataout; wire wire_nlii1O_dataout; wire wire_nliii_dataout; wire wire_nliiii_dataout; wire wire_nliiil_dataout; wire wire_nliiiO_dataout; wire wire_nliil_dataout; wire wire_nliili_dataout; wire wire_nliill_dataout; wire wire_nliilO_dataout; wire wire_nliiO_dataout; wire wire_nliiOi_dataout; wire wire_nliiOl_dataout; wire wire_nliiOO_dataout; wire wire_nlil_dataout; wire wire_nlil0i_dataout; wire wire_nlil0l_dataout; wire wire_nlil0O_dataout; wire wire_nlil1i_dataout; wire wire_nlil1l_dataout; wire wire_nlil1O_dataout; wire wire_nlili_dataout; wire wire_nlilii_dataout; wire wire_nlilil_dataout; wire wire_nliliO_dataout; wire wire_nlill_dataout; wire wire_nlilli_dataout; wire wire_nlilll_dataout; wire wire_nlillO_dataout; wire wire_nlilO_dataout; wire wire_nlilOi_dataout; wire wire_nlilOl_dataout; wire wire_nlilOO_dataout; wire wire_nliO_dataout; wire wire_nliO0i_dataout; wire wire_nliO0l_dataout; wire wire_nliO0O_dataout; wire wire_nliO1i_dataout; wire wire_nliO1l_dataout; wire wire_nliO1O_dataout; wire wire_nliOi_dataout; wire wire_nliOii_dataout; wire wire_nliOil_dataout; wire wire_nliOiO_dataout; wire wire_nliOl_dataout; wire wire_nliOli_dataout; wire wire_nliOll_dataout; wire wire_nliOO_dataout; wire wire_nll_dataout; wire wire_nll00i_dataout; wire wire_nll00l_dataout; wire wire_nll00O_dataout; wire wire_nll01i_dataout; wire wire_nll01l_dataout; wire wire_nll01O_dataout; wire wire_nll0i_dataout; wire wire_nll0ii_dataout; wire wire_nll0il_dataout; wire wire_nll0iO_dataout; wire wire_nll0l_dataout; wire wire_nll0li_dataout; wire wire_nll0ll_dataout; wire wire_nll0lO_dataout; wire wire_nll0O_dataout; wire wire_nll0Oi_dataout; wire wire_nll0Ol_dataout; wire wire_nll0OO_dataout; wire wire_nll10O_dataout; wire wire_nll1i_dataout; wire wire_nll1ii_dataout; wire wire_nll1il_dataout; wire wire_nll1iO_dataout; wire wire_nll1l_dataout; wire wire_nll1li_dataout; wire wire_nll1ll_dataout; wire wire_nll1lO_dataout; wire wire_nll1O_dataout; wire wire_nll1Oi_dataout; wire wire_nll1Ol_dataout; wire wire_nll1OO_dataout; wire wire_nlli_dataout; wire wire_nlli0i_dataout; wire wire_nlli0l_dataout; wire wire_nlli0O_dataout; wire wire_nlli1i_dataout; wire wire_nlli1l_dataout; wire wire_nlli1O_dataout; wire wire_nllii_dataout; wire wire_nlliii_dataout; wire wire_nlliil_dataout; wire wire_nlliiO_dataout; wire wire_nllil_dataout; wire wire_nllili_dataout; wire wire_nllill_dataout; wire wire_nllilO_dataout; wire wire_nlliO_dataout; wire wire_nlliOi_dataout; wire wire_nlliOl_dataout; wire wire_nlliOO_dataout; wire wire_nlll_dataout; wire wire_nlll0i_dataout; wire wire_nlll0l_dataout; wire wire_nlll0O_dataout; wire wire_nlll1i_dataout; wire wire_nlll1l_dataout; wire wire_nlll1O_dataout; wire wire_nlllii_dataout; wire wire_nlllil_dataout; wire wire_nllliO_dataout; wire wire_nlllli_dataout; wire wire_nlllll_dataout; wire wire_nllllO_dataout; wire wire_nlllOi_dataout; wire wire_nlllOl_dataout; wire wire_nllO_dataout; wire wire_nllOiO_dataout; wire wire_nllOli_dataout; wire wire_nllOll_dataout; wire wire_nllOlO_dataout; wire wire_nllOOi_dataout; wire wire_nllOOl_dataout; wire wire_nllOOO_dataout; wire wire_nlO_dataout; wire wire_nlO00i_dataout; wire wire_nlO00l_dataout; wire wire_nlO00O_dataout; wire wire_nlO01i_dataout; wire wire_nlO01l_dataout; wire wire_nlO01O_dataout; wire wire_nlO0ii_dataout; wire wire_nlO0il_dataout; wire wire_nlO0iO_dataout; wire wire_nlO0li_dataout; wire wire_nlO0ll_dataout; wire wire_nlO0lO_dataout; wire wire_nlO0Oi_dataout; wire wire_nlO0Ol_dataout; wire wire_nlO0OO_dataout; wire wire_nlO10i_dataout; wire wire_nlO10l_dataout; wire wire_nlO10O_dataout; wire wire_nlO11i_dataout; wire wire_nlO11l_dataout; wire wire_nlO11O_dataout; wire wire_nlO1i_dataout; wire wire_nlO1ii_dataout; wire wire_nlO1il_dataout; wire wire_nlO1iO_dataout; wire wire_nlO1l_dataout; wire wire_nlO1li_dataout; wire wire_nlO1ll_dataout; wire wire_nlO1lO_dataout; wire wire_nlO1Oi_dataout; wire wire_nlO1Ol_dataout; wire wire_nlO1OO_dataout; wire wire_nlOi_dataout; wire wire_nlOi0i_dataout; wire wire_nlOi0l_dataout; wire wire_nlOi0O_dataout; wire wire_nlOi1i_dataout; wire wire_nlOi1l_dataout; wire wire_nlOi1O_dataout; wire wire_nlOiii_dataout; wire wire_nlOiil_dataout; wire wire_nlOiiO_dataout; wire wire_nlOili_dataout; wire wire_nlOill_dataout; wire wire_nlOilO_dataout; wire wire_nlOiOi_dataout; wire wire_nlOiOl_dataout; wire wire_nlOiOO_dataout; wire wire_nlOl_dataout; wire wire_nlOl0i_dataout; wire wire_nlOl0l_dataout; wire wire_nlOl0O_dataout; wire wire_nlOl1i_dataout; wire wire_nlOl1l_dataout; wire wire_nlOl1O_dataout; wire wire_nlOlii_dataout; wire wire_nlOlil_dataout; wire wire_nlOliO_dataout; wire wire_nlOlli_dataout; wire wire_nlOlll_dataout; wire wire_nlOlOl_dataout; wire wire_nlOlOO_dataout; wire wire_nlOO_dataout; wire wire_nlOO0i_dataout; wire wire_nlOO0l_dataout; wire wire_nlOO0O_dataout; wire wire_nlOO1i_dataout; wire wire_nlOO1l_dataout; wire wire_nlOO1O_dataout; wire wire_nlOOi_dataout; wire wire_nlOOii_dataout; wire wire_nlOOil_dataout; wire wire_nlOOiO_dataout; wire wire_nlOOl_dataout; wire wire_nlOOli_dataout; wire wire_nlOOll_dataout; wire wire_nlOOlO_dataout; wire wire_nlOOOi_dataout; wire wire_nlOOOl_dataout; wire wire_nlOOOO_dataout; wire wire_nO_dataout; wire wire_nllOi_o; wire wire_nllOl_o; wire wire_nllOO_o; wire n0Oill; wire n0OilO; wire n0OiOi; wire n0OiOl; wire n0OiOO; wire n0Ol0i; wire n0Ol0l; wire n0Ol0O; wire n0Ol1i; wire n0Ol1l; wire n0Ol1O; wire n0Olii; wire n0Olil; wire n0OliO; wire n0OllO; wire n0OlOi; wire n0OO0i; wire n0OO1i; wire n0OOii; wire n0OOll; wire ni100i; wire ni101l; wire ni101O; wire ni10ii; wire ni10il; wire ni10iO; wire ni10li; wire ni10ll; wire ni10lO; wire ni10Oi; wire ni10Ol; wire ni110i; wire ni111i; wire ni111O; wire ni11iO; wire ni11li; wire ni11ll; wire ni11lO; wire ni1i0i; wire ni1i0l; wire ni1i1l; wire ni1i1O; wire ni1iil; wire ni1iiO; wire ni1iOl; wire ni1iOO; wire ni1l0l; wire ni1l0O; wire ni1l1i; wire ni1l1l; wire ni1lii; initial n0Olli45 = 0; always @ ( posedge clk_2) n0Olli45 <= n0Olli46; event n0Olli45_event; initial #1 ->n0Olli45_event; always @(n0Olli45_event) n0Olli45 <= {1{1'b1}}; initial n0Olli46 = 0; always @ ( posedge clk_2) n0Olli46 <= n0Olli45; initial n0OlOl43 = 0; always @ ( posedge clk_2) n0OlOl43 <= n0OlOl44; event n0OlOl43_event; initial #1 ->n0OlOl43_event; always @(n0OlOl43_event) n0OlOl43 <= {1{1'b1}}; initial n0OlOl44 = 0; always @ ( posedge clk_2) n0OlOl44 <= n0OlOl43; initial n0OO0l39 = 0; always @ ( posedge clk_2) n0OO0l39 <= n0OO0l40; event n0OO0l39_event; initial #1 ->n0OO0l39_event; always @(n0OO0l39_event) n0OO0l39 <= {1{1'b1}}; initial n0OO0l40 = 0; always @ ( posedge clk_2) n0OO0l40 <= n0OO0l39; initial n0OO1l41 = 0; always @ ( posedge clk_2) n0OO1l41 <= n0OO1l42; event n0OO1l41_event; initial #1 ->n0OO1l41_event; always @(n0OO1l41_event) n0OO1l41 <= {1{1'b1}}; initial n0OO1l42 = 0; always @ ( posedge clk_2) n0OO1l42 <= n0OO1l41; initial n0OOil37 = 0; always @ ( posedge clk_2) n0OOil37 <= n0OOil38; event n0OOil37_event; initial #1 ->n0OOil37_event; always @(n0OOil37_event) n0OOil37 <= {1{1'b1}}; initial n0OOil38 = 0; always @ ( posedge clk_2) n0OOil38 <= n0OOil37; initial n0OOiO35 = 0; always @ ( posedge clk_2) n0OOiO35 <= n0OOiO36; event n0OOiO35_event; initial #1 ->n0OOiO35_event; always @(n0OOiO35_event) n0OOiO35 <= {1{1'b1}}; initial n0OOiO36 = 0; always @ ( posedge clk_2) n0OOiO36 <= n0OOiO35; initial n0OOli33 = 0; always @ ( posedge clk_2) n0OOli33 <= n0OOli34; event n0OOli33_event; initial #1 ->n0OOli33_event; always @(n0OOli33_event) n0OOli33 <= {1{1'b1}}; initial n0OOli34 = 0; always @ ( posedge clk_2) n0OOli34 <= n0OOli33; initial n0OOlO31 = 0; always @ ( posedge clk_2) n0OOlO31 <= n0OOlO32; event n0OOlO31_event; initial #1 ->n0OOlO31_event; always @(n0OOlO31_event) n0OOlO31 <= {1{1'b1}}; initial n0OOlO32 = 0; always @ ( posedge clk_2) n0OOlO32 <= n0OOlO31; initial n0OOOl29 = 0; always @ ( posedge clk_2) n0OOOl29 <= n0OOOl30; event n0OOOl29_event; initial #1 ->n0OOOl29_event; always @(n0OOOl29_event) n0OOOl29 <= {1{1'b1}}; initial n0OOOl30 = 0; always @ ( posedge clk_2) n0OOOl30 <= n0OOOl29; initial n0OOOO27 = 0; always @ ( posedge clk_2) n0OOOO27 <= n0OOOO28; event n0OOOO27_event; initial #1 ->n0OOOO27_event; always @(n0OOOO27_event) n0OOOO27 <= {1{1'b1}}; initial n0OOOO28 = 0; always @ ( posedge clk_2) n0OOOO28 <= n0OOOO27; initial ni100l15 = 0; always @ ( posedge clk_2) ni100l15 <= ni100l16; event ni100l15_event; initial #1 ->ni100l15_event; always @(ni100l15_event) ni100l15 <= {1{1'b1}}; initial ni100l16 = 0; always @ ( posedge clk_2) ni100l16 <= ni100l15; initial ni10OO13 = 0; always @ ( posedge clk_2) ni10OO13 <= ni10OO14; event ni10OO13_event; initial #1 ->ni10OO13_event; always @(ni10OO13_event) ni10OO13 <= {1{1'b1}}; initial ni10OO14 = 0; always @ ( posedge clk_2) ni10OO14 <= ni10OO13; initial ni110l23 = 0; always @ ( posedge clk_2) ni110l23 <= ni110l24; event ni110l23_event; initial #1 ->ni110l23_event; always @(ni110l23_event) ni110l23 <= {1{1'b1}}; initial ni110l24 = 0; always @ ( posedge clk_2) ni110l24 <= ni110l23; initial ni111l25 = 0; always @ ( posedge clk_2) ni111l25 <= ni111l26; event ni111l25_event; initial #1 ->ni111l25_event; always @(ni111l25_event) ni111l25 <= {1{1'b1}}; initial ni111l26 = 0; always @ ( posedge clk_2) ni111l26 <= ni111l25; initial ni11ii21 = 0; always @ ( posedge clk_2) ni11ii21 <= ni11ii22; event ni11ii21_event; initial #1 ->ni11ii21_event; always @(ni11ii21_event) ni11ii21 <= {1{1'b1}}; initial ni11ii22 = 0; always @ ( posedge clk_2) ni11ii22 <= ni11ii21; initial ni11Oi19 = 0; always @ ( posedge clk_2) ni11Oi19 <= ni11Oi20; event ni11Oi19_event; initial #1 ->ni11Oi19_event; always @(ni11Oi19_event) ni11Oi19 <= {1{1'b1}}; initial ni11Oi20 = 0; always @ ( posedge clk_2) ni11Oi20 <= ni11Oi19; initial ni11OO17 = 0; always @ ( posedge clk_2) ni11OO17 <= ni11OO18; event ni11OO17_event; initial #1 ->ni11OO17_event; always @(ni11OO17_event) ni11OO17 <= {1{1'b1}}; initial ni11OO18 = 0; always @ ( posedge clk_2) ni11OO18 <= ni11OO17; initial ni1i0O11 = 0; always @ ( posedge clk_2) ni1i0O11 <= ni1i0O12; event ni1i0O11_event; initial #1 ->ni1i0O11_event; always @(ni1i0O11_event) ni1i0O11 <= {1{1'b1}}; initial ni1i0O12 = 0; always @ ( posedge clk_2) ni1i0O12 <= ni1i0O11; initial ni1ili10 = 0; always @ ( posedge clk_2) ni1ili10 <= ni1ili9; initial ni1ili9 = 0; always @ ( posedge clk_2) ni1ili9 <= ni1ili10; event ni1ili9_event; initial #1 ->ni1ili9_event; always @(ni1ili9_event) ni1ili9 <= {1{1'b1}}; initial ni1ilO7 = 0; always @ ( posedge clk_2) ni1ilO7 <= ni1ilO8; event ni1ilO7_event; initial #1 ->ni1ilO7_event; always @(ni1ilO7_event) ni1ilO7 <= {1{1'b1}}; initial ni1ilO8 = 0; always @ ( posedge clk_2) ni1ilO8 <= ni1ilO7; initial ni1l1O5 = 0; always @ ( posedge clk_2) ni1l1O5 <= ni1l1O6; event ni1l1O5_event; initial #1 ->ni1l1O5_event; always @(ni1l1O5_event) ni1l1O5 <= {1{1'b1}}; initial ni1l1O6 = 0; always @ ( posedge clk_2) ni1l1O6 <= ni1l1O5; initial ni1lil3 = 0; always @ ( posedge clk_2) ni1lil3 <= ni1lil4; event ni1lil3_event; initial #1 ->ni1lil3_event; always @(ni1lil3_event) ni1lil3 <= {1{1'b1}}; initial ni1lil4 = 0; always @ ( posedge clk_2) ni1lil4 <= ni1lil3; initial ni1lli1 = 0; always @ ( posedge clk_2) ni1lli1 <= ni1lli2; event ni1lli1_event; initial #1 ->ni1lli1_event; always @(ni1lli1_event) ni1lli1 <= {1{1'b1}}; initial ni1lli2 = 0; always @ ( posedge clk_2) ni1lli2 <= ni1lli1; initial begin n000i = 0; n001O = 0; n00ii = 0; n01Ol = 0; n0liO = 0; n0lli = 0; n0lll = 0; n0llO = 0; n0lOi = 0; n0lOl = 0; n0lOO = 0; n0O1i = 0; n0O1l = 0; n10il = 0; n10iO = 0; n10li = 0; n10ll = 0; n10lO = 0; n10Oi = 0; n10Ol = 0; n10OO = 0; n11l = 0; n1i1i = 0; nii00i = 0; nii00l = 0; nii00O = 0; nii0ii = 0; nii0il = 0; nii0lO = 0; nii0Oi = 0; niiii = 0; niiil = 0; niiiO = 0; niili = 0; niill = 0; niilO = 0; niiOi = 0; niiOl = 0; nill0i = 0; nill1l = 0; nill1O = 0; nillil = 0; nilliO = 0; nillll = 0; niO00i = 0; niO00l = 0; niO00O = 0; niO01O = 0; niO0ii = 0; niO0il = 0; niO0iO = 0; niO0li = 0; niO0ll = 0; nl00i = 0; nl00l = 0; nl00O = 0; nl0ii = 0; nl0iiO = 0; nl0il = 0; nl0ili = 0; nl0ill = 0; nl0ilO = 0; nl0iO = 0; nl0iOi = 0; nl0iOl = 0; nl0iOO = 0; nl0l1i = 0; nl0l1l = 0; nl0li = 0; nl0ll = 0; nl0lO = 0; nl1l0O = 0; nl1lii = 0; nl1lil = 0; nl1liO = 0; nl1lli = 0; nl1lll = 0; nl1llO = 0; nl1lOi = 0; nl1lOl = 0; nliOlO = 0; nliOOi = 0; nliOOl = 0; nliOOO = 0; nll10i = 0; nll11i = 0; nll11l = 0; nll11O = 0; nlllOO = 0; nllO0i = 0; nllO0l = 0; nllO0O = 0; nllO1i = 0; nllO1l = 0; nllO1O = 0; nllOii = 0; nlO0i = 0; nlO0l = 0; nlO0O = 0; nlOii = 0; nlOil = 0; nlOiO = 0; nlOli = 0; nlOll = 0; nlOlO = 0; end always @ (clk_2 or wire_n11i_PRN or wire_n11i_CLRN) begin if (wire_n11i_PRN == 1'b0) begin n000i <= 1; n001O <= 1; n00ii <= 1; n01Ol <= 1; n0liO <= 1; n0lli <= 1; n0lll <= 1; n0llO <= 1; n0lOi <= 1; n0lOl <= 1; n0lOO <= 1; n0O1i <= 1; n0O1l <= 1; n10il <= 1; n10iO <= 1; n10li <= 1; n10ll <= 1; n10lO <= 1; n10Oi <= 1; n10Ol <= 1; n10OO <= 1; n11l <= 1; n1i1i <= 1; nii00i <= 1; nii00l <= 1; nii00O <= 1; nii0ii <= 1; nii0il <= 1; nii0lO <= 1; nii0Oi <= 1; niiii <= 1; niiil <= 1; niiiO <= 1; niili <= 1; niill <= 1; niilO <= 1; niiOi <= 1; niiOl <= 1; nill0i <= 1; nill1l <= 1; nill1O <= 1; nillil <= 1; nilliO <= 1; nillll <= 1; niO00i <= 1; niO00l <= 1; niO00O <= 1; niO01O <= 1; niO0ii <= 1; niO0il <= 1; niO0iO <= 1; niO0li <= 1; niO0ll <= 1; nl00i <= 1; nl00l <= 1; nl00O <= 1; nl0ii <= 1; nl0iiO <= 1; nl0il <= 1; nl0ili <= 1; nl0ill <= 1; nl0ilO <= 1; nl0iO <= 1; nl0iOi <= 1; nl0iOl <= 1; nl0iOO <= 1; nl0l1i <= 1; nl0l1l <= 1; nl0li <= 1; nl0ll <= 1; nl0lO <= 1; nl1l0O <= 1; nl1lii <= 1; nl1lil <= 1; nl1liO <= 1; nl1lli <= 1; nl1lll <= 1; nl1llO <= 1; nl1lOi <= 1; nl1lOl <= 1; nliOlO <= 1; nliOOi <= 1; nliOOl <= 1; nliOOO <= 1; nll10i <= 1; nll11i <= 1; nll11l <= 1; nll11O <= 1; nlllOO <= 1; nllO0i <= 1; nllO0l <= 1; nllO0O <= 1; nllO1i <= 1; nllO1l <= 1; nllO1O <= 1; nllOii <= 1; nlO0i <= 1; nlO0l <= 1; nlO0O <= 1; nlOii <= 1; nlOil <= 1; nlOiO <= 1; nlOli <= 1; nlOll <= 1; nlOlO <= 1; end else if (wire_n11i_CLRN == 1'b0) begin n000i <= 0; n001O <= 0; n00ii <= 0; n01Ol <= 0; n0liO <= 0; n0lli <= 0; n0lll <= 0; n0llO <= 0; n0lOi <= 0; n0lOl <= 0; n0lOO <= 0; n0O1i <= 0; n0O1l <= 0; n10il <= 0; n10iO <= 0; n10li <= 0; n10ll <= 0; n10lO <= 0; n10Oi <= 0; n10Ol <= 0; n10OO <= 0; n11l <= 0; n1i1i <= 0; nii00i <= 0; nii00l <= 0; nii00O <= 0; nii0ii <= 0; nii0il <= 0; nii0lO <= 0; nii0Oi <= 0; niiii <= 0; niiil <= 0; niiiO <= 0; niili <= 0; niill <= 0; niilO <= 0; niiOi <= 0; niiOl <= 0; nill0i <= 0; nill1l <= 0; nill1O <= 0; nillil <= 0; nilliO <= 0; nillll <= 0; niO00i <= 0; niO00l <= 0; niO00O <= 0; niO01O <= 0; niO0ii <= 0; niO0il <= 0; niO0iO <= 0; niO0li <= 0; niO0ll <= 0; nl00i <= 0; nl00l <= 0; nl00O <= 0; nl0ii <= 0; nl0iiO <= 0; nl0il <= 0; nl0ili <= 0; nl0ill <= 0; nl0ilO <= 0; nl0iO <= 0; nl0iOi <= 0; nl0iOl <= 0; nl0iOO <= 0; nl0l1i <= 0; nl0l1l <= 0; nl0li <= 0; nl0ll <= 0; nl0lO <= 0; nl1l0O <= 0; nl1lii <= 0; nl1lil <= 0; nl1liO <= 0; nl1lli <= 0; nl1lll <= 0; nl1llO <= 0; nl1lOi <= 0; nl1lOl <= 0; nliOlO <= 0; nliOOi <= 0; nliOOl <= 0; nliOOO <= 0; nll10i <= 0; nll11i <= 0; nll11l <= 0; nll11O <= 0; nlllOO <= 0; nllO0i <= 0; nllO0l <= 0; nllO0O <= 0; nllO1i <= 0; nllO1l <= 0; nllO1O <= 0; nllOii <= 0; nlO0i <= 0; nlO0l <= 0; nlO0O <= 0; nlOii <= 0; nlOil <= 0; nlOiO <= 0; nlOli <= 0; nlOll <= 0; nlOlO <= 0; end else if (clk_2 != n11i_clk_prev && clk_2 == 1'b1) begin n000i <= wire_n00Ol_dataout; n001O <= wire_n00Oi_dataout; n00ii <= wire_n0O1O_dataout; n01Ol <= wire_n00iO_dataout; n0liO <= wire_n0O0i_dataout; n0lli <= wire_n0O0l_dataout; n0lll <= wire_n0O0O_dataout; n0llO <= wire_n0Oii_dataout; n0lOi <= wire_n0Oil_dataout; n0lOl <= wire_n0OiO_dataout; n0lOO <= wire_n0Oli_dataout; n0O1i <= wire_n0Oll_dataout; n0O1l <= wire_nil1i_dataout; n10il <= wire_n1i1O_dataout; n10iO <= wire_n1i0i_dataout; n10li <= wire_n1i0l_dataout; n10ll <= wire_n1i0O_dataout; n10lO <= wire_n1iii_dataout; n10Oi <= wire_n1iil_dataout; n10Ol <= wire_n1iiO_dataout; n10OO <= wire_n1ili_dataout; n11l <= rx_local_fault_clr; n1i1i <= wire_n00il_dataout; nii00i <= ni1iiO; nii00l <= ni1iOO; nii00O <= ((~ wire_ni0O_dataout) & (dec_ctl[3] & n0Oill)); nii0ii <= wire_niii1l_dataout; nii0il <= wire_niii1O_dataout; nii0lO <= wire_niiiii_dataout; nii0Oi <= wire_niiiil_dataout; niiii <= wire_nil1l_dataout; niiil <= wire_nil1O_dataout; niiiO <= wire_nil0i_dataout; niili <= wire_nil0l_dataout; niill <= wire_nil0O_dataout; niilO <= wire_nilii_dataout; niiOi <= wire_nilil_dataout; niiOl <= wire_niliO_dataout; nill0i <= wire_nillOl_dataout; nill1l <= ni1l1l; nill1O <= wire_nillOi_dataout; nillil <= wire_nilO1O_dataout; nilliO <= wire_nilO0i_dataout; nillll <= wire_niO0lO_dataout; niO00i <= wire_niO0Ol_dataout; niO00l <= wire_niO0OO_dataout; niO00O <= wire_niOi1i_dataout; niO01O <= wire_niO0Oi_dataout; niO0ii <= wire_niOi1l_dataout; niO0il <= wire_niOi1O_dataout; niO0iO <= wire_niOi0i_dataout; niO0li <= wire_niOi0l_dataout; niO0ll <= wire_nl1lOO_dataout; nl00i <= wire_nl0Ol_dataout; nl00l <= wire_nl0OO_dataout; nl00O <= wire_nli1i_dataout; nl0ii <= wire_nli1l_dataout; nl0iiO <= wire_nl0l0i_dataout; nl0il <= wire_nli1O_dataout; nl0ili <= wire_nl0l0l_dataout; nl0ill <= wire_nl0l0O_dataout; nl0ilO <= wire_nl0lii_dataout; nl0iO <= wire_nli0i_dataout; nl0iOi <= wire_nl0lil_dataout; nl0iOl <= wire_nl0liO_dataout; nl0iOO <= wire_nl0lli_dataout; nl0l1i <= wire_nl0lll_dataout; nl0l1l <= wire_nll10O_dataout; nl0li <= wire_nli0l_dataout; nl0ll <= wire_nli0O_dataout; nl0lO <= nlO0i; nl1l0O <= wire_nl1O1i_dataout; nl1lii <= wire_nl1O1l_dataout; nl1lil <= wire_nl1O1O_dataout; nl1liO <= wire_nl1O0i_dataout; nl1lli <= wire_nl1O0l_dataout; nl1lll <= wire_nl1O0O_dataout; nl1llO <= wire_nl1Oii_dataout; nl1lOi <= wire_nl1Oil_dataout; nl1lOl <= wire_nl0l1O_dataout; nliOlO <= wire_nll1ii_dataout; nliOOi <= wire_nll1il_dataout; nliOOl <= wire_nll1iO_dataout; nliOOO <= wire_nll1li_dataout; nll10i <= wire_nll1Ol_dataout; nll11i <= wire_nll1ll_dataout; nll11l <= wire_nll1lO_dataout; nll11O <= wire_nll1Oi_dataout; nlllOO <= wire_nllOli_dataout; nllO0i <= wire_nllOOl_dataout; nllO0l <= wire_nllOOO_dataout; nllO0O <= wire_nlO11i_dataout; nllO1i <= wire_nllOll_dataout; nllO1l <= wire_nllOlO_dataout; nllO1O <= wire_nllOOi_dataout; nllOii <= wire_nlO11l_dataout; nlO0i <= indv; nlO0l <= (~ wire_nllOO_o); nlO0O <= wire_nllOi_o; nlOii <= nlOil; nlOil <= tx_local_fault_det; nlOiO <= nlOli; nlOli <= xs_link_status_set; nlOll <= wire_nlOOi_dataout; nlOlO <= n11l; end n11i_clk_prev <= clk_2; end assign wire_n11i_CLRN = ((n0OOOO28 ^ n0OOOO27) & (~ soft_reset)), wire_n11i_PRN = (n0OOOl30 ^ n0OOOl29); initial begin n000l = 0; n000O = 0; n001i = 0; n001l = 0; n01OO = 0; n10i = 0; nii0iO = 0; nii0li = 0; nii0ll = 0; nii0Ol = 0; nii0OO = 0; niii1i = 0; niiOO = 0; nill0l = 0; nill0O = 0; nillii = 0; nillli = 0; nll10l = 0; nllOil = 0; end always @ (clk_2 or soft_reset or wire_n11O_CLRN) begin if (soft_reset == 1'b1) begin n000l <= 1; n000O <= 1; n001i <= 1; n001l <= 1; n01OO <= 1; n10i <= 1; nii0iO <= 1; nii0li <= 1; nii0ll <= 1; nii0Ol <= 1; nii0OO <= 1; niii1i <= 1; niiOO <= 1; nill0l <= 1; nill0O <= 1; nillii <= 1; nillli <= 1; nll10l <= 1; nllOil <= 1; end else if (wire_n11O_CLRN == 1'b0) begin n000l <= 0; n000O <= 0; n001i <= 0; n001l <= 0; n01OO <= 0; n10i <= 0; nii0iO <= 0; nii0li <= 0; nii0ll <= 0; nii0Ol <= 0; nii0OO <= 0; niii1i <= 0; niiOO <= 0; nill0l <= 0; nill0O <= 0; nillii <= 0; nillli <= 0; nll10l <= 0; nllOil <= 0; end else if (clk_2 != n11O_clk_prev && clk_2 == 1'b1) begin n000l <= wire_n00OO_dataout; n000O <= wire_n0i1i_dataout; n001i <= wire_n00ll_dataout; n001l <= wire_n00lO_dataout; n01OO <= wire_n00li_dataout; n10i <= wire_n10l_dataout; nii0iO <= wire_niii0i_dataout; nii0li <= wire_niii0l_dataout; nii0ll <= wire_niii0O_dataout; nii0Ol <= wire_niiiiO_dataout; nii0OO <= wire_niiili_dataout; niii1i <= wire_nilllO_dataout; niiOO <= wire_nl0Oi_dataout; nill0l <= wire_nillOO_dataout; nill0O <= wire_nilO1i_dataout; nillii <= wire_nilO1l_dataout; nillli <= wire_nilO0l_dataout; nll10l <= wire_nllOiO_dataout; nllOil <= wire_n1i1l_dataout; end n11O_clk_prev <= clk_2; end assign wire_n11O_CLRN = (ni111l26 ^ ni111l25); event n000l_event; event n000O_event; event n001i_event; event n001l_event; event n01OO_event; event n10i_event; event nii0iO_event; event nii0li_event; event nii0ll_event; event nii0Ol_event; event nii0OO_event; event niii1i_event; event niiOO_event; event nill0l_event; event nill0O_event; event nillii_event; event nillli_event; event nll10l_event; event nllOil_event; initial #1 ->n000l_event; initial #1 ->n000O_event; initial #1 ->n001i_event; initial #1 ->n001l_event; initial #1 ->n01OO_event; initial #1 ->n10i_event; initial #1 ->nii0iO_event; initial #1 ->nii0li_event; initial #1 ->nii0ll_event; initial #1 ->nii0Ol_event; initial #1 ->nii0OO_event; initial #1 ->niii1i_event; initial #1 ->niiOO_event; initial #1 ->nill0l_event; initial #1 ->nill0O_event; initial #1 ->nillii_event; initial #1 ->nillli_event; initial #1 ->nll10l_event; initial #1 ->nllOil_event; always @(n000l_event) n000l <= 1; always @(n000O_event) n000O <= 1; always @(n001i_event) n001i <= 1; always @(n001l_event) n001l <= 1; always @(n01OO_event) n01OO <= 1; always @(n10i_event) n10i <= 1; always @(nii0iO_event) nii0iO <= 1; always @(nii0li_event) nii0li <= 1; always @(nii0ll_event) nii0ll <= 1; always @(nii0Ol_event) nii0Ol <= 1; always @(nii0OO_event) nii0OO <= 1; always @(niii1i_event) niii1i <= 1; always @(niiOO_event) niiOO <= 1; always @(nill0l_event) nill0l <= 1; always @(nill0O_event) nill0O <= 1; always @(nillii_event) nillii <= 1; always @(nillli_event) nillli <= 1; always @(nll10l_event) nll10l <= 1; always @(nllOil_event) nllOil <= 1; and(wire_n00il_dataout, wire_n0i1l_dataout, ~(ni1l0O)); and(wire_n00iO_dataout, wire_n0i1O_dataout, ~(ni1l0O)); or(wire_n00li_dataout, wire_n0i0i_dataout, ni1l0O); or(wire_n00ll_dataout, wire_n0i0l_dataout, ni1l0O); or(wire_n00lO_dataout, wire_n0i0O_dataout, ni1l0O); and(wire_n00Oi_dataout, wire_n0iii_dataout, ~(ni1l0O)); and(wire_n00Ol_dataout, wire_n0iil_dataout, ~(ni1l0O)); or(wire_n00OO_dataout, wire_n0iiO_dataout, ni1l0O); or(wire_n010i_dataout, wire_n1O1i_dataout, n0Ol1l); and(wire_n010l_dataout, wire_n1O1l_dataout, ~(n0Ol1l)); and(wire_n010O_dataout, wire_n1O1O_dataout, ~(n0Ol1l)); and(wire_n011i_dataout, wire_n01li_dataout, ~((~ ni111O))); or(wire_n011l_dataout, wire_n1lOl_dataout, n0Ol1l); or(wire_n011O_dataout, wire_n1lOO_dataout, n0Ol1l); and(wire_n01ii_dataout, wire_n1O0i_dataout, ~(n0Ol1l)); and(wire_n01il_dataout, wire_n1O0l_dataout, ~(n0Ol1l)); and(wire_n01iO_dataout, wire_n1O0O_dataout, ~(n0Ol1l)); or(wire_n01li_dataout, wire_n1Oii_dataout, n0Ol1l); assign wire_n0i_dataout = (rxaui_s2gx_en === 1'b1) ? nliOOO : nl0ilO; assign wire_n0i0i_dataout = (n0Ol0O === 1'b1) ? wire_n0iOi_dataout : wire_nl1i_dataout; assign wire_n0i0l_dataout = (n0Ol0O === 1'b1) ? wire_n0iOl_dataout : wire_nl1l_dataout; assign wire_n0i0O_dataout = (n0Ol0O === 1'b1) ? wire_n0iOO_dataout : wire_nl1O_dataout; or(wire_n0i1i_dataout, wire_n0ili_dataout, ni1l0O); assign wire_n0i1l_dataout = (n0Ol0O === 1'b1) ? wire_n0ill_dataout : wire_niOl_dataout; assign wire_n0i1O_dataout = (n0Ol0O === 1'b1) ? wire_n0ilO_dataout : wire_niOO_dataout; assign wire_n0iii_dataout = (n0Ol0O === 1'b1) ? wire_n0l1i_dataout : wire_nl0i_dataout; assign wire_n0iil_dataout = (n0Ol0O === 1'b1) ? wire_n0l1l_dataout : wire_nl0l_dataout; assign wire_n0iiO_dataout = (n0Ol0O === 1'b1) ? wire_n0l1O_dataout : wire_nl0O_dataout; assign wire_n0ili_dataout = (n0Ol0O === 1'b1) ? wire_n0l0i_dataout : wire_nili_dataout; and(wire_n0ill_dataout, wire_niOl_dataout, ~(n0Ol0l)); or(wire_n0ilO_dataout, wire_niOO_dataout, n0Ol0l); or(wire_n0iOi_dataout, wire_nl1i_dataout, n0Ol0l); or(wire_n0iOl_dataout, wire_nl1l_dataout, n0Ol0l); or(wire_n0iOO_dataout, wire_nl1O_dataout, n0Ol0l); assign wire_n0l_dataout = (rxaui_s2gx_en === 1'b1) ? nll11i : nl0iOi; or(wire_n0l0i_dataout, wire_nili_dataout, n0Ol0l); or(wire_n0l1i_dataout, wire_nl0i_dataout, n0Ol0l); or(wire_n0l1l_dataout, wire_nl0l_dataout, n0Ol0l); or(wire_n0l1O_dataout, wire_nl0O_dataout, n0Ol0l); assign wire_n0O_dataout = (rxaui_s2gx_en === 1'b1) ? nll11l : nl0iOl; and(wire_n0O0i_dataout, wire_n0OOi_dataout, ~(ni1l0O)); and(wire_n0O0l_dataout, wire_n0OOl_dataout, ~(ni1l0O)); and(wire_n0O0O_dataout, wire_n0OOO_dataout, ~(ni1l0O)); and(wire_n0O1O_dataout, wire_n0OlO_dataout, ~(ni1l0O)); and(wire_n0Oii_dataout, wire_ni11i_dataout, ~(ni1l0O)); and(wire_n0Oil_dataout, wire_ni11l_dataout, ~(ni1l0O)); and(wire_n0OiO_dataout, wire_ni11O_dataout, ~(ni1l0O)); and(wire_n0Oli_dataout, wire_ni10i_dataout, ~(ni1l0O)); and(wire_n0Oll_dataout, wire_ni10l_dataout, ~(ni1l0O)); assign wire_n0OlO_dataout = (ni1l1l === 1'b1) ? wire_ni0lO_dataout : wire_ni10O_dataout; assign wire_n0OOi_dataout = (ni1l1l === 1'b1) ? wire_ni0Oi_dataout : wire_ni1ii_dataout; assign wire_n0OOl_dataout = (ni1l1l === 1'b1) ? wire_ni0Ol_dataout : wire_ni1il_dataout; assign wire_n0OOO_dataout = (ni1l1l === 1'b1) ? wire_ni0OO_dataout : wire_ni1iO_dataout; or(wire_n100i_dataout, wire_nlOlli_dataout, n0OiOO); or(wire_n100l_dataout, wire_nlOlll_dataout, n0OiOO); or(wire_n101i_dataout, wire_nlOlii_dataout, n0OiOO); or(wire_n101l_dataout, wire_nlOlil_dataout, n0OiOO); or(wire_n101O_dataout, wire_nlOliO_dataout, n0OiOO); and(wire_n10l_dataout, wire_n10O_dataout, ~(nlOlO)); or(wire_n10O_dataout, n10i, ~(ni111O)); or(wire_n110i_dataout, wire_nlOill_dataout, n0OiOl); assign wire_n110l_dataout = (n0OiOl === 1'b1) ? n0OO1i : wire_nlOilO_dataout; assign wire_n110O_dataout = (n0OiOl === 1'b1) ? n0OO1i : wire_nlOiOi_dataout; assign wire_n111i_dataout = (ni1lii === 1'b1) ? wire_n100l_dataout : wire_n11li_dataout; assign wire_n111l_dataout = (n0OiOl === 1'b1) ? (~ n0OO1i) : wire_nlOiiO_dataout; or(wire_n111O_dataout, wire_nlOili_dataout, n0OiOl); assign wire_n11ii_dataout = (n0OiOl === 1'b1) ? n0OO1i : wire_nlOiOl_dataout; assign wire_n11il_dataout = (n0OiOl === 1'b1) ? n0OO1i : wire_nlOiOO_dataout; assign wire_n11iO_dataout = (n0OiOl === 1'b1) ? n0OO1i : wire_nlOl1i_dataout; or(wire_n11li_dataout, wire_nlOl1l_dataout, n0OiOl); and(wire_n11lO_dataout, wire_nlOl1O_dataout, ~(n0OiOO)); or(wire_n11Oi_dataout, wire_nlOl0i_dataout, n0OiOO); or(wire_n11Ol_dataout, wire_nlOl0l_dataout, n0OiOO); or(wire_n11OO_dataout, wire_nlOl0O_dataout, n0OiOO); assign wire_n1i_dataout = (rxaui_s2gx_en === 1'b1) ? nliOlO : nl0iiO; assign wire_n1i0i_dataout = (n0Ol1i === 1'b1) ? wire_n1Oli_dataout : wire_n1iOi_dataout; assign wire_n1i0l_dataout = (n0Ol1i === 1'b1) ? wire_n1Oll_dataout : wire_n1iOl_dataout; assign wire_n1i0O_dataout = (n0Ol1i === 1'b1) ? wire_n1OlO_dataout : wire_n1iOO_dataout; assign wire_n1i1l_dataout = (n0Ol1i === 1'b1) ? wire_n1Oil_dataout : wire_n1ill_dataout; assign wire_n1i1O_dataout = (n0Ol1i === 1'b1) ? wire_n1OiO_dataout : wire_n1ilO_dataout; assign wire_n1iii_dataout = (n0Ol1i === 1'b1) ? wire_n1OOi_dataout : wire_n1l1i_dataout; assign wire_n1iil_dataout = (n0Ol1i === 1'b1) ? wire_n1OOl_dataout : wire_n1l1l_dataout; assign wire_n1iiO_dataout = (n0Ol1i === 1'b1) ? wire_n1OOO_dataout : wire_n1l1O_dataout; assign wire_n1ili_dataout = (n0Ol1i === 1'b1) ? wire_n011i_dataout : wire_n1l0i_dataout; or(wire_n1ill_dataout, wire_n1l0l_dataout, (~ ni111O)); and(wire_n1ilO_dataout, wire_n1l0O_dataout, ~((~ ni111O))); and(wire_n1iOi_dataout, wire_n1lii_dataout, ~((~ ni111O))); and(wire_n1iOl_dataout, wire_n1lil_dataout, ~((~ ni111O))); and(wire_n1iOO_dataout, wire_n1liO_dataout, ~((~ ni111O))); assign wire_n1l_dataout = (rxaui_s2gx_en === 1'b1) ? nliOOi : nl0ili; and(wire_n1l0i_dataout, wire_n1lOi_dataout, ~((~ ni111O))); or(wire_n1l0l_dataout, wire_n1lOl_dataout, ni110i); or(wire_n1l0O_dataout, wire_n1lOO_dataout, ni110i); and(wire_n1l1i_dataout, wire_n1lli_dataout, ~((~ ni111O))); and(wire_n1l1l_dataout, wire_n1lll_dataout, ~((~ ni111O))); and(wire_n1l1O_dataout, wire_n1llO_dataout, ~((~ ni111O))); or(wire_n1lii_dataout, wire_n1O1i_dataout, ni110i); and(wire_n1lil_dataout, wire_n1O1l_dataout, ~(ni110i)); and(wire_n1liO_dataout, wire_n1O1O_dataout, ~(ni110i)); and(wire_n1lli_dataout, wire_n1O0i_dataout, ~(ni110i)); and(wire_n1lll_dataout, wire_n1O0l_dataout, ~(ni110i)); and(wire_n1llO_dataout, wire_n1O0O_dataout, ~(ni110i)); or(wire_n1lOi_dataout, wire_n1Oii_dataout, ni110i); and(wire_n1lOl_dataout, dec_data[24], ~(wire_ni0O_dataout)); or(wire_n1lOO_dataout, dec_data[25], wire_ni0O_dataout); assign wire_n1O_dataout = (rxaui_s2gx_en === 1'b1) ? nliOOl : nl0ill; or(wire_n1O0i_dataout, dec_data[29], wire_ni0O_dataout); or(wire_n1O0l_dataout, dec_data[30], wire_ni0O_dataout); or(wire_n1O0O_dataout, dec_data[31], wire_ni0O_dataout); or(wire_n1O1i_dataout, dec_data[26], wire_ni0O_dataout); or(wire_n1O1l_dataout, dec_data[27], wire_ni0O_dataout); or(wire_n1O1O_dataout, dec_data[28], wire_ni0O_dataout); or(wire_n1Oii_dataout, dec_ctl[3], wire_ni0O_dataout); or(wire_n1Oil_dataout, wire_n011l_dataout, (~ ni111O)); and(wire_n1OiO_dataout, wire_n011O_dataout, ~((~ ni111O))); and(wire_n1Oli_dataout, wire_n010i_dataout, ~((~ ni111O))); and(wire_n1Oll_dataout, wire_n010l_dataout, ~((~ ni111O))); and(wire_n1OlO_dataout, wire_n010O_dataout, ~((~ ni111O))); and(wire_n1OOi_dataout, wire_n01ii_dataout, ~((~ ni111O))); and(wire_n1OOl_dataout, wire_n01il_dataout, ~((~ ni111O))); and(wire_n1OOO_dataout, wire_n01iO_dataout, ~((~ ni111O))); assign wire_ni_dataout = (rxaui_s2gx_en === 1'b1) ? n10lO : nllO0i; or(wire_ni00i_dataout, wire_nlll_dataout, n0Olii); or(wire_ni00l_dataout, wire_nllO_dataout, n0Olii); or(wire_ni00O_dataout, wire_nlOi_dataout, n0Olii); or(wire_ni01i_dataout, wire_nlil_dataout, n0Olii); or(wire_ni01l_dataout, wire_nliO_dataout, n0Olii); or(wire_ni01O_dataout, wire_nlli_dataout, n0Olii); and(wire_ni0i_dataout, running_disp[1], ~(ni1l0O)); or(wire_ni0ii_dataout, wire_nlOl_dataout, n0Olii); or(wire_ni0il_dataout, wire_nill_dataout, n0Olii); and(wire_ni0l_dataout, running_disp[2], ~(ni1l0O)); and(wire_ni0lO_dataout, wire_nlii_dataout, ~(n0OliO)); and(wire_ni0O_dataout, running_disp[3], ~(ni1l0O)); or(wire_ni0Oi_dataout, wire_nlil_dataout, n0OliO); or(wire_ni0Ol_dataout, wire_nliO_dataout, n0OliO); or(wire_ni0OO_dataout, wire_nlli_dataout, n0OliO); assign wire_ni10i_dataout = (ni1l1l === 1'b1) ? wire_nii0i_dataout : wire_ni1Oi_dataout; assign wire_ni10l_dataout = (ni1l1l === 1'b1) ? wire_nii0l_dataout : wire_ni1Ol_dataout; assign wire_ni10O_dataout = (n0Olil === 1'b1) ? wire_ni1OO_dataout : wire_nlii_dataout; assign wire_ni11i_dataout = (ni1l1l === 1'b1) ? wire_nii1i_dataout : wire_ni1li_dataout; assign wire_ni11l_dataout = (ni1l1l === 1'b1) ? wire_nii1l_dataout : wire_ni1ll_dataout; assign wire_ni11O_dataout = (ni1l1l === 1'b1) ? wire_nii1O_dataout : wire_ni1lO_dataout; assign wire_ni1ii_dataout = (n0Olil === 1'b1) ? wire_ni01i_dataout : wire_nlil_dataout; assign wire_ni1il_dataout = (n0Olil === 1'b1) ? wire_ni01l_dataout : wire_nliO_dataout; assign wire_ni1iO_dataout = (n0Olil === 1'b1) ? wire_ni01O_dataout : wire_nlli_dataout; assign wire_ni1li_dataout = (n0Olil === 1'b1) ? wire_ni00i_dataout : wire_nlll_dataout; assign wire_ni1ll_dataout = (n0Olil === 1'b1) ? wire_ni00l_dataout : wire_nllO_dataout; assign wire_ni1lO_dataout = (n0Olil === 1'b1) ? wire_ni00O_dataout : wire_nlOi_dataout; and(wire_ni1O_dataout, running_disp[0], ~(ni1l0O)); assign wire_ni1Oi_dataout = (n0Olil === 1'b1) ? wire_ni0ii_dataout : wire_nlOl_dataout; assign wire_ni1Ol_dataout = (n0Olil === 1'b1) ? wire_ni0il_dataout : wire_nill_dataout; and(wire_ni1OO_dataout, wire_nlii_dataout, ~(n0Olii)); assign wire_nii_dataout = (rxaui_s2gx_en === 1'b1) ? nll11O : nl0iOO; or(wire_nii0i_dataout, wire_nlOl_dataout, n0OliO); or(wire_nii0l_dataout, wire_nill_dataout, n0OliO); or(wire_nii1i_dataout, wire_nlll_dataout, n0OliO); or(wire_nii1l_dataout, wire_nllO_dataout, n0OliO); or(wire_nii1O_dataout, wire_nlOi_dataout, n0OliO); assign wire_niii0i_dataout = (n0Ol1i === 1'b1) ? wire_nil0ii_dataout : wire_niiiOi_dataout; assign wire_niii0l_dataout = (n0Ol1i === 1'b1) ? wire_nil0il_dataout : wire_niiiOl_dataout; assign wire_niii0O_dataout = (n0Ol1i === 1'b1) ? wire_nil0iO_dataout : wire_niiiOO_dataout; assign wire_niii1l_dataout = (n0Ol1i === 1'b1) ? wire_nil00l_dataout : wire_niiill_dataout; assign wire_niii1O_dataout = (n0Ol1i === 1'b1) ? wire_nil00O_dataout : wire_niiilO_dataout; assign wire_niiiii_dataout = (n0Ol1i === 1'b1) ? wire_nil0li_dataout : wire_niil1i_dataout; assign wire_niiiil_dataout = (n0Ol1i === 1'b1) ? wire_nil0ll_dataout : wire_niil1l_dataout; assign wire_niiiiO_dataout = (n0Ol1i === 1'b1) ? wire_nil0lO_dataout : wire_niil1O_dataout; assign wire_niiili_dataout = (n0Ol1i === 1'b1) ? wire_nil0Oi_dataout : wire_niil0i_dataout; assign wire_niiill_dataout = (n0OilO === 1'b1) ? wire_niiOil_dataout : wire_niil0l_dataout; assign wire_niiilO_dataout = (n0OilO === 1'b1) ? wire_niiOiO_dataout : wire_niil0O_dataout; assign wire_niiiOi_dataout = (n0OilO === 1'b1) ? wire_niiOli_dataout : wire_niilii_dataout; assign wire_niiiOl_dataout = (n0OilO === 1'b1) ? wire_niiOll_dataout : wire_niilil_dataout; assign wire_niiiOO_dataout = (n0OilO === 1'b1) ? wire_niiOlO_dataout : wire_niiliO_dataout; assign wire_niil0i_dataout = (n0OilO === 1'b1) ? wire_nil11i_dataout : wire_niilOi_dataout; and(wire_niil0l_dataout, wire_niilOl_dataout, ni111O); and(wire_niil0O_dataout, wire_niilOO_dataout, ni111O); assign wire_niil1i_dataout = (n0OilO === 1'b1) ? wire_niiOOi_dataout : wire_niilli_dataout; assign wire_niil1l_dataout = (n0OilO === 1'b1) ? wire_niiOOl_dataout : wire_niilll_dataout; assign wire_niil1O_dataout = (n0OilO === 1'b1) ? wire_niiOOO_dataout : wire_niillO_dataout; or(wire_niilii_dataout, wire_niiO1i_dataout, ~(ni111O)); or(wire_niilil_dataout, wire_niiO1l_dataout, ~(ni111O)); or(wire_niiliO_dataout, wire_niiO1O_dataout, ~(ni111O)); and(wire_niilli_dataout, wire_niiO0i_dataout, ni111O); and(wire_niilll_dataout, wire_niiO0l_dataout, ni111O); or(wire_niillO_dataout, wire_niiO0O_dataout, ~(ni111O)); or(wire_niilOi_dataout, wire_niiOii_dataout, ~(ni111O)); or(wire_niilOl_dataout, dec_data[0], ni110i); or(wire_niilOO_dataout, dec_data[1], ni110i); and(wire_niiO0i_dataout, dec_data[5], ~(ni110i)); and(wire_niiO0l_dataout, dec_data[6], ~(ni110i)); and(wire_niiO0O_dataout, dec_data[7], ~(ni110i)); or(wire_niiO1i_dataout, dec_data[2], ni110i); and(wire_niiO1l_dataout, dec_data[3], ~(ni110i)); and(wire_niiO1O_dataout, dec_data[4], ~(ni110i)); or(wire_niiOii_dataout, dec_ctl[0], ni110i); and(wire_niiOil_dataout, wire_nil11l_dataout, ~((~ ni111O))); and(wire_niiOiO_dataout, wire_nil11O_dataout, ~((~ ni111O))); or(wire_niiOli_dataout, wire_nil10i_dataout, (~ ni111O)); or(wire_niiOll_dataout, wire_nil10l_dataout, (~ ni111O)); or(wire_niiOlO_dataout, wire_nil10O_dataout, (~ ni111O)); and(wire_niiOOi_dataout, wire_nil1ii_dataout, ~((~ ni111O))); and(wire_niiOOl_dataout, wire_nil1il_dataout, ~((~ ni111O))); or(wire_niiOOO_dataout, wire_nil1iO_dataout, (~ ni111O)); assign wire_nil_dataout = (rxaui_s2gx_en === 1'b1) ? nllOil : nll10l; or(wire_nil00i_dataout, dec_ctl[0], n0OiOi); and(wire_nil00l_dataout, wire_nil0Ol_dataout, ~((~ ni111O))); and(wire_nil00O_dataout, wire_nil0OO_dataout, ~((~ ni111O))); and(wire_nil01i_dataout, dec_data[5], ~(n0OiOi)); and(wire_nil01l_dataout, dec_data[6], ~(n0OiOi)); and(wire_nil01O_dataout, dec_data[7], ~(n0OiOi)); and(wire_nil0i_dataout, wire_nilOi_dataout, ~(ni1l0O)); or(wire_nil0ii_dataout, wire_nili1i_dataout, (~ ni111O)); or(wire_nil0il_dataout, wire_nili1l_dataout, (~ ni111O)); or(wire_nil0iO_dataout, wire_nili1O_dataout, (~ ni111O)); and(wire_nil0l_dataout, wire_nilOl_dataout, ~(ni1l0O)); and(wire_nil0li_dataout, wire_nili0i_dataout, ~((~ ni111O))); and(wire_nil0ll_dataout, wire_nili0l_dataout, ~((~ ni111O))); or(wire_nil0lO_dataout, wire_nili0O_dataout, (~ ni111O)); and(wire_nil0O_dataout, wire_nilOO_dataout, ~(ni1l0O)); or(wire_nil0Oi_dataout, wire_niliii_dataout, (~ ni111O)); assign wire_nil0Ol_dataout = (ni1lii === 1'b1) ? wire_niliil_dataout : wire_nil11l_dataout; assign wire_nil0OO_dataout = (ni1lii === 1'b1) ? wire_niliiO_dataout : wire_nil11O_dataout; or(wire_nil10i_dataout, wire_nil1Oi_dataout, wire_ni1O_dataout); or(wire_nil10l_dataout, wire_nil1Ol_dataout, wire_ni1O_dataout); or(wire_nil10O_dataout, wire_nil1OO_dataout, wire_ni1O_dataout); or(wire_nil11i_dataout, wire_nil1li_dataout, (~ ni111O)); and(wire_nil11l_dataout, wire_nil1ll_dataout, ~(wire_ni1O_dataout)); or(wire_nil11O_dataout, wire_nil1lO_dataout, wire_ni1O_dataout); and(wire_nil1i_dataout, wire_nilli_dataout, ~(ni1l0O)); or(wire_nil1ii_dataout, wire_nil01i_dataout, wire_ni1O_dataout); or(wire_nil1il_dataout, wire_nil01l_dataout, wire_ni1O_dataout); or(wire_nil1iO_dataout, wire_nil01O_dataout, wire_ni1O_dataout); and(wire_nil1l_dataout, wire_nilll_dataout, ~(ni1l0O)); or(wire_nil1li_dataout, wire_nil00i_dataout, wire_ni1O_dataout); or(wire_nil1ll_dataout, dec_data[0], n0OiOi); or(wire_nil1lO_dataout, dec_data[1], n0OiOi); and(wire_nil1O_dataout, wire_nillO_dataout, ~(ni1l0O)); or(wire_nil1Oi_dataout, dec_data[2], n0OiOi); and(wire_nil1Ol_dataout, dec_data[3], ~(n0OiOi)); and(wire_nil1OO_dataout, dec_data[4], ~(n0OiOi)); assign wire_nili_dataout = (rxaui_s2gx_en === 1'b1) ? niii1i : nii0OO; assign wire_nili0i_dataout = (ni1lii === 1'b1) ? wire_niliOi_dataout : wire_nil1ii_dataout; assign wire_nili0l_dataout = (ni1lii === 1'b1) ? wire_niliOl_dataout : wire_nil1il_dataout; assign wire_nili0O_dataout = (ni1lii === 1'b1) ? wire_niliOO_dataout : wire_nil1iO_dataout; assign wire_nili1i_dataout = (ni1lii === 1'b1) ? wire_nilili_dataout : wire_nil10i_dataout; assign wire_nili1l_dataout = (ni1lii === 1'b1) ? wire_nilill_dataout : wire_nil10l_dataout; assign wire_nili1O_dataout = (ni1lii === 1'b1) ? wire_nililO_dataout : wire_nil10O_dataout; and(wire_nilii_dataout, wire_niO1i_dataout, ~(ni1l0O)); assign wire_niliii_dataout = (ni1lii === 1'b1) ? wire_nill1i_dataout : wire_nil1li_dataout; and(wire_niliil_dataout, wire_nil1ll_dataout, ~(n0Ol0l)); or(wire_niliiO_dataout, wire_nil1lO_dataout, n0Ol0l); and(wire_nilil_dataout, wire_niO1l_dataout, ~(ni1l0O)); or(wire_nilili_dataout, wire_nil1Oi_dataout, n0Ol0l); or(wire_nilill_dataout, wire_nil1Ol_dataout, n0Ol0l); or(wire_nililO_dataout, wire_nil1OO_dataout, n0Ol0l); and(wire_niliO_dataout, wire_niO1O_dataout, ~(ni1l0O)); or(wire_niliOi_dataout, wire_nil01i_dataout, n0Ol0l); or(wire_niliOl_dataout, wire_nil01l_dataout, n0Ol0l); or(wire_niliOO_dataout, wire_nil01O_dataout, n0Ol0l); assign wire_nill_dataout = (rxaui_s2gx_en === 1'b1) ? nl1lOi : niO0li; or(wire_nill1i_dataout, wire_nil00i_dataout, n0Ol0l); assign wire_nilli_dataout = (n0OOii === 1'b1) ? wire_nl1iO_dataout : wire_niO0i_dataout; assign wire_nilll_dataout = (n0OOii === 1'b1) ? wire_nl1li_dataout : wire_niO0l_dataout; or(wire_nilllO_dataout, wire_nilO0O_dataout, wire_nllOO_o); assign wire_nillO_dataout = (n0OOii === 1'b1) ? wire_nl1ll_dataout : wire_niO0O_dataout; and(wire_nillOi_dataout, wire_nilOii_dataout, ~(wire_nllOO_o)); and(wire_nillOl_dataout, wire_nilOil_dataout, ~(wire_nllOO_o)); or(wire_nillOO_dataout, wire_nilOiO_dataout, wire_nllOO_o); assign wire_nilO_dataout = (rxaui_s2gx_en === 1'b1) ? nll10i : nl0l1i; and(wire_nilO0i_dataout, wire_nilOOi_dataout, ~(wire_nllOO_o)); or(wire_nilO0l_dataout, wire_nilOOl_dataout, wire_nllOO_o); or(wire_nilO0O_dataout, wire_nilOOO_dataout, wire_nllOl_o); or(wire_nilO1i_dataout, wire_nilOli_dataout, wire_nllOO_o); or(wire_nilO1l_dataout, wire_nilOll_dataout, wire_nllOO_o); and(wire_nilO1O_dataout, wire_nilOlO_dataout, ~(wire_nllOO_o)); assign wire_nilOi_dataout = (n0OOii === 1'b1) ? wire_nl1lO_dataout : wire_niOii_dataout; or(wire_nilOii_dataout, wire_niO11i_dataout, wire_nllOl_o); or(wire_nilOil_dataout, wire_niO11l_dataout, wire_nllOl_o); or(wire_nilOiO_dataout, wire_niO11O_dataout, wire_nllOl_o); assign wire_nilOl_dataout = (n0OOii === 1'b1) ? wire_nl1Oi_dataout : wire_niOil_dataout; and(wire_nilOli_dataout, wire_niO10i_dataout, ~(wire_nllOl_o)); and(wire_nilOll_dataout, wire_niO10l_dataout, ~(wire_nllOl_o)); and(wire_nilOlO_dataout, wire_niO10O_dataout, ~(wire_nllOl_o)); assign wire_nilOO_dataout = (n0OOii === 1'b1) ? wire_nl1Ol_dataout : wire_niOiO_dataout; and(wire_nilOOi_dataout, wire_niO1ii_dataout, ~(wire_nllOl_o)); and(wire_nilOOl_dataout, wire_niO1il_dataout, ~(wire_nllOl_o)); assign wire_nilOOO_dataout = (ni1l1l === 1'b1) ? dec_ctl[0] : wire_niO01l_dataout; assign wire_niO_dataout = (rxaui_s2gx_en === 1'b1) ? n10il : nlllOO; or(wire_niO01i_dataout, dec_data[7], wire_ni1O_dataout); or(wire_niO01l_dataout, dec_ctl[0], wire_ni1O_dataout); assign wire_niO0i_dataout = (nii00O === 1'b1) ? wire_niOOi_dataout : wire_nlOO_dataout; assign wire_niO0l_dataout = (nii00O === 1'b1) ? wire_niOOl_dataout : wire_n1i_dataout; assign wire_niO0lO_dataout = (n0Ol1i === 1'b1) ? wire_nl11OO_dataout : wire_niOi0O_dataout; assign wire_niO0O_dataout = (nii00O === 1'b1) ? wire_niOOO_dataout : wire_n1l_dataout; assign wire_niO0Oi_dataout = (n0Ol1i === 1'b1) ? wire_nl101i_dataout : wire_niOiii_dataout; assign wire_niO0Ol_dataout = (n0Ol1i === 1'b1) ? wire_nl101l_dataout : wire_niOiil_dataout; assign wire_niO0OO_dataout = (n0Ol1i === 1'b1) ? wire_nl101O_dataout : wire_niOiiO_dataout; assign wire_niO10i_dataout = (ni1l1l === 1'b1) ? dec_data[3] : wire_niO1lO_dataout; assign wire_niO10l_dataout = (ni1l1l === 1'b1) ? dec_data[4] : wire_niO1Oi_dataout; assign wire_niO10O_dataout = (ni1l1l === 1'b1) ? dec_data[5] : wire_niO1Ol_dataout; assign wire_niO11i_dataout = (ni1l1l === 1'b1) ? dec_data[0] : wire_niO1iO_dataout; assign wire_niO11l_dataout = (ni1l1l === 1'b1) ? dec_data[1] : wire_niO1li_dataout; assign wire_niO11O_dataout = (ni1l1l === 1'b1) ? dec_data[2] : wire_niO1ll_dataout; assign wire_niO1i_dataout = (n0OOii === 1'b1) ? wire_nl1OO_dataout : wire_niOli_dataout; assign wire_niO1ii_dataout = (ni1l1l === 1'b1) ? dec_data[6] : wire_niO1OO_dataout; assign wire_niO1il_dataout = (ni1l1l === 1'b1) ? dec_data[7] : wire_niO01i_dataout; and(wire_niO1iO_dataout, dec_data[0], ~(wire_ni1O_dataout)); assign wire_niO1l_dataout = (n0OOii === 1'b1) ? wire_nl01i_dataout : wire_niOll_dataout; or(wire_niO1li_dataout, dec_data[1], wire_ni1O_dataout); or(wire_niO1ll_dataout, dec_data[2], wire_ni1O_dataout); or(wire_niO1lO_dataout, dec_data[3], wire_ni1O_dataout); assign wire_niO1O_dataout = (n0OOii === 1'b1) ? wire_nl01l_dataout : wire_niOlO_dataout; or(wire_niO1Oi_dataout, dec_data[4], wire_ni1O_dataout); or(wire_niO1Ol_dataout, dec_data[5], wire_ni1O_dataout); or(wire_niO1OO_dataout, dec_data[6], wire_ni1O_dataout); assign wire_niOi_dataout = (rxaui_s2gx_en === 1'b1) ? n10OO : nllOii; assign wire_niOi0i_dataout = (n0Ol1i === 1'b1) ? wire_nl10ii_dataout : wire_niOiOi_dataout; assign wire_niOi0l_dataout = (n0Ol1i === 1'b1) ? wire_nl10il_dataout : wire_niOiOl_dataout; assign wire_niOi0O_dataout = (n0OilO === 1'b1) ? wire_niOO1O_dataout : wire_niOiOO_dataout; assign wire_niOi1i_dataout = (n0Ol1i === 1'b1) ? wire_nl100i_dataout : wire_niOili_dataout; assign wire_niOi1l_dataout = (n0Ol1i === 1'b1) ? wire_nl100l_dataout : wire_niOill_dataout; assign wire_niOi1O_dataout = (n0Ol1i === 1'b1) ? wire_nl100O_dataout : wire_niOilO_dataout; assign wire_niOii_dataout = (nii00O === 1'b1) ? wire_nl11i_dataout : wire_n1O_dataout; assign wire_niOiii_dataout = (n0OilO === 1'b1) ? wire_niOO0i_dataout : wire_niOl1i_dataout; assign wire_niOiil_dataout = (n0OilO === 1'b1) ? wire_niOO0l_dataout : wire_niOl1l_dataout; assign wire_niOiiO_dataout = (n0OilO === 1'b1) ? wire_niOO0O_dataout : wire_niOl1O_dataout; assign wire_niOil_dataout = (nii00O === 1'b1) ? wire_nl11l_dataout : wire_n0i_dataout; assign wire_niOili_dataout = (n0OilO === 1'b1) ? wire_niOOii_dataout : wire_niOl0i_dataout; assign wire_niOill_dataout = (n0OilO === 1'b1) ? wire_niOOil_dataout : wire_niOl0l_dataout; assign wire_niOilO_dataout = (n0OilO === 1'b1) ? wire_niOOiO_dataout : wire_niOl0O_dataout; assign wire_niOiO_dataout = (nii00O === 1'b1) ? wire_nl11O_dataout : wire_n0l_dataout; assign wire_niOiOi_dataout = (n0OilO === 1'b1) ? wire_niOOli_dataout : wire_niOlii_dataout; assign wire_niOiOl_dataout = (n0OilO === 1'b1) ? wire_niOOll_dataout : wire_niOlil_dataout; and(wire_niOiOO_dataout, wire_niOliO_dataout, ni111O); assign wire_niOl_dataout = (rxaui_s2gx_en === 1'b1) ? nill1O : nii0ii; and(wire_niOl0i_dataout, wire_niOlOi_dataout, ni111O); and(wire_niOl0l_dataout, wire_niOlOl_dataout, ni111O); and(wire_niOl0O_dataout, wire_niOlOO_dataout, ni111O); and(wire_niOl1i_dataout, wire_niOlli_dataout, ni111O); and(wire_niOl1l_dataout, wire_niOlll_dataout, ni111O); and(wire_niOl1O_dataout, wire_niOllO_dataout, ni111O); assign wire_niOli_dataout = (nii00O === 1'b1) ? wire_nl10i_dataout : wire_n0O_dataout; and(wire_niOlii_dataout, wire_niOO1i_dataout, ni111O); and(wire_niOlil_dataout, wire_niOO1l_dataout, ni111O); or(wire_niOliO_dataout, dec_data[8], ni110i); assign wire_niOll_dataout = (nii00O === 1'b1) ? wire_nl10l_dataout : wire_nii_dataout; or(wire_niOlli_dataout, dec_data[9], ni110i); or(wire_niOlll_dataout, dec_data[10], ni110i); and(wire_niOllO_dataout, dec_data[11], ~(ni110i)); assign wire_niOlO_dataout = (nii00O === 1'b1) ? wire_nl10O_dataout : wire_nilO_dataout; and(wire_niOlOi_dataout, dec_data[12], ~(ni110i)); and(wire_niOlOl_dataout, dec_data[13], ~(ni110i)); and(wire_niOlOO_dataout, dec_data[14], ~(ni110i)); assign wire_niOO_dataout = (rxaui_s2gx_en === 1'b1) ? nill0i : nii0il; and(wire_niOO0i_dataout, wire_niOOOi_dataout, ~((~ ni111O))); and(wire_niOO0l_dataout, wire_niOOOl_dataout, ~((~ ni111O))); and(wire_niOO0O_dataout, wire_niOOOO_dataout, ~((~ ni111O))); and(wire_niOO1i_dataout, dec_data[15], ~(ni110i)); or(wire_niOO1l_dataout, dec_ctl[1], ni110i); and(wire_niOO1O_dataout, wire_niOOlO_dataout, ~((~ ni111O))); and(wire_niOOi_dataout, wire_nlOO_dataout, ~(n0OllO)); and(wire_niOOii_dataout, wire_nl111i_dataout, ~((~ ni111O))); and(wire_niOOil_dataout, wire_nl111l_dataout, ~((~ ni111O))); and(wire_niOOiO_dataout, wire_nl111O_dataout, ~((~ ni111O))); or(wire_niOOl_dataout, wire_n1i_dataout, n0OllO); and(wire_niOOli_dataout, wire_nl110i_dataout, ~((~ ni111O))); and(wire_niOOll_dataout, wire_nl110l_dataout, ~((~ ni111O))); and(wire_niOOlO_dataout, wire_nl110O_dataout, ~(wire_ni0i_dataout)); or(wire_niOOO_dataout, wire_n1l_dataout, n0OllO); or(wire_niOOOi_dataout, wire_nl11ii_dataout, wire_ni0i_dataout); or(wire_niOOOl_dataout, wire_nl11il_dataout, wire_ni0i_dataout); or(wire_niOOOO_dataout, wire_nl11iO_dataout, wire_ni0i_dataout); assign wire_nl_dataout = (rxaui_s2gx_en === 1'b1) ? n10Oi : nllO0l; or(wire_nl000i_dataout, dec_data[15], wire_ni0i_dataout); or(wire_nl000l_dataout, dec_ctl[1], wire_ni0i_dataout); and(wire_nl000O_dataout, wire_nl00OO_dataout, ~((~ ni111O))); or(wire_nl001i_dataout, dec_data[12], wire_ni0i_dataout); or(wire_nl001l_dataout, dec_data[13], wire_ni0i_dataout); or(wire_nl001O_dataout, dec_data[14], wire_ni0i_dataout); and(wire_nl00ii_dataout, wire_nl0i1i_dataout, ~((~ ni111O))); and(wire_nl00il_dataout, wire_nl0i1l_dataout, ~((~ ni111O))); and(wire_nl00iO_dataout, wire_nl0i1O_dataout, ~((~ ni111O))); and(wire_nl00li_dataout, wire_nl0i0i_dataout, ~((~ ni111O))); and(wire_nl00ll_dataout, wire_nl0i0l_dataout, ~((~ ni111O))); and(wire_nl00lO_dataout, wire_nl0i0O_dataout, ~((~ ni111O))); and(wire_nl00Oi_dataout, wire_nl0iii_dataout, ~((~ ni111O))); and(wire_nl00Ol_dataout, wire_nl0iil_dataout, ~((~ ni111O))); or(wire_nl00OO_dataout, wire_nl01lO_dataout, n0Ol0i); or(wire_nl010i_dataout, wire_nl01Oi_dataout, ni110i); or(wire_nl010l_dataout, wire_nl01Ol_dataout, ni110i); and(wire_nl010O_dataout, wire_nl01OO_dataout, ~(ni110i)); and(wire_nl011i_dataout, wire_nl01li_dataout, ~((~ ni111O))); and(wire_nl011l_dataout, wire_nl01ll_dataout, ~((~ ni111O))); or(wire_nl011O_dataout, wire_nl01lO_dataout, ni110i); or(wire_nl01i_dataout, wire_nii_dataout, n0OlOi); and(wire_nl01ii_dataout, wire_nl001i_dataout, ~(ni110i)); and(wire_nl01il_dataout, wire_nl001l_dataout, ~(ni110i)); and(wire_nl01iO_dataout, wire_nl001O_dataout, ~(ni110i)); or(wire_nl01l_dataout, wire_nilO_dataout, n0OlOi); and(wire_nl01li_dataout, wire_nl000i_dataout, ~(ni110i)); or(wire_nl01ll_dataout, wire_nl000l_dataout, ni110i); and(wire_nl01lO_dataout, dec_data[8], ~(wire_ni0i_dataout)); or(wire_nl01Oi_dataout, dec_data[9], wire_ni0i_dataout); or(wire_nl01Ol_dataout, dec_data[10], wire_ni0i_dataout); or(wire_nl01OO_dataout, dec_data[11], wire_ni0i_dataout); assign wire_nl0i_dataout = (rxaui_s2gx_en === 1'b1) ? nillil : nii0lO; and(wire_nl0i0i_dataout, wire_nl001i_dataout, ~(n0Ol0i)); and(wire_nl0i0l_dataout, wire_nl001l_dataout, ~(n0Ol0i)); and(wire_nl0i0O_dataout, wire_nl001O_dataout, ~(n0Ol0i)); or(wire_nl0i1i_dataout, wire_nl01Oi_dataout, n0Ol0i); or(wire_nl0i1l_dataout, wire_nl01Ol_dataout, n0Ol0i); and(wire_nl0i1O_dataout, wire_nl01OO_dataout, ~(n0Ol0i)); and(wire_nl0iii_dataout, wire_nl000i_dataout, ~(n0Ol0i)); or(wire_nl0iil_dataout, wire_nl000l_dataout, n0Ol0i); assign wire_nl0l_dataout = (rxaui_s2gx_en === 1'b1) ? nilliO : nii0Oi; assign wire_nl0l0i_dataout = (n0Ol1i === 1'b1) ? wire_nliiii_dataout : wire_nl0lOi_dataout; assign wire_nl0l0l_dataout = (n0Ol1i === 1'b1) ? wire_nliiil_dataout : wire_nl0lOl_dataout; assign wire_nl0l0O_dataout = (n0Ol1i === 1'b1) ? wire_nliiiO_dataout : wire_nl0lOO_dataout; assign wire_nl0l1O_dataout = (n0Ol1i === 1'b1) ? wire_nlii0O_dataout : wire_nl0llO_dataout; assign wire_nl0lii_dataout = (n0Ol1i === 1'b1) ? wire_nliili_dataout : wire_nl0O1i_dataout; assign wire_nl0lil_dataout = (n0Ol1i === 1'b1) ? wire_nliill_dataout : wire_nl0O1l_dataout; assign wire_nl0liO_dataout = (n0Ol1i === 1'b1) ? wire_nliilO_dataout : wire_nl0O1O_dataout; assign wire_nl0lli_dataout = (n0Ol1i === 1'b1) ? wire_nliiOi_dataout : wire_nl0O0i_dataout; assign wire_nl0lll_dataout = (n0Ol1i === 1'b1) ? wire_nliiOl_dataout : wire_nl0O0l_dataout; assign wire_nl0llO_dataout = (n0OilO === 1'b1) ? wire_nli1iO_dataout : wire_nl0O0O_dataout; assign wire_nl0lOi_dataout = (n0OilO === 1'b1) ? wire_nli1li_dataout : wire_nl0Oii_dataout; assign wire_nl0lOl_dataout = (n0OilO === 1'b1) ? wire_nli1ll_dataout : wire_nl0Oil_dataout; assign wire_nl0lOO_dataout = (n0OilO === 1'b1) ? wire_nli1lO_dataout : wire_nl0OiO_dataout; assign wire_nl0O_dataout = (rxaui_s2gx_en === 1'b1) ? nillli : nii0Ol; assign wire_nl0O0i_dataout = (n0OilO === 1'b1) ? wire_nli01i_dataout : wire_nl0OOi_dataout; assign wire_nl0O0l_dataout = (n0OilO === 1'b1) ? wire_nli01l_dataout : wire_nl0OOl_dataout; and(wire_nl0O0O_dataout, wire_nl0OOO_dataout, ni111O); assign wire_nl0O1i_dataout = (n0OilO === 1'b1) ? wire_nli1Oi_dataout : wire_nl0Oli_dataout; assign wire_nl0O1l_dataout = (n0OilO === 1'b1) ? wire_nli1Ol_dataout : wire_nl0Oll_dataout; assign wire_nl0O1O_dataout = (n0OilO === 1'b1) ? wire_nli1OO_dataout : wire_nl0OlO_dataout; or(wire_nl0Oi_dataout, wire_nliii_dataout, ni1l0O); and(wire_nl0Oii_dataout, wire_nli11i_dataout, ni111O); and(wire_nl0Oil_dataout, wire_nli11l_dataout, ni111O); and(wire_nl0OiO_dataout, wire_nli11O_dataout, ni111O); and(wire_nl0Ol_dataout, wire_nliil_dataout, ~(ni1l0O)); and(wire_nl0Oli_dataout, wire_nli10i_dataout, ni111O); and(wire_nl0Oll_dataout, wire_nli10l_dataout, ni111O); and(wire_nl0OlO_dataout, wire_nli10O_dataout, ni111O); and(wire_nl0OO_dataout, wire_nliiO_dataout, ~(ni1l0O)); and(wire_nl0OOi_dataout, wire_nli1ii_dataout, ni111O); and(wire_nl0OOl_dataout, wire_nli1il_dataout, ni111O); or(wire_nl0OOO_dataout, dec_data[16], ni110i); and(wire_nl100i_dataout, wire_nl10Oi_dataout, ~((~ ni111O))); and(wire_nl100l_dataout, wire_nl10Ol_dataout, ~((~ ni111O))); and(wire_nl100O_dataout, wire_nl10OO_dataout, ~((~ ni111O))); and(wire_nl101i_dataout, wire_nl10li_dataout, ~((~ ni111O))); and(wire_nl101l_dataout, wire_nl10ll_dataout, ~((~ ni111O))); and(wire_nl101O_dataout, wire_nl10lO_dataout, ~((~ ni111O))); or(wire_nl10i_dataout, wire_n0O_dataout, n0OllO); and(wire_nl10ii_dataout, wire_nl1i1i_dataout, ~((~ ni111O))); and(wire_nl10il_dataout, wire_nl1i1l_dataout, ~((~ ni111O))); assign wire_nl10iO_dataout = (ni1lii === 1'b1) ? wire_nl1ilO_dataout : wire_nl1i1O_dataout; or(wire_nl10l_dataout, wire_nii_dataout, n0OllO); assign wire_nl10li_dataout = (ni1lii === 1'b1) ? wire_nl1iOi_dataout : wire_nl1i0i_dataout; assign wire_nl10ll_dataout = (ni1lii === 1'b1) ? wire_nl1iOl_dataout : wire_nl1i0l_dataout; assign wire_nl10lO_dataout = (ni1lii === 1'b1) ? wire_nl1iOO_dataout : wire_nl1i0O_dataout; or(wire_nl10O_dataout, wire_nilO_dataout, n0OllO); assign wire_nl10Oi_dataout = (ni1lii === 1'b1) ? wire_nl1l1i_dataout : wire_nl1iii_dataout; assign wire_nl10Ol_dataout = (ni1lii === 1'b1) ? wire_nl1l1l_dataout : wire_nl1iil_dataout; assign wire_nl10OO_dataout = (ni1lii === 1'b1) ? wire_nl1l1O_dataout : wire_nl1iiO_dataout; or(wire_nl110i_dataout, wire_nl11Oi_dataout, wire_ni0i_dataout); or(wire_nl110l_dataout, wire_nl11Ol_dataout, wire_ni0i_dataout); or(wire_nl110O_dataout, dec_data[8], n0OiOi); or(wire_nl111i_dataout, wire_nl11li_dataout, wire_ni0i_dataout); or(wire_nl111l_dataout, wire_nl11ll_dataout, wire_ni0i_dataout); or(wire_nl111O_dataout, wire_nl11lO_dataout, wire_ni0i_dataout); or(wire_nl11i_dataout, wire_n1O_dataout, n0OllO); or(wire_nl11ii_dataout, dec_data[9], n0OiOi); or(wire_nl11il_dataout, dec_data[10], n0OiOi); and(wire_nl11iO_dataout, dec_data[11], ~(n0OiOi)); or(wire_nl11l_dataout, wire_n0i_dataout, n0OllO); and(wire_nl11li_dataout, dec_data[12], ~(n0OiOi)); and(wire_nl11ll_dataout, dec_data[13], ~(n0OiOi)); and(wire_nl11lO_dataout, dec_data[14], ~(n0OiOi)); or(wire_nl11O_dataout, wire_n0l_dataout, n0OllO); and(wire_nl11Oi_dataout, dec_data[15], ~(n0OiOi)); or(wire_nl11Ol_dataout, dec_ctl[1], n0OiOi); and(wire_nl11OO_dataout, wire_nl10iO_dataout, ~((~ ni111O))); assign wire_nl1i_dataout = (rxaui_s2gx_en === 1'b1) ? nill0l : nii0iO; or(wire_nl1i0i_dataout, wire_niOOOi_dataout, ni1l1l); or(wire_nl1i0l_dataout, wire_niOOOl_dataout, ni1l1l); assign wire_nl1i0O_dataout = (ni1l1l === 1'b1) ? n0OliO : wire_niOOOO_dataout; assign wire_nl1i1i_dataout = (ni1lii === 1'b1) ? wire_nl1l0i_dataout : wire_nl1ili_dataout; assign wire_nl1i1l_dataout = (ni1lii === 1'b1) ? wire_nl1l0l_dataout : wire_nl1ill_dataout; assign wire_nl1i1O_dataout = (ni1l1l === 1'b1) ? (~ n0OliO) : wire_niOOlO_dataout; assign wire_nl1iii_dataout = (ni1l1l === 1'b1) ? n0OliO : wire_nl111i_dataout; assign wire_nl1iil_dataout = (ni1l1l === 1'b1) ? n0OliO : wire_nl111l_dataout; assign wire_nl1iiO_dataout = (ni1l1l === 1'b1) ? n0OliO : wire_nl111O_dataout; assign wire_nl1ili_dataout = (ni1l1l === 1'b1) ? n0OliO : wire_nl110i_dataout; or(wire_nl1ill_dataout, wire_nl110l_dataout, ni1l1l); and(wire_nl1ilO_dataout, wire_nl110O_dataout, ~(n0Olii)); and(wire_nl1iO_dataout, wire_nlOO_dataout, ~(n0OlOi)); or(wire_nl1iOi_dataout, wire_nl11ii_dataout, n0Olii); or(wire_nl1iOl_dataout, wire_nl11il_dataout, n0Olii); or(wire_nl1iOO_dataout, wire_nl11iO_dataout, n0Olii); assign wire_nl1l_dataout = (rxaui_s2gx_en === 1'b1) ? nill0O : nii0li; or(wire_nl1l0i_dataout, wire_nl11Oi_dataout, n0Olii); or(wire_nl1l0l_dataout, wire_nl11Ol_dataout, n0Olii); or(wire_nl1l1i_dataout, wire_nl11li_dataout, n0Olii); or(wire_nl1l1l_dataout, wire_nl11ll_dataout, n0Olii); or(wire_nl1l1O_dataout, wire_nl11lO_dataout, n0Olii); or(wire_nl1li_dataout, wire_n1i_dataout, n0OlOi); or(wire_nl1ll_dataout, wire_n1l_dataout, n0OlOi); or(wire_nl1lO_dataout, wire_n1O_dataout, n0OlOi); assign wire_nl1lOO_dataout = (n0Ol1i === 1'b1) ? wire_nl000O_dataout : wire_nl1OiO_dataout; assign wire_nl1O_dataout = (rxaui_s2gx_en === 1'b1) ? nillii : nii0ll; assign wire_nl1O0i_dataout = (n0Ol1i === 1'b1) ? wire_nl00li_dataout : wire_nl1OOi_dataout; assign wire_nl1O0l_dataout = (n0Ol1i === 1'b1) ? wire_nl00ll_dataout : wire_nl1OOl_dataout; assign wire_nl1O0O_dataout = (n0Ol1i === 1'b1) ? wire_nl00lO_dataout : wire_nl1OOO_dataout; assign wire_nl1O1i_dataout = (n0Ol1i === 1'b1) ? wire_nl00ii_dataout : wire_nl1Oli_dataout; assign wire_nl1O1l_dataout = (n0Ol1i === 1'b1) ? wire_nl00il_dataout : wire_nl1Oll_dataout; assign wire_nl1O1O_dataout = (n0Ol1i === 1'b1) ? wire_nl00iO_dataout : wire_nl1OlO_dataout; or(wire_nl1Oi_dataout, wire_n0i_dataout, n0OlOi); assign wire_nl1Oii_dataout = (n0Ol1i === 1'b1) ? wire_nl00Oi_dataout : wire_nl011i_dataout; assign wire_nl1Oil_dataout = (n0Ol1i === 1'b1) ? wire_nl00Ol_dataout : wire_nl011l_dataout; and(wire_nl1OiO_dataout, wire_nl011O_dataout, ~((~ ni111O))); or(wire_nl1Ol_dataout, wire_n0l_dataout, n0OlOi); and(wire_nl1Oli_dataout, wire_nl010i_dataout, ~((~ ni111O))); and(wire_nl1Oll_dataout, wire_nl010l_dataout, ~((~ ni111O))); and(wire_nl1OlO_dataout, wire_nl010O_dataout, ~((~ ni111O))); or(wire_nl1OO_dataout, wire_n0O_dataout, n0OlOi); and(wire_nl1OOi_dataout, wire_nl01ii_dataout, ~((~ ni111O))); and(wire_nl1OOl_dataout, wire_nl01il_dataout, ~((~ ni111O))); and(wire_nl1OOO_dataout, wire_nl01iO_dataout, ~((~ ni111O))); assign wire_nli_dataout = (rxaui_s2gx_en === 1'b1) ? n10iO : nllO1i; or(wire_nli00i_dataout, wire_nli0Oi_dataout, wire_ni0l_dataout); or(wire_nli00l_dataout, wire_nli0Ol_dataout, wire_ni0l_dataout); or(wire_nli00O_dataout, wire_nli0OO_dataout, wire_ni0l_dataout); and(wire_nli01i_dataout, wire_nli0li_dataout, ~((~ ni111O))); and(wire_nli01l_dataout, wire_nli0ll_dataout, ~((~ ni111O))); and(wire_nli01O_dataout, wire_nli0lO_dataout, ~(wire_ni0l_dataout)); and(wire_nli0i_dataout, wire_nliOi_dataout, ~(ni1l0O)); or(wire_nli0ii_dataout, wire_nlii1i_dataout, wire_ni0l_dataout); or(wire_nli0il_dataout, wire_nlii1l_dataout, wire_ni0l_dataout); or(wire_nli0iO_dataout, wire_nlii1O_dataout, wire_ni0l_dataout); and(wire_nli0l_dataout, wire_nliOl_dataout, ~(ni1l0O)); or(wire_nli0li_dataout, wire_nlii0i_dataout, wire_ni0l_dataout); or(wire_nli0ll_dataout, wire_nlii0l_dataout, wire_ni0l_dataout); or(wire_nli0lO_dataout, dec_data[16], n0OiOi); and(wire_nli0O_dataout, wire_nliOO_dataout, ~(ni1l0O)); or(wire_nli0Oi_dataout, dec_data[17], n0OiOi); or(wire_nli0Ol_dataout, dec_data[18], n0OiOi); and(wire_nli0OO_dataout, dec_data[19], ~(n0OiOi)); and(wire_nli10i_dataout, dec_data[20], ~(ni110i)); and(wire_nli10l_dataout, dec_data[21], ~(ni110i)); and(wire_nli10O_dataout, dec_data[22], ~(ni110i)); or(wire_nli11i_dataout, dec_data[17], ni110i); or(wire_nli11l_dataout, dec_data[18], ni110i); and(wire_nli11O_dataout, dec_data[19], ~(ni110i)); and(wire_nli1i_dataout, wire_nlili_dataout, ~(ni1l0O)); and(wire_nli1ii_dataout, dec_data[23], ~(ni110i)); or(wire_nli1il_dataout, dec_ctl[2], ni110i); and(wire_nli1iO_dataout, wire_nli01O_dataout, ~((~ ni111O))); and(wire_nli1l_dataout, wire_nlill_dataout, ~(ni1l0O)); and(wire_nli1li_dataout, wire_nli00i_dataout, ~((~ ni111O))); and(wire_nli1ll_dataout, wire_nli00l_dataout, ~((~ ni111O))); and(wire_nli1lO_dataout, wire_nli00O_dataout, ~((~ ni111O))); and(wire_nli1O_dataout, wire_nlilO_dataout, ~(ni1l0O)); and(wire_nli1Oi_dataout, wire_nli0ii_dataout, ~((~ ni111O))); and(wire_nli1Ol_dataout, wire_nli0il_dataout, ~((~ ni111O))); and(wire_nli1OO_dataout, wire_nli0iO_dataout, ~((~ ni111O))); assign wire_nlii_dataout = (rxaui_s2gx_en === 1'b1) ? niO0ll : nillll; and(wire_nlii0i_dataout, dec_data[23], ~(n0OiOi)); or(wire_nlii0l_dataout, dec_ctl[2], n0OiOi); and(wire_nlii0O_dataout, wire_nliiOO_dataout, ~((~ ni111O))); and(wire_nlii1i_dataout, dec_data[20], ~(n0OiOi)); and(wire_nlii1l_dataout, dec_data[21], ~(n0OiOi)); and(wire_nlii1O_dataout, dec_data[22], ~(n0OiOi)); assign wire_nliii_dataout = (n0OO0i === 1'b1) ? wire_nll1i_dataout : wire_nil_dataout; and(wire_nliiii_dataout, wire_nlil1i_dataout, ~((~ ni111O))); and(wire_nliiil_dataout, wire_nlil1l_dataout, ~((~ ni111O))); and(wire_nliiiO_dataout, wire_nlil1O_dataout, ~((~ ni111O))); assign wire_nliil_dataout = (n0OO0i === 1'b1) ? wire_nll1l_dataout : wire_niO_dataout; and(wire_nliili_dataout, wire_nlil0i_dataout, ~((~ ni111O))); and(wire_nliill_dataout, wire_nlil0l_dataout, ~((~ ni111O))); and(wire_nliilO_dataout, wire_nlil0O_dataout, ~((~ ni111O))); assign wire_nliiO_dataout = (n0OO0i === 1'b1) ? wire_nll1O_dataout : wire_nli_dataout; and(wire_nliiOi_dataout, wire_nlilii_dataout, ~((~ ni111O))); and(wire_nliiOl_dataout, wire_nlilil_dataout, ~((~ ni111O))); assign wire_nliiOO_dataout = (ni1lii === 1'b1) ? wire_nliO1O_dataout : wire_nliliO_dataout; assign wire_nlil_dataout = (rxaui_s2gx_en === 1'b1) ? nl1l0O : niO01O; assign wire_nlil0i_dataout = (ni1lii === 1'b1) ? wire_nliOii_dataout : wire_nlilOi_dataout; assign wire_nlil0l_dataout = (ni1lii === 1'b1) ? wire_nliOil_dataout : wire_nlilOl_dataout; assign wire_nlil0O_dataout = (ni1lii === 1'b1) ? wire_nliOiO_dataout : wire_nlilOO_dataout; assign wire_nlil1i_dataout = (ni1lii === 1'b1) ? wire_nliO0i_dataout : wire_nlilli_dataout; assign wire_nlil1l_dataout = (ni1lii === 1'b1) ? wire_nliO0l_dataout : wire_nlilll_dataout; assign wire_nlil1O_dataout = (ni1lii === 1'b1) ? wire_nliO0O_dataout : wire_nlillO_dataout; assign wire_nlili_dataout = (n0OO0i === 1'b1) ? wire_nll0i_dataout : wire_nll_dataout; assign wire_nlilii_dataout = (ni1lii === 1'b1) ? wire_nliOli_dataout : wire_nliO1i_dataout; assign wire_nlilil_dataout = (ni1lii === 1'b1) ? wire_nliOll_dataout : wire_nliO1l_dataout; assign wire_nliliO_dataout = (n0OOii === 1'b1) ? (~ n0OlOi) : wire_nli01O_dataout; assign wire_nlill_dataout = (n0OO0i === 1'b1) ? wire_nll0l_dataout : wire_nlO_dataout; or(wire_nlilli_dataout, wire_nli00i_dataout, n0OOii); or(wire_nlilll_dataout, wire_nli00l_dataout, n0OOii); assign wire_nlillO_dataout = (n0OOii === 1'b1) ? n0OlOi : wire_nli00O_dataout; assign wire_nlilO_dataout = (n0OO0i === 1'b1) ? wire_nll0O_dataout : wire_ni_dataout; assign wire_nlilOi_dataout = (n0OOii === 1'b1) ? n0OlOi : wire_nli0ii_dataout; assign wire_nlilOl_dataout = (n0OOii === 1'b1) ? n0OlOi : wire_nli0il_dataout; assign wire_nlilOO_dataout = (n0OOii === 1'b1) ? n0OlOi : wire_nli0iO_dataout; assign wire_nliO_dataout = (rxaui_s2gx_en === 1'b1) ? nl1lii : niO00i; or(wire_nliO0i_dataout, wire_nli0Oi_dataout, n0OllO); or(wire_nliO0l_dataout, wire_nli0Ol_dataout, n0OllO); or(wire_nliO0O_dataout, wire_nli0OO_dataout, n0OllO); assign wire_nliO1i_dataout = (n0OOii === 1'b1) ? n0OlOi : wire_nli0li_dataout; or(wire_nliO1l_dataout, wire_nli0ll_dataout, n0OOii); and(wire_nliO1O_dataout, wire_nli0lO_dataout, ~(n0OllO)); assign wire_nliOi_dataout = (n0OO0i === 1'b1) ? wire_nllii_dataout : wire_nl_dataout; or(wire_nliOii_dataout, wire_nlii1i_dataout, n0OllO); or(wire_nliOil_dataout, wire_nlii1l_dataout, n0OllO); or(wire_nliOiO_dataout, wire_nlii1O_dataout, n0OllO); assign wire_nliOl_dataout = (n0OO0i === 1'b1) ? wire_nllil_dataout : wire_nO_dataout; or(wire_nliOli_dataout, wire_nlii0i_dataout, n0OllO); or(wire_nliOll_dataout, wire_nlii0l_dataout, n0OllO); assign wire_nliOO_dataout = (n0OO0i === 1'b1) ? wire_nlliO_dataout : wire_niOi_dataout; assign wire_nll_dataout = (rxaui_s2gx_en === 1'b1) ? n10li : nllO1l; and(wire_nll00i_dataout, wire_nll0Oi_dataout, ~((~ ni111O))); and(wire_nll00l_dataout, wire_nll0Ol_dataout, ~((~ ni111O))); and(wire_nll00O_dataout, wire_nll0OO_dataout, ~((~ ni111O))); and(wire_nll01i_dataout, wire_nll0li_dataout, ~((~ ni111O))); and(wire_nll01l_dataout, wire_nll0ll_dataout, ~((~ ni111O))); and(wire_nll01O_dataout, wire_nll0lO_dataout, ~((~ ni111O))); or(wire_nll0i_dataout, wire_nll_dataout, n0OO1i); and(wire_nll0ii_dataout, wire_nlli1i_dataout, ~((~ ni111O))); and(wire_nll0il_dataout, wire_nlli1l_dataout, ~((~ ni111O))); or(wire_nll0iO_dataout, wire_nlli1O_dataout, ni110i); or(wire_nll0l_dataout, wire_nlO_dataout, n0OO1i); or(wire_nll0li_dataout, wire_nlli0i_dataout, ni110i); or(wire_nll0ll_dataout, wire_nlli0l_dataout, ni110i); and(wire_nll0lO_dataout, wire_nlli0O_dataout, ~(ni110i)); or(wire_nll0O_dataout, wire_ni_dataout, n0OO1i); and(wire_nll0Oi_dataout, wire_nlliii_dataout, ~(ni110i)); and(wire_nll0Ol_dataout, wire_nlliil_dataout, ~(ni110i)); and(wire_nll0OO_dataout, wire_nlliiO_dataout, ~(ni110i)); assign wire_nll10O_dataout = (n0Ol1i === 1'b1) ? wire_nllilO_dataout : wire_nll1OO_dataout; and(wire_nll1i_dataout, wire_nil_dataout, ~(n0OO1i)); assign wire_nll1ii_dataout = (n0Ol1i === 1'b1) ? wire_nlliOi_dataout : wire_nll01i_dataout; assign wire_nll1il_dataout = (n0Ol1i === 1'b1) ? wire_nlliOl_dataout : wire_nll01l_dataout; assign wire_nll1iO_dataout = (n0Ol1i === 1'b1) ? wire_nlliOO_dataout : wire_nll01O_dataout; or(wire_nll1l_dataout, wire_niO_dataout, n0OO1i); assign wire_nll1li_dataout = (n0Ol1i === 1'b1) ? wire_nlll1i_dataout : wire_nll00i_dataout; assign wire_nll1ll_dataout = (n0Ol1i === 1'b1) ? wire_nlll1l_dataout : wire_nll00l_dataout; assign wire_nll1lO_dataout = (n0Ol1i === 1'b1) ? wire_nlll1O_dataout : wire_nll00O_dataout; or(wire_nll1O_dataout, wire_nli_dataout, n0OO1i); assign wire_nll1Oi_dataout = (n0Ol1i === 1'b1) ? wire_nlll0i_dataout : wire_nll0ii_dataout; assign wire_nll1Ol_dataout = (n0Ol1i === 1'b1) ? wire_nlll0l_dataout : wire_nll0il_dataout; or(wire_nll1OO_dataout, wire_nll0iO_dataout, (~ ni111O)); assign wire_nlli_dataout = (rxaui_s2gx_en === 1'b1) ? nl1lil : niO00l; or(wire_nlli0i_dataout, dec_data[17], wire_ni0l_dataout); or(wire_nlli0l_dataout, dec_data[18], wire_ni0l_dataout); or(wire_nlli0O_dataout, dec_data[19], wire_ni0l_dataout); and(wire_nlli1i_dataout, wire_nllili_dataout, ~(ni110i)); or(wire_nlli1l_dataout, wire_nllill_dataout, ni110i); and(wire_nlli1O_dataout, dec_data[16], ~(wire_ni0l_dataout)); or(wire_nllii_dataout, wire_nl_dataout, n0OO1i); or(wire_nlliii_dataout, dec_data[20], wire_ni0l_dataout); or(wire_nlliil_dataout, dec_data[21], wire_ni0l_dataout); or(wire_nlliiO_dataout, dec_data[22], wire_ni0l_dataout); or(wire_nllil_dataout, wire_nO_dataout, n0OO1i); or(wire_nllili_dataout, dec_data[23], wire_ni0l_dataout); or(wire_nllill_dataout, dec_ctl[2], wire_ni0l_dataout); and(wire_nllilO_dataout, wire_nlll0O_dataout, ~((~ ni111O))); or(wire_nlliO_dataout, wire_niOi_dataout, n0OO1i); and(wire_nlliOi_dataout, wire_nlllii_dataout, ~((~ ni111O))); and(wire_nlliOl_dataout, wire_nlllil_dataout, ~((~ ni111O))); and(wire_nlliOO_dataout, wire_nllliO_dataout, ~((~ ni111O))); assign wire_nlll_dataout = (rxaui_s2gx_en === 1'b1) ? nl1liO : niO00O; and(wire_nlll0i_dataout, wire_nlllOi_dataout, ~((~ ni111O))); and(wire_nlll0l_dataout, wire_nlllOl_dataout, ~((~ ni111O))); or(wire_nlll0O_dataout, wire_nlli1O_dataout, n0Ol1O); and(wire_nlll1i_dataout, wire_nlllli_dataout, ~((~ ni111O))); and(wire_nlll1l_dataout, wire_nlllll_dataout, ~((~ ni111O))); and(wire_nlll1O_dataout, wire_nllllO_dataout, ~((~ ni111O))); or(wire_nlllii_dataout, wire_nlli0i_dataout, n0Ol1O); or(wire_nlllil_dataout, wire_nlli0l_dataout, n0Ol1O); and(wire_nllliO_dataout, wire_nlli0O_dataout, ~(n0Ol1O)); and(wire_nlllli_dataout, wire_nlliii_dataout, ~(n0Ol1O)); and(wire_nlllll_dataout, wire_nlliil_dataout, ~(n0Ol1O)); and(wire_nllllO_dataout, wire_nlliiO_dataout, ~(n0Ol1O)); and(wire_nlllOi_dataout, wire_nllili_dataout, ~(n0Ol1O)); or(wire_nlllOl_dataout, wire_nllill_dataout, n0Ol1O); assign wire_nllO_dataout = (rxaui_s2gx_en === 1'b1) ? nl1lli : niO0ii; assign wire_nllOiO_dataout = (n0Ol1i === 1'b1) ? wire_nlOlOl_dataout : wire_nlO11O_dataout; assign wire_nllOli_dataout = (n0Ol1i === 1'b1) ? wire_nlOlOO_dataout : wire_nlO10i_dataout; assign wire_nllOll_dataout = (n0Ol1i === 1'b1) ? wire_nlOO1i_dataout : wire_nlO10l_dataout; assign wire_nllOlO_dataout = (n0Ol1i === 1'b1) ? wire_nlOO1l_dataout : wire_nlO10O_dataout; assign wire_nllOOi_dataout = (n0Ol1i === 1'b1) ? wire_nlOO1O_dataout : wire_nlO1ii_dataout; assign wire_nllOOl_dataout = (n0Ol1i === 1'b1) ? wire_nlOO0i_dataout : wire_nlO1il_dataout; assign wire_nllOOO_dataout = (n0Ol1i === 1'b1) ? wire_nlOO0l_dataout : wire_nlO1iO_dataout; assign wire_nlO_dataout = (rxaui_s2gx_en === 1'b1) ? n10ll : nllO1O; and(wire_nlO00i_dataout, wire_nlO0Oi_dataout, ni111O); and(wire_nlO00l_dataout, wire_nlO0Ol_dataout, ni111O); or(wire_nlO00O_dataout, dec_data[24], ni110i); and(wire_nlO01i_dataout, wire_nlO0li_dataout, ni111O); and(wire_nlO01l_dataout, wire_nlO0ll_dataout, ni111O); and(wire_nlO01O_dataout, wire_nlO0lO_dataout, ni111O); or(wire_nlO0ii_dataout, dec_data[25], ni110i); or(wire_nlO0il_dataout, dec_data[26], ni110i); and(wire_nlO0iO_dataout, dec_data[27], ~(ni110i)); and(wire_nlO0li_dataout, dec_data[28], ~(ni110i)); and(wire_nlO0ll_dataout, dec_data[29], ~(ni110i)); and(wire_nlO0lO_dataout, dec_data[30], ~(ni110i)); and(wire_nlO0Oi_dataout, dec_data[31], ~(ni110i)); or(wire_nlO0Ol_dataout, dec_ctl[3], ni110i); or(wire_nlO0OO_dataout, wire_nlOiiO_dataout, (~ ni111O)); assign wire_nlO10i_dataout = (n0OilO === 1'b1) ? wire_nlOi1i_dataout : wire_nlO1Oi_dataout; assign wire_nlO10l_dataout = (n0OilO === 1'b1) ? wire_nlOi1l_dataout : wire_nlO1Ol_dataout; assign wire_nlO10O_dataout = (n0OilO === 1'b1) ? wire_nlOi1O_dataout : wire_nlO1OO_dataout; assign wire_nlO11i_dataout = (n0Ol1i === 1'b1) ? wire_nlOO0O_dataout : wire_nlO1li_dataout; assign wire_nlO11l_dataout = (n0Ol1i === 1'b1) ? wire_nlOOii_dataout : wire_nlO1ll_dataout; assign wire_nlO11O_dataout = (n0OilO === 1'b1) ? wire_nlO0OO_dataout : wire_nlO1lO_dataout; and(wire_nlO1i_dataout, (~ ni110i), ~(n0OOll)); assign wire_nlO1ii_dataout = (n0OilO === 1'b1) ? wire_nlOi0i_dataout : wire_nlO01i_dataout; assign wire_nlO1il_dataout = (n0OilO === 1'b1) ? wire_nlOi0l_dataout : wire_nlO01l_dataout; assign wire_nlO1iO_dataout = (n0OilO === 1'b1) ? wire_nlOi0O_dataout : wire_nlO01O_dataout; and(wire_nlO1l_dataout, ni110i, ~(n0OOll)); assign wire_nlO1li_dataout = (n0OilO === 1'b1) ? wire_nlOiii_dataout : wire_nlO00i_dataout; assign wire_nlO1ll_dataout = (n0OilO === 1'b1) ? wire_nlOiil_dataout : wire_nlO00l_dataout; or(wire_nlO1lO_dataout, wire_nlO00O_dataout, ~(ni111O)); and(wire_nlO1Oi_dataout, wire_nlO0ii_dataout, ni111O); and(wire_nlO1Ol_dataout, wire_nlO0il_dataout, ni111O); and(wire_nlO1OO_dataout, wire_nlO0iO_dataout, ni111O); assign wire_nlOi_dataout = (rxaui_s2gx_en === 1'b1) ? nl1lll : niO0il; and(wire_nlOi0i_dataout, wire_nlOiOi_dataout, ~((~ ni111O))); and(wire_nlOi0l_dataout, wire_nlOiOl_dataout, ~((~ ni111O))); and(wire_nlOi0O_dataout, wire_nlOiOO_dataout, ~((~ ni111O))); and(wire_nlOi1i_dataout, wire_nlOili_dataout, ~((~ ni111O))); and(wire_nlOi1l_dataout, wire_nlOill_dataout, ~((~ ni111O))); and(wire_nlOi1O_dataout, wire_nlOilO_dataout, ~((~ ni111O))); and(wire_nlOiii_dataout, wire_nlOl1i_dataout, ~((~ ni111O))); and(wire_nlOiil_dataout, wire_nlOl1l_dataout, ~((~ ni111O))); and(wire_nlOiiO_dataout, wire_nlOl1O_dataout, ~(wire_ni0O_dataout)); or(wire_nlOili_dataout, wire_nlOl0i_dataout, wire_ni0O_dataout); or(wire_nlOill_dataout, wire_nlOl0l_dataout, wire_ni0O_dataout); or(wire_nlOilO_dataout, wire_nlOl0O_dataout, wire_ni0O_dataout); or(wire_nlOiOi_dataout, wire_nlOlii_dataout, wire_ni0O_dataout); or(wire_nlOiOl_dataout, wire_nlOlil_dataout, wire_ni0O_dataout); or(wire_nlOiOO_dataout, wire_nlOliO_dataout, wire_ni0O_dataout); assign wire_nlOl_dataout = (rxaui_s2gx_en === 1'b1) ? nl1llO : niO0iO; or(wire_nlOl0i_dataout, dec_data[25], n0OiOi); or(wire_nlOl0l_dataout, dec_data[26], n0OiOi); and(wire_nlOl0O_dataout, dec_data[27], ~(n0OiOi)); or(wire_nlOl1i_dataout, wire_nlOlli_dataout, wire_ni0O_dataout); or(wire_nlOl1l_dataout, wire_nlOlll_dataout, wire_ni0O_dataout); or(wire_nlOl1O_dataout, dec_data[24], n0OiOi); and(wire_nlOlii_dataout, dec_data[28], ~(n0OiOi)); and(wire_nlOlil_dataout, dec_data[29], ~(n0OiOi)); and(wire_nlOliO_dataout, dec_data[30], ~(n0OiOi)); and(wire_nlOlli_dataout, dec_data[31], ~(n0OiOi)); or(wire_nlOlll_dataout, dec_ctl[3], n0OiOi); or(wire_nlOlOl_dataout, wire_nlOOil_dataout, (~ ni111O)); and(wire_nlOlOO_dataout, wire_nlOOiO_dataout, ~((~ ni111O))); assign wire_nlOO_dataout = (rxaui_s2gx_en === 1'b1) ? nl0l1l : nl1lOl; and(wire_nlOO0i_dataout, wire_nlOOOi_dataout, ~((~ ni111O))); and(wire_nlOO0l_dataout, wire_nlOOOl_dataout, ~((~ ni111O))); and(wire_nlOO0O_dataout, wire_nlOOOO_dataout, ~((~ ni111O))); and(wire_nlOO1i_dataout, wire_nlOOli_dataout, ~((~ ni111O))); and(wire_nlOO1l_dataout, wire_nlOOll_dataout, ~((~ ni111O))); and(wire_nlOO1O_dataout, wire_nlOOlO_dataout, ~((~ ni111O))); or(wire_nlOOi_dataout, wire_nlOOl_dataout, nlOiO); and(wire_nlOOii_dataout, wire_n111i_dataout, ~((~ ni111O))); assign wire_nlOOil_dataout = (ni1lii === 1'b1) ? wire_n11lO_dataout : wire_n111l_dataout; assign wire_nlOOiO_dataout = (ni1lii === 1'b1) ? wire_n11Oi_dataout : wire_n111O_dataout; and(wire_nlOOl_dataout, nlOll, ~((((~ ni111O) | nlOii) | (~ (n0OOlO32 ^ n0OOlO31))))); assign wire_nlOOli_dataout = (ni1lii === 1'b1) ? wire_n11Ol_dataout : wire_n110i_dataout; assign wire_nlOOll_dataout = (ni1lii === 1'b1) ? wire_n11OO_dataout : wire_n110l_dataout; assign wire_nlOOlO_dataout = (ni1lii === 1'b1) ? wire_n101i_dataout : wire_n110O_dataout; assign wire_nlOOOi_dataout = (ni1lii === 1'b1) ? wire_n101l_dataout : wire_n11ii_dataout; assign wire_nlOOOl_dataout = (ni1lii === 1'b1) ? wire_n101O_dataout : wire_n11il_dataout; assign wire_nlOOOO_dataout = (ni1lii === 1'b1) ? wire_n100i_dataout : wire_n11iO_dataout; assign wire_nO_dataout = (rxaui_s2gx_en === 1'b1) ? n10Ol : nllO0O; oper_mux nllOi ( .data({wire_nlO1i_dataout, 1'b0, {2{wire_nlO1i_dataout}}}), .o(wire_nllOi_o), .sel({nlO0O, nlO0l})); defparam nllOi.width_data = 4, nllOi.width_sel = 2; oper_mux nllOl ( .data({((n0OOil38 ^ n0OOil37) & wire_nlO1l_dataout), 1'b0, ((n0OOiO36 ^ n0OOiO35) & wire_nlO1l_dataout), wire_nlO1l_dataout}), .o(wire_nllOl_o), .sel({nlO0O, nlO0l})); defparam nllOl.width_data = 4, nllOl.width_sel = 2; oper_mux nllOO ( .data({n0OOll, 1'b1, {2{n0OOll}}}), .o(wire_nllOO_o), .sel({nlO0O, ((n0OOli34 ^ n0OOli33) & nlO0l)})); defparam nllOO.width_data = 4, nllOO.width_sel = 2; assign curr_state = {nlO0O, nlO0l}, n0Oill = (((((((dec_data[24] & (~ dec_data[25])) & dec_data[26]) & dec_data[27]) & dec_data[28]) & dec_data[29]) & dec_data[30]) & dec_data[31]), n0OilO = ((~ nlO0O) & nlO0l), n0OiOi = (ni110i & (~ (((wire_ni0O_dataout | wire_ni0l_dataout) | wire_ni0i_dataout) | wire_ni1O_dataout))), n0OiOl = (ni1iiO | n0OOii), n0OiOO = (wire_ni0O_dataout | (ni10lO & ni101l)), n0Ol0i = (ni1l1l | ni110i), n0Ol0l = (wire_ni1O_dataout | (ni1i0l & ni10li)), n0Ol0O = ((nii00l | nii00i) | nii00O), n0Ol1i = (nlO0O & nlO0l), n0Ol1l = (ni1iiO | n0Ol1O), n0Ol1O = (ni1iOO | n0Ol0i), n0Olii = (wire_ni0i_dataout | (ni1i1O & ni10il)), n0Olil = (nii00O | nii00i), n0OliO = ((wire_ni0i_dataout | ni1i1O) | (~ (n0Olli46 ^ n0Olli45))), n0OllO = (wire_ni0l_dataout | (ni10Ol & ni100i)), n0OlOi = ((wire_ni0l_dataout | ni10Ol) | (~ (n0OlOl44 ^ n0OlOl43))), n0OO0i = ((ni1iiO | n0OOii) | (~ (n0OO0l40 ^ n0OO0l39))), n0OO1i = ((wire_ni0O_dataout | ni10lO) | (~ (n0OO1l42 ^ n0OO1l41))), n0OOii = (ni1l1l | ni1iOO), n0OOll = ((~ ni111O) | nl0lO), ni100i = (((~ dec_ctl[2]) | (~ ni10ii)) | (~ (ni100l16 ^ ni100l15))), ni101l = ((~ dec_ctl[3]) | (~ ni101O)), ni101O = ((((((((~ dec_data[24]) & (~ dec_data[25])) & dec_data[26]) & dec_data[27]) & dec_data[28]) & dec_data[29]) & dec_data[30]) & (~ dec_data[31])), ni10ii = ((((((((~ dec_data[16]) & (~ dec_data[17])) & dec_data[18]) & dec_data[19]) & dec_data[20]) & dec_data[21]) & dec_data[22]) & (~ dec_data[23])), ni10il = ((~ dec_ctl[1]) | (~ ni10iO)), ni10iO = ((((((((~ dec_data[8]) & (~ dec_data[9])) & dec_data[10]) & dec_data[11]) & dec_data[12]) & dec_data[13]) & dec_data[14]) & (~ dec_data[15])), ni10li = ((~ dec_ctl[0]) | (~ ni10ll)), ni10ll = ((((((((~ dec_data[0]) & (~ dec_data[1])) & dec_data[2]) & dec_data[3]) & dec_data[4]) & dec_data[5]) & dec_data[6]) & (~ dec_data[7])), ni10lO = ((~ dec_ctl[3]) | (~ ni10Oi)), ni10Oi = ((((((((~ dec_data[24]) & (~ dec_data[25])) & dec_data[26]) & dec_data[27]) & dec_data[28]) & dec_data[29]) & (~ dec_data[30])) & dec_data[31]), ni10Ol = (((~ dec_ctl[2]) | (~ ni1i1l)) | (~ (ni10OO14 ^ ni10OO13))), ni110i = ((((~ (((ni10li | ni10il) | ni100i) | ni101l)) | (~ ((((ni1i0l | ni1i1O) | ni10Ol) | ni10lO) | (~ (ni11OO18 ^ ni11OO17))))) | (~ (ni11Oi20 ^ ni11Oi19))) | (~ ((((((~ dec_ctl[0]) | (~ ni11lO)) | ((~ dec_ctl[1]) | (~ ni11ll))) | ((~ dec_ctl[2]) | (~ ni11li))) | (((~ dec_ctl[3]) | (~ ni11iO)) | (~ (ni11ii22 ^ ni11ii21)))) | (~ (ni110l24 ^ ni110l23))))), ni111i = 1'b1, ni111O = (((dec_data_valid[0] & dec_data_valid[1]) & dec_data_valid[2]) & dec_data_valid[3]), ni11iO = ((((((((~ dec_data[24]) & (~ dec_data[25])) & dec_data[26]) & dec_data[27]) & dec_data[28]) & (~ dec_data[29])) & (~ dec_data[30])) & (~ dec_data[31])), ni11li = ((((((((~ dec_data[16]) & (~ dec_data[17])) & dec_data[18]) & dec_data[19]) & dec_data[20]) & (~ dec_data[21])) & (~ dec_data[22])) & (~ dec_data[23])), ni11ll = ((((((((~ dec_data[8]) & (~ dec_data[9])) & dec_data[10]) & dec_data[11]) & dec_data[12]) & (~ dec_data[13])) & (~ dec_data[14])) & (~ dec_data[15])), ni11lO = ((((((((~ dec_data[0]) & (~ dec_data[1])) & dec_data[2]) & dec_data[3]) & dec_data[4]) & (~ dec_data[5])) & (~ dec_data[6])) & (~ dec_data[7])), ni1i0i = ((((((((~ dec_data[8]) & (~ dec_data[9])) & dec_data[10]) & dec_data[11]) & dec_data[12]) & dec_data[13]) & (~ dec_data[14])) & dec_data[15]), ni1i0l = (((~ dec_ctl[0]) | (~ ni1iil)) | (~ (ni1i0O12 ^ ni1i0O11))), ni1i1l = ((((((((~ dec_data[16]) & (~ dec_data[17])) & dec_data[18]) & dec_data[19]) & dec_data[20]) & dec_data[21]) & (~ dec_data[22])) & dec_data[23]), ni1i1O = ((~ dec_ctl[1]) | (~ ni1i0i)), ni1iil = ((((((((~ dec_data[0]) & (~ dec_data[1])) & dec_data[2]) & dec_data[3]) & dec_data[4]) & dec_data[5]) & (~ dec_data[6])) & dec_data[7]), ni1iiO = (((~ wire_ni0l_dataout) & ((dec_ctl[2] & ni1iOl) & (ni1ilO8 ^ ni1ilO7))) & (ni1ili10 ^ ni1ili9)), ni1iOl = (((((((dec_data[16] & (~ dec_data[17])) & dec_data[18]) & dec_data[19]) & dec_data[20]) & dec_data[21]) & dec_data[22]) & dec_data[23]), ni1iOO = ((~ wire_ni0i_dataout) & (dec_ctl[1] & ni1l1i)), ni1l0l = (((((((dec_data[0] & (~ dec_data[1])) & dec_data[2]) & dec_data[3]) & dec_data[4]) & dec_data[5]) & dec_data[6]) & dec_data[7]), ni1l0O = ((~ nlO0O) & (~ nlO0l)), ni1l1i = (((((((dec_data[8] & (~ dec_data[9])) & dec_data[10]) & dec_data[11]) & dec_data[12]) & dec_data[13]) & dec_data[14]) & dec_data[15]), ni1l1l = (((~ wire_ni1O_dataout) & (dec_ctl[0] & ni1l0l)) & (ni1l1O6 ^ ni1l1O5)), ni1lii = (((((nill1l | nii00l) | (~ (ni1lli2 ^ ni1lli1))) | nii00i) | nii00O) | (~ (ni1lil4 ^ ni1lil3))), rx_ctl_rs = {nl0ll, niiOl, n0O1i, n000O}, rx_data_rs = {nl0li, nl0iO, nl0il, nl0ii, nl00O, nl00l, nl00i, niiOO, niiOi, niilO, niill, niili, niiiO, niiil, niiii, n0O1l, n0lOO, n0lOl, n0lOi, n0llO, n0lll, n0lli, n0liO, n00ii, n000l, n000i, n001O, n001l, n001i, n01OO, n01Ol, n1i1i}, rx_local_fault = n10i, xs_link_status = nlOll; endmodule //stratixiv_hssi_rcv_sm //synopsys translate_on //VALID FILE `timescale 1ns / 1ps module stratixiv_hssi_cmu_chnl_reset (hard_reset, soft_reset_all_hssi, rreset, rpowerdown, rxurstpma, rxurstpcs, txurstpcs, rpowdnr, rpowdnt, rrxurstpcs, rtxurstpcs, rrxurstpma, rrx_cru_rst, radce_rst, urx_pdb, rurx_pdb, radce_pdb, rrx_ib_pdb, rtx_ob_pdb, rtx_cgb_pdb, rrx_cru_pdb, rtx_pipe_en, p0_state, p0s_state, p2_state, rxpma_rstb, txpma_rstb, rxpcs_rst, txpcs_rst, cru_rstb, adce_rstb, adce_pdb, cru_pdb, rx_pdb, tx_pdb, cgb_pdb, rx_det_pdb ); // Inputs from QUAD reset module input hard_reset; // hardreset signal input soft_reset_all_hssi;// soft reset for all channel input rreset; // Quad reset CRAM input rpowerdown; // Quad power down CRAM // Channel Reset inputs input rxurstpma; // RX PMA user reset input rxurstpcs; // RX PCS user reset input txurstpcs; // TX PCS user reset // Channel Reset CRAMs input rpowdnr; // RX channel power down CRAM input rpowdnt; // TX channel power down CRAM input rrxurstpcs; // Gating CRAM for RXURSTPCS input rtxurstpcs; // Gating CRAM for TXURSTPCS input rrxurstpma; // Gating CRAM for RXURSTPMA input rrx_cru_rst; // Channel RX PLL reset CRAMs input radce_rst; // Channel Adaptive block reset CRAMs // Powerdown inputs input urx_pdb; // RX user powerdown signal // Powerdown CRAMs input rurx_pdb; // Gating CRAM for urx_pdb signals input radce_pdb; // Adaptive block powerdown CRAMs input rrx_ib_pdb; // RX Input buffer and PLL powerdown CRAMs input rtx_ob_pdb; // TX Output buffer powerdown CRAMs input rtx_cgb_pdb; // TX clock generator powerdown CRAMs input rrx_cru_pdb; // RX PLL powerdown CRAMs // PIPE Inputs input rtx_pipe_en; // PIPE enable CRAMs input p0_state; // PIPE P0 state indicators input p0s_state; // PIPE P0S state indicators input p2_state; // PIPE P2 state indicators // Channel Reset outputs output rxpma_rstb; // RX PMA resets (powerdown) output txpma_rstb; // TX PMA resets (powerdown) output rxpcs_rst; // RX PCS resets output txpcs_rst; // TX PCS resets output cru_rstb; // RX PLL resets output adce_rstb; // Adaptive block resets // Channel Powerdown outputs output adce_pdb; // Adaptive block powerdown output cru_pdb; // RX PLL powerdown output rx_pdb; // RX powerdown output tx_pdb; // TX driver powerdown output cgb_pdb; // Clock generator powerdown output rx_det_pdb; // Receiver detector powerdown /************************************************************************************************ ****************************** RTL section ******************************************************/ // Wiring section for Resets wire rxpcsrst_hssi; wire txpcsrst_hssi; wire rxpmarst_hssi; // Wiring section for Powerdowns wire adce_pd_hssi; wire cru_pd_hssi; wire rx_pd_hssi; wire tx_pd_hssi; wire cgb_pd_hssi; wire rx_det_pd_hssi; // reset internal signals assign rxpcsrst_hssi = (rxurstpcs & rrxurstpcs) | rpowdnr; assign txpcsrst_hssi = (txurstpcs & rtxurstpcs) | rpowdnt; assign rxpmarst_hssi = (rxurstpma & rrxurstpma) | rreset; // reset outputs assign rxpma_rstb = ~(rxpmarst_hssi | hard_reset); assign txpma_rstb = ~(rreset | hard_reset); assign cru_rstb = ~(hard_reset | rreset | rrx_cru_rst); assign adce_rstb = rxpma_rstb & ~(radce_rst); assign rxpcs_rst = rxpcsrst_hssi | hard_reset | soft_reset_all_hssi; assign txpcs_rst = txpcsrst_hssi | hard_reset | soft_reset_all_hssi; // powerdown internal signals assign adce_pd_hssi = ~(radce_pdb) | rpowdnr | rpowerdown; assign cru_pd_hssi = ~(rrx_cru_pdb) | rpowdnr | rpowerdown; assign rx_pd_hssi = ~(urx_pdb | ~(rurx_pdb)) | ~(rrx_ib_pdb) | rpowdnr | rpowerdown; assign tx_pd_hssi = ~(rtx_ob_pdb) | rpowdnt | rpowerdown; assign cgb_pd_hssi = ~(rtx_cgb_pdb) | rpowdnt | rpowerdown; assign rx_det_pd_hssi = (rtx_pipe_en & (p0_state | p0s_state | p2_state)) | rpowdnt | rpowerdown; // powerdown outputs assign adce_pdb = ~(adce_pd_hssi | hard_reset); assign cru_pdb = ~(cru_pd_hssi | hard_reset); assign rx_pdb = ~(rx_pd_hssi | hard_reset); assign tx_pdb = ~(tx_pd_hssi | hard_reset); assign cgb_pdb = ~(cgb_pd_hssi | hard_reset); assign rx_det_pdb = ~(rx_det_pd_hssi | hard_reset); endmodule `timescale 1ps / 1ps module stratixiv_hssi_cmu_quad_reset ( // Common reset inputs entest, plniotri, npor, frzreg, pllurst, // Common reset CRAMs rpllurst, rpowerdown, rreset, // CMU reset inputs rxurstcmu, // CMU reset CRAMs rrxurstcmu, rrx_cmu_rst, // CMU powerdown inputs ucmurx_pdb, // CMU powerdown CRAMs rclk_pdb, rcmu_powdnr, rcmu_cru_pdb, rcmu_urx_pdb, rcmu_rx_ib_pdb, rcmu_powdnt, rcmu_tx_ob_pdb, rcmu_tx_cgb_pdb, rcmu_rx_det_pdb, // CMU reset outputs cmu0_rxpma_rstb, cmu0_txpma_rstb, cmu0_cru_rstb, cmu1_rxpma_rstb, cmu1_txpma_rstb, cmu1_cru_rstb, // CMU powerdown outputs cmu0_rx_pdb, cmu0_cru_pdb, cmu0_clk_pdb, cmu0_tx_pdb, cmu0_cgb_pdb, cmu0_rx_det_pdb, cmu1_rx_pdb, cmu1_cru_pdb, cmu1_clk_pdb, cmu1_tx_pdb, cmu1_cgb_pdb, cmu1_rx_det_pdb, // Other outputs mdio_rst, hard_reset, soft_reset_all_hssi ); // Common reset inputs input entest; // Test mode control from Control block input plniotri; // PLL output enable input npor; // Power on reset input frzreg; // Freeze register during power-up input pllurst; // PLL user reset // Common reset CRAMs input rpllurst; // Gating CRAM for PLLURST input rpowerdown; // Quad power down CRAM input rreset; // Quad reset CRAM // CMU reset inputs input [1:0] rxurstcmu; // Dynamic signal for CMU[1:0]_RXPMA_RSTB // CMU reset CRAMs input [1:0] rrxurstcmu; // Gating CRAM for dynamic signal rxurstcmu input [1:0] rrx_cmu_rst; // TXPLL / RXPLL reset // CMU powerdown inputs input [1:0] ucmurx_pdb; // Dynamic signal for CMU[1:0]_RX_PDB // CMU powerdown CRAMs input [1:0] rclk_pdb; input [1:0] rcmu_powdnr; input [1:0] rcmu_cru_pdb; input [1:0] rcmu_urx_pdb; input [1:0] rcmu_rx_ib_pdb; input [1:0] rcmu_powdnt; input [1:0] rcmu_tx_ob_pdb; input [1:0] rcmu_tx_cgb_pdb; input [1:0] rcmu_rx_det_pdb; // CMU reset outputs output cmu0_rxpma_rstb; output cmu0_txpma_rstb; output cmu0_cru_rstb; output cmu1_rxpma_rstb; output cmu1_txpma_rstb; output cmu1_cru_rstb; // CMU powerdown outputs output cmu0_rx_pdb; output cmu0_cru_pdb; output cmu0_clk_pdb; output cmu0_tx_pdb; output cmu0_cgb_pdb; output cmu0_rx_det_pdb; output cmu1_rx_pdb; output cmu1_cru_pdb; output cmu1_clk_pdb; output cmu1_tx_pdb; output cmu1_cgb_pdb; output cmu1_rx_det_pdb; // Other outputs output mdio_rst; // MDIO reset output hard_reset; // Output HARD_RESET signal for other MDIO modules output soft_reset_all_hssi; // Quad soft reset output /*********************************************************************************** ****************************** RTL section *****************************************/ //---------------------------------- // Wiring section for Resets //---------------------------------- wire cmu0_rxpma_rst_hssi; wire cmu1_rxpma_rst_hssi; wire hard_reset; wire soft_reset_all_hssi; //---------------------------------- // Wiring section for Powerdowns //---------------------------------- wire cmu0_cru_pd_hssi; wire cmu0_rx_pd_hssi; wire cmu0_tx_pd_hssi; wire cmu0_cgb_pd_hssi; wire cmu0_rx_det_pd_hssi; wire cmu1_cru_pd_hssi; wire cmu1_rx_pd_hssi; wire cmu1_tx_pd_hssi; wire cmu1_cgb_pd_hssi; wire cmu1_rx_det_pd_hssi; //---------------------------------- // Other reset outputs //---------------------------------- // SP update 10/17/07 - enpll term removed from hard_reset // assign hard_reset = ~(plniotri & ~entest & npor & (enpll | rnenbpin) & (~pllurst | ~rpllurst)); assign hard_reset = ~(plniotri & ~entest & npor & (~pllurst | ~rpllurst)); assign soft_reset_all_hssi = frzreg | rpowerdown | rreset; assign mdio_rst = ~(plniotri & ~entest & npor); //---------------------------------- // CMU reset internal signals //---------------------------------- assign cmu0_rxpma_rst_hssi = (rxurstcmu[0] & rrxurstcmu[0]) | rreset; assign cmu1_rxpma_rst_hssi = (rxurstcmu[1] & rrxurstcmu[1]) | rreset; //---------------------------------- // CMU reset outputs //---------------------------------- assign cmu0_rxpma_rstb = ~(cmu0_rxpma_rst_hssi | hard_reset); assign cmu0_txpma_rstb = ~(hard_reset | rreset); assign cmu0_cru_rstb = ~(hard_reset | rreset | rrx_cmu_rst[0]); assign cmu1_rxpma_rstb = ~(cmu1_rxpma_rst_hssi | hard_reset); assign cmu1_txpma_rstb = ~(hard_reset | rreset); assign cmu1_cru_rstb = ~(hard_reset | rreset | rrx_cmu_rst[1]); //---------------------------------- // powerdown internal signals //---------------------------------- assign cmu0_cru_pd_hssi = rpowerdown | rcmu_powdnr[0] | ~(rcmu_cru_pdb[0]); assign cmu0_rx_pd_hssi = rpowerdown | rcmu_powdnr[0] | ~(ucmurx_pdb[0] | ~(rcmu_urx_pdb[0])) | ~(rcmu_rx_ib_pdb[0]); assign cmu0_tx_pd_hssi = rpowerdown | rcmu_powdnt[0] | ~(rcmu_tx_ob_pdb[0]); assign cmu0_cgb_pd_hssi = rpowerdown | rcmu_powdnt[0] | ~(rcmu_tx_cgb_pdb[0]); assign cmu0_rx_det_pd_hssi = rpowerdown | rcmu_powdnt[0] | ~(rcmu_rx_det_pdb[0]); assign cmu1_cru_pd_hssi = rpowerdown | rcmu_powdnr[1] | ~(rcmu_cru_pdb[1]); assign cmu1_rx_pd_hssi = rpowerdown | rcmu_powdnr[1] | ~(ucmurx_pdb[1] | ~(rcmu_urx_pdb[1])) | ~(rcmu_rx_ib_pdb[1]); assign cmu1_tx_pd_hssi = rpowerdown | rcmu_powdnt[1] | ~(rcmu_tx_ob_pdb[1]); assign cmu1_cgb_pd_hssi = rpowerdown | rcmu_powdnt[1] | ~(rcmu_tx_cgb_pdb[1]); assign cmu1_rx_det_pd_hssi = rpowerdown | rcmu_powdnt[1] | ~(rcmu_rx_det_pdb[1]); //---------------------------------- // powerdown outputs //---------------------------------- assign cmu0_clk_pdb = rclk_pdb[0]; assign cmu0_cru_pdb = ~(hard_reset | cmu0_cru_pd_hssi); assign cmu0_rx_pdb = ~(hard_reset | cmu0_rx_pd_hssi); assign cmu0_tx_pdb = ~(hard_reset | cmu0_tx_pd_hssi); assign cmu0_cgb_pdb = ~(hard_reset | cmu0_cgb_pd_hssi); assign cmu0_rx_det_pdb = ~(hard_reset | cmu0_rx_det_pd_hssi); assign cmu1_clk_pdb = rclk_pdb[1]; assign cmu1_cru_pdb = ~(hard_reset | cmu1_cru_pd_hssi); assign cmu1_rx_pdb = ~(hard_reset | cmu1_rx_pd_hssi); assign cmu1_tx_pdb = ~(hard_reset | cmu1_tx_pd_hssi); assign cmu1_cgb_pdb = ~(hard_reset | cmu1_cgb_pd_hssi); assign cmu1_rx_det_pdb = ~(hard_reset | cmu1_rx_det_pd_hssi); endmodule `timescale 1 ns / 1 ps module stratixiv_hssi_cmu_auto_speed_neg ( refclk, rxpcs_rst_int, rate, gen2ngen1, config_sel_centrl, config_sel_quad_up, config_sel_quad_down, rindv_rx, rmaster_rx, rmaster_up_rx, rauto_speed_ena, singleorbundle, rphfifo_regmode_rx, rpma_done_count, rauto_deassert_pc_rst_cnt, rauto_pc_en_cnt, rwait_for_phfifo_cnt, config_sel, pcie_switch, speed_change, dis_pc_byte, reset_pc_ptrs, cs ); // Clocks and Resets input refclk; input rxpcs_rst_int; // Input from LTSSM (sideband). high is gen2, low is gen1. input rate; // Input from PMA // PMA indication for change in frequency. transistions one cycle before actually frequency change. high is gen2, low is gen1. input gen2ngen1; // Bundle Mode Inputs for config_sel input config_sel_centrl; input config_sel_quad_up; input config_sel_quad_down; // MDIO input rindv_rx; input rmaster_rx; input rmaster_up_rx; input rauto_speed_ena; input singleorbundle; input rphfifo_regmode_rx; input [17:0] rpma_done_count; input [3:0] rauto_deassert_pc_rst_cnt; input [4:0] rauto_pc_en_cnt; input [5:0] rwait_for_phfifo_cnt; // control signal output for bundle mode high is gen2, low is gen1. output config_sel; // PMA rate change control output pcie_switch; // RX Phase Comp // Handshake signal to PIPE interface to assert PhyStatus output speed_change; // Phase Comp and byte ser/deser control signals output dis_pc_byte; output reset_pc_ptrs; output [3:0] cs; reg config_sel; reg set_config_sel_reg; reg [3:0] cs; reg [3:0] next_state; reg rate_int_reg; reg gen2ngen1_del; reg freq_switch; reg dis_pc_byte; reg reset_pc_ptrs; reg speed_change; reg reset_count; reg count_pma_done; reg count_deassert_rst; reg count_enable_pc; reg rate_sync1_reg; reg rate_sync2_reg; reg [18:0] counter; reg counter_done; reg count_phfifo; wire rate_edge; //============================================================================ // FSM states // //============================================================================ parameter WAIT_RATE_CHANGE = 4'b0000; parameter WAIT_FOR_PHFIFO = 4'b0001; parameter DISABLE_PC_BYTE = 4'b0010; parameter SET_CONFIG_SEL = 4'b0011; parameter WAIT_GEN2NGEN1_CHANGE = 4'b0100; parameter WAIT_PMA_DONE_CNTR = 4'b0101; parameter DEASSERT_PC_PTR_RESET = 4'b0110; parameter WAIT_DEASSERT_RST_CNTR = 4'b0111; parameter ENABLE_PC_BYTE = 4'b1000; parameter WAIT_ENABLE_CNTR = 4'b1001; parameter SPEED_CHANGE_DONE = 4'b1010; //============================================================================ // Multi-use Counter with *2 done flag capablility // //============================================================================ always @ (posedge refclk or posedge rxpcs_rst_int) begin if (rxpcs_rst_int) begin counter <= #1 19'h00000; counter_done <= #1 1'b0; end else if (reset_count) begin counter <= #1 19'h00000; counter_done <= #1 1'b0; end else begin counter <= #1 counter + 19'h00001; if (~counter_done) begin if(count_pma_done) begin counter_done <= #1 (((counter[18:1] == rpma_done_count[17:0]) && gen2ngen1 && counter[0] == 1) || ((counter[17:0] == rpma_done_count[17:0]) && ~gen2ngen1)) ? 1'b1 : 1'b0; end else if (count_deassert_rst) begin counter_done <= #1 (((counter[4:1] == rauto_deassert_pc_rst_cnt[3:0]) && gen2ngen1 && counter[0] == 1) || ((counter[3:0] == rauto_deassert_pc_rst_cnt[3:0]) && ~gen2ngen1)) ? 1'b1 : 1'b0; end else if (count_enable_pc) begin counter_done <= #1 (((counter[5:1] == rauto_pc_en_cnt[4:0]) && gen2ngen1 && counter[0] == 1) || ((counter[4:0] == rauto_pc_en_cnt[4:0]) && ~gen2ngen1)) ? 1'b1 : 1'b0; end else if (count_phfifo) begin counter_done <= #1 (((counter[6:1] == rwait_for_phfifo_cnt[5:0]) && gen2ngen1 && counter[0] == 1) || ((counter[5:0] == rwait_for_phfifo_cnt[5:0]) && ~gen2ngen1)) ? 1'b1 : 1'b0; end end // if (~count_pma_done) end end // always @ (posedge clk or posedge reset) //============================================================================ // Control signal output logic // //============================================================================ assign pcie_switch = (rmaster_rx) ? (rindv_rx ? config_sel : config_sel_centrl) : (rmaster_up_rx ? config_sel_quad_up : config_sel_quad_down); //============================================================================ // Synchronization, Input & Output Logic // //============================================================================ always @ (posedge refclk or posedge rxpcs_rst_int) begin if (rxpcs_rst_int) begin rate_sync1_reg <= #1 1'b0; rate_sync2_reg <= #1 1'b0; rate_int_reg <= #1 1'b0; end else begin rate_sync1_reg <= #1 rate; rate_sync2_reg <= #1 rate_sync1_reg; rate_int_reg <= #1 rate_sync2_reg; end end // always @ (posedge refclk or posedge reset) assign rate_edge = (rate_sync2_reg != rate_int_reg) ? 1'b1 : 1'b0; // convert gen2ngen1 to freq_switch always @ (posedge refclk or posedge rxpcs_rst_int) begin if (rxpcs_rst_int) begin gen2ngen1_del <= #1 1'b0; freq_switch <= #1 1'b0; end else begin gen2ngen1_del <= #1 gen2ngen1; freq_switch <= #1 (gen2ngen1_del != gen2ngen1) ? 1'b1 : 1'b0; end end // always @ (posedge refclk or posedge reset) // config_sel always @ (posedge refclk or posedge rxpcs_rst_int) begin if (rxpcs_rst_int) begin config_sel <= #1 1'b0; end else if (set_config_sel_reg) begin config_sel <= #1 rate_sync2_reg; end end // always @ (posedge refclk or posedge reset) //============================================================================ // Auto Speed Negotiation State Machine // //============================================================================ // always @ (posedge refclk or posedge rxpcs_rst_int) begin if (rxpcs_rst_int) begin cs <= #1 WAIT_RATE_CHANGE; end else begin cs <= #1 next_state; end end // always @ (posedge refclk or posedge reset) always @ (cs or rate_edge or rauto_speed_ena or rphfifo_regmode_rx or freq_switch or counter_done or singleorbundle) begin next_state = cs; dis_pc_byte = 1'b0; reset_pc_ptrs = 1'b0; set_config_sel_reg = 1'b0; speed_change = 1'b0; reset_count = 1'b1; count_pma_done = 1'b0; count_deassert_rst = 1'b0; count_enable_pc = 1'b0; count_phfifo = 1'b0; case (cs) WAIT_RATE_CHANGE: begin if (rate_edge && rauto_speed_ena && singleorbundle) begin if(~rphfifo_regmode_rx) next_state = WAIT_FOR_PHFIFO; else next_state = SET_CONFIG_SEL; end end // case: WAIT_RATE_CHANGE WAIT_FOR_PHFIFO: begin reset_count = 1'b0; count_phfifo = 1'b1; if(counter_done) next_state = DISABLE_PC_BYTE; end DISABLE_PC_BYTE: begin dis_pc_byte = 1'b1; reset_pc_ptrs = 1'b1; speed_change = 1'b1; next_state = SET_CONFIG_SEL; end // case: DISABLE_PC_BYTE SET_CONFIG_SEL: begin dis_pc_byte = 1'b1; reset_pc_ptrs = 1'b1; set_config_sel_reg = 1'b1; speed_change = 1'b1; next_state = WAIT_GEN2NGEN1_CHANGE; end // case: SET_CONFIG_SEL WAIT_GEN2NGEN1_CHANGE: begin dis_pc_byte = 1'b1; reset_pc_ptrs = 1'b1; speed_change = 1'b1; if (freq_switch) next_state = WAIT_PMA_DONE_CNTR; end // case: WAIT_GEN2NGEN1_CHANGE WAIT_PMA_DONE_CNTR: begin dis_pc_byte = 1'b1; reset_pc_ptrs = 1'b1; speed_change = 1'b1; reset_count = 1'b0; count_pma_done = 1'b1; if (counter_done) begin if (~rphfifo_regmode_rx) next_state = DEASSERT_PC_PTR_RESET; else next_state = SPEED_CHANGE_DONE; end end // case: WAIT_PMA_DONE_CNTR DEASSERT_PC_PTR_RESET: begin dis_pc_byte = 1'b1; speed_change = 1'b1; next_state = WAIT_DEASSERT_RST_CNTR; end WAIT_DEASSERT_RST_CNTR: begin dis_pc_byte = 1'b1; speed_change = 1'b1; reset_count = 1'b0; count_deassert_rst = 1'b1; if (counter_done) next_state = ENABLE_PC_BYTE; end // case: WAIT_DEASSERT_RST_CNTR ENABLE_PC_BYTE: begin speed_change = 1'b1; next_state = WAIT_ENABLE_CNTR; end WAIT_ENABLE_CNTR: begin speed_change = 1'b1; reset_count = 1'b0; count_enable_pc = 1'b1; if (counter_done) next_state = SPEED_CHANGE_DONE; end SPEED_CHANGE_DONE: begin next_state = WAIT_RATE_CHANGE; end default: begin dis_pc_byte = 1'b0; reset_pc_ptrs = 1'b0; set_config_sel_reg = 1'b0; speed_change = 1'b0; reset_count = 1'b1; count_pma_done = 1'b0; count_deassert_rst = 1'b0; count_enable_pc = 1'b0; next_state = WAIT_RATE_CHANGE; end // case: default endcase // case(cs) end // always @ (cs or rate_edge or rauto_speed_ena or rphfifo_regmode_rx or freq_switch or counter_done) endmodule // auto_speed_neg_centrl `timescale 1 ps / 1 ps module stratixiv_hssi_cmu_clk_gating ( select_n, clk1, clk2, clk1out_n, clk2out_n ); input select_n; input clk1; input clk2; output clk1out_n; output clk2out_n; assign clk1out_n = ~(select_n | clk1); assign clk2out_n = ~(~select_n | clk2); endmodule // centrl_clk_gating `timescale 1 ns /1 ps module stratixiv_hssi_cmu_clk_ctl (pclk_pma, refclk_dig, mdc, ser_clk, ser_mode, scan_mode, scan_clk, rfreerun_centrl, rcentrl_clk_sel, rrefclk_out_div2, hard_reset, txrst, refclk_pma_out, mdc_b, refclk_out, rauto_speed_ena, rfreq_sel, gen2ngen1_bundle ); input pclk_pma; // x4 PCLK from PMA CMU input refclk_dig; // External digital clock input mdc; // MDIO input clock input ser_clk; // Serial clock input ser_mode; // Serial shift configuration mode input scan_mode; // Scan mode input scan_clk; // Scan mode input rfreerun_centrl; // REFCLK_OUT free running enable CRAM input rcentrl_clk_sel; // REFCLK_PMA global clock selection CRAM input rrefclk_out_div2; // REFCLK_OUT divide by 2 enable CRAM input hard_reset; // Hard reset input input txrst; input rauto_speed_ena; input rfreq_sel; input gen2ngen1_bundle; output refclk_pma_out; // Global TX PCS clock output mdc_b; // Configuration output clock output refclk_out; // REFCLK_OUT output clk wire refclk_pma_int, refclk_out_div2_inv, hard_reset_n; reg refclk_out_div2; reg gen2ngen1_local_sync; wire dynamic_div2ndiv1; wire clk1out_n; wire clk2out_n; // shawn initial begin ------ initial begin refclk_out_div2 = 1'b1; end // shawn initial end ------ // The following assignments need to be replaced with clock buffers // instantiation when the technology is identified later // refclk_pma clock selection assign refclk_pma_int = (rcentrl_clk_sel) ? refclk_dig : pclk_pma; assign refclk_pma_out = (scan_mode) ? scan_clk : refclk_pma_int; // refclk_out logic // This register is used to generate divided by two clock. Div by 2 clock starts off high after reset assign refclk_out_div2_inv = (rauto_speed_ena & ~rfreq_sel) ? (~refclk_out_div2 | ~gen2ngen1_local_sync) : ~refclk_out_div2; assign hard_reset_n = rfreerun_centrl ? 1'b1 : ~hard_reset; always @(negedge hard_reset_n or posedge refclk_pma_out) begin if (~hard_reset_n) refclk_out_div2 <= 1'b1; else refclk_out_div2 <= refclk_out_div2_inv; end always @(posedge txrst or posedge refclk_pma_out) begin if (txrst) gen2ngen1_local_sync <= #1 1'b0; else gen2ngen1_local_sync <= #1 gen2ngen1_bundle; end assign dynamic_div2ndiv1 = rrefclk_out_div2 | (gen2ngen1_local_sync & rauto_speed_ena & ~rfreq_sel); stratixiv_hssi_cmu_clk_gating centrl_clk_gating ( .select_n(dynamic_div2ndiv1), .clk1(refclk_pma_out), .clk2(refclk_out_div2), .clk1out_n(clk1out_n), .clk2out_n(clk2out_n) ); assign refclk_out = ~(clk1out_n | clk2out_n); // mdc_b clock logic assign mdc_b = ({scan_mode, ser_mode} == 2'b11) ? refclk_pma_out : ({scan_mode, ser_mode} == 2'b10) ? refclk_pma_out : ({scan_mode, ser_mode} == 2'b01) ? ser_clk : ({scan_mode, ser_mode} == 2'b00) ? mdc : mdc; endmodule // centrl_clk_ctl module stratixiv_hssi_cmu_rx_ctrl (soft_reset, clk_2, rx_rd_clk, rx_wr_clk, scan_mode, rrxfifo_urst_en, rxfifo_urst, rrxphfifopldctl_en, pld_wr_dis, pld_re, dis_pc_byte, rauto_speed_ena, rx_we_out, wr_enable_out, rd_enable_out ); // ======= // inputs // ======= input soft_reset; input clk_2; input rx_rd_clk; // This replaces PLD_RX_CLK input rx_wr_clk; // divided by 1 or 2 write clock. input scan_mode; // scan enable input rrxfifo_urst_en; // Enable rxfifo_urst input rxfifo_urst; // User reset exclusive to rx_ctrl & below input rrxphfifopldctl_en; // CRAM to enable PLD controlled write/read enable input pld_wr_dis; // PLD write disable input pld_re; // PLD read eanble input dis_pc_byte; // New MDIO for new bundling scheme and new PCIE features like autospeed input rauto_speed_ena; // ======= // outputs // ======= output rx_we_out; output wr_enable_out; output rd_enable_out; // reset signals wire rrxfifo_urst_en; wire local_soft_reset; // OR of local & global resets. reg soft_reset_wclk0; reg soft_reset_wclk1_b4scan; wire soft_reset_wclk1; // reset for fifo_wr_clk reg soft_reset_rclk0; reg soft_reset_rclk1_b4scan; wire soft_reset_rclk1; // reset for pld_rx_clk reg rx_we_out; // Channel zero output should all channel rx_we_in of rx_ctrl reg rd_enable0; reg rd_enable0p5; reg rd_enable1; reg pld_wr_dis0; reg pld_wr_dis1; reg pld_wr_dis2; reg pld_wr_dis_edge; reg wr_enable0; reg wr_enable0p5; reg wr_enable1; reg wr_enable2; reg rxfifo_en_clk2_0; reg rxfifo_en_clk2_1; reg wr_enable_clk2; assign local_soft_reset = soft_reset | (rrxfifo_urst_en && rxfifo_urst) ; assign wr_enable_out = wr_enable1; assign rd_enable_out = rd_enable1; // generate rx_wr_clk reset always@(posedge local_soft_reset or posedge rx_wr_clk) begin if (local_soft_reset) begin soft_reset_wclk0 <= #1 1'b1; soft_reset_wclk1_b4scan <= #1 1'b1; end else begin soft_reset_wclk0 <= #1 1'b0; soft_reset_wclk1_b4scan <= #1 soft_reset_wclk0; end end assign soft_reset_wclk1 = (scan_mode)? 1'b0 : soft_reset_wclk1_b4scan; // generate pld_rx_clk reset always@(posedge local_soft_reset or posedge rx_rd_clk) begin if (local_soft_reset) begin soft_reset_rclk0 <= #1 1'b1; soft_reset_rclk1_b4scan <= #1 1'b1; end else begin soft_reset_rclk0 <= #1 1'b0; soft_reset_rclk1_b4scan <= #1 soft_reset_rclk0; end end assign soft_reset_rclk1 = (scan_mode)? 1'b0 : soft_reset_rclk1_b4scan; // write enable, fifo data in always @(posedge rx_wr_clk or posedge soft_reset_wclk1) begin if (soft_reset_wclk1) begin pld_wr_dis0 <= #1 1'b0; pld_wr_dis1 <= #1 1'b0; pld_wr_dis2 <= #1 1'b0; pld_wr_dis_edge <= #1 1'b0; wr_enable0 <= #1 1'b0; wr_enable0p5 <= #1 1'b0; wr_enable1 <= #1 1'b0; wr_enable2 <= #1 1'b0; end else begin pld_wr_dis0 <= #1 pld_wr_dis; pld_wr_dis1 <= #1 pld_wr_dis0; pld_wr_dis2 <= #1 pld_wr_dis1; pld_wr_dis_edge <= #1 (pld_wr_dis2 != pld_wr_dis1); wr_enable0 <= #1 ~(rauto_speed_ena & dis_pc_byte); wr_enable0p5 <= #1 wr_enable0; wr_enable1 <= #1 (rrxphfifopldctl_en)? (wr_enable0p5 & !pld_wr_dis_edge) : wr_enable0p5; wr_enable2 <= #1 wr_enable1; end end // read enable always @(posedge rx_rd_clk or posedge soft_reset_rclk1) begin if (soft_reset_rclk1 == 1'b1) begin rd_enable0 <= #1 1'b0; rd_enable0p5 <= #1 1'b0; rd_enable1 <= #1 1'b0; end else begin rd_enable0 <= #1 ~(rauto_speed_ena & dis_pc_byte); rd_enable0p5 <= #1 rd_enable0; rd_enable1 <= #1 (rrxphfifopldctl_en)? (rd_enable0p5 && pld_re) : rd_enable0p5; end end // byte de-serializer high/low select always @(posedge clk_2 or posedge soft_reset) begin if (soft_reset) begin rx_we_out <= #1 1'b1; rxfifo_en_clk2_0 <= #1 1'b0; rxfifo_en_clk2_1 <= #1 1'b0; wr_enable_clk2 <= #1 1'b0; end else begin //rxfifo_en_clk2_0 <= rxfifo_en; // rxfifo_en_clk2_0 <= 1'b1; rxfifo_en_clk2_0 <= #1 ~(rauto_speed_ena & dis_pc_byte); rxfifo_en_clk2_1 <= #1 rxfifo_en_clk2_0; if (rxfifo_en_clk2_1 == 1'b0) wr_enable_clk2 <= #1 1'b0; else if (wr_enable_clk2 == 1'b0) wr_enable_clk2 <= #1 wr_enable2; if (wr_enable_clk2 == 1'b1) rx_we_out <= #1 ~rx_we_out; else rx_we_out <= #1 1'b0; end end endmodule // rx_ctrl_centrl `timescale 1 ps /1 ps module stratixiv_hssi_cmu_rxclk_gating ( select_n, clk1, clk2, clk1out_n, clk2out_n ); input select_n; input clk1; input clk2; output clk1out_n; output clk2out_n; assign clk1out_n = ~(select_n | clk1); assign clk2out_n = ~(~select_n | clk2); endmodule `timescale 1 ps /1 ps module stratixiv_hssi_cmu_rxclk_ctl (pld_rx_clk, rcvd_clk_pma, rcvd_clk0_pma, tx_pma_clk, refclk_pma, fref, clklow, scan_mode, gen2ngen1, gen2ngen1_bundle, rx_div2_sync_centrl, rx_div2_sync_quad_up, rx_div2_sync_quad_down, rrcvd_clk_sel, rclk_1_sel, rclk_2_sel, rrx_rd_clk_sel, rxrst, rindv_rx, rdwidth_rx, rfreerun_rx, rauto_speed_ena, rfreq_sel, rrxpcsclkpwdn, rmaster_rx, rmaster_up_rx, rself_sw_en_rx, fref_muxed, clklow_muxed, rcvd_clk, clk_1_b, clk_2_b, rx_wr_clk, rx_rd_clk, rx_clk, rcvd_clk_pma_b, clk_2_b_raw, rx_wr_clk_raw, rx_rd_clk_raw, rx_div2_sync_out ); // Clock Inputs input pld_rx_clk; // PLD clock from PLD clock trees input rcvd_clk_pma; // local recovered clock input rcvd_clk0_pma; // channel zero recovered clock input tx_pma_clk; // local TX PMA clock input refclk_pma; // Quad based clk from TXPLL input fref; input clklow; // Control Inputs input scan_mode; // Scan mode enable signal input rxrst; // This is the soft_reset for the RX_PCS // New Control Inputs input gen2ngen1; // from PMA for PCIexp Gen1/Gen2 datawidth scaling input gen2ngen1_bundle; // from PMA for PCIexp Gen1/Gen2 datawidth scaling in x4 and x8 input rx_div2_sync_centrl; // divided clock from the central channel (x2, x4 mode) input rx_div2_sync_quad_up; // divided clock from quad above (> x4 mode) input rx_div2_sync_quad_down; // divided clock from quad below (> x4 mode) // MDIO Inputs input [1:0] rrcvd_clk_sel; input [1:0] rclk_1_sel; input [1:0] rclk_2_sel; input rrx_rd_clk_sel; // Select clock for rx ph comp fifo read side input rindv_rx; // Select between XAUI mode or indiv channel mode input rdwidth_rx; // divide by 1 or 2 before feeding to FIFO write clock input rfreerun_rx; // Select whether divider is permamently enabled (free -running) or divider should be enabled / reset by RX PCS reset // New MDIO Inputs input rauto_speed_ena; // auto speed negotiation enable input rfreq_sel; // freq scaling or data width scaling input rrxpcsclkpwdn; // RX clocking power down enable input rmaster_rx; // New bundle mode MDIO, selects master quad input rmaster_up_rx; // New bundle mode MDIO, selects master quad input rself_sw_en_rx; // enables self-switch to have correct /2 clock in all quads in bundle mode // Removed Inputs // input rphfifo_master_sel_rx; // RX Phase comp. FIFO rx_div2_sync selection CRAM // input rx_div2_sync_in_ch0; // Connect from channel zero rx_div2_sync_out // input rx_div2_sync_in_q0_ch0; // Connect from channel zero rx_div2_sync_out of Master Quad // Clock Outputs with CTS output fref_muxed; output clklow_muxed; output rcvd_clk; output clk_1_b; output clk_2_b; output rx_wr_clk; // drives the rx ph comp fifo write clock tree output rx_rd_clk; // drives the rx ph comp fifo read clock tree // Clock Outputs to PLD, no CTS output rx_clk; // drives the PLD clock tree in x1 mode, logically same as rx_wr_clk output rcvd_clk_pma_b; // debug output clock to PLD // New Clock Outputs with CTS output clk_2_b_raw; // same as clk_2_b, but with no clock gating output rx_wr_clk_raw; // same as rx_wr_clk, but with no clock gating output rx_rd_clk_raw; // same as rx_rd_clk, but with no clock gating // Control Outputs output rx_div2_sync_out; // inverted /2 clock. not used w/new bundling scheme. (left for safety) reg rx_clk_2_by2; reg gen2ngen1_local_sync; reg [1:0] counter; wire rx_div2_sync; wire rx_div2_sync_out; wire rx_rst_n; wire [1:0] rrcvd_clk_sel_int; wire [1:0] rclk_1_sel_int; wire [1:0] rclk_2_sel_int; wire dynamic_div2ndiv1; wire gen2ngen1_local; wire fref_muxed; wire clklow_muxed; wire rrxpcsclkpwdn_nscan; wire rx_div2_this_quad; wire rx_div2_this_channel; wire rx_div2_other_quad; wire force_master; wire select_div1_n; wire clk1out_n; wire clk2out_n; // shawn initial begin ------ initial begin rx_clk_2_by2 = 1'b1; end // shawn initial end ------ // Old bundle logic: // Select between the local synchronization signal or the global synchronization signal //assign rx_div2_sync = rindv_rx ? rx_div2_sync_out : rx_div2_sync_in; // assign rx_div2_sync = (rphfifo_master_sel_rx == 1'b0) ? rx_div2_sync_in_q0_ch0 : // (rindv_rx == 1'b0) ? rx_div2_sync_in_ch0 : // (rauto_speed_ena & ~rfreq_sel) ? (rx_div2_sync_out | ~gen2ngen1_local_sync) : rx_div2_sync_out; always @(posedge rxrst or posedge clk_2_b_raw) begin if (rxrst) counter <= #1 2'b00; else if ((rauto_speed_ena & ~rfreq_sel & rself_sw_en_rx) & ~force_master) counter <= #1 counter + 1'b1; end assign force_master = ((counter == 2'b11) & (rauto_speed_ena & ~rfreq_sel & rself_sw_en_rx)) ? 1'b1 : 1'b0; assign rx_div2_sync = (rmaster_rx | force_master) ? rx_div2_this_quad : rx_div2_other_quad; assign rx_div2_this_quad = (rindv_rx | force_master) ? rx_div2_this_channel : rx_div2_sync_centrl; assign rx_div2_this_channel = (rauto_speed_ena & ~rfreq_sel) ? (rx_div2_sync_out | ~gen2ngen1_local_sync) : rx_div2_sync_out; assign rx_div2_other_quad = rmaster_up_rx ? rx_div2_sync_quad_up : rx_div2_sync_quad_down; assign gen2ngen1_local = (rindv_rx == 1'b0) ? gen2ngen1_bundle : gen2ngen1; always @(posedge rxrst or posedge clk_2_b_raw) begin if (rxrst) gen2ngen1_local_sync <= #1 1'b0; else gen2ngen1_local_sync <= #1 gen2ngen1_local; end assign dynamic_div2ndiv1 = rdwidth_rx | (gen2ngen1_local_sync & rauto_speed_ena & ~rfreq_sel); // Reset for Divide-by-2 FF and synchronization FF's for clock gating assign rx_rst_n = (rfreerun_rx) ? 1'b1 : ~rxrst; assign rrxpcsclkpwdn_nscan = rrxpcsclkpwdn & ~scan_mode; // clocks are assigned below in the order in which they appear in the out flowing data path // RCVD_CLK selection assign rrcvd_clk_sel_int = (scan_mode) ? 2'b01 : rrcvd_clk_sel; assign rcvd_clk = rrxpcsclkpwdn_nscan ? 1'b1 : (rrcvd_clk_sel_int == 2'b00) ? rcvd_clk_pma : (rrcvd_clk_sel_int == 2'b01) ? refclk_pma : (rrcvd_clk_sel_int == 2'b10) ? tx_pma_clk : (rrcvd_clk_sel_int == 2'b11) ? rcvd_clk_pma : rcvd_clk_pma; // CLK_1 seleciton assign rclk_1_sel_int = (scan_mode) ? 2'b01 : rclk_1_sel; assign clk_1_b = rrxpcsclkpwdn_nscan ? 1'b1 : (rclk_1_sel_int == 2'b00) ? rcvd_clk_pma : (rclk_1_sel_int == 2'b01) ? refclk_pma : (rclk_1_sel_int == 2'b10) ? tx_pma_clk : (rclk_1_sel_int == 2'b11) ? rcvd_clk0_pma : rcvd_clk_pma; // CLK_2 selection assign rclk_2_sel_int = (scan_mode) ? 2'b10 : rclk_2_sel; assign clk_2_b_raw = (rclk_2_sel_int == 2'b00) ? rcvd_clk_pma : (rclk_2_sel_int == 2'b01) ? tx_pma_clk : (rclk_2_sel_int == 2'b10) ? refclk_pma : rcvd_clk_pma; //change made for S3GX to remove pld_rx_clk from mux input //(rclk_2_sel_int == 2'b10) ? refclk_pma : //(rclk_2_sel_int == 2'b11) ? pld_rx_clk : rcvd_clk_pma; assign clk_2_b = rrxpcsclkpwdn_nscan ? 1'b1 : clk_2_b_raw; // This register is used to generate divided by two clock. Div by 2 clock starts off high after reset // No #1 on this FF as it generates a clock always @(negedge rx_rst_n or posedge clk_2_b_raw) begin if (~rx_rst_n) rx_clk_2_by2 <= 1'b1; else rx_clk_2_by2 <= rx_div2_sync; end assign rx_div2_sync_out = ~rx_clk_2_by2; // RX FIFO write clock: could be fast or divided by 2 // old code: // assign rx_wr_clk = ((rdwidth_rx == 1'b0) || scan_mode) ? clk_2_b_raw : rx_clk_2_by2; assign select_div1_n = ~(scan_mode | ~dynamic_div2ndiv1); stratixiv_hssi_cmu_rxclk_gating rxclk_gating ( .select_n(select_div1_n), .clk1(clk_2_b_raw), .clk2(rx_clk_2_by2), .clk1out_n(clk1out_n), .clk2out_n(clk2out_n) ); assign rx_wr_clk_raw = ~(clk1out_n | clk2out_n); assign rx_wr_clk = rrxpcsclkpwdn_nscan ? 1'b1 : rx_wr_clk_raw; // RX FIFO read clock assign rx_rd_clk_raw = (scan_mode | (rrx_rd_clk_sel == 1'b0)) ? rx_wr_clk_raw : pld_rx_clk; assign rx_rd_clk = rrxpcsclkpwdn_nscan ? 1'b1 : rx_rd_clk_raw; // RX clock out assign rx_clk = rx_wr_clk; // drives PLD clock tree // Recovered clock for debugging assign rcvd_clk_pma_b = rcvd_clk_pma; // Goes out to PLD as debug clock. This clock may or may not be routed out to PLD fabric. TBD assign fref_muxed = scan_mode ? refclk_pma : rrxpcsclkpwdn ? 1'b1 : fref; assign clklow_muxed = scan_mode ? refclk_pma : rrxpcsclkpwdn ? 1'b1 : clklow; endmodule // rxclk_ctl_centrl module stratixiv_hssi_cmu_tx_ctrl (soft_reset, fifo_wr_clk, fifo_rd_clk, refclk_b_in, scan_mode, rtxfifo_urst_en, txfifo_urst, rtxphfifopldctl_en, pld_we, pld_rd_dis, dis_pc_byte, rauto_speed_ena, wr_enable_out, rd_enable_out, fifo_select_out ); // ====== // inputs // ====== input soft_reset; // Reset input fifo_wr_clk; // Used to be wr_clk_pos input fifo_rd_clk; // Coming from txclk_xg_ctl input refclk_b_in; // The local reference clock used by the internal input scan_mode; // scan enable input rtxfifo_urst_en; // user reset CRAM enable input txfifo_urst; // user reset input rtxphfifopldctl_en; // CRAM to enable PLD controlled write/read enable input pld_we; // PLD phase comp. fifo we, level active input pld_rd_dis; // PLD phase comp. fifo rd dis, edge active input dis_pc_byte; // New MDIO for new bundling scheme and new PCIE features like autospeed input rauto_speed_ena; // ======= // outputs // ======= output wr_enable_out; // ch0 wr_enable1 output for X4/X8 mode output rd_enable_out; // ch0 rd_enable1 output for X4/X8 mode output fifo_select_out; // New output for Rev.B reg fifo_select_out; reg wr_enable0; reg wr_enable0p5; reg wr_enable1; reg rd_enable0; reg rd_enable0p5; reg rd_enable1; reg rd_enable2; wire soft_reset_local; reg soft_reset_wclk0; reg soft_reset_wclk1_b4scan; wire soft_reset_wclk1; reg soft_reset_rclk0; reg soft_reset_rclk1_b4scan; wire soft_reset_rclk1; reg pld_rd_dis0, pld_rd_dis1, pld_rd_dis2, pld_rd_dis_edge; reg txfifo_en_refclk0; reg txfifo_en_refclk1; reg rd_enable_sync_refclk_b_in; assign wr_enable_out = wr_enable1; assign rd_enable_out = rd_enable1; assign soft_reset_local = soft_reset | (rtxfifo_urst_en && txfifo_urst); // synchronize reset input (in refclk_b domain) always @(posedge soft_reset_local or posedge fifo_wr_clk) begin if (soft_reset_local) begin soft_reset_wclk0 <= #1 1'b1; soft_reset_wclk1_b4scan <= #1 1'b1; end else begin soft_reset_wclk0 <= #1 1'b0; soft_reset_wclk1_b4scan <= #1 soft_reset_wclk0; end end // always @ (posedge soft_reset_local or posedge fifo_wr_clk) assign soft_reset_wclk1 = (scan_mode)? 1'b0 : soft_reset_wclk1_b4scan; // synchronize reset input (in refclk_b domain) and balance it with fifo_wr_clk reset always @(posedge soft_reset_local or posedge fifo_rd_clk) begin if (soft_reset_local) begin soft_reset_rclk0 <= #1 1'b1; soft_reset_rclk1_b4scan <= #1 1'b1; end else begin soft_reset_rclk0 <= #1 1'b0; soft_reset_rclk1_b4scan <= #1 soft_reset_rclk0; end end // always @ (posedge soft_reset_local or posedge fifo_rd_clk) assign soft_reset_rclk1 = (scan_mode)? 1'b0 : soft_reset_rclk1_b4scan; // write enable always @ (posedge soft_reset_wclk1 or posedge fifo_wr_clk) begin if (soft_reset_wclk1) begin wr_enable0 <= #1 1'b0; wr_enable0p5 <= #1 1'b0; wr_enable1 <= #1 1'b0; end else begin wr_enable0 <= #1 ~(rauto_speed_ena & dis_pc_byte); wr_enable0p5 <= #1 wr_enable0; wr_enable1 <= #1 (rtxphfifopldctl_en)? (wr_enable0p5 && pld_we) : wr_enable0p5; end end // always @ (posedge soft_reset_wclk1 or posedge fifo_wr_clk) // read enable & // read enable sync (for byte serializer output enable) always @(posedge soft_reset_rclk1 or posedge fifo_rd_clk) begin if (soft_reset_rclk1) begin pld_rd_dis0 <= #1 1'b0; pld_rd_dis1 <= #1 1'b0; pld_rd_dis2 <= #1 1'b0; pld_rd_dis_edge <= #1 1'b0; rd_enable0 <= #1 1'b0; rd_enable0p5 <= #1 1'b0; rd_enable1 <= #1 1'b0; rd_enable2 <= #1 1'b0; end else begin pld_rd_dis0 <= #1 pld_rd_dis; pld_rd_dis1 <= #1 pld_rd_dis0; pld_rd_dis2 <= #1 pld_rd_dis1; pld_rd_dis_edge <= #1 (pld_rd_dis2 != pld_rd_dis1); rd_enable0 <= #1 ~(rauto_speed_ena & dis_pc_byte); rd_enable0p5 <= #1 rd_enable0; rd_enable1 <= #1 (rtxphfifopldctl_en)? (rd_enable0p5 && !pld_rd_dis_edge) : rd_enable0p5; rd_enable2 <= #1 rd_enable1; end end // always @ (posedge soft_reset_rclk1 or posedge fifo_rd_clk) // byte serializer high/low select always @(posedge soft_reset or posedge refclk_b_in) begin if (soft_reset) begin rd_enable_sync_refclk_b_in <= #1 1'b0; txfifo_en_refclk0 <= #1 1'b0; txfifo_en_refclk1 <= #1 1'b0; fifo_select_out <= #1 1'b0; end else begin txfifo_en_refclk0 <= #1 ~(rauto_speed_ena & dis_pc_byte); txfifo_en_refclk1 <= #1 txfifo_en_refclk0; if (txfifo_en_refclk1 ==1'b0) rd_enable_sync_refclk_b_in <= #1 1'b0; else if (rd_enable_sync_refclk_b_in == 1'b0) rd_enable_sync_refclk_b_in <= #1 rd_enable2; if (rd_enable_sync_refclk_b_in == 1'b1) fifo_select_out <= #1 ~fifo_select_out; else fifo_select_out <= #1 1'b0; end end // always @ (posedge soft_reset or posedge refclk_b_in) endmodule // tx_ctrl_centrl module stratixiv_hssi_cmu_txclk_gating ( select_n, clk1, clk2, clk1out_n, clk2out_n ); input select_n; input clk1; input clk2; output clk1out_n; output clk2out_n; assign clk1out_n = ~(select_n | clk1); assign clk2out_n = ~(~select_n | clk2); endmodule // txclk_gating_centrl `timescale 1 ns / 1 ps module stratixiv_hssi_cmu_txclk_ctl (pld_tx_clk, refclk_pma, txpma_local_clk, txrst, scan_mode, gen2ngen1, gen2ngen1_bundle, tx_div2_sync_centrl, tx_div2_sync_quad_up, tx_div2_sync_quad_down, rindv_tx, rtxwrclksel, rtxrdclksel, rdwidth_tx, rfreerun_tx, rauto_speed_ena, rfreq_sel, rtxpcsclkpwdn, rmaster_tx, rmaster_up_tx, rself_sw_en_tx, refclk_b, wr_clk_pos, fifo_rd_clk, tx_clk_out, refclk_b_raw, wr_clk_pos_raw, fifo_rd_clk_raw, tx_div2_sync_out ); // Clock Inputs input pld_tx_clk; // PLD clock from PLD clock trees, the transmit clock from XGMII. input refclk_pma; // Quad based clk from TXPLL input txpma_local_clk; // Local channel TX PMA clock. // Control Inputs input txrst; // reset for the tx_pcs input scan_mode; // Scan mode enable signal for selecting scan_clk from refclk_pma // New Control Inputs input gen2ngen1; // from PMA for PCIexp Gen1/Gen2 datawidth scaling input gen2ngen1_bundle; // from PMA for PCIexp Gen1/Gen2 datawidth scaling in x4 and x8 input tx_div2_sync_centrl; // divided clock from the central channel (x2, x4 mode) input tx_div2_sync_quad_up; // divided clock from quad above (> x4 mode) input tx_div2_sync_quad_down; // divided clock from quad below (> x4 mode) // MDIO Inputs input rindv_tx; // Selects between indiv chan. mode and bundled mode input rtxwrclksel; // Selects which clock writes into FIFO input rtxrdclksel; // Selects which clock reads from FIFO and also clocks reest of TX logic input rdwidth_tx; // divide by 1 or 2 before feeding to FIFO read clock input rfreerun_tx; // Select whether divider is permamently enabled (free -running) or divider should be enabled / reset by TX PCS reset // New MDIO Inputs input rauto_speed_ena; // auto speed negotiation enable input rfreq_sel; // freq scaling or data width scaling input rtxpcsclkpwdn; // TX clocking power down enable input rmaster_tx; // New bundle mode MDIO, selects master quad input rmaster_up_tx; // New bundle mode MDIO, selects master quad input rself_sw_en_tx; // enables self-switch to have correct /2 clock in all quads in bundle mode // Removed Inputs // input tx_div2_sync_in_ch0; // from the channel zero tx_div2_sync_out // input tx_div2_sync_in_q0_ch0; // From channel0 of Master Quad // input rphfifo_master_sel_tx; // TX Phase comp. FIFO tx_div2_sync selection CRAM // Clock Outputs wtih CTS output refclk_b; // Drives the tx channel clock output wr_clk_pos; // Drives tx phase comp fifo write side output fifo_rd_clk; // Drives tx phase comp fifo read side // Clock Outputs to PLD, w/o CTS output tx_clk_out; // Drives to the PLD clock tree -- unconnected // New Clock Outputs with CTS output refclk_b_raw; // same as refclk_b, but with no clock gating output wr_clk_pos_raw; // same as wr_clk_pos, but with no clock gating output fifo_rd_clk_raw; // same as fifo_rd_clk, but with no clock gating // Control Outputs output tx_div2_sync_out; // Synchronizes the divided by two clock reg fifo_rd_clk_by2; reg gen2ngen1_local_sync; reg [1:0] counter; wire tx_rst_n; wire tx_div2_sync; wire dynamic_div2ndiv1; wire gen2ngen1_local; wire tx_div2_this_quad; wire tx_div2_this_channel; wire tx_div2_other_quad; wire force_master; wire rtxpcsclkpwdn_nscan; wire select_div1_n; wire clk1out_n; wire clk2out_n; // shawn initial begin ------ initial begin fifo_rd_clk_by2 = 1'b1; end // shawn initial end ------ // Old bundle logic: // Select between the local synchronization signal or the global synchronization signal (either from Channel0 or // Channel0 of Master Quad //assign tx_div2_sync = rindv_tx ? tx_div2_sync_out : tx_div2_sync_in; // assign tx_div2_sync = (rphfifo_master_sel_tx == 1'b0) ? tx_div2_sync_in_q0_ch0 : // (rindv_tx == 1'b0) ? tx_div2_sync_in_ch0 : // (rauto_speed_ena & ~rfreq_sel) ? (tx_div2_sync_out | ~gen2ngen1_local_sync) : tx_div2_sync_out; // always @(posedge txrst or posedge refclk_b_raw) begin if (txrst) counter <= #1 2'b00; else if ((rauto_speed_ena & ~rfreq_sel & rself_sw_en_tx) & ~force_master) counter <= #1 counter + 1'b1; end assign force_master = ((counter == 2'b11) && (rauto_speed_ena & ~rfreq_sel & rself_sw_en_tx)) ? 1'b1 : 1'b0; assign tx_div2_sync = (rmaster_tx || force_master) ? tx_div2_this_quad : tx_div2_other_quad; assign tx_div2_this_quad = (rindv_tx || force_master) ? tx_div2_this_channel : tx_div2_sync_centrl; assign tx_div2_this_channel = (rauto_speed_ena && ~rfreq_sel) ? (tx_div2_sync_out | ~gen2ngen1_local_sync) : tx_div2_sync_out; assign tx_div2_other_quad = rmaster_up_tx ? tx_div2_sync_quad_up : tx_div2_sync_quad_down; assign gen2ngen1_local = (rindv_tx == 1'b0) ? gen2ngen1_bundle : gen2ngen1; always @(posedge txrst or posedge refclk_b_raw) begin if (txrst) gen2ngen1_local_sync <= #1 1'b0; else gen2ngen1_local_sync <= #1 gen2ngen1_local; end assign dynamic_div2ndiv1 = rdwidth_tx | (gen2ngen1_local_sync & rauto_speed_ena & ~rfreq_sel); // Reset for Divide-by-2 FF assign tx_rst_n = (rfreerun_tx) ? 1'b1 : ~txrst; assign rtxpcsclkpwdn_nscan = rtxpcsclkpwdn & ~scan_mode; // Full speed clock for TX PCS assign refclk_b_raw = (scan_mode || rtxrdclksel) ? refclk_pma : txpma_local_clk; assign refclk_b = rtxpcsclkpwdn_nscan ? 1'b1 : refclk_b_raw; // Divide-by-2 FF always @(negedge tx_rst_n or posedge refclk_b_raw) begin if (~tx_rst_n) fifo_rd_clk_by2 <= 1'b1; else fifo_rd_clk_by2 <= tx_div2_sync; // local divided clock end assign tx_div2_sync_out = ~fifo_rd_clk_by2; // TX FIFO read clock: could be fast or divided by 2 // old code: // assign fifo_rd_clk = ((rdwidth_tx == 1'b0) || scan_mode) ? refclk_b_raw : fifo_rd_clk_by2; assign select_div1_n = ~(scan_mode | ~dynamic_div2ndiv1); stratixiv_hssi_cmu_txclk_gating txclk_gating ( .select_n(select_div1_n), .clk1(refclk_b_raw), .clk2(fifo_rd_clk_by2), .clk1out_n(clk1out_n), .clk2out_n(clk2out_n) ); assign fifo_rd_clk_raw = ~(clk1out_n | clk2out_n); assign fifo_rd_clk = rtxpcsclkpwdn_nscan ? 1'b1 : fifo_rd_clk_raw; // TX FIFO write clock: used internal clock when in BIST or scan or HIP assign wr_clk_pos_raw = (scan_mode || rtxwrclksel) ? fifo_rd_clk_raw : pld_tx_clk; assign wr_clk_pos = rtxpcsclkpwdn_nscan ? 1'b1 : wr_clk_pos_raw; // TX Clock Out assign tx_clk_out = fifo_rd_clk; // drives PLD clock tree endmodule // txclk_ctl_cenrtl `timescale 1 ns / 1 ps module stratixiv_hssi_cmu_dprio_bit (reset, clk, sig_in, ext_in, serial_mode, si, shift, mdio_dis, sig_out, so); input reset; // reset input clk; // clock input sig_in; // signal input input ext_in; // external input port input serial_mode;// serial shift mode enable input si; // scan input input shift; // 1'b1=shift in data from si into scan flop // 1'b0=load data from sig_in into scan flop input mdio_dis; // 1'b1=choose ext_in to the sig_out mux // 1'b0=choose so to the sign_out mux output sig_out; // signal output output so; // scan output wire sig_out; wire cram_int; wire set_int; reg so; // select signal output assign sig_out = (serial_mode) ? (so & ~shift) : (cram_int); assign cram_int = (mdio_dis) ? (ext_in) : (so); // Set signal for the flop assign set_int = (shift | reset) ? 1'b0 : ext_in; // scan flop always @ (posedge reset or posedge set_int or posedge clk) if (reset) so <= 1'b0; else if (set_int) so <= 1'b1; else if (shift && serial_mode) so <= si; else so <= sig_in; endmodule `timescale 1 ns / 1 ps module stratixiv_hssi_cmu_dprio_bit_pma (reset, clk, sig_in, ext_in, serial_mode, si, shift, mdio_dis, pma_cram_test, sig_out, so); input reset; // reset input clk; // clock input sig_in; // signal input input ext_in; // external input port input serial_mode;// serial shift mode enable input si; // scan input input shift; // 1'b1=shift in data from si into scan flop // 1'b0=load data from sig_in into scan flop input mdio_dis; // 1'b1=choose ext_in to the sig_out mux // 1'b0=choose so to the sign_out mux input pma_cram_test; //1'b1: choose the previous output of this register //1'b0: choose either si or input from DPRIO SM (sig_in) output sig_out; // signal output output so; // scan output wire sig_out; wire cram_int; wire set_int; reg so; // select signal output assign sig_out = (serial_mode) ? (so & ~shift) : (cram_int); assign cram_int = (mdio_dis) ? (ext_in) : (so); // Set signal for the flop assign set_int = (shift | reset) ? 1'b0 : ext_in; // scan flop always @ (posedge reset or posedge set_int or posedge clk) if (reset) so <= 1'b0; else if (set_int) so <= 1'b1; else if (pma_cram_test) so <= sig_out; else if (shift && serial_mode) so <= si; else so <= sig_in; endmodule `timescale 1 ns / 1 ps module stratixiv_hssi_cmu_dprio_16bit (reset, mdio_wr, reg_addr, target_addr, clk, sig_in, ext_in, serial_mode, si, shift, mdio_dis, sig_out, so); input reset; // reset input mdio_wr; input [15:0] reg_addr; input [15:0] target_addr; input clk; // clock input [15:0] sig_in; // signal input input [15:0] ext_in; // external port input input serial_mode;// serial shift mode enable input si; // scan input input shift; // 1'b1=shift in data from si into scan flop // 1'b0=load data from sig_in into scan flop input mdio_dis; // // 1'b1=output CRAM // 1'b0=output MDIO control register output [15:0] sig_out; // signal output output so; // scan output wire [15:0] signal_in_int; wire [15:0] sig_out; wire [14:0] chain; wire so; assign signal_in_int = (mdio_wr && (reg_addr == target_addr)) ? sig_in : {so, chain}; stratixiv_hssi_cmu_dprio_bit ctrl_reg_bit_0 (.reset (reset), .clk (clk), .sig_in (signal_in_int[0]), .ext_in (ext_in[0]), .serial_mode (serial_mode), .si (si), .shift (shift), .mdio_dis (mdio_dis), .sig_out (sig_out[0]), .so (chain[0])); stratixiv_hssi_cmu_dprio_bit ctrl_reg_bit_1 (.reset (reset), .clk (clk), .sig_in (signal_in_int[1]), .ext_in (ext_in[1]), .serial_mode (serial_mode), .si (chain[0]), .shift (shift), .mdio_dis (mdio_dis), .sig_out (sig_out[1]), .so (chain[1])); stratixiv_hssi_cmu_dprio_bit ctrl_reg_bit_2 (.reset (reset), .clk (clk), .sig_in (signal_in_int[2]), .ext_in (ext_in[2]), .serial_mode (serial_mode), .si (chain[1]), .shift (shift), .mdio_dis (mdio_dis), .sig_out (sig_out[2]), .so (chain[2])); stratixiv_hssi_cmu_dprio_bit ctrl_reg_bit_3 (.reset (reset), .clk (clk), .sig_in (signal_in_int[3]), .ext_in (ext_in[3]), .serial_mode (serial_mode), .si (chain[2]), .shift (shift), .mdio_dis (mdio_dis), .sig_out (sig_out[3]), .so (chain[3])); stratixiv_hssi_cmu_dprio_bit ctrl_reg_bit_4 (.reset (reset), .clk (clk), .sig_in (signal_in_int[4]), .ext_in (ext_in[4]), .serial_mode (serial_mode), .si (chain[3]), .shift (shift), .mdio_dis (mdio_dis), .sig_out (sig_out[4]), .so (chain[4])); stratixiv_hssi_cmu_dprio_bit ctrl_reg_bit_5 (.reset (reset), .clk (clk), .sig_in (signal_in_int[5]), .ext_in (ext_in[5]), .serial_mode (serial_mode), .si (chain[4]), .shift (shift), .mdio_dis (mdio_dis), .sig_out (sig_out[5]), .so (chain[5])); stratixiv_hssi_cmu_dprio_bit ctrl_reg_bit_6 (.reset (reset), .clk (clk), .sig_in (signal_in_int[6]), .ext_in (ext_in[6]), .serial_mode (serial_mode), .si (chain[5]), .shift (shift), .mdio_dis (mdio_dis), .sig_out (sig_out[6]), .so (chain[6])); stratixiv_hssi_cmu_dprio_bit ctrl_reg_bit_7 (.reset (reset), .clk (clk), .sig_in (signal_in_int[7]), .ext_in (ext_in[7]), .serial_mode (serial_mode), .si (chain[6]), .shift (shift), .mdio_dis (mdio_dis), .sig_out (sig_out[7]), .so (chain[7])); stratixiv_hssi_cmu_dprio_bit ctrl_reg_bit_8 (.reset (reset), .clk (clk), .sig_in (signal_in_int[8]), .ext_in (ext_in[8]), .serial_mode (serial_mode), .si (chain[7]), .shift (shift), .mdio_dis (mdio_dis), .sig_out (sig_out[8]), .so (chain[8])); stratixiv_hssi_cmu_dprio_bit ctrl_reg_bit_9 (.reset (reset), .clk (clk), .sig_in (signal_in_int[9]), .ext_in (ext_in[9]), .serial_mode (serial_mode), .si (chain[8]), .shift (shift), .mdio_dis (mdio_dis), .sig_out (sig_out[9]), .so (chain[9])); stratixiv_hssi_cmu_dprio_bit ctrl_reg_bit_10 (.reset (reset), .clk (clk), .sig_in (signal_in_int[10]), .ext_in (ext_in[10]), .serial_mode (serial_mode), .si (chain[9]), .shift (shift), .mdio_dis (mdio_dis), .sig_out (sig_out[10]), .so (chain[10])); stratixiv_hssi_cmu_dprio_bit ctrl_reg_bit_11 (.reset (reset), .clk (clk), .sig_in (signal_in_int[11]), .ext_in (ext_in[11]), .serial_mode (serial_mode), .si (chain[10]), .shift (shift), .mdio_dis (mdio_dis), .sig_out (sig_out[11]), .so (chain[11])); stratixiv_hssi_cmu_dprio_bit ctrl_reg_bit_12 (.reset (reset), .clk (clk), .sig_in (signal_in_int[12]), .ext_in (ext_in[12]), .serial_mode (serial_mode), .si (chain[11]), .shift (shift), .mdio_dis (mdio_dis), .sig_out (sig_out[12]), .so (chain[12])); stratixiv_hssi_cmu_dprio_bit ctrl_reg_bit_13 (.reset (reset), .clk (clk), .sig_in (signal_in_int[13]), .ext_in (ext_in[13]), .serial_mode (serial_mode), .si (chain[12]), .shift (shift), .mdio_dis (mdio_dis), .sig_out (sig_out[13]), .so (chain[13])); stratixiv_hssi_cmu_dprio_bit ctrl_reg_bit_14 (.reset (reset), .clk (clk), .sig_in (signal_in_int[14]), .ext_in (ext_in[14]), .serial_mode (serial_mode), .si (chain[13]), .shift (shift), .mdio_dis (mdio_dis), .sig_out (sig_out[14]), .so (chain[14])); stratixiv_hssi_cmu_dprio_bit ctrl_reg_bit_15 (.reset (reset), .clk (clk), .sig_in (signal_in_int[15]), .ext_in (ext_in[15]), .serial_mode (serial_mode), .si (chain[14]), .shift (shift), .mdio_dis (mdio_dis), .sig_out (sig_out[15]), .so (so)); endmodule `timescale 1 ns / 1 ps module stratixiv_hssi_cmu_dprio_16bit_pma (reset, mdio_wr, reg_addr, target_addr, clk, sig_in, ext_in, serial_mode, si, shift, mdio_dis, pma_cram_test, sig_out, so); input reset; // reset input mdio_wr; input [15:0] reg_addr; input [15:0] target_addr; input clk; // clock input [15:0] sig_in; // signal input input [15:0] ext_in; // external port input input serial_mode;// serial shift mode enable input si; // scan input input shift; // 1'b1=shift in data from si into scan flop // 1'b0=load data from sig_in into scan flop input mdio_dis; // // 1'b1=output CRAM // 1'b0=output MDIO control register input pma_cram_test; //1'b1: choose the previous output of this register //1'b0: choose either si or input from DPRIO SM (sig_in) output [15:0] sig_out; // signal output output so; // scan output wire [15:0] signal_in_int; wire [15:0] sig_out; wire [14:0] chain; wire so; assign signal_in_int = (mdio_wr && (reg_addr == target_addr)) ? sig_in : {so, chain}; stratixiv_hssi_cmu_dprio_bit_pma ctrl_reg_bit_pma_0 (.reset (reset), .clk (clk), .sig_in (signal_in_int[0]), .ext_in (ext_in[0]), .serial_mode (serial_mode), .si (si), .shift (shift), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (sig_out[0]), .so (chain[0])); stratixiv_hssi_cmu_dprio_bit_pma ctrl_reg_bit_pma_1 (.reset (reset), .clk (clk), .sig_in (signal_in_int[1]), .ext_in (ext_in[1]), .serial_mode (serial_mode), .si (chain[0]), .shift (shift), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (sig_out[1]), .so (chain[1])); stratixiv_hssi_cmu_dprio_bit_pma ctrl_reg_bit_pma_2 (.reset (reset), .clk (clk), .sig_in (signal_in_int[2]), .ext_in (ext_in[2]), .serial_mode (serial_mode), .si (chain[1]), .shift (shift), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (sig_out[2]), .so (chain[2])); stratixiv_hssi_cmu_dprio_bit_pma ctrl_reg_bit_pma_3 (.reset (reset), .clk (clk), .sig_in (signal_in_int[3]), .ext_in (ext_in[3]), .serial_mode (serial_mode), .si (chain[2]), .shift (shift), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (sig_out[3]), .so (chain[3])); stratixiv_hssi_cmu_dprio_bit_pma ctrl_reg_bit_pma_4 (.reset (reset), .clk (clk), .sig_in (signal_in_int[4]), .ext_in (ext_in[4]), .serial_mode (serial_mode), .si (chain[3]), .shift (shift), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (sig_out[4]), .so (chain[4])); stratixiv_hssi_cmu_dprio_bit_pma ctrl_reg_bit_pma_5 (.reset (reset), .clk (clk), .sig_in (signal_in_int[5]), .ext_in (ext_in[5]), .serial_mode (serial_mode), .si (chain[4]), .shift (shift), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (sig_out[5]), .so (chain[5])); stratixiv_hssi_cmu_dprio_bit_pma ctrl_reg_bit_pma_6 (.reset (reset), .clk (clk), .sig_in (signal_in_int[6]), .ext_in (ext_in[6]), .serial_mode (serial_mode), .si (chain[5]), .shift (shift), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (sig_out[6]), .so (chain[6])); stratixiv_hssi_cmu_dprio_bit_pma ctrl_reg_bit_pma_7 (.reset (reset), .clk (clk), .sig_in (signal_in_int[7]), .ext_in (ext_in[7]), .serial_mode (serial_mode), .si (chain[6]), .shift (shift), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (sig_out[7]), .so (chain[7])); stratixiv_hssi_cmu_dprio_bit_pma ctrl_reg_bit_pma_8 (.reset (reset), .clk (clk), .sig_in (signal_in_int[8]), .ext_in (ext_in[8]), .serial_mode (serial_mode), .si (chain[7]), .shift (shift), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (sig_out[8]), .so (chain[8])); stratixiv_hssi_cmu_dprio_bit_pma ctrl_reg_bit_pma_9 (.reset (reset), .clk (clk), .sig_in (signal_in_int[9]), .ext_in (ext_in[9]), .serial_mode (serial_mode), .si (chain[8]), .shift (shift), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (sig_out[9]), .so (chain[9])); stratixiv_hssi_cmu_dprio_bit_pma ctrl_reg_bit_pma_10 (.reset (reset), .clk (clk), .sig_in (signal_in_int[10]), .ext_in (ext_in[10]), .serial_mode (serial_mode), .si (chain[9]), .shift (shift), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (sig_out[10]), .so (chain[10])); stratixiv_hssi_cmu_dprio_bit_pma ctrl_reg_bit_pma_11 (.reset (reset), .clk (clk), .sig_in (signal_in_int[11]), .ext_in (ext_in[11]), .serial_mode (serial_mode), .si (chain[10]), .shift (shift), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (sig_out[11]), .so (chain[11])); stratixiv_hssi_cmu_dprio_bit_pma ctrl_reg_bit_pma_12 (.reset (reset), .clk (clk), .sig_in (signal_in_int[12]), .ext_in (ext_in[12]), .serial_mode (serial_mode), .si (chain[11]), .shift (shift), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (sig_out[12]), .so (chain[12])); stratixiv_hssi_cmu_dprio_bit_pma ctrl_reg_bit_pma_13 (.reset (reset), .clk (clk), .sig_in (signal_in_int[13]), .ext_in (ext_in[13]), .serial_mode (serial_mode), .si (chain[12]), .shift (shift), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (sig_out[13]), .so (chain[13])); stratixiv_hssi_cmu_dprio_bit_pma ctrl_reg_bit_pma_14 (.reset (reset), .clk (clk), .sig_in (signal_in_int[14]), .ext_in (ext_in[14]), .serial_mode (serial_mode), .si (chain[13]), .shift (shift), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (sig_out[14]), .so (chain[14])); stratixiv_hssi_cmu_dprio_bit_pma ctrl_reg_bit_pma_15 (.reset (reset), .clk (clk), .sig_in (signal_in_int[15]), .ext_in (ext_in[15]), .serial_mode (serial_mode), .si (chain[14]), .shift (shift), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (sig_out[15]), .so (so)); endmodule `timescale 1 ps / 1 ps module stratixiv_hssi_cmu_dprio_reg_chnl (mdio_rst, mdio_wr, reg_addr, mdc, mbus_in, serial_mode, mdio_dis, pma_cram_test, ser_shift_load, si, // CSR input ext_chnl_ctrl_1, ext_chnl_ctrl_2, ext_chnl_ctrl_3, ext_chnl_ctrl_4, ext_chnl_ctrl_5, ext_chnl_ctrl_6, ext_chnl_ctrl_7, ext_chnl_ctrl_8, ext_chnl_ctrl_9, ext_chnl_ctrl_10, ext_chnl_ctrl_11, ext_chnl_ctrl_12, ext_chnl_ctrl_13, ext_chnl_ctrl_14, ext_chnl_ctrl_15, ext_chnl_ctrl_16, ext_chnl_ctrl_17, ext_chnl_ctrl_18, ext_chnl_ctrl_19, ext_chnl_ctrl_20, ext_chnl_ctrl_21, ext_chnl_ctrl_22, ext_chnl_ctrl_23, ext_chnl_ctrl_24, ext_chnl_ctrl_25, ext_chnl_ctrl_26, ext_chnl_ctrl_27, ext_chnl_ctrl_28, ext_chnl_ctrl_29, ext_chnl_ctrl_30, ext_chnl_ctrl_31, ext_chnl_ctrl_32, ext_chnl_ctrl_33, ext_chnl_ctrl_34, ext_chnl_ctrl_35, ext_chnl_ctrl_36, ext_chnl_ctrl_37, ext_chnl_ctrl_38, ext_chnl_ctrl_39, ext_chnl_ctrl_40, ext_chnl_ctrl_41, ext_chnl_ctrl_42, ext_chnl_ctrl_43, ext_chnl_ctrl_44, ext_chnl_ctrl_45, ext_chnl_ctrl_46, ext_chnl_ctrl_47, ext_chnl_ctrl_48, ext_chnl_ctrl_49, ext_chnl_ctrl_50, ext_chnl_ctrl_51, ext_chnl_ctrl_52, ext_chnl_ctrl_53, targ_addr_ctrl_1, targ_addr_ctrl_2, targ_addr_ctrl_3, targ_addr_ctrl_4, targ_addr_ctrl_5, targ_addr_ctrl_6, targ_addr_ctrl_7, targ_addr_ctrl_8, targ_addr_ctrl_9, targ_addr_ctrl_10, targ_addr_ctrl_11, targ_addr_ctrl_12, targ_addr_ctrl_13, targ_addr_ctrl_14, targ_addr_ctrl_15, targ_addr_ctrl_16, targ_addr_ctrl_17, targ_addr_ctrl_18, targ_addr_ctrl_19, targ_addr_ctrl_20, targ_addr_ctrl_21, targ_addr_ctrl_22, targ_addr_ctrl_23, targ_addr_ctrl_24, targ_addr_ctrl_25, targ_addr_ctrl_26, targ_addr_ctrl_27, targ_addr_ctrl_28, targ_addr_ctrl_29, targ_addr_ctrl_30, targ_addr_ctrl_31, targ_addr_ctrl_32, targ_addr_ctrl_33, targ_addr_ctrl_34, targ_addr_ctrl_35, targ_addr_ctrl_36, targ_addr_ctrl_37, targ_addr_ctrl_38, targ_addr_ctrl_39, targ_addr_ctrl_40, targ_addr_ctrl_41, targ_addr_ctrl_42, targ_addr_ctrl_43, targ_addr_ctrl_44, targ_addr_ctrl_45, targ_addr_ctrl_46, targ_addr_ctrl_47, targ_addr_ctrl_48, targ_addr_ctrl_49, targ_addr_ctrl_50, targ_addr_ctrl_51, targ_addr_ctrl_52, targ_addr_ctrl_53, // DPRIO register output out_chnl_ctrl_1, out_chnl_ctrl_2, out_chnl_ctrl_3, out_chnl_ctrl_4, out_chnl_ctrl_5, out_chnl_ctrl_6, out_chnl_ctrl_7, out_chnl_ctrl_8, out_chnl_ctrl_9, out_chnl_ctrl_10, out_chnl_ctrl_11, out_chnl_ctrl_12, out_chnl_ctrl_13, out_chnl_ctrl_14, out_chnl_ctrl_15, out_chnl_ctrl_16, out_chnl_ctrl_17, out_chnl_ctrl_18, out_chnl_ctrl_19, out_chnl_ctrl_20, out_chnl_ctrl_21, out_chnl_ctrl_22, out_chnl_ctrl_23, out_chnl_ctrl_24, out_chnl_ctrl_25, out_chnl_ctrl_26, out_chnl_ctrl_27, out_chnl_ctrl_28, out_chnl_ctrl_29, out_chnl_ctrl_30, out_chnl_ctrl_31, out_chnl_ctrl_32, out_chnl_ctrl_33, out_chnl_ctrl_34, out_chnl_ctrl_35, out_chnl_ctrl_36, out_chnl_ctrl_37, out_chnl_ctrl_38, out_chnl_ctrl_39, out_chnl_ctrl_40, out_chnl_ctrl_41, out_chnl_ctrl_42, out_chnl_ctrl_43, out_chnl_ctrl_44, out_chnl_ctrl_45, out_chnl_ctrl_46, out_chnl_ctrl_47, out_chnl_ctrl_48, out_chnl_ctrl_49, out_chnl_ctrl_50, out_chnl_ctrl_51, out_chnl_ctrl_52, out_chnl_ctrl_53, so); input mdio_rst; input mdio_wr; input [15:0] reg_addr; input mdc; input [15:0] mbus_in; input serial_mode; input mdio_dis; input pma_cram_test; input ser_shift_load; input si; input [15:0] ext_chnl_ctrl_1; input [15:0] ext_chnl_ctrl_2; input [15:0] ext_chnl_ctrl_3; input [15:0] ext_chnl_ctrl_4; input [15:0] ext_chnl_ctrl_5; input [15:0] ext_chnl_ctrl_6; input [15:0] ext_chnl_ctrl_7; input [15:0] ext_chnl_ctrl_8; input [15:0] ext_chnl_ctrl_9; input [15:0] ext_chnl_ctrl_10; input [15:0] ext_chnl_ctrl_11; input [15:0] ext_chnl_ctrl_12; input [15:0] ext_chnl_ctrl_13; input [15:0] ext_chnl_ctrl_14; input [15:0] ext_chnl_ctrl_15; input [15:0] ext_chnl_ctrl_16; input [15:0] ext_chnl_ctrl_17; input [15:0] ext_chnl_ctrl_18; input [15:0] ext_chnl_ctrl_19; input [15:0] ext_chnl_ctrl_20; input [15:0] ext_chnl_ctrl_21; input [15:0] ext_chnl_ctrl_22; input [15:0] ext_chnl_ctrl_23; input [15:0] ext_chnl_ctrl_24; input [15:0] ext_chnl_ctrl_25; input [15:0] ext_chnl_ctrl_26; input [15:0] ext_chnl_ctrl_27; input [15:0] ext_chnl_ctrl_28; input [15:0] ext_chnl_ctrl_29; input [15:0] ext_chnl_ctrl_30; input [15:0] ext_chnl_ctrl_31; input [15:0] ext_chnl_ctrl_32; input [15:0] ext_chnl_ctrl_33; input [15:0] ext_chnl_ctrl_34; input [15:0] ext_chnl_ctrl_35; input [15:0] ext_chnl_ctrl_36; input [15:0] ext_chnl_ctrl_37; input [15:0] ext_chnl_ctrl_38; input [15:0] ext_chnl_ctrl_39; input [15:0] ext_chnl_ctrl_40; input [15:0] ext_chnl_ctrl_41; input [15:0] ext_chnl_ctrl_42; input [15:0] ext_chnl_ctrl_43; input [15:0] ext_chnl_ctrl_44; input [15:0] ext_chnl_ctrl_45; input [15:0] ext_chnl_ctrl_46; input [15:0] ext_chnl_ctrl_47; input [15:0] ext_chnl_ctrl_48; input [15:0] ext_chnl_ctrl_49; input [15:0] ext_chnl_ctrl_50; input [15:0] ext_chnl_ctrl_51; input [15:0] ext_chnl_ctrl_52; input [15:0] ext_chnl_ctrl_53; input [15:0] targ_addr_ctrl_1; input [15:0] targ_addr_ctrl_2; input [15:0] targ_addr_ctrl_3; input [15:0] targ_addr_ctrl_4; input [15:0] targ_addr_ctrl_5; input [15:0] targ_addr_ctrl_6; input [15:0] targ_addr_ctrl_7; input [15:0] targ_addr_ctrl_8; input [15:0] targ_addr_ctrl_9; input [15:0] targ_addr_ctrl_10; input [15:0] targ_addr_ctrl_11; input [15:0] targ_addr_ctrl_12; input [15:0] targ_addr_ctrl_13; input [15:0] targ_addr_ctrl_14; input [15:0] targ_addr_ctrl_15; input [15:0] targ_addr_ctrl_16; input [15:0] targ_addr_ctrl_17; input [15:0] targ_addr_ctrl_18; input [15:0] targ_addr_ctrl_19; input [15:0] targ_addr_ctrl_20; input [15:0] targ_addr_ctrl_21; input [15:0] targ_addr_ctrl_22; input [15:0] targ_addr_ctrl_23; input [15:0] targ_addr_ctrl_24; input [15:0] targ_addr_ctrl_25; input [15:0] targ_addr_ctrl_26; input [15:0] targ_addr_ctrl_27; input [15:0] targ_addr_ctrl_28; input [15:0] targ_addr_ctrl_29; input [15:0] targ_addr_ctrl_30; input [15:0] targ_addr_ctrl_31; input [15:0] targ_addr_ctrl_32; input [15:0] targ_addr_ctrl_33; input [15:0] targ_addr_ctrl_34; input [15:0] targ_addr_ctrl_35; input [15:0] targ_addr_ctrl_36; input [15:0] targ_addr_ctrl_37; input [15:0] targ_addr_ctrl_38; input [15:0] targ_addr_ctrl_39; input [15:0] targ_addr_ctrl_40; input [15:0] targ_addr_ctrl_41; input [15:0] targ_addr_ctrl_42; input [15:0] targ_addr_ctrl_43; input [15:0] targ_addr_ctrl_44; input [15:0] targ_addr_ctrl_45; input [15:0] targ_addr_ctrl_46; input [15:0] targ_addr_ctrl_47; input [15:0] targ_addr_ctrl_48; input [15:0] targ_addr_ctrl_49; input [15:0] targ_addr_ctrl_50; input [15:0] targ_addr_ctrl_51; input [15:0] targ_addr_ctrl_52; input [15:0] targ_addr_ctrl_53; output [15:0] out_chnl_ctrl_1; output [15:0] out_chnl_ctrl_2; output [15:0] out_chnl_ctrl_3; output [15:0] out_chnl_ctrl_4; output [15:0] out_chnl_ctrl_5; output [15:0] out_chnl_ctrl_6; output [15:0] out_chnl_ctrl_7; output [15:0] out_chnl_ctrl_8; output [15:0] out_chnl_ctrl_9; output [15:0] out_chnl_ctrl_10; output [15:0] out_chnl_ctrl_11; output [15:0] out_chnl_ctrl_12; output [15:0] out_chnl_ctrl_13; output [15:0] out_chnl_ctrl_14; output [15:0] out_chnl_ctrl_15; output [15:0] out_chnl_ctrl_16; output [15:0] out_chnl_ctrl_17; output [15:0] out_chnl_ctrl_18; output [15:0] out_chnl_ctrl_19; output [15:0] out_chnl_ctrl_20; output [15:0] out_chnl_ctrl_21; output [15:0] out_chnl_ctrl_22; output [15:0] out_chnl_ctrl_23; output [15:0] out_chnl_ctrl_24; output [15:0] out_chnl_ctrl_25; output [15:0] out_chnl_ctrl_26; output [15:0] out_chnl_ctrl_27; output [15:0] out_chnl_ctrl_28; output [15:0] out_chnl_ctrl_29; output [15:0] out_chnl_ctrl_30; output [15:0] out_chnl_ctrl_31; output [15:0] out_chnl_ctrl_32; output [15:0] out_chnl_ctrl_33; output [15:0] out_chnl_ctrl_34; output [15:0] out_chnl_ctrl_35; output [15:0] out_chnl_ctrl_36; output [15:0] out_chnl_ctrl_37; output [15:0] out_chnl_ctrl_38; output [15:0] out_chnl_ctrl_39; output [15:0] out_chnl_ctrl_40; output [15:0] out_chnl_ctrl_41; output [15:0] out_chnl_ctrl_42; output [15:0] out_chnl_ctrl_43; output [15:0] out_chnl_ctrl_44; output [15:0] out_chnl_ctrl_45; output [15:0] out_chnl_ctrl_46; output [15:0] out_chnl_ctrl_47; output [15:0] out_chnl_ctrl_48; output [15:0] out_chnl_ctrl_49; output [15:0] out_chnl_ctrl_50; output [15:0] out_chnl_ctrl_51; output [15:0] out_chnl_ctrl_52; output [15:0] out_chnl_ctrl_53; output so; wire [51:0] chain; stratixiv_hssi_cmu_dprio_16bit chnl_ctrl_1 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_1), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_1), .serial_mode (serial_mode), .si (si), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_chnl_ctrl_1), .so (chain[0])); stratixiv_hssi_cmu_dprio_16bit chnl_ctrl_2 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_2), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_2), .serial_mode (serial_mode), .si (chain[0]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_chnl_ctrl_2), .so (chain[1])); stratixiv_hssi_cmu_dprio_16bit chnl_ctrl_3 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_3), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_3), .serial_mode (serial_mode), .si (chain[1]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_chnl_ctrl_3), .so (chain[2])); stratixiv_hssi_cmu_dprio_16bit chnl_ctrl_4 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_4), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_4), .serial_mode (serial_mode), .si (chain[2]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_chnl_ctrl_4), .so (chain[3])); stratixiv_hssi_cmu_dprio_16bit chnl_ctrl_5 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_5), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_5), .serial_mode (serial_mode), .si (chain[3]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_chnl_ctrl_5), .so (chain[4])); stratixiv_hssi_cmu_dprio_16bit chnl_ctrl_6 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_6), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_6), .serial_mode (serial_mode), .si (chain[4]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_chnl_ctrl_6), .so (chain[5])); stratixiv_hssi_cmu_dprio_16bit chnl_ctrl_7 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_7), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_7), .serial_mode (serial_mode), .si (chain[5]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_chnl_ctrl_7), .so (chain[6])); stratixiv_hssi_cmu_dprio_16bit chnl_ctrl_8 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_8), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_8), .serial_mode (serial_mode), .si (chain[6]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_chnl_ctrl_8), .so (chain[7])); stratixiv_hssi_cmu_dprio_16bit chnl_ctrl_9 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_9), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_9), .serial_mode (serial_mode), .si (chain[7]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_chnl_ctrl_9), .so (chain[8])); stratixiv_hssi_cmu_dprio_16bit chnl_ctrl_10 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_10), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_10), .serial_mode (serial_mode), .si (chain[8]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_chnl_ctrl_10), .so (chain[9])); stratixiv_hssi_cmu_dprio_16bit chnl_ctrl_11 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_11), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_11), .serial_mode (serial_mode), .si (chain[9]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_chnl_ctrl_11), .so (chain[10])); stratixiv_hssi_cmu_dprio_16bit chnl_ctrl_12 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_12), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_12), .serial_mode (serial_mode), .si (chain[10]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_chnl_ctrl_12), .so (chain[11])); stratixiv_hssi_cmu_dprio_16bit chnl_ctrl_13 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_13), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_13), .serial_mode (serial_mode), .si (chain[11]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_chnl_ctrl_13), .so (chain[12])); stratixiv_hssi_cmu_dprio_16bit chnl_ctrl_14 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_14), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_14), .serial_mode (serial_mode), .si (chain[12]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_chnl_ctrl_14), .so (chain[13])); stratixiv_hssi_cmu_dprio_16bit chnl_ctrl_15 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_15), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_15), .serial_mode (serial_mode), .si (chain[13]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_chnl_ctrl_15), .so (chain[14])); stratixiv_hssi_cmu_dprio_16bit chnl_ctrl_16 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_16), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_16), .serial_mode (serial_mode), .si (chain[14]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_chnl_ctrl_16), .so (chain[15])); stratixiv_hssi_cmu_dprio_16bit chnl_ctrl_17 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_17), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_17), .serial_mode (serial_mode), .si (chain[15]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_chnl_ctrl_17), .so (chain[16])); stratixiv_hssi_cmu_dprio_16bit chnl_ctrl_18 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_18), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_18), .serial_mode (serial_mode), .si (chain[16]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_chnl_ctrl_18), .so (chain[17])); stratixiv_hssi_cmu_dprio_16bit chnl_ctrl_19 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_19), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_19), .serial_mode (serial_mode), .si (chain[17]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_chnl_ctrl_19), .so (chain[18])); stratixiv_hssi_cmu_dprio_16bit chnl_ctrl_20 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_20), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_20), .serial_mode (serial_mode), .si (chain[18]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_chnl_ctrl_20), .so (chain[19])); stratixiv_hssi_cmu_dprio_16bit chnl_ctrl_21 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_21), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_21), .serial_mode (serial_mode), .si (chain[19]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_chnl_ctrl_21), .so (chain[20])); stratixiv_hssi_cmu_dprio_16bit chnl_ctrl_22 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_22), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_22), .serial_mode (serial_mode), .si (chain[20]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_chnl_ctrl_22), .so (chain[21])); stratixiv_hssi_cmu_dprio_16bit chnl_ctrl_23 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_23), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_23), .serial_mode (serial_mode), .si (chain[21]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_chnl_ctrl_23), .so (chain[22])); stratixiv_hssi_cmu_dprio_16bit chnl_ctrl_24 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_24), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_24), .serial_mode (serial_mode), .si (chain[22]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_chnl_ctrl_24), .so (chain[23])); stratixiv_hssi_cmu_dprio_16bit chnl_ctrl_25 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_25), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_25), .serial_mode (serial_mode), .si (chain[23]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_chnl_ctrl_25), .so (chain[24])); stratixiv_hssi_cmu_dprio_16bit chnl_ctrl_26 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_26), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_26), .serial_mode (serial_mode), .si (chain[24]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_chnl_ctrl_26), .so (chain[25])); stratixiv_hssi_cmu_dprio_16bit chnl_ctrl_27 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_27), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_27), .serial_mode (serial_mode), .si (chain[25]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_chnl_ctrl_27), .so (chain[26])); stratixiv_hssi_cmu_dprio_16bit_pma chnl_ctrl_28 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_28), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_28), .serial_mode (serial_mode), .si (chain[26]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_chnl_ctrl_28), .so (chain[27])); stratixiv_hssi_cmu_dprio_16bit_pma chnl_ctrl_29 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_29), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_29), .serial_mode (serial_mode), .si (chain[27]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_chnl_ctrl_29), .so (chain[28])); stratixiv_hssi_cmu_dprio_16bit_pma chnl_ctrl_30 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_30), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_30), .serial_mode (serial_mode), .si (chain[28]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_chnl_ctrl_30), .so (chain[29])); stratixiv_hssi_cmu_dprio_16bit_pma chnl_ctrl_31 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_31), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_31), .serial_mode (serial_mode), .si (chain[29]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_chnl_ctrl_31), .so (chain[30])); stratixiv_hssi_cmu_dprio_16bit_pma chnl_ctrl_32 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_32), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_32), .serial_mode (serial_mode), .si (chain[30]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_chnl_ctrl_32), .so (chain[31])); stratixiv_hssi_cmu_dprio_16bit_pma chnl_ctrl_33 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_33), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_33), .serial_mode (serial_mode), .si (chain[31]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_chnl_ctrl_33), .so (chain[32])); stratixiv_hssi_cmu_dprio_16bit_pma chnl_ctrl_34 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_34), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_34), .serial_mode (serial_mode), .si (chain[32]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_chnl_ctrl_34), .so (chain[33])); stratixiv_hssi_cmu_dprio_16bit_pma chnl_ctrl_35 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_35), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_35), .serial_mode (serial_mode), .si (chain[33]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_chnl_ctrl_35), .so (chain[34])); stratixiv_hssi_cmu_dprio_16bit_pma chnl_ctrl_36 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_36), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_36), .serial_mode (serial_mode), .si (chain[34]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_chnl_ctrl_36), .so (chain[35])); stratixiv_hssi_cmu_dprio_16bit_pma chnl_ctrl_37 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_37), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_37), .serial_mode (serial_mode), .si (chain[35]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_chnl_ctrl_37), .so (chain[36])); stratixiv_hssi_cmu_dprio_16bit_pma chnl_ctrl_38 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_38), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_38), .serial_mode (serial_mode), .si (chain[36]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_chnl_ctrl_38), .so (chain[37])); stratixiv_hssi_cmu_dprio_16bit_pma chnl_ctrl_39 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_39), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_39), .serial_mode (serial_mode), .si (chain[37]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_chnl_ctrl_39), .so (chain[38])); stratixiv_hssi_cmu_dprio_16bit_pma chnl_ctrl_40 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_40), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_40), .serial_mode (serial_mode), .si (chain[38]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_chnl_ctrl_40), .so (chain[39])); stratixiv_hssi_cmu_dprio_16bit_pma chnl_ctrl_41 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_41), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_41), .serial_mode (serial_mode), .si (chain[39]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_chnl_ctrl_41), .so (chain[40])); stratixiv_hssi_cmu_dprio_16bit_pma chnl_ctrl_42 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_42), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_42), .serial_mode (serial_mode), .si (chain[40]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_chnl_ctrl_42), .so (chain[41])); stratixiv_hssi_cmu_dprio_16bit_pma chnl_ctrl_43 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_43), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_43), .serial_mode (serial_mode), .si (chain[41]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_chnl_ctrl_43), .so (chain[42])); stratixiv_hssi_cmu_dprio_16bit_pma chnl_ctrl_44 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_44), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_44), .serial_mode (serial_mode), .si (chain[42]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_chnl_ctrl_44), .so (chain[43])); stratixiv_hssi_cmu_dprio_16bit_pma chnl_ctrl_45 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_45), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_45), .serial_mode (serial_mode), .si (chain[43]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_chnl_ctrl_45), .so (chain[44])); stratixiv_hssi_cmu_dprio_16bit_pma chnl_ctrl_46 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_46), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_46), .serial_mode (serial_mode), .si (chain[44]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_chnl_ctrl_46), .so (chain[45])); stratixiv_hssi_cmu_dprio_16bit_pma chnl_ctrl_47 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_47), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_47), .serial_mode (serial_mode), .si (chain[45]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_chnl_ctrl_47), .so (chain[46])); stratixiv_hssi_cmu_dprio_16bit_pma chnl_ctrl_48 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_48), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_48), .serial_mode (serial_mode), .si (chain[46]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_chnl_ctrl_48), .so (chain[47])); stratixiv_hssi_cmu_dprio_16bit_pma chnl_ctrl_49 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_49), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_49), .serial_mode (serial_mode), .si (chain[47]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_chnl_ctrl_49), .so (chain[48])); stratixiv_hssi_cmu_dprio_16bit_pma chnl_ctrl_50 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_50), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_50), .serial_mode (serial_mode), .si (chain[48]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_chnl_ctrl_50), .so (chain[49])); stratixiv_hssi_cmu_dprio_16bit_pma chnl_ctrl_51 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_51), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_51), .serial_mode (serial_mode), .si (chain[49]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_chnl_ctrl_51), .so (chain[50])); stratixiv_hssi_cmu_dprio_16bit_pma chnl_ctrl_52 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_52), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_52), .serial_mode (serial_mode), .si (chain[50]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_chnl_ctrl_52), .so (chain[51])); stratixiv_hssi_cmu_dprio_16bit_pma chnl_ctrl_53 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_53), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_chnl_ctrl_53), .serial_mode (serial_mode), .si (chain[51]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_chnl_ctrl_53), .so (so)); endmodule `timescale 1 ps / 1 ps module stratixiv_hssi_cmu_dprio_chnl_bus_out_mux (chnl_ctrl_in1, chnl_ctrl_in2, chnl_ctrl_in3, chnl_ctrl_in4, chnl_ctrl_in5, chnl_ctrl_in6, chnl_ctrl_in7, chnl_ctrl_in8, chnl_ctrl_in9, chnl_ctrl_in10, chnl_ctrl_in11, chnl_ctrl_in12, chnl_ctrl_in13, chnl_ctrl_in14, chnl_ctrl_in15, chnl_ctrl_in16, chnl_ctrl_in17, chnl_ctrl_in18, chnl_ctrl_in19, chnl_ctrl_in20, chnl_ctrl_in21, chnl_ctrl_in22, chnl_ctrl_in23, chnl_ctrl_in24, chnl_ctrl_in25, chnl_ctrl_in26, chnl_ctrl_in27, chnl_ctrl_in28, chnl_ctrl_in29, chnl_ctrl_in30, chnl_ctrl_in31, chnl_ctrl_in32, chnl_ctrl_in33, chnl_ctrl_in34, chnl_ctrl_in35, chnl_ctrl_in36, chnl_ctrl_in37, chnl_ctrl_in38, chnl_ctrl_in39,chnl_ctrl_in40, chnl_ctrl_in41, chnl_ctrl_in42, chnl_ctrl_in43, chnl_ctrl_in44, chnl_ctrl_in45, chnl_ctrl_in46, chnl_ctrl_in47, chnl_ctrl_in48, chnl_ctrl_in49, chnl_ctrl_in50, chnl_ctrl_in51, chnl_ctrl_in52, chnl_ctrl_in53, hw_address_ctrl_in1, hw_address_ctrl_in2, hw_address_ctrl_in3, hw_address_ctrl_in4, hw_address_ctrl_in5, hw_address_ctrl_in6, hw_address_ctrl_in7, hw_address_ctrl_in8, hw_address_ctrl_in9, hw_address_ctrl_in10, hw_address_ctrl_in11, hw_address_ctrl_in12, hw_address_ctrl_in13, hw_address_ctrl_in14, hw_address_ctrl_in15, hw_address_ctrl_in16, hw_address_ctrl_in17, hw_address_ctrl_in18, hw_address_ctrl_in19, hw_address_ctrl_in20, hw_address_ctrl_in21, hw_address_ctrl_in22, hw_address_ctrl_in23, hw_address_ctrl_in24, hw_address_ctrl_in25, hw_address_ctrl_in26, hw_address_ctrl_in27, hw_address_ctrl_in28, hw_address_ctrl_in29, hw_address_ctrl_in30, hw_address_ctrl_in31, hw_address_ctrl_in32, hw_address_ctrl_in33, hw_address_ctrl_in34, hw_address_ctrl_in35, hw_address_ctrl_in36, hw_address_ctrl_in37, hw_address_ctrl_in38, hw_address_ctrl_in39, hw_address_ctrl_in40, hw_address_ctrl_in41, hw_address_ctrl_in42, hw_address_ctrl_in43, hw_address_ctrl_in44, hw_address_ctrl_in45, hw_address_ctrl_in46, hw_address_ctrl_in47, hw_address_ctrl_in48, hw_address_ctrl_in49, hw_address_ctrl_in50, hw_address_ctrl_in51, hw_address_ctrl_in52, hw_address_ctrl_in53, reg_addr, chnl_ctrl_out ); input [15:0] chnl_ctrl_in1; input [15:0] chnl_ctrl_in2; input [15:0] chnl_ctrl_in3; input [15:0] chnl_ctrl_in4; input [15:0] chnl_ctrl_in5; input [15:0] chnl_ctrl_in6; input [15:0] chnl_ctrl_in7; input [15:0] chnl_ctrl_in8; input [15:0] chnl_ctrl_in9; input [15:0] chnl_ctrl_in10; input [15:0] chnl_ctrl_in11; input [15:0] chnl_ctrl_in12; input [15:0] chnl_ctrl_in13; input [15:0] chnl_ctrl_in14; input [15:0] chnl_ctrl_in15; input [15:0] chnl_ctrl_in16; input [15:0] chnl_ctrl_in17; input [15:0] chnl_ctrl_in18; input [15:0] chnl_ctrl_in19; input [15:0] chnl_ctrl_in20; input [15:0] chnl_ctrl_in21; input [15:0] chnl_ctrl_in22; input [15:0] chnl_ctrl_in23; input [15:0] chnl_ctrl_in24; input [15:0] chnl_ctrl_in25; input [15:0] chnl_ctrl_in26; input [15:0] chnl_ctrl_in27; input [15:0] chnl_ctrl_in28; input [15:0] chnl_ctrl_in29; input [15:0] chnl_ctrl_in30; input [15:0] chnl_ctrl_in31; input [15:0] chnl_ctrl_in32; input [15:0] chnl_ctrl_in33; input [15:0] chnl_ctrl_in34; input [15:0] chnl_ctrl_in35; input [15:0] chnl_ctrl_in36; input [15:0] chnl_ctrl_in37; input [15:0] chnl_ctrl_in38; input [15:0] chnl_ctrl_in39; input [15:0] chnl_ctrl_in40; input [15:0] chnl_ctrl_in41; input [15:0] chnl_ctrl_in42; input [15:0] chnl_ctrl_in43; input [15:0] chnl_ctrl_in44; input [15:0] chnl_ctrl_in45; input [15:0] chnl_ctrl_in46; input [15:0] chnl_ctrl_in47; input [15:0] chnl_ctrl_in48; input [15:0] chnl_ctrl_in49; input [15:0] chnl_ctrl_in50; input [15:0] chnl_ctrl_in51; input [15:0] chnl_ctrl_in52; input [15:0] chnl_ctrl_in53; input [15:0] hw_address_ctrl_in1; input [15:0] hw_address_ctrl_in2; input [15:0] hw_address_ctrl_in3; input [15:0] hw_address_ctrl_in4; input [15:0] hw_address_ctrl_in5; input [15:0] hw_address_ctrl_in6; input [15:0] hw_address_ctrl_in7; input [15:0] hw_address_ctrl_in8; input [15:0] hw_address_ctrl_in9; input [15:0] hw_address_ctrl_in10; input [15:0] hw_address_ctrl_in11; input [15:0] hw_address_ctrl_in12; input [15:0] hw_address_ctrl_in13; input [15:0] hw_address_ctrl_in14; input [15:0] hw_address_ctrl_in15; input [15:0] hw_address_ctrl_in16; input [15:0] hw_address_ctrl_in17; input [15:0] hw_address_ctrl_in18; input [15:0] hw_address_ctrl_in19; input [15:0] hw_address_ctrl_in20; input [15:0] hw_address_ctrl_in21; input [15:0] hw_address_ctrl_in22; input [15:0] hw_address_ctrl_in23; input [15:0] hw_address_ctrl_in24; input [15:0] hw_address_ctrl_in25; input [15:0] hw_address_ctrl_in26; input [15:0] hw_address_ctrl_in27; input [15:0] hw_address_ctrl_in28; input [15:0] hw_address_ctrl_in29; input [15:0] hw_address_ctrl_in30; input [15:0] hw_address_ctrl_in31; input [15:0] hw_address_ctrl_in32; input [15:0] hw_address_ctrl_in33; input [15:0] hw_address_ctrl_in34; input [15:0] hw_address_ctrl_in35; input [15:0] hw_address_ctrl_in36; input [15:0] hw_address_ctrl_in37; input [15:0] hw_address_ctrl_in38; input [15:0] hw_address_ctrl_in39; input [15:0] hw_address_ctrl_in40; input [15:0] hw_address_ctrl_in41; input [15:0] hw_address_ctrl_in42; input [15:0] hw_address_ctrl_in43; input [15:0] hw_address_ctrl_in44; input [15:0] hw_address_ctrl_in45; input [15:0] hw_address_ctrl_in46; input [15:0] hw_address_ctrl_in47; input [15:0] hw_address_ctrl_in48; input [15:0] hw_address_ctrl_in49; input [15:0] hw_address_ctrl_in50; input [15:0] hw_address_ctrl_in51; input [15:0] hw_address_ctrl_in52; input [15:0] hw_address_ctrl_in53; input [15:0] reg_addr; output [15:0] chnl_ctrl_out; assign chnl_ctrl_out =(reg_addr == hw_address_ctrl_in1 ) ? chnl_ctrl_in1 : (reg_addr == hw_address_ctrl_in2 ) ? chnl_ctrl_in2 : (reg_addr == hw_address_ctrl_in3 ) ? chnl_ctrl_in3 : (reg_addr == hw_address_ctrl_in4 ) ? chnl_ctrl_in4 : (reg_addr == hw_address_ctrl_in5 ) ? chnl_ctrl_in5 : (reg_addr == hw_address_ctrl_in6 ) ? chnl_ctrl_in6 : (reg_addr == hw_address_ctrl_in7 ) ? chnl_ctrl_in7 : (reg_addr == hw_address_ctrl_in8 ) ? chnl_ctrl_in8 : (reg_addr == hw_address_ctrl_in9 ) ? chnl_ctrl_in9 : (reg_addr == hw_address_ctrl_in10) ? chnl_ctrl_in10 : (reg_addr == hw_address_ctrl_in11) ? chnl_ctrl_in11 : (reg_addr == hw_address_ctrl_in12) ? chnl_ctrl_in12 : (reg_addr == hw_address_ctrl_in13) ? chnl_ctrl_in13 : (reg_addr == hw_address_ctrl_in14) ? chnl_ctrl_in14 : (reg_addr == hw_address_ctrl_in15) ? chnl_ctrl_in15 : (reg_addr == hw_address_ctrl_in16) ? chnl_ctrl_in16 : (reg_addr == hw_address_ctrl_in17) ? chnl_ctrl_in17 : (reg_addr == hw_address_ctrl_in18) ? chnl_ctrl_in18 : (reg_addr == hw_address_ctrl_in19) ? chnl_ctrl_in19 : (reg_addr == hw_address_ctrl_in20) ? chnl_ctrl_in20 : (reg_addr == hw_address_ctrl_in21) ? chnl_ctrl_in21 : (reg_addr == hw_address_ctrl_in22) ? chnl_ctrl_in22 : (reg_addr == hw_address_ctrl_in23) ? chnl_ctrl_in23 : (reg_addr == hw_address_ctrl_in24) ? chnl_ctrl_in24 : (reg_addr == hw_address_ctrl_in25) ? chnl_ctrl_in25 : (reg_addr == hw_address_ctrl_in26) ? chnl_ctrl_in26 : (reg_addr == hw_address_ctrl_in27) ? chnl_ctrl_in27 : (reg_addr == hw_address_ctrl_in28) ? chnl_ctrl_in28 : (reg_addr == hw_address_ctrl_in29) ? chnl_ctrl_in29 : (reg_addr == hw_address_ctrl_in30) ? chnl_ctrl_in30 : (reg_addr == hw_address_ctrl_in31) ? chnl_ctrl_in31 : (reg_addr == hw_address_ctrl_in32) ? chnl_ctrl_in32 : (reg_addr == hw_address_ctrl_in33) ? chnl_ctrl_in33 : (reg_addr == hw_address_ctrl_in34) ? chnl_ctrl_in34 : (reg_addr == hw_address_ctrl_in35) ? chnl_ctrl_in35 : (reg_addr == hw_address_ctrl_in36) ? chnl_ctrl_in36 : (reg_addr == hw_address_ctrl_in37) ? chnl_ctrl_in37 : (reg_addr == hw_address_ctrl_in38) ? chnl_ctrl_in38 : (reg_addr == hw_address_ctrl_in39) ? chnl_ctrl_in39 : (reg_addr == hw_address_ctrl_in40) ? chnl_ctrl_in40 : (reg_addr == hw_address_ctrl_in41) ? chnl_ctrl_in41 : (reg_addr == hw_address_ctrl_in42) ? chnl_ctrl_in42 : (reg_addr == hw_address_ctrl_in43) ? chnl_ctrl_in43 : (reg_addr == hw_address_ctrl_in44) ? chnl_ctrl_in44 : (reg_addr == hw_address_ctrl_in45) ? chnl_ctrl_in45 : (reg_addr == hw_address_ctrl_in46) ? chnl_ctrl_in46 : (reg_addr == hw_address_ctrl_in47) ? chnl_ctrl_in47 : (reg_addr == hw_address_ctrl_in48) ? chnl_ctrl_in48 : (reg_addr == hw_address_ctrl_in49) ? chnl_ctrl_in49 : (reg_addr == hw_address_ctrl_in50) ? chnl_ctrl_in50 : (reg_addr == hw_address_ctrl_in51) ? chnl_ctrl_in51 : (reg_addr == hw_address_ctrl_in52) ? chnl_ctrl_in52 : (reg_addr == hw_address_ctrl_in53) ? chnl_ctrl_in53 : 16'h0000; endmodule `timescale 1 ps / 1 ps module stratixiv_hssi_cmu_dprio_chnl_top (mdio_rst, mdio_wr, reg_addr, mdc, mbus_in, serial_mode, mdio_dis, pma_cram_test, ser_shift_load, si, csr_chnl_in, csr_chnl_in_reserved, dprio_chnl_id, dp_chnl_out, dp_chnl_out_reserved, so, mbus_out ); input mdio_rst; // DPRIO reset input input mdio_wr; // DPRIO register write enable input [15:0] reg_addr; // DPRIO register address from SM input mdc; // DPRIO clock input [15:0] mbus_in; // DPRIO data in from SM input serial_mode; // DPRIO serial mode enable input mdio_dis; // DPRIO disable signal (using CSR input) input pma_cram_test; // For TE/PE increased coverage for PMA DPRIO cell input ser_shift_load; // DPRIO serial shift or load control signal input si; // DPRIO serial input input [3:0] dprio_chnl_id; // DPRIO channel base address ID, tells which channel/central DPRIO // register is located input [831:0] csr_chnl_in; // CSR inputs input [15:0] csr_chnl_in_reserved; // CSR input, reserved but needed for reye_monitor //wire [15:0] csr_chnl_in_reserved; // CSR input, reserved but needed for reye_monitor output [831:0] dp_chnl_out; // CSR inputs output [15:0] dp_chnl_out_reserved; // reserved but needed for reye_monitor output so; // DPRIO serial out output[15:0] mbus_out; // DPRIO dataout ////////////////////////////////////////////////////////////////////////// // begin of CRAM output ------------------------------------------------- ////////////////////////////////////////////////////////////////////////// // CRAM output // TX PCS CRAMs wire rforce_kchar; // Force /K/ char CRAM wire rforce_echar; // Force /E/ char CRAM wire rtxfifo_dis; // TX FIFO disable CRAM wire rib_force_disp; // Disparity force CRAM in IB mode wire rtxfifo_lowlatency_en; // TX FIFO low latency enable CRAM wire rdwidth_tx; // TX parallel interface data width CRAM wire rge_xaui_tx; // GIGE Idle test enable CRAM wire rphfifopldentx; // TX phase comp. FIFO PLD read/write enable CRAM wire rphfifoursttx; // TX phase comp. FIFO user reset enable CRAM wire rtxurstpcs; // TX PCS user reset enable CRAm wire rfreerun_tx; // TX_CLK out free running during TX PCS reset enable CRAM wire rtxwrclksel; // TX FIFO write clock selection CRAM wire rtxrdclksel; // TX FIFO read clock selection CRAM wire rrev_loopbk; // CRAM - Enable dynamic Reverse, PIPE mode wire rforce_disp; // Acting with TXD[9, 19] forces current disparity to 1 or 0 wire rendec_tx; // Enable 8B/10B encoder CRAM wire r8b10b_enc_ibm_en; // 8B10B Encoder fix enable CRAM wire rcascaded_8b10b_en_tx; // Caascaded 8b/10b encoder enable CRAM wire rensymswap_tx; // TX symbol swap enable CRAM wire renpolinv_tx; // TX Polarity inversion enable CRAM wire renbitrev_tx; // TX bit reversal enable CRAM wire rprbsen_tx; // PRBS generator enable CRAM wire [2:0] rprbs_sel; // PRBS selection CRAM wire rbisten_tx; // BIST generator enable CRAM wire [1:0] rbist_sel; // BIST selection CRAM wire [1:0] rcxpat_chnl_en; // CRPAT or CJPAT selection CRAM wire rtxpcsbypass_en; // Bypass TX PCS CRAM wire rtx_pipe_enable; // TX PIPE interface enable CRAM wire [2:0] rtx_idle_delay; // PIPE TxElecIdle delay value CRAM wire rtxswing_sel_ena; // Txswing select enable CRAM wire rtxpcsclkpwdn; // Enables/Disables all clocks to TX PCS wire rcid_pattern_tx; // Select CID pattern to be 0 or 1 wire [7:0] rcid_len_tx; // Length of CID pattern in cycles wire rself_sw_en_tx; // En/Disable self switch circuit for clk divider in TX clk circuit wire rpipeline_bypass_tx; // Use/Don't use pipeline registers for TX inter-quad signals wire rphfifo_regmode_tx; // Enable TX phase comp register mode wire rtxbitslip_en; // 1: Enable TX bitslip for CPRI, 0: Normal operation (default) // RX PCS CRAMs wire rrxurstpcs; // RX PCS user reset enable CRAm wire rfreerun_rx; // RX_CLK out free running during RX PCS reset enable CRAM wire [1:0] rrcvd_clk_sel; // RCVD_CLK domain selection CRAM wire [1:0] rclk_1_sel; // CLK_1 domain selection CRAM wire [1:0] rclk_2_sel; // CLK_2 domain selection CRAM wire rrx_rd_clk_sel; // RX FIFO read clock selection CRAM wire rprbsen_rx; // PRBS Verifier enable CRAM wire rprbs_clr_rslt_rx; // PRBS pass/fail flag clear CRAM wire rbisten_rx; // BIST Verifier enable CRAM wire rbist_clr_rx; // BIST pass/fail flag clear CRAM wire rall_one_dect_only; // PRBS Verifier detect all one only enable CRAM wire rrxpcsbypass_en; // RX PCS bypass CRAM wire [1:0] resync_badcg_en; // wire rencdt_rising; // encdt on rising edge enable CRAM wire rdis_rx_disp; // Receive running disparity calculation disable CRAM wire rcomp_pat_porn; // Positive and negative match enable CRAM wire [2:0] rcomp_size; // Pattern comparision length CRAMs wire [39:0] rcomp_pat; // Sync pattern CRAMs wire rsync_sm_dis; // GIGE/XAUI Sync SM disable CRAM wire [1:0] rib_inv_cd; // Invalid code setting CRAMs for IB wire [5:0] renumber; // Number of consecutive errors without valid data to goto LOSS_OF_SYNC wire rkchar; // use kchar at cg_bad logic calculation wire rosbased; // Enable ordered-set based algorithm wire [1:0] rosnumber; // Length of the ordered set wire rwa_6g_en; // 6G word alignment enable CRAM wire rbysync_polinv_en; // Word alignment polarity inversion enable CRAM wire rbitloc_rev_en; // Bit reversal enable CRAM wire [7:0] rgnumber; // Number of consecutive good data to approach SYNC_ACQ wire [7:0] rknumber; // Number of consecutive commas to reach SYNC_ACQ from LOSS_OF_SYNC wire [5:0] rrundisp; // Run lengh violation setting CRAMs wire rbyte_rev_en; // Byte swap enable CRAM wire rforce_sig_det_pcs; // Forcing sigdet to high in PCS CRAM wire rlp20ben; // 20-b loopback enable CRAM wire rrlv_en; // RLV enable CRAM wire rautobtalg_dis; // BITSLIP mode enable CRAM wire rendec_rx; // 10B/8B decoder enable CRAM wire [1:0] r8b10b_dec_ibm_en; // 8B10B Decoder fix enable CRAM wire rcascaded_8b10b_en_rx; // Cascaded 8B/10B decoder enable CRAM wire renpolinv_rx; // Allow polarity inversion wire rmatchen; // Clock compensation enable CRAM wire rgenericfifo; // GenericFIFO mode enable CRAM wire rskpsetbased; // Enable rate matching for PCI-E/PIPE, other standards based on COMMA DEL DEL.. wire rtruebac2bac; // Enabled (high) for all standards except PIPE. Back to back rate match enable. wire rclkcmpinsertpad; // Rate matching pad insertion enable CRAM wire rclkcmpsqmd; // How many characters to match wire [19:0] rclkcmpsq1p; // Programmable 20-bit encoded comp sequence pos. disp. wire [19:0] rclkcmpsq1n; // Programmable 20-bit encoded comp sequence neg. disp. wire rclkcmp_pipe_en; // RM FIFO Pipe-compatible mode enable CRAM wire [4:0] rins_threshold; // Rate Match FIFO programmable insertion threshold CRAMs wire [4:0] rdel_threshold; // Rate Match FIFO programmable delettion threshold CRAMs wire [4:0] rfull_threshold; // Rate Match FIFO programmable full condition threshold CRAMs wire [2:0] rempty_threshold; // Rate Match FIFO programmable empty condition threshold CRAMs wire [2:0] rstart_threshold; // Rate Match FIFO programmable start point CRAMs wire [17:0] rpma_done_count; // Programmable counter threshold for pma_done_int (1ms) wire rpma_done_gen_ena; // Enable/Disable internal generation of PMA_DONE wire rhip_ena; // Enable/Disable Hard IP wire rauto_speed_ena; // Enable/Disable Auto Speed Negotiation wire rfreq_sel; // 1: Frequency Scaling, 0: Data width scaling wire rrxfifo_dis; // RX FIFO bypassing CRAM wire rrxfifo_lowlatency_en; // RX FIFO low latency enable CRAM wire rdwidth_rx; // RX parallel interface data width selection CRAM wire rphfifourstrx; // Enable phfifourst_rx wire rcmpfifourst; // Enable cmpfifourst wire rinvalid_code_err_only;// enable error (EDB) replacement only on invalid code-group in RX FIFO wire rbytord_2sym_en; // Enable 2 symbols byte orderring CRAM wire [1:0] rbyteorden; // Byte ordering enable CRAM wire rbytordplden; // PLD control signal BYTEORDPLD enable CRAM wire rphfifopldenrx; // RX phase comp. FIFO read/write enable CRAM wire rautoinsdis; // Disable CRAM for auto insertion of 8'h9C wire [3:0] rtest_bus_sel; // Per channel test bus selection CRAMs wire [19:0] rbytordpat; // Byte ordering pattern CRAM wire [9:0] rbytordpad; // Byte ordering pad pattern CRAM wire rrx_pipe_enable; // RX PIPE interface enable CRAM wire rrx_detect_bypass; // PMA RX detection bypass enable CRAM wire rind_error_reporting; // Enable individual reporting for rxstatus in 8b/10b error and disparity error wire [2:0] rphystatus_delay; // Programmable dleay for the PHYSTATUS flag when power transtition wire reidleinferenable; // Enable Electrical Idle inference module wire rk285detect; // Enable detection of K28.7 in PMA for EIdle exit wire [1:0] reidle_com_detect; // Thet number of COMs required to enter/exit EIdle wire rphystatus_rst_toggle; // Enable option for PIPE PHY_STATUS wire toggle upon exitting reset wire [4:0] rload_shreg_del; // Programmable delay to allow for loading of the shadow registers before re-enabling the clock driving the PCS logic wire rerr_flags_sel; // Choose values for disparity error, invalid code, and disp err value from either WA (0) or 8b/10b (1) wire rrxpcsclkpwdn; // Enables/Disables all clocks to RX PCS wire rcdr_ctrl_en; // Enable/Disable CDR control block wire rbytord_s2gx; // 0: S4GX Byte ordering (trigger on every WA lock), 1: S2GX BO behavior wire rbytord_6g_mask_en; // 0: 6G BO normal operation, 1: mask out upper byte wire [7:0] rwait_count; // Minimum programmable period of time that LTR is asserted when CDR is enabled wire [5:0] rwait_for_phfifo_cnt; // Counter timeout value to delay disabling of phase comp FIFO after rate change wire [9:0] rfts_count; // Programmable timer during which CDR control block controls PPM detector wire rpcs_wrapback_en; // Enables PCS Wrapback mode wire rcid_pattern_rx; // Select CID pattern to be 0 or 1 wire [7:0] rcid_len_rx; // Length of CID pattern in cycles wire rppm_meas_delay; // 0: Wait 200, 1: Wait 400 cycles before starting post-eidle-exit PPM measurement wire rphfifo_regmode_rx; // Enable RX phase comp register mode wire rcid_en; // PIPE only, enable generation of early_eios by CDR to place in protected CID mode wire rrxvalid_mask; // PIPE only, enables masking of rxvalid by CDR control block wire rself_sw_en_rx; // En/Disable self switch circuit for clk divider in TX clk circuit wire rpipeline_bypass_rx; // Use/Don't use pipeline registers for TX inter-quad signals wire [3:0] rauto_deassert_pc_rst_cnt; // Programmable counter threshold for timing to release sync reset to PC ptrs wire [4:0] rauto_pc_en_cnt; // Programmable counter threshold for timing to delay phystatus notification to upper layer wire riei_eios_priority_dis;// Disable EIOS detection priority over EIdle Inference when EIdle Inference is enabled wire rgen1_sigdet_ena; // Usage of signal detect under Gen 1 conditions when EIdle Inference is enabled wire [9:0] rmask_count; // Programmable counter to mask out the high bit error period upon exiting electrical // idle in terms of number of gen1 cycles //////////////// // TX PMA CRAMs //////////////// wire [2:0] rvod_sel_non_pcie; // TX wire buffer Vod switching control CRAMs wire [2:0] rvod_sela; wire [2:0] rvod_selb; wire [2:0] rvod_selc; wire [2:0] rvod_seld; wire rpowdnt; // TX channel power down CRAM wire [4:0] rpre_em_1t_no_pcie; // TX wire buffer pre-emphasis switching control for 1st post tap wire [4:0] rpre_em_1t_a; wire [4:0] rpre_em_1t_b; wire [4:0] rpre_em_1t_c; wire [3:0] rpre_em_2t; // TX wire buffer pre-emphasis switching control for 2nd post tap wire [3:0] rpre_em_pt; // TX wire buffer pre-emphasis switching control for pre-tap wire [2:0] rtx_term_sel; // TX's Differential Termination selction CRAMs wire [1:0] rtx_vtt; // TX's Common-mode driver selection control CRAMs wire [3:0] rtx_lst; // Low Speed Test Selection CRAMs. wire [1:0] rslew; // Slew rate control for TX wire rsig_inv_ptap; // Signal invert for Pre-tap wire rsig_inv_2t; // Signal invert for 2nd Post tap wire [1:0] rrx_det; // RAM bit for RX signal detect wire rlowv; // 0: cascaded current source/sink, 1: bypass cascaded current source/sink wire [2:0] r_dft_sel; // Design for testing selection to check decoder outputs of main tap, 1st post tap, 2nd // post tap, and pre-tap wire rtx_ob_pdb; // TX Power down CRAM (1: normal operation, 0: power down) //Serializer - Clock Generation Block (SER-CGB) CRAMs wire [1:0] rcgb_x_en; // Single channel mode (X1 mode) enable CRAM (individual clock drives individual Serializer) wire rcgb_cmu_sel; // CMU selection CRAM in CLKGENBUF_6G block wire [1:0] rcgb_m_sel; // Division ratio selection CRAM for input clock in CLKGENBU /net/grouse/nobackup F_6G block wire rpma_doublewidth_tx; // TX PCS to TX PMA double data width (16/20) enable CRAM (S2GX RPMA_DOUBLEWIDTH_TX) wire rpmadwidth_tx; // TX PCS to TX PMA data width (8/10)selection CRAM (S2GX RPMADWIDTH_TX) wire rcgb_delay_sel; // Insert 6 gates delay CRAM for CLKMUX in TX channel wire rs_lpbk; // reverse loop back control CRAM wire rdynamic_sw; // 0: disable dynamic switch, 1: enable dynamic switch wire rpclksel; // 0: select local pclk, 1: select global pclk wire rtx_cgb_pdb; // Power down CRAM for CLKGENBUF, CLKMUX, and Serializer in TX channel (1: normal operation) //C_TX_RX CRAMs wire [1:0] riqclk_sel; // RX path CLKMUX selection CRAM to select either iqclk or pldclk wire [1:0] rrefclk_sel; // RX path REFCLKMUX selection CRAM wire rvcobypass; // RX clock selection sent to PCS wire rrevlb_sw; // Switch select signal for TX_RLPBK wire rimpctrl; // Control calibration bi-direction buffer wire rrx_refclk; // RAM bit to choose RX clock to train CDR wire rpcs_sd_sel; // 0: select analog signal detect output, 1: select digital signal detect output //Reserved CRAMs for TX PMA and RX PMA wire [31:0] rpma_reserved; //Reserved bits for RX/TX PMA channel divided into 2 sixteen bit busses //End TX CRAMs //////////////// // RX PMA CRAMs //////////////// wire [4:0] rrx_lst; // ATB Control Bits (refer to ATB table for details) wire [3:0] rrx_bit_dc; // Select pin for DC gain 0db, 3db, 6db, 9db and 12 db wire rrx_s_rdlpbk; // Loopback control pin wire [2:0] rrx_vtt; // Control bits for common mode driver wire [2:0] rrx_term_sel; // RX's Differential Termination selection CRAMs wire [3:0] rrx_sdlv; // Control bits for Signal Detect hysteresis (TBD) wire rrx_oc_en; // Offset Cancellation control (TBD) wire [7:0] rrx_oc; // Offset Cancellation control (TBD) wire rrx_sd_force; // Signal detect override wire rrx_test; // Loopback to test ADCE and EQ stages wire rrxurstpma; // Enable CRAM for RXURSTPMA dynamic signal wire [3:0] rrx_sd_on; // Control bits for Signal Detect wire [4:0] rrx_sd_off; // Control bits for Signal Detect wire rrx_oc_calpd; // Offset cancellation calibration mode wire rurx_pdb; // RX/DFE power down wire rrx_ib_pdb; // RX Power down CRAM (1: normal operation, 0: power down) wire rpowdnr; // RX channel power down CRAM // CDR CRAMs wire rcru_div2; // Reference clock divided by two enable CRAMS wire [1:0] rcru_m_sel; // Division ratio selection of input clock wire [3:0] rcru_m; // Programmable Control. Select among 1,4,5,8,10,16,20 and 25. wire [1:0] rcru_l; // Programmable Control. Select among 1,2, and 4. wire rcru_ctl0; // CTL0 is Programmable Control CRAMs for Ring VCO frequency range control wire [1:0] rcru_crplctrl; // Ripple capacitor control CRAM: wire [1:0] rcru_pfdbwctrl; // RXPLL PFD mode BW control CRAMS (resistor control in loop filter for PFD mode) wire [1:0] rcru_pdbwctrl; // RXPLL PD mode BW control CRAMS (resistor control in loop filter for PD mode) wire rcru_rlbk; // Enable reverse serial loopback from RX CDR to TX wire buffer with main tab wire [3:0] rcru_lst; // Low speed test selection CRAM wire rcru_testen; // Charge Pump Current test mode control CRAM in RXPLL wire rcru_testupen; // Charge Pump UP current test control CRAM in RXPLL wire rcru_testdnen; // Charge Pump DOWN current test control CRAM in RXPLL wire [2:0] rcru_isel; // RXPLL charge pump current control CRAM wire [2:0] rcru_iselpd; // Charge pump current control CRAM at PD mode wire rcp_mode; // Charge pump mode select CRAM wire rltd; // Lock to Data enable signal (0: normal operation) wire rltr; // Lock to Reference enable signal (0: normal operation) wire rrx_cru_pdb; // Power down CRAM for CRU in RX channel (1: normal operation) wire rrx_cru_rst; // CRU reset CRAM (1: normal operation) wire rcru_cmu_mode; // Used to disable the buffers in the L-counter when the CDR is configured just as a // TXPLL wire rcru_ignore_phslck; // Used in LCK2REFCTRL block that will override Lock Detect outcome wire rcru_sd_sel; // Select signal detect wire either from analog signal detect or digital signal detect blocks for CDR wire rcru_pdfl; // Fast Lock control. Use when the data is suddently switched to a different phase (esp 90 degree out of phase) wire [2:0] rcru_pdof_test; // These RAM bits are used to characterize the offset of SALATCHs inside the BBPD wire [2:0] rcru_rgla_isel; // Increase 1.8V regulator wire voltage. wire [3:0] rcru_pdof_0i; // BBPD SALATCH offset control. Latch connects to CLK0. Choose either Left or Right, not both. wire [3:0] rcru_pdof_90i; // BBPD SALATCH offset control. Latch connects to CLK90. Choose either Left or Right, not both. wire [3:0] rcru_pdof_180i; // BBPD SALATCH offset control. Latch connects to CLK180. Choose either Left or Right, not both. wire [3:0] rcru_pdof_270i; // BBPD SALATCH offset control. Latch connects to CLK270. Choose either Left or Right, not both. wire [7:0] reye_monitor; //Reserved CRAMs for RX PMA (declared above) //wire [15:0] rpma_reserved[15:0]; //Reserved bits for RX PMA channel //DeSerializer CRAMs wire rpma_doublewidth_rx; // RX PMA to RX PCS double data width (16/20) enable CRAM (S2GX RPMA_DOUBLEWIDTH_RX) wire rpmadwidth_rx; // RX PMA to RX PCS data width (8/10) selection CRAM (S2GX RPMADWIDTH_RX) wire rtest_fastsd; // Mux select between Fast SD circuit and Test signal wire [3:0] rfastsd; // Controls Fast Signal Detect Logic wire [5:0] rppmsel; // Programmable PPM ajustment CRAM wire rforce0_freqdet; // Forcing FREQDET signal to low CRAM wire rforce1_freqdet; // Forcing FREQDET signal to high CRAM wire rppm_cnt_reset; // PPM counter reset CRAM (latched version on Test bus) //DFE CRAMs wire [2:0] r_dfe_1t; // DFE 1st tap setting wire [2:0] r_dfe_2t; // DFE 2nd tap setting wire rppm_post_eidle_del; wire rppm_gen1_2xcnt_en; //ADCE CRAMs wire [2:0] reqa_set; wire [2:0] reqb_set; wire [2:0] reqc_set; wire [2:0] reqd_set; wire [2:0] reqv_set; wire rlock_lf_ovd; // Overdrive the dependency of ADAPT_DONE on low-frequency path wire [1:0] rseq_sel; // Used to select the sequence of adaptation (these bits for characterization only) wire radce_adapt; // This signal is used in conjunction with ADCE_PDB wire [2:0] rrgen_set; // These are the 3 MSB bits controlling the D2A wire [3:0] rclkdiv; // Effective division ratio for LFCLK and HFCLK wire [2:0] rhyst_lf; // Sets low-frequency path programmable digital filtering. When set to 000 the digital filter is bypassed. wire [1:0] rdc_freq; // Sets corner frequency for the DC block. wire [2:0] rhyst_hf; // Sets high-frequency path programmable digital filtering. When set to 000 the digital filter is bypassed. wire [1:0] rf_lpf; // Sets corner frequency for the LPF. wire [1:0] rf_hpf; // Sets corner frequency for the HPF. wire [2:0] rrgen_vod; // Sets RGEN amplitude wire [1:0] rrgen_bw; // Sets corner frequency of RGEN. wire [1:0] rrect_adj; // Sets rectifier leaker and amplifier current. wire [1:0] rd2a_res; // Sets the D2A resolution. Default is 8 bit resolution. Adaptation time may be faster for lower resolution, but jitter may be increased. wire [3:0] rlf_os; // These bits are for characterization purposes only. These bits will allow cancellation of systematic offset in the low frequency loop wire [3:0] rhf_os; // These bits are for characterization purposes only. These bits will allow cancellation of systematic offset in the high frequency loop. wire radce_rst; // Presets counters in adaptive engine wire radce_pdb; // Used in conjunction with RADCE_ADAPT wire [14:0] radce_hflck; // These bits are used in the HF portion of the adapt macro wire [14:0] radce_lflck; // These bits are used in the adapt_done macro wire [9:0] radce_digital; // Reserved bits //End RX CRAMs ////////////////////////////////////////////////////////////////////////// // end of CRAM output --------------------------------------------------- ////////////////////////////////////////////////////////////////////////// wire [15:0] targ_addr_ctrl_1; wire [15:0] targ_addr_ctrl_2; wire [15:0] targ_addr_ctrl_3; wire [15:0] targ_addr_ctrl_4; wire [15:0] targ_addr_ctrl_5; wire [15:0] targ_addr_ctrl_6; wire [15:0] targ_addr_ctrl_7; wire [15:0] targ_addr_ctrl_8; wire [15:0] targ_addr_ctrl_9; wire [15:0] targ_addr_ctrl_10; wire [15:0] targ_addr_ctrl_11; wire [15:0] targ_addr_ctrl_12; wire [15:0] targ_addr_ctrl_13; wire [15:0] targ_addr_ctrl_14; wire [15:0] targ_addr_ctrl_15; wire [15:0] targ_addr_ctrl_16; wire [15:0] targ_addr_ctrl_17; wire [15:0] targ_addr_ctrl_18; wire [15:0] targ_addr_ctrl_19; wire [15:0] targ_addr_ctrl_20; wire [15:0] targ_addr_ctrl_21; wire [15:0] targ_addr_ctrl_22; wire [15:0] targ_addr_ctrl_23; wire [15:0] targ_addr_ctrl_24; wire [15:0] targ_addr_ctrl_25; wire [15:0] targ_addr_ctrl_26; wire [15:0] targ_addr_ctrl_27; wire [15:0] targ_addr_ctrl_28; wire [15:0] targ_addr_ctrl_29; wire [15:0] targ_addr_ctrl_30; wire [15:0] targ_addr_ctrl_31; wire [15:0] targ_addr_ctrl_32; wire [15:0] targ_addr_ctrl_33; wire [15:0] targ_addr_ctrl_34; wire [15:0] targ_addr_ctrl_35; wire [15:0] targ_addr_ctrl_36; wire [15:0] targ_addr_ctrl_37; wire [15:0] targ_addr_ctrl_38; wire [15:0] targ_addr_ctrl_39; wire [15:0] targ_addr_ctrl_40; wire [15:0] targ_addr_ctrl_41; wire [15:0] targ_addr_ctrl_42; wire [15:0] targ_addr_ctrl_43; wire [15:0] targ_addr_ctrl_44; wire [15:0] targ_addr_ctrl_45; wire [15:0] targ_addr_ctrl_46; wire [15:0] targ_addr_ctrl_47; wire [15:0] targ_addr_ctrl_48; wire [15:0] targ_addr_ctrl_49; wire [15:0] targ_addr_ctrl_50; wire [15:0] targ_addr_ctrl_51; wire [15:0] targ_addr_ctrl_52; wire [15:0] targ_addr_ctrl_53; wire [15:0] out_chnl_ctrl_1; wire [15:0] out_chnl_ctrl_2; wire [15:0] out_chnl_ctrl_3; wire [15:0] out_chnl_ctrl_4; wire [15:0] out_chnl_ctrl_5; wire [15:0] out_chnl_ctrl_6; wire [15:0] out_chnl_ctrl_7; wire [15:0] out_chnl_ctrl_8; wire [15:0] out_chnl_ctrl_9; wire [15:0] out_chnl_ctrl_10; wire [15:0] out_chnl_ctrl_11; wire [15:0] out_chnl_ctrl_12; wire [15:0] out_chnl_ctrl_13; wire [15:0] out_chnl_ctrl_14; wire [15:0] out_chnl_ctrl_15; wire [15:0] out_chnl_ctrl_16; wire [15:0] out_chnl_ctrl_17; wire [15:0] out_chnl_ctrl_18; wire [15:0] out_chnl_ctrl_19; wire [15:0] out_chnl_ctrl_20; wire [15:0] out_chnl_ctrl_21; wire [15:0] out_chnl_ctrl_22; wire [15:0] out_chnl_ctrl_23; wire [15:0] out_chnl_ctrl_24; wire [15:0] out_chnl_ctrl_25; wire [15:0] out_chnl_ctrl_26; wire [15:0] out_chnl_ctrl_27; wire [15:0] out_chnl_ctrl_28; wire [15:0] out_chnl_ctrl_29; wire [15:0] out_chnl_ctrl_30; wire [15:0] out_chnl_ctrl_31; wire [15:0] out_chnl_ctrl_32; wire [15:0] out_chnl_ctrl_33; wire [15:0] out_chnl_ctrl_34; wire [15:0] out_chnl_ctrl_35; wire [15:0] out_chnl_ctrl_36; wire [15:0] out_chnl_ctrl_37; wire [15:0] out_chnl_ctrl_38; wire [15:0] out_chnl_ctrl_39; wire [15:0] out_chnl_ctrl_40; wire [15:0] out_chnl_ctrl_41; wire [15:0] out_chnl_ctrl_42; wire [15:0] out_chnl_ctrl_43; wire [15:0] out_chnl_ctrl_44; wire [15:0] out_chnl_ctrl_45; wire [15:0] out_chnl_ctrl_46; wire [15:0] out_chnl_ctrl_47; wire [15:0] out_chnl_ctrl_48; wire [15:0] out_chnl_ctrl_49; wire [15:0] out_chnl_ctrl_50; wire [15:0] out_chnl_ctrl_51; wire [15:0] out_chnl_ctrl_52; wire [15:0] out_chnl_ctrl_53; ////////////////////////////////////////////////////////////////////////// // begin of CRAM output ------------------------------------------------- ////////////////////////////////////////////////////////////////////////// assign dp_chnl_out[15:0] = out_chnl_ctrl_1; assign dp_chnl_out[31:16] = out_chnl_ctrl_2; assign dp_chnl_out[47:32] = out_chnl_ctrl_3; assign dp_chnl_out[63:48] = out_chnl_ctrl_4; assign dp_chnl_out[79:64] = out_chnl_ctrl_5; assign dp_chnl_out[95:80] = out_chnl_ctrl_6; assign dp_chnl_out[111:96] = out_chnl_ctrl_7; assign dp_chnl_out[127:112] = out_chnl_ctrl_8; assign dp_chnl_out[143:128] = out_chnl_ctrl_9; assign dp_chnl_out[159:144] = out_chnl_ctrl_10; assign dp_chnl_out[175:160] = out_chnl_ctrl_11; assign dp_chnl_out[191:176] = out_chnl_ctrl_12; assign dp_chnl_out[207:192] = out_chnl_ctrl_13; assign dp_chnl_out[223:208] = out_chnl_ctrl_14; assign dp_chnl_out[239:224] = out_chnl_ctrl_15; assign dp_chnl_out[255:240] = out_chnl_ctrl_16; assign dp_chnl_out[271:256] = out_chnl_ctrl_17; assign dp_chnl_out[287:272] = out_chnl_ctrl_18; assign dp_chnl_out[303:288] = out_chnl_ctrl_19; assign dp_chnl_out[319:304] = out_chnl_ctrl_20; assign dp_chnl_out[335:320] = out_chnl_ctrl_21; assign dp_chnl_out[351:336] = out_chnl_ctrl_22; assign dp_chnl_out[367:352] = out_chnl_ctrl_23; assign dp_chnl_out[383:368] = out_chnl_ctrl_24; assign dp_chnl_out[399:384] = out_chnl_ctrl_25; assign dp_chnl_out[415:400] = out_chnl_ctrl_26; assign dp_chnl_out[431:416] = out_chnl_ctrl_27; assign dp_chnl_out[447:432] = out_chnl_ctrl_28; assign dp_chnl_out[463:448] = out_chnl_ctrl_29; assign dp_chnl_out[479:464] = out_chnl_ctrl_30; assign dp_chnl_out[495:480] = out_chnl_ctrl_31; assign dp_chnl_out[511:496] = out_chnl_ctrl_32; assign dp_chnl_out[527:512] = out_chnl_ctrl_33; assign dp_chnl_out[543:528] = out_chnl_ctrl_34; assign dp_chnl_out[559:544] = out_chnl_ctrl_35; assign dp_chnl_out[575:560] = out_chnl_ctrl_36; assign dp_chnl_out[591:576] = out_chnl_ctrl_37; assign dp_chnl_out[607:592] = out_chnl_ctrl_38; assign dp_chnl_out[623:608] = out_chnl_ctrl_39; assign dp_chnl_out[639:624] = out_chnl_ctrl_40; assign dp_chnl_out[655:640] = out_chnl_ctrl_41; assign dp_chnl_out[671:656] = out_chnl_ctrl_42; assign dp_chnl_out_reserved = out_chnl_ctrl_43; // Table43 not part of csr regular assign dp_chnl_out[687:672] = out_chnl_ctrl_44; assign dp_chnl_out[703:688] = out_chnl_ctrl_45; assign dp_chnl_out[719:704] = out_chnl_ctrl_46; assign dp_chnl_out[735:720] = out_chnl_ctrl_47; assign dp_chnl_out[751:736] = out_chnl_ctrl_48; assign dp_chnl_out[767:752] = out_chnl_ctrl_49; assign dp_chnl_out[783:768] = out_chnl_ctrl_50; assign dp_chnl_out[799:784] = out_chnl_ctrl_51; assign dp_chnl_out[815:800] = out_chnl_ctrl_52; assign dp_chnl_out[831:816] = out_chnl_ctrl_53; ////////////////////////////////////////////////////////////////////////// // end of CRAM output --------------------------------------------------- ////////////////////////////////////////////////////////////////////////// // Control register address assignment // PCS channel address space assign targ_addr_ctrl_1 = {dprio_chnl_id,12'h000} + 16'h0000; assign targ_addr_ctrl_2 = {dprio_chnl_id,12'h000} + 16'h0001; assign targ_addr_ctrl_3 = {dprio_chnl_id,12'h000} + 16'h0002; assign targ_addr_ctrl_4 = {dprio_chnl_id,12'h000} + 16'h0003; assign targ_addr_ctrl_5 = {dprio_chnl_id,12'h400} + 16'h0000; assign targ_addr_ctrl_6 = {dprio_chnl_id,12'h400} + 16'h0001; assign targ_addr_ctrl_7 = {dprio_chnl_id,12'h400} + 16'h0002; assign targ_addr_ctrl_8 = {dprio_chnl_id,12'h400} + 16'h0003; assign targ_addr_ctrl_9 = {dprio_chnl_id,12'h400} + 16'h0004; assign targ_addr_ctrl_10 = {dprio_chnl_id,12'h400} + 16'h0005; assign targ_addr_ctrl_11 = {dprio_chnl_id,12'h400} + 16'h0006; assign targ_addr_ctrl_12 = {dprio_chnl_id,12'h400} + 16'h0007; assign targ_addr_ctrl_13 = {dprio_chnl_id,12'h400} + 16'h0008; assign targ_addr_ctrl_14 = {dprio_chnl_id,12'h400} + 16'h0009; assign targ_addr_ctrl_15 = {dprio_chnl_id,12'h400} + 16'h000A; assign targ_addr_ctrl_16 = {dprio_chnl_id,12'h400} + 16'h000B; assign targ_addr_ctrl_17 = {dprio_chnl_id,12'h400} + 16'h000C; assign targ_addr_ctrl_18 = {dprio_chnl_id,12'h400} + 16'h000D; assign targ_addr_ctrl_19 = {dprio_chnl_id,12'h400} + 16'h000E; assign targ_addr_ctrl_20 = {dprio_chnl_id,12'h400} + 16'h000F; assign targ_addr_ctrl_21 = {dprio_chnl_id,12'h400} + 16'h0010; assign targ_addr_ctrl_22 = {dprio_chnl_id,12'h400} + 16'h0011; assign targ_addr_ctrl_23 = {dprio_chnl_id,12'h400} + 16'h0012; assign targ_addr_ctrl_24 = {dprio_chnl_id,12'h400} + 16'h0013; assign targ_addr_ctrl_25 = {dprio_chnl_id,12'h400} + 16'h0014; assign targ_addr_ctrl_26 = {dprio_chnl_id,12'h400} + 16'h0015; assign targ_addr_ctrl_27 = {dprio_chnl_id,12'h400} + 16'h0016; // PMA channel address space assign targ_addr_ctrl_28 = {dprio_chnl_id,12'h800} + 16'h0000; assign targ_addr_ctrl_29 = {dprio_chnl_id,12'h800} + 16'h0001; assign targ_addr_ctrl_30 = {dprio_chnl_id,12'h800} + 16'h0002; assign targ_addr_ctrl_31 = {dprio_chnl_id,12'h800} + 16'h0003; assign targ_addr_ctrl_32 = {dprio_chnl_id,12'h800} + 16'h0004; assign targ_addr_ctrl_33 = {dprio_chnl_id,12'h800} + 16'h0005; assign targ_addr_ctrl_34 = {dprio_chnl_id,12'h800} + 16'h0006; assign targ_addr_ctrl_35 = {dprio_chnl_id,12'h800} + 16'h0007; assign targ_addr_ctrl_36 = {dprio_chnl_id,12'hC00} + 16'h0000; assign targ_addr_ctrl_37 = {dprio_chnl_id,12'hC00} + 16'h0001; assign targ_addr_ctrl_38 = {dprio_chnl_id,12'hC00} + 16'h0002; assign targ_addr_ctrl_39 = {dprio_chnl_id,12'hC00} + 16'h0003; assign targ_addr_ctrl_40 = {dprio_chnl_id,12'hC00} + 16'h0004; assign targ_addr_ctrl_41 = {dprio_chnl_id,12'hC00} + 16'h0005; assign targ_addr_ctrl_42 = {dprio_chnl_id,12'hC00} + 16'h0006; assign targ_addr_ctrl_43 = {dprio_chnl_id,12'hC00} + 16'h0007; assign targ_addr_ctrl_44 = {dprio_chnl_id,12'hC00} + 16'h0008; assign targ_addr_ctrl_45 = {dprio_chnl_id,12'hC00} + 16'h0009; assign targ_addr_ctrl_46 = {dprio_chnl_id,12'hC00} + 16'h000A; assign targ_addr_ctrl_47 = {dprio_chnl_id,12'hC00} + 16'h000B; assign targ_addr_ctrl_48 = {dprio_chnl_id,12'hC00} + 16'h000C; assign targ_addr_ctrl_49 = {dprio_chnl_id,12'hC00} + 16'h000D; assign targ_addr_ctrl_50 = {dprio_chnl_id,12'hC00} + 16'h000E; assign targ_addr_ctrl_51 = {dprio_chnl_id,12'hC00} + 16'h000F; assign targ_addr_ctrl_52 = {dprio_chnl_id,12'hC00} + 16'h0010; assign targ_addr_ctrl_53 = {dprio_chnl_id,12'hC00} + 16'h0011; // CRAM output assignment // TX PCS CRAMs // TX PCS Per channel control register 1 assign rforce_kchar =out_chnl_ctrl_1[15]; assign rforce_echar =out_chnl_ctrl_1[14]; assign rtxfifo_dis =out_chnl_ctrl_1[13]; assign rib_force_disp =out_chnl_ctrl_1[12]; assign rtxfifo_lowlatency_en=out_chnl_ctrl_1[11]; assign rdwidth_tx =out_chnl_ctrl_1[10]; assign rge_xaui_tx =out_chnl_ctrl_1[9]; assign rphfifopldentx =out_chnl_ctrl_1[8]; assign rphfifoursttx =out_chnl_ctrl_1[7]; assign rtxurstpcs =out_chnl_ctrl_1[5]; assign rfreerun_tx =out_chnl_ctrl_1[4]; assign rtxwrclksel =out_chnl_ctrl_1[3]; assign rtxrdclksel =out_chnl_ctrl_1[2]; assign rrev_loopbk =out_chnl_ctrl_1[1]; assign rforce_disp =out_chnl_ctrl_1[0]; // TX PCS Per channel control register 2 assign rendec_tx =out_chnl_ctrl_2[15]; assign r8b10b_enc_ibm_en =out_chnl_ctrl_2[14]; assign rcascaded_8b10b_en_tx=out_chnl_ctrl_2[13]; assign rensymswap_tx =out_chnl_ctrl_2[12]; assign renpolinv_tx =out_chnl_ctrl_2[11]; assign renbitrev_tx =out_chnl_ctrl_2[10]; assign rprbsen_tx =out_chnl_ctrl_2[9]; assign rprbs_sel =out_chnl_ctrl_2[8:6]; assign rbisten_tx =out_chnl_ctrl_2[5]; assign rbist_sel =out_chnl_ctrl_2[4:3]; assign rcxpat_chnl_en =out_chnl_ctrl_2[2:1]; assign rtxpcsbypass_en =out_chnl_ctrl_2[0]; // TX PCS Per channel control register 3 assign rtx_pipe_enable =out_chnl_ctrl_3[15]; assign rtx_idle_delay =out_chnl_ctrl_3[14:12]; assign rtxswing_sel_ena =out_chnl_ctrl_3[11]; assign rtxpcsclkpwdn =out_chnl_ctrl_3[10]; assign rcid_pattern_tx =out_chnl_ctrl_3[9]; assign rcid_len_tx =out_chnl_ctrl_3[8:1]; // TX PCS Per channel control register 4 assign rself_sw_en_tx =out_chnl_ctrl_4[15]; assign rpipeline_bypass_tx =out_chnl_ctrl_4[14]; assign rphfifo_regmode_tx =out_chnl_ctrl_4[13]; assign rtxbitslip_en =out_chnl_ctrl_4[12]; // RX PCS CRAMs // RX PCS Per channel control register 1 assign rrxurstpcs =out_chnl_ctrl_5[14]; assign rfreerun_rx =out_chnl_ctrl_5[13]; assign rrcvd_clk_sel =out_chnl_ctrl_5[12:11]; assign rclk_1_sel =out_chnl_ctrl_5[10:9]; assign rclk_2_sel =out_chnl_ctrl_5[8:7]; assign rrx_rd_clk_sel =out_chnl_ctrl_5[6]; assign rprbsen_rx =out_chnl_ctrl_5[5]; assign rprbs_clr_rslt_rx =out_chnl_ctrl_5[4]; assign rbisten_rx =out_chnl_ctrl_5[3]; assign rbist_clr_rx =out_chnl_ctrl_5[2]; assign rall_one_dect_only =out_chnl_ctrl_5[1]; assign rrxpcsbypass_en =out_chnl_ctrl_5[0]; // RX PCS Per channel control register 2 assign resync_badcg_en =out_chnl_ctrl_6[15:14]; assign rencdt_rising =out_chnl_ctrl_6[13]; assign rdis_rx_disp =out_chnl_ctrl_6[12]; assign rcomp_pat_porn =out_chnl_ctrl_6[11]; assign rcomp_size =out_chnl_ctrl_6[10:8]; assign rcomp_pat[39:32] =out_chnl_ctrl_6[7:0]; // RX PCS Per channel control register 3 assign rcomp_pat[31:16] =out_chnl_ctrl_7[15:0]; // RX PCS Per channel control register 4 assign rcomp_pat[15:0] =out_chnl_ctrl_8[15:0]; // RX PCS Per channel control register 5 assign rsync_sm_dis =out_chnl_ctrl_9[15]; assign rib_inv_cd =out_chnl_ctrl_9[14:13]; assign renumber =out_chnl_ctrl_9[12:7]; assign rkchar =out_chnl_ctrl_9[6]; assign rosbased =out_chnl_ctrl_9[5]; assign rosnumber =out_chnl_ctrl_9[4:3]; assign rwa_6g_en =out_chnl_ctrl_9[2]; assign rbysync_polinv_en =out_chnl_ctrl_9[1]; assign rbitloc_rev_en =out_chnl_ctrl_9[0]; // RX PCS Per channel control register 6 assign rgnumber =out_chnl_ctrl_10[15:8]; assign rknumber =out_chnl_ctrl_10[7:0]; // RX PCS Per channel control register 7 assign rrundisp =out_chnl_ctrl_11[15:10]; assign rbyte_rev_en =out_chnl_ctrl_11[9]; assign rforce_sig_det_pcs =out_chnl_ctrl_11[8]; assign rlp20ben =out_chnl_ctrl_11[7]; assign rrlv_en =out_chnl_ctrl_11[6]; assign rautobtalg_dis =out_chnl_ctrl_11[5]; assign rendec_rx =out_chnl_ctrl_11[4]; assign r8b10b_dec_ibm_en =out_chnl_ctrl_11[3:2]; assign rcascaded_8b10b_en_rx =out_chnl_ctrl_11[1]; assign renpolinv_rx =out_chnl_ctrl_11[0]; // RX PCS Per channel control register 8 assign rmatchen =out_chnl_ctrl_12[15]; assign rgenericfifo =out_chnl_ctrl_12[14]; assign rskpsetbased =out_chnl_ctrl_12[13]; assign rtruebac2bac =out_chnl_ctrl_12[12]; assign rclkcmpinsertpad =out_chnl_ctrl_12[11]; assign rclkcmpsqmd =out_chnl_ctrl_12[10]; assign rclkcmpsq1p[9:0] =out_chnl_ctrl_12[9:0]; // RX PCS Per channel control register 9 assign rclkcmpsq1p[19:10] =out_chnl_ctrl_13[9:0]; assign rclkcmpsq1n[19:15] =out_chnl_ctrl_13[15:11]; // RX PCS Per channel control register 10 assign rclkcmpsq1n[14:10] =out_chnl_ctrl_14[15:11]; assign rclkcmpsq1n[9:0] =out_chnl_ctrl_14[9:0]; // RX PCS Per channel control register 11 assign rclkcmp_pipe_en =out_chnl_ctrl_15[15]; assign rins_threshold =out_chnl_ctrl_15[14:10]; assign rdel_threshold =out_chnl_ctrl_15[9:5]; assign rfull_threshold =out_chnl_ctrl_15[4:0]; // RX PCS Per channel control register 12 assign rempty_threshold =out_chnl_ctrl_16[15:13]; assign rstart_threshold =out_chnl_ctrl_16[12:10]; assign rpma_done_count[17:16]=out_chnl_ctrl_16[5:4]; assign rpma_done_gen_ena =out_chnl_ctrl_16[3]; assign rhip_ena =out_chnl_ctrl_16[2]; assign rauto_speed_ena =out_chnl_ctrl_16[1]; assign rfreq_sel =out_chnl_ctrl_16[0]; // RX PCS Per channel control register 13 assign rrxfifo_dis =out_chnl_ctrl_17[15]; assign rrxfifo_lowlatency_en =out_chnl_ctrl_17[14]; assign rdwidth_rx =out_chnl_ctrl_17[13]; assign rphfifourstrx =out_chnl_ctrl_17[12]; assign rcmpfifourst =out_chnl_ctrl_17[11]; assign rinvalid_code_err_only=out_chnl_ctrl_17[10]; assign rbytord_2sym_en =out_chnl_ctrl_17[9]; assign rbyteorden =out_chnl_ctrl_17[8:7]; assign rbytordplden =out_chnl_ctrl_17[6]; assign rphfifopldenrx =out_chnl_ctrl_17[5]; assign rautoinsdis =out_chnl_ctrl_17[4]; assign rtest_bus_sel[3:0] =out_chnl_ctrl_17[3:0]; // RX PCS Per channel control register 14 assign rbytordpat[9:0] =out_chnl_ctrl_18[9:0]; // RX PCS Per channel control register 15 assign rbytordpad =out_chnl_ctrl_19[9:0]; // RX PCS Per channel control register 16 assign rrx_pipe_enable =out_chnl_ctrl_20[15]; assign rrx_detect_bypass =out_chnl_ctrl_20[14]; assign rind_error_reporting =out_chnl_ctrl_20[13]; assign rphystatus_delay =out_chnl_ctrl_20[12:10]; assign reidleinferenable =out_chnl_ctrl_20[9]; assign rk285detect =out_chnl_ctrl_20[8]; assign reidle_com_detect =out_chnl_ctrl_20[7:6]; assign rphystatus_rst_toggle =out_chnl_ctrl_20[5]; assign rload_shreg_del =out_chnl_ctrl_20[4:0]; // RX PCS Per channel control register 17 assign rpma_done_count[15:0] =out_chnl_ctrl_21[15:0]; // RX PCS Per channel control register 18 assign rerr_flags_sel =out_chnl_ctrl_22[15]; assign rrxpcsclkpwdn =out_chnl_ctrl_22[14]; assign rcdr_ctrl_en =out_chnl_ctrl_22[13]; assign rbytord_s2gx =out_chnl_ctrl_22[11]; assign rbytord_6g_mask_en =out_chnl_ctrl_22[10]; assign rbytordpat[19:10] =out_chnl_ctrl_22[9:0]; // RX PCS Per channel control register 19 assign rwait_count[7:0] =out_chnl_ctrl_23[7:0]; // RX PCS Per channel control register 20 assign rwait_for_phfifo_cnt[5:0]=out_chnl_ctrl_24[15:10]; assign rfts_count[9:0] =out_chnl_ctrl_24[9:0]; // RX PCS Per channel control register 21 assign rpcs_wrapback_en =out_chnl_ctrl_25[10]; assign rcid_pattern_rx =out_chnl_ctrl_25[9]; assign rcid_len_rx[7:0] =out_chnl_ctrl_25[8:1]; assign rppm_meas_delay =out_chnl_ctrl_25[0]; // RX PCS Per channel control register 22 assign rphfifo_regmode_rx =out_chnl_ctrl_26[15]; assign rcid_en =out_chnl_ctrl_26[14]; assign rrxvalid_mask =out_chnl_ctrl_26[13]; assign rself_sw_en_rx =out_chnl_ctrl_26[12]; assign rpipeline_bypass_rx =out_chnl_ctrl_26[11]; assign rauto_deassert_pc_rst_cnt[3:0] =out_chnl_ctrl_26[9:6]; assign rauto_pc_en_cnt[4:0] =out_chnl_ctrl_26[4:0]; // RX PCS Per channel control register 23 assign riei_eios_priority_dis=out_chnl_ctrl_27[11]; assign rgen1_sigdet_ena =out_chnl_ctrl_27[10]; assign rmask_count[9:0] =out_chnl_ctrl_27[9:0]; //End PCS CRAMs // TX PMA CRAMs // TX PMA Per channel control register 1 assign rvod_sel_non_pcie[2:0] =out_chnl_ctrl_28[15:13]; assign rvod_sela[2:0] =out_chnl_ctrl_28[12:10]; assign rvod_selb[2:0] =out_chnl_ctrl_28[9:7]; assign rvod_selc[2:0] =out_chnl_ctrl_28[6:4]; assign rvod_seld[2:0] =out_chnl_ctrl_28[3:1]; assign rpowdnt =out_chnl_ctrl_28[0]; // TX PMA Per channel control register 2 assign rpre_em_1t_no_pcie[4:0] =out_chnl_ctrl_29[15:11]; assign rpre_em_1t_a[4:0] =out_chnl_ctrl_29[10:6]; assign rpre_em_1t_b[4:0] =out_chnl_ctrl_29[5:1]; // TX PMA Per channel control register 3 assign rpre_em_1t_c[4:0] =out_chnl_ctrl_30[12:8]; assign rpre_em_2t[3:0] =out_chnl_ctrl_30[7:4]; assign rpre_em_pt[3:0] =out_chnl_ctrl_30[3:0]; // TX PMA Per channel control register 4 assign rtx_term_sel[2:0] =out_chnl_ctrl_31[15:13]; assign rtx_vtt[1:0] =out_chnl_ctrl_31[12:11]; assign rtx_lst[3:0] =out_chnl_ctrl_31[10:7]; assign rslew[1:0] =out_chnl_ctrl_31[6:5]; assign rsig_inv_ptap =out_chnl_ctrl_31[4]; assign rsig_inv_2t =out_chnl_ctrl_31[3]; assign rrx_det[1:0] =out_chnl_ctrl_31[2:1]; assign rlowv =out_chnl_ctrl_31[0]; // TX PMA Per channel control register 5 assign r_dft_sel[2:0] =out_chnl_ctrl_32[15:13]; assign rtx_ob_pdb =out_chnl_ctrl_32[11]; // TX PMA Per channel control register 6 assign rcgb_x_en[1:0] =out_chnl_ctrl_33[15:14]; assign rcgb_cmu_sel =out_chnl_ctrl_33[13]; assign rcgb_m_sel[1:0] =out_chnl_ctrl_33[12:11]; assign rpma_doublewidth_tx=out_chnl_ctrl_33[10]; assign rpmadwidth_tx =out_chnl_ctrl_33[9]; assign rcgb_delay_sel =out_chnl_ctrl_33[8]; assign rs_lpbk =out_chnl_ctrl_33[7]; assign rdynamic_sw =out_chnl_ctrl_33[6]; assign rpclksel =out_chnl_ctrl_33[5]; assign rtx_cgb_pdb =out_chnl_ctrl_33[4]; // TX PMA Per channel control register 7 assign riqclk_sel[1:0] =out_chnl_ctrl_34[15:14]; assign rrefclk_sel[1:0] =out_chnl_ctrl_34[13:12]; assign rvcobypass =out_chnl_ctrl_34[11]; assign rrevlb_sw =out_chnl_ctrl_34[10]; assign rimpctrl =out_chnl_ctrl_34[5]; assign rrx_refclk =out_chnl_ctrl_34[4]; assign rpcs_sd_sel =out_chnl_ctrl_34[3]; // TX PMA Per channel control register 8 assign rpma_reserved[31:16] =out_chnl_ctrl_35[15:0]; //RX PMA CRAMs // RX PMA Per channel control register 1 assign rrx_lst[4:0] =out_chnl_ctrl_36[15:11]; assign rrx_bit_dc[3:0] =out_chnl_ctrl_36[10:7]; assign rrx_s_rdlpbk =out_chnl_ctrl_36[6]; assign rrx_vtt[2:0] =out_chnl_ctrl_36[5:3]; assign rrx_term_sel[2:0] =out_chnl_ctrl_36[2:0]; // RX PMA Per channel control register 2 assign rrx_sdlv[3:0] =out_chnl_ctrl_37[15:12]; assign rrx_oc_en =out_chnl_ctrl_37[11]; assign rrx_oc[7:0] =out_chnl_ctrl_37[10:3]; assign rrx_sd_force =out_chnl_ctrl_37[2]; assign rrx_test =out_chnl_ctrl_37[1]; assign rrxurstpma =out_chnl_ctrl_37[0]; // RX PMA Per channel control register 3 assign rrx_sd_on[3:0] =out_chnl_ctrl_38[15:12]; assign rrx_sd_off[4:0] =out_chnl_ctrl_38[11:7]; assign rrx_oc_calpd =out_chnl_ctrl_38[6]; assign rurx_pdb =out_chnl_ctrl_38[5]; assign rrx_ib_pdb =out_chnl_ctrl_38[4]; assign rpowdnr =out_chnl_ctrl_38[3]; // RX PMA Per channel control register 4 assign rcru_div2 =out_chnl_ctrl_39[15]; assign rcru_m_sel[1:0] =out_chnl_ctrl_39[14:13]; assign rcru_m[3:0] =out_chnl_ctrl_39[12:9]; assign rcru_l[1:0] =out_chnl_ctrl_39[8:7]; assign rcru_ctl0 =out_chnl_ctrl_39[6]; assign rcru_crplctrl[1:0] =out_chnl_ctrl_39[5:4]; assign rcru_pfdbwctrl[1:0]=out_chnl_ctrl_39[3:2]; assign rcru_pdbwctrl[1:0] =out_chnl_ctrl_39[1:0]; // RX PMA Per channel control register 5 assign rcru_rlbk =out_chnl_ctrl_40[15]; assign rcru_lst[3:0] =out_chnl_ctrl_40[14:11]; assign rcru_testen =out_chnl_ctrl_40[10]; assign rcru_testupen =out_chnl_ctrl_40[9]; assign rcru_testdnen =out_chnl_ctrl_40[8]; assign rcru_isel[2:0] =out_chnl_ctrl_40[7:5]; assign rcru_iselpd[2:0] =out_chnl_ctrl_40[4:2]; // RX PMA Per channel control register 6 assign rcp_mode =out_chnl_ctrl_41[15]; assign rltd =out_chnl_ctrl_41[14]; assign rltr =out_chnl_ctrl_41[13]; assign rrx_cru_pdb =out_chnl_ctrl_41[12]; assign rrx_cru_rst =out_chnl_ctrl_41[11]; assign rcru_cmu_mode =out_chnl_ctrl_41[10]; assign rcru_ignore_phslck =out_chnl_ctrl_41[9]; assign rcru_sd_sel =out_chnl_ctrl_41[7]; assign rcru_pdfl =out_chnl_ctrl_41[6]; assign rcru_pdof_test[2:0]=out_chnl_ctrl_41[5:3]; assign rcru_rgla_isel[2:0]=out_chnl_ctrl_41[2:0]; // RX PMA Per channel control register 7 assign rcru_pdof_0i[3:0] =out_chnl_ctrl_42[15:12]; assign rcru_pdof_90i[3:0] =out_chnl_ctrl_42[11:8]; assign rcru_pdof_180i[3:0]=out_chnl_ctrl_42[7:4]; assign rcru_pdof_270i[3:0]=out_chnl_ctrl_42[3:0]; // RX PMA Per channel control register 8 assign reye_monitor[7:0] =out_chnl_ctrl_43[7:0]; // RX PMA Per channel control register 9 assign rpma_reserved[15:0]=out_chnl_ctrl_44[15:0]; // RX PMA Per channel control register 10 assign rpma_doublewidth_rx=out_chnl_ctrl_45[15]; assign rpmadwidth_rx =out_chnl_ctrl_45[14]; assign rtest_fastsd =out_chnl_ctrl_45[13]; assign rfastsd[3:0] =out_chnl_ctrl_45[12:9]; assign rppmsel[5:0] =out_chnl_ctrl_45[8:3]; assign rforce0_freqdet =out_chnl_ctrl_45[2]; assign rforce1_freqdet =out_chnl_ctrl_45[1]; assign rppm_cnt_reset =out_chnl_ctrl_45[0]; // RX PMA Per channel control register 11 assign r_dfe_1t[2:0] =out_chnl_ctrl_46[15:13]; assign r_dfe_2t[2:0] =out_chnl_ctrl_46[12:10]; assign rppm_post_eidle_del=out_chnl_ctrl_46[9]; assign rppm_gen1_2xcnt_en =out_chnl_ctrl_46[8]; // RX PMA Per channel control register 12 assign reqa_set =out_chnl_ctrl_47[14:12]; assign reqb_set =out_chnl_ctrl_47[11:9]; assign reqc_set =out_chnl_ctrl_47[8:6]; assign reqd_set =out_chnl_ctrl_47[5:3]; assign reqv_set =out_chnl_ctrl_47[2:0]; // RX PMA Per channel control register 13 assign rlock_lf_ovd =out_chnl_ctrl_48[15]; assign rseq_sel[1:0] =out_chnl_ctrl_48[14:13]; assign radce_adapt =out_chnl_ctrl_48[12]; assign rrgen_set[2:0] =out_chnl_ctrl_48[11:9]; assign rclkdiv[3:0] =out_chnl_ctrl_48[8:5]; assign rhyst_lf[2:0] =out_chnl_ctrl_48[4:2]; assign rdc_freq[1:0] =out_chnl_ctrl_48[1:0]; // RX PMA Per channel control register 14 assign rhyst_hf[2:0] =out_chnl_ctrl_49[15:13]; assign rf_lpf[1:0] =out_chnl_ctrl_49[6:5]; assign rf_hpf[1:0] =out_chnl_ctrl_49[4:3]; assign rrgen_vod[2:0] =out_chnl_ctrl_49[2:0]; // RX PMA Per channel control register 15 assign rrgen_bw[1:0] =out_chnl_ctrl_50[15:14]; assign rrect_adj[1:0] =out_chnl_ctrl_50[13:12]; assign rd2a_res[1:0] =out_chnl_ctrl_50[11:10]; assign rlf_os[3:0] =out_chnl_ctrl_50[9:6]; assign rhf_os[3:0] =out_chnl_ctrl_50[5:2]; assign radce_rst =out_chnl_ctrl_50[1]; assign radce_pdb =out_chnl_ctrl_50[0]; // RX PMA Per channel control register 16 assign radce_hflck[14:0] =out_chnl_ctrl_51[14:0]; // RX PMA Per channel control register 17 assign radce_lflck[14:0] =out_chnl_ctrl_52[14:0]; // RX PMA Per channel control register 18 assign radce_digital =out_chnl_ctrl_53[9:0]; stratixiv_hssi_cmu_dprio_reg_chnl reg_chnl_inst ( .mdio_rst(mdio_rst), .mdio_wr(mdio_wr), .reg_addr(reg_addr), .mdc(mdc), .mbus_in(mbus_in), .serial_mode(serial_mode), .mdio_dis(mdio_dis), .pma_cram_test(pma_cram_test), .ser_shift_load(ser_shift_load), .si(si), // CSR input .ext_chnl_ctrl_1(csr_chnl_in[15:0]), .ext_chnl_ctrl_2(csr_chnl_in[31:16]), .ext_chnl_ctrl_3(csr_chnl_in[47:32]), .ext_chnl_ctrl_4(csr_chnl_in[63:48]), .ext_chnl_ctrl_5(csr_chnl_in[79:64]), .ext_chnl_ctrl_6(csr_chnl_in[95:80]), .ext_chnl_ctrl_7(csr_chnl_in[111:96]), .ext_chnl_ctrl_8(csr_chnl_in[127:112]), .ext_chnl_ctrl_9(csr_chnl_in[143:128]), .ext_chnl_ctrl_10(csr_chnl_in[159:144]), .ext_chnl_ctrl_11(csr_chnl_in[175:160]), .ext_chnl_ctrl_12(csr_chnl_in[191:176]), .ext_chnl_ctrl_13(csr_chnl_in[207:192]), .ext_chnl_ctrl_14(csr_chnl_in[223:208]), .ext_chnl_ctrl_15(csr_chnl_in[239:224]), .ext_chnl_ctrl_16(csr_chnl_in[255:240]), .ext_chnl_ctrl_17(csr_chnl_in[271:256]), .ext_chnl_ctrl_18(csr_chnl_in[287:272]), .ext_chnl_ctrl_19(csr_chnl_in[303:288]), .ext_chnl_ctrl_20(csr_chnl_in[319:304]), .ext_chnl_ctrl_21(csr_chnl_in[335:320]), .ext_chnl_ctrl_22(csr_chnl_in[351:336]), .ext_chnl_ctrl_23(csr_chnl_in[367:352]), .ext_chnl_ctrl_24(csr_chnl_in[383:368]), .ext_chnl_ctrl_25(csr_chnl_in[399:384]), .ext_chnl_ctrl_26(csr_chnl_in[415:400]), .ext_chnl_ctrl_27(csr_chnl_in[431:416]), .ext_chnl_ctrl_28(csr_chnl_in[447:432]), .ext_chnl_ctrl_29(csr_chnl_in[463:448]), .ext_chnl_ctrl_30(csr_chnl_in[479:464]), .ext_chnl_ctrl_31(csr_chnl_in[495:480]), .ext_chnl_ctrl_32(csr_chnl_in[511:496]), .ext_chnl_ctrl_33(csr_chnl_in[527:512]), .ext_chnl_ctrl_34(csr_chnl_in[543:528]), .ext_chnl_ctrl_35(csr_chnl_in[559:544]), .ext_chnl_ctrl_36(csr_chnl_in[575:560]), .ext_chnl_ctrl_37(csr_chnl_in[591:576]), .ext_chnl_ctrl_38(csr_chnl_in[607:592]), .ext_chnl_ctrl_39(csr_chnl_in[623:608]), .ext_chnl_ctrl_40(csr_chnl_in[639:624]), .ext_chnl_ctrl_41(csr_chnl_in[655:640]), .ext_chnl_ctrl_42(csr_chnl_in[671:656]), .ext_chnl_ctrl_43(csr_chnl_in_reserved[15:0]), .ext_chnl_ctrl_44(csr_chnl_in[687:672]), .ext_chnl_ctrl_45(csr_chnl_in[703:688]), .ext_chnl_ctrl_46(csr_chnl_in[719:704]), .ext_chnl_ctrl_47(csr_chnl_in[735:720]), .ext_chnl_ctrl_48(csr_chnl_in[751:736]), .ext_chnl_ctrl_49(csr_chnl_in[767:752]), .ext_chnl_ctrl_50(csr_chnl_in[783:768]), .ext_chnl_ctrl_51(csr_chnl_in[799:784]), .ext_chnl_ctrl_52(csr_chnl_in[815:800]), .ext_chnl_ctrl_53(csr_chnl_in[831:816]), .targ_addr_ctrl_1(targ_addr_ctrl_1), .targ_addr_ctrl_2(targ_addr_ctrl_2), .targ_addr_ctrl_3(targ_addr_ctrl_3), .targ_addr_ctrl_4(targ_addr_ctrl_4), .targ_addr_ctrl_5(targ_addr_ctrl_5), .targ_addr_ctrl_6(targ_addr_ctrl_6), .targ_addr_ctrl_7(targ_addr_ctrl_7), .targ_addr_ctrl_8(targ_addr_ctrl_8), .targ_addr_ctrl_9(targ_addr_ctrl_9), .targ_addr_ctrl_10(targ_addr_ctrl_10), .targ_addr_ctrl_11(targ_addr_ctrl_11), .targ_addr_ctrl_12(targ_addr_ctrl_12), .targ_addr_ctrl_13(targ_addr_ctrl_13), .targ_addr_ctrl_14(targ_addr_ctrl_14), .targ_addr_ctrl_15(targ_addr_ctrl_15), .targ_addr_ctrl_16(targ_addr_ctrl_16), .targ_addr_ctrl_17(targ_addr_ctrl_17), .targ_addr_ctrl_18(targ_addr_ctrl_18), .targ_addr_ctrl_19(targ_addr_ctrl_19), .targ_addr_ctrl_20(targ_addr_ctrl_20), .targ_addr_ctrl_21(targ_addr_ctrl_21), .targ_addr_ctrl_22(targ_addr_ctrl_22), .targ_addr_ctrl_23(targ_addr_ctrl_23), .targ_addr_ctrl_24(targ_addr_ctrl_24), .targ_addr_ctrl_25(targ_addr_ctrl_25), .targ_addr_ctrl_26(targ_addr_ctrl_26), .targ_addr_ctrl_27(targ_addr_ctrl_27), .targ_addr_ctrl_28(targ_addr_ctrl_28), .targ_addr_ctrl_29(targ_addr_ctrl_29), .targ_addr_ctrl_30(targ_addr_ctrl_30), .targ_addr_ctrl_31(targ_addr_ctrl_31), .targ_addr_ctrl_32(targ_addr_ctrl_32), .targ_addr_ctrl_33(targ_addr_ctrl_33), .targ_addr_ctrl_34(targ_addr_ctrl_34), .targ_addr_ctrl_35(targ_addr_ctrl_35), .targ_addr_ctrl_36(targ_addr_ctrl_36), .targ_addr_ctrl_37(targ_addr_ctrl_37), .targ_addr_ctrl_38(targ_addr_ctrl_38), .targ_addr_ctrl_39(targ_addr_ctrl_39), .targ_addr_ctrl_40(targ_addr_ctrl_40), .targ_addr_ctrl_41(targ_addr_ctrl_41), .targ_addr_ctrl_42(targ_addr_ctrl_42), .targ_addr_ctrl_43(targ_addr_ctrl_43), .targ_addr_ctrl_44(targ_addr_ctrl_44), .targ_addr_ctrl_45(targ_addr_ctrl_45), .targ_addr_ctrl_46(targ_addr_ctrl_46), .targ_addr_ctrl_47(targ_addr_ctrl_47), .targ_addr_ctrl_48(targ_addr_ctrl_48), .targ_addr_ctrl_49(targ_addr_ctrl_49), .targ_addr_ctrl_50(targ_addr_ctrl_50), .targ_addr_ctrl_51(targ_addr_ctrl_51), .targ_addr_ctrl_52(targ_addr_ctrl_52), .targ_addr_ctrl_53(targ_addr_ctrl_53), // DPRIO register output .out_chnl_ctrl_1(out_chnl_ctrl_1), .out_chnl_ctrl_2(out_chnl_ctrl_2), .out_chnl_ctrl_3(out_chnl_ctrl_3), .out_chnl_ctrl_4(out_chnl_ctrl_4), .out_chnl_ctrl_5(out_chnl_ctrl_5), .out_chnl_ctrl_6(out_chnl_ctrl_6), .out_chnl_ctrl_7(out_chnl_ctrl_7), .out_chnl_ctrl_8(out_chnl_ctrl_8), .out_chnl_ctrl_9(out_chnl_ctrl_9), .out_chnl_ctrl_10(out_chnl_ctrl_10), .out_chnl_ctrl_11(out_chnl_ctrl_11), .out_chnl_ctrl_12(out_chnl_ctrl_12), .out_chnl_ctrl_13(out_chnl_ctrl_13), .out_chnl_ctrl_14(out_chnl_ctrl_14), .out_chnl_ctrl_15(out_chnl_ctrl_15), .out_chnl_ctrl_16(out_chnl_ctrl_16), .out_chnl_ctrl_17(out_chnl_ctrl_17), .out_chnl_ctrl_18(out_chnl_ctrl_18), .out_chnl_ctrl_19(out_chnl_ctrl_19), .out_chnl_ctrl_20(out_chnl_ctrl_20), .out_chnl_ctrl_21(out_chnl_ctrl_21), .out_chnl_ctrl_22(out_chnl_ctrl_22), .out_chnl_ctrl_23(out_chnl_ctrl_23), .out_chnl_ctrl_24(out_chnl_ctrl_24), .out_chnl_ctrl_25(out_chnl_ctrl_25), .out_chnl_ctrl_26(out_chnl_ctrl_26), .out_chnl_ctrl_27(out_chnl_ctrl_27), .out_chnl_ctrl_28(out_chnl_ctrl_28), .out_chnl_ctrl_29(out_chnl_ctrl_29), .out_chnl_ctrl_30(out_chnl_ctrl_30), .out_chnl_ctrl_31(out_chnl_ctrl_31), .out_chnl_ctrl_32(out_chnl_ctrl_32), .out_chnl_ctrl_33(out_chnl_ctrl_33), .out_chnl_ctrl_34(out_chnl_ctrl_34), .out_chnl_ctrl_35(out_chnl_ctrl_35), .out_chnl_ctrl_36(out_chnl_ctrl_36), .out_chnl_ctrl_37(out_chnl_ctrl_37), .out_chnl_ctrl_38(out_chnl_ctrl_38), .out_chnl_ctrl_39(out_chnl_ctrl_39), .out_chnl_ctrl_40(out_chnl_ctrl_40), .out_chnl_ctrl_41(out_chnl_ctrl_41), .out_chnl_ctrl_42(out_chnl_ctrl_42), .out_chnl_ctrl_43(out_chnl_ctrl_43), .out_chnl_ctrl_44(out_chnl_ctrl_44), .out_chnl_ctrl_45(out_chnl_ctrl_45), .out_chnl_ctrl_46(out_chnl_ctrl_46), .out_chnl_ctrl_47(out_chnl_ctrl_47), .out_chnl_ctrl_48(out_chnl_ctrl_48), .out_chnl_ctrl_49(out_chnl_ctrl_49), .out_chnl_ctrl_50(out_chnl_ctrl_50), .out_chnl_ctrl_51(out_chnl_ctrl_51), .out_chnl_ctrl_52(out_chnl_ctrl_52), .out_chnl_ctrl_53(out_chnl_ctrl_53), .so(so) ); // MBUS_OUT muxing stratixiv_hssi_cmu_dprio_chnl_bus_out_mux mbus_mux ( .chnl_ctrl_in1 (out_chnl_ctrl_1), .chnl_ctrl_in2 (out_chnl_ctrl_2), .chnl_ctrl_in3 (out_chnl_ctrl_3), .chnl_ctrl_in4 (out_chnl_ctrl_4), .chnl_ctrl_in5 (out_chnl_ctrl_5), .chnl_ctrl_in6 (out_chnl_ctrl_6), .chnl_ctrl_in7 (out_chnl_ctrl_7), .chnl_ctrl_in8 (out_chnl_ctrl_8), .chnl_ctrl_in9 (out_chnl_ctrl_9), .chnl_ctrl_in10(out_chnl_ctrl_10), .chnl_ctrl_in11(out_chnl_ctrl_11), .chnl_ctrl_in12(out_chnl_ctrl_12), .chnl_ctrl_in13(out_chnl_ctrl_13), .chnl_ctrl_in14(out_chnl_ctrl_14), .chnl_ctrl_in15(out_chnl_ctrl_15), .chnl_ctrl_in16(out_chnl_ctrl_16), .chnl_ctrl_in17(out_chnl_ctrl_17), .chnl_ctrl_in18(out_chnl_ctrl_18), .chnl_ctrl_in19(out_chnl_ctrl_19), .chnl_ctrl_in20(out_chnl_ctrl_20), .chnl_ctrl_in21(out_chnl_ctrl_21), .chnl_ctrl_in22(out_chnl_ctrl_22), .chnl_ctrl_in23(out_chnl_ctrl_23), .chnl_ctrl_in24(out_chnl_ctrl_24), .chnl_ctrl_in25(out_chnl_ctrl_25), .chnl_ctrl_in26(out_chnl_ctrl_26), .chnl_ctrl_in27(out_chnl_ctrl_27), .chnl_ctrl_in28(out_chnl_ctrl_28), .chnl_ctrl_in29(out_chnl_ctrl_29), .chnl_ctrl_in30(out_chnl_ctrl_30), .chnl_ctrl_in31(out_chnl_ctrl_31), .chnl_ctrl_in32(out_chnl_ctrl_32), .chnl_ctrl_in33(out_chnl_ctrl_33), .chnl_ctrl_in34(out_chnl_ctrl_34), .chnl_ctrl_in35(out_chnl_ctrl_35), .chnl_ctrl_in36(out_chnl_ctrl_36), .chnl_ctrl_in37(out_chnl_ctrl_37), .chnl_ctrl_in38(out_chnl_ctrl_38), .chnl_ctrl_in39(out_chnl_ctrl_39), .chnl_ctrl_in40(out_chnl_ctrl_40), .chnl_ctrl_in41(out_chnl_ctrl_41), .chnl_ctrl_in42(out_chnl_ctrl_42), .chnl_ctrl_in43(out_chnl_ctrl_43), .chnl_ctrl_in44(out_chnl_ctrl_44), .chnl_ctrl_in45(out_chnl_ctrl_45), .chnl_ctrl_in46(out_chnl_ctrl_46), .chnl_ctrl_in47(out_chnl_ctrl_47), .chnl_ctrl_in48(out_chnl_ctrl_48), .chnl_ctrl_in49(out_chnl_ctrl_49), .chnl_ctrl_in50(out_chnl_ctrl_50), .chnl_ctrl_in51(out_chnl_ctrl_51), .chnl_ctrl_in52(out_chnl_ctrl_52), .chnl_ctrl_in53(out_chnl_ctrl_53), .hw_address_ctrl_in1 (targ_addr_ctrl_1), .hw_address_ctrl_in2 (targ_addr_ctrl_2), .hw_address_ctrl_in3 (targ_addr_ctrl_3), .hw_address_ctrl_in4 (targ_addr_ctrl_4), .hw_address_ctrl_in5 (targ_addr_ctrl_5), .hw_address_ctrl_in6 (targ_addr_ctrl_6), .hw_address_ctrl_in7 (targ_addr_ctrl_7), .hw_address_ctrl_in8 (targ_addr_ctrl_8), .hw_address_ctrl_in9 (targ_addr_ctrl_9), .hw_address_ctrl_in10(targ_addr_ctrl_10), .hw_address_ctrl_in11(targ_addr_ctrl_11), .hw_address_ctrl_in12(targ_addr_ctrl_12), .hw_address_ctrl_in13(targ_addr_ctrl_13), .hw_address_ctrl_in14(targ_addr_ctrl_14), .hw_address_ctrl_in15(targ_addr_ctrl_15), .hw_address_ctrl_in16(targ_addr_ctrl_16), .hw_address_ctrl_in17(targ_addr_ctrl_17), .hw_address_ctrl_in18(targ_addr_ctrl_18), .hw_address_ctrl_in19(targ_addr_ctrl_19), .hw_address_ctrl_in20(targ_addr_ctrl_20), .hw_address_ctrl_in21(targ_addr_ctrl_21), .hw_address_ctrl_in22(targ_addr_ctrl_22), .hw_address_ctrl_in23(targ_addr_ctrl_23), .hw_address_ctrl_in24(targ_addr_ctrl_24), .hw_address_ctrl_in25(targ_addr_ctrl_25), .hw_address_ctrl_in26(targ_addr_ctrl_26), .hw_address_ctrl_in27(targ_addr_ctrl_27), .hw_address_ctrl_in28(targ_addr_ctrl_28), .hw_address_ctrl_in29(targ_addr_ctrl_29), .hw_address_ctrl_in30(targ_addr_ctrl_30), .hw_address_ctrl_in31(targ_addr_ctrl_31), .hw_address_ctrl_in32(targ_addr_ctrl_32), .hw_address_ctrl_in33(targ_addr_ctrl_33), .hw_address_ctrl_in34(targ_addr_ctrl_34), .hw_address_ctrl_in35(targ_addr_ctrl_35), .hw_address_ctrl_in36(targ_addr_ctrl_36), .hw_address_ctrl_in37(targ_addr_ctrl_37), .hw_address_ctrl_in38(targ_addr_ctrl_38), .hw_address_ctrl_in39(targ_addr_ctrl_39), .hw_address_ctrl_in40(targ_addr_ctrl_40), .hw_address_ctrl_in41(targ_addr_ctrl_41), .hw_address_ctrl_in42(targ_addr_ctrl_42), .hw_address_ctrl_in43(targ_addr_ctrl_43), .hw_address_ctrl_in44(targ_addr_ctrl_44), .hw_address_ctrl_in45(targ_addr_ctrl_45), .hw_address_ctrl_in46(targ_addr_ctrl_46), .hw_address_ctrl_in47(targ_addr_ctrl_47), .hw_address_ctrl_in48(targ_addr_ctrl_48), .hw_address_ctrl_in49(targ_addr_ctrl_49), .hw_address_ctrl_in50(targ_addr_ctrl_50), .hw_address_ctrl_in51(targ_addr_ctrl_51), .hw_address_ctrl_in52(targ_addr_ctrl_52), .hw_address_ctrl_in53(targ_addr_ctrl_53), .reg_addr(reg_addr), .chnl_ctrl_out(mbus_out) ); endmodule `timescale 1 ps / 1 ps module stratixiv_hssi_cmu_dprio_status (mdio_rst, mdio_rd, reg_addr, dev_addr_0, mdc, serial_mode, ser_shift_load, si, mbus_out_ch0, mbus_out_ch1, mbus_out_ch2, mbus_out_ch3, mbus_out_centrl, align_status, sync_status, xs_link_status, rx_local_fault, tx_local_fault, rxs_link_status_set, rtx_rx_local_fault_clr, mbus_out, so ); input mdio_rst; input mdio_rd; input [15:0] reg_addr; input dev_addr_0; input mdc; input serial_mode; input ser_shift_load; input si; input [15:0] mbus_out_ch0; input [15:0] mbus_out_ch1; input [15:0] mbus_out_ch2; input [15:0] mbus_out_ch3; input [15:0] mbus_out_centrl; // Status inputs input align_status; input [3:0] sync_status; input xs_link_status; input rx_local_fault; input tx_local_fault; // Outputs output rxs_link_status_set; output rtx_rx_local_fault_clr; output [15:0] mbus_out; output so; wire chain; wire xs_link_status_rd; wire tx_rx_local_fault_status_rd; wire local_fault; wire xs_tx_local_fault; wire xs_rx_local_fault; wire [15:0] xgxs_stat1_reg; wire [15:0] xgxs_stat2_reg; wire [15:0] xgxs_lane_stat_reg; // Status register address parameters parameter XGXS_STATUS1 = 16'h6004; parameter XGXS_STATUS2 = 16'h6005; parameter XGXS_LANE_STATUS = 16'h6006; // XGXS_STATUS1 and XGXS_STATUS2 status registers assign xs_link_status_rd = mdio_rd & (reg_addr==XGXS_STATUS1); assign tx_rx_local_fault_status_rd = mdio_rd & (reg_addr==XGXS_STATUS2); // Status registers assign local_fault = tx_local_fault | rx_local_fault; assign xs_tx_local_fault = (dev_addr_0) ? tx_local_fault : rx_local_fault ; assign xs_rx_local_fault = (dev_addr_0) ? rx_local_fault : tx_local_fault ; assign xgxs_stat1_reg = {8'h00, local_fault, 4'h0, xs_link_status, 2'b10}; assign xgxs_stat2_reg = {4'h8, xs_rx_local_fault, xs_tx_local_fault, 10'b0000000000}; assign xgxs_lane_stat_reg = {3'b000, align_status, 8'hc0, sync_status}; // Single control bits stratixiv_hssi_cmu_dprio_bit xs_link_status_set (.reset(mdio_rst), .clk(mdc), .sig_in(xs_link_status_rd), .ext_in(1'b0), .serial_mode(serial_mode), .si(si), .shift(ser_shift_load), .mdio_dis(1'b0), .sig_out(rxs_link_status_set), .so(chain) ); stratixiv_hssi_cmu_dprio_bit tx_rx_local_fault_clr (.reset(mdio_rst), .clk(mdc), .sig_in(tx_rx_local_fault_status_rd), .ext_in(1'b0), .serial_mode(serial_mode), .si(chain), .shift(ser_shift_load), .mdio_dis(1'b0), .sig_out(rtx_rx_local_fault_clr), .so(so) ); // MDIO readout data assign mbus_out = // Muxing for status registers (reg_addr == XGXS_STATUS1) ? xgxs_stat1_reg : (reg_addr == XGXS_STATUS2) ? xgxs_stat2_reg : (reg_addr == XGXS_LANE_STATUS) ? xgxs_lane_stat_reg : // Muxing for Central PCS registers (reg_addr == {16'h6000 + 16'h0000}) ? mbus_out_centrl : (reg_addr == {16'h6000 + 16'h0001}) ? mbus_out_centrl : (reg_addr == {16'h6000 + 16'h0002}) ? mbus_out_centrl : (reg_addr == {16'h6000 + 16'h0003}) ? mbus_out_centrl : // Muxing for CMU PMA registers (reg_addr == {16'h4800 + 16'h0000}) ? mbus_out_centrl : (reg_addr == {16'h4800 + 16'h0001}) ? mbus_out_centrl : (reg_addr == {16'h4800 + 16'h0002}) ? mbus_out_centrl : (reg_addr == {16'h4800 + 16'h0003}) ? mbus_out_centrl : (reg_addr == {16'h4800 + 16'h0004}) ? mbus_out_centrl : (reg_addr == {16'h4800 + 16'h0005}) ? mbus_out_centrl : (reg_addr == {16'h4800 + 16'h0006}) ? mbus_out_centrl : (reg_addr == {16'h4800 + 16'h0007}) ? mbus_out_centrl : (reg_addr == {16'h4C00 + 16'h0000}) ? mbus_out_centrl : (reg_addr == {16'h4C00 + 16'h0001}) ? mbus_out_centrl : (reg_addr == {16'h4C00 + 16'h0002}) ? mbus_out_centrl : (reg_addr == {16'h4C00 + 16'h0003}) ? mbus_out_centrl : (reg_addr == {16'h4C00 + 16'h0004}) ? mbus_out_centrl : (reg_addr == {16'h4C00 + 16'h0005}) ? mbus_out_centrl : (reg_addr == {16'h4C00 + 16'h0006}) ? mbus_out_centrl : (reg_addr == {16'h4C00 + 16'h0007}) ? mbus_out_centrl : (reg_addr == {16'h4C00 + 16'h0008}) ? mbus_out_centrl : (reg_addr == {16'h4C00 + 16'h0009}) ? mbus_out_centrl : (reg_addr == {16'h4C00 + 16'h000A}) ? mbus_out_centrl : (reg_addr == {16'h4C00 + 16'h000B}) ? mbus_out_centrl : (reg_addr == {16'h4C00 + 16'h000C}) ? mbus_out_centrl : (reg_addr == {16'h5800 + 16'h0000}) ? mbus_out_centrl : (reg_addr == {16'h5800 + 16'h0001}) ? mbus_out_centrl : (reg_addr == {16'h5800 + 16'h0002}) ? mbus_out_centrl : (reg_addr == {16'h5800 + 16'h0003}) ? mbus_out_centrl : (reg_addr == {16'h5800 + 16'h0004}) ? mbus_out_centrl : (reg_addr == {16'h5800 + 16'h0005}) ? mbus_out_centrl : (reg_addr == {16'h5800 + 16'h0006}) ? mbus_out_centrl : (reg_addr == {16'h5800 + 16'h0007}) ? mbus_out_centrl : (reg_addr == {16'h5C00 + 16'h0000}) ? mbus_out_centrl : (reg_addr == {16'h5C00 + 16'h0001}) ? mbus_out_centrl : (reg_addr == {16'h5C00 + 16'h0002}) ? mbus_out_centrl : (reg_addr == {16'h5C00 + 16'h0003}) ? mbus_out_centrl : (reg_addr == {16'h5C00 + 16'h0004}) ? mbus_out_centrl : (reg_addr == {16'h5C00 + 16'h0005}) ? mbus_out_centrl : (reg_addr == {16'h5C00 + 16'h0006}) ? mbus_out_centrl : (reg_addr == {16'h5C00 + 16'h0007}) ? mbus_out_centrl : (reg_addr == {16'h5C00 + 16'h0008}) ? mbus_out_centrl : (reg_addr == {16'h5C00 + 16'h0009}) ? mbus_out_centrl : (reg_addr == {16'h5C00 + 16'h000A}) ? mbus_out_centrl : (reg_addr == {16'h5C00 + 16'h000B}) ? mbus_out_centrl : (reg_addr == {16'h5C00 + 16'h000C}) ? mbus_out_centrl : // Muxing for PCS channel0 registers (reg_addr == {16'h0000 + 16'h0000}) ? mbus_out_ch0 : (reg_addr == {16'h0000 + 16'h0001}) ? mbus_out_ch0 : (reg_addr == {16'h0000 + 16'h0002}) ? mbus_out_ch0 : (reg_addr == {16'h0000 + 16'h0003}) ? mbus_out_ch0 : (reg_addr == {16'h0400 + 16'h0000}) ? mbus_out_ch0 : (reg_addr == {16'h0400 + 16'h0001}) ? mbus_out_ch0 : (reg_addr == {16'h0400 + 16'h0002}) ? mbus_out_ch0 : (reg_addr == {16'h0400 + 16'h0003}) ? mbus_out_ch0 : (reg_addr == {16'h0400 + 16'h0004}) ? mbus_out_ch0 : (reg_addr == {16'h0400 + 16'h0005}) ? mbus_out_ch0 : (reg_addr == {16'h0400 + 16'h0006}) ? mbus_out_ch0 : (reg_addr == {16'h0400 + 16'h0007}) ? mbus_out_ch0 : (reg_addr == {16'h0400 + 16'h0008}) ? mbus_out_ch0 : (reg_addr == {16'h0400 + 16'h0009}) ? mbus_out_ch0 : (reg_addr == {16'h0400 + 16'h000A}) ? mbus_out_ch0 : (reg_addr == {16'h0400 + 16'h000B}) ? mbus_out_ch0 : (reg_addr == {16'h0400 + 16'h000C}) ? mbus_out_ch0 : (reg_addr == {16'h0400 + 16'h000D}) ? mbus_out_ch0 : (reg_addr == {16'h0400 + 16'h000E}) ? mbus_out_ch0 : (reg_addr == {16'h0400 + 16'h000F}) ? mbus_out_ch0 : (reg_addr == {16'h0400 + 16'h0010}) ? mbus_out_ch0 : (reg_addr == {16'h0400 + 16'h0011}) ? mbus_out_ch0 : (reg_addr == {16'h0400 + 16'h0012}) ? mbus_out_ch0 : (reg_addr == {16'h0400 + 16'h0013}) ? mbus_out_ch0 : (reg_addr == {16'h0400 + 16'h0014}) ? mbus_out_ch0 : (reg_addr == {16'h0400 + 16'h0015}) ? mbus_out_ch0 : (reg_addr == {16'h0400 + 16'h0016}) ? mbus_out_ch0 : // Muxing for PMA channel0 registers (reg_addr == {16'h0800 + 16'h0000}) ? mbus_out_ch0 : (reg_addr == {16'h0800 + 16'h0001}) ? mbus_out_ch0 : (reg_addr == {16'h0800 + 16'h0002}) ? mbus_out_ch0 : (reg_addr == {16'h0800 + 16'h0003}) ? mbus_out_ch0 : (reg_addr == {16'h0800 + 16'h0004}) ? mbus_out_ch0 : (reg_addr == {16'h0800 + 16'h0005}) ? mbus_out_ch0 : (reg_addr == {16'h0800 + 16'h0006}) ? mbus_out_ch0 : (reg_addr == {16'h0800 + 16'h0007}) ? mbus_out_ch0 : (reg_addr == {16'h0C00 + 16'h0000}) ? mbus_out_ch0 : (reg_addr == {16'h0C00 + 16'h0001}) ? mbus_out_ch0 : (reg_addr == {16'h0C00 + 16'h0002}) ? mbus_out_ch0 : (reg_addr == {16'h0C00 + 16'h0003}) ? mbus_out_ch0 : (reg_addr == {16'h0C00 + 16'h0004}) ? mbus_out_ch0 : (reg_addr == {16'h0C00 + 16'h0005}) ? mbus_out_ch0 : (reg_addr == {16'h0C00 + 16'h0006}) ? mbus_out_ch0 : (reg_addr == {16'h0C00 + 16'h0007}) ? mbus_out_ch0 : (reg_addr == {16'h0C00 + 16'h0008}) ? mbus_out_ch0 : (reg_addr == {16'h0C00 + 16'h0009}) ? mbus_out_ch0 : (reg_addr == {16'h0C00 + 16'h000A}) ? mbus_out_ch0 : (reg_addr == {16'h0C00 + 16'h000B}) ? mbus_out_ch0 : (reg_addr == {16'h0C00 + 16'h000C}) ? mbus_out_ch0 : (reg_addr == {16'h0C00 + 16'h000D}) ? mbus_out_ch0 : (reg_addr == {16'h0C00 + 16'h000E}) ? mbus_out_ch0 : (reg_addr == {16'h0C00 + 16'h000F}) ? mbus_out_ch0 : (reg_addr == {16'h0C00 + 16'h0010}) ? mbus_out_ch0 : (reg_addr == {16'h0C00 + 16'h0011}) ? mbus_out_ch0 : // Muxing for PCS channel1 registers (reg_addr == {16'h1000 + 16'h0000}) ? mbus_out_ch1 : (reg_addr == {16'h1000 + 16'h0001}) ? mbus_out_ch1 : (reg_addr == {16'h1000 + 16'h0002}) ? mbus_out_ch1 : (reg_addr == {16'h1000 + 16'h0003}) ? mbus_out_ch1 : (reg_addr == {16'h1400 + 16'h0000}) ? mbus_out_ch1 : (reg_addr == {16'h1400 + 16'h0001}) ? mbus_out_ch1 : (reg_addr == {16'h1400 + 16'h0002}) ? mbus_out_ch1 : (reg_addr == {16'h1400 + 16'h0003}) ? mbus_out_ch1 : (reg_addr == {16'h1400 + 16'h0004}) ? mbus_out_ch1 : (reg_addr == {16'h1400 + 16'h0005}) ? mbus_out_ch1 : (reg_addr == {16'h1400 + 16'h0006}) ? mbus_out_ch1 : (reg_addr == {16'h1400 + 16'h0007}) ? mbus_out_ch1 : (reg_addr == {16'h1400 + 16'h0008}) ? mbus_out_ch1 : (reg_addr == {16'h1400 + 16'h0009}) ? mbus_out_ch1 : (reg_addr == {16'h1400 + 16'h000A}) ? mbus_out_ch1 : (reg_addr == {16'h1400 + 16'h000B}) ? mbus_out_ch1 : (reg_addr == {16'h1400 + 16'h000C}) ? mbus_out_ch1 : (reg_addr == {16'h1400 + 16'h000D}) ? mbus_out_ch1 : (reg_addr == {16'h1400 + 16'h000E}) ? mbus_out_ch1 : (reg_addr == {16'h1400 + 16'h000F}) ? mbus_out_ch1 : (reg_addr == {16'h1400 + 16'h0010}) ? mbus_out_ch1 : (reg_addr == {16'h1400 + 16'h0011}) ? mbus_out_ch1 : (reg_addr == {16'h1400 + 16'h0012}) ? mbus_out_ch1 : (reg_addr == {16'h1400 + 16'h0013}) ? mbus_out_ch1 : (reg_addr == {16'h1400 + 16'h0014}) ? mbus_out_ch1 : (reg_addr == {16'h1400 + 16'h0015}) ? mbus_out_ch1 : (reg_addr == {16'h1400 + 16'h0016}) ? mbus_out_ch1 : // Muxing for PMA channel1 registers (reg_addr == {16'h1800 + 16'h0000}) ? mbus_out_ch1 : (reg_addr == {16'h1800 + 16'h0001}) ? mbus_out_ch1 : (reg_addr == {16'h1800 + 16'h0002}) ? mbus_out_ch1 : (reg_addr == {16'h1800 + 16'h0003}) ? mbus_out_ch1 : (reg_addr == {16'h1800 + 16'h0004}) ? mbus_out_ch1 : (reg_addr == {16'h1800 + 16'h0005}) ? mbus_out_ch1 : (reg_addr == {16'h1800 + 16'h0006}) ? mbus_out_ch1 : (reg_addr == {16'h1800 + 16'h0007}) ? mbus_out_ch1 : (reg_addr == {16'h1C00 + 16'h0000}) ? mbus_out_ch1 : (reg_addr == {16'h1C00 + 16'h0001}) ? mbus_out_ch1 : (reg_addr == {16'h1C00 + 16'h0002}) ? mbus_out_ch1 : (reg_addr == {16'h1C00 + 16'h0003}) ? mbus_out_ch1 : (reg_addr == {16'h1C00 + 16'h0004}) ? mbus_out_ch1 : (reg_addr == {16'h1C00 + 16'h0005}) ? mbus_out_ch1 : (reg_addr == {16'h1C00 + 16'h0006}) ? mbus_out_ch1 : (reg_addr == {16'h1C00 + 16'h0007}) ? mbus_out_ch1 : (reg_addr == {16'h1C00 + 16'h0008}) ? mbus_out_ch1 : (reg_addr == {16'h1C00 + 16'h0009}) ? mbus_out_ch1 : (reg_addr == {16'h1C00 + 16'h000A}) ? mbus_out_ch1 : (reg_addr == {16'h1C00 + 16'h000B}) ? mbus_out_ch1 : (reg_addr == {16'h1C00 + 16'h000C}) ? mbus_out_ch1 : (reg_addr == {16'h1C00 + 16'h000D}) ? mbus_out_ch1 : (reg_addr == {16'h1C00 + 16'h000E}) ? mbus_out_ch1 : (reg_addr == {16'h1C00 + 16'h000F}) ? mbus_out_ch1 : (reg_addr == {16'h1C00 + 16'h0010}) ? mbus_out_ch1 : (reg_addr == {16'h1C00 + 16'h0011}) ? mbus_out_ch1 : // Muxing for PCS channel2 registers (reg_addr == {16'h2000 + 16'h0000}) ? mbus_out_ch2 : (reg_addr == {16'h2000 + 16'h0001}) ? mbus_out_ch2 : (reg_addr == {16'h2000 + 16'h0002}) ? mbus_out_ch2 : (reg_addr == {16'h2000 + 16'h0003}) ? mbus_out_ch2 : (reg_addr == {16'h2400 + 16'h0000}) ? mbus_out_ch2 : (reg_addr == {16'h2400 + 16'h0001}) ? mbus_out_ch2 : (reg_addr == {16'h2400 + 16'h0002}) ? mbus_out_ch2 : (reg_addr == {16'h2400 + 16'h0003}) ? mbus_out_ch2 : (reg_addr == {16'h2400 + 16'h0004}) ? mbus_out_ch2 : (reg_addr == {16'h2400 + 16'h0005}) ? mbus_out_ch2 : (reg_addr == {16'h2400 + 16'h0006}) ? mbus_out_ch2 : (reg_addr == {16'h2400 + 16'h0007}) ? mbus_out_ch2 : (reg_addr == {16'h2400 + 16'h0008}) ? mbus_out_ch2 : (reg_addr == {16'h2400 + 16'h0009}) ? mbus_out_ch2 : (reg_addr == {16'h2400 + 16'h000A}) ? mbus_out_ch2 : (reg_addr == {16'h2400 + 16'h000B}) ? mbus_out_ch2 : (reg_addr == {16'h2400 + 16'h000C}) ? mbus_out_ch2 : (reg_addr == {16'h2400 + 16'h000D}) ? mbus_out_ch2 : (reg_addr == {16'h2400 + 16'h000E}) ? mbus_out_ch2 : (reg_addr == {16'h2400 + 16'h000F}) ? mbus_out_ch2 : (reg_addr == {16'h2400 + 16'h0010}) ? mbus_out_ch2 : (reg_addr == {16'h2400 + 16'h0011}) ? mbus_out_ch2 : (reg_addr == {16'h2400 + 16'h0012}) ? mbus_out_ch2 : (reg_addr == {16'h2400 + 16'h0013}) ? mbus_out_ch2 : (reg_addr == {16'h2400 + 16'h0014}) ? mbus_out_ch2 : (reg_addr == {16'h2400 + 16'h0015}) ? mbus_out_ch2 : (reg_addr == {16'h2400 + 16'h0016}) ? mbus_out_ch2 : // Muxing for PMA channel2 registers (reg_addr == {16'h2800 + 16'h0000}) ? mbus_out_ch2 : (reg_addr == {16'h2800 + 16'h0001}) ? mbus_out_ch2 : (reg_addr == {16'h2800 + 16'h0002}) ? mbus_out_ch2 : (reg_addr == {16'h2800 + 16'h0003}) ? mbus_out_ch2 : (reg_addr == {16'h2800 + 16'h0004}) ? mbus_out_ch2 : (reg_addr == {16'h2800 + 16'h0005}) ? mbus_out_ch2 : (reg_addr == {16'h2800 + 16'h0006}) ? mbus_out_ch2 : (reg_addr == {16'h2800 + 16'h0007}) ? mbus_out_ch2 : (reg_addr == {16'h2C00 + 16'h0000}) ? mbus_out_ch2 : (reg_addr == {16'h2C00 + 16'h0001}) ? mbus_out_ch2 : (reg_addr == {16'h2C00 + 16'h0002}) ? mbus_out_ch2 : (reg_addr == {16'h2C00 + 16'h0003}) ? mbus_out_ch2 : (reg_addr == {16'h2C00 + 16'h0004}) ? mbus_out_ch2 : (reg_addr == {16'h2C00 + 16'h0005}) ? mbus_out_ch2 : (reg_addr == {16'h2C00 + 16'h0006}) ? mbus_out_ch2 : (reg_addr == {16'h2C00 + 16'h0007}) ? mbus_out_ch2 : (reg_addr == {16'h2C00 + 16'h0008}) ? mbus_out_ch2 : (reg_addr == {16'h2C00 + 16'h0009}) ? mbus_out_ch2 : (reg_addr == {16'h2C00 + 16'h000A}) ? mbus_out_ch2 : (reg_addr == {16'h2C00 + 16'h000B}) ? mbus_out_ch2 : (reg_addr == {16'h2C00 + 16'h000C}) ? mbus_out_ch2 : (reg_addr == {16'h2C00 + 16'h000D}) ? mbus_out_ch2 : (reg_addr == {16'h2C00 + 16'h000E}) ? mbus_out_ch2 : (reg_addr == {16'h2C00 + 16'h000F}) ? mbus_out_ch2 : (reg_addr == {16'h2C00 + 16'h0010}) ? mbus_out_ch2 : (reg_addr == {16'h2C00 + 16'h0011}) ? mbus_out_ch2 : // Muxing for PCS channel3 registers (reg_addr == {16'h3000 + 16'h0000}) ? mbus_out_ch3 : (reg_addr == {16'h3000 + 16'h0001}) ? mbus_out_ch3 : (reg_addr == {16'h3000 + 16'h0002}) ? mbus_out_ch3 : (reg_addr == {16'h3000 + 16'h0003}) ? mbus_out_ch3 : (reg_addr == {16'h3400 + 16'h0000}) ? mbus_out_ch3 : (reg_addr == {16'h3400 + 16'h0001}) ? mbus_out_ch3 : (reg_addr == {16'h3400 + 16'h0002}) ? mbus_out_ch3 : (reg_addr == {16'h3400 + 16'h0003}) ? mbus_out_ch3 : (reg_addr == {16'h3400 + 16'h0004}) ? mbus_out_ch3 : (reg_addr == {16'h3400 + 16'h0005}) ? mbus_out_ch3 : (reg_addr == {16'h3400 + 16'h0006}) ? mbus_out_ch3 : (reg_addr == {16'h3400 + 16'h0007}) ? mbus_out_ch3 : (reg_addr == {16'h3400 + 16'h0008}) ? mbus_out_ch3 : (reg_addr == {16'h3400 + 16'h0009}) ? mbus_out_ch3 : (reg_addr == {16'h3400 + 16'h000A}) ? mbus_out_ch3 : (reg_addr == {16'h3400 + 16'h000B}) ? mbus_out_ch3 : (reg_addr == {16'h3400 + 16'h000C}) ? mbus_out_ch3 : (reg_addr == {16'h3400 + 16'h000D}) ? mbus_out_ch3 : (reg_addr == {16'h3400 + 16'h000E}) ? mbus_out_ch3 : (reg_addr == {16'h3400 + 16'h000F}) ? mbus_out_ch3 : (reg_addr == {16'h3400 + 16'h0010}) ? mbus_out_ch3 : (reg_addr == {16'h3400 + 16'h0011}) ? mbus_out_ch3 : (reg_addr == {16'h3400 + 16'h0012}) ? mbus_out_ch3 : (reg_addr == {16'h3400 + 16'h0013}) ? mbus_out_ch3 : (reg_addr == {16'h3400 + 16'h0014}) ? mbus_out_ch3 : (reg_addr == {16'h3400 + 16'h0015}) ? mbus_out_ch3 : (reg_addr == {16'h3400 + 16'h0016}) ? mbus_out_ch3 : // Muxing for PMA channel3 registers (reg_addr == {16'h3800 + 16'h0000}) ? mbus_out_ch3 : (reg_addr == {16'h3800 + 16'h0001}) ? mbus_out_ch3 : (reg_addr == {16'h3800 + 16'h0002}) ? mbus_out_ch3 : (reg_addr == {16'h3800 + 16'h0003}) ? mbus_out_ch3 : (reg_addr == {16'h3800 + 16'h0004}) ? mbus_out_ch3 : (reg_addr == {16'h3800 + 16'h0005}) ? mbus_out_ch3 : (reg_addr == {16'h3800 + 16'h0006}) ? mbus_out_ch3 : (reg_addr == {16'h3800 + 16'h0007}) ? mbus_out_ch3 : (reg_addr == {16'h3C00 + 16'h0000}) ? mbus_out_ch3 : (reg_addr == {16'h3C00 + 16'h0001}) ? mbus_out_ch3 : (reg_addr == {16'h3C00 + 16'h0002}) ? mbus_out_ch3 : (reg_addr == {16'h3C00 + 16'h0003}) ? mbus_out_ch3 : (reg_addr == {16'h3C00 + 16'h0004}) ? mbus_out_ch3 : (reg_addr == {16'h3C00 + 16'h0005}) ? mbus_out_ch3 : (reg_addr == {16'h3C00 + 16'h0006}) ? mbus_out_ch3 : (reg_addr == {16'h3C00 + 16'h0007}) ? mbus_out_ch3 : (reg_addr == {16'h3C00 + 16'h0008}) ? mbus_out_ch3 : (reg_addr == {16'h3C00 + 16'h0009}) ? mbus_out_ch3 : (reg_addr == {16'h3C00 + 16'h000A}) ? mbus_out_ch3 : (reg_addr == {16'h3C00 + 16'h000B}) ? mbus_out_ch3 : (reg_addr == {16'h3C00 + 16'h000C}) ? mbus_out_ch3 : (reg_addr == {16'h3C00 + 16'h000D}) ? mbus_out_ch3 : (reg_addr == {16'h3C00 + 16'h000E}) ? mbus_out_ch3 : (reg_addr == {16'h3C00 + 16'h000F}) ? mbus_out_ch3 : (reg_addr == {16'h3C00 + 16'h0010}) ? mbus_out_ch3 : (reg_addr == {16'h3C00 + 16'h0011}) ? mbus_out_ch3 : 16'h0000; endmodule //IP Functional Simulation Model //VERSION_BEGIN 12.0 cbx_mgl 2012:05:31:20:09:47:SJ cbx_simgen 2012:05:31:20:08:35:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 // Copyright (C) 1991-2012 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // You may only use these simulation model output files for simulation // purposes and expressly not for synthesis or any other purposes (in which // event Altera disclaims all warranties of any kind). //synopsys translate_off //synthesis_resources = lut 33 mux21 32 oper_add 1 `timescale 1 ps / 1 ps module stratixiv_hssi_cmu_dprio_addr ( incr_addr, mdc, mdio_in, reg_addr, reset, shift_addr) /* synthesis synthesis_clearbox=1 */; input incr_addr; input mdc; input mdio_in; output [15:0] reg_addr; input reset; input shift_addr; reg nlO0i15; reg nlO0i16; reg nlO0l13; reg nlO0l14; reg nlO0O11; reg nlO0O12; reg nlOii10; reg nlOii9; reg nlOil7; reg nlOil8; reg nlOiO5; reg nlOiO6; reg nlOli3; reg nlOli4; reg nlOOi1; reg nlOOi2; reg n0il; reg n0iO; reg n0li; reg n0ll; reg n0lO; reg n0Oi; reg n0Ol; reg n0OO; reg ni0i; reg ni0l; reg ni0O; reg ni1i; reg ni1l; reg ni1O; reg niii; reg niil; reg nili; reg niiO_clk_prev; wire wire_niiO_CLRN; wire wire_niiO_PRN; wire wire_n0i_dataout; wire wire_n0l_dataout; wire wire_n0O_dataout; wire wire_n1i_dataout; wire wire_n1l_dataout; wire wire_n1O_dataout; wire wire_nii_dataout; wire wire_nil_dataout; wire wire_nill_dataout; wire wire_nilO_dataout; wire wire_niO_dataout; wire wire_niOi_dataout; wire wire_niOl_dataout; wire wire_niOO_dataout; wire wire_nl0i_dataout; wire wire_nl0l_dataout; wire wire_nl0O_dataout; wire wire_nl1i_dataout; wire wire_nl1l_dataout; wire wire_nl1O_dataout; wire wire_nli_dataout; wire wire_nlii_dataout; wire wire_nlil_dataout; wire wire_nliO_dataout; wire wire_nll_dataout; wire wire_nlli_dataout; wire wire_nlll_dataout; wire wire_nllO_dataout; wire wire_nlO_dataout; wire wire_nlOi_dataout; wire wire_nlOl_dataout; wire wire_nlOO_dataout; wire [15:0] wire_ni_o; wire nlO1O; wire nlOll; wire nlOlO; initial nlO0i15 = 0; always @ ( posedge mdc) nlO0i15 <= nlO0i16; event nlO0i15_event; initial #1 ->nlO0i15_event; always @(nlO0i15_event) nlO0i15 <= {1{1'b1}}; initial nlO0i16 = 0; always @ ( posedge mdc) nlO0i16 <= nlO0i15; initial nlO0l13 = 0; always @ ( posedge mdc) nlO0l13 <= nlO0l14; event nlO0l13_event; initial #1 ->nlO0l13_event; always @(nlO0l13_event) nlO0l13 <= {1{1'b1}}; initial nlO0l14 = 0; always @ ( posedge mdc) nlO0l14 <= nlO0l13; initial nlO0O11 = 0; always @ ( posedge mdc) nlO0O11 <= nlO0O12; event nlO0O11_event; initial #1 ->nlO0O11_event; always @(nlO0O11_event) nlO0O11 <= {1{1'b1}}; initial nlO0O12 = 0; always @ ( posedge mdc) nlO0O12 <= nlO0O11; initial nlOii10 = 0; always @ ( posedge mdc) nlOii10 <= nlOii9; initial nlOii9 = 0; always @ ( posedge mdc) nlOii9 <= nlOii10; event nlOii9_event; initial #1 ->nlOii9_event; always @(nlOii9_event) nlOii9 <= {1{1'b1}}; initial nlOil7 = 0; always @ ( posedge mdc) nlOil7 <= nlOil8; event nlOil7_event; initial #1 ->nlOil7_event; always @(nlOil7_event) nlOil7 <= {1{1'b1}}; initial nlOil8 = 0; always @ ( posedge mdc) nlOil8 <= nlOil7; initial nlOiO5 = 0; always @ ( posedge mdc) nlOiO5 <= nlOiO6; event nlOiO5_event; initial #1 ->nlOiO5_event; always @(nlOiO5_event) nlOiO5 <= {1{1'b1}}; initial nlOiO6 = 0; always @ ( posedge mdc) nlOiO6 <= nlOiO5; initial nlOli3 = 0; always @ ( posedge mdc) nlOli3 <= nlOli4; event nlOli3_event; initial #1 ->nlOli3_event; always @(nlOli3_event) nlOli3 <= {1{1'b1}}; initial nlOli4 = 0; always @ ( posedge mdc) nlOli4 <= nlOli3; initial nlOOi1 = 0; always @ ( posedge mdc) nlOOi1 <= nlOOi2; event nlOOi1_event; initial #1 ->nlOOi1_event; always @(nlOOi1_event) nlOOi1 <= {1{1'b1}}; initial nlOOi2 = 0; always @ ( posedge mdc) nlOOi2 <= nlOOi1; initial begin n0il = 0; n0iO = 0; n0li = 0; n0ll = 0; n0lO = 0; n0Oi = 0; n0Ol = 0; n0OO = 0; ni0i = 0; ni0l = 0; ni0O = 0; ni1i = 0; ni1l = 0; ni1O = 0; niii = 0; niil = 0; nili = 0; end always @ (mdc or wire_niiO_PRN or wire_niiO_CLRN) begin if (wire_niiO_PRN == 1'b0) begin n0il <= 1; n0iO <= 1; n0li <= 1; n0ll <= 1; n0lO <= 1; n0Oi <= 1; n0Ol <= 1; n0OO <= 1; ni0i <= 1; ni0l <= 1; ni0O <= 1; ni1i <= 1; ni1l <= 1; ni1O <= 1; niii <= 1; niil <= 1; nili <= 1; end else if (wire_niiO_CLRN == 1'b0) begin n0il <= 0; n0iO <= 0; n0li <= 0; n0ll <= 0; n0lO <= 0; n0Oi <= 0; n0Ol <= 0; n0OO <= 0; ni0i <= 0; ni0l <= 0; ni0O <= 0; ni1i <= 0; ni1l <= 0; ni1O <= 0; niii <= 0; niil <= 0; nili <= 0; end else if (mdc != niiO_clk_prev && mdc == 1'b1) begin n0il <= wire_nill_dataout; n0iO <= wire_nilO_dataout; n0li <= wire_niOi_dataout; n0ll <= wire_niOl_dataout; n0lO <= wire_niOO_dataout; n0Oi <= wire_nl1i_dataout; n0Ol <= wire_nl1l_dataout; n0OO <= wire_nl1O_dataout; ni0i <= wire_nlii_dataout; ni0l <= wire_nlil_dataout; ni0O <= wire_nliO_dataout; ni1i <= wire_nl0i_dataout; ni1l <= wire_nl0l_dataout; ni1O <= wire_nl0O_dataout; niii <= wire_nlli_dataout; niil <= wire_nlll_dataout; nili <= mdio_in; end niiO_clk_prev <= mdc; end assign wire_niiO_CLRN = ((nlO0l14 ^ nlO0l13) & (~ reset)), wire_niiO_PRN = (nlO0i16 ^ nlO0i15); assign wire_n0i_dataout = (nlOll === 1'b1) ? wire_ni_o[7] : n0OO; assign wire_n0l_dataout = (nlOll === 1'b1) ? wire_ni_o[8] : ni1i; assign wire_n0O_dataout = (nlOll === 1'b1) ? wire_ni_o[9] : ni1l; assign wire_n1i_dataout = (nlOll === 1'b1) ? wire_ni_o[4] : n0lO; assign wire_n1l_dataout = (nlOll === 1'b1) ? wire_ni_o[5] : n0Oi; assign wire_n1O_dataout = (nlOll === 1'b1) ? wire_ni_o[6] : n0Ol; assign wire_nii_dataout = (nlOll === 1'b1) ? wire_ni_o[10] : ni1O; assign wire_nil_dataout = (nlOll === 1'b1) ? wire_ni_o[11] : ni0i; assign wire_nill_dataout = (shift_addr === 1'b1) ? nili : wire_nllO_dataout; assign wire_nilO_dataout = (shift_addr === 1'b1) ? n0il : wire_nlOi_dataout; assign wire_niO_dataout = (nlOll === 1'b1) ? wire_ni_o[12] : ni0l; assign wire_niOi_dataout = (shift_addr === 1'b1) ? n0iO : wire_nlOl_dataout; assign wire_niOl_dataout = (shift_addr === 1'b1) ? n0li : wire_nlOO_dataout; assign wire_niOO_dataout = (shift_addr === 1'b1) ? n0ll : wire_n1i_dataout; assign wire_nl0i_dataout = (shift_addr === 1'b1) ? n0OO : wire_n0l_dataout; assign wire_nl0l_dataout = (shift_addr === 1'b1) ? ni1i : wire_n0O_dataout; assign wire_nl0O_dataout = (shift_addr === 1'b1) ? ni1l : wire_nii_dataout; assign wire_nl1i_dataout = (shift_addr === 1'b1) ? n0lO : wire_n1l_dataout; assign wire_nl1l_dataout = (shift_addr === 1'b1) ? n0Oi : wire_n1O_dataout; assign wire_nl1O_dataout = (shift_addr === 1'b1) ? n0Ol : wire_n0i_dataout; assign wire_nli_dataout = (nlOll === 1'b1) ? wire_ni_o[13] : ni0O; assign wire_nlii_dataout = (shift_addr === 1'b1) ? ni1O : wire_nil_dataout; assign wire_nlil_dataout = (shift_addr === 1'b1) ? ni0i : wire_niO_dataout; assign wire_nliO_dataout = (shift_addr === 1'b1) ? ni0l : wire_nli_dataout; assign wire_nll_dataout = (nlOll === 1'b1) ? wire_ni_o[14] : niii; assign wire_nlli_dataout = (shift_addr === 1'b1) ? ni0O : wire_nll_dataout; assign wire_nlll_dataout = (shift_addr === 1'b1) ? niii : wire_nlO_dataout; assign wire_nllO_dataout = (nlOll === 1'b1) ? wire_ni_o[0] : n0il; assign wire_nlO_dataout = (nlOll === 1'b1) ? wire_ni_o[15] : niil; assign wire_nlOi_dataout = (nlOll === 1'b1) ? wire_ni_o[1] : n0iO; assign wire_nlOl_dataout = (nlOll === 1'b1) ? wire_ni_o[2] : n0li; assign wire_nlOO_dataout = (nlOll === 1'b1) ? wire_ni_o[3] : n0ll; oper_add ni ( .a({((nlO0O12 ^ nlO0O11) & niil), niii, ni0O, ni0l, ni0i, ni1O, ((nlOii10 ^ nlOii9) & ni1l), ni1i, ((nlOil8 ^ nlOil7) & n0OO), ((nlOiO6 ^ nlOiO5) & n0Ol), n0Oi, n0lO, ((nlOli4 ^ nlOli3) & n0ll), n0li, n0iO, n0il}), .b({{15{1'b0}}, 1'b1}), .cin(1'b0), .cout(), .o(wire_ni_o)); defparam ni.sgate_representation = 0, ni.width_a = 16, ni.width_b = 16, ni.width_o = 16; assign nlO1O = 1'b1, nlOll = ((~ nlOlO) & incr_addr), nlOlO = ((((((((((((((((niil & niii) & ni0O) & ni0l) & ni0i) & ni1O) & ni1l) & ni1i) & n0OO) & n0Ol) & n0Oi) & n0lO) & n0ll) & n0li) & n0iO) & n0il) & (nlOOi2 ^ nlOOi1)), reg_addr = {niil, niii, ni0O, ni0l, ni0i, ni1O, ni1l, ni1i, n0OO, n0Ol, n0Oi, n0lO, n0ll, n0li, n0iO, n0il}; endmodule //stratixiv_hssi_cmu_dprio_addr //synopsys translate_on //VALID FILE //IP Functional Simulation Model //VERSION_BEGIN 12.0 cbx_mgl 2012:05:31:20:09:47:SJ cbx_simgen 2012:05:31:20:08:35:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 // Copyright (C) 1991-2012 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // You may only use these simulation model output files for simulation // purposes and expressly not for synthesis or any other purposes (in which // event Altera disclaims all warranties of any kind). //synopsys translate_off //synthesis_resources = lut 17 mux21 10 oper_add 1 `timescale 1 ps / 1 ps module stratixiv_hssi_cmu_dprio_cnt ( cnt_eq_0, cnt_val, ld_cnt, mdc, reset) /* synthesis synthesis_clearbox=1 */; output cnt_eq_0; input [4:0] cnt_val; input ld_cnt; input mdc; input reset; reg ni0O10; reg ni0O9; reg ni1O11; reg ni1O12; reg niiO7; reg niiO8; reg nili5; reg nili6; reg nill3; reg nill4; reg niOi1; reg niOi2; reg n1i; reg ni; reg nlOi; reg nlOl; reg nlOO; reg nlO_clk_prev; wire wire_nlO_CLRN; wire wire_nlO_PRN; wire wire_n0i_dataout; wire wire_n0l_dataout; wire wire_n0O_dataout; wire wire_n1l_dataout; wire wire_n1O_dataout; wire wire_nii_dataout; wire wire_nil_dataout; wire wire_niO_dataout; wire wire_nli_dataout; wire wire_nll_dataout; wire [5:0] wire_nl_o; wire ni0l; wire niil; wire nilO; initial ni0O10 = 0; always @ ( posedge mdc) ni0O10 <= ni0O9; initial ni0O9 = 0; always @ ( posedge mdc) ni0O9 <= ni0O10; event ni0O9_event; initial #1 ->ni0O9_event; always @(ni0O9_event) ni0O9 <= {1{1'b1}}; initial ni1O11 = 0; always @ ( posedge mdc) ni1O11 <= ni1O12; event ni1O11_event; initial #1 ->ni1O11_event; always @(ni1O11_event) ni1O11 <= {1{1'b1}}; initial ni1O12 = 0; always @ ( posedge mdc) ni1O12 <= ni1O11; initial niiO7 = 0; always @ ( posedge mdc) niiO7 <= niiO8; event niiO7_event; initial #1 ->niiO7_event; always @(niiO7_event) niiO7 <= {1{1'b1}}; initial niiO8 = 0; always @ ( posedge mdc) niiO8 <= niiO7; initial nili5 = 0; always @ ( posedge mdc) nili5 <= nili6; event nili5_event; initial #1 ->nili5_event; always @(nili5_event) nili5 <= {1{1'b1}}; initial nili6 = 0; always @ ( posedge mdc) nili6 <= nili5; initial nill3 = 0; always @ ( posedge mdc) nill3 <= nill4; event nill3_event; initial #1 ->nill3_event; always @(nill3_event) nill3 <= {1{1'b1}}; initial nill4 = 0; always @ ( posedge mdc) nill4 <= nill3; initial niOi1 = 0; always @ ( posedge mdc) niOi1 <= niOi2; event niOi1_event; initial #1 ->niOi1_event; always @(niOi1_event) niOi1 <= {1{1'b1}}; initial niOi2 = 0; always @ ( posedge mdc) niOi2 <= niOi1; initial begin n1i = 0; ni = 0; nlOi = 0; nlOl = 0; nlOO = 0; end always @ (mdc or wire_nlO_PRN or wire_nlO_CLRN) begin if (wire_nlO_PRN == 1'b0) begin n1i <= 1; ni <= 1; nlOi <= 1; nlOl <= 1; nlOO <= 1; end else if (wire_nlO_CLRN == 1'b0) begin n1i <= 0; ni <= 0; nlOi <= 0; nlOl <= 0; nlOO <= 0; end else if (mdc != nlO_clk_prev && mdc == 1'b1) begin n1i <= wire_n0O_dataout; ni <= wire_n1l_dataout; nlOi <= wire_n1O_dataout; nlOl <= wire_n0i_dataout; nlOO <= wire_n0l_dataout; end nlO_clk_prev <= mdc; end assign wire_nlO_CLRN = ((nili6 ^ nili5) & (~ reset)), wire_nlO_PRN = (niiO8 ^ niiO7); assign wire_n0i_dataout = (ld_cnt === 1'b1) ? cnt_val[2] : wire_niO_dataout; assign wire_n0l_dataout = (ld_cnt === 1'b1) ? cnt_val[3] : wire_nli_dataout; assign wire_n0O_dataout = (ld_cnt === 1'b1) ? cnt_val[4] : wire_nll_dataout; assign wire_n1l_dataout = (ld_cnt === 1'b1) ? cnt_val[0] : wire_nii_dataout; assign wire_n1O_dataout = (ld_cnt === 1'b1) ? cnt_val[1] : wire_nil_dataout; assign wire_nii_dataout = (nilO === 1'b1) ? wire_nl_o[1] : ni; assign wire_nil_dataout = (nilO === 1'b1) ? wire_nl_o[2] : nlOi; assign wire_niO_dataout = (nilO === 1'b1) ? wire_nl_o[3] : nlOl; assign wire_nli_dataout = (nilO === 1'b1) ? wire_nl_o[4] : nlOO; assign wire_nll_dataout = (nilO === 1'b1) ? wire_nl_o[5] : n1i; oper_add nl ( .a({((nill4 ^ nill3) & n1i), nlOO, nlOl, nlOi, ni, 1'b1}), .b({{4{1'b1}}, 1'b0, 1'b1}), .cin(1'b0), .cout(), .o(wire_nl_o)); defparam nl.sgate_representation = 0, nl.width_a = 6, nl.width_b = 6, nl.width_o = 6; assign cnt_eq_0 = (((~ ni0l) & (~ ld_cnt)) & (ni1O12 ^ ni1O11)), ni0l = (((((ni | n1i) | nlOO) | nlOl) | nlOi) | (~ (ni0O10 ^ ni0O9))), niil = 1'b1, nilO = (((((ni | n1i) | nlOO) | nlOl) | nlOi) | (~ (niOi2 ^ niOi1))); endmodule //stratixiv_hssi_cmu_dprio_cnt //synopsys translate_on //VALID FILE //IP Functional Simulation Model //VERSION_BEGIN 12.0 cbx_mgl 2012:05:31:20:09:47:SJ cbx_simgen 2012:05:31:20:08:35:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 // Copyright (C) 1991-2012 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // You may only use these simulation model output files for simulation // purposes and expressly not for synthesis or any other purposes (in which // event Altera disclaims all warranties of any kind). //synopsys translate_off //synthesis_resources = lut 47 mux21 36 `timescale 1 ps / 1 ps module stratixiv_hssi_cmu_dprio_ctl_data ( data_enable_n, dev_addr, latch_ctl, ld_data, mbus_in, mbus_out, mdc, mdio_in, mdio_out, opcode, port_addr, reset, shift_in, shift_out, valid_addr, valid_addr_lt) /* synthesis synthesis_clearbox=1 */; output data_enable_n; input [4:0] dev_addr; input latch_ctl; input ld_data; output [15:0] mbus_in; input [15:0] mbus_out; input mdc; input mdio_in; output mdio_out; output [1:0] opcode; input [4:0] port_addr; input reset; input shift_in; input shift_out; output valid_addr; input valid_addr_lt; reg nilll25; reg nilll26; reg nilOi23; reg nilOi24; reg nilOO21; reg nilOO22; reg niO0i17; reg niO0i18; reg niO0O15; reg niO0O16; reg niO1l19; reg niO1l20; reg niOil13; reg niOil14; reg niOiO11; reg niOiO12; reg niOlO10; reg niOlO9; reg niOOl7; reg niOOl8; reg nl10l3; reg nl10l4; reg nl11l5; reg nl11l6; reg nl1iO1; reg nl1iO2; reg n1li; reg n1lO; reg n1ll_clk_prev; wire wire_n1ll_PRN; reg n00i; reg n00l; reg n00O; reg n01l; reg n01O; reg n0ii; reg n0il; reg n0iO; reg n0li; reg n0ll; reg n0lO; reg n0Oi; reg n0Ol; reg n0OO; reg n1iO; reg n1Oi; reg ni0i; reg ni1i; reg ni1l; wire wire_ni1O_CLRN; wire wire_n0i_dataout; wire wire_n0l_dataout; wire wire_n0O_dataout; wire wire_n1i_dataout; wire wire_n1l_dataout; wire wire_n1O_dataout; wire wire_n1Ol_dataout; wire wire_n1OO_dataout; wire wire_ni0l_dataout; wire wire_ni0O_dataout; wire wire_niii_dataout; wire wire_niil_dataout; wire wire_niiO_dataout; wire wire_nili_dataout; wire wire_nill_dataout; wire wire_nilO_dataout; wire wire_niOi_dataout; wire wire_niOl_dataout; wire wire_niOO_dataout; wire wire_nl_dataout; wire wire_nl0i_dataout; wire wire_nl0l_dataout; wire wire_nl0O_dataout; wire wire_nl1i_dataout; wire wire_nl1l_dataout; wire wire_nl1O_dataout; wire wire_nlii_dataout; wire wire_nlil_dataout; wire wire_nliO_dataout; wire wire_nlli_dataout; wire wire_nlll_dataout; wire wire_nllO_dataout; wire wire_nlOi_dataout; wire wire_nlOl_dataout; wire wire_nlOO_dataout; wire wire_nO_dataout; wire niOll; wire nl10i; wire nl11i; wire nl11O; wire nl1ii; wire nl1il; initial nilll25 = 0; always @ ( posedge mdc) nilll25 <= nilll26; event nilll25_event; initial #1 ->nilll25_event; always @(nilll25_event) nilll25 <= {1{1'b1}}; initial nilll26 = 0; always @ ( posedge mdc) nilll26 <= nilll25; initial nilOi23 = 0; always @ ( posedge mdc) nilOi23 <= nilOi24; event nilOi23_event; initial #1 ->nilOi23_event; always @(nilOi23_event) nilOi23 <= {1{1'b1}}; initial nilOi24 = 0; always @ ( posedge mdc) nilOi24 <= nilOi23; initial nilOO21 = 0; always @ ( posedge mdc) nilOO21 <= nilOO22; event nilOO21_event; initial #1 ->nilOO21_event; always @(nilOO21_event) nilOO21 <= {1{1'b1}}; initial nilOO22 = 0; always @ ( posedge mdc) nilOO22 <= nilOO21; initial niO0i17 = 0; always @ ( posedge mdc) niO0i17 <= niO0i18; event niO0i17_event; initial #1 ->niO0i17_event; always @(niO0i17_event) niO0i17 <= {1{1'b1}}; initial niO0i18 = 0; always @ ( posedge mdc) niO0i18 <= niO0i17; initial niO0O15 = 0; always @ ( posedge mdc) niO0O15 <= niO0O16; event niO0O15_event; initial #1 ->niO0O15_event; always @(niO0O15_event) niO0O15 <= {1{1'b1}}; initial niO0O16 = 0; always @ ( posedge mdc) niO0O16 <= niO0O15; initial niO1l19 = 0; always @ ( posedge mdc) niO1l19 <= niO1l20; event niO1l19_event; initial #1 ->niO1l19_event; always @(niO1l19_event) niO1l19 <= {1{1'b1}}; initial niO1l20 = 0; always @ ( posedge mdc) niO1l20 <= niO1l19; initial niOil13 = 0; always @ ( posedge mdc) niOil13 <= niOil14; event niOil13_event; initial #1 ->niOil13_event; always @(niOil13_event) niOil13 <= {1{1'b1}}; initial niOil14 = 0; always @ ( posedge mdc) niOil14 <= niOil13; initial niOiO11 = 0; always @ ( posedge mdc) niOiO11 <= niOiO12; event niOiO11_event; initial #1 ->niOiO11_event; always @(niOiO11_event) niOiO11 <= {1{1'b1}}; initial niOiO12 = 0; always @ ( posedge mdc) niOiO12 <= niOiO11; initial niOlO10 = 0; always @ ( posedge mdc) niOlO10 <= niOlO9; initial niOlO9 = 0; always @ ( posedge mdc) niOlO9 <= niOlO10; event niOlO9_event; initial #1 ->niOlO9_event; always @(niOlO9_event) niOlO9 <= {1{1'b1}}; initial niOOl7 = 0; always @ ( posedge mdc) niOOl7 <= niOOl8; event niOOl7_event; initial #1 ->niOOl7_event; always @(niOOl7_event) niOOl7 <= {1{1'b1}}; initial niOOl8 = 0; always @ ( posedge mdc) niOOl8 <= niOOl7; initial nl10l3 = 0; always @ ( posedge mdc) nl10l3 <= nl10l4; event nl10l3_event; initial #1 ->nl10l3_event; always @(nl10l3_event) nl10l3 <= {1{1'b1}}; initial nl10l4 = 0; always @ ( posedge mdc) nl10l4 <= nl10l3; initial nl11l5 = 0; always @ ( posedge mdc) nl11l5 <= nl11l6; event nl11l5_event; initial #1 ->nl11l5_event; always @(nl11l5_event) nl11l5 <= {1{1'b1}}; initial nl11l6 = 0; always @ ( posedge mdc) nl11l6 <= nl11l5; initial nl1iO1 = 0; always @ ( posedge mdc) nl1iO1 <= nl1iO2; event nl1iO1_event; initial #1 ->nl1iO1_event; always @(nl1iO1_event) nl1iO1 <= {1{1'b1}}; initial nl1iO2 = 0; always @ ( posedge mdc) nl1iO2 <= nl1iO1; initial begin n1li = 0; n1lO = 0; end always @ (mdc or wire_n1ll_PRN or reset) begin if (wire_n1ll_PRN == 1'b0) begin n1li <= 1; n1lO <= 1; end else if (reset == 1'b1) begin n1li <= 0; n1lO <= 0; end else if (latch_ctl == 1'b1) if (mdc != n1ll_clk_prev && mdc == 1'b1) begin n1li <= n0lO; n1lO <= n0Oi; end n1ll_clk_prev <= mdc; end assign wire_n1ll_PRN = (niOil14 ^ niOil13); initial begin n00i = 0; n00l = 0; n00O = 0; n01l = 0; n01O = 0; n0ii = 0; n0il = 0; n0iO = 0; n0li = 0; n0ll = 0; n0lO = 0; n0Oi = 0; n0Ol = 0; n0OO = 0; n1iO = 0; n1Oi = 0; ni0i = 0; ni1i = 0; ni1l = 0; end always @ ( posedge mdc or negedge wire_ni1O_CLRN) begin if (wire_ni1O_CLRN == 1'b0) begin n00i <= 0; n00l <= 0; n00O <= 0; n01l <= 0; n01O <= 0; n0ii <= 0; n0il <= 0; n0iO <= 0; n0li <= 0; n0ll <= 0; n0lO <= 0; n0Oi <= 0; n0Ol <= 0; n0OO <= 0; n1iO <= 0; n1Oi <= 0; ni0i <= 0; ni1i <= 0; ni1l <= 0; end else begin n00i <= wire_ni0O_dataout; n00l <= wire_niii_dataout; n00O <= wire_niil_dataout; n01l <= wire_n1Ol_dataout; n01O <= wire_ni0l_dataout; n0ii <= wire_niiO_dataout; n0il <= wire_nili_dataout; n0iO <= wire_nill_dataout; n0li <= wire_nilO_dataout; n0ll <= wire_niOi_dataout; n0lO <= wire_niOl_dataout; n0Oi <= wire_niOO_dataout; n0Ol <= wire_nl1i_dataout; n0OO <= wire_nl1l_dataout; n1iO <= wire_n1OO_dataout; n1Oi <= mdio_in; ni0i <= wire_nl0l_dataout; ni1i <= wire_nl1O_dataout; ni1l <= wire_nl0i_dataout; end end assign wire_ni1O_CLRN = ((nl11l6 ^ nl11l5) & (~ reset)); assign wire_n0i_dataout = (nl11O === 1'b1) ? n0OO : ni1i; assign wire_n0l_dataout = (nl11O === 1'b1) ? ni1i : ni1l; assign wire_n0O_dataout = (nl11O === 1'b1) ? ni1l : ni0i; assign wire_n1i_dataout = (nl11O === 1'b1) ? n0lO : n0Oi; assign wire_n1l_dataout = (nl11O === 1'b1) ? n0Oi : n0Ol; assign wire_n1O_dataout = (nl11O === 1'b1) ? n0Ol : n0OO; assign wire_n1Ol_dataout = (latch_ctl === 1'b1) ? niOll : ((n01l & n1iO) & (niOiO12 ^ niOiO11)); and(wire_n1OO_dataout, niOll, latch_ctl); assign wire_ni0l_dataout = (ld_data === 1'b1) ? mbus_out[15] : wire_nl0O_dataout; assign wire_ni0O_dataout = (ld_data === 1'b1) ? mbus_out[0] : wire_nlii_dataout; assign wire_niii_dataout = (ld_data === 1'b1) ? mbus_out[1] : wire_nlil_dataout; assign wire_niil_dataout = (ld_data === 1'b1) ? mbus_out[2] : wire_nliO_dataout; assign wire_niiO_dataout = (ld_data === 1'b1) ? mbus_out[3] : wire_nlli_dataout; assign wire_nili_dataout = (ld_data === 1'b1) ? mbus_out[4] : wire_nlll_dataout; assign wire_nill_dataout = (ld_data === 1'b1) ? mbus_out[5] : wire_nllO_dataout; assign wire_nilO_dataout = (ld_data === 1'b1) ? mbus_out[6] : wire_nlOi_dataout; assign wire_niOi_dataout = (ld_data === 1'b1) ? mbus_out[7] : wire_nlOl_dataout; assign wire_niOl_dataout = (ld_data === 1'b1) ? mbus_out[8] : wire_nlOO_dataout; assign wire_niOO_dataout = (ld_data === 1'b1) ? mbus_out[9] : wire_n1i_dataout; assign wire_nl_dataout = (ld_data === 1'b1) ? mbus_out[15] : wire_nO_dataout; assign wire_nl0i_dataout = (ld_data === 1'b1) ? mbus_out[13] : wire_n0l_dataout; assign wire_nl0l_dataout = (ld_data === 1'b1) ? mbus_out[14] : wire_n0O_dataout; assign wire_nl0O_dataout = (nl11O === 1'b1) ? n1Oi : n01O; assign wire_nl1i_dataout = (ld_data === 1'b1) ? mbus_out[10] : wire_n1l_dataout; assign wire_nl1l_dataout = (ld_data === 1'b1) ? mbus_out[11] : wire_n1O_dataout; assign wire_nl1O_dataout = (ld_data === 1'b1) ? mbus_out[12] : wire_n0i_dataout; assign wire_nlii_dataout = (nl11O === 1'b1) ? n01O : n00i; assign wire_nlil_dataout = (nl11O === 1'b1) ? n00i : n00l; assign wire_nliO_dataout = (nl11O === 1'b1) ? n00l : n00O; assign wire_nlli_dataout = (nl11O === 1'b1) ? n00O : n0ii; assign wire_nlll_dataout = (nl11O === 1'b1) ? n0ii : n0il; assign wire_nllO_dataout = (nl11O === 1'b1) ? n0il : n0iO; assign wire_nlOi_dataout = (nl11O === 1'b1) ? n0iO : n0li; assign wire_nlOl_dataout = (nl11O === 1'b1) ? n0li : n0ll; assign wire_nlOO_dataout = (nl11O === 1'b1) ? n0ll : n0lO; and(wire_nO_dataout, ni0i, shift_out); assign data_enable_n = (~ ((((shift_out | ld_data) | n01l) & (nl10i | valid_addr_lt)) & (niO0O16 ^ niO0O15))), mbus_in = {ni0i, ni1l, ni1i, n0OO, n0Ol, n0Oi, n0lO, n0ll, n0li, n0iO, n0il, n0ii, n00O, n00l, n00i, n01O}, mdio_out = wire_nl_dataout, niOll = (((n0Oi & n0lO) | ((n0Oi & (~ n0lO)) & (niOOl8 ^ niOOl7))) | (~ (niOlO10 ^ niOlO9))), nl10i = ((((((~ ni1i) & (~ n0OO)) & (nl1iO2 ^ nl1iO1)) & nl1il) & nl1ii) & (nl10l4 ^ nl10l3)), nl11i = 1'b1, nl11O = (shift_in | shift_out), nl1ii = ((((((~ (n01O ^ dev_addr[0])) & (~ ((n00i ^ dev_addr[1]) ^ (~ (nilOO22 ^ nilOO21))))) & (~ ((n00l ^ dev_addr[2]) ^ (~ (nilOi24 ^ nilOi23))))) & (~ (n00O ^ dev_addr[3]))) & (~ (n0ii ^ dev_addr[4]))) & (nilll26 ^ nilll25)), nl1il = (((((~ (n0il ^ port_addr[0])) & (~ (n0iO ^ port_addr[1]))) & (~ ((n0li ^ port_addr[2]) ^ (~ (niO0i18 ^ niO0i17))))) & (~ ((n0ll ^ port_addr[3]) ^ (~ (niO1l20 ^ niO1l19))))) & (~ (n0lO ^ port_addr[4]))), opcode = {n1lO, n1li}, valid_addr = nl10i; endmodule //stratixiv_hssi_cmu_dprio_ctl_data //synopsys translate_on //VALID FILE `timescale 1 ns / 1 ps module stratixiv_hssi_cmu_dprio_sm (mdc, mdio_in, reset, opcode, valid_addr, cnt_eq_0, shift_in, shift_out, latch_ctl, incr_addr, mdio_wr, mdio_rd, shift_addr, ld_data, ld_cnt, cnt_val, valid_addr_lt, curr_state); input mdc; // Clock for MDIO interface input mdio_in; // Signal bit data input reset; // Active high Hard Reset input [1:0] opcode; // 2 bit opcode from mdio_ctl_data module // 00 - Address // 01 - Write // 10 - Read with no post Increment // 11 - Read with post increment input valid_addr; // When set the Port and Dev Address // corresponds to this module input cnt_eq_0; // From mdio_cnt module, down counter is 0 output shift_in; // Shift in enable for either data or control output shift_out; // Shift out enable for mdio_ctl_data output latch_ctl; // Latch the Opcode, to mdio_ctl_data output incr_addr; // Increment signal for mdio_addr output mdio_wr; // This is used for writing the mdio registers output mdio_rd; // This is used for clearing the mdio status registers output shift_addr; // Shift in Enable for mdio_addr output ld_data; // When set, the shift register is mdio_ctl_data is parallely // loaded with the data from mdio_reg module //output ld_data_d; output ld_cnt; // Load Down counter output [4:0] cnt_val; // Value to load the down counter output valid_addr_lt; output [2:0] curr_state; reg shift_in; reg shift_out; reg latch_ctl; reg incr_addr; reg mdio_wr; reg mdio_rd; reg shift_addr; reg ld_data; reg ld_cnt; reg [4:0] cnt_val; //wire ld_data_d; // Allowed states for curr_state and next_state parameter IDLE = 3'b000; parameter PREAMBLE = 3'b001; parameter CONTROL = 3'b010; parameter TURN_ARND_0 = 3'b011; parameter TURN_ARND_1 = 3'b100; parameter ADDR_DATA = 3'b101; // Decode for opcode parameter ADDR_OP = 2'b00; parameter WR_OP = 2'b01; parameter RD_INC_OP = 2'b10; parameter RD_OP = 2'b11; reg [2:0] curr_state; reg [2:0] next_state; reg valid_addr_lt; // Latch Curr State always @(posedge reset or posedge mdc) begin if (reset) curr_state <= IDLE; else curr_state <= next_state; end // Next State loic for mdio_sm always @(curr_state or mdio_in or cnt_eq_0 or valid_addr or opcode) begin case (curr_state) IDLE : if (mdio_in) next_state <= PREAMBLE; else next_state <= IDLE; PREAMBLE : if (~mdio_in && ~cnt_eq_0) next_state <= IDLE; else if (~mdio_in && cnt_eq_0) next_state <= CONTROL; else next_state <= PREAMBLE; CONTROL : if (cnt_eq_0) if (~mdio_in) next_state <= IDLE; else next_state <= TURN_ARND_0; else next_state <= CONTROL; TURN_ARND_0 : if (mdio_in || ~valid_addr) next_state <= IDLE; else if (opcode == WR_OP || opcode == ADDR_OP) next_state <= TURN_ARND_1; else next_state <= ADDR_DATA; TURN_ARND_1 : // if (mdio_in) // next_state <= IDLE; // else next_state <= ADDR_DATA; ADDR_DATA : if (cnt_eq_0 && mdio_in && (opcode == WR_OP || opcode == ADDR_OP)) next_state <= PREAMBLE; else if (cnt_eq_0) next_state <= IDLE; else next_state <= ADDR_DATA; default: next_state <= IDLE; endcase end // Valid_addr_lt is used to enable mdio_out always @(posedge reset or posedge mdc) begin if (reset) valid_addr_lt <= 1'b0; else if (valid_addr && curr_state == TURN_ARND_0) valid_addr_lt <= 1'b1; else if (curr_state == ADDR_DATA && cnt_eq_0) valid_addr_lt <= 1'b0; end // Logic for shift_in, This signal is used for shifting in // control logic, during all commands, and data during // Write command always @(posedge reset or posedge mdc) begin if (reset) shift_in <= 1'b0; else if ((curr_state == PREAMBLE && next_state == CONTROL) || (next_state == CONTROL) || (next_state == ADDR_DATA && opcode == WR_OP)) shift_in <= 1'b1; else shift_in <= 1'b0; end // Shift_out logic, shift_out is set when data is shifted out on // a RD_OP or RD_INC_OP command always @(posedge reset or posedge mdc) begin if (reset) shift_out <= 1'b0; else if ((curr_state == TURN_ARND_0 && next_state == ADDR_DATA) || (curr_state == ADDR_DATA && (opcode == RD_OP || opcode == RD_INC_OP) && (~cnt_eq_0))) shift_out <= 1'b1; else shift_out <= 1'b0; end // Logic for latch_ctl, this signal is used for latching the opcode // This signal is set when in Control state and moving to TURN_ARND_0 // state /* always @(posedge reset or posedge mdc) begin if (reset) latch_ctl <= 1'b0; else if (curr_state == CONTROL && next_state == TURN_ARND_0) latch_ctl <= 1'b1; else latch_ctl <= 1'b0; end */ always @(cnt_eq_0 or curr_state) latch_ctl = cnt_eq_0 && (curr_state == CONTROL); // Logic for incr_addr, incr_addr is set for opcode RD_INC_OP and // after completely shifting out the read data for the current command always @(posedge reset or posedge mdc) begin if (reset) incr_addr <= 1'b0; else if (curr_state == ADDR_DATA && cnt_eq_0 && opcode == RD_INC_OP) incr_addr <= 1'b1; else incr_addr <= 1'b0; end // Logic for shift addr, this bit is set when moving to ADDR_DATA // state and when in ADDR_DATA state for ADDR_OP command always @(posedge reset or posedge mdc) begin if (reset) shift_addr <= 1'b0; else if (next_state == ADDR_DATA && opcode == ADDR_OP) shift_addr <= 1'b1; else shift_addr <= 1'b0; end // Logic for mdio_wr, this bit is set when moving from ADDR_DATA to the // IDLE for a WR_OP command // Logic for mdio_rd, this bit is set when moving from ADDR_DATA to the // IDLE for a RD_OP/RD_INC_OP command always @(posedge reset or posedge mdc) begin if (reset) begin mdio_wr <= 1'b0; mdio_rd <= 1'b0; end else if (curr_state == ADDR_DATA && cnt_eq_0) begin if (opcode == WR_OP) mdio_wr <= 1'b1; else mdio_wr <= 1'b0; if (opcode == RD_OP || opcode == RD_INC_OP) mdio_rd <= 1'b1; else mdio_rd <= 1'b0; end else begin mdio_wr <= 1'b0; mdio_rd <= 1'b0; end end // Logic for ld_data, this signal is used for parallely loading the // shift register in mdio_ctl_data module with the data from mdio_reg // module. This set is set for RD_OP and RD_INC_OP commands when the // SM transitions from TURN_ARND_0 to ADDR_DATA state // assign ld_data_d = (curr_state == TURN_ARND_0 && (opcode == RD_OP | opcode == RD_INC_OP)); always @(posedge reset or posedge mdc) begin if (reset) ld_data <= 1'b0; else ld_data <= (curr_state == TURN_ARND_0 && next_state == ADDR_DATA); end // Logic for ld_cnt, this signal is used for loading the down counter // with cnt_val signal. This signal is set when going to // CONTROL state or ADDR_DATA state or PREAMBLE states always @(posedge reset or posedge mdc) begin if (reset) ld_cnt <= 1'b0; else if ((curr_state == IDLE && next_state == PREAMBLE) || (curr_state == ADDR_DATA && next_state == PREAMBLE) || (curr_state == PREAMBLE && next_state == CONTROL) || (curr_state == TURN_ARND_0 && next_state == ADDR_DATA) || (curr_state == TURN_ARND_1 && next_state == ADDR_DATA) ) ld_cnt <= 1'b1; else ld_cnt <= 1'b0; end // Logic for cnt_val, this counter value is used for sown counting // the mdio_cnt, when the counter reaches zero, the cnt_eq_0 is // set. The counter is loading with 31 for PREAMBLE, 13 for // CONTROL, and 15 for ADDR_DATA always @(posedge reset or posedge mdc) begin if (reset) cnt_val <= 5'b00000; else if ((curr_state == IDLE | curr_state == ADDR_DATA) && next_state == PREAMBLE) cnt_val <= 5'b11110; else if (curr_state == PREAMBLE && next_state == CONTROL) cnt_val <= 5'b01100; else if (curr_state == TURN_ARND_0 && next_state == ADDR_DATA) cnt_val <= 5'b01110; else if (curr_state == TURN_ARND_1 && next_state == ADDR_DATA) cnt_val <= 5'b01110; else cnt_val <= cnt_val; end endmodule `timescale 1 ps / 1 ps module stratixiv_hssi_cmu_dprio_reg_centrl (mdio_rst, mdio_wr, reg_addr, mdc, mbus_in, serial_mode, mdio_dis, pma_cram_test, ser_shift_load, si, // CSR input ext_centrl_ctrl_1, ext_centrl_ctrl_2, ext_centrl_ctrl_3, ext_centrl_ctrl_4, ext_centrl_ctrl_5, ext_centrl_ctrl_6, ext_centrl_ctrl_7, ext_centrl_ctrl_8, ext_centrl_ctrl_9, ext_centrl_ctrl_10, ext_centrl_ctrl_11, ext_centrl_ctrl_12, ext_centrl_ctrl_13, ext_centrl_ctrl_14, ext_centrl_ctrl_15, ext_centrl_ctrl_16, ext_centrl_ctrl_17, ext_centrl_ctrl_18, ext_centrl_ctrl_19, ext_centrl_ctrl_20, ext_centrl_ctrl_21, ext_centrl_ctrl_22, ext_centrl_ctrl_23, ext_centrl_ctrl_24, ext_centrl_ctrl_25, ext_centrl_ctrl_26, ext_centrl_ctrl_27, ext_centrl_ctrl_28, ext_centrl_ctrl_29, ext_centrl_ctrl_30, ext_centrl_ctrl_31, ext_centrl_ctrl_32, ext_centrl_ctrl_33, ext_centrl_ctrl_34, ext_centrl_ctrl_35, ext_centrl_ctrl_36, ext_centrl_ctrl_37, ext_centrl_ctrl_38, ext_centrl_ctrl_39, ext_centrl_ctrl_40, ext_centrl_ctrl_41, ext_centrl_ctrl_42, ext_centrl_ctrl_43, ext_centrl_ctrl_44, ext_centrl_ctrl_45, ext_centrl_ctrl_46, targ_addr_ctrl_1, targ_addr_ctrl_2, targ_addr_ctrl_3, targ_addr_ctrl_4, targ_addr_ctrl_5, targ_addr_ctrl_6, targ_addr_ctrl_7, targ_addr_ctrl_8, targ_addr_ctrl_9, targ_addr_ctrl_10, targ_addr_ctrl_11, targ_addr_ctrl_12, targ_addr_ctrl_13, targ_addr_ctrl_14, targ_addr_ctrl_15, targ_addr_ctrl_16, targ_addr_ctrl_17, targ_addr_ctrl_18, targ_addr_ctrl_19, targ_addr_ctrl_20, targ_addr_ctrl_21, targ_addr_ctrl_22, targ_addr_ctrl_23, targ_addr_ctrl_24, targ_addr_ctrl_25, targ_addr_ctrl_26, targ_addr_ctrl_27, targ_addr_ctrl_28, targ_addr_ctrl_29, targ_addr_ctrl_30, targ_addr_ctrl_31, targ_addr_ctrl_32, targ_addr_ctrl_33, targ_addr_ctrl_34, targ_addr_ctrl_35, targ_addr_ctrl_36, targ_addr_ctrl_37, targ_addr_ctrl_38, targ_addr_ctrl_39, targ_addr_ctrl_40, targ_addr_ctrl_41, targ_addr_ctrl_42, targ_addr_ctrl_43, targ_addr_ctrl_44, targ_addr_ctrl_45, targ_addr_ctrl_46, // DPRIO register output out_centrl_ctrl_1, out_centrl_ctrl_2, out_centrl_ctrl_3, out_centrl_ctrl_4, out_centrl_ctrl_5, out_centrl_ctrl_6, out_centrl_ctrl_7, out_centrl_ctrl_8, out_centrl_ctrl_9, out_centrl_ctrl_10, out_centrl_ctrl_11, out_centrl_ctrl_12, out_centrl_ctrl_13, out_centrl_ctrl_14, out_centrl_ctrl_15, out_centrl_ctrl_16, out_centrl_ctrl_17, out_centrl_ctrl_18, out_centrl_ctrl_19, out_centrl_ctrl_20, out_centrl_ctrl_21, out_centrl_ctrl_22, out_centrl_ctrl_23, out_centrl_ctrl_24, out_centrl_ctrl_25, out_centrl_ctrl_26, out_centrl_ctrl_27, out_centrl_ctrl_28, out_centrl_ctrl_29, out_centrl_ctrl_30, out_centrl_ctrl_31, out_centrl_ctrl_32, out_centrl_ctrl_33, out_centrl_ctrl_34, out_centrl_ctrl_35, out_centrl_ctrl_36, out_centrl_ctrl_37, out_centrl_ctrl_38, out_centrl_ctrl_39, out_centrl_ctrl_40, out_centrl_ctrl_41, out_centrl_ctrl_42, out_centrl_ctrl_43, out_centrl_ctrl_44, out_centrl_ctrl_45, out_centrl_ctrl_46, so); input mdio_rst; input mdio_wr; input [15:0] reg_addr; input mdc; input [15:0] mbus_in; input serial_mode; input mdio_dis; input pma_cram_test; input ser_shift_load; input si; input [15:0] ext_centrl_ctrl_1; input [15:0] ext_centrl_ctrl_2; input [15:0] ext_centrl_ctrl_3; input [15:0] ext_centrl_ctrl_4; input [15:0] ext_centrl_ctrl_5; input [15:0] ext_centrl_ctrl_6; input [15:0] ext_centrl_ctrl_7; input [15:0] ext_centrl_ctrl_8; input [15:0] ext_centrl_ctrl_9; input [15:0] ext_centrl_ctrl_10; input [15:0] ext_centrl_ctrl_11; input [15:0] ext_centrl_ctrl_12; input [15:0] ext_centrl_ctrl_13; input [15:0] ext_centrl_ctrl_14; input [15:0] ext_centrl_ctrl_15; input [15:0] ext_centrl_ctrl_16; input [15:0] ext_centrl_ctrl_17; input [15:0] ext_centrl_ctrl_18; input [15:0] ext_centrl_ctrl_19; input [15:0] ext_centrl_ctrl_20; input [15:0] ext_centrl_ctrl_21; input [15:0] ext_centrl_ctrl_22; input [15:0] ext_centrl_ctrl_23; input [15:0] ext_centrl_ctrl_24; input [15:0] ext_centrl_ctrl_25; input [15:0] ext_centrl_ctrl_26; input [15:0] ext_centrl_ctrl_27; input [15:0] ext_centrl_ctrl_28; input [15:0] ext_centrl_ctrl_29; input [15:0] ext_centrl_ctrl_30; input [15:0] ext_centrl_ctrl_31; input [15:0] ext_centrl_ctrl_32; input [15:0] ext_centrl_ctrl_33; input [15:0] ext_centrl_ctrl_34; input [15:0] ext_centrl_ctrl_35; input [15:0] ext_centrl_ctrl_36; input [15:0] ext_centrl_ctrl_37; input [15:0] ext_centrl_ctrl_38; input [15:0] ext_centrl_ctrl_39; input [15:0] ext_centrl_ctrl_40; input [15:0] ext_centrl_ctrl_41; input [15:0] ext_centrl_ctrl_42; input [15:0] ext_centrl_ctrl_43; input [15:0] ext_centrl_ctrl_44; input [15:0] ext_centrl_ctrl_45; input [15:0] ext_centrl_ctrl_46; input [15:0] targ_addr_ctrl_1; input [15:0] targ_addr_ctrl_2; input [15:0] targ_addr_ctrl_3; input [15:0] targ_addr_ctrl_4; input [15:0] targ_addr_ctrl_5; input [15:0] targ_addr_ctrl_6; input [15:0] targ_addr_ctrl_7; input [15:0] targ_addr_ctrl_8; input [15:0] targ_addr_ctrl_9; input [15:0] targ_addr_ctrl_10; input [15:0] targ_addr_ctrl_11; input [15:0] targ_addr_ctrl_12; input [15:0] targ_addr_ctrl_13; input [15:0] targ_addr_ctrl_14; input [15:0] targ_addr_ctrl_15; input [15:0] targ_addr_ctrl_16; input [15:0] targ_addr_ctrl_17; input [15:0] targ_addr_ctrl_18; input [15:0] targ_addr_ctrl_19; input [15:0] targ_addr_ctrl_20; input [15:0] targ_addr_ctrl_21; input [15:0] targ_addr_ctrl_22; input [15:0] targ_addr_ctrl_23; input [15:0] targ_addr_ctrl_24; input [15:0] targ_addr_ctrl_25; input [15:0] targ_addr_ctrl_26; input [15:0] targ_addr_ctrl_27; input [15:0] targ_addr_ctrl_28; input [15:0] targ_addr_ctrl_29; input [15:0] targ_addr_ctrl_30; input [15:0] targ_addr_ctrl_31; input [15:0] targ_addr_ctrl_32; input [15:0] targ_addr_ctrl_33; input [15:0] targ_addr_ctrl_34; input [15:0] targ_addr_ctrl_35; input [15:0] targ_addr_ctrl_36; input [15:0] targ_addr_ctrl_37; input [15:0] targ_addr_ctrl_38; input [15:0] targ_addr_ctrl_39; input [15:0] targ_addr_ctrl_40; input [15:0] targ_addr_ctrl_41; input [15:0] targ_addr_ctrl_42; input [15:0] targ_addr_ctrl_43; input [15:0] targ_addr_ctrl_44; input [15:0] targ_addr_ctrl_45; input [15:0] targ_addr_ctrl_46; output [15:0] out_centrl_ctrl_1; output [15:0] out_centrl_ctrl_2; output [15:0] out_centrl_ctrl_3; output [15:0] out_centrl_ctrl_4; output [15:0] out_centrl_ctrl_5; output [15:0] out_centrl_ctrl_6; output [15:0] out_centrl_ctrl_7; output [15:0] out_centrl_ctrl_8; output [15:0] out_centrl_ctrl_9; output [15:0] out_centrl_ctrl_10; output [15:0] out_centrl_ctrl_11; output [15:0] out_centrl_ctrl_12; output [15:0] out_centrl_ctrl_13; output [15:0] out_centrl_ctrl_14; output [15:0] out_centrl_ctrl_15; output [15:0] out_centrl_ctrl_16; output [15:0] out_centrl_ctrl_17; output [15:0] out_centrl_ctrl_18; output [15:0] out_centrl_ctrl_19; output [15:0] out_centrl_ctrl_20; output [15:0] out_centrl_ctrl_21; output [15:0] out_centrl_ctrl_22; output [15:0] out_centrl_ctrl_23; output [15:0] out_centrl_ctrl_24; output [15:0] out_centrl_ctrl_25; output [15:0] out_centrl_ctrl_26; output [15:0] out_centrl_ctrl_27; output [15:0] out_centrl_ctrl_28; output [15:0] out_centrl_ctrl_29; output [15:0] out_centrl_ctrl_30; output [15:0] out_centrl_ctrl_31; output [15:0] out_centrl_ctrl_32; output [15:0] out_centrl_ctrl_33; output [15:0] out_centrl_ctrl_34; output [15:0] out_centrl_ctrl_35; output [15:0] out_centrl_ctrl_36; output [15:0] out_centrl_ctrl_37; output [15:0] out_centrl_ctrl_38; output [15:0] out_centrl_ctrl_39; output [15:0] out_centrl_ctrl_40; output [15:0] out_centrl_ctrl_41; output [15:0] out_centrl_ctrl_42; output [15:0] out_centrl_ctrl_43; output [15:0] out_centrl_ctrl_44; output [15:0] out_centrl_ctrl_45; output [15:0] out_centrl_ctrl_46; output so; wire [44:0] chain; stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_1 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_1), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_1), .serial_mode (serial_mode), .si (si), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_1), .so (chain[0])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_2 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_2), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_2), .serial_mode (serial_mode), .si (chain[0]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_2), .so (chain[1])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_3 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_3), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_3), .serial_mode (serial_mode), .si (chain[1]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_3), .so (chain[2])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_4 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_4), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_4), .serial_mode (serial_mode), .si (chain[2]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_4), .so (chain[3])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_5 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_5), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_5), .serial_mode (serial_mode), .si (chain[3]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_5), .so (chain[4])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_6 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_6), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_6), .serial_mode (serial_mode), .si (chain[4]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_6), .so (chain[5])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_7 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_7), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_7), .serial_mode (serial_mode), .si (chain[5]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_7), .so (chain[6])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_8 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_8), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_8), .serial_mode (serial_mode), .si (chain[6]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_8), .so (chain[7])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_9 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_9), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_9), .serial_mode (serial_mode), .si (chain[7]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_9), .so (chain[8])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_10 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_10), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_10), .serial_mode (serial_mode), .si (chain[8]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_10), .so (chain[9])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_11 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_11), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_11), .serial_mode (serial_mode), .si (chain[9]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_11), .so (chain[10])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_12 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_12), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_12), .serial_mode (serial_mode), .si (chain[10]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_12), .so (chain[11])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_13 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_13), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_13), .serial_mode (serial_mode), .si (chain[11]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_13), .so (chain[12])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_14 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_14), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_14), .serial_mode (serial_mode), .si (chain[12]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_14), .so (chain[13])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_15 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_15), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_15), .serial_mode (serial_mode), .si (chain[13]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_15), .so (chain[14])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_16 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_16), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_16), .serial_mode (serial_mode), .si (chain[14]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_16), .so (chain[15])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_17 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_17), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_17), .serial_mode (serial_mode), .si (chain[15]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_17), .so (chain[16])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_18 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_18), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_18), .serial_mode (serial_mode), .si (chain[16]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_18), .so (chain[17])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_19 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_19), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_19), .serial_mode (serial_mode), .si (chain[17]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_19), .so (chain[18])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_20 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_20), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_20), .serial_mode (serial_mode), .si (chain[18]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_20), .so (chain[19])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_21 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_21), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_21), .serial_mode (serial_mode), .si (chain[19]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_21), .so (chain[20])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_22 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_22), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_22), .serial_mode (serial_mode), .si (chain[20]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_22), .so (chain[21])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_23 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_23), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_23), .serial_mode (serial_mode), .si (chain[21]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_23), .so (chain[22])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_24 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_24), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_24), .serial_mode (serial_mode), .si (chain[22]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_24), .so (chain[23])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_25 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_25), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_25), .serial_mode (serial_mode), .si (chain[23]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_25), .so (chain[24])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_26 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_26), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_26), .serial_mode (serial_mode), .si (chain[24]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_26), .so (chain[25])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_27 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_27), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_27), .serial_mode (serial_mode), .si (chain[25]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_27), .so (chain[26])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_28 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_28), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_28), .serial_mode (serial_mode), .si (chain[26]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_28), .so (chain[27])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_29 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_29), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_29), .serial_mode (serial_mode), .si (chain[27]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_29), .so (chain[28])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_30 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_30), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_30), .serial_mode (serial_mode), .si (chain[28]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_30), .so (chain[29])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_31 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_31), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_31), .serial_mode (serial_mode), .si (chain[29]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_31), .so (chain[30])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_32 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_32), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_32), .serial_mode (serial_mode), .si (chain[30]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_32), .so (chain[31])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_33 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_33), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_33), .serial_mode (serial_mode), .si (chain[31]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_33), .so (chain[32])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_34 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_34), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_34), .serial_mode (serial_mode), .si (chain[32]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_34), .so (chain[33])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_35 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_35), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_35), .serial_mode (serial_mode), .si (chain[33]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_35), .so (chain[34])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_36 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_36), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_36), .serial_mode (serial_mode), .si (chain[34]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_36), .so (chain[35])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_37 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_37), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_37), .serial_mode (serial_mode), .si (chain[35]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_37), .so (chain[36])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_38 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_38), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_38), .serial_mode (serial_mode), .si (chain[36]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_38), .so (chain[37])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_39 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_39), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_39), .serial_mode (serial_mode), .si (chain[37]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_39), .so (chain[38])); stratixiv_hssi_cmu_dprio_16bit_pma centrl_ctrl_40 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_40), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_40), .serial_mode (serial_mode), .si (chain[38]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .pma_cram_test(pma_cram_test), .sig_out (out_centrl_ctrl_40), .so (chain[39])); stratixiv_hssi_cmu_dprio_16bit centrl_ctrl_41 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_41), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_41), .serial_mode (serial_mode), .si (chain[39]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_centrl_ctrl_41), .so (chain[40])); stratixiv_hssi_cmu_dprio_16bit centrl_ctrl_42 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_42), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_42), .serial_mode (serial_mode), .si (chain[40]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_centrl_ctrl_42), .so (chain[41])); stratixiv_hssi_cmu_dprio_16bit centrl_ctrl_43 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_43), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_43), .serial_mode (serial_mode), .si (chain[41]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_centrl_ctrl_43), .so (chain[42])); stratixiv_hssi_cmu_dprio_16bit centrl_ctrl_44 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_44), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_44), .serial_mode (serial_mode), .si (chain[42]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_centrl_ctrl_44), .so (chain[43])); stratixiv_hssi_cmu_dprio_16bit centrl_ctrl_45 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_45), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_45), .serial_mode (serial_mode), .si (chain[43]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_centrl_ctrl_45), .so (chain[44])); stratixiv_hssi_cmu_dprio_16bit centrl_ctrl_46 (.reset (mdio_rst), .mdio_wr (mdio_wr), .reg_addr (reg_addr), .target_addr (targ_addr_ctrl_46), .clk (mdc), .sig_in (mbus_in), .ext_in (ext_centrl_ctrl_46), .serial_mode (serial_mode), .si (chain[44]), .shift (ser_shift_load), .mdio_dis (mdio_dis), .sig_out (out_centrl_ctrl_46), .so (so)); endmodule `timescale 1 ps / 1 ps module stratixiv_hssi_cmu_dprio_centrl_bus_out_mux (centrl_ctrl_in1, centrl_ctrl_in2, centrl_ctrl_in3, centrl_ctrl_in4, centrl_ctrl_in5, centrl_ctrl_in6, centrl_ctrl_in7, centrl_ctrl_in8, centrl_ctrl_in9, centrl_ctrl_in10, centrl_ctrl_in11, centrl_ctrl_in12, centrl_ctrl_in13, centrl_ctrl_in14, centrl_ctrl_in15, centrl_ctrl_in16, centrl_ctrl_in17, centrl_ctrl_in18, centrl_ctrl_in19, centrl_ctrl_in20, centrl_ctrl_in21, centrl_ctrl_in22, centrl_ctrl_in23, centrl_ctrl_in24, centrl_ctrl_in25, centrl_ctrl_in26, centrl_ctrl_in27, centrl_ctrl_in28, centrl_ctrl_in29, centrl_ctrl_in30, centrl_ctrl_in31, centrl_ctrl_in32, centrl_ctrl_in33, centrl_ctrl_in34, centrl_ctrl_in35, centrl_ctrl_in36, centrl_ctrl_in37, centrl_ctrl_in38, centrl_ctrl_in39, centrl_ctrl_in40, centrl_ctrl_in41, centrl_ctrl_in42, centrl_ctrl_in43, centrl_ctrl_in44, centrl_ctrl_in45, centrl_ctrl_in46, hw_address_ctrl_in1, hw_address_ctrl_in2, hw_address_ctrl_in3, hw_address_ctrl_in4, hw_address_ctrl_in5, hw_address_ctrl_in6, hw_address_ctrl_in7, hw_address_ctrl_in8, hw_address_ctrl_in9, hw_address_ctrl_in10, hw_address_ctrl_in11, hw_address_ctrl_in12, hw_address_ctrl_in13, hw_address_ctrl_in14, hw_address_ctrl_in15, hw_address_ctrl_in16, hw_address_ctrl_in17, hw_address_ctrl_in18, hw_address_ctrl_in19, hw_address_ctrl_in20, hw_address_ctrl_in21, hw_address_ctrl_in22, hw_address_ctrl_in23, hw_address_ctrl_in24, hw_address_ctrl_in25, hw_address_ctrl_in26, hw_address_ctrl_in27, hw_address_ctrl_in28, hw_address_ctrl_in29, hw_address_ctrl_in30, hw_address_ctrl_in31, hw_address_ctrl_in32, hw_address_ctrl_in33, hw_address_ctrl_in34, hw_address_ctrl_in35, hw_address_ctrl_in36, hw_address_ctrl_in37, hw_address_ctrl_in38, hw_address_ctrl_in39, hw_address_ctrl_in40, hw_address_ctrl_in41, hw_address_ctrl_in42, hw_address_ctrl_in43, hw_address_ctrl_in44, hw_address_ctrl_in45, hw_address_ctrl_in46, reg_addr, centrl_ctrl_out ); input [15:0] centrl_ctrl_in1; input [15:0] centrl_ctrl_in2; input [15:0] centrl_ctrl_in3; input [15:0] centrl_ctrl_in4; input [15:0] centrl_ctrl_in5; input [15:0] centrl_ctrl_in6; input [15:0] centrl_ctrl_in7; input [15:0] centrl_ctrl_in8; input [15:0] centrl_ctrl_in9; input [15:0] centrl_ctrl_in10; input [15:0] centrl_ctrl_in11; input [15:0] centrl_ctrl_in12; input [15:0] centrl_ctrl_in13; input [15:0] centrl_ctrl_in14; input [15:0] centrl_ctrl_in15; input [15:0] centrl_ctrl_in16; input [15:0] centrl_ctrl_in17; input [15:0] centrl_ctrl_in18; input [15:0] centrl_ctrl_in19; input [15:0] centrl_ctrl_in20; input [15:0] centrl_ctrl_in21; input [15:0] centrl_ctrl_in22; input [15:0] centrl_ctrl_in23; input [15:0] centrl_ctrl_in24; input [15:0] centrl_ctrl_in25; input [15:0] centrl_ctrl_in26; input [15:0] centrl_ctrl_in27; input [15:0] centrl_ctrl_in28; input [15:0] centrl_ctrl_in29; input [15:0] centrl_ctrl_in30; input [15:0] centrl_ctrl_in31; input [15:0] centrl_ctrl_in32; input [15:0] centrl_ctrl_in33; input [15:0] centrl_ctrl_in34; input [15:0] centrl_ctrl_in35; input [15:0] centrl_ctrl_in36; input [15:0] centrl_ctrl_in37; input [15:0] centrl_ctrl_in38; input [15:0] centrl_ctrl_in39; input [15:0] centrl_ctrl_in40; input [15:0] centrl_ctrl_in41; input [15:0] centrl_ctrl_in42; input [15:0] centrl_ctrl_in43; input [15:0] centrl_ctrl_in44; input [15:0] centrl_ctrl_in45; input [15:0] centrl_ctrl_in46; input [15:0] hw_address_ctrl_in1; input [15:0] hw_address_ctrl_in2; input [15:0] hw_address_ctrl_in3; input [15:0] hw_address_ctrl_in4; input [15:0] hw_address_ctrl_in5; input [15:0] hw_address_ctrl_in6; input [15:0] hw_address_ctrl_in7; input [15:0] hw_address_ctrl_in8; input [15:0] hw_address_ctrl_in9; input [15:0] hw_address_ctrl_in10; input [15:0] hw_address_ctrl_in11; input [15:0] hw_address_ctrl_in12; input [15:0] hw_address_ctrl_in13; input [15:0] hw_address_ctrl_in14; input [15:0] hw_address_ctrl_in15; input [15:0] hw_address_ctrl_in16; input [15:0] hw_address_ctrl_in17; input [15:0] hw_address_ctrl_in18; input [15:0] hw_address_ctrl_in19; input [15:0] hw_address_ctrl_in20; input [15:0] hw_address_ctrl_in21; input [15:0] hw_address_ctrl_in22; input [15:0] hw_address_ctrl_in23; input [15:0] hw_address_ctrl_in24; input [15:0] hw_address_ctrl_in25; input [15:0] hw_address_ctrl_in26; input [15:0] hw_address_ctrl_in27; input [15:0] hw_address_ctrl_in28; input [15:0] hw_address_ctrl_in29; input [15:0] hw_address_ctrl_in30; input [15:0] hw_address_ctrl_in31; input [15:0] hw_address_ctrl_in32; input [15:0] hw_address_ctrl_in33; input [15:0] hw_address_ctrl_in34; input [15:0] hw_address_ctrl_in35; input [15:0] hw_address_ctrl_in36; input [15:0] hw_address_ctrl_in37; input [15:0] hw_address_ctrl_in38; input [15:0] hw_address_ctrl_in39; input [15:0] hw_address_ctrl_in40; input [15:0] hw_address_ctrl_in41; input [15:0] hw_address_ctrl_in42; input [15:0] hw_address_ctrl_in43; input [15:0] hw_address_ctrl_in44; input [15:0] hw_address_ctrl_in45; input [15:0] hw_address_ctrl_in46; input [15:0] reg_addr; output [15:0] centrl_ctrl_out; assign centrl_ctrl_out =(reg_addr == hw_address_ctrl_in1 ) ? centrl_ctrl_in1 : (reg_addr == hw_address_ctrl_in2 ) ? centrl_ctrl_in2 : (reg_addr == hw_address_ctrl_in3 ) ? centrl_ctrl_in3 : (reg_addr == hw_address_ctrl_in4 ) ? centrl_ctrl_in4 : (reg_addr == hw_address_ctrl_in5 ) ? centrl_ctrl_in5 : (reg_addr == hw_address_ctrl_in6 ) ? centrl_ctrl_in6 : (reg_addr == hw_address_ctrl_in7 ) ? centrl_ctrl_in7 : (reg_addr == hw_address_ctrl_in8 ) ? centrl_ctrl_in8 : (reg_addr == hw_address_ctrl_in9 ) ? centrl_ctrl_in9 : (reg_addr == hw_address_ctrl_in10) ? centrl_ctrl_in10 : (reg_addr == hw_address_ctrl_in11) ? centrl_ctrl_in11 : (reg_addr == hw_address_ctrl_in12) ? centrl_ctrl_in12 : (reg_addr == hw_address_ctrl_in13) ? centrl_ctrl_in13 : (reg_addr == hw_address_ctrl_in14) ? centrl_ctrl_in14 : (reg_addr == hw_address_ctrl_in15) ? centrl_ctrl_in15 : (reg_addr == hw_address_ctrl_in16) ? centrl_ctrl_in16 : (reg_addr == hw_address_ctrl_in17) ? centrl_ctrl_in17 : (reg_addr == hw_address_ctrl_in18) ? centrl_ctrl_in18 : (reg_addr == hw_address_ctrl_in19) ? centrl_ctrl_in19 : (reg_addr == hw_address_ctrl_in20) ? centrl_ctrl_in20 : (reg_addr == hw_address_ctrl_in21) ? centrl_ctrl_in21 : (reg_addr == hw_address_ctrl_in22) ? centrl_ctrl_in22 : (reg_addr == hw_address_ctrl_in23) ? centrl_ctrl_in23 : (reg_addr == hw_address_ctrl_in24) ? centrl_ctrl_in24 : (reg_addr == hw_address_ctrl_in25) ? centrl_ctrl_in25 : (reg_addr == hw_address_ctrl_in26) ? centrl_ctrl_in26 : (reg_addr == hw_address_ctrl_in27) ? centrl_ctrl_in27 : (reg_addr == hw_address_ctrl_in28) ? centrl_ctrl_in28 : (reg_addr == hw_address_ctrl_in29) ? centrl_ctrl_in29 : (reg_addr == hw_address_ctrl_in30) ? centrl_ctrl_in30 : (reg_addr == hw_address_ctrl_in31) ? centrl_ctrl_in31 : (reg_addr == hw_address_ctrl_in32) ? centrl_ctrl_in32 : (reg_addr == hw_address_ctrl_in33) ? centrl_ctrl_in33 : (reg_addr == hw_address_ctrl_in34) ? centrl_ctrl_in34 : (reg_addr == hw_address_ctrl_in35) ? centrl_ctrl_in35 : (reg_addr == hw_address_ctrl_in36) ? centrl_ctrl_in36 : (reg_addr == hw_address_ctrl_in37) ? centrl_ctrl_in37 : (reg_addr == hw_address_ctrl_in38) ? centrl_ctrl_in38 : (reg_addr == hw_address_ctrl_in39) ? centrl_ctrl_in39 : (reg_addr == hw_address_ctrl_in40) ? centrl_ctrl_in40 : (reg_addr == hw_address_ctrl_in41) ? centrl_ctrl_in41 : (reg_addr == hw_address_ctrl_in42) ? centrl_ctrl_in42 : (reg_addr == hw_address_ctrl_in43) ? centrl_ctrl_in43 : (reg_addr == hw_address_ctrl_in44) ? centrl_ctrl_in44 : (reg_addr == hw_address_ctrl_in45) ? centrl_ctrl_in45 : (reg_addr == hw_address_ctrl_in46) ? centrl_ctrl_in46 : 16'h0000; endmodule `timescale 1 ps / 1 ps module stratixiv_hssi_cmu_dprio_centrl_top ( mdio_rst, mdio_wr, reg_addr, mdc, mbus_in, serial_mode, mdio_dis, pma_cram_test, ser_shift_load, si, csr_centrl_in, csr_centrl_in_reserved, //ww25.2008 dp_centrl_out, dp_centrl_out_reserved, //ww25.2008 so, mbus_out ); input mdio_rst; // DPRIO reset input input mdio_wr; // DPRIO register write enable input [15:0] reg_addr; // DPRIO register address from SM input mdc; // DPRIO clock input [15:0] mbus_in; // DPRIO data in from SM input serial_mode; // DPRIO serial mode enable input mdio_dis; // DPRIO disable signal (using CSR input) input pma_cram_test; // PLD dynamic signal for PMA DPRIO cell for coverage for PE/TE input ser_shift_load; // DPRIO serial shift or load control signal input si; // DPRIO serial input input [703:0] csr_centrl_in; // CSR inputs input [31:0] csr_centrl_in_reserved; output [703:0] dp_centrl_out; // CSR inputs output [31:0] dp_centrl_out_reserved; output so; // DPRIO serial out output [15:0] mbus_out; // DPRIO dataout ////////////////////////////////////////////////////////////////////////// // begin of CRAM output ------------------------------------------------- ////////////////////////////////////////////////////////////////////////// // CRAM output // Central PCS CRAMs wire rs_lpbk_all; // Global serial loopback enable CRAM wire rpowerdown; // Output CRAM of RPOWERDOWN wire [3:0] rtest_bus_centrl_sel; // Central Test bus selection CRAMs wire rx16_x12_sel_tx; // Enable/Disable x16/x12 wire rx16_x12_sel_rx; // Enable/Disable x16/x12 wire rphfifo_master_sel_tx; // TX Phase comp. FIFO pointers selection CRAM wire rphfifo_master_sel_rx; // TX Phase comp. FIFO pointers selection CRAM wire rendec_data_sel_tx; // TX 8B10B encoder data in selection CRAM wire rendec_data_sel_rx; // RX 8B10B decoder data out selection CRAM wire rnenbpin; // Output CRAM of RNENBPIN wire rpllurst; // Output CRAM of RPLLURST wire rreset; // Output CRAM of RRESET wire rdeskewen; // Deskew function enable CRAM wire rindv_tx; // TX SM bypassing CRAM wire rindv_rx; // RX SM bypassing CRAM wire rfreerun_centrl; // REFCLK_OUT free running enable CRAM wire rcentrl_clk_sel; // REFCLK_PMA global clock selection CRAM wire rrefclk_out_div2; // REFCLK_OUT divide by 2 enable CRAM wire rxaui_s2gx_en_rx; // Enable S2GX XAUI RX SM behavior wire ralgnopt; // De-skew SM Hysteresis Option wire rdskposdisp; // Match the programmed de-skew pattern only wire [9:0] rdskchrp; // Programmable Deskew Char. Pos. Disp. wire rxaui_s2gx_en_tx; // Enable S2GX XAUI TX SM behavior wire [10:0] rpcs_centrl_rsvd_cram; // Central PCS reserved CRAMs wire rmaster_rx; // Please see S4GX DPRIO spreadsheet for description wire rmaster_up_rx; wire rmaster_tx; wire rmaster_up_tx; // CMU0 PMA CRAMs // Clock Output Buffer - refer to PMA TX section for description wire [2:0] rcmu0_vod_sel; wire rcmu0_powdnt; wire [4:0] rcmu0_pre_em_1t; wire [3:0] rcmu0_pre_em_2t; wire [3:0] rcmu0_pre_em_pt; wire [2:0] rcmu0_tx_term_sel; wire [1:0] rcmu0_tx_vtt; wire [3:0] rcmu0_tx_lst; wire [1:0] rcmu0_rslew; wire rcmu0_sig_inv_ptap; wire rcmu0_sig_inv_2t; wire [1:0] rcmu0_rx_det; wire rcmu0_lowv; wire [2:0] rcmu0_tx_dft_sel; wire rcmu0_tx_ob_pdb; // Central Clock Generation (refer to CGB section for description) // Serializer (Refer to serializer section for description) wire [1:0] rcmu0_cgb_x_en; wire rcmu0_cgb_cmu_sel; wire [1:0] rcmu0_cgb_m_sel; wire rcmu0_pma_doublewidth_tx; wire rcmu0_pmadwidth_tx; wire rcmu0_delay_sel; wire rcmu0_dynamic_sw; wire rcmu0_pclksel; wire rcmu0_tx_cgb_pdb; wire [1:0] rcmu0_iqsel; wire [1:0] rcmu0_refsel; wire rcmu0_vcobypass; wire rcmu0_revlb_sw; wire rcmu0_pcs_sd_sel; wire [31:0] rcmu0_reserved; //divided into 2 sixteen bit busses // CMU0 RX CRAMs // CDR/TXPLL - refer to CDR section for description wire [4:0] rcmu0_rx_lst; wire [3:0] rcmu0_rx_bit_dc; wire rcmu0_s_rdlpbk; wire [2:0] rcmu0_rx_vtt; wire [2:0] rcmu0_term; wire [3:0] rcmu0_rx_sdlv; wire rcmu0_rx_oc_en; wire [7:0] rcmu0_rx_oc; wire rcmu0_sd_force; wire rcmu0_rx_test; wire rcmu0_rxurst; wire [3:0] rcmu0_rx_sd_on; wire [4:0] rcmu0_rx_sd_off; wire rcmu0_rx_oc_calpd; wire rcmu0_urx_pdb; wire rcmu0_rx_ib_pdb; wire rcmu0_powdnr; wire rcmu0_div2; wire [1:0] rcmu0_m_sel; wire [3:0] rcmu0_m; wire [1:0] rcmu0_l; wire rcmu0_ctl0; wire [1:0] rcmu0_crplctrl; wire [1:0] rcmu0_pfdbwctrl; wire [1:0] rcmu0_pdbwctrl; wire rcmu0_rlbk; wire [3:0] rcmu0_lst; wire rcmu0_testen; wire rcmu0_testupen; wire rcmu0_testdnen; wire [2:0] rcmu0_isel; wire [2:0] rcmu0_iselpd; wire rcmu0_rcp_mode; wire rcmu0_cru_pdb; wire rcmu0_rx_cmu_rst; wire rcmu0_cmu_mode; wire rcmu0_ignore_phslck; wire rcmu0_sd_sel; wire rcmu0_pdfl; wire [2:0] rcmu0_pdof_test; wire [2:0] rcmu0_rgla_isel; wire [3:0] rcmu0_pdof_0i; wire [3:0] rcmu0_pdof_90i; wire [3:0] rcmu0_pdof_180i; wire [3:0] rcmu0_pdof_270i; wire [7:0] rcmu0_eye_monitor; //wire [15:0] rcmu0_reserved[15:0]; declared above // DeSerializer - refer to deserializer section for description wire rcmu0_pma_doublewidth_rx; wire rcmu0_pmadwidth_rx; wire rcmu0_test_fastsd; wire [3:0] rcmu0_fastsd; wire [5:0] rcmu0_ppmsel; wire rcmu0_force0_freqdet; wire rcmu0_force1_freqdet; //DFE wire [2:0] rcmu0_dfe_1t; wire [2:0] rcmu0_dfe_2t; // RX/D2A - Refer to RX and ADCE for description wire [1:0] rcmu0_eqa_set; wire [1:0] rcmu0_eqb_set; wire [1:0] rcmu0_eqc_set; wire [1:0] rcmu0_eqd_set; wire [1:0] rcmu0_eqv_set; wire [5:0] rcmu0_d2a_res; wire [1:0] rcmu0_clk_div2; wire rcmu0_ht_sel; wire rcmu0_fbclk_sel; wire rcmu0_clk_pdb; wire rcmu0_rx_det_pdb; wire rcmu0_iqclk_sel; wire rcmu0_detect_on; // END CMU0 CRAMs // CMU1 PMA CRAMs // Clock Output Buffer - refer to PMA TX section for description wire [2:0] rcmu1_vod_sel; wire rcmu1_powdnt; wire [4:0] rcmu1_pre_em_1t; wire [3:0] rcmu1_pre_em_2t; wire [3:0] rcmu1_pre_em_pt; wire [2:0] rcmu1_tx_term_sel; wire [1:0] rcmu1_tx_vtt; wire [3:0] rcmu1_tx_lst; wire [1:0] rcmu1_rslew; wire rcmu1_sig_inv_ptap; wire rcmu1_sig_inv_2t; wire [1:0] rcmu1_rx_det; wire rcmu1_lowv; wire [2:0] rcmu1_tx_dft_sel; wire rcmu1_tx_ob_pdb; // Central Clock Generation (refer to CGB section for description) // Serializer (Refer to serializer section for description) wire [1:0] rcmu1_cgb_x_en; wire rcmu1_cgb_cmu_sel; wire [1:0] rcmu1_cgb_m_sel; wire rcmu1_pma_doublewidth_tx; wire rcmu1_pmadwidth_tx; wire rcmu1_delay_sel; wire rcmu1_dynamic_sw; wire rcmu1_pclksel; wire rcmu1_tx_cgb_pdb; wire [1:0] rcmu1_iqsel; wire [1:0] rcmu1_refsel; wire rcmu1_vcobypass; wire rcmu1_revlb_sw; wire rcmu1_pcs_sd_sel; wire [31:0] rcmu1_reserved; //divided into 2 sixteen bit busses // cmu1 RX CRAMs // CDR/TXPLL - refer to CDR section for description wire [4:0] rcmu1_rx_lst; wire [3:0] rcmu1_rx_bit_dc; wire rcmu1_s_rdlpbk; wire [2:0] rcmu1_rx_vtt; wire [2:0] rcmu1_term; wire [3:0] rcmu1_rx_sdlv; wire rcmu1_rx_oc_en; wire [7:0] rcmu1_rx_oc; wire rcmu1_sd_force; wire rcmu1_rx_test; wire rcmu1_rxurst; wire [3:0] rcmu1_rx_sd_on; wire [4:0] rcmu1_rx_sd_off; wire rcmu1_rx_oc_calpd; wire rcmu1_urx_pdb; wire rcmu1_rx_ib_pdb; wire rcmu1_powdnr; wire rcmu1_div2; wire [1:0] rcmu1_m_sel; wire [3:0] rcmu1_m; wire [1:0] rcmu1_l; wire rcmu1_ctl0; wire [1:0] rcmu1_crplctrl; wire [1:0] rcmu1_pfdbwctrl; wire [1:0] rcmu1_pdbwctrl; wire rcmu1_rlbk; wire [3:0] rcmu1_lst; wire rcmu1_testen; wire rcmu1_testupen; wire rcmu1_testdnen; wire [2:0] rcmu1_isel; wire [2:0] rcmu1_iselpd; wire rcmu1_rcp_mode; wire rcmu1_cru_pdb; wire rcmu1_rx_cmu_rst; wire rcmu1_cmu_mode; wire rcmu1_ignore_phslck; wire rcmu1_sd_sel; wire rcmu1_pdfl; wire [2:0] rcmu1_pdof_test; wire [2:0] rcmu1_rgla_isel; wire [3:0] rcmu1_pdof_0i; wire [3:0] rcmu1_pdof_90i; wire [3:0] rcmu1_pdof_180i; wire [3:0] rcmu1_pdof_270i; wire [7:0] rcmu1_eye_monitor; //wire [15:0] rcmu1_reserved[15:0]; //declared above // DeSerializer - refer to deserializer section for description wire rcmu1_pma_doublewidth_rx; wire rcmu1_pmadwidth_rx; wire rcmu1_test_fastsd; wire [3:0] rcmu1_fastsd; wire [5:0] rcmu1_ppmsel; wire rcmu1_force0_freqdet; wire rcmu1_force1_freqdet; //DFE wire [2:0] rcmu1_dfe_1t; wire [2:0] rcmu1_dfe_2t; // RX/D2A - Refer to RX and ADCE for description wire [1:0] rcmu1_eqa_set; wire [1:0] rcmu1_eqb_set; wire [1:0] rcmu1_eqc_set; wire [1:0] rcmu1_eqd_set; wire [1:0] rcmu1_eqv_set; wire [5:0] rcmu1_d2a_res; wire [1:0] rcmu1_clk_div2; wire rcmu1_ht_sel; wire rcmu1_fbclk_sel; wire rcmu1_clk_pdb; wire rcmu1_rx_det_pdb; wire rcmu1_iqclk_sel; wire rcmu1_detect_on; // END CMU1 CRAMs ////////////////////////////////////////////////////////////////////////// // end of CRAM output --------------------------------------------------- ////////////////////////////////////////////////////////////////////////// wire [15:0] targ_addr_ctrl_1; wire [15:0] targ_addr_ctrl_2; wire [15:0] targ_addr_ctrl_3; wire [15:0] targ_addr_ctrl_4; wire [15:0] targ_addr_ctrl_5; wire [15:0] targ_addr_ctrl_6; wire [15:0] targ_addr_ctrl_7; wire [15:0] targ_addr_ctrl_8; wire [15:0] targ_addr_ctrl_9; wire [15:0] targ_addr_ctrl_10; wire [15:0] targ_addr_ctrl_11; wire [15:0] targ_addr_ctrl_12; wire [15:0] targ_addr_ctrl_13; wire [15:0] targ_addr_ctrl_14; wire [15:0] targ_addr_ctrl_15; wire [15:0] targ_addr_ctrl_16; wire [15:0] targ_addr_ctrl_17; wire [15:0] targ_addr_ctrl_18; wire [15:0] targ_addr_ctrl_19; wire [15:0] targ_addr_ctrl_20; wire [15:0] targ_addr_ctrl_21; wire [15:0] targ_addr_ctrl_22; wire [15:0] targ_addr_ctrl_23; wire [15:0] targ_addr_ctrl_24; wire [15:0] targ_addr_ctrl_25; wire [15:0] targ_addr_ctrl_26; wire [15:0] targ_addr_ctrl_27; wire [15:0] targ_addr_ctrl_28; wire [15:0] targ_addr_ctrl_29; wire [15:0] targ_addr_ctrl_30; wire [15:0] targ_addr_ctrl_31; wire [15:0] targ_addr_ctrl_32; wire [15:0] targ_addr_ctrl_33; wire [15:0] targ_addr_ctrl_34; wire [15:0] targ_addr_ctrl_35; wire [15:0] targ_addr_ctrl_36; wire [15:0] targ_addr_ctrl_37; wire [15:0] targ_addr_ctrl_38; wire [15:0] targ_addr_ctrl_39; wire [15:0] targ_addr_ctrl_40; wire [15:0] targ_addr_ctrl_41; wire [15:0] targ_addr_ctrl_42; wire [15:0] targ_addr_ctrl_43; wire [15:0] targ_addr_ctrl_44; wire [15:0] targ_addr_ctrl_45; wire [15:0] targ_addr_ctrl_46; wire [15:0] out_centrl_ctrl_1; wire [15:0] out_centrl_ctrl_2; wire [15:0] out_centrl_ctrl_3; wire [15:0] out_centrl_ctrl_4; wire [15:0] out_centrl_ctrl_5; wire [15:0] out_centrl_ctrl_6; wire [15:0] out_centrl_ctrl_7; wire [15:0] out_centrl_ctrl_8; wire [15:0] out_centrl_ctrl_9; wire [15:0] out_centrl_ctrl_10; wire [15:0] out_centrl_ctrl_11; wire [15:0] out_centrl_ctrl_12; wire [15:0] out_centrl_ctrl_13; wire [15:0] out_centrl_ctrl_14; wire [15:0] out_centrl_ctrl_15; wire [15:0] out_centrl_ctrl_16; wire [15:0] out_centrl_ctrl_17; wire [15:0] out_centrl_ctrl_18; wire [15:0] out_centrl_ctrl_19; wire [15:0] out_centrl_ctrl_20; wire [15:0] out_centrl_ctrl_21; wire [15:0] out_centrl_ctrl_22; wire [15:0] out_centrl_ctrl_23; wire [15:0] out_centrl_ctrl_24; wire [15:0] out_centrl_ctrl_25; wire [15:0] out_centrl_ctrl_26; wire [15:0] out_centrl_ctrl_27; wire [15:0] out_centrl_ctrl_28; wire [15:0] out_centrl_ctrl_29; wire [15:0] out_centrl_ctrl_30; wire [15:0] out_centrl_ctrl_31; wire [15:0] out_centrl_ctrl_32; wire [15:0] out_centrl_ctrl_33; wire [15:0] out_centrl_ctrl_34; wire [15:0] out_centrl_ctrl_35; wire [15:0] out_centrl_ctrl_36; wire [15:0] out_centrl_ctrl_37; wire [15:0] out_centrl_ctrl_38; wire [15:0] out_centrl_ctrl_39; wire [15:0] out_centrl_ctrl_40; wire [15:0] out_centrl_ctrl_41; wire [15:0] out_centrl_ctrl_42; wire [15:0] out_centrl_ctrl_43; wire [15:0] out_centrl_ctrl_44; wire [15:0] out_centrl_ctrl_45; wire [15:0] out_centrl_ctrl_46; ////////////////////////////////////////////////////////////////////////// // begin of CRAM output ------------------------------------------------- ////////////////////////////////////////////////////////////////////////// assign dp_centrl_out[15:0] = out_centrl_ctrl_1; assign dp_centrl_out[31:16] = out_centrl_ctrl_2; assign dp_centrl_out[47:32] = out_centrl_ctrl_3; assign dp_centrl_out[63:48] = out_centrl_ctrl_4; assign dp_centrl_out[79:64] = out_centrl_ctrl_5; assign dp_centrl_out[95:80] = out_centrl_ctrl_6; assign dp_centrl_out[111:96] = out_centrl_ctrl_7; assign dp_centrl_out[127:112] = out_centrl_ctrl_8; assign dp_centrl_out[143:128] = out_centrl_ctrl_9; assign dp_centrl_out[159:144] = out_centrl_ctrl_10; assign dp_centrl_out[175:160] = out_centrl_ctrl_11; assign dp_centrl_out[191:176] = out_centrl_ctrl_12; assign dp_centrl_out[207:192] = out_centrl_ctrl_13; assign dp_centrl_out[223:208] = out_centrl_ctrl_14; assign dp_centrl_out[239:224] = out_centrl_ctrl_15; assign dp_centrl_out_reserved[15:0] = out_centrl_ctrl_16; assign dp_centrl_out[255:240] = out_centrl_ctrl_17; assign dp_centrl_out[271:256] = out_centrl_ctrl_18; assign dp_centrl_out[287:272] = out_centrl_ctrl_19; assign dp_centrl_out[303:288] = out_centrl_ctrl_20; assign dp_centrl_out[319:304] = out_centrl_ctrl_21; assign dp_centrl_out[335:320] = out_centrl_ctrl_22; assign dp_centrl_out[351:336] = out_centrl_ctrl_23; assign dp_centrl_out[367:352] = out_centrl_ctrl_24; assign dp_centrl_out[383:368] = out_centrl_ctrl_25; assign dp_centrl_out[399:384] = out_centrl_ctrl_26; assign dp_centrl_out[415:400] = out_centrl_ctrl_27; assign dp_centrl_out[431:416] = out_centrl_ctrl_28; assign dp_centrl_out[447:432] = out_centrl_ctrl_29; assign dp_centrl_out[463:448] = out_centrl_ctrl_30; assign dp_centrl_out[479:464] = out_centrl_ctrl_31; assign dp_centrl_out[495:480] = out_centrl_ctrl_32; assign dp_centrl_out[511:496] = out_centrl_ctrl_33; assign dp_centrl_out[527:512] = out_centrl_ctrl_34; assign dp_centrl_out[543:528] = out_centrl_ctrl_35; assign dp_centrl_out[559:544] = out_centrl_ctrl_36; assign dp_centrl_out_reserved[31:16] = out_centrl_ctrl_37; assign dp_centrl_out[575:560] = out_centrl_ctrl_38; assign dp_centrl_out[591:576] = out_centrl_ctrl_39; assign dp_centrl_out[607:592] = out_centrl_ctrl_40; assign dp_centrl_out[623:608] = out_centrl_ctrl_41; assign dp_centrl_out[639:624] = out_centrl_ctrl_42; assign dp_centrl_out[655:640] = out_centrl_ctrl_43; assign dp_centrl_out[671:656] = out_centrl_ctrl_44; assign dp_centrl_out[687:672] = out_centrl_ctrl_45; assign dp_centrl_out[703:688] = out_centrl_ctrl_46; ////////////////////////////////////////////////////////////////////////// // end of CRAM output --------------------------------------------------- ////////////////////////////////////////////////////////////////////////// // Control register address assignment // CMU0 PMA address space assign targ_addr_ctrl_1 = 16'h4800 + 16'h0000; assign targ_addr_ctrl_2 = 16'h4800 + 16'h0001; assign targ_addr_ctrl_3 = 16'h4800 + 16'h0002; assign targ_addr_ctrl_4 = 16'h4800 + 16'h0003; assign targ_addr_ctrl_5 = 16'h4800 + 16'h0004; assign targ_addr_ctrl_6 = 16'h4800 + 16'h0005; assign targ_addr_ctrl_7 = 16'h4800 + 16'h0006; assign targ_addr_ctrl_8 = 16'h4800 + 16'h0007; assign targ_addr_ctrl_9 = 16'h4C00 + 16'h0000; assign targ_addr_ctrl_10 = 16'h4C00 + 16'h0001; assign targ_addr_ctrl_11 = 16'h4C00 + 16'h0002; assign targ_addr_ctrl_12 = 16'h4C00 + 16'h0003; assign targ_addr_ctrl_13 = 16'h4C00 + 16'h0004; assign targ_addr_ctrl_14 = 16'h4C00 + 16'h0005; assign targ_addr_ctrl_15 = 16'h4C00 + 16'h0006; assign targ_addr_ctrl_16 = 16'h4C00 + 16'h0007; assign targ_addr_ctrl_17 = 16'h4C00 + 16'h0008; assign targ_addr_ctrl_18 = 16'h4C00 + 16'h0009; assign targ_addr_ctrl_19 = 16'h4C00 + 16'h000A; assign targ_addr_ctrl_20 = 16'h4C00 + 16'h000B; assign targ_addr_ctrl_21 = 16'h4C00 + 16'h000C; // CMU1 PMA address space assign targ_addr_ctrl_22 = 16'h5800 + 16'h0000; assign targ_addr_ctrl_23 = 16'h5800 + 16'h0001; assign targ_addr_ctrl_24 = 16'h5800 + 16'h0002; assign targ_addr_ctrl_25 = 16'h5800 + 16'h0003; assign targ_addr_ctrl_26 = 16'h5800 + 16'h0004; assign targ_addr_ctrl_27 = 16'h5800 + 16'h0005; assign targ_addr_ctrl_28 = 16'h5800 + 16'h0006; assign targ_addr_ctrl_29 = 16'h5800 + 16'h0007; assign targ_addr_ctrl_30 = 16'h5C00 + 16'h0000; assign targ_addr_ctrl_31 = 16'h5C00 + 16'h0001; assign targ_addr_ctrl_32 = 16'h5C00 + 16'h0002; assign targ_addr_ctrl_33 = 16'h5C00 + 16'h0003; assign targ_addr_ctrl_34 = 16'h5C00 + 16'h0004; assign targ_addr_ctrl_35 = 16'h5C00 + 16'h0005; assign targ_addr_ctrl_36 = 16'h5C00 + 16'h0006; assign targ_addr_ctrl_37 = 16'h5C00 + 16'h0007; assign targ_addr_ctrl_38 = 16'h5C00 + 16'h0008; assign targ_addr_ctrl_39 = 16'h5C00 + 16'h0009; assign targ_addr_ctrl_40 = 16'h5C00 + 16'h000A; assign targ_addr_ctrl_41 = 16'h5C00 + 16'h000B; assign targ_addr_ctrl_42 = 16'h5C00 + 16'h000C; // Central PCS address space assign targ_addr_ctrl_43 = 16'h6000 + 16'h0000; assign targ_addr_ctrl_44 = 16'h6000 + 16'h0001; assign targ_addr_ctrl_45 = 16'h6000 + 16'h0002; assign targ_addr_ctrl_46 = 16'h6000 + 16'h0003; // CRAM output assignment // CMU0 PMA CRAMs // CMU0 control register 1 assign rcmu0_vod_sel[2:0] = out_centrl_ctrl_1[15:13]; assign rcmu0_powdnt = out_centrl_ctrl_1[0]; // CMU0 control register 2 assign rcmu0_pre_em_1t[4:0] = out_centrl_ctrl_2[15:11]; // CMU0 control register 3 assign rcmu0_pre_em_2t[3:0] = out_centrl_ctrl_3[7:4]; assign rcmu0_pre_em_pt[3:0] = out_centrl_ctrl_3[3:0]; // CMU0 control register 4 assign rcmu0_tx_term_sel[2:0] = out_centrl_ctrl_4[15:13]; assign rcmu0_tx_vtt[1:0] = out_centrl_ctrl_4[12:11]; assign rcmu0_tx_lst[3:0] = out_centrl_ctrl_4[10:7]; assign rcmu0_rslew[1:0] = out_centrl_ctrl_4[6:5]; assign rcmu0_sig_inv_ptap = out_centrl_ctrl_4[4]; assign rcmu0_sig_inv_2t = out_centrl_ctrl_4[3]; assign rcmu0_rx_det[1:0] = out_centrl_ctrl_4[2:1]; assign rcmu0_lowv = out_centrl_ctrl_4[0]; // CMU0 control register 5 assign rcmu0_tx_dft_sel[2:0] = out_centrl_ctrl_5[15:13]; assign rcmu0_tx_ob_pdb = out_centrl_ctrl_5[11]; // CMU0 control register 6 assign rcmu0_cgb_x_en[1:0] = out_centrl_ctrl_6[15:14]; assign rcmu0_cgb_cmu_sel = out_centrl_ctrl_6[13]; assign rcmu0_cgb_m_sel[1:0] = out_centrl_ctrl_6[12:11]; assign rcmu0_pma_doublewidth_tx = out_centrl_ctrl_6[10]; assign rcmu0_pmadwidth_tx = out_centrl_ctrl_6[9]; assign rcmu0_delay_sel = out_centrl_ctrl_6[8]; assign rcmu0_dynamic_sw = out_centrl_ctrl_6[6]; assign rcmu0_pclksel = out_centrl_ctrl_6[5]; assign rcmu0_tx_cgb_pdb = out_centrl_ctrl_6[4]; // CMU0 control register 7 assign rcmu0_iqsel[1:0] = out_centrl_ctrl_7[15:14]; assign rcmu0_refsel[1:0] = out_centrl_ctrl_7[13:12]; assign rcmu0_vcobypass = out_centrl_ctrl_7[11]; assign rcmu0_revlb_sw = out_centrl_ctrl_7[10]; assign rcmu0_pcs_sd_sel = out_centrl_ctrl_7[3]; // CMU0 control register 8 assign rcmu0_reserved[31:16] = out_centrl_ctrl_8[15:0]; // CMU0 RX CRAMs // CMU0 control register 9 assign rcmu0_rx_lst[4:0] = out_centrl_ctrl_9[15:11]; assign rcmu0_rx_bit_dc[3:0] = out_centrl_ctrl_9[10:7]; assign rcmu0_s_rdlpbk = out_centrl_ctrl_9[6]; assign rcmu0_rx_vtt[2:0] = out_centrl_ctrl_9[5:3]; assign rcmu0_term[2:0] = out_centrl_ctrl_9[2:0]; // CMU0 control register 10 assign rcmu0_rx_sdlv[3:0] = out_centrl_ctrl_10[15:12]; assign rcmu0_rx_oc_en = out_centrl_ctrl_10[11]; assign rcmu0_rx_oc[7:0] = out_centrl_ctrl_10[10:3]; assign rcmu0_sd_force = out_centrl_ctrl_10[2]; assign rcmu0_rx_test = out_centrl_ctrl_10[1]; assign rcmu0_rxurst = out_centrl_ctrl_10[0]; // CMU0 control register 11 assign rcmu0_rx_sd_on[3:0] = out_centrl_ctrl_11[15:12]; assign rcmu0_rx_sd_off[4:0] = out_centrl_ctrl_11[11:7]; assign rcmu0_rx_oc_calpd = out_centrl_ctrl_11[6]; assign rcmu0_urx_pdb = out_centrl_ctrl_11[5]; assign rcmu0_rx_ib_pdb = out_centrl_ctrl_11[4]; assign rcmu0_powdnr = out_centrl_ctrl_11[3]; // CMU0 control register 12 assign rcmu0_div2 = out_centrl_ctrl_12[15]; assign rcmu0_m_sel[1:0] = out_centrl_ctrl_12[14:13]; assign rcmu0_m[3:0] = out_centrl_ctrl_12[12:9]; assign rcmu0_l[1:0] = out_centrl_ctrl_12[8:7]; assign rcmu0_ctl0 = out_centrl_ctrl_12[6]; assign rcmu0_crplctrl[1:0] = out_centrl_ctrl_12[5:4]; assign rcmu0_pfdbwctrl[1:0] = out_centrl_ctrl_12[3:2]; assign rcmu0_pdbwctrl[1:0] = out_centrl_ctrl_12[1:0]; // CMU0 control register 13 assign rcmu0_rlbk = out_centrl_ctrl_13[15]; assign rcmu0_lst[3:0] = out_centrl_ctrl_13[14:11]; assign rcmu0_testen = out_centrl_ctrl_13[10]; assign rcmu0_testupen = out_centrl_ctrl_13[9]; assign rcmu0_testdnen = out_centrl_ctrl_13[8]; assign rcmu0_isel[2:0] = out_centrl_ctrl_13[7:5]; assign rcmu0_iselpd[2:0] = out_centrl_ctrl_13[4:2]; // CMU0 control register 14 assign rcmu0_rcp_mode = out_centrl_ctrl_14[15]; assign rcmu0_cru_pdb = out_centrl_ctrl_14[12]; assign rcmu0_rx_cmu_rst = out_centrl_ctrl_14[11]; assign rcmu0_cmu_mode = out_centrl_ctrl_14[10]; assign rcmu0_ignore_phslck = out_centrl_ctrl_14[9]; assign rcmu0_sd_sel = out_centrl_ctrl_14[7]; assign rcmu0_pdfl = out_centrl_ctrl_14[6]; assign rcmu0_pdof_test[2:0] = out_centrl_ctrl_14[5:3]; assign rcmu0_rgla_isel[2:0] = out_centrl_ctrl_14[2:0]; // CMU0 control register 15 assign rcmu0_pdof_0i[3:0] = out_centrl_ctrl_15[15:12]; assign rcmu0_pdof_90i[3:0] = out_centrl_ctrl_15[11:8]; assign rcmu0_pdof_180i[3:0] = out_centrl_ctrl_15[7:4]; assign rcmu0_pdof_270i[3:0] = out_centrl_ctrl_15[3:0]; // CMU0 control register 16 assign rcmu0_eye_monitor[7:0] = out_centrl_ctrl_16[7:0]; // CMU0 control register 17 assign rcmu0_reserved[15:0] = out_centrl_ctrl_17[15:0]; // CMU0 control register 18 assign rcmu0_pma_doublewidth_rx = out_centrl_ctrl_18[15]; assign rcmu0_pmadwidth_rx = out_centrl_ctrl_18[14]; assign rcmu0_test_fastsd = out_centrl_ctrl_18[13]; assign rcmu0_fastsd[3:0] = out_centrl_ctrl_18[12:9]; assign rcmu0_ppmsel[5:0] = out_centrl_ctrl_18[8:3]; assign rcmu0_force0_freqdet = out_centrl_ctrl_18[2]; assign rcmu0_force1_freqdet = out_centrl_ctrl_18[1]; // CMU0 control register 19 assign rcmu0_dfe_1t[2:0] = out_centrl_ctrl_19[15:13]; assign rcmu0_dfe_2t[2:0] = out_centrl_ctrl_19[12:10]; // CMU0 control register 20 assign rcmu0_eqa_set[1:0] = out_centrl_ctrl_20[13:12]; assign rcmu0_eqb_set[1:0] = out_centrl_ctrl_20[10:9]; assign rcmu0_eqc_set[1:0] = out_centrl_ctrl_20[7:6]; assign rcmu0_eqd_set[1:0] = out_centrl_ctrl_20[4:3]; assign rcmu0_eqv_set[1:0] = out_centrl_ctrl_20[1:0]; // CMU0 control register 21 assign rcmu0_d2a_res[5:0] = out_centrl_ctrl_21[15:10]; assign rcmu0_clk_div2[1:0] = out_centrl_ctrl_21[9:8]; assign rcmu0_ht_sel = out_centrl_ctrl_21[7]; assign rcmu0_fbclk_sel = out_centrl_ctrl_21[6]; assign rcmu0_clk_pdb = out_centrl_ctrl_21[5]; assign rcmu0_rx_det_pdb = out_centrl_ctrl_21[4]; assign rcmu0_iqclk_sel = out_centrl_ctrl_21[2]; assign rcmu0_detect_on = out_centrl_ctrl_21[1]; // END CMU0 CRAMs // CMU1 PMA CRAMs // CMU1 control register 1 assign rcmu1_vod_sel[2:0] = out_centrl_ctrl_22[15:13]; assign rcmu1_powdnt = out_centrl_ctrl_22[0]; // CMU1 control register 2 assign rcmu1_pre_em_1t[4:0] = out_centrl_ctrl_23[15:11]; // CMU1 control register 3 assign rcmu1_pre_em_2t[3:0] = out_centrl_ctrl_24[7:4]; assign rcmu1_pre_em_pt[3:0] = out_centrl_ctrl_24[3:0]; // CMU1 control register 4 assign rcmu1_tx_term_sel[2:0] = out_centrl_ctrl_25[15:13]; assign rcmu1_tx_vtt[1:0] = out_centrl_ctrl_25[12:11]; assign rcmu1_tx_lst[3:0] = out_centrl_ctrl_25[10:7]; assign rcmu1_rslew[1:0] = out_centrl_ctrl_25[6:5]; assign rcmu1_sig_inv_ptap = out_centrl_ctrl_25[4]; assign rcmu1_sig_inv_2t = out_centrl_ctrl_25[3]; assign rcmu1_rx_det[1:0] = out_centrl_ctrl_25[2:1]; assign rcmu1_lowv = out_centrl_ctrl_25[0]; // CMU1 control register 5 assign rcmu1_tx_dft_sel[2:0] = out_centrl_ctrl_26[15:13]; assign rcmu1_tx_ob_pdb = out_centrl_ctrl_26[11]; // CMU1 control register 6 assign rcmu1_cgb_x_en[1:0] = out_centrl_ctrl_27[15:14]; assign rcmu1_cgb_cmu_sel = out_centrl_ctrl_27[13]; assign rcmu1_cgb_m_sel[1:0] = out_centrl_ctrl_27[12:11]; assign rcmu1_pma_doublewidth_tx = out_centrl_ctrl_27[10]; assign rcmu1_pmadwidth_tx = out_centrl_ctrl_27[9]; assign rcmu1_delay_sel = out_centrl_ctrl_27[8]; assign rcmu1_dynamic_sw = out_centrl_ctrl_27[6]; assign rcmu1_pclksel = out_centrl_ctrl_27[5]; assign rcmu1_tx_cgb_pdb = out_centrl_ctrl_27[4]; // CMU1 control register 7 assign rcmu1_iqsel = out_centrl_ctrl_28[15:14]; assign rcmu1_refsel[1:0] = out_centrl_ctrl_28[13:12]; assign rcmu1_vcobypass = out_centrl_ctrl_28[11]; assign rcmu1_revlb_sw = out_centrl_ctrl_28[10]; assign rcmu1_pcs_sd_sel = out_centrl_ctrl_28[3]; // CMU1 control register 8 assign rcmu1_reserved[31:16] = out_centrl_ctrl_29[15:0]; // CMU1 RX CRAMs // CMU1 control register 9 assign rcmu1_rx_lst[4:0] = out_centrl_ctrl_30[15:11]; assign rcmu1_rx_bit_dc[3:0] = out_centrl_ctrl_30[10:7]; assign rcmu1_s_rdlpbk = out_centrl_ctrl_30[6]; assign rcmu1_rx_vtt[2:0] = out_centrl_ctrl_30[5:3]; assign rcmu1_term[2:0] = out_centrl_ctrl_30[2:0]; // CMU1 control register 10 assign rcmu1_rx_sdlv[3:0] = out_centrl_ctrl_31[15:12]; assign rcmu1_rx_oc_en = out_centrl_ctrl_31[11]; assign rcmu1_rx_oc[7:0] = out_centrl_ctrl_31[10:3]; assign rcmu1_sd_force = out_centrl_ctrl_31[2]; assign rcmu1_rx_test = out_centrl_ctrl_31[1]; assign rcmu1_rxurst = out_centrl_ctrl_31[0]; // CMU1 control register 11 assign rcmu1_rx_sd_on[3:0] = out_centrl_ctrl_32[15:12]; assign rcmu1_rx_sd_off[4:0] = out_centrl_ctrl_32[11:7]; assign rcmu1_rx_oc_calpd = out_centrl_ctrl_32[6]; assign rcmu1_urx_pdb = out_centrl_ctrl_32[5]; assign rcmu1_rx_ib_pdb = out_centrl_ctrl_32[4]; assign rcmu1_powdnr = out_centrl_ctrl_32[3]; // CMU1 control register 12 assign rcmu1_div2 = out_centrl_ctrl_33[15]; assign rcmu1_m_sel[1:0] = out_centrl_ctrl_33[14:13]; assign rcmu1_m[3:0] = out_centrl_ctrl_33[12:9]; assign rcmu1_l[1:0] = out_centrl_ctrl_33[8:7]; assign rcmu1_ctl0 = out_centrl_ctrl_33[6]; assign rcmu1_crplctrl[1:0] = out_centrl_ctrl_33[5:4]; assign rcmu1_pfdbwctrl[1:0] = out_centrl_ctrl_33[3:2]; assign rcmu1_pdbwctrl[1:0] = out_centrl_ctrl_33[1:0]; // CMU1 control register 13 assign rcmu1_rlbk = out_centrl_ctrl_34[15]; assign rcmu1_lst[3:0] = out_centrl_ctrl_34[14:11]; assign rcmu1_testen = out_centrl_ctrl_34[10]; assign rcmu1_testupen = out_centrl_ctrl_34[9]; assign rcmu1_testdnen = out_centrl_ctrl_34[8]; assign rcmu1_isel[2:0] = out_centrl_ctrl_34[7:5]; assign rcmu1_iselpd[2:0] = out_centrl_ctrl_34[4:2]; // CMU1 control register 14 assign rcmu1_rcp_mode = out_centrl_ctrl_35[15]; assign rcmu1_cru_pdb = out_centrl_ctrl_35[12]; assign rcmu1_rx_cmu_rst = out_centrl_ctrl_35[11]; assign rcmu1_cmu_mode = out_centrl_ctrl_35[10]; assign rcmu1_ignore_phslck = out_centrl_ctrl_35[9]; assign rcmu1_sd_sel = out_centrl_ctrl_35[7]; assign rcmu1_pdfl = out_centrl_ctrl_35[6]; assign rcmu1_pdof_test[2:0] = out_centrl_ctrl_35[5:3]; assign rcmu1_rgla_isel[2:0] = out_centrl_ctrl_35[2:0]; // CMU1 control register 15 assign rcmu1_pdof_0i[3:0] = out_centrl_ctrl_36[15:12]; assign rcmu1_pdof_90i[3:0] = out_centrl_ctrl_36[11:8]; assign rcmu1_pdof_180i[3:0] = out_centrl_ctrl_36[7:4]; assign rcmu1_pdof_270i[3:0] = out_centrl_ctrl_36[3:0]; // CMU1 control register 16 assign rcmu1_eye_monitor[7:0] = out_centrl_ctrl_37[7:0]; // CMU1 control register 17 assign rcmu1_reserved[15:0] = out_centrl_ctrl_38[15:0]; // CMU1 control register 18 assign rcmu1_pma_doublewidth_rx = out_centrl_ctrl_39[15]; assign rcmu1_pmadwidth_rx = out_centrl_ctrl_39[14]; assign rcmu1_test_fastsd = out_centrl_ctrl_39[13]; assign rcmu1_fastsd[3:0] = out_centrl_ctrl_39[12:9]; assign rcmu1_ppmsel[5:0] = out_centrl_ctrl_39[8:3]; assign rcmu1_force0_freqdet = out_centrl_ctrl_39[2]; assign rcmu1_force1_freqdet = out_centrl_ctrl_39[1]; // CMU1 control register 19 assign rcmu1_dfe_1t[2:0] = out_centrl_ctrl_40[15:13]; assign rcmu1_dfe_2t[2:0] = out_centrl_ctrl_40[12:10]; // CMU1 control register 20 assign rcmu1_eqa_set[1:0] = out_centrl_ctrl_41[13:12]; assign rcmu1_eqb_set[1:0] = out_centrl_ctrl_41[10:9]; assign rcmu1_eqc_set[1:0] = out_centrl_ctrl_41[7:6]; assign rcmu1_eqd_set[1:0] = out_centrl_ctrl_41[4:3]; assign rcmu1_eqv_set[1:0] = out_centrl_ctrl_41[1:0]; // CMU1 control register 21 assign rcmu1_d2a_res[5:0] = out_centrl_ctrl_42[15:10]; assign rcmu1_clk_div2[1:0] = out_centrl_ctrl_42[9:8]; assign rcmu1_ht_sel = out_centrl_ctrl_42[7]; assign rcmu1_fbclk_sel = out_centrl_ctrl_42[6]; assign rcmu1_clk_pdb = out_centrl_ctrl_42[5]; assign rcmu1_rx_det_pdb = out_centrl_ctrl_42[4]; assign rcmu1_iqclk_sel = out_centrl_ctrl_42[2]; assign rcmu1_detect_on = out_centrl_ctrl_42[1]; // END CMU1 CRAMs // Central PCS CRAMs // PCS central channel control register: DTE XS register assign rs_lpbk_all =out_centrl_ctrl_43[14]; assign rpowerdown =out_centrl_ctrl_43[11]; // PCS central channel control register 1 assign rtest_bus_centrl_sel[3]=out_centrl_ctrl_44[15]; assign rx16_x12_sel_tx =out_centrl_ctrl_44[14]; assign rx16_x12_sel_rx =out_centrl_ctrl_44[13]; assign rtest_bus_centrl_sel[2:0]=out_centrl_ctrl_44[12:10]; assign rphfifo_master_sel_tx =out_centrl_ctrl_44[9]; assign rphfifo_master_sel_rx =out_centrl_ctrl_44[8]; assign rendec_data_sel_tx =out_centrl_ctrl_44[7]; assign rendec_data_sel_rx =out_centrl_ctrl_44[6]; assign rnenbpin =out_centrl_ctrl_44[5]; assign rpllurst =out_centrl_ctrl_44[4]; assign rreset =out_centrl_ctrl_44[3]; assign rdeskewen =out_centrl_ctrl_44[2]; assign rindv_tx =out_centrl_ctrl_44[1]; assign rindv_rx =out_centrl_ctrl_44[0]; // PCS central channel control register 2 assign rfreerun_centrl =out_centrl_ctrl_45[15]; assign rcentrl_clk_sel =out_centrl_ctrl_45[14]; assign rrefclk_out_div2 =out_centrl_ctrl_45[13]; assign rxaui_s2gx_en_rx =out_centrl_ctrl_45[12]; assign ralgnopt =out_centrl_ctrl_45[11]; assign rdskposdisp =out_centrl_ctrl_45[10]; assign rdskchrp =out_centrl_ctrl_45[9:0]; // PCS central channel control register 3 assign rxaui_s2gx_en_tx =out_centrl_ctrl_46[15]; assign rpcs_centrl_rsvd_cram =out_centrl_ctrl_46[14:4]; assign rmaster_rx =out_centrl_ctrl_46[3]; assign rmaster_up_rx =out_centrl_ctrl_46[2]; assign rmaster_tx =out_centrl_ctrl_46[1]; assign rmaster_up_tx =out_centrl_ctrl_46[0]; // DPRIO registers stratixiv_hssi_cmu_dprio_reg_centrl reg_centrl_inst ( .mdio_rst(mdio_rst), .mdio_wr(mdio_wr), .reg_addr(reg_addr), .mdc(mdc), .mbus_in(mbus_in), .serial_mode(serial_mode), .mdio_dis(mdio_dis), .pma_cram_test(pma_cram_test), .ser_shift_load(ser_shift_load), .si(si), // CSR input .ext_centrl_ctrl_1(csr_centrl_in[15:0]), .ext_centrl_ctrl_2(csr_centrl_in[31:16]), .ext_centrl_ctrl_3(csr_centrl_in[47:32]), .ext_centrl_ctrl_4(csr_centrl_in[63:48]), .ext_centrl_ctrl_5(csr_centrl_in[79:64]), .ext_centrl_ctrl_6(csr_centrl_in[95:80]), .ext_centrl_ctrl_7(csr_centrl_in[111:96]), .ext_centrl_ctrl_8(csr_centrl_in[127:112]), .ext_centrl_ctrl_9(csr_centrl_in[143:128]), .ext_centrl_ctrl_10(csr_centrl_in[159:144]), .ext_centrl_ctrl_11(csr_centrl_in[175:160]), .ext_centrl_ctrl_12(csr_centrl_in[191:176]), .ext_centrl_ctrl_13(csr_centrl_in[207:192]), .ext_centrl_ctrl_14(csr_centrl_in[223:208]), .ext_centrl_ctrl_15(csr_centrl_in[239:224]), .ext_centrl_ctrl_16(csr_centrl_in_reserved[15:0]), .ext_centrl_ctrl_17(csr_centrl_in[255:240]), .ext_centrl_ctrl_18(csr_centrl_in[271:256]), .ext_centrl_ctrl_19(csr_centrl_in[287:272]), .ext_centrl_ctrl_20(csr_centrl_in[303:288]), .ext_centrl_ctrl_21(csr_centrl_in[319:304]), .ext_centrl_ctrl_22(csr_centrl_in[335:320]), .ext_centrl_ctrl_23(csr_centrl_in[351:336]), .ext_centrl_ctrl_24(csr_centrl_in[367:352]), .ext_centrl_ctrl_25(csr_centrl_in[383:368]), .ext_centrl_ctrl_26(csr_centrl_in[399:384]), .ext_centrl_ctrl_27(csr_centrl_in[415:400]), .ext_centrl_ctrl_28(csr_centrl_in[431:416]), .ext_centrl_ctrl_29(csr_centrl_in[447:432]), .ext_centrl_ctrl_30(csr_centrl_in[463:448]), .ext_centrl_ctrl_31(csr_centrl_in[479:464]), .ext_centrl_ctrl_32(csr_centrl_in[495:480]), .ext_centrl_ctrl_33(csr_centrl_in[511:496]), .ext_centrl_ctrl_34(csr_centrl_in[527:512]), .ext_centrl_ctrl_35(csr_centrl_in[543:528]), .ext_centrl_ctrl_36(csr_centrl_in[559:544]), .ext_centrl_ctrl_37(csr_centrl_in_reserved[31:16]), .ext_centrl_ctrl_38(csr_centrl_in[575:560]), .ext_centrl_ctrl_39(csr_centrl_in[591:576]), .ext_centrl_ctrl_40(csr_centrl_in[607:592]), .ext_centrl_ctrl_41(csr_centrl_in[623:608]), .ext_centrl_ctrl_42(csr_centrl_in[639:624]), .ext_centrl_ctrl_43(csr_centrl_in[655:640]), .ext_centrl_ctrl_44(csr_centrl_in[671:656]), .ext_centrl_ctrl_45(csr_centrl_in[687:672]), .ext_centrl_ctrl_46(csr_centrl_in[703:688]), .targ_addr_ctrl_1(targ_addr_ctrl_1), .targ_addr_ctrl_2(targ_addr_ctrl_2), .targ_addr_ctrl_3(targ_addr_ctrl_3), .targ_addr_ctrl_4(targ_addr_ctrl_4), .targ_addr_ctrl_5(targ_addr_ctrl_5), .targ_addr_ctrl_6(targ_addr_ctrl_6), .targ_addr_ctrl_7(targ_addr_ctrl_7), .targ_addr_ctrl_8(targ_addr_ctrl_8), .targ_addr_ctrl_9(targ_addr_ctrl_9), .targ_addr_ctrl_10(targ_addr_ctrl_10), .targ_addr_ctrl_11(targ_addr_ctrl_11), .targ_addr_ctrl_12(targ_addr_ctrl_12), .targ_addr_ctrl_13(targ_addr_ctrl_13), .targ_addr_ctrl_14(targ_addr_ctrl_14), .targ_addr_ctrl_15(targ_addr_ctrl_15), .targ_addr_ctrl_16(targ_addr_ctrl_16), .targ_addr_ctrl_17(targ_addr_ctrl_17), .targ_addr_ctrl_18(targ_addr_ctrl_18), .targ_addr_ctrl_19(targ_addr_ctrl_19), .targ_addr_ctrl_20(targ_addr_ctrl_20), .targ_addr_ctrl_21(targ_addr_ctrl_21), .targ_addr_ctrl_22(targ_addr_ctrl_22), .targ_addr_ctrl_23(targ_addr_ctrl_23), .targ_addr_ctrl_24(targ_addr_ctrl_24), .targ_addr_ctrl_25(targ_addr_ctrl_25), .targ_addr_ctrl_26(targ_addr_ctrl_26), .targ_addr_ctrl_27(targ_addr_ctrl_27), .targ_addr_ctrl_28(targ_addr_ctrl_28), .targ_addr_ctrl_29(targ_addr_ctrl_29), .targ_addr_ctrl_30(targ_addr_ctrl_30), .targ_addr_ctrl_31(targ_addr_ctrl_31), .targ_addr_ctrl_32(targ_addr_ctrl_32), .targ_addr_ctrl_33(targ_addr_ctrl_33), .targ_addr_ctrl_34(targ_addr_ctrl_34), .targ_addr_ctrl_35(targ_addr_ctrl_35), .targ_addr_ctrl_36(targ_addr_ctrl_36), .targ_addr_ctrl_37(targ_addr_ctrl_37), .targ_addr_ctrl_38(targ_addr_ctrl_38), .targ_addr_ctrl_39(targ_addr_ctrl_39), .targ_addr_ctrl_40(targ_addr_ctrl_40), .targ_addr_ctrl_41(targ_addr_ctrl_41), .targ_addr_ctrl_42(targ_addr_ctrl_42), .targ_addr_ctrl_43(targ_addr_ctrl_43), .targ_addr_ctrl_44(targ_addr_ctrl_44), .targ_addr_ctrl_45(targ_addr_ctrl_45), .targ_addr_ctrl_46(targ_addr_ctrl_46), // DPRIO register output .out_centrl_ctrl_1(out_centrl_ctrl_1), .out_centrl_ctrl_2(out_centrl_ctrl_2), .out_centrl_ctrl_3(out_centrl_ctrl_3), .out_centrl_ctrl_4(out_centrl_ctrl_4), .out_centrl_ctrl_5(out_centrl_ctrl_5), .out_centrl_ctrl_6(out_centrl_ctrl_6), .out_centrl_ctrl_7(out_centrl_ctrl_7), .out_centrl_ctrl_8(out_centrl_ctrl_8), .out_centrl_ctrl_9(out_centrl_ctrl_9), .out_centrl_ctrl_10(out_centrl_ctrl_10), .out_centrl_ctrl_11(out_centrl_ctrl_11), .out_centrl_ctrl_12(out_centrl_ctrl_12), .out_centrl_ctrl_13(out_centrl_ctrl_13), .out_centrl_ctrl_14(out_centrl_ctrl_14), .out_centrl_ctrl_15(out_centrl_ctrl_15), .out_centrl_ctrl_16(out_centrl_ctrl_16), .out_centrl_ctrl_17(out_centrl_ctrl_17), .out_centrl_ctrl_18(out_centrl_ctrl_18), .out_centrl_ctrl_19(out_centrl_ctrl_19), .out_centrl_ctrl_20(out_centrl_ctrl_20), .out_centrl_ctrl_21(out_centrl_ctrl_21), .out_centrl_ctrl_22(out_centrl_ctrl_22), .out_centrl_ctrl_23(out_centrl_ctrl_23), .out_centrl_ctrl_24(out_centrl_ctrl_24), .out_centrl_ctrl_25(out_centrl_ctrl_25), .out_centrl_ctrl_26(out_centrl_ctrl_26), .out_centrl_ctrl_27(out_centrl_ctrl_27), .out_centrl_ctrl_28(out_centrl_ctrl_28), .out_centrl_ctrl_29(out_centrl_ctrl_29), .out_centrl_ctrl_30(out_centrl_ctrl_30), .out_centrl_ctrl_31(out_centrl_ctrl_31), .out_centrl_ctrl_32(out_centrl_ctrl_32), .out_centrl_ctrl_33(out_centrl_ctrl_33), .out_centrl_ctrl_34(out_centrl_ctrl_34), .out_centrl_ctrl_35(out_centrl_ctrl_35), .out_centrl_ctrl_36(out_centrl_ctrl_36), .out_centrl_ctrl_37(out_centrl_ctrl_37), .out_centrl_ctrl_38(out_centrl_ctrl_38), .out_centrl_ctrl_39(out_centrl_ctrl_39), .out_centrl_ctrl_40(out_centrl_ctrl_40), .out_centrl_ctrl_41(out_centrl_ctrl_41), .out_centrl_ctrl_42(out_centrl_ctrl_42), .out_centrl_ctrl_43(out_centrl_ctrl_43), .out_centrl_ctrl_44(out_centrl_ctrl_44), .out_centrl_ctrl_45(out_centrl_ctrl_45), .out_centrl_ctrl_46(out_centrl_ctrl_46), .so(so) ); // MBUS_OUT muxing for central channel stratixiv_hssi_cmu_dprio_centrl_bus_out_mux mbus_mux_inst ( .centrl_ctrl_in1 (out_centrl_ctrl_1), .centrl_ctrl_in2 (out_centrl_ctrl_2), .centrl_ctrl_in3 (out_centrl_ctrl_3), .centrl_ctrl_in4 (out_centrl_ctrl_4), .centrl_ctrl_in5 (out_centrl_ctrl_5), .centrl_ctrl_in6 (out_centrl_ctrl_6), .centrl_ctrl_in7 (out_centrl_ctrl_7), .centrl_ctrl_in8 (out_centrl_ctrl_8), .centrl_ctrl_in9 (out_centrl_ctrl_9), .centrl_ctrl_in10(out_centrl_ctrl_10), .centrl_ctrl_in11(out_centrl_ctrl_11), .centrl_ctrl_in12(out_centrl_ctrl_12), .centrl_ctrl_in13(out_centrl_ctrl_13), .centrl_ctrl_in14(out_centrl_ctrl_14), .centrl_ctrl_in15(out_centrl_ctrl_15), .centrl_ctrl_in16(out_centrl_ctrl_16), .centrl_ctrl_in17(out_centrl_ctrl_17), .centrl_ctrl_in18(out_centrl_ctrl_18), .centrl_ctrl_in19(out_centrl_ctrl_19), .centrl_ctrl_in20(out_centrl_ctrl_20), .centrl_ctrl_in21(out_centrl_ctrl_21), .centrl_ctrl_in22(out_centrl_ctrl_22), .centrl_ctrl_in23(out_centrl_ctrl_23), .centrl_ctrl_in24(out_centrl_ctrl_24), .centrl_ctrl_in25(out_centrl_ctrl_25), .centrl_ctrl_in26(out_centrl_ctrl_26), .centrl_ctrl_in27(out_centrl_ctrl_27), .centrl_ctrl_in28(out_centrl_ctrl_28), .centrl_ctrl_in29(out_centrl_ctrl_29), .centrl_ctrl_in30(out_centrl_ctrl_30), .centrl_ctrl_in31(out_centrl_ctrl_31), .centrl_ctrl_in32(out_centrl_ctrl_32), .centrl_ctrl_in33(out_centrl_ctrl_33), .centrl_ctrl_in34(out_centrl_ctrl_34), .centrl_ctrl_in35(out_centrl_ctrl_35), .centrl_ctrl_in36(out_centrl_ctrl_36), .centrl_ctrl_in37(out_centrl_ctrl_37), .centrl_ctrl_in38(out_centrl_ctrl_38), .centrl_ctrl_in39(out_centrl_ctrl_39), .centrl_ctrl_in40(out_centrl_ctrl_40), .centrl_ctrl_in41(out_centrl_ctrl_41), .centrl_ctrl_in42(out_centrl_ctrl_42), .centrl_ctrl_in43(out_centrl_ctrl_43), .centrl_ctrl_in44(out_centrl_ctrl_44), .centrl_ctrl_in45(out_centrl_ctrl_45), .centrl_ctrl_in46(out_centrl_ctrl_46), .hw_address_ctrl_in1 (targ_addr_ctrl_1), .hw_address_ctrl_in2 (targ_addr_ctrl_2), .hw_address_ctrl_in3 (targ_addr_ctrl_3), .hw_address_ctrl_in4 (targ_addr_ctrl_4), .hw_address_ctrl_in5 (targ_addr_ctrl_5), .hw_address_ctrl_in6 (targ_addr_ctrl_6), .hw_address_ctrl_in7 (targ_addr_ctrl_7), .hw_address_ctrl_in8 (targ_addr_ctrl_8), .hw_address_ctrl_in9 (targ_addr_ctrl_9), .hw_address_ctrl_in10(targ_addr_ctrl_10), .hw_address_ctrl_in11(targ_addr_ctrl_11), .hw_address_ctrl_in12(targ_addr_ctrl_12), .hw_address_ctrl_in13(targ_addr_ctrl_13), .hw_address_ctrl_in14(targ_addr_ctrl_14), .hw_address_ctrl_in15(targ_addr_ctrl_15), .hw_address_ctrl_in16(targ_addr_ctrl_16), .hw_address_ctrl_in17(targ_addr_ctrl_17), .hw_address_ctrl_in18(targ_addr_ctrl_18), .hw_address_ctrl_in19(targ_addr_ctrl_19), .hw_address_ctrl_in20(targ_addr_ctrl_20), .hw_address_ctrl_in21(targ_addr_ctrl_21), .hw_address_ctrl_in22(targ_addr_ctrl_22), .hw_address_ctrl_in23(targ_addr_ctrl_23), .hw_address_ctrl_in24(targ_addr_ctrl_24), .hw_address_ctrl_in25(targ_addr_ctrl_25), .hw_address_ctrl_in26(targ_addr_ctrl_26), .hw_address_ctrl_in27(targ_addr_ctrl_27), .hw_address_ctrl_in28(targ_addr_ctrl_28), .hw_address_ctrl_in29(targ_addr_ctrl_29), .hw_address_ctrl_in30(targ_addr_ctrl_30), .hw_address_ctrl_in31(targ_addr_ctrl_31), .hw_address_ctrl_in32(targ_addr_ctrl_32), .hw_address_ctrl_in33(targ_addr_ctrl_33), .hw_address_ctrl_in34(targ_addr_ctrl_34), .hw_address_ctrl_in35(targ_addr_ctrl_35), .hw_address_ctrl_in36(targ_addr_ctrl_36), .hw_address_ctrl_in37(targ_addr_ctrl_37), .hw_address_ctrl_in38(targ_addr_ctrl_38), .hw_address_ctrl_in39(targ_addr_ctrl_39), .hw_address_ctrl_in40(targ_addr_ctrl_40), .hw_address_ctrl_in41(targ_addr_ctrl_41), .hw_address_ctrl_in42(targ_addr_ctrl_42), .hw_address_ctrl_in43(targ_addr_ctrl_43), .hw_address_ctrl_in44(targ_addr_ctrl_44), .hw_address_ctrl_in45(targ_addr_ctrl_45), .hw_address_ctrl_in46(targ_addr_ctrl_46), .reg_addr(reg_addr), .centrl_ctrl_out(mbus_out) ); endmodule `timescale 1 ps / 1 ps module stratixiv_hssi_cmu_dprio_map_index( pll0_init_pfd_clk_sel, pll0_dp_riqclk_sel, pll0_dp_rrefclk_sel, pll0_csr_riqclk_sel, pll0_csr_rrefclk_sel, pll0_dp_pfd_clk_sel, pll1_init_pfd_clk_sel, pll1_dp_riqclk_sel, pll1_dp_rrefclk_sel, pll1_csr_riqclk_sel, pll1_csr_rrefclk_sel, pll1_dp_pfd_clk_sel, pll2_init_pfd_clk_sel, pll2_dp_riqclk_sel, pll2_dp_rrefclk_sel, pll2_csr_riqclk_sel, pll2_csr_rrefclk_sel, pll2_dp_pfd_clk_sel, pll3_init_pfd_clk_sel, pll3_dp_riqclk_sel, pll3_dp_rrefclk_sel, pll3_csr_riqclk_sel, pll3_csr_rrefclk_sel, pll3_dp_pfd_clk_sel, pll4_init_pfd_clk_sel, pll4_dp_riqclk_sel, pll4_dp_rrefclk_sel, pll4_csr_riqclk_sel, pll4_csr_rrefclk_sel, pll4_dp_pfd_clk_sel, pll5_init_pfd_clk_sel, pll5_dp_riqclk_sel, pll5_dp_rrefclk_sel, pll5_csr_riqclk_sel, pll5_csr_rrefclk_sel, pll5_dp_pfd_clk_sel, txpma0_init_clkin_sel, txpma0_csr_rcgb_x_en, txpma0_dp_rcgb_x_en, txpma0_dp_clkin_sel, txpma1_init_clkin_sel, txpma1_csr_rcgb_x_en, txpma1_dp_rcgb_x_en, txpma1_dp_clkin_sel, txpma2_init_clkin_sel, txpma2_csr_rcgb_x_en, txpma2_dp_rcgb_x_en, txpma2_dp_clkin_sel, txpma3_init_clkin_sel, txpma3_csr_rcgb_x_en, txpma3_dp_rcgb_x_en, txpma3_dp_clkin_sel, txpma4_init_clkin_sel, txpma4_csr_rcgb_x_en, txpma4_dp_rcgb_x_en, txpma4_dp_clkin_sel, txpma5_init_clkin_sel, txpma5_csr_rcgb_x_en, txpma5_dp_rcgb_x_en, txpma5_dp_clkin_sel, clkdiv0_init_inclk_select, clkdiv0_csr_rcgb_cmu_sel, clkdiv0_dp_rcgb_cmu_sel, clkdiv0_dp_inclk_select, clkdiv1_init_inclk_select, clkdiv1_csr_rcgb_cmu_sel, clkdiv1_dp_rcgb_cmu_sel, clkdiv1_dp_inclk_select, clkdiv2_init_inclk_select, clkdiv2_csr_rcgb_cmu_sel, clkdiv2_dp_rcgb_cmu_sel, clkdiv2_dp_inclk_select, clkdiv3_init_inclk_select, clkdiv3_csr_rcgb_cmu_sel, clkdiv3_dp_rcgb_cmu_sel, clkdiv3_dp_inclk_select, clkdiv4_init_inclk_select, clkdiv4_csr_rcgb_cmu_sel, clkdiv4_dp_rcgb_cmu_sel, clkdiv4_dp_inclk_select, clkdiv5_init_inclk_select, clkdiv5_csr_rcgb_cmu_sel, clkdiv5_dp_rcgb_cmu_sel, clkdiv5_dp_inclk_select ); input [3:0] pll0_init_pfd_clk_sel; // on logic channel pll0 input [1:0] pll0_dp_riqclk_sel; input [1:0] pll0_dp_rrefclk_sel; output [1:0] pll0_csr_riqclk_sel; output [1:0] pll0_csr_rrefclk_sel; output [3:0] pll0_dp_pfd_clk_sel; input [3:0] pll1_init_pfd_clk_sel; input [1:0] pll1_dp_riqclk_sel; input [1:0] pll1_dp_rrefclk_sel; output [1:0] pll1_csr_riqclk_sel; output [1:0] pll1_csr_rrefclk_sel; output [3:0] pll1_dp_pfd_clk_sel; input [3:0] pll2_init_pfd_clk_sel; input [1:0] pll2_dp_riqclk_sel; input [1:0] pll2_dp_rrefclk_sel; output [1:0] pll2_csr_riqclk_sel; output [1:0] pll2_csr_rrefclk_sel; output [3:0] pll2_dp_pfd_clk_sel; input [3:0] pll3_init_pfd_clk_sel; input [1:0] pll3_dp_riqclk_sel; input [1:0] pll3_dp_rrefclk_sel; output [1:0] pll3_csr_riqclk_sel; output [1:0] pll3_csr_rrefclk_sel; output [3:0] pll3_dp_pfd_clk_sel; input [3:0] pll4_init_pfd_clk_sel; input [1:0] pll4_dp_riqclk_sel; input [1:0] pll4_dp_rrefclk_sel; output [1:0] pll4_csr_riqclk_sel; output [1:0] pll4_csr_rrefclk_sel; output [3:0] pll4_dp_pfd_clk_sel; input [3:0] pll5_init_pfd_clk_sel; input [1:0] pll5_dp_riqclk_sel; input [1:0] pll5_dp_rrefclk_sel; output [1:0] pll5_csr_riqclk_sel; output [1:0] pll5_csr_rrefclk_sel; output [3:0] pll5_dp_pfd_clk_sel; input [2:0] txpma0_init_clkin_sel; output [1:0] txpma0_csr_rcgb_x_en; input [1:0] txpma0_dp_rcgb_x_en; output [2:0] txpma0_dp_clkin_sel; input [2:0] txpma1_init_clkin_sel; output [1:0] txpma1_csr_rcgb_x_en; input [1:0] txpma1_dp_rcgb_x_en; output [2:0] txpma1_dp_clkin_sel; input [2:0] txpma2_init_clkin_sel; output [1:0] txpma2_csr_rcgb_x_en; input [1:0] txpma2_dp_rcgb_x_en; output [2:0] txpma2_dp_clkin_sel; input [2:0] txpma3_init_clkin_sel; output [1:0] txpma3_csr_rcgb_x_en; input [1:0] txpma3_dp_rcgb_x_en; output [2:0] txpma3_dp_clkin_sel; input [2:0] txpma4_init_clkin_sel; output [1:0] txpma4_csr_rcgb_x_en; input [1:0] txpma4_dp_rcgb_x_en; output [2:0] txpma4_dp_clkin_sel; input [2:0] txpma5_init_clkin_sel; output [1:0] txpma5_csr_rcgb_x_en; input [1:0] txpma5_dp_rcgb_x_en; output [2:0] txpma5_dp_clkin_sel; input clkdiv0_init_inclk_select; output clkdiv0_csr_rcgb_cmu_sel; input clkdiv0_dp_rcgb_cmu_sel; output clkdiv0_dp_inclk_select; input clkdiv1_init_inclk_select; output clkdiv1_csr_rcgb_cmu_sel; input clkdiv1_dp_rcgb_cmu_sel; output clkdiv1_dp_inclk_select; input clkdiv2_init_inclk_select; output clkdiv2_csr_rcgb_cmu_sel; input clkdiv2_dp_rcgb_cmu_sel; output clkdiv2_dp_inclk_select; input clkdiv3_init_inclk_select; output clkdiv3_csr_rcgb_cmu_sel; input clkdiv3_dp_rcgb_cmu_sel; output clkdiv3_dp_inclk_select; input clkdiv4_init_inclk_select; output clkdiv4_csr_rcgb_cmu_sel; input clkdiv4_dp_rcgb_cmu_sel; output clkdiv4_dp_inclk_select; input clkdiv5_init_inclk_select; output clkdiv5_csr_rcgb_cmu_sel; input clkdiv5_dp_rcgb_cmu_sel; output clkdiv5_dp_inclk_select; // -------------------- Simulation only parameters ---------------------------- parameter clkdiv0_inclk0_logical_to_physical_mapping = "pll0"; parameter clkdiv0_inclk1_logical_to_physical_mapping = "pll1"; parameter clkdiv1_inclk0_logical_to_physical_mapping = "pll0"; parameter clkdiv1_inclk1_logical_to_physical_mapping = "pll1"; parameter clkdiv2_inclk0_logical_to_physical_mapping = "pll0"; parameter clkdiv2_inclk1_logical_to_physical_mapping = "pll1"; parameter clkdiv3_inclk0_logical_to_physical_mapping = "pll0"; parameter clkdiv3_inclk1_logical_to_physical_mapping = "pll1"; parameter clkdiv4_inclk0_logical_to_physical_mapping = "pll0"; parameter clkdiv4_inclk1_logical_to_physical_mapping = "pll1"; parameter clkdiv5_inclk0_logical_to_physical_mapping = "pll0"; parameter clkdiv5_inclk1_logical_to_physical_mapping = "pll1"; parameter pll0_inclk0_logical_to_physical_mapping = "clkrefclk0"; parameter pll0_inclk1_logical_to_physical_mapping = "clkrefclk1"; parameter pll0_inclk2_logical_to_physical_mapping = "iq2"; parameter pll0_inclk3_logical_to_physical_mapping = "iq3"; parameter pll0_inclk4_logical_to_physical_mapping = "iq4"; parameter pll0_inclk5_logical_to_physical_mapping = "iq5"; parameter pll0_inclk6_logical_to_physical_mapping = "iq6"; parameter pll0_inclk7_logical_to_physical_mapping = "iq7"; parameter pll0_inclk8_logical_to_physical_mapping = "pld_clk"; parameter pll0_inclk9_logical_to_physical_mapping = "gpll_clk"; parameter pll1_inclk0_logical_to_physical_mapping = "clkrefclk0"; parameter pll1_inclk1_logical_to_physical_mapping = "clkrefclk1"; parameter pll1_inclk2_logical_to_physical_mapping = "iq2"; parameter pll1_inclk3_logical_to_physical_mapping = "iq3"; parameter pll1_inclk4_logical_to_physical_mapping = "iq4"; parameter pll1_inclk5_logical_to_physical_mapping = "iq5"; parameter pll1_inclk6_logical_to_physical_mapping = "iq6"; parameter pll1_inclk7_logical_to_physical_mapping = "iq7"; parameter pll1_inclk8_logical_to_physical_mapping = "pld_clk"; parameter pll1_inclk9_logical_to_physical_mapping = "gpll_clk"; parameter pll2_inclk0_logical_to_physical_mapping = "clkrefclk0"; parameter pll2_inclk1_logical_to_physical_mapping = "clkrefclk1"; parameter pll2_inclk2_logical_to_physical_mapping = "iq2"; parameter pll2_inclk3_logical_to_physical_mapping = "iq3"; parameter pll2_inclk4_logical_to_physical_mapping = "iq4"; parameter pll2_inclk5_logical_to_physical_mapping = "iq5"; parameter pll2_inclk6_logical_to_physical_mapping = "iq6"; parameter pll2_inclk7_logical_to_physical_mapping = "iq7"; parameter pll2_inclk8_logical_to_physical_mapping = "pld_clk"; parameter pll2_inclk9_logical_to_physical_mapping = "gpll_clk"; parameter pll3_inclk0_logical_to_physical_mapping = "clkrefclk0"; parameter pll3_inclk1_logical_to_physical_mapping = "clkrefclk1"; parameter pll3_inclk2_logical_to_physical_mapping = "iq2"; parameter pll3_inclk3_logical_to_physical_mapping = "iq3"; parameter pll3_inclk4_logical_to_physical_mapping = "iq4"; parameter pll3_inclk5_logical_to_physical_mapping = "iq5"; parameter pll3_inclk6_logical_to_physical_mapping = "iq6"; parameter pll3_inclk7_logical_to_physical_mapping = "iq7"; parameter pll3_inclk8_logical_to_physical_mapping = "pld_clk"; parameter pll3_inclk9_logical_to_physical_mapping = "gpll_clk"; parameter pll4_inclk0_logical_to_physical_mapping = "clkrefclk0"; parameter pll4_inclk1_logical_to_physical_mapping = "clkrefclk1"; parameter pll4_inclk2_logical_to_physical_mapping = "iq2"; parameter pll4_inclk3_logical_to_physical_mapping = "iq3"; parameter pll4_inclk4_logical_to_physical_mapping = "iq4"; parameter pll4_inclk5_logical_to_physical_mapping = "iq5"; parameter pll4_inclk6_logical_to_physical_mapping = "iq6"; parameter pll4_inclk7_logical_to_physical_mapping = "iq7"; parameter pll4_inclk8_logical_to_physical_mapping = "pld_clk"; parameter pll4_inclk9_logical_to_physical_mapping = "gpll_clk"; parameter pll5_inclk0_logical_to_physical_mapping = "clkrefclk0"; parameter pll5_inclk1_logical_to_physical_mapping = "clkrefclk1"; parameter pll5_inclk2_logical_to_physical_mapping = "iq2"; parameter pll5_inclk3_logical_to_physical_mapping = "iq3"; parameter pll5_inclk4_logical_to_physical_mapping = "iq4"; parameter pll5_inclk5_logical_to_physical_mapping = "iq5"; parameter pll5_inclk6_logical_to_physical_mapping = "iq6"; parameter pll5_inclk7_logical_to_physical_mapping = "iq7"; parameter pll5_inclk8_logical_to_physical_mapping = "pld_clk"; parameter pll5_inclk9_logical_to_physical_mapping = "gpll_clk"; parameter pll0_logical_to_physical_mapping = 0 ; parameter pll1_logical_to_physical_mapping = 1 ; parameter pll2_logical_to_physical_mapping = 2 ; parameter pll3_logical_to_physical_mapping = 3 ; parameter pll4_logical_to_physical_mapping = 4 ; parameter pll5_logical_to_physical_mapping = 5 ; parameter refclk_divider0_logical_to_physical_mapping = 0 ; parameter refclk_divider1_logical_to_physical_mapping = 1 ; parameter rx0_logical_to_physical_mapping = 0 ; parameter rx1_logical_to_physical_mapping = 1 ; parameter rx2_logical_to_physical_mapping = 2 ; parameter rx3_logical_to_physical_mapping = 3 ; parameter rx4_logical_to_physical_mapping = 4 ; parameter rx5_logical_to_physical_mapping = 5 ; parameter tx0_logical_to_physical_mapping = 0 ; parameter tx1_logical_to_physical_mapping = 1 ; parameter tx2_logical_to_physical_mapping = 2 ; parameter tx3_logical_to_physical_mapping = 3 ; parameter tx4_logical_to_physical_mapping = 4 ; parameter tx5_logical_to_physical_mapping = 5 ; parameter tx0_pma_inclk0_logical_to_physical_mapping = "x1"; parameter tx0_pma_inclk1_logical_to_physical_mapping = "x4"; parameter tx0_pma_inclk2_logical_to_physical_mapping = "xn_top"; parameter tx0_pma_inclk3_logical_to_physical_mapping = "xn_bottom"; parameter tx0_pma_inclk4_logical_to_physical_mapping = "hypertransport"; parameter tx1_pma_inclk0_logical_to_physical_mapping = "x1"; parameter tx1_pma_inclk1_logical_to_physical_mapping = "x4"; parameter tx1_pma_inclk2_logical_to_physical_mapping = "xn_top"; parameter tx1_pma_inclk3_logical_to_physical_mapping = "xn_bottom"; parameter tx1_pma_inclk4_logical_to_physical_mapping = "hypertransport"; parameter tx2_pma_inclk0_logical_to_physical_mapping = "x1"; parameter tx2_pma_inclk1_logical_to_physical_mapping = "x4"; parameter tx2_pma_inclk2_logical_to_physical_mapping = "xn_top"; parameter tx2_pma_inclk3_logical_to_physical_mapping = "xn_bottom"; parameter tx2_pma_inclk4_logical_to_physical_mapping = "hypertransport"; parameter tx3_pma_inclk0_logical_to_physical_mapping = "x1"; parameter tx3_pma_inclk1_logical_to_physical_mapping = "x4"; parameter tx3_pma_inclk2_logical_to_physical_mapping = "xn_top"; parameter tx3_pma_inclk3_logical_to_physical_mapping = "xn_bottom"; parameter tx3_pma_inclk4_logical_to_physical_mapping = "hypertransport"; parameter tx4_pma_inclk0_logical_to_physical_mapping = "x1"; parameter tx4_pma_inclk1_logical_to_physical_mapping = "x4"; parameter tx4_pma_inclk2_logical_to_physical_mapping = "xn_top"; parameter tx4_pma_inclk3_logical_to_physical_mapping = "xn_bottom"; parameter tx4_pma_inclk4_logical_to_physical_mapping = "hypertransport"; parameter tx5_pma_inclk0_logical_to_physical_mapping = "x1"; parameter tx5_pma_inclk1_logical_to_physical_mapping = "x4"; parameter tx5_pma_inclk2_logical_to_physical_mapping = "xn_top"; parameter tx5_pma_inclk3_logical_to_physical_mapping = "xn_bottom"; parameter tx5_pma_inclk4_logical_to_physical_mapping = "hypertransport"; //------------------------------------------------------------------------- // PLL clock selection ---------------------------------------------------- //------------------------------------------------------------------------- `define PLL_CLOCK_SELECT_CLKREFCLK0 4'b0000 `define PLL_CLOCK_SELECT_CLKREFCLK1 4'b0001 `define PLL_CLOCK_SELECT_IQ2 4'b0010 `define PLL_CLOCK_SELECT_IQ3 4'b0011 `define PLL_CLOCK_SELECT_IQ4 4'b0100 `define PLL_CLOCK_SELECT_IQ5 4'b0101 `define PLL_CLOCK_SELECT_IQ6 4'b0110 `define PLL_CLOCK_SELECT_IQ7 4'b0111 `define PLL_CLOCK_SELECT_PLD_CLK 4'b1000 `define PLL_CLOCK_SELECT_GPLL_CLK 4'b1001 `define PLL_CLOCK_SELECT_ERR 4'b1010 function [3:0] convert_pll_clock_cram_to_phyport; input [1:0] rrefclk_sel; input [1:0] pldiq; reg [3:0] res; begin casex ({rrefclk_sel, pldiq}) 4'b00xx: res = `PLL_CLOCK_SELECT_CLKREFCLK0; 4'b01xx: res = `PLL_CLOCK_SELECT_CLKREFCLK1; 4'b1000: res = `PLL_CLOCK_SELECT_IQ2; 4'b1001: res = `PLL_CLOCK_SELECT_IQ3; 4'b1010: res = `PLL_CLOCK_SELECT_IQ4; 4'b1100: res = `PLL_CLOCK_SELECT_IQ5; 4'b1101: res = `PLL_CLOCK_SELECT_IQ6; 4'b1110: res = `PLL_CLOCK_SELECT_IQ7; 4'b1011: res = `PLL_CLOCK_SELECT_PLD_CLK; 4'b1111: res = `PLL_CLOCK_SELECT_GPLL_CLK; default: res = `PLL_CLOCK_SELECT_ERR; endcase convert_pll_clock_cram_to_phyport = res; end endfunction // input is at most 15 characters function integer convert_pll_phyport_str_to_phyport_enum; input phyport_str; reg [8*15:1] phyport_str; integer res; begin if (phyport_str == "iq2") res = `PLL_CLOCK_SELECT_IQ2; else if (phyport_str == "iq3") res = `PLL_CLOCK_SELECT_IQ3; else if (phyport_str == "iq4") res = `PLL_CLOCK_SELECT_IQ4; else if (phyport_str == "iq5") res = `PLL_CLOCK_SELECT_IQ5; else if (phyport_str == "iq6") res = `PLL_CLOCK_SELECT_IQ6; else if (phyport_str == "iq7") res = `PLL_CLOCK_SELECT_IQ7; else if (phyport_str == "refclk0" || phyport_str == "clkrefclk0") res = `PLL_CLOCK_SELECT_CLKREFCLK0; else if (phyport_str == "refclk1" || phyport_str == "clkrefclk1") res = `PLL_CLOCK_SELECT_CLKREFCLK1; else if (phyport_str == "pld_clk") res = `PLL_CLOCK_SELECT_PLD_CLK; else if (phyport_str == "gpll_clk") res = `PLL_CLOCK_SELECT_GPLL_CLK; else // like "none" res = `PLL_CLOCK_SELECT_ERR; convert_pll_phyport_str_to_phyport_enum = res; end endfunction // common to all PLL channels reg [4:0] pll_clock_phyport_to_cram [0:10]; // phyport to cram - include error string // READ --------------- ch0 reg [3:0] pll0_clock_index_to_phyport [0:9]; // map table - index to phyport integer wire [3:0] pll0_clock_select; wire [3:0] pll0_clock_phyport; wire [4:0] pll0_clock_cram, pll0_clock_cram_phy; // Write --------------- ch0 wire [3:0] pll0_clock_phyport_out, pll0_clock_phyport_out_logic; wire [3:0] pll0_clock_select_out_logic, pll0_clock_select_out; // READ reg [3:0] pll1_clock_index_to_phyport [0:9]; // map table - index to phyport integer wire [3:0] pll1_clock_select; wire [3:0] pll1_clock_phyport; wire [4:0] pll1_clock_cram, pll1_clock_cram_phy; // Write wire [3:0] pll1_clock_phyport_out, pll1_clock_phyport_out_logic; wire [3:0] pll1_clock_select_out_logic, pll1_clock_select_out; // READ reg [3:0] pll2_clock_index_to_phyport [0:9]; // map table - index to phyport integer wire [3:0] pll2_clock_select; wire [3:0] pll2_clock_phyport; wire [4:0] pll2_clock_cram, pll2_clock_cram_phy; // Write wire [3:0] pll2_clock_phyport_out, pll2_clock_phyport_out_logic; wire [3:0] pll2_clock_select_out_logic, pll2_clock_select_out; // READ reg [3:0] pll3_clock_index_to_phyport [0:9]; // map table - index to phyport integer wire [3:0] pll3_clock_select; wire [3:0] pll3_clock_phyport; wire [4:0] pll3_clock_cram, pll3_clock_cram_phy; // Write wire [3:0] pll3_clock_phyport_out, pll3_clock_phyport_out_logic; wire [3:0] pll3_clock_select_out_logic, pll3_clock_select_out; // READ reg [3:0] pll4_clock_index_to_phyport [0:9]; // map table - index to phyport integer wire [3:0] pll4_clock_select; wire [3:0] pll4_clock_phyport; wire [4:0] pll4_clock_cram, pll4_clock_cram_phy; // Write wire [3:0] pll4_clock_phyport_out, pll4_clock_phyport_out_logic; wire [3:0] pll4_clock_select_out_logic, pll4_clock_select_out; // READ reg [3:0] pll5_clock_index_to_phyport [0:9]; // map table - index to phyport integer wire [3:0] pll5_clock_select; wire [3:0] pll5_clock_phyport; wire [4:0] pll5_clock_cram, pll5_clock_cram_phy; // Write wire [3:0] pll5_clock_phyport_out, pll5_clock_phyport_out_logic; wire [3:0] pll5_clock_select_out_logic, pll5_clock_select_out; //------------------------------------------------------------------------- // TX PMA selection ------------------------------------------------------- //------------------------------------------------------------------------- `define TXPMA_CLKIN_SELECT_X1 0 `define TXPMA_CLKIN_SELECT_X4 1 `define TXPMA_CLKIN_SELECT_XN_TOP 2 `define TXPMA_CLKIN_SELECT_XN_BOTTOM 3 `define TXPMA_CLKIN_SELECT_HT 4 `define TXPMA_CLKIN_SELECT_ERR 7 function [2:0] convert_txpma_clock_cram_to_phyport; input [1:0] rcgb_x_en; reg [2:0] res; begin case (rcgb_x_en) 2'b00: res = `TXPMA_CLKIN_SELECT_X1; 2'b01: res = `TXPMA_CLKIN_SELECT_X4; 2'b10: res = `TXPMA_CLKIN_SELECT_XN_TOP; 2'b11: res = `TXPMA_CLKIN_SELECT_XN_BOTTOM; default: res = `TXPMA_CLKIN_SELECT_ERR; endcase convert_txpma_clock_cram_to_phyport = res; end endfunction // input is at most 20 characters function integer convert_txpma_phyport_str_to_phyport_enum; input phyport_str; reg [8*20:1] phyport_str; integer res; begin if (phyport_str == "x1" || phyport_str == "X1") res = `TXPMA_CLKIN_SELECT_X1; else if (phyport_str == "x4" || phyport_str == "X4") res = `TXPMA_CLKIN_SELECT_X4; else if (phyport_str == "xn_top" || phyport_str == "XN_TOP") res = `TXPMA_CLKIN_SELECT_XN_TOP; else if (phyport_str == "xn_bottom" || phyport_str == "XN_BOTTOM") res = `TXPMA_CLKIN_SELECT_XN_BOTTOM; else if (phyport_str == "hypertransport" || phyport_str == "HYPERTRANSPORT") res = `TXPMA_CLKIN_SELECT_HT; else // like "none" res = `TXPMA_CLKIN_SELECT_ERR; convert_txpma_phyport_str_to_phyport_enum = res; end endfunction // common to all channels reg [4:0] txpma_clock_phyport_to_cram [0:7]; // phyport to cram - include error string // READ --------------- ch0 reg [2:0] txpma0_clock_index_to_phyport [0:4]; // map table - index to phyport integer wire [2:0] txpma0_clock_select; wire [2:0] txpma0_clock_phyport; wire [4:0] txpma0_clock_cram, txpma0_clock_cram_phy; // Write --------------- ch0 wire [2:0] txpma0_clock_phyport_out, txpma0_clock_phyport_out_logic; wire [2:0] txpma0_clock_select_out_logic, txpma0_clock_select_out; // READ --------------- reg [2:0] txpma1_clock_index_to_phyport [0:4]; // map table - index to phyport integer wire [2:0] txpma1_clock_select; wire [2:0] txpma1_clock_phyport; wire [4:0] txpma1_clock_cram, txpma1_clock_cram_phy; // Write --------------- ch wire [2:0] txpma1_clock_phyport_out, txpma1_clock_phyport_out_logic; wire [2:0] txpma1_clock_select_out_logic, txpma1_clock_select_out; // READ --------------- ch reg [2:0] txpma2_clock_index_to_phyport [0:4]; // map table - index to phyport integer wire [2:0] txpma2_clock_select; wire [2:0] txpma2_clock_phyport; wire [4:0] txpma2_clock_cram, txpma2_clock_cram_phy; // Write --------------- ch wire [2:0] txpma2_clock_phyport_out, txpma2_clock_phyport_out_logic; wire [2:0] txpma2_clock_select_out_logic, txpma2_clock_select_out; // READ --------------- ch reg [2:0] txpma3_clock_index_to_phyport [0:4]; // map table - index to phyport integer wire [2:0] txpma3_clock_select; wire [2:0] txpma3_clock_phyport; wire [4:0] txpma3_clock_cram, txpma3_clock_cram_phy; // Write --------------- ch wire [2:0] txpma3_clock_phyport_out, txpma3_clock_phyport_out_logic; wire [2:0] txpma3_clock_select_out_logic, txpma3_clock_select_out; // READ --------------- ch reg [2:0] txpma4_clock_index_to_phyport [0:4]; // map table - index to phyport integer wire [2:0] txpma4_clock_select; wire [2:0] txpma4_clock_phyport; wire [4:0] txpma4_clock_cram, txpma4_clock_cram_phy; // Write --------------- ch wire [2:0] txpma4_clock_phyport_out, txpma4_clock_phyport_out_logic; wire [2:0] txpma4_clock_select_out_logic, txpma4_clock_select_out; // READ --------------- ch reg [2:0] txpma5_clock_index_to_phyport [0:4]; // map table - index to phyport integer wire [2:0] txpma5_clock_select; wire [2:0] txpma5_clock_phyport; wire [4:0] txpma5_clock_cram, txpma5_clock_cram_phy; // Write --------------- ch wire [2:0] txpma5_clock_phyport_out, txpma5_clock_phyport_out_logic; wire [2:0] txpma5_clock_select_out_logic, txpma5_clock_select_out; //------------------------------------------------------------------------- // PLL0/PLL1 selection ---------------------------------------------------- //------------------------------------------------------------------------- `define CLKDIV_INCLK_SELECT_PLL0 0 `define CLKDIV_INCLK_SELECT_PLL1 1 `define CLKDIV_INCLK_SELECT_ERR 2 function convert_clkdiv_pll_cram_to_phyport; input rcgb_cmu_sel; reg [1:0] res; begin case (rcgb_cmu_sel) 1'b0: res = `CLKDIV_INCLK_SELECT_PLL0; 1'b1: res = `CLKDIV_INCLK_SELECT_PLL1; default: res = `CLKDIV_INCLK_SELECT_ERR; endcase convert_clkdiv_pll_cram_to_phyport = res[0]; end endfunction // input is at most 10 characters function integer convert_clkdiv_pll_phyport_str_to_phyport_enum; input phyport_str; reg [8*10:1] phyport_str; integer res; begin if (phyport_str == "pll0") res = `CLKDIV_INCLK_SELECT_PLL0; else if (phyport_str == "pll1") res = `CLKDIV_INCLK_SELECT_PLL1; else // like "none" res = `CLKDIV_INCLK_SELECT_ERR; convert_clkdiv_pll_phyport_str_to_phyport_enum = res; end endfunction // common to all PLL channels reg clkdiv_pll_phyport_to_cram [0:2]; // phyport to cram - include error string // READ --------------- ch0 reg clkdiv0_pll_index_to_phyport [0:1]; // map table - index to phyport integer wire clkdiv0_pll_select; wire clkdiv0_pll_phyport; wire clkdiv0_pll_cram, clkdiv0_pll_cram_phy; // Write --------------- ch0 wire clkdiv0_pll_phyport_out, clkdiv0_pll_phyport_out_logic; wire clkdiv0_pll_select_out_logic, clkdiv0_pll_select_out; // READ --------------- ch1 reg clkdiv1_pll_index_to_phyport [0:1]; // map table - index to phyport integer wire clkdiv1_pll_select; wire clkdiv1_pll_phyport; wire clkdiv1_pll_cram, clkdiv1_pll_cram_phy; // Write --------------- ch1 wire clkdiv1_pll_phyport_out, clkdiv1_pll_phyport_out_logic; wire clkdiv1_pll_select_out_logic, clkdiv1_pll_select_out; // READ --------------- ch2 reg clkdiv2_pll_index_to_phyport [0:1]; // map table - index to phyport integer wire clkdiv2_pll_select; wire clkdiv2_pll_phyport; wire clkdiv2_pll_cram, clkdiv2_pll_cram_phy; // Write --------------- ch2 wire clkdiv2_pll_phyport_out, clkdiv2_pll_phyport_out_logic; wire clkdiv2_pll_select_out_logic, clkdiv2_pll_select_out; // READ --------------- ch3 reg clkdiv3_pll_index_to_phyport [0:1]; // map table - index to phyport integer wire clkdiv3_pll_select; wire clkdiv3_pll_phyport; wire clkdiv3_pll_cram, clkdiv3_pll_cram_phy; // Write --------------- ch3 wire clkdiv3_pll_phyport_out, clkdiv3_pll_phyport_out_logic; wire clkdiv3_pll_select_out_logic, clkdiv3_pll_select_out; // READ --------------- ch4 reg clkdiv4_pll_index_to_phyport [0:1]; // map table - index to phyport integer wire clkdiv4_pll_select; wire clkdiv4_pll_phyport; wire clkdiv4_pll_cram, clkdiv4_pll_cram_phy; // Write --------------- ch4 wire clkdiv4_pll_phyport_out, clkdiv4_pll_phyport_out_logic; wire clkdiv4_pll_select_out_logic, clkdiv4_pll_select_out; // READ --------------- ch5 reg clkdiv5_pll_index_to_phyport [0:1]; // map table - index to phyport integer wire clkdiv5_pll_select; wire clkdiv5_pll_phyport; wire clkdiv5_pll_cram, clkdiv5_pll_cram_phy; // Write --------------- ch5 wire clkdiv5_pll_phyport_out, clkdiv5_pll_phyport_out_logic; wire clkdiv5_pll_select_out_logic, clkdiv5_pll_select_out; //------------------------------------------------------------------------- // PLL clock selection ---------------------------------------------------- //------------------------------------------------------------------------- initial begin // rrefclk_sel, z, pldiq pll_clock_phyport_to_cram[`PLL_CLOCK_SELECT_IQ2] = 5'b10z00; pll_clock_phyport_to_cram[`PLL_CLOCK_SELECT_IQ3] = 5'b10z01; pll_clock_phyport_to_cram[`PLL_CLOCK_SELECT_IQ4] = 5'b10z10; pll_clock_phyport_to_cram[`PLL_CLOCK_SELECT_IQ5] = 5'b11z00; // skip pll_clock_phyport_to_cram[`PLL_CLOCK_SELECT_IQ6] = 5'b11z01; pll_clock_phyport_to_cram[`PLL_CLOCK_SELECT_IQ7] = 5'b11z10; pll_clock_phyport_to_cram[`PLL_CLOCK_SELECT_PLD_CLK] = 5'b10z11; pll_clock_phyport_to_cram[`PLL_CLOCK_SELECT_GPLL_CLK] = 5'b11z11; // iqsel below is donot care so take default for preventing X values passing around pll_clock_phyport_to_cram[`PLL_CLOCK_SELECT_CLKREFCLK0] = 5'b00z00; pll_clock_phyport_to_cram[`PLL_CLOCK_SELECT_CLKREFCLK1] = 5'b01z00; pll_clock_phyport_to_cram[`PLL_CLOCK_SELECT_ERR] = 5'b11111; end initial begin pll0_clock_index_to_phyport[0] = convert_pll_phyport_str_to_phyport_enum(pll0_inclk0_logical_to_physical_mapping); pll0_clock_index_to_phyport[1] = convert_pll_phyport_str_to_phyport_enum(pll0_inclk1_logical_to_physical_mapping); pll0_clock_index_to_phyport[2] = convert_pll_phyport_str_to_phyport_enum(pll0_inclk2_logical_to_physical_mapping); pll0_clock_index_to_phyport[3] = convert_pll_phyport_str_to_phyport_enum(pll0_inclk3_logical_to_physical_mapping); pll0_clock_index_to_phyport[4] = convert_pll_phyport_str_to_phyport_enum(pll0_inclk4_logical_to_physical_mapping); pll0_clock_index_to_phyport[5] = convert_pll_phyport_str_to_phyport_enum(pll0_inclk5_logical_to_physical_mapping); pll0_clock_index_to_phyport[6] = convert_pll_phyport_str_to_phyport_enum(pll0_inclk6_logical_to_physical_mapping); pll0_clock_index_to_phyport[7] = convert_pll_phyport_str_to_phyport_enum(pll0_inclk7_logical_to_physical_mapping); pll0_clock_index_to_phyport[8] = convert_pll_phyport_str_to_phyport_enum(pll0_inclk8_logical_to_physical_mapping); pll0_clock_index_to_phyport[9] = convert_pll_phyport_str_to_phyport_enum(pll0_inclk9_logical_to_physical_mapping); pll1_clock_index_to_phyport[0] = convert_pll_phyport_str_to_phyport_enum(pll1_inclk0_logical_to_physical_mapping); pll1_clock_index_to_phyport[1] = convert_pll_phyport_str_to_phyport_enum(pll1_inclk1_logical_to_physical_mapping); pll1_clock_index_to_phyport[2] = convert_pll_phyport_str_to_phyport_enum(pll1_inclk2_logical_to_physical_mapping); pll1_clock_index_to_phyport[3] = convert_pll_phyport_str_to_phyport_enum(pll1_inclk3_logical_to_physical_mapping); pll1_clock_index_to_phyport[4] = convert_pll_phyport_str_to_phyport_enum(pll1_inclk4_logical_to_physical_mapping); pll1_clock_index_to_phyport[5] = convert_pll_phyport_str_to_phyport_enum(pll1_inclk5_logical_to_physical_mapping); pll1_clock_index_to_phyport[6] = convert_pll_phyport_str_to_phyport_enum(pll1_inclk6_logical_to_physical_mapping); pll1_clock_index_to_phyport[7] = convert_pll_phyport_str_to_phyport_enum(pll1_inclk7_logical_to_physical_mapping); pll1_clock_index_to_phyport[8] = convert_pll_phyport_str_to_phyport_enum(pll1_inclk8_logical_to_physical_mapping); pll1_clock_index_to_phyport[9] = convert_pll_phyport_str_to_phyport_enum(pll1_inclk9_logical_to_physical_mapping); pll2_clock_index_to_phyport[0] = convert_pll_phyport_str_to_phyport_enum(pll2_inclk0_logical_to_physical_mapping); pll2_clock_index_to_phyport[1] = convert_pll_phyport_str_to_phyport_enum(pll2_inclk1_logical_to_physical_mapping); pll2_clock_index_to_phyport[2] = convert_pll_phyport_str_to_phyport_enum(pll2_inclk2_logical_to_physical_mapping); pll2_clock_index_to_phyport[3] = convert_pll_phyport_str_to_phyport_enum(pll2_inclk3_logical_to_physical_mapping); pll2_clock_index_to_phyport[4] = convert_pll_phyport_str_to_phyport_enum(pll2_inclk4_logical_to_physical_mapping); pll2_clock_index_to_phyport[5] = convert_pll_phyport_str_to_phyport_enum(pll2_inclk5_logical_to_physical_mapping); pll2_clock_index_to_phyport[6] = convert_pll_phyport_str_to_phyport_enum(pll2_inclk6_logical_to_physical_mapping); pll2_clock_index_to_phyport[7] = convert_pll_phyport_str_to_phyport_enum(pll2_inclk7_logical_to_physical_mapping); pll2_clock_index_to_phyport[8] = convert_pll_phyport_str_to_phyport_enum(pll2_inclk8_logical_to_physical_mapping); pll2_clock_index_to_phyport[9] = convert_pll_phyport_str_to_phyport_enum(pll2_inclk9_logical_to_physical_mapping); pll3_clock_index_to_phyport[0] = convert_pll_phyport_str_to_phyport_enum(pll3_inclk0_logical_to_physical_mapping); pll3_clock_index_to_phyport[1] = convert_pll_phyport_str_to_phyport_enum(pll3_inclk1_logical_to_physical_mapping); pll3_clock_index_to_phyport[2] = convert_pll_phyport_str_to_phyport_enum(pll3_inclk2_logical_to_physical_mapping); pll3_clock_index_to_phyport[3] = convert_pll_phyport_str_to_phyport_enum(pll3_inclk3_logical_to_physical_mapping); pll3_clock_index_to_phyport[4] = convert_pll_phyport_str_to_phyport_enum(pll3_inclk4_logical_to_physical_mapping); pll3_clock_index_to_phyport[5] = convert_pll_phyport_str_to_phyport_enum(pll3_inclk5_logical_to_physical_mapping); pll3_clock_index_to_phyport[6] = convert_pll_phyport_str_to_phyport_enum(pll3_inclk6_logical_to_physical_mapping); pll3_clock_index_to_phyport[7] = convert_pll_phyport_str_to_phyport_enum(pll3_inclk7_logical_to_physical_mapping); pll3_clock_index_to_phyport[8] = convert_pll_phyport_str_to_phyport_enum(pll3_inclk8_logical_to_physical_mapping); pll3_clock_index_to_phyport[9] = convert_pll_phyport_str_to_phyport_enum(pll3_inclk9_logical_to_physical_mapping); pll4_clock_index_to_phyport[0] = convert_pll_phyport_str_to_phyport_enum(pll4_inclk0_logical_to_physical_mapping); pll4_clock_index_to_phyport[1] = convert_pll_phyport_str_to_phyport_enum(pll4_inclk1_logical_to_physical_mapping); pll4_clock_index_to_phyport[2] = convert_pll_phyport_str_to_phyport_enum(pll4_inclk2_logical_to_physical_mapping); pll4_clock_index_to_phyport[3] = convert_pll_phyport_str_to_phyport_enum(pll4_inclk3_logical_to_physical_mapping); pll4_clock_index_to_phyport[4] = convert_pll_phyport_str_to_phyport_enum(pll4_inclk4_logical_to_physical_mapping); pll4_clock_index_to_phyport[5] = convert_pll_phyport_str_to_phyport_enum(pll4_inclk5_logical_to_physical_mapping); pll4_clock_index_to_phyport[6] = convert_pll_phyport_str_to_phyport_enum(pll4_inclk6_logical_to_physical_mapping); pll4_clock_index_to_phyport[7] = convert_pll_phyport_str_to_phyport_enum(pll4_inclk7_logical_to_physical_mapping); pll4_clock_index_to_phyport[8] = convert_pll_phyport_str_to_phyport_enum(pll4_inclk8_logical_to_physical_mapping); pll4_clock_index_to_phyport[9] = convert_pll_phyport_str_to_phyport_enum(pll4_inclk9_logical_to_physical_mapping); pll5_clock_index_to_phyport[0] = convert_pll_phyport_str_to_phyport_enum(pll5_inclk0_logical_to_physical_mapping); pll5_clock_index_to_phyport[1] = convert_pll_phyport_str_to_phyport_enum(pll5_inclk1_logical_to_physical_mapping); pll5_clock_index_to_phyport[2] = convert_pll_phyport_str_to_phyport_enum(pll5_inclk2_logical_to_physical_mapping); pll5_clock_index_to_phyport[3] = convert_pll_phyport_str_to_phyport_enum(pll5_inclk3_logical_to_physical_mapping); pll5_clock_index_to_phyport[4] = convert_pll_phyport_str_to_phyport_enum(pll5_inclk4_logical_to_physical_mapping); pll5_clock_index_to_phyport[5] = convert_pll_phyport_str_to_phyport_enum(pll5_inclk5_logical_to_physical_mapping); pll5_clock_index_to_phyport[6] = convert_pll_phyport_str_to_phyport_enum(pll5_inclk6_logical_to_physical_mapping); pll5_clock_index_to_phyport[7] = convert_pll_phyport_str_to_phyport_enum(pll5_inclk7_logical_to_physical_mapping); pll5_clock_index_to_phyport[8] = convert_pll_phyport_str_to_phyport_enum(pll5_inclk8_logical_to_physical_mapping); pll5_clock_index_to_phyport[9] = convert_pll_phyport_str_to_phyport_enum(pll5_inclk9_logical_to_physical_mapping); end // DPRIO read - logical pll channel assign pll0_clock_select = pll0_init_pfd_clk_sel; assign pll0_clock_phyport = (pll0_clock_select == 0) ? pll0_clock_index_to_phyport[0] : (pll0_clock_select == 1) ? pll0_clock_index_to_phyport[1] : (pll0_clock_select == 2) ? pll0_clock_index_to_phyport[2] : (pll0_clock_select == 3) ? pll0_clock_index_to_phyport[3] : (pll0_clock_select == 4) ? pll0_clock_index_to_phyport[4] : (pll0_clock_select == 5) ? pll0_clock_index_to_phyport[5] : (pll0_clock_select == 6) ? pll0_clock_index_to_phyport[6] : (pll0_clock_select == 7) ? pll0_clock_index_to_phyport[7] : (pll0_clock_select == 8) ? pll0_clock_index_to_phyport[8] : (pll0_clock_select == 9) ? pll0_clock_index_to_phyport[9] : pll0_clock_index_to_phyport[0]; assign pll0_clock_cram = (pll0_clock_phyport == 0) ? pll_clock_phyport_to_cram[0] : (pll0_clock_phyport == 1) ? pll_clock_phyport_to_cram[1] : (pll0_clock_phyport == 2) ? pll_clock_phyport_to_cram[2] : (pll0_clock_phyport == 3) ? pll_clock_phyport_to_cram[3] : (pll0_clock_phyport == 4) ? pll_clock_phyport_to_cram[4] : (pll0_clock_phyport == 5) ? pll_clock_phyport_to_cram[5] : (pll0_clock_phyport == 6) ? pll_clock_phyport_to_cram[6] : (pll0_clock_phyport == 7) ? pll_clock_phyport_to_cram[7] : (pll0_clock_phyport == 8) ? pll_clock_phyport_to_cram[8] : (pll0_clock_phyport == 9) ? pll_clock_phyport_to_cram[9] : (pll0_clock_phyport == 10) ? pll_clock_phyport_to_cram[10] : pll_clock_phyport_to_cram[0]; // switch to physical pll number assign pll0_clock_cram_phy = (pll0_logical_to_physical_mapping == 0) ? pll0_clock_cram : (pll1_logical_to_physical_mapping == 0) ? pll1_clock_cram : (pll2_logical_to_physical_mapping == 0) ? pll2_clock_cram : (pll3_logical_to_physical_mapping == 0) ? pll3_clock_cram : (pll4_logical_to_physical_mapping == 0) ? pll4_clock_cram : (pll5_logical_to_physical_mapping == 0) ? pll5_clock_cram : pll0_clock_cram; assign pll0_csr_riqclk_sel = pll0_clock_cram_phy[1:0]; assign pll0_csr_rrefclk_sel = pll0_clock_cram_phy[4:3]; // DPRIO write - CRAM on physical assign pll0_clock_phyport_out = convert_pll_clock_cram_to_phyport(pll0_dp_rrefclk_sel, pll0_dp_riqclk_sel); // but the map is on logic channel assign pll0_clock_phyport_out_logic = (pll0_logical_to_physical_mapping == 0) ? pll0_clock_phyport_out : (pll0_logical_to_physical_mapping == 1) ? pll1_clock_phyport_out : (pll0_logical_to_physical_mapping == 2) ? pll2_clock_phyport_out : (pll0_logical_to_physical_mapping == 3) ? pll3_clock_phyport_out : (pll0_logical_to_physical_mapping == 4) ? pll4_clock_phyport_out : (pll0_logical_to_physical_mapping == 5) ? pll5_clock_phyport_out : pll0_clock_phyport_out; assign pll0_clock_select_out_logic = (pll0_clock_index_to_phyport[0] === pll0_clock_phyport_out_logic) ? 4'b0000 : (pll0_clock_index_to_phyport[1] === pll0_clock_phyport_out_logic) ? 4'b0001 : (pll0_clock_index_to_phyport[2] === pll0_clock_phyport_out_logic) ? 4'b0010 : (pll0_clock_index_to_phyport[3] === pll0_clock_phyport_out_logic) ? 4'b0011 : (pll0_clock_index_to_phyport[4] === pll0_clock_phyport_out_logic) ? 4'b0100 : (pll0_clock_index_to_phyport[5] === pll0_clock_phyport_out_logic) ? 4'b0101 : (pll0_clock_index_to_phyport[6] === pll0_clock_phyport_out_logic) ? 4'b0110 : (pll0_clock_index_to_phyport[7] === pll0_clock_phyport_out_logic) ? 4'b0111 : (pll0_clock_index_to_phyport[8] === pll0_clock_phyport_out_logic) ? 4'b1000 : (pll0_clock_index_to_phyport[9] === pll0_clock_phyport_out_logic) ? 4'b1001 : 4'b1111; // invalid cram values // back to physical assign pll0_clock_select_out = (pll0_logical_to_physical_mapping == 0) ? pll0_clock_select_out_logic : (pll1_logical_to_physical_mapping == 0) ? pll1_clock_select_out_logic : (pll2_logical_to_physical_mapping == 0) ? pll2_clock_select_out_logic : (pll3_logical_to_physical_mapping == 0) ? pll3_clock_select_out_logic : (pll4_logical_to_physical_mapping == 0) ? pll4_clock_select_out_logic : (pll5_logical_to_physical_mapping == 0) ? pll5_clock_select_out_logic : pll0_clock_select_out_logic; assign pll0_dp_pfd_clk_sel = pll0_clock_select_out; // DPRIO read - physical pll channel assign pll1_clock_select = pll1_init_pfd_clk_sel; assign pll1_clock_phyport = (pll1_clock_select == 0) ? pll1_clock_index_to_phyport[0] : (pll1_clock_select == 1) ? pll1_clock_index_to_phyport[1] : (pll1_clock_select == 2) ? pll1_clock_index_to_phyport[2] : (pll1_clock_select == 3) ? pll1_clock_index_to_phyport[3] : (pll1_clock_select == 4) ? pll1_clock_index_to_phyport[4] : (pll1_clock_select == 5) ? pll1_clock_index_to_phyport[5] : (pll1_clock_select == 6) ? pll1_clock_index_to_phyport[6] : (pll1_clock_select == 7) ? pll1_clock_index_to_phyport[7] : (pll1_clock_select == 8) ? pll1_clock_index_to_phyport[8] : (pll1_clock_select == 9) ? pll1_clock_index_to_phyport[9] : pll1_clock_index_to_phyport[0]; assign pll1_clock_cram = (pll1_clock_phyport == 0) ? pll_clock_phyport_to_cram[0] : (pll1_clock_phyport == 1) ? pll_clock_phyport_to_cram[1] : (pll1_clock_phyport == 2) ? pll_clock_phyport_to_cram[2] : (pll1_clock_phyport == 3) ? pll_clock_phyport_to_cram[3] : (pll1_clock_phyport == 4) ? pll_clock_phyport_to_cram[4] : (pll1_clock_phyport == 5) ? pll_clock_phyport_to_cram[5] : (pll1_clock_phyport == 6) ? pll_clock_phyport_to_cram[6] : (pll1_clock_phyport == 7) ? pll_clock_phyport_to_cram[7] : (pll1_clock_phyport == 8) ? pll_clock_phyport_to_cram[8] : (pll1_clock_phyport == 9) ? pll_clock_phyport_to_cram[9] : (pll1_clock_phyport == 10) ? pll_clock_phyport_to_cram[10] : pll_clock_phyport_to_cram[0]; // switch to physical pll number assign pll1_clock_cram_phy = (pll0_logical_to_physical_mapping == 1) ? pll0_clock_cram : (pll1_logical_to_physical_mapping == 1) ? pll1_clock_cram : (pll2_logical_to_physical_mapping == 1) ? pll2_clock_cram : (pll3_logical_to_physical_mapping == 1) ? pll3_clock_cram : (pll4_logical_to_physical_mapping == 1) ? pll4_clock_cram : (pll5_logical_to_physical_mapping == 1) ? pll5_clock_cram : pll1_clock_cram; assign pll1_csr_riqclk_sel = pll1_clock_cram_phy[1:0]; assign pll1_csr_rrefclk_sel = pll1_clock_cram_phy[4:3]; // DPRIO write - CRAM on physical assign pll1_clock_phyport_out = convert_pll_clock_cram_to_phyport(pll1_dp_rrefclk_sel, pll1_dp_riqclk_sel); // but the map is on logic channel assign pll1_clock_phyport_out_logic = (pll1_logical_to_physical_mapping == 0) ? pll0_clock_phyport_out : (pll1_logical_to_physical_mapping == 1) ? pll1_clock_phyport_out : (pll1_logical_to_physical_mapping == 2) ? pll2_clock_phyport_out : (pll1_logical_to_physical_mapping == 3) ? pll3_clock_phyport_out : (pll1_logical_to_physical_mapping == 4) ? pll4_clock_phyport_out : (pll1_logical_to_physical_mapping == 5) ? pll5_clock_phyport_out : pll1_clock_phyport_out; assign pll1_clock_select_out_logic = (pll1_clock_index_to_phyport[0] === pll1_clock_phyport_out_logic) ? 4'b0000 : (pll1_clock_index_to_phyport[1] === pll1_clock_phyport_out_logic) ? 4'b0001 : (pll1_clock_index_to_phyport[2] === pll1_clock_phyport_out_logic) ? 4'b0010 : (pll1_clock_index_to_phyport[3] === pll1_clock_phyport_out_logic) ? 4'b0011 : (pll1_clock_index_to_phyport[4] === pll1_clock_phyport_out_logic) ? 4'b0100 : (pll1_clock_index_to_phyport[5] === pll1_clock_phyport_out_logic) ? 4'b0101 : (pll1_clock_index_to_phyport[6] === pll1_clock_phyport_out_logic) ? 4'b0110 : (pll1_clock_index_to_phyport[7] === pll1_clock_phyport_out_logic) ? 4'b0111 : (pll1_clock_index_to_phyport[8] === pll1_clock_phyport_out_logic) ? 4'b1000 : (pll1_clock_index_to_phyport[9] === pll1_clock_phyport_out_logic) ? 4'b1001 : 4'b1111; // invalid cram values // back to physical assign pll1_clock_select_out = (pll0_logical_to_physical_mapping == 1) ? pll0_clock_select_out_logic : (pll1_logical_to_physical_mapping == 1) ? pll1_clock_select_out_logic : (pll2_logical_to_physical_mapping == 1) ? pll2_clock_select_out_logic : (pll3_logical_to_physical_mapping == 1) ? pll3_clock_select_out_logic : (pll4_logical_to_physical_mapping == 1) ? pll4_clock_select_out_logic : (pll5_logical_to_physical_mapping == 1) ? pll5_clock_select_out_logic : pll1_clock_select_out_logic; assign pll1_dp_pfd_clk_sel = pll1_clock_select_out; // DPRIO read - physical pll channel assign pll2_clock_select = pll2_init_pfd_clk_sel; assign pll2_clock_phyport = (pll2_clock_select == 0) ? pll2_clock_index_to_phyport[0] : (pll2_clock_select == 1) ? pll2_clock_index_to_phyport[1] : (pll2_clock_select == 2) ? pll2_clock_index_to_phyport[2] : (pll2_clock_select == 3) ? pll2_clock_index_to_phyport[3] : (pll2_clock_select == 4) ? pll2_clock_index_to_phyport[4] : (pll2_clock_select == 5) ? pll2_clock_index_to_phyport[5] : (pll2_clock_select == 6) ? pll2_clock_index_to_phyport[6] : (pll2_clock_select == 7) ? pll2_clock_index_to_phyport[7] : (pll2_clock_select == 8) ? pll2_clock_index_to_phyport[8] : (pll2_clock_select == 9) ? pll2_clock_index_to_phyport[9] : pll2_clock_index_to_phyport[0]; assign pll2_clock_cram = (pll2_clock_phyport == 0) ? pll_clock_phyport_to_cram[0] : (pll2_clock_phyport == 1) ? pll_clock_phyport_to_cram[1] : (pll2_clock_phyport == 2) ? pll_clock_phyport_to_cram[2] : (pll2_clock_phyport == 3) ? pll_clock_phyport_to_cram[3] : (pll2_clock_phyport == 4) ? pll_clock_phyport_to_cram[4] : (pll2_clock_phyport == 5) ? pll_clock_phyport_to_cram[5] : (pll2_clock_phyport == 6) ? pll_clock_phyport_to_cram[6] : (pll2_clock_phyport == 7) ? pll_clock_phyport_to_cram[7] : (pll2_clock_phyport == 8) ? pll_clock_phyport_to_cram[8] : (pll2_clock_phyport == 9) ? pll_clock_phyport_to_cram[9] : (pll2_clock_phyport == 10) ? pll_clock_phyport_to_cram[10] : pll_clock_phyport_to_cram[0]; // switch to physical pll number assign pll2_clock_cram_phy = (pll0_logical_to_physical_mapping == 2) ? pll0_clock_cram : (pll1_logical_to_physical_mapping == 2) ? pll1_clock_cram : (pll2_logical_to_physical_mapping == 2) ? pll2_clock_cram : (pll3_logical_to_physical_mapping == 2) ? pll3_clock_cram : (pll4_logical_to_physical_mapping == 2) ? pll4_clock_cram : (pll5_logical_to_physical_mapping == 2) ? pll5_clock_cram : pll2_clock_cram; assign pll2_csr_riqclk_sel = pll2_clock_cram_phy[1:0]; assign pll2_csr_rrefclk_sel = pll2_clock_cram_phy[4:3]; // DPRIO write - CRAM on physical assign pll2_clock_phyport_out = convert_pll_clock_cram_to_phyport(pll2_dp_rrefclk_sel, pll2_dp_riqclk_sel); // but the map is on logic channel assign pll2_clock_phyport_out_logic = (pll2_logical_to_physical_mapping == 0) ? pll0_clock_phyport_out : (pll2_logical_to_physical_mapping == 1) ? pll1_clock_phyport_out : (pll2_logical_to_physical_mapping == 2) ? pll2_clock_phyport_out : (pll2_logical_to_physical_mapping == 3) ? pll3_clock_phyport_out : (pll2_logical_to_physical_mapping == 4) ? pll4_clock_phyport_out : (pll2_logical_to_physical_mapping == 5) ? pll5_clock_phyport_out : pll2_clock_phyport_out; assign pll2_clock_select_out_logic = (pll2_clock_index_to_phyport[0] === pll2_clock_phyport_out_logic) ? 4'b0000 : (pll2_clock_index_to_phyport[1] === pll2_clock_phyport_out_logic) ? 4'b0001 : (pll2_clock_index_to_phyport[2] === pll2_clock_phyport_out_logic) ? 4'b0010 : (pll2_clock_index_to_phyport[3] === pll2_clock_phyport_out_logic) ? 4'b0011 : (pll2_clock_index_to_phyport[4] === pll2_clock_phyport_out_logic) ? 4'b0100 : (pll2_clock_index_to_phyport[5] === pll2_clock_phyport_out_logic) ? 4'b0101 : (pll2_clock_index_to_phyport[6] === pll2_clock_phyport_out_logic) ? 4'b0110 : (pll2_clock_index_to_phyport[7] === pll2_clock_phyport_out_logic) ? 4'b0111 : (pll2_clock_index_to_phyport[8] === pll2_clock_phyport_out_logic) ? 4'b1000 : (pll2_clock_index_to_phyport[9] === pll2_clock_phyport_out_logic) ? 4'b1001 : 4'b1111; // invalid cram values // back to physical assign pll2_clock_select_out = (pll0_logical_to_physical_mapping == 2) ? pll0_clock_select_out_logic : (pll1_logical_to_physical_mapping == 2) ? pll1_clock_select_out_logic : (pll2_logical_to_physical_mapping == 2) ? pll2_clock_select_out_logic : (pll3_logical_to_physical_mapping == 2) ? pll3_clock_select_out_logic : (pll4_logical_to_physical_mapping == 2) ? pll4_clock_select_out_logic : (pll5_logical_to_physical_mapping == 2) ? pll5_clock_select_out_logic : pll2_clock_select_out_logic; assign pll2_dp_pfd_clk_sel = pll2_clock_select_out; // DPRIO read - physical pll channel assign pll3_clock_select = pll3_init_pfd_clk_sel; assign pll3_clock_phyport = (pll3_clock_select == 0) ? pll3_clock_index_to_phyport[0] : (pll3_clock_select == 1) ? pll3_clock_index_to_phyport[1] : (pll3_clock_select == 2) ? pll3_clock_index_to_phyport[2] : (pll3_clock_select == 3) ? pll3_clock_index_to_phyport[3] : (pll3_clock_select == 4) ? pll3_clock_index_to_phyport[4] : (pll3_clock_select == 5) ? pll3_clock_index_to_phyport[5] : (pll3_clock_select == 6) ? pll3_clock_index_to_phyport[6] : (pll3_clock_select == 7) ? pll3_clock_index_to_phyport[7] : (pll3_clock_select == 8) ? pll3_clock_index_to_phyport[8] : (pll3_clock_select == 9) ? pll3_clock_index_to_phyport[9] : pll3_clock_index_to_phyport[0]; assign pll3_clock_cram = (pll3_clock_phyport == 0) ? pll_clock_phyport_to_cram[0] : (pll3_clock_phyport == 1) ? pll_clock_phyport_to_cram[1] : (pll3_clock_phyport == 2) ? pll_clock_phyport_to_cram[2] : (pll3_clock_phyport == 3) ? pll_clock_phyport_to_cram[3] : (pll3_clock_phyport == 4) ? pll_clock_phyport_to_cram[4] : (pll3_clock_phyport == 5) ? pll_clock_phyport_to_cram[5] : (pll3_clock_phyport == 6) ? pll_clock_phyport_to_cram[6] : (pll3_clock_phyport == 7) ? pll_clock_phyport_to_cram[7] : (pll3_clock_phyport == 8) ? pll_clock_phyport_to_cram[8] : (pll3_clock_phyport == 9) ? pll_clock_phyport_to_cram[9] : (pll3_clock_phyport == 10) ? pll_clock_phyport_to_cram[10] : pll_clock_phyport_to_cram[0]; // switch to physical pll number assign pll3_clock_cram_phy = (pll0_logical_to_physical_mapping == 3) ? pll0_clock_cram : (pll1_logical_to_physical_mapping == 3) ? pll1_clock_cram : (pll2_logical_to_physical_mapping == 3) ? pll2_clock_cram : (pll3_logical_to_physical_mapping == 3) ? pll3_clock_cram : (pll4_logical_to_physical_mapping == 3) ? pll4_clock_cram : (pll5_logical_to_physical_mapping == 3) ? pll5_clock_cram : pll3_clock_cram; assign pll3_csr_riqclk_sel = pll3_clock_cram_phy[1:0]; assign pll3_csr_rrefclk_sel = pll3_clock_cram_phy[4:3]; // DPRIO write - CRAM on physical assign pll3_clock_phyport_out = convert_pll_clock_cram_to_phyport(pll3_dp_rrefclk_sel, pll3_dp_riqclk_sel); // but the map is on logic channel assign pll3_clock_phyport_out_logic = (pll3_logical_to_physical_mapping == 0) ? pll0_clock_phyport_out : (pll3_logical_to_physical_mapping == 1) ? pll1_clock_phyport_out : (pll3_logical_to_physical_mapping == 2) ? pll2_clock_phyport_out : (pll3_logical_to_physical_mapping == 3) ? pll3_clock_phyport_out : (pll3_logical_to_physical_mapping == 4) ? pll4_clock_phyport_out : (pll3_logical_to_physical_mapping == 5) ? pll5_clock_phyport_out : pll3_clock_phyport_out; assign pll3_clock_select_out_logic = (pll3_clock_index_to_phyport[0] === pll3_clock_phyport_out_logic) ? 4'b0000 : (pll3_clock_index_to_phyport[1] === pll3_clock_phyport_out_logic) ? 4'b0001 : (pll3_clock_index_to_phyport[2] === pll3_clock_phyport_out_logic) ? 4'b0010 : (pll3_clock_index_to_phyport[3] === pll3_clock_phyport_out_logic) ? 4'b0011 : (pll3_clock_index_to_phyport[4] === pll3_clock_phyport_out_logic) ? 4'b0100 : (pll3_clock_index_to_phyport[5] === pll3_clock_phyport_out_logic) ? 4'b0101 : (pll3_clock_index_to_phyport[6] === pll3_clock_phyport_out_logic) ? 4'b0110 : (pll3_clock_index_to_phyport[7] === pll3_clock_phyport_out_logic) ? 4'b0111 : (pll3_clock_index_to_phyport[8] === pll3_clock_phyport_out_logic) ? 4'b1000 : (pll3_clock_index_to_phyport[9] === pll3_clock_phyport_out_logic) ? 4'b1001 : 4'b1111; // invalid cram values // back to physical assign pll3_clock_select_out = (pll0_logical_to_physical_mapping == 3) ? pll0_clock_select_out_logic : (pll1_logical_to_physical_mapping == 3) ? pll1_clock_select_out_logic : (pll2_logical_to_physical_mapping == 3) ? pll2_clock_select_out_logic : (pll3_logical_to_physical_mapping == 3) ? pll3_clock_select_out_logic : (pll4_logical_to_physical_mapping == 3) ? pll4_clock_select_out_logic : (pll5_logical_to_physical_mapping == 3) ? pll5_clock_select_out_logic : pll3_clock_select_out_logic; assign pll3_dp_pfd_clk_sel = pll3_clock_select_out; // DPRIO read - physical pll channel assign pll4_clock_select = pll4_init_pfd_clk_sel; assign pll4_clock_phyport = (pll4_clock_select == 0) ? pll4_clock_index_to_phyport[0] : (pll4_clock_select == 1) ? pll4_clock_index_to_phyport[1] : (pll4_clock_select == 2) ? pll4_clock_index_to_phyport[2] : (pll4_clock_select == 3) ? pll4_clock_index_to_phyport[3] : (pll4_clock_select == 4) ? pll4_clock_index_to_phyport[4] : (pll4_clock_select == 5) ? pll4_clock_index_to_phyport[5] : (pll4_clock_select == 6) ? pll4_clock_index_to_phyport[6] : (pll4_clock_select == 7) ? pll4_clock_index_to_phyport[7] : (pll4_clock_select == 8) ? pll4_clock_index_to_phyport[8] : (pll4_clock_select == 9) ? pll4_clock_index_to_phyport[9] : pll4_clock_index_to_phyport[0]; assign pll4_clock_cram = (pll4_clock_phyport == 0) ? pll_clock_phyport_to_cram[0] : (pll4_clock_phyport == 1) ? pll_clock_phyport_to_cram[1] : (pll4_clock_phyport == 2) ? pll_clock_phyport_to_cram[2] : (pll4_clock_phyport == 3) ? pll_clock_phyport_to_cram[3] : (pll4_clock_phyport == 4) ? pll_clock_phyport_to_cram[4] : (pll4_clock_phyport == 5) ? pll_clock_phyport_to_cram[5] : (pll4_clock_phyport == 6) ? pll_clock_phyport_to_cram[6] : (pll4_clock_phyport == 7) ? pll_clock_phyport_to_cram[7] : (pll4_clock_phyport == 8) ? pll_clock_phyport_to_cram[8] : (pll4_clock_phyport == 9) ? pll_clock_phyport_to_cram[9] : (pll4_clock_phyport == 10) ? pll_clock_phyport_to_cram[10] : pll_clock_phyport_to_cram[0]; // switch to physical pll number assign pll4_clock_cram_phy = (pll0_logical_to_physical_mapping == 4) ? pll0_clock_cram : (pll1_logical_to_physical_mapping == 4) ? pll1_clock_cram : (pll2_logical_to_physical_mapping == 4) ? pll2_clock_cram : (pll3_logical_to_physical_mapping == 4) ? pll3_clock_cram : (pll4_logical_to_physical_mapping == 4) ? pll4_clock_cram : (pll5_logical_to_physical_mapping == 4) ? pll5_clock_cram : pll4_clock_cram; assign pll4_csr_riqclk_sel = pll4_clock_cram_phy[1:0]; assign pll4_csr_rrefclk_sel = pll4_clock_cram_phy[4:3]; // DPRIO write - CRAM on physical assign pll4_clock_phyport_out = convert_pll_clock_cram_to_phyport(pll4_dp_rrefclk_sel, pll4_dp_riqclk_sel); // but the map is on logic channel assign pll4_clock_phyport_out_logic = (pll4_logical_to_physical_mapping == 0) ? pll0_clock_phyport_out : (pll4_logical_to_physical_mapping == 1) ? pll1_clock_phyport_out : (pll4_logical_to_physical_mapping == 2) ? pll2_clock_phyport_out : (pll4_logical_to_physical_mapping == 3) ? pll3_clock_phyport_out : (pll4_logical_to_physical_mapping == 4) ? pll4_clock_phyport_out : (pll4_logical_to_physical_mapping == 5) ? pll5_clock_phyport_out : pll4_clock_phyport_out; assign pll4_clock_select_out_logic = (pll4_clock_index_to_phyport[0] === pll4_clock_phyport_out_logic) ? 4'b0000 : (pll4_clock_index_to_phyport[1] === pll4_clock_phyport_out_logic) ? 4'b0001 : (pll4_clock_index_to_phyport[2] === pll4_clock_phyport_out_logic) ? 4'b0010 : (pll4_clock_index_to_phyport[3] === pll4_clock_phyport_out_logic) ? 4'b0011 : (pll4_clock_index_to_phyport[4] === pll4_clock_phyport_out_logic) ? 4'b0100 : (pll4_clock_index_to_phyport[5] === pll4_clock_phyport_out_logic) ? 4'b0101 : (pll4_clock_index_to_phyport[6] === pll4_clock_phyport_out_logic) ? 4'b0110 : (pll4_clock_index_to_phyport[7] === pll4_clock_phyport_out_logic) ? 4'b0111 : (pll4_clock_index_to_phyport[8] === pll4_clock_phyport_out_logic) ? 4'b1000 : (pll4_clock_index_to_phyport[9] === pll4_clock_phyport_out_logic) ? 4'b1001 : 4'b1111; // invalid cram values // back to physical assign pll4_clock_select_out = (pll0_logical_to_physical_mapping == 4) ? pll0_clock_select_out_logic : (pll1_logical_to_physical_mapping == 4) ? pll1_clock_select_out_logic : (pll2_logical_to_physical_mapping == 4) ? pll2_clock_select_out_logic : (pll3_logical_to_physical_mapping == 4) ? pll3_clock_select_out_logic : (pll4_logical_to_physical_mapping == 4) ? pll4_clock_select_out_logic : (pll5_logical_to_physical_mapping == 4) ? pll5_clock_select_out_logic : pll4_clock_select_out_logic; assign pll4_dp_pfd_clk_sel = pll4_clock_select_out; // DPRIO read - physical pll channel assign pll5_clock_select = pll5_init_pfd_clk_sel; assign pll5_clock_phyport = (pll5_clock_select == 0) ? pll5_clock_index_to_phyport[0] : (pll5_clock_select == 1) ? pll5_clock_index_to_phyport[1] : (pll5_clock_select == 2) ? pll5_clock_index_to_phyport[2] : (pll5_clock_select == 3) ? pll5_clock_index_to_phyport[3] : (pll5_clock_select == 4) ? pll5_clock_index_to_phyport[4] : (pll5_clock_select == 5) ? pll5_clock_index_to_phyport[5] : (pll5_clock_select == 6) ? pll5_clock_index_to_phyport[6] : (pll5_clock_select == 7) ? pll5_clock_index_to_phyport[7] : (pll5_clock_select == 8) ? pll5_clock_index_to_phyport[8] : (pll5_clock_select == 9) ? pll5_clock_index_to_phyport[9] : pll5_clock_index_to_phyport[0]; assign pll5_clock_cram = (pll5_clock_phyport == 0) ? pll_clock_phyport_to_cram[0] : (pll5_clock_phyport == 1) ? pll_clock_phyport_to_cram[1] : (pll5_clock_phyport == 2) ? pll_clock_phyport_to_cram[2] : (pll5_clock_phyport == 3) ? pll_clock_phyport_to_cram[3] : (pll5_clock_phyport == 4) ? pll_clock_phyport_to_cram[4] : (pll5_clock_phyport == 5) ? pll_clock_phyport_to_cram[5] : (pll5_clock_phyport == 6) ? pll_clock_phyport_to_cram[6] : (pll5_clock_phyport == 7) ? pll_clock_phyport_to_cram[7] : (pll5_clock_phyport == 8) ? pll_clock_phyport_to_cram[8] : (pll5_clock_phyport == 9) ? pll_clock_phyport_to_cram[9] : (pll5_clock_phyport == 10) ? pll_clock_phyport_to_cram[10] : pll_clock_phyport_to_cram[0]; // switch to physical pll number assign pll5_clock_cram_phy = (pll0_logical_to_physical_mapping == 5) ? pll0_clock_cram : (pll1_logical_to_physical_mapping == 5) ? pll1_clock_cram : (pll2_logical_to_physical_mapping == 5) ? pll2_clock_cram : (pll3_logical_to_physical_mapping == 5) ? pll3_clock_cram : (pll4_logical_to_physical_mapping == 5) ? pll4_clock_cram : (pll5_logical_to_physical_mapping == 5) ? pll5_clock_cram : pll5_clock_cram; assign pll5_csr_riqclk_sel = pll5_clock_cram_phy[1:0]; assign pll5_csr_rrefclk_sel = pll5_clock_cram_phy[4:3]; // DPRIO write - CRAM on physical assign pll5_clock_phyport_out = convert_pll_clock_cram_to_phyport(pll5_dp_rrefclk_sel, pll5_dp_riqclk_sel); // but the map is on logic channel assign pll5_clock_phyport_out_logic = (pll5_logical_to_physical_mapping == 0) ? pll0_clock_phyport_out : (pll5_logical_to_physical_mapping == 1) ? pll1_clock_phyport_out : (pll5_logical_to_physical_mapping == 2) ? pll2_clock_phyport_out : (pll5_logical_to_physical_mapping == 3) ? pll3_clock_phyport_out : (pll5_logical_to_physical_mapping == 4) ? pll4_clock_phyport_out : (pll5_logical_to_physical_mapping == 5) ? pll5_clock_phyport_out : pll5_clock_phyport_out; assign pll5_clock_select_out_logic = (pll5_clock_index_to_phyport[0] === pll5_clock_phyport_out_logic) ? 4'b0000 : (pll5_clock_index_to_phyport[1] === pll5_clock_phyport_out_logic) ? 4'b0001 : (pll5_clock_index_to_phyport[2] === pll5_clock_phyport_out_logic) ? 4'b0010 : (pll5_clock_index_to_phyport[3] === pll5_clock_phyport_out_logic) ? 4'b0011 : (pll5_clock_index_to_phyport[4] === pll5_clock_phyport_out_logic) ? 4'b0100 : (pll5_clock_index_to_phyport[5] === pll5_clock_phyport_out_logic) ? 4'b0101 : (pll5_clock_index_to_phyport[6] === pll5_clock_phyport_out_logic) ? 4'b0110 : (pll5_clock_index_to_phyport[7] === pll5_clock_phyport_out_logic) ? 4'b0111 : (pll5_clock_index_to_phyport[8] === pll5_clock_phyport_out_logic) ? 4'b1000 : (pll5_clock_index_to_phyport[9] === pll5_clock_phyport_out_logic) ? 4'b1001 : 4'b1111; // invalid cram values // back to physical assign pll5_clock_select_out = (pll0_logical_to_physical_mapping == 5) ? pll0_clock_select_out_logic : (pll1_logical_to_physical_mapping == 5) ? pll1_clock_select_out_logic : (pll2_logical_to_physical_mapping == 5) ? pll2_clock_select_out_logic : (pll3_logical_to_physical_mapping == 5) ? pll3_clock_select_out_logic : (pll4_logical_to_physical_mapping == 5) ? pll4_clock_select_out_logic : (pll5_logical_to_physical_mapping == 5) ? pll5_clock_select_out_logic : pll5_clock_select_out_logic; assign pll5_dp_pfd_clk_sel = pll5_clock_select_out; //------------------------------------------------------------------------- // TXPMA clock selection -------------------------------------------------- //------------------------------------------------------------------------- initial begin // cgb_x_en txpma_clock_phyport_to_cram[`TXPMA_CLKIN_SELECT_X1] = 2'b00; txpma_clock_phyport_to_cram[`TXPMA_CLKIN_SELECT_X4] = 2'b01; txpma_clock_phyport_to_cram[`TXPMA_CLKIN_SELECT_XN_TOP] = 2'b10; txpma_clock_phyport_to_cram[`TXPMA_CLKIN_SELECT_XN_BOTTOM] = 2'b11; txpma_clock_phyport_to_cram[`TXPMA_CLKIN_SELECT_HT] = 2'b00; txpma_clock_phyport_to_cram[`TXPMA_CLKIN_SELECT_ERR] = 2'b11; end initial begin txpma0_clock_index_to_phyport[0] = convert_txpma_phyport_str_to_phyport_enum(tx0_pma_inclk0_logical_to_physical_mapping); txpma0_clock_index_to_phyport[1] = convert_txpma_phyport_str_to_phyport_enum(tx0_pma_inclk1_logical_to_physical_mapping); txpma0_clock_index_to_phyport[2] = convert_txpma_phyport_str_to_phyport_enum(tx0_pma_inclk2_logical_to_physical_mapping); txpma0_clock_index_to_phyport[3] = convert_txpma_phyport_str_to_phyport_enum(tx0_pma_inclk3_logical_to_physical_mapping); txpma0_clock_index_to_phyport[4] = convert_txpma_phyport_str_to_phyport_enum(tx0_pma_inclk4_logical_to_physical_mapping); txpma1_clock_index_to_phyport[0] = convert_txpma_phyport_str_to_phyport_enum(tx1_pma_inclk0_logical_to_physical_mapping); txpma1_clock_index_to_phyport[1] = convert_txpma_phyport_str_to_phyport_enum(tx1_pma_inclk1_logical_to_physical_mapping); txpma1_clock_index_to_phyport[2] = convert_txpma_phyport_str_to_phyport_enum(tx1_pma_inclk2_logical_to_physical_mapping); txpma1_clock_index_to_phyport[3] = convert_txpma_phyport_str_to_phyport_enum(tx1_pma_inclk3_logical_to_physical_mapping); txpma1_clock_index_to_phyport[4] = convert_txpma_phyport_str_to_phyport_enum(tx1_pma_inclk4_logical_to_physical_mapping); txpma2_clock_index_to_phyport[0] = convert_txpma_phyport_str_to_phyport_enum(tx2_pma_inclk0_logical_to_physical_mapping); txpma2_clock_index_to_phyport[1] = convert_txpma_phyport_str_to_phyport_enum(tx2_pma_inclk1_logical_to_physical_mapping); txpma2_clock_index_to_phyport[2] = convert_txpma_phyport_str_to_phyport_enum(tx2_pma_inclk2_logical_to_physical_mapping); txpma2_clock_index_to_phyport[3] = convert_txpma_phyport_str_to_phyport_enum(tx2_pma_inclk3_logical_to_physical_mapping); txpma2_clock_index_to_phyport[4] = convert_txpma_phyport_str_to_phyport_enum(tx2_pma_inclk4_logical_to_physical_mapping); txpma3_clock_index_to_phyport[0] = convert_txpma_phyport_str_to_phyport_enum(tx3_pma_inclk0_logical_to_physical_mapping); txpma3_clock_index_to_phyport[1] = convert_txpma_phyport_str_to_phyport_enum(tx3_pma_inclk1_logical_to_physical_mapping); txpma3_clock_index_to_phyport[2] = convert_txpma_phyport_str_to_phyport_enum(tx3_pma_inclk2_logical_to_physical_mapping); txpma3_clock_index_to_phyport[3] = convert_txpma_phyport_str_to_phyport_enum(tx3_pma_inclk3_logical_to_physical_mapping); txpma3_clock_index_to_phyport[4] = convert_txpma_phyport_str_to_phyport_enum(tx3_pma_inclk4_logical_to_physical_mapping); txpma4_clock_index_to_phyport[0] = convert_txpma_phyport_str_to_phyport_enum(tx4_pma_inclk0_logical_to_physical_mapping); txpma4_clock_index_to_phyport[1] = convert_txpma_phyport_str_to_phyport_enum(tx4_pma_inclk1_logical_to_physical_mapping); txpma4_clock_index_to_phyport[2] = convert_txpma_phyport_str_to_phyport_enum(tx4_pma_inclk2_logical_to_physical_mapping); txpma4_clock_index_to_phyport[3] = convert_txpma_phyport_str_to_phyport_enum(tx4_pma_inclk3_logical_to_physical_mapping); txpma4_clock_index_to_phyport[4] = convert_txpma_phyport_str_to_phyport_enum(tx4_pma_inclk4_logical_to_physical_mapping); txpma5_clock_index_to_phyport[0] = convert_txpma_phyport_str_to_phyport_enum(tx5_pma_inclk0_logical_to_physical_mapping); txpma5_clock_index_to_phyport[1] = convert_txpma_phyport_str_to_phyport_enum(tx5_pma_inclk1_logical_to_physical_mapping); txpma5_clock_index_to_phyport[2] = convert_txpma_phyport_str_to_phyport_enum(tx5_pma_inclk2_logical_to_physical_mapping); txpma5_clock_index_to_phyport[3] = convert_txpma_phyport_str_to_phyport_enum(tx5_pma_inclk3_logical_to_physical_mapping); txpma5_clock_index_to_phyport[4] = convert_txpma_phyport_str_to_phyport_enum(tx5_pma_inclk4_logical_to_physical_mapping); end // DPRIO read - physical pll channel assign txpma0_clock_select = txpma0_init_clkin_sel; assign txpma0_clock_phyport = (txpma0_clock_select == 0) ? txpma0_clock_index_to_phyport[0] : (txpma0_clock_select == 1) ? txpma0_clock_index_to_phyport[1] : (txpma0_clock_select == 2) ? txpma0_clock_index_to_phyport[2] : (txpma0_clock_select == 3) ? txpma0_clock_index_to_phyport[3] : (txpma0_clock_select == 4) ? txpma0_clock_index_to_phyport[4] : txpma0_clock_index_to_phyport[0]; assign txpma0_clock_cram = (txpma0_clock_phyport == 0) ? txpma_clock_phyport_to_cram[0] : (txpma0_clock_phyport == 1) ? txpma_clock_phyport_to_cram[1] : (txpma0_clock_phyport == 2) ? txpma_clock_phyport_to_cram[2] : (txpma0_clock_phyport == 3) ? txpma_clock_phyport_to_cram[3] : (txpma0_clock_phyport == 4) ? txpma_clock_phyport_to_cram[4] : (txpma0_clock_phyport == 7) ? txpma_clock_phyport_to_cram[7] : txpma_clock_phyport_to_cram[0]; assign txpma0_clock_cram_phy = (tx0_logical_to_physical_mapping == 0) ? txpma0_clock_cram : (tx1_logical_to_physical_mapping == 0) ? txpma1_clock_cram : (tx2_logical_to_physical_mapping == 0) ? txpma2_clock_cram : (tx3_logical_to_physical_mapping == 0) ? txpma3_clock_cram : (tx4_logical_to_physical_mapping == 0) ? txpma4_clock_cram : (tx5_logical_to_physical_mapping == 0) ? txpma5_clock_cram : txpma0_clock_cram; assign txpma0_csr_rcgb_x_en = txpma0_clock_cram_phy[1:0]; // DPRIO write - CRAM on physical assign txpma0_clock_phyport_out = convert_txpma_clock_cram_to_phyport(txpma0_dp_rcgb_x_en); // but the map is on logic channel assign txpma0_clock_phyport_out_logic = (tx0_logical_to_physical_mapping == 0) ? txpma0_clock_phyport_out : (tx0_logical_to_physical_mapping == 1) ? txpma1_clock_phyport_out : (tx0_logical_to_physical_mapping == 2) ? txpma2_clock_phyport_out : (tx0_logical_to_physical_mapping == 3) ? txpma3_clock_phyport_out : (tx0_logical_to_physical_mapping == 4) ? txpma4_clock_phyport_out : (tx0_logical_to_physical_mapping == 5) ? txpma5_clock_phyport_out : txpma0_clock_phyport_out; assign txpma0_clock_select_out_logic = (txpma0_clock_index_to_phyport[0] === txpma0_clock_phyport_out_logic) ? 3'b000 : (txpma0_clock_index_to_phyport[1] === txpma0_clock_phyport_out_logic) ? 3'b001 : (txpma0_clock_index_to_phyport[2] === txpma0_clock_phyport_out_logic) ? 3'b010 : (txpma0_clock_index_to_phyport[3] === txpma0_clock_phyport_out_logic) ? 3'b011 : (txpma0_clock_index_to_phyport[4] === txpma0_clock_phyport_out_logic) ? 3'b100 : 3'b111; // invalid cram values // back to physical assign txpma0_clock_select_out = (tx0_logical_to_physical_mapping == 0) ? txpma0_clock_select_out_logic : (tx1_logical_to_physical_mapping == 0) ? txpma1_clock_select_out_logic : (tx2_logical_to_physical_mapping == 0) ? txpma2_clock_select_out_logic : (tx3_logical_to_physical_mapping == 0) ? txpma3_clock_select_out_logic : (tx4_logical_to_physical_mapping == 0) ? txpma4_clock_select_out_logic : (tx5_logical_to_physical_mapping == 0) ? txpma5_clock_select_out_logic : txpma0_clock_select_out_logic; assign txpma0_dp_clkin_sel = txpma0_clock_select_out; // DPRIO read - physical pll channel assign txpma1_clock_select = txpma1_init_clkin_sel; assign txpma1_clock_phyport = (txpma1_clock_select == 0) ? txpma1_clock_index_to_phyport[0] : (txpma1_clock_select == 1) ? txpma1_clock_index_to_phyport[1] : (txpma1_clock_select == 2) ? txpma1_clock_index_to_phyport[2] : (txpma1_clock_select == 3) ? txpma1_clock_index_to_phyport[3] : (txpma1_clock_select == 4) ? txpma1_clock_index_to_phyport[4] : txpma1_clock_index_to_phyport[0]; assign txpma1_clock_cram = (txpma1_clock_phyport == 0) ? txpma_clock_phyport_to_cram[0] : (txpma1_clock_phyport == 1) ? txpma_clock_phyport_to_cram[1] : (txpma1_clock_phyport == 2) ? txpma_clock_phyport_to_cram[2] : (txpma1_clock_phyport == 3) ? txpma_clock_phyport_to_cram[3] : (txpma1_clock_phyport == 4) ? txpma_clock_phyport_to_cram[4] : (txpma1_clock_phyport == 7) ? txpma_clock_phyport_to_cram[7] : txpma_clock_phyport_to_cram[0]; assign txpma1_clock_cram_phy = (tx0_logical_to_physical_mapping == 1) ? txpma0_clock_cram : (tx1_logical_to_physical_mapping == 1) ? txpma1_clock_cram : (tx2_logical_to_physical_mapping == 1) ? txpma2_clock_cram : (tx3_logical_to_physical_mapping == 1) ? txpma3_clock_cram : (tx4_logical_to_physical_mapping == 1) ? txpma4_clock_cram : (tx5_logical_to_physical_mapping == 1) ? txpma5_clock_cram : txpma1_clock_cram; assign txpma1_csr_rcgb_x_en = txpma1_clock_cram_phy[1:0]; // DPRIO write - CRAM on physical assign txpma1_clock_phyport_out = convert_txpma_clock_cram_to_phyport(txpma1_dp_rcgb_x_en); // but the map is on logic channel assign txpma1_clock_phyport_out_logic = (tx1_logical_to_physical_mapping == 0) ? txpma0_clock_phyport_out : (tx1_logical_to_physical_mapping == 1) ? txpma1_clock_phyport_out : (tx1_logical_to_physical_mapping == 2) ? txpma2_clock_phyport_out : (tx1_logical_to_physical_mapping == 3) ? txpma3_clock_phyport_out : (tx1_logical_to_physical_mapping == 4) ? txpma4_clock_phyport_out : (tx1_logical_to_physical_mapping == 5) ? txpma5_clock_phyport_out : txpma1_clock_phyport_out; assign txpma1_clock_select_out_logic = (txpma1_clock_index_to_phyport[0] === txpma1_clock_phyport_out_logic) ? 3'b000 : (txpma1_clock_index_to_phyport[1] === txpma1_clock_phyport_out_logic) ? 3'b001 : (txpma1_clock_index_to_phyport[2] === txpma1_clock_phyport_out_logic) ? 3'b010 : (txpma1_clock_index_to_phyport[3] === txpma1_clock_phyport_out_logic) ? 3'b011 : (txpma1_clock_index_to_phyport[4] === txpma1_clock_phyport_out_logic) ? 3'b100 : 3'b111; // invalid cram values // back to physical assign txpma1_clock_select_out = (tx0_logical_to_physical_mapping == 1) ? txpma0_clock_select_out_logic : (tx1_logical_to_physical_mapping == 1) ? txpma1_clock_select_out_logic : (tx2_logical_to_physical_mapping == 1) ? txpma2_clock_select_out_logic : (tx3_logical_to_physical_mapping == 1) ? txpma3_clock_select_out_logic : (tx4_logical_to_physical_mapping == 1) ? txpma4_clock_select_out_logic : (tx5_logical_to_physical_mapping == 1) ? txpma5_clock_select_out_logic : txpma1_clock_select_out_logic; assign txpma1_dp_clkin_sel = txpma1_clock_select_out; // DPRIO read - physical pll channel assign txpma2_clock_select = txpma2_init_clkin_sel; assign txpma2_clock_phyport = (txpma2_clock_select == 0) ? txpma2_clock_index_to_phyport[0] : (txpma2_clock_select == 1) ? txpma2_clock_index_to_phyport[1] : (txpma2_clock_select == 2) ? txpma2_clock_index_to_phyport[2] : (txpma2_clock_select == 3) ? txpma2_clock_index_to_phyport[3] : (txpma2_clock_select == 4) ? txpma2_clock_index_to_phyport[4] : txpma2_clock_index_to_phyport[0]; assign txpma2_clock_cram = (txpma2_clock_phyport == 0) ? txpma_clock_phyport_to_cram[0] : (txpma2_clock_phyport == 1) ? txpma_clock_phyport_to_cram[1] : (txpma2_clock_phyport == 2) ? txpma_clock_phyport_to_cram[2] : (txpma2_clock_phyport == 3) ? txpma_clock_phyport_to_cram[3] : (txpma2_clock_phyport == 4) ? txpma_clock_phyport_to_cram[4] : (txpma2_clock_phyport == 7) ? txpma_clock_phyport_to_cram[7] : txpma_clock_phyport_to_cram[0]; assign txpma2_clock_cram_phy = (tx0_logical_to_physical_mapping == 2) ? txpma0_clock_cram : (tx1_logical_to_physical_mapping == 2) ? txpma1_clock_cram : (tx2_logical_to_physical_mapping == 2) ? txpma2_clock_cram : (tx3_logical_to_physical_mapping == 2) ? txpma3_clock_cram : (tx4_logical_to_physical_mapping == 2) ? txpma4_clock_cram : (tx5_logical_to_physical_mapping == 2) ? txpma5_clock_cram : txpma2_clock_cram; assign txpma2_csr_rcgb_x_en = txpma2_clock_cram_phy[1:0]; // DPRIO write - CRAM on physical assign txpma2_clock_phyport_out = convert_txpma_clock_cram_to_phyport(txpma2_dp_rcgb_x_en); // but the map is on logic channel assign txpma2_clock_phyport_out_logic = (tx2_logical_to_physical_mapping == 0) ? txpma0_clock_phyport_out : (tx2_logical_to_physical_mapping == 1) ? txpma1_clock_phyport_out : (tx2_logical_to_physical_mapping == 2) ? txpma2_clock_phyport_out : (tx2_logical_to_physical_mapping == 3) ? txpma3_clock_phyport_out : (tx2_logical_to_physical_mapping == 4) ? txpma4_clock_phyport_out : (tx2_logical_to_physical_mapping == 5) ? txpma5_clock_phyport_out : txpma2_clock_phyport_out; assign txpma2_clock_select_out_logic = (txpma2_clock_index_to_phyport[0] === txpma2_clock_phyport_out_logic) ? 3'b000 : (txpma2_clock_index_to_phyport[1] === txpma2_clock_phyport_out_logic) ? 3'b001 : (txpma2_clock_index_to_phyport[2] === txpma2_clock_phyport_out_logic) ? 3'b010 : (txpma2_clock_index_to_phyport[3] === txpma2_clock_phyport_out_logic) ? 3'b011 : (txpma2_clock_index_to_phyport[4] === txpma2_clock_phyport_out_logic) ? 3'b100 : 3'b111; // invalid cram values // back to physical assign txpma2_clock_select_out = (tx0_logical_to_physical_mapping == 2) ? txpma0_clock_select_out_logic : (tx1_logical_to_physical_mapping == 2) ? txpma1_clock_select_out_logic : (tx2_logical_to_physical_mapping == 2) ? txpma2_clock_select_out_logic : (tx3_logical_to_physical_mapping == 2) ? txpma3_clock_select_out_logic : (tx4_logical_to_physical_mapping == 2) ? txpma4_clock_select_out_logic : (tx5_logical_to_physical_mapping == 2) ? txpma5_clock_select_out_logic : txpma2_clock_select_out_logic; assign txpma2_dp_clkin_sel = txpma2_clock_select_out; // DPRIO read - physical pll channel assign txpma3_clock_select = txpma3_init_clkin_sel; assign txpma3_clock_phyport = (txpma3_clock_select == 0) ? txpma3_clock_index_to_phyport[0] : (txpma3_clock_select == 1) ? txpma3_clock_index_to_phyport[1] : (txpma3_clock_select == 2) ? txpma3_clock_index_to_phyport[2] : (txpma3_clock_select == 3) ? txpma3_clock_index_to_phyport[3] : (txpma3_clock_select == 4) ? txpma3_clock_index_to_phyport[4] : txpma3_clock_index_to_phyport[0]; assign txpma3_clock_cram = (txpma3_clock_phyport == 0) ? txpma_clock_phyport_to_cram[0] : (txpma3_clock_phyport == 1) ? txpma_clock_phyport_to_cram[1] : (txpma3_clock_phyport == 2) ? txpma_clock_phyport_to_cram[2] : (txpma3_clock_phyport == 3) ? txpma_clock_phyport_to_cram[3] : (txpma3_clock_phyport == 4) ? txpma_clock_phyport_to_cram[4] : (txpma3_clock_phyport == 7) ? txpma_clock_phyport_to_cram[7] : txpma_clock_phyport_to_cram[0]; assign txpma3_clock_cram_phy = (tx0_logical_to_physical_mapping == 3) ? txpma0_clock_cram : (tx1_logical_to_physical_mapping == 3) ? txpma1_clock_cram : (tx2_logical_to_physical_mapping == 3) ? txpma2_clock_cram : (tx3_logical_to_physical_mapping == 3) ? txpma3_clock_cram : (tx4_logical_to_physical_mapping == 3) ? txpma4_clock_cram : (tx5_logical_to_physical_mapping == 3) ? txpma5_clock_cram : txpma3_clock_cram; assign txpma3_csr_rcgb_x_en = txpma3_clock_cram_phy[1:0]; // DPRIO write - CRAM on physical assign txpma3_clock_phyport_out = convert_txpma_clock_cram_to_phyport(txpma3_dp_rcgb_x_en); // but the map is on logic channel assign txpma3_clock_phyport_out_logic = (tx3_logical_to_physical_mapping == 0) ? txpma0_clock_phyport_out : (tx3_logical_to_physical_mapping == 1) ? txpma1_clock_phyport_out : (tx3_logical_to_physical_mapping == 2) ? txpma2_clock_phyport_out : (tx3_logical_to_physical_mapping == 3) ? txpma3_clock_phyport_out : (tx3_logical_to_physical_mapping == 4) ? txpma4_clock_phyport_out : (tx3_logical_to_physical_mapping == 5) ? txpma5_clock_phyport_out : txpma3_clock_phyport_out; assign txpma3_clock_select_out_logic = (txpma3_clock_index_to_phyport[0] === txpma3_clock_phyport_out_logic) ? 3'b000 : (txpma3_clock_index_to_phyport[1] === txpma3_clock_phyport_out_logic) ? 3'b001 : (txpma3_clock_index_to_phyport[2] === txpma3_clock_phyport_out_logic) ? 3'b010 : (txpma3_clock_index_to_phyport[3] === txpma3_clock_phyport_out_logic) ? 3'b011 : (txpma3_clock_index_to_phyport[4] === txpma3_clock_phyport_out_logic) ? 3'b100 : 3'b111; // invalid cram values // back to physical assign txpma3_clock_select_out = (tx0_logical_to_physical_mapping == 3) ? txpma0_clock_select_out_logic : (tx1_logical_to_physical_mapping == 3) ? txpma1_clock_select_out_logic : (tx2_logical_to_physical_mapping == 3) ? txpma2_clock_select_out_logic : (tx3_logical_to_physical_mapping == 3) ? txpma3_clock_select_out_logic : (tx4_logical_to_physical_mapping == 3) ? txpma4_clock_select_out_logic : (tx5_logical_to_physical_mapping == 3) ? txpma5_clock_select_out_logic : txpma3_clock_select_out_logic; assign txpma3_dp_clkin_sel = txpma3_clock_select_out; // DPRIO read - physical pll channel assign txpma4_clock_select = txpma4_init_clkin_sel; assign txpma4_clock_phyport = (txpma4_clock_select == 0) ? txpma4_clock_index_to_phyport[0] : (txpma4_clock_select == 1) ? txpma4_clock_index_to_phyport[1] : (txpma4_clock_select == 2) ? txpma4_clock_index_to_phyport[2] : (txpma4_clock_select == 3) ? txpma4_clock_index_to_phyport[3] : (txpma4_clock_select == 4) ? txpma4_clock_index_to_phyport[4] : txpma4_clock_index_to_phyport[0]; assign txpma4_clock_cram = (txpma4_clock_phyport == 0) ? txpma_clock_phyport_to_cram[0] : (txpma4_clock_phyport == 1) ? txpma_clock_phyport_to_cram[1] : (txpma4_clock_phyport == 2) ? txpma_clock_phyport_to_cram[2] : (txpma4_clock_phyport == 3) ? txpma_clock_phyport_to_cram[3] : (txpma4_clock_phyport == 4) ? txpma_clock_phyport_to_cram[4] : (txpma4_clock_phyport == 7) ? txpma_clock_phyport_to_cram[7] : txpma_clock_phyport_to_cram[0]; assign txpma4_clock_cram_phy = (tx0_logical_to_physical_mapping == 4) ? txpma0_clock_cram : (tx1_logical_to_physical_mapping == 4) ? txpma1_clock_cram : (tx2_logical_to_physical_mapping == 4) ? txpma2_clock_cram : (tx3_logical_to_physical_mapping == 4) ? txpma3_clock_cram : (tx4_logical_to_physical_mapping == 4) ? txpma4_clock_cram : (tx5_logical_to_physical_mapping == 4) ? txpma5_clock_cram : txpma4_clock_cram; assign txpma4_csr_rcgb_x_en = txpma4_clock_cram_phy[1:0]; // DPRIO write - CRAM on physical assign txpma4_clock_phyport_out = convert_txpma_clock_cram_to_phyport(txpma4_dp_rcgb_x_en); // but the map is on logic channel assign txpma4_clock_phyport_out_logic = (tx4_logical_to_physical_mapping == 0) ? txpma0_clock_phyport_out : (tx4_logical_to_physical_mapping == 1) ? txpma1_clock_phyport_out : (tx4_logical_to_physical_mapping == 2) ? txpma2_clock_phyport_out : (tx4_logical_to_physical_mapping == 3) ? txpma3_clock_phyport_out : (tx4_logical_to_physical_mapping == 4) ? txpma4_clock_phyport_out : (tx4_logical_to_physical_mapping == 5) ? txpma5_clock_phyport_out : txpma4_clock_phyport_out; assign txpma4_clock_select_out_logic = (txpma4_clock_index_to_phyport[0] === txpma4_clock_phyport_out_logic) ? 3'b000 : (txpma4_clock_index_to_phyport[1] === txpma4_clock_phyport_out_logic) ? 3'b001 : (txpma4_clock_index_to_phyport[2] === txpma4_clock_phyport_out_logic) ? 3'b010 : (txpma4_clock_index_to_phyport[3] === txpma4_clock_phyport_out_logic) ? 3'b011 : (txpma4_clock_index_to_phyport[4] === txpma4_clock_phyport_out_logic) ? 3'b100 : 3'b111; // invalid cram values // back to physical assign txpma4_clock_select_out = (tx0_logical_to_physical_mapping == 4) ? txpma0_clock_select_out_logic : (tx1_logical_to_physical_mapping == 4) ? txpma1_clock_select_out_logic : (tx2_logical_to_physical_mapping == 4) ? txpma2_clock_select_out_logic : (tx3_logical_to_physical_mapping == 4) ? txpma3_clock_select_out_logic : (tx4_logical_to_physical_mapping == 4) ? txpma4_clock_select_out_logic : (tx5_logical_to_physical_mapping == 4) ? txpma5_clock_select_out_logic : txpma4_clock_select_out_logic; assign txpma4_dp_clkin_sel = txpma4_clock_select_out; // DPRIO read - physical pll channel assign txpma5_clock_select = txpma5_init_clkin_sel; assign txpma5_clock_phyport = (txpma5_clock_select == 0) ? txpma5_clock_index_to_phyport[0] : (txpma5_clock_select == 1) ? txpma5_clock_index_to_phyport[1] : (txpma5_clock_select == 2) ? txpma5_clock_index_to_phyport[2] : (txpma5_clock_select == 3) ? txpma5_clock_index_to_phyport[3] : (txpma5_clock_select == 4) ? txpma5_clock_index_to_phyport[4] : txpma5_clock_index_to_phyport[0]; assign txpma5_clock_cram = (txpma5_clock_phyport == 0) ? txpma_clock_phyport_to_cram[0] : (txpma5_clock_phyport == 1) ? txpma_clock_phyport_to_cram[1] : (txpma5_clock_phyport == 2) ? txpma_clock_phyport_to_cram[2] : (txpma5_clock_phyport == 3) ? txpma_clock_phyport_to_cram[3] : (txpma5_clock_phyport == 4) ? txpma_clock_phyport_to_cram[4] : (txpma5_clock_phyport == 7) ? txpma_clock_phyport_to_cram[7] : txpma_clock_phyport_to_cram[0]; assign txpma5_clock_cram_phy = (tx0_logical_to_physical_mapping == 5) ? txpma0_clock_cram : (tx1_logical_to_physical_mapping == 5) ? txpma1_clock_cram : (tx2_logical_to_physical_mapping == 5) ? txpma2_clock_cram : (tx3_logical_to_physical_mapping == 5) ? txpma3_clock_cram : (tx4_logical_to_physical_mapping == 5) ? txpma4_clock_cram : (tx5_logical_to_physical_mapping == 5) ? txpma5_clock_cram : txpma5_clock_cram; assign txpma5_csr_rcgb_x_en = txpma5_clock_cram_phy[1:0]; // DPRIO write - CRAM on physical assign txpma5_clock_phyport_out = convert_txpma_clock_cram_to_phyport(txpma5_dp_rcgb_x_en); // but the map is on logic channel assign txpma5_clock_phyport_out_logic = (tx5_logical_to_physical_mapping == 0) ? txpma0_clock_phyport_out : (tx5_logical_to_physical_mapping == 1) ? txpma1_clock_phyport_out : (tx5_logical_to_physical_mapping == 2) ? txpma2_clock_phyport_out : (tx5_logical_to_physical_mapping == 3) ? txpma3_clock_phyport_out : (tx5_logical_to_physical_mapping == 4) ? txpma4_clock_phyport_out : (tx5_logical_to_physical_mapping == 5) ? txpma5_clock_phyport_out : txpma5_clock_phyport_out; assign txpma5_clock_select_out_logic = (txpma5_clock_index_to_phyport[0] === txpma5_clock_phyport_out_logic) ? 3'b000 : (txpma5_clock_index_to_phyport[1] === txpma5_clock_phyport_out_logic) ? 3'b001 : (txpma5_clock_index_to_phyport[2] === txpma5_clock_phyport_out_logic) ? 3'b010 : (txpma5_clock_index_to_phyport[3] === txpma5_clock_phyport_out_logic) ? 3'b011 : (txpma5_clock_index_to_phyport[4] === txpma5_clock_phyport_out_logic) ? 3'b100 : 3'b111; // invalid cram values // back to physical assign txpma5_clock_select_out = (tx0_logical_to_physical_mapping == 5) ? txpma0_clock_select_out_logic : (tx1_logical_to_physical_mapping == 5) ? txpma1_clock_select_out_logic : (tx2_logical_to_physical_mapping == 5) ? txpma2_clock_select_out_logic : (tx3_logical_to_physical_mapping == 5) ? txpma3_clock_select_out_logic : (tx4_logical_to_physical_mapping == 5) ? txpma4_clock_select_out_logic : (tx5_logical_to_physical_mapping == 5) ? txpma5_clock_select_out_logic : txpma5_clock_select_out_logic; assign txpma5_dp_clkin_sel = txpma5_clock_select_out; //------------------------------------------------------------------------- // PLL0/PLL1 selection ---------------------------------------------------- //------------------------------------------------------------------------- initial begin // rcgb_cmu_sel clkdiv_pll_phyport_to_cram[`CLKDIV_INCLK_SELECT_PLL0] = 1'b0; clkdiv_pll_phyport_to_cram[`CLKDIV_INCLK_SELECT_PLL1] = 1'b1; clkdiv_pll_phyport_to_cram[`CLKDIV_INCLK_SELECT_ERR] = 1'b1; end initial begin clkdiv0_pll_index_to_phyport[0] = convert_clkdiv_pll_phyport_str_to_phyport_enum(clkdiv0_inclk0_logical_to_physical_mapping); clkdiv0_pll_index_to_phyport[1] = convert_clkdiv_pll_phyport_str_to_phyport_enum(clkdiv0_inclk1_logical_to_physical_mapping); clkdiv1_pll_index_to_phyport[0] = convert_clkdiv_pll_phyport_str_to_phyport_enum(clkdiv1_inclk0_logical_to_physical_mapping); clkdiv1_pll_index_to_phyport[1] = convert_clkdiv_pll_phyport_str_to_phyport_enum(clkdiv1_inclk1_logical_to_physical_mapping); clkdiv2_pll_index_to_phyport[0] = convert_clkdiv_pll_phyport_str_to_phyport_enum(clkdiv2_inclk0_logical_to_physical_mapping); clkdiv2_pll_index_to_phyport[1] = convert_clkdiv_pll_phyport_str_to_phyport_enum(clkdiv2_inclk1_logical_to_physical_mapping); clkdiv3_pll_index_to_phyport[0] = convert_clkdiv_pll_phyport_str_to_phyport_enum(clkdiv3_inclk0_logical_to_physical_mapping); clkdiv3_pll_index_to_phyport[1] = convert_clkdiv_pll_phyport_str_to_phyport_enum(clkdiv3_inclk1_logical_to_physical_mapping); clkdiv4_pll_index_to_phyport[0] = convert_clkdiv_pll_phyport_str_to_phyport_enum(clkdiv4_inclk0_logical_to_physical_mapping); clkdiv4_pll_index_to_phyport[1] = convert_clkdiv_pll_phyport_str_to_phyport_enum(clkdiv4_inclk1_logical_to_physical_mapping); clkdiv5_pll_index_to_phyport[0] = convert_clkdiv_pll_phyport_str_to_phyport_enum(clkdiv5_inclk0_logical_to_physical_mapping); clkdiv5_pll_index_to_phyport[1] = convert_clkdiv_pll_phyport_str_to_phyport_enum(clkdiv5_inclk1_logical_to_physical_mapping); end // DPRIO read - logical clkdiv channel assign clkdiv0_pll_select = clkdiv0_init_inclk_select; assign clkdiv0_pll_phyport = (clkdiv0_pll_select == 0) ? clkdiv0_pll_index_to_phyport[0] : (clkdiv0_pll_select == 1) ? clkdiv0_pll_index_to_phyport[1] : clkdiv0_pll_index_to_phyport[0]; assign clkdiv0_pll_cram = (clkdiv0_pll_phyport == 0) ? clkdiv_pll_phyport_to_cram[0] : (clkdiv0_pll_phyport == 1) ? clkdiv_pll_phyport_to_cram[1] : clkdiv_pll_phyport_to_cram[0]; // switch to physical pll number assign clkdiv0_pll_cram_phy = (tx0_logical_to_physical_mapping == 0) ? clkdiv0_pll_cram : (tx1_logical_to_physical_mapping == 0) ? clkdiv1_pll_cram : (tx2_logical_to_physical_mapping == 0) ? clkdiv2_pll_cram : (tx3_logical_to_physical_mapping == 0) ? clkdiv3_pll_cram : (tx4_logical_to_physical_mapping == 0) ? clkdiv4_pll_cram : (tx5_logical_to_physical_mapping == 0) ? clkdiv5_pll_cram : clkdiv0_pll_cram; assign clkdiv0_csr_rcgb_cmu_sel = clkdiv0_pll_cram_phy; // DPRIO write - CRAM on physical assign clkdiv0_pll_phyport_out = convert_clkdiv_pll_cram_to_phyport(clkdiv0_dp_rcgb_cmu_sel); // but the map is on logic channel assign clkdiv0_pll_phyport_out_logic = (tx0_logical_to_physical_mapping == 0) ? clkdiv0_pll_phyport_out : (tx0_logical_to_physical_mapping == 1) ? clkdiv1_pll_phyport_out : (tx0_logical_to_physical_mapping == 2) ? clkdiv2_pll_phyport_out : (tx0_logical_to_physical_mapping == 3) ? clkdiv3_pll_phyport_out : (tx0_logical_to_physical_mapping == 4) ? clkdiv4_pll_phyport_out : (tx0_logical_to_physical_mapping == 5) ? clkdiv5_pll_phyport_out : clkdiv0_pll_phyport_out; assign clkdiv0_pll_select_out_logic = (clkdiv0_pll_index_to_phyport[0] === clkdiv0_pll_phyport_out_logic) ? 1'b0 : (clkdiv0_pll_index_to_phyport[1] === clkdiv0_pll_phyport_out_logic) ? 1'b1 : 1'b1; // back to physical assign clkdiv0_pll_select_out = (tx0_logical_to_physical_mapping == 0) ? clkdiv0_pll_select_out_logic : (tx1_logical_to_physical_mapping == 0) ? clkdiv1_pll_select_out_logic : (tx2_logical_to_physical_mapping == 0) ? clkdiv2_pll_select_out_logic : (tx3_logical_to_physical_mapping == 0) ? clkdiv3_pll_select_out_logic : (tx4_logical_to_physical_mapping == 0) ? clkdiv4_pll_select_out_logic : (tx5_logical_to_physical_mapping == 0) ? clkdiv5_pll_select_out_logic : clkdiv0_pll_select_out_logic; assign clkdiv0_dp_inclk_select = clkdiv0_pll_select_out; // DPRIO read - logical clkdiv channel assign clkdiv1_pll_select = clkdiv1_init_inclk_select; assign clkdiv1_pll_phyport = (clkdiv1_pll_select == 0) ? clkdiv1_pll_index_to_phyport[0] : (clkdiv1_pll_select == 1) ? clkdiv1_pll_index_to_phyport[1] : clkdiv1_pll_index_to_phyport[0]; assign clkdiv1_pll_cram = (clkdiv1_pll_phyport == 0) ? clkdiv_pll_phyport_to_cram[0] : (clkdiv1_pll_phyport == 1) ? clkdiv_pll_phyport_to_cram[1] : clkdiv_pll_phyport_to_cram[0]; // switch to physical pll number assign clkdiv1_pll_cram_phy = (tx0_logical_to_physical_mapping == 1) ? clkdiv0_pll_cram : (tx1_logical_to_physical_mapping == 1) ? clkdiv1_pll_cram : (tx2_logical_to_physical_mapping == 1) ? clkdiv2_pll_cram : (tx3_logical_to_physical_mapping == 1) ? clkdiv3_pll_cram : (tx4_logical_to_physical_mapping == 1) ? clkdiv4_pll_cram : (tx5_logical_to_physical_mapping == 1) ? clkdiv5_pll_cram : clkdiv1_pll_cram; assign clkdiv1_csr_rcgb_cmu_sel = clkdiv1_pll_cram_phy; // DPRIO write - CRAM on physical assign clkdiv1_pll_phyport_out = convert_clkdiv_pll_cram_to_phyport(clkdiv1_dp_rcgb_cmu_sel); // but the map is on logic channel assign clkdiv1_pll_phyport_out_logic = (tx1_logical_to_physical_mapping == 0) ? clkdiv0_pll_phyport_out : (tx1_logical_to_physical_mapping == 1) ? clkdiv1_pll_phyport_out : (tx1_logical_to_physical_mapping == 2) ? clkdiv2_pll_phyport_out : (tx1_logical_to_physical_mapping == 3) ? clkdiv3_pll_phyport_out : (tx1_logical_to_physical_mapping == 4) ? clkdiv4_pll_phyport_out : (tx1_logical_to_physical_mapping == 5) ? clkdiv5_pll_phyport_out : clkdiv1_pll_phyport_out; assign clkdiv1_pll_select_out_logic = (clkdiv1_pll_index_to_phyport[0] === clkdiv1_pll_phyport_out_logic) ? 1'b0 : (clkdiv1_pll_index_to_phyport[1] === clkdiv1_pll_phyport_out_logic) ? 1'b1 : 1'b1; // back to physical assign clkdiv1_pll_select_out = (tx0_logical_to_physical_mapping == 1) ? clkdiv0_pll_select_out_logic : (tx1_logical_to_physical_mapping == 1) ? clkdiv1_pll_select_out_logic : (tx2_logical_to_physical_mapping == 1) ? clkdiv2_pll_select_out_logic : (tx3_logical_to_physical_mapping == 1) ? clkdiv3_pll_select_out_logic : (tx4_logical_to_physical_mapping == 1) ? clkdiv4_pll_select_out_logic : (tx5_logical_to_physical_mapping == 1) ? clkdiv5_pll_select_out_logic : clkdiv1_pll_select_out_logic; assign clkdiv1_dp_inclk_select = clkdiv1_pll_select_out; // DPRIO read - logical clkdiv channel assign clkdiv2_pll_select = clkdiv2_init_inclk_select; assign clkdiv2_pll_phyport = (clkdiv2_pll_select == 0) ? clkdiv2_pll_index_to_phyport[0] : (clkdiv2_pll_select == 1) ? clkdiv2_pll_index_to_phyport[1] : clkdiv2_pll_index_to_phyport[0]; assign clkdiv2_pll_cram = (clkdiv2_pll_phyport == 0) ? clkdiv_pll_phyport_to_cram[0] : (clkdiv2_pll_phyport == 1) ? clkdiv_pll_phyport_to_cram[1] : clkdiv_pll_phyport_to_cram[0]; // switch to physical pll number assign clkdiv2_pll_cram_phy = (tx0_logical_to_physical_mapping == 2) ? clkdiv0_pll_cram : (tx1_logical_to_physical_mapping == 2) ? clkdiv1_pll_cram : (tx2_logical_to_physical_mapping == 2) ? clkdiv2_pll_cram : (tx3_logical_to_physical_mapping == 2) ? clkdiv3_pll_cram : (tx4_logical_to_physical_mapping == 2) ? clkdiv4_pll_cram : (tx5_logical_to_physical_mapping == 2) ? clkdiv5_pll_cram : clkdiv2_pll_cram; assign clkdiv2_csr_rcgb_cmu_sel = clkdiv2_pll_cram_phy; // DPRIO write - CRAM on physical assign clkdiv2_pll_phyport_out = convert_clkdiv_pll_cram_to_phyport(clkdiv2_dp_rcgb_cmu_sel); // but the map is on logic channel assign clkdiv2_pll_phyport_out_logic = (tx2_logical_to_physical_mapping == 0) ? clkdiv0_pll_phyport_out : (tx2_logical_to_physical_mapping == 1) ? clkdiv1_pll_phyport_out : (tx2_logical_to_physical_mapping == 2) ? clkdiv2_pll_phyport_out : (tx2_logical_to_physical_mapping == 3) ? clkdiv3_pll_phyport_out : (tx2_logical_to_physical_mapping == 4) ? clkdiv4_pll_phyport_out : (tx2_logical_to_physical_mapping == 5) ? clkdiv5_pll_phyport_out : clkdiv2_pll_phyport_out; assign clkdiv2_pll_select_out_logic = (clkdiv2_pll_index_to_phyport[0] === clkdiv2_pll_phyport_out_logic) ? 1'b0 : (clkdiv2_pll_index_to_phyport[1] === clkdiv2_pll_phyport_out_logic) ? 1'b1 : 1'b1; // back to physical assign clkdiv2_pll_select_out = (tx0_logical_to_physical_mapping == 2) ? clkdiv0_pll_select_out_logic : (tx1_logical_to_physical_mapping == 2) ? clkdiv1_pll_select_out_logic : (tx2_logical_to_physical_mapping == 2) ? clkdiv2_pll_select_out_logic : (tx3_logical_to_physical_mapping == 2) ? clkdiv3_pll_select_out_logic : (tx4_logical_to_physical_mapping == 2) ? clkdiv4_pll_select_out_logic : (tx5_logical_to_physical_mapping == 2) ? clkdiv5_pll_select_out_logic : clkdiv2_pll_select_out_logic; assign clkdiv2_dp_inclk_select = clkdiv2_pll_select_out; // DPRIO read - logical clkdiv channel assign clkdiv3_pll_select = clkdiv3_init_inclk_select; assign clkdiv3_pll_phyport = (clkdiv3_pll_select == 0) ? clkdiv3_pll_index_to_phyport[0] : (clkdiv3_pll_select == 1) ? clkdiv3_pll_index_to_phyport[1] : clkdiv3_pll_index_to_phyport[0]; assign clkdiv3_pll_cram = (clkdiv3_pll_phyport == 0) ? clkdiv_pll_phyport_to_cram[0] : (clkdiv3_pll_phyport == 1) ? clkdiv_pll_phyport_to_cram[1] : clkdiv_pll_phyport_to_cram[0]; // switch to physical pll number assign clkdiv3_pll_cram_phy = (tx0_logical_to_physical_mapping == 3) ? clkdiv0_pll_cram : (tx1_logical_to_physical_mapping == 3) ? clkdiv1_pll_cram : (tx2_logical_to_physical_mapping == 3) ? clkdiv2_pll_cram : (tx3_logical_to_physical_mapping == 3) ? clkdiv3_pll_cram : (tx4_logical_to_physical_mapping == 3) ? clkdiv4_pll_cram : (tx5_logical_to_physical_mapping == 3) ? clkdiv5_pll_cram : clkdiv3_pll_cram; assign clkdiv3_csr_rcgb_cmu_sel = clkdiv3_pll_cram_phy; // DPRIO write - CRAM on physical assign clkdiv3_pll_phyport_out = convert_clkdiv_pll_cram_to_phyport(clkdiv3_dp_rcgb_cmu_sel); // but the map is on logic channel assign clkdiv3_pll_phyport_out_logic = (tx3_logical_to_physical_mapping == 0) ? clkdiv0_pll_phyport_out : (tx3_logical_to_physical_mapping == 1) ? clkdiv1_pll_phyport_out : (tx3_logical_to_physical_mapping == 2) ? clkdiv2_pll_phyport_out : (tx3_logical_to_physical_mapping == 3) ? clkdiv3_pll_phyport_out : (tx3_logical_to_physical_mapping == 4) ? clkdiv4_pll_phyport_out : (tx3_logical_to_physical_mapping == 5) ? clkdiv5_pll_phyport_out : clkdiv3_pll_phyport_out; assign clkdiv3_pll_select_out_logic = (clkdiv3_pll_index_to_phyport[0] === clkdiv3_pll_phyport_out_logic) ? 1'b0 : (clkdiv3_pll_index_to_phyport[1] === clkdiv3_pll_phyport_out_logic) ? 1'b1 : 1'b1; // back to physical assign clkdiv3_pll_select_out = (tx0_logical_to_physical_mapping == 3) ? clkdiv0_pll_select_out_logic : (tx1_logical_to_physical_mapping == 3) ? clkdiv1_pll_select_out_logic : (tx2_logical_to_physical_mapping == 3) ? clkdiv2_pll_select_out_logic : (tx3_logical_to_physical_mapping == 3) ? clkdiv3_pll_select_out_logic : (tx4_logical_to_physical_mapping == 3) ? clkdiv4_pll_select_out_logic : (tx5_logical_to_physical_mapping == 3) ? clkdiv5_pll_select_out_logic : clkdiv3_pll_select_out_logic; assign clkdiv3_dp_inclk_select = clkdiv3_pll_select_out; // DPRIO read - logical clkdiv channel assign clkdiv4_pll_select = clkdiv4_init_inclk_select; assign clkdiv4_pll_phyport = (clkdiv4_pll_select == 0) ? clkdiv4_pll_index_to_phyport[0] : (clkdiv4_pll_select == 1) ? clkdiv4_pll_index_to_phyport[1] : clkdiv4_pll_index_to_phyport[0]; assign clkdiv4_pll_cram = (clkdiv4_pll_phyport == 0) ? clkdiv_pll_phyport_to_cram[0] : (clkdiv4_pll_phyport == 1) ? clkdiv_pll_phyport_to_cram[1] : clkdiv_pll_phyport_to_cram[0]; // switch to physical pll number assign clkdiv4_pll_cram_phy = (tx0_logical_to_physical_mapping == 4) ? clkdiv0_pll_cram : (tx1_logical_to_physical_mapping == 4) ? clkdiv1_pll_cram : (tx2_logical_to_physical_mapping == 4) ? clkdiv2_pll_cram : (tx3_logical_to_physical_mapping == 4) ? clkdiv3_pll_cram : (tx4_logical_to_physical_mapping == 4) ? clkdiv4_pll_cram : (tx5_logical_to_physical_mapping == 4) ? clkdiv5_pll_cram : clkdiv4_pll_cram; assign clkdiv4_csr_rcgb_cmu_sel = clkdiv4_pll_cram_phy; // DPRIO write - CRAM on physical assign clkdiv4_pll_phyport_out = convert_clkdiv_pll_cram_to_phyport(clkdiv4_dp_rcgb_cmu_sel); // but the map is on logic channel assign clkdiv4_pll_phyport_out_logic = (tx4_logical_to_physical_mapping == 0) ? clkdiv0_pll_phyport_out : (tx4_logical_to_physical_mapping == 1) ? clkdiv1_pll_phyport_out : (tx4_logical_to_physical_mapping == 2) ? clkdiv2_pll_phyport_out : (tx4_logical_to_physical_mapping == 3) ? clkdiv3_pll_phyport_out : (tx4_logical_to_physical_mapping == 4) ? clkdiv4_pll_phyport_out : (tx4_logical_to_physical_mapping == 5) ? clkdiv5_pll_phyport_out : clkdiv4_pll_phyport_out; assign clkdiv4_pll_select_out_logic = (clkdiv4_pll_index_to_phyport[0] === clkdiv4_pll_phyport_out_logic) ? 1'b0 : (clkdiv4_pll_index_to_phyport[1] === clkdiv4_pll_phyport_out_logic) ? 1'b1 : 1'b1; // back to physical assign clkdiv4_pll_select_out = (tx0_logical_to_physical_mapping == 4) ? clkdiv0_pll_select_out_logic : (tx1_logical_to_physical_mapping == 4) ? clkdiv1_pll_select_out_logic : (tx2_logical_to_physical_mapping == 4) ? clkdiv2_pll_select_out_logic : (tx3_logical_to_physical_mapping == 4) ? clkdiv3_pll_select_out_logic : (tx4_logical_to_physical_mapping == 4) ? clkdiv4_pll_select_out_logic : (tx5_logical_to_physical_mapping == 4) ? clkdiv5_pll_select_out_logic : clkdiv4_pll_select_out_logic; assign clkdiv4_dp_inclk_select = clkdiv4_pll_select_out; // DPRIO read - logical clkdiv channel assign clkdiv5_pll_select = clkdiv5_init_inclk_select; assign clkdiv5_pll_phyport = (clkdiv5_pll_select == 0) ? clkdiv5_pll_index_to_phyport[0] : (clkdiv5_pll_select == 1) ? clkdiv5_pll_index_to_phyport[1] : clkdiv5_pll_index_to_phyport[0]; assign clkdiv5_pll_cram = (clkdiv5_pll_phyport == 0) ? clkdiv_pll_phyport_to_cram[0] : (clkdiv5_pll_phyport == 1) ? clkdiv_pll_phyport_to_cram[1] : clkdiv_pll_phyport_to_cram[0]; // switch to physical pll number assign clkdiv5_pll_cram_phy = (tx0_logical_to_physical_mapping == 5) ? clkdiv0_pll_cram : (tx1_logical_to_physical_mapping == 5) ? clkdiv1_pll_cram : (tx2_logical_to_physical_mapping == 5) ? clkdiv2_pll_cram : (tx3_logical_to_physical_mapping == 5) ? clkdiv3_pll_cram : (tx4_logical_to_physical_mapping == 5) ? clkdiv4_pll_cram : (tx5_logical_to_physical_mapping == 5) ? clkdiv5_pll_cram : clkdiv5_pll_cram; assign clkdiv5_csr_rcgb_cmu_sel = clkdiv5_pll_cram_phy; // DPRIO write - CRAM on physical assign clkdiv5_pll_phyport_out = convert_clkdiv_pll_cram_to_phyport(clkdiv5_dp_rcgb_cmu_sel); // but the map is on logic channel assign clkdiv5_pll_phyport_out_logic = (tx5_logical_to_physical_mapping == 0) ? clkdiv0_pll_phyport_out : (tx5_logical_to_physical_mapping == 1) ? clkdiv1_pll_phyport_out : (tx5_logical_to_physical_mapping == 2) ? clkdiv2_pll_phyport_out : (tx5_logical_to_physical_mapping == 3) ? clkdiv3_pll_phyport_out : (tx5_logical_to_physical_mapping == 4) ? clkdiv4_pll_phyport_out : (tx5_logical_to_physical_mapping == 5) ? clkdiv5_pll_phyport_out : clkdiv5_pll_phyport_out; assign clkdiv5_pll_select_out_logic = (clkdiv5_pll_index_to_phyport[0] === clkdiv5_pll_phyport_out_logic) ? 1'b0 : (clkdiv5_pll_index_to_phyport[1] === clkdiv5_pll_phyport_out_logic) ? 1'b1 : 1'b1; // back to physical assign clkdiv5_pll_select_out = (tx0_logical_to_physical_mapping == 5) ? clkdiv0_pll_select_out_logic : (tx1_logical_to_physical_mapping == 5) ? clkdiv1_pll_select_out_logic : (tx2_logical_to_physical_mapping == 5) ? clkdiv2_pll_select_out_logic : (tx3_logical_to_physical_mapping == 5) ? clkdiv3_pll_select_out_logic : (tx4_logical_to_physical_mapping == 5) ? clkdiv4_pll_select_out_logic : (tx5_logical_to_physical_mapping == 5) ? clkdiv5_pll_select_out_logic : clkdiv5_pll_select_out_logic; assign clkdiv5_dp_inclk_select = clkdiv5_pll_select_out; endmodule /////////////////////////////////////////////////////////////////////////////// // DPRIO INDEX TABLE --------------------------------------------------------// /////////////////////////////////////////////////////////////////////////////// // make sure indices with _DP_ in the middle to distiguish from rx/tx // RX PMA Per channel control register 4 // assign rcru_div2 =out_chnl_ctrl_39[15]; // assign rcru_m_sel[1:0] =out_chnl_ctrl_39[14:13]; // assign rcru_m[3:0] =out_chnl_ctrl_39[12:9]; // assign rcru_l[1:0] =out_chnl_ctrl_39[8:7]; // assign rcru_ctl0 =out_chnl_ctrl_39[6]; // assign rcru_crplctrl[1:0] =out_chnl_ctrl_39[5:4]; // assign rcru_pfdbwctrl[1:0] =out_chnl_ctrl_39[3:2]; // assign rcru_pdbwctrl[1:0] =out_chnl_ctrl_39[1:0]; `timescale 1 ps / 1 ps module stratixiv_hssi_cmu_dprio_map( cmudividerdprioin, cmuplldprioin, refclkdividerdprioin, rxpcsdprioin, rxpmadprioin, txpcsdprioin, txpmadprioin, ch0_dp_chnl_out, ch1_dp_chnl_out, ch2_dp_chnl_out, ch3_dp_chnl_out, ch0_dp_chnl_out_reserved, ch1_dp_chnl_out_reserved, ch2_dp_chnl_out_reserved, ch3_dp_chnl_out_reserved, dp_centrl_out, dp_centrl_out_reserved, ch0_csr_chnl_in, ch1_csr_chnl_in, ch2_csr_chnl_in, ch3_csr_chnl_in, ch0_csr_chnl_in_reserved, ch1_csr_chnl_in_reserved, ch2_csr_chnl_in_reserved, ch3_csr_chnl_in_reserved, csr_centrl_in, csr_centrl_in_reserved, cmudividerdprioout, cmuplldprioout, refclkdividerdprioout, rxpcsdprioout, rxpmadprioout, txpcsdprioout, txpmadprioout ); // -------------------- Simulation only parameters ---------------------------- parameter clkdiv0_inclk0_logical_to_physical_mapping = "pll0"; parameter clkdiv0_inclk1_logical_to_physical_mapping = "pll1"; parameter clkdiv1_inclk0_logical_to_physical_mapping = "pll0"; parameter clkdiv1_inclk1_logical_to_physical_mapping = "pll1"; parameter clkdiv2_inclk0_logical_to_physical_mapping = "pll0"; parameter clkdiv2_inclk1_logical_to_physical_mapping = "pll1"; parameter clkdiv3_inclk0_logical_to_physical_mapping = "pll0"; parameter clkdiv3_inclk1_logical_to_physical_mapping = "pll1"; parameter clkdiv4_inclk0_logical_to_physical_mapping = "pll0"; parameter clkdiv4_inclk1_logical_to_physical_mapping = "pll1"; parameter clkdiv5_inclk0_logical_to_physical_mapping = "pll0"; parameter clkdiv5_inclk1_logical_to_physical_mapping = "pll1"; parameter pll0_inclk0_logical_to_physical_mapping = "clkrefclk0"; parameter pll0_inclk1_logical_to_physical_mapping = "clkrefclk1"; parameter pll0_inclk2_logical_to_physical_mapping = "iq2"; parameter pll0_inclk3_logical_to_physical_mapping = "iq3"; parameter pll0_inclk4_logical_to_physical_mapping = "iq4"; parameter pll0_inclk5_logical_to_physical_mapping = "iq5"; parameter pll0_inclk6_logical_to_physical_mapping = "iq6"; parameter pll0_inclk7_logical_to_physical_mapping = "iq7"; parameter pll0_inclk8_logical_to_physical_mapping = "pld_clk"; parameter pll0_inclk9_logical_to_physical_mapping = "gpll_clk"; parameter pll0_logical_to_physical_mapping = 0 ; parameter pll1_inclk0_logical_to_physical_mapping = "clkrefclk0"; parameter pll1_inclk1_logical_to_physical_mapping = "clkrefclk1"; parameter pll1_inclk2_logical_to_physical_mapping = "iq2"; parameter pll1_inclk3_logical_to_physical_mapping = "iq3"; parameter pll1_inclk4_logical_to_physical_mapping = "iq4"; parameter pll1_inclk5_logical_to_physical_mapping = "iq5"; parameter pll1_inclk6_logical_to_physical_mapping = "iq6"; parameter pll1_inclk7_logical_to_physical_mapping = "iq7"; parameter pll1_inclk8_logical_to_physical_mapping = "pld_clk"; parameter pll1_inclk9_logical_to_physical_mapping = "gpll_clk"; parameter pll1_logical_to_physical_mapping = 1 ; parameter pll2_inclk0_logical_to_physical_mapping = "clkrefclk0"; parameter pll2_inclk1_logical_to_physical_mapping = "clkrefclk1"; parameter pll2_inclk2_logical_to_physical_mapping = "iq2"; parameter pll2_inclk3_logical_to_physical_mapping = "iq3"; parameter pll2_inclk4_logical_to_physical_mapping = "iq4"; parameter pll2_inclk5_logical_to_physical_mapping = "iq5"; parameter pll2_inclk6_logical_to_physical_mapping = "iq6"; parameter pll2_inclk7_logical_to_physical_mapping = "iq7"; parameter pll2_inclk8_logical_to_physical_mapping = "pld_clk"; parameter pll2_inclk9_logical_to_physical_mapping = "gpll_clk"; parameter pll2_logical_to_physical_mapping = 2 ; parameter pll3_inclk0_logical_to_physical_mapping = "clkrefclk0"; parameter pll3_inclk1_logical_to_physical_mapping = "clkrefclk1"; parameter pll3_inclk2_logical_to_physical_mapping = "iq2"; parameter pll3_inclk3_logical_to_physical_mapping = "iq3"; parameter pll3_inclk4_logical_to_physical_mapping = "iq4"; parameter pll3_inclk5_logical_to_physical_mapping = "iq5"; parameter pll3_inclk6_logical_to_physical_mapping = "iq6"; parameter pll3_inclk7_logical_to_physical_mapping = "iq7"; parameter pll3_inclk8_logical_to_physical_mapping = "pld_clk"; parameter pll3_inclk9_logical_to_physical_mapping = "gpll_clk"; parameter pll3_logical_to_physical_mapping = 3 ; parameter pll4_inclk0_logical_to_physical_mapping = "clkrefclk0"; parameter pll4_inclk1_logical_to_physical_mapping = "clkrefclk1"; parameter pll4_inclk2_logical_to_physical_mapping = "iq2"; parameter pll4_inclk3_logical_to_physical_mapping = "iq3"; parameter pll4_inclk4_logical_to_physical_mapping = "iq4"; parameter pll4_inclk5_logical_to_physical_mapping = "iq5"; parameter pll4_inclk6_logical_to_physical_mapping = "iq6"; parameter pll4_inclk7_logical_to_physical_mapping = "iq7"; parameter pll4_inclk8_logical_to_physical_mapping = "pld_clk"; parameter pll4_inclk9_logical_to_physical_mapping = "gpll_clk"; parameter pll4_logical_to_physical_mapping = 4 ; parameter pll5_inclk0_logical_to_physical_mapping = "clkrefclk0"; parameter pll5_inclk1_logical_to_physical_mapping = "clkrefclk1"; parameter pll5_inclk2_logical_to_physical_mapping = "iq2"; parameter pll5_inclk3_logical_to_physical_mapping = "iq3"; parameter pll5_inclk4_logical_to_physical_mapping = "iq4"; parameter pll5_inclk5_logical_to_physical_mapping = "iq5"; parameter pll5_inclk6_logical_to_physical_mapping = "iq6"; parameter pll5_inclk7_logical_to_physical_mapping = "iq7"; parameter pll5_inclk8_logical_to_physical_mapping = "pld_clk"; parameter pll5_inclk9_logical_to_physical_mapping = "gpll_clk"; parameter pll5_logical_to_physical_mapping = 5 ; parameter refclk_divider0_logical_to_physical_mapping = 0 ; parameter refclk_divider1_logical_to_physical_mapping = 1 ; parameter rx0_logical_to_physical_mapping = 0 ; parameter rx1_logical_to_physical_mapping = 1 ; parameter rx2_logical_to_physical_mapping = 2 ; parameter rx3_logical_to_physical_mapping = 3 ; parameter rx4_logical_to_physical_mapping = 4 ; parameter rx5_logical_to_physical_mapping = 5 ; parameter tx0_logical_to_physical_mapping = 0 ; parameter tx1_logical_to_physical_mapping = 1 ; parameter tx2_logical_to_physical_mapping = 2 ; parameter tx3_logical_to_physical_mapping = 3 ; parameter tx4_logical_to_physical_mapping = 4 ; parameter tx5_logical_to_physical_mapping = 5 ; parameter tx0_pma_inclk0_logical_to_physical_mapping = "x1"; parameter tx0_pma_inclk1_logical_to_physical_mapping = "x4"; parameter tx0_pma_inclk2_logical_to_physical_mapping = "xn_top"; parameter tx0_pma_inclk3_logical_to_physical_mapping = "xn_bottom"; parameter tx0_pma_inclk4_logical_to_physical_mapping = "hypertransport"; parameter tx1_pma_inclk0_logical_to_physical_mapping = "x1"; parameter tx1_pma_inclk1_logical_to_physical_mapping = "x4"; parameter tx1_pma_inclk2_logical_to_physical_mapping = "xn_top"; parameter tx1_pma_inclk3_logical_to_physical_mapping = "xn_bottom"; parameter tx1_pma_inclk4_logical_to_physical_mapping = "hypertransport"; parameter tx2_pma_inclk0_logical_to_physical_mapping = "x1"; parameter tx2_pma_inclk1_logical_to_physical_mapping = "x4"; parameter tx2_pma_inclk2_logical_to_physical_mapping = "xn_top"; parameter tx2_pma_inclk3_logical_to_physical_mapping = "xn_bottom"; parameter tx2_pma_inclk4_logical_to_physical_mapping = "hypertransport"; parameter tx3_pma_inclk0_logical_to_physical_mapping = "x1"; parameter tx3_pma_inclk1_logical_to_physical_mapping = "x4"; parameter tx3_pma_inclk2_logical_to_physical_mapping = "xn_top"; parameter tx3_pma_inclk3_logical_to_physical_mapping = "xn_bottom"; parameter tx3_pma_inclk4_logical_to_physical_mapping = "hypertransport"; parameter tx4_pma_inclk0_logical_to_physical_mapping = "x1"; parameter tx4_pma_inclk1_logical_to_physical_mapping = "x4"; parameter tx4_pma_inclk2_logical_to_physical_mapping = "xn_top"; parameter tx4_pma_inclk3_logical_to_physical_mapping = "xn_bottom"; parameter tx4_pma_inclk4_logical_to_physical_mapping = "hypertransport"; parameter tx5_pma_inclk0_logical_to_physical_mapping = "x1"; parameter tx5_pma_inclk1_logical_to_physical_mapping = "x4"; parameter tx5_pma_inclk2_logical_to_physical_mapping = "xn_top"; parameter tx5_pma_inclk3_logical_to_physical_mapping = "xn_bottom"; parameter tx5_pma_inclk4_logical_to_physical_mapping = "hypertransport"; // external parameters // DEBUG dump parameter sim_dump_dprio_internal_reg_at_time = 0; // in ps parameter sim_dump_filename = "sim_dprio_dump.txt"; input [599 : 0] cmudividerdprioin; input [1799 : 0] cmuplldprioin; input [1 : 0] refclkdividerdprioin; input [1599 : 0] rxpcsdprioin; input [1799 : 0] rxpmadprioin; input [599 : 0] txpcsdprioin; input [1799 : 0] txpmadprioin; input [831:0] ch0_dp_chnl_out; input [831:0] ch1_dp_chnl_out; input [831:0] ch2_dp_chnl_out; input [831:0] ch3_dp_chnl_out; input [15:0] ch0_dp_chnl_out_reserved; input [15:0] ch1_dp_chnl_out_reserved; input [15:0] ch2_dp_chnl_out_reserved; input [15:0] ch3_dp_chnl_out_reserved; input [703:0] dp_centrl_out; input [31:0] dp_centrl_out_reserved; output [831:0] ch0_csr_chnl_in; output [831:0] ch1_csr_chnl_in; output [831:0] ch2_csr_chnl_in; output [831:0] ch3_csr_chnl_in; output [15:0] ch0_csr_chnl_in_reserved; output [15:0] ch1_csr_chnl_in_reserved; output [15:0] ch2_csr_chnl_in_reserved; output [15:0] ch3_csr_chnl_in_reserved; output [703:0] csr_centrl_in; output [31:0] csr_centrl_in_reserved; output [599 : 0] cmudividerdprioout; output [1799 : 0] cmuplldprioout; output [1 : 0] refclkdividerdprioout; output [1599 : 0] rxpcsdprioout; output [1799 : 0] rxpmadprioout; output [599 : 0] txpcsdprioout; output [1799 : 0] txpmadprioout; // ******************************************************************* // RXPLL and CMUPLL must have same indices since they share same Atom // ******************************************************************* // Table1: PCS Per Channel TX Control Register 1 for Channel 0 `define rforce_disp_DP_TXPCS_IDX_0 0 `define rrev_loopbk_DP_TXPCS_IDX_0 1 `define rtxrdclksel_DP_TXPCS_IDX_0 2 `define rtxwrclksel_DP_TXPCS_IDX_0 3 `define rfreerun_tx_DP_TXPCS_IDX_0 4 `define rtxurstpcs_DP_TXPCS_IDX_0 5 `define reserved_0_TB1_DP_TXPCS_IDX_0 6 `define rphfifoursttx_DP_TXPCS_IDX_0 7 `define rphfifopldentx_DP_TXPCS_IDX_0 8 `define rge_xaui_tx_DP_TXPCS_IDX_0 9 `define rdwidth_tx_DP_TXPCS_IDX_0 10 `define rtxfifo_lowlatency_en_DP_TXPCS_IDX_0 11 `define rib_force_disp_DP_TXPCS_IDX_0 12 `define rtxfifo_dis_DP_TXPCS_IDX_0 13 `define rforce_echar_DP_TXPCS_IDX_0 14 `define rforce_kchar_DP_TXPCS_IDX_0 15 // Table2: PCS Per Channel TX Control Register 2 for Channel 0 `define rtxpcsbypass_en_DP_TXPCS_IDX_0 16 `define rcxpat_chnl_en_DP_TXPCS_IDX_0 17 `define rcxpat_chnl_en_DP_TXPCS_IDX_1 18 `define rbist_sel_DP_TXPCS_IDX_0 19 `define rbist_sel_DP_TXPCS_IDX_1 20 `define rbisten_tx_DP_TXPCS_IDX_0 21 `define rprbs_sel_DP_TXPCS_IDX_0 22 `define rprbs_sel_DP_TXPCS_IDX_1 23 `define rprbs_sel_DP_TXPCS_IDX_2 24 `define rprbsen_tx_DP_TXPCS_IDX_0 25 `define renbitrev_tx_DP_TXPCS_IDX_0 26 `define renpolinv_tx_DP_TXPCS_IDX_0 27 `define rensymswap_tx_DP_TXPCS_IDX_0 28 `define rcascaded_8b10b_en_tx_DP_TXPCS_IDX_0 29 `define r8b10b_enc_ibm_en_DP_TXPCS_IDX_0 30 `define rendec_tx_DP_TXPCS_IDX_0 31 // Table3: PCS Per Channel TX Control Register 3 for Channel 0 `define reserved_0_TB3_DP_TXPCS_IDX_0 32 `define rcid_len_tx_DP_TXPCS_IDX_0 33 `define rcid_len_tx_DP_TXPCS_IDX_1 34 `define rcid_len_tx_DP_TXPCS_IDX_2 35 `define rcid_len_tx_DP_TXPCS_IDX_3 36 `define rcid_len_tx_DP_TXPCS_IDX_4 37 `define rcid_len_tx_DP_TXPCS_IDX_5 38 `define rcid_len_tx_DP_TXPCS_IDX_6 39 `define rcid_len_tx_DP_TXPCS_IDX_7 40 `define rcid_pattern_tx_DP_TXPCS_IDX_0 41 `define rtxpcsclkpwdn_DP_TXPCS_IDX_0 42 `define rtxswing_sel_ena_DP_TXPCS_IDX_0 43 `define rtx_elec_idle_delay_DP_TXPCS_IDX_0 44 `define rtx_elec_idle_delay_DP_TXPCS_IDX_1 45 `define rtx_elec_idle_delay_DP_TXPCS_IDX_2 46 `define rtx_pipe_enable_DP_TXPCS_IDX_0 47 // Table4: PCS Per Channel TX Control Register 4 for Channel 0 `define reserved_0_TB4_DP_TXPCS_IDX_0 48 `define reserved_0_TB4_DP_TXPCS_IDX_1 49 `define reserved_0_TB4_DP_TXPCS_IDX_2 50 `define reserved_0_TB4_DP_TXPCS_IDX_3 51 `define reserved_0_TB4_DP_TXPCS_IDX_4 52 `define reserved_0_TB4_DP_TXPCS_IDX_5 53 `define reserved_0_TB4_DP_TXPCS_IDX_6 54 `define reserved_0_TB4_DP_TXPCS_IDX_7 55 `define reserved_0_TB4_DP_TXPCS_IDX_8 56 `define reserved_0_TB4_DP_TXPCS_IDX_9 57 `define reserved_0_TB4_DP_TXPCS_IDX_10 58 `define reserved_0_TB4_DP_TXPCS_IDX_11 59 `define rtxbitslip_en_DP_TXPCS_IDX_0 60 `define rphfifo_regmode_tx_DP_TXPCS_IDX_0 61 `define rpipeline_bypass_tx_DP_TXPCS_IDX_0 62 `define rself_sw_en_tx_DP_TXPCS_IDX_0 63 // Table5: PCS Per Channel RX Control Register 1 for Channel 0 `define rrxpcsbypass_en_DP_RXPCS_IDX_0 0 `define rall_one_dect_only_DP_RXPCS_IDX_0 1 `define rbist_clr_rx_DP_RXPCS_IDX_0 2 `define rbisten_rx_DP_RXPCS_IDX_0 3 `define rprbs_clr_rslt_rx_DP_RXPCS_IDX_0 4 `define rprbsen_rx_DP_RXPCS_IDX_0 5 `define rrx_rd_clk_sel_DP_RXPCS_IDX_0 6 `define rclk_2_sel_DP_RXPCS_IDX_0 7 `define rclk_2_sel_DP_RXPCS_IDX_1 8 `define rclk_1_sel_DP_RXPCS_IDX_0 9 `define rclk_1_sel_DP_RXPCS_IDX_1 10 `define rrcvd_clk_sel_DP_RXPCS_IDX_0 11 `define rrcvd_clk_sel_DP_RXPCS_IDX_1 12 `define rfreerun_rx_DP_RXPCS_IDX_0 13 `define rrxurstpcs_DP_RXPCS_IDX_0 14 `define reserved_0_TB5_DP_RXPCS_IDX_0 15 // Table6: PCS Per Channel RX Control Register 2 for Channel 0 `define rcomp_pat_32_DP_RXPCS_IDX_0 16 `define rcomp_pat_33_DP_RXPCS_IDX_0 17 `define rcomp_pat_34_DP_RXPCS_IDX_0 18 `define rcomp_pat_35_DP_RXPCS_IDX_0 19 `define rcomp_pat_36_DP_RXPCS_IDX_0 20 `define rcomp_pat_37_DP_RXPCS_IDX_0 21 `define rcomp_pat_38_DP_RXPCS_IDX_0 22 `define rcomp_pat_39_DP_RXPCS_IDX_0 23 `define rcomp_size_DP_RXPCS_IDX_0 24 `define rcomp_size_DP_RXPCS_IDX_1 25 `define rcomp_size_DP_RXPCS_IDX_2 26 `define rcomp_pat_porn_DP_RXPCS_IDX_0 27 `define rdis_rx_disp_DP_RXPCS_IDX_0 28 `define rencdt_rising_DP_RXPCS_IDX_0 29 `define resync_badcg_en_DP_RXPCS_IDX_0 30 `define resync_badcg_en_DP_RXPCS_IDX_1 31 // Table7: PCS Per Channel RX Control Register 3 for Channel 0 `define rcomp_pat_16_DP_RXPCS_IDX_0 32 `define rcomp_pat_17_DP_RXPCS_IDX_0 33 `define rcomp_pat_18_DP_RXPCS_IDX_0 34 `define rcomp_pat_19_DP_RXPCS_IDX_0 35 `define rcomp_pat_20_DP_RXPCS_IDX_0 36 `define rcomp_pat_21_DP_RXPCS_IDX_0 37 `define rcomp_pat_22_DP_RXPCS_IDX_0 38 `define rcomp_pat_23_DP_RXPCS_IDX_0 39 `define rcomp_pat_24_DP_RXPCS_IDX_0 40 `define rcomp_pat_25_DP_RXPCS_IDX_0 41 `define rcomp_pat_26_DP_RXPCS_IDX_0 42 `define rcomp_pat_27_DP_RXPCS_IDX_0 43 `define rcomp_pat_28_DP_RXPCS_IDX_0 44 `define rcomp_pat_29_DP_RXPCS_IDX_0 45 `define rcomp_pat_30_DP_RXPCS_IDX_0 46 `define rcomp_pat_31_DP_RXPCS_IDX_0 47 // Table8: PCS Per Channel RX Control Register 4 for Channel 0 `define rcomp_pat_0_DP_RXPCS_IDX_0 48 `define rcomp_pat_1_DP_RXPCS_IDX_0 49 `define rcomp_pat_2_DP_RXPCS_IDX_0 50 `define rcomp_pat_3_DP_RXPCS_IDX_0 51 `define rcomp_pat_4_DP_RXPCS_IDX_0 52 `define rcomp_pat_5_DP_RXPCS_IDX_0 53 `define rcomp_pat_6_DP_RXPCS_IDX_0 54 `define rcomp_pat_7_DP_RXPCS_IDX_0 55 `define rcomp_pat_8_DP_RXPCS_IDX_0 56 `define rcomp_pat_9_DP_RXPCS_IDX_0 57 `define rcomp_pat_10_DP_RXPCS_IDX_0 58 `define rcomp_pat_11_DP_RXPCS_IDX_0 59 `define rcomp_pat_12_DP_RXPCS_IDX_0 60 `define rcomp_pat_13_DP_RXPCS_IDX_0 61 `define rcomp_pat_14_DP_RXPCS_IDX_0 62 `define rcomp_pat_15_DP_RXPCS_IDX_0 63 // Table9: PCS Per Channel RX Control Register 5 for Channel 0 `define rbitloc_rev_en_DP_RXPCS_IDX_0 64 `define rbysync_polinv_en_DP_RXPCS_IDX_0 65 `define rwa_6g_en_DP_RXPCS_IDX_0 66 `define rosnumber_DP_RXPCS_IDX_0 67 `define rosnumber_DP_RXPCS_IDX_1 68 `define rosbased_DP_RXPCS_IDX_0 69 `define rkchar_DP_RXPCS_IDX_0 70 `define renumber_DP_RXPCS_IDX_0 71 `define renumber_DP_RXPCS_IDX_1 72 `define renumber_DP_RXPCS_IDX_2 73 `define renumber_DP_RXPCS_IDX_3 74 `define renumber_DP_RXPCS_IDX_4 75 `define renumber_DP_RXPCS_IDX_5 76 `define rib_inv_cd_DP_RXPCS_IDX_0 77 `define rib_inv_cd_DP_RXPCS_IDX_1 78 `define rsync_sm_dis_DP_RXPCS_IDX_0 79 // Table10: PCS Per Channel RX Control Register 6 for Channel 0 `define rknumber_DP_RXPCS_IDX_0 80 `define rknumber_DP_RXPCS_IDX_1 81 `define rknumber_DP_RXPCS_IDX_2 82 `define rknumber_DP_RXPCS_IDX_3 83 `define rknumber_DP_RXPCS_IDX_4 84 `define rknumber_DP_RXPCS_IDX_5 85 `define rknumber_DP_RXPCS_IDX_6 86 `define rknumber_DP_RXPCS_IDX_7 87 `define rgnumber_DP_RXPCS_IDX_0 88 `define rgnumber_DP_RXPCS_IDX_1 89 `define rgnumber_DP_RXPCS_IDX_2 90 `define rgnumber_DP_RXPCS_IDX_3 91 `define rgnumber_DP_RXPCS_IDX_4 92 `define rgnumber_DP_RXPCS_IDX_5 93 `define rgnumber_DP_RXPCS_IDX_6 94 `define rgnumber_DP_RXPCS_IDX_7 95 // Table11: PCS Per Channel RX Control Register 7 for Channel 0 `define renpolinv_rx_DP_RXPCS_IDX_0 96 `define rcascaded_8b10b_en_rx_DP_RXPCS_IDX_0 97 `define r8b10b_dec_ibm_en_DP_RXPCS_IDX_0 98 `define r8b10b_dec_ibm_en_DP_RXPCS_IDX_1 99 `define rendec_rx_DP_RXPCS_IDX_0 100 `define rautobtalg_dis_DP_RXPCS_IDX_0 101 `define rrlv_en_DP_RXPCS_IDX_0 102 `define rlp20ben_DP_RXPCS_IDX_0 103 `define rforce_sig_det_pcs_DP_RXPCS_IDX_0 104 `define rbyte_rev_en_DP_RXPCS_IDX_0 105 `define rrundisp_DP_RXPCS_IDX_0 106 `define rrundisp_DP_RXPCS_IDX_1 107 `define rrundisp_DP_RXPCS_IDX_2 108 `define rrundisp_DP_RXPCS_IDX_3 109 `define rrundisp_DP_RXPCS_IDX_4 110 `define rrundisp_DP_RXPCS_IDX_5 111 // Table12: PCS Per Channel RX Control Register 8 for Channel 0 `define rclkcmpsq1p_0_DP_RXPCS_IDX_0 112 `define rclkcmpsq1p_1_DP_RXPCS_IDX_0 113 `define rclkcmpsq1p_2_DP_RXPCS_IDX_0 114 `define rclkcmpsq1p_3_DP_RXPCS_IDX_0 115 `define rclkcmpsq1p_4_DP_RXPCS_IDX_0 116 `define rclkcmpsq1p_5_DP_RXPCS_IDX_0 117 `define rclkcmpsq1p_6_DP_RXPCS_IDX_0 118 `define rclkcmpsq1p_7_DP_RXPCS_IDX_0 119 `define rclkcmpsq1p_8_DP_RXPCS_IDX_0 120 `define rclkcmpsq1p_9_DP_RXPCS_IDX_0 121 `define rclkcmpsqmd_DP_RXPCS_IDX_0 122 `define rclkcmpinsertpad_DP_RXPCS_IDX_0 123 `define rtruebac2bac_DP_RXPCS_IDX_0 124 `define rskpsetbased_DP_RXPCS_IDX_0 125 `define rgenericfifo_DP_RXPCS_IDX_0 126 `define rmatchen_DP_RXPCS_IDX_0 127 // Table13: PCS Per Channel RX Control Register 9 for Channel 0 `define rclkcmpsq1p_10_DP_RXPCS_IDX_0 128 `define rclkcmpsq1p_11_DP_RXPCS_IDX_0 129 `define rclkcmpsq1p_12_DP_RXPCS_IDX_0 130 `define rclkcmpsq1p_13_DP_RXPCS_IDX_0 131 `define rclkcmpsq1p_14_DP_RXPCS_IDX_0 132 `define rclkcmpsq1p_15_DP_RXPCS_IDX_0 133 `define rclkcmpsq1p_16_DP_RXPCS_IDX_0 134 `define rclkcmpsq1p_17_DP_RXPCS_IDX_0 135 `define rclkcmpsq1p_18_DP_RXPCS_IDX_0 136 `define rclkcmpsq1p_19_DP_RXPCS_IDX_0 137 `define reserved_0_TB13_DP_RXPCS_IDX_0 138 `define rclkcmpsq1n_15_DP_RXPCS_IDX_0 139 `define rclkcmpsq1n_16_DP_RXPCS_IDX_0 140 `define rclkcmpsq1n_17_DP_RXPCS_IDX_0 141 `define rclkcmpsq1n_18_DP_RXPCS_IDX_0 142 `define rclkcmpsq1n_19_DP_RXPCS_IDX_0 143 // Table14: PCS Per Channel RX Control Register 10 for Channel 0 `define rclkcmpsq1n_0_DP_RXPCS_IDX_0 144 `define rclkcmpsq1n_1_DP_RXPCS_IDX_0 145 `define rclkcmpsq1n_2_DP_RXPCS_IDX_0 146 `define rclkcmpsq1n_3_DP_RXPCS_IDX_0 147 `define rclkcmpsq1n_4_DP_RXPCS_IDX_0 148 `define rclkcmpsq1n_5_DP_RXPCS_IDX_0 149 `define rclkcmpsq1n_6_DP_RXPCS_IDX_0 150 `define rclkcmpsq1n_7_DP_RXPCS_IDX_0 151 `define rclkcmpsq1n_8_DP_RXPCS_IDX_0 152 `define rclkcmpsq1n_9_DP_RXPCS_IDX_0 153 `define reserved_0_TB14_DP_RXPCS_IDX_0 154 `define rclkcmpsq1n_10_DP_RXPCS_IDX_0 155 `define rclkcmpsq1n_11_DP_RXPCS_IDX_0 156 `define rclkcmpsq1n_12_DP_RXPCS_IDX_0 157 `define rclkcmpsq1n_13_DP_RXPCS_IDX_0 158 `define rclkcmpsq1n_14_DP_RXPCS_IDX_0 159 // Table15: PCS Per Channel RX Control Register 11 for Channel 0 `define rfull_threshold_DP_RXPCS_IDX_0 160 `define rfull_threshold_DP_RXPCS_IDX_1 161 `define rfull_threshold_DP_RXPCS_IDX_2 162 `define rfull_threshold_DP_RXPCS_IDX_3 163 `define rfull_threshold_DP_RXPCS_IDX_4 164 `define rdel_threshold_DP_RXPCS_IDX_0 165 `define rdel_threshold_DP_RXPCS_IDX_1 166 `define rdel_threshold_DP_RXPCS_IDX_2 167 `define rdel_threshold_DP_RXPCS_IDX_3 168 `define rdel_threshold_DP_RXPCS_IDX_4 169 `define rins_threshold_DP_RXPCS_IDX_0 170 `define rins_threshold_DP_RXPCS_IDX_1 171 `define rins_threshold_DP_RXPCS_IDX_2 172 `define rins_threshold_DP_RXPCS_IDX_3 173 `define rins_threshold_DP_RXPCS_IDX_4 174 `define rclkcmp_pipe_en_DP_RXPCS_IDX_0 175 // Table16: PCS Per Channel RX Control Register 12 for Channel 0 `define rfreq_sel_DP_RXPCS_IDX_0 176 `define rauto_speed_ena_DP_RXPCS_IDX_0 177 `define rhip_ena_DP_RXPCS_IDX_0 178 `define rpma_done_gen_ena_DP_RXPCS_IDX_0 179 `define rpma_done_count_16_DP_RXPCS_IDX_0 180 `define rpma_done_count_17_DP_RXPCS_IDX_0 181 `define reserved_0_TB16_DP_RXPCS_IDX_0 182 `define reserved_0_TB16_DP_RXPCS_IDX_1 183 `define reserved_0_TB16_DP_RXPCS_IDX_2 184 `define reserved_0_TB16_DP_RXPCS_IDX_3 185 `define rstart_threshold_DP_RXPCS_IDX_0 186 `define rstart_threshold_DP_RXPCS_IDX_1 187 `define rstart_threshold_DP_RXPCS_IDX_2 188 `define rempty_threshold_DP_RXPCS_IDX_0 189 `define rempty_threshold_DP_RXPCS_IDX_1 190 `define rempty_threshold_DP_RXPCS_IDX_2 191 // Table17: PCS Per Channel RX Control Register 13 for Channel 0 `define rtest_bus_sel_DP_RXPCS_IDX_0 192 `define rtest_bus_sel_DP_RXPCS_IDX_1 193 `define rtest_bus_sel_DP_RXPCS_IDX_2 194 `define rtest_bus_sel_DP_RXPCS_IDX_3 195 `define rautoinsdis_DP_RXPCS_IDX_0 196 `define rphfifopldenrx_DP_RXPCS_IDX_0 197 `define rbytordplden_DP_RXPCS_IDX_0 198 `define rbyteorden_DP_RXPCS_IDX_0 199 `define rbyteorden_DP_RXPCS_IDX_1 200 `define rbytord_2sym_en_DP_RXPCS_IDX_0 201 `define rinvalid_code_err_only_DP_RXPCS_IDX_0 202 `define rcmpfifourst_DP_RXPCS_IDX_0 203 `define rphfifourstrx_DP_RXPCS_IDX_0 204 `define rdwidth_rx_DP_RXPCS_IDX_0 205 `define rrxfifo_lowlatency_en_DP_RXPCS_IDX_0 206 `define rrxfifo_dis_DP_RXPCS_IDX_0 207 // Table18: PCS Per Channel RX Control Register 14 for Channel 0 `define rbytordpat_0_DP_RXPCS_IDX_0 208 `define rbytordpat_1_DP_RXPCS_IDX_0 209 `define rbytordpat_2_DP_RXPCS_IDX_0 210 `define rbytordpat_3_DP_RXPCS_IDX_0 211 `define rbytordpat_4_DP_RXPCS_IDX_0 212 `define rbytordpat_5_DP_RXPCS_IDX_0 213 `define rbytordpat_6_DP_RXPCS_IDX_0 214 `define rbytordpat_7_DP_RXPCS_IDX_0 215 `define rbytordpat_8_DP_RXPCS_IDX_0 216 `define rbytordpat_9_DP_RXPCS_IDX_0 217 `define reserved_0_TB18_DP_RXPCS_IDX_0 218 `define reserved_0_TB18_DP_RXPCS_IDX_1 219 `define reserved_0_TB18_DP_RXPCS_IDX_2 220 `define reserved_0_TB18_DP_RXPCS_IDX_3 221 `define reserved_0_TB18_DP_RXPCS_IDX_4 222 `define reserved_0_TB18_DP_RXPCS_IDX_5 223 // Table19: PCS Per Channel RX Control Register 15 for Channel 0 `define rbytordpad_DP_RXPCS_IDX_0 224 `define rbytordpad_DP_RXPCS_IDX_1 225 `define rbytordpad_DP_RXPCS_IDX_2 226 `define rbytordpad_DP_RXPCS_IDX_3 227 `define rbytordpad_DP_RXPCS_IDX_4 228 `define rbytordpad_DP_RXPCS_IDX_5 229 `define rbytordpad_DP_RXPCS_IDX_6 230 `define rbytordpad_DP_RXPCS_IDX_7 231 `define rbytordpad_DP_RXPCS_IDX_8 232 `define rbytordpad_DP_RXPCS_IDX_9 233 `define reserved_0_TB19_DP_RXPCS_IDX_0 234 `define reserved_0_TB19_DP_RXPCS_IDX_1 235 `define reserved_0_TB19_DP_RXPCS_IDX_2 236 `define reserved_0_TB19_DP_RXPCS_IDX_3 237 `define reserved_0_TB19_DP_RXPCS_IDX_4 238 `define reserved_0_TB19_DP_RXPCS_IDX_5 239 // Table20: PCS Per Channel RX Control Register 16 for Channel 0 `define rload_shreg_del_DP_RXPCS_IDX_0 240 `define rload_shreg_del_DP_RXPCS_IDX_1 241 `define rload_shreg_del_DP_RXPCS_IDX_2 242 `define rload_shreg_del_DP_RXPCS_IDX_3 243 `define rload_shreg_del_DP_RXPCS_IDX_4 244 `define rphystatus_rst_toggle_DP_RXPCS_IDX_0 245 `define reidle_com_detect_DP_RXPCS_IDX_0 246 `define reidle_com_detect_DP_RXPCS_IDX_1 247 `define rk285detect_DP_RXPCS_IDX_0 248 `define reidleinferenable_DP_RXPCS_IDX_0 249 `define rphystatus_delay_DP_RXPCS_IDX_0 250 `define rphystatus_delay_DP_RXPCS_IDX_1 251 `define rphystatus_delay_DP_RXPCS_IDX_2 252 `define rind_error_reporting_DP_RXPCS_IDX_0 253 `define rrx_detect_bypass_DP_RXPCS_IDX_0 254 `define rrx_pipe_enable_DP_RXPCS_IDX_0 255 // Table21: PCS Per Channel RX Control Register 17 for Channel 0 `define rpma_done_count_0_DP_RXPCS_IDX_0 256 `define rpma_done_count_1_DP_RXPCS_IDX_0 257 `define rpma_done_count_2_DP_RXPCS_IDX_0 258 `define rpma_done_count_3_DP_RXPCS_IDX_0 259 `define rpma_done_count_4_DP_RXPCS_IDX_0 260 `define rpma_done_count_5_DP_RXPCS_IDX_0 261 `define rpma_done_count_6_DP_RXPCS_IDX_0 262 `define rpma_done_count_7_DP_RXPCS_IDX_0 263 `define rpma_done_count_8_DP_RXPCS_IDX_0 264 `define rpma_done_count_9_DP_RXPCS_IDX_0 265 `define rpma_done_count_10_DP_RXPCS_IDX_0 266 `define rpma_done_count_11_DP_RXPCS_IDX_0 267 `define rpma_done_count_12_DP_RXPCS_IDX_0 268 `define rpma_done_count_13_DP_RXPCS_IDX_0 269 `define rpma_done_count_14_DP_RXPCS_IDX_0 270 `define rpma_done_count_15_DP_RXPCS_IDX_0 271 // Table22: PCS Per Channel RX Control Register 18 for Channel 0 `define rbytordpat_10_DP_RXPCS_IDX_0 272 `define rbytordpat_11_DP_RXPCS_IDX_0 273 `define rbytordpat_12_DP_RXPCS_IDX_0 274 `define rbytordpat_13_DP_RXPCS_IDX_0 275 `define rbytordpat_14_DP_RXPCS_IDX_0 276 `define rbytordpat_15_DP_RXPCS_IDX_0 277 `define rbytordpat_16_DP_RXPCS_IDX_0 278 `define rbytordpat_17_DP_RXPCS_IDX_0 279 `define rbytordpat_18_DP_RXPCS_IDX_0 280 `define rbytordpat_19_DP_RXPCS_IDX_0 281 `define rbytord_6g_mask_en_DP_RXPCS_IDX_0 282 `define rbytord_s2gx_DP_RXPCS_IDX_0 283 `define reserved_0_TB22_DP_RXPCS_IDX_0 284 `define rcdr_ctrl_en_DP_RXPCS_IDX_0 285 `define rrxpcsclkpwdn_DP_RXPCS_IDX_0 286 `define rerr_flags_sel_DP_RXPCS_IDX_0 287 // Table23: PCS Per Channel RX Control Register 19 for Channel 0 `define rwait_count_DP_RXPCS_IDX_0 288 `define rwait_count_DP_RXPCS_IDX_1 289 `define rwait_count_DP_RXPCS_IDX_2 290 `define rwait_count_DP_RXPCS_IDX_3 291 `define rwait_count_DP_RXPCS_IDX_4 292 `define rwait_count_DP_RXPCS_IDX_5 293 `define rwait_count_DP_RXPCS_IDX_6 294 `define rwait_count_DP_RXPCS_IDX_7 295 `define reserved_0_TB23_DP_RXPCS_IDX_0 296 `define reserved_0_TB23_DP_RXPCS_IDX_1 297 `define reserved_0_TB23_DP_RXPCS_IDX_2 298 `define reserved_0_TB23_DP_RXPCS_IDX_3 299 `define reserved_0_TB23_DP_RXPCS_IDX_4 300 `define reserved_0_TB23_DP_RXPCS_IDX_5 301 `define reserved_0_TB23_DP_RXPCS_IDX_6 302 `define reserved_0_TB23_DP_RXPCS_IDX_7 303 // Table24: PCS Per Channel RX Control Register 20 for Channel 0 `define rfts_count_DP_RXPCS_IDX_0 304 `define rfts_count_DP_RXPCS_IDX_1 305 `define rfts_count_DP_RXPCS_IDX_2 306 `define rfts_count_DP_RXPCS_IDX_3 307 `define rfts_count_DP_RXPCS_IDX_4 308 `define rfts_count_DP_RXPCS_IDX_5 309 `define rfts_count_DP_RXPCS_IDX_6 310 `define rfts_count_DP_RXPCS_IDX_7 311 `define rfts_count_DP_RXPCS_IDX_8 312 `define rfts_count_DP_RXPCS_IDX_9 313 `define rwait_for_phfifo_cnt_DP_RXPCS_IDX_0 314 `define rwait_for_phfifo_cnt_DP_RXPCS_IDX_1 315 `define rwait_for_phfifo_cnt_DP_RXPCS_IDX_2 316 `define rwait_for_phfifo_cnt_DP_RXPCS_IDX_3 317 `define rwait_for_phfifo_cnt_DP_RXPCS_IDX_4 318 `define rwait_for_phfifo_cnt_DP_RXPCS_IDX_5 319 // Table25: PCS Per Channel RX Control Register 21 for Channel 0 `define rppm_meas_delay_DP_RXPCS_IDX_0 320 `define rcid_len_rx_DP_RXPCS_IDX_0 321 `define rcid_len_rx_DP_RXPCS_IDX_1 322 `define rcid_len_rx_DP_RXPCS_IDX_2 323 `define rcid_len_rx_DP_RXPCS_IDX_3 324 `define rcid_len_rx_DP_RXPCS_IDX_4 325 `define rcid_len_rx_DP_RXPCS_IDX_5 326 `define rcid_len_rx_DP_RXPCS_IDX_6 327 `define rcid_len_rx_DP_RXPCS_IDX_7 328 `define rcid_pattern_rx_DP_RXPCS_IDX_0 329 `define rpcs_wrapback_en_DP_RXPCS_IDX_0 330 `define reserved_0_TB25_DP_RXPCS_IDX_0 331 `define reserved_0_TB25_DP_RXPCS_IDX_1 332 `define reserved_0_TB25_DP_RXPCS_IDX_2 333 `define reserved_0_TB25_DP_RXPCS_IDX_3 334 `define reserved_0_TB25_DP_RXPCS_IDX_4 335 // Table26: PCS Per Channel RX Control Register 22 for Channel 0 `define rauto_pc_en_cnt_DP_RXPCS_IDX_0 336 `define rauto_pc_en_cnt_DP_RXPCS_IDX_1 337 `define rauto_pc_en_cnt_DP_RXPCS_IDX_2 338 `define rauto_pc_en_cnt_DP_RXPCS_IDX_3 339 `define rauto_pc_en_cnt_DP_RXPCS_IDX_4 340 `define reserved_1_TB26_DP_RXPCS_IDX_0 341 `define rauto_deassert_pc_rst_cnt_DP_RXPCS_IDX_0 342 `define rauto_deassert_pc_rst_cnt_DP_RXPCS_IDX_1 343 `define rauto_deassert_pc_rst_cnt_DP_RXPCS_IDX_2 344 `define rauto_deassert_pc_rst_cnt_DP_RXPCS_IDX_3 345 `define reserved_0_TB26_DP_RXPCS_IDX_0 346 `define rpipeline_bypass_rx_DP_RXPCS_IDX_0 347 `define rself_sw_en_rx_DP_RXPCS_IDX_0 348 `define rrxvalid_mask_DP_RXPCS_IDX_0 349 `define rcid_en_DP_RXPCS_IDX_0 350 `define rphfifo_regmode_rx_DP_RXPCS_IDX_0 351 // Table27: PCS Per Channel RX Control Register 23 for Channel 0 `define rmask_count_DP_RXPCS_IDX_0 352 `define rmask_count_DP_RXPCS_IDX_1 353 `define rmask_count_DP_RXPCS_IDX_2 354 `define rmask_count_DP_RXPCS_IDX_3 355 `define rmask_count_DP_RXPCS_IDX_4 356 `define rmask_count_DP_RXPCS_IDX_5 357 `define rmask_count_DP_RXPCS_IDX_6 358 `define rmask_count_DP_RXPCS_IDX_7 359 `define rmask_count_DP_RXPCS_IDX_8 360 `define rmask_count_DP_RXPCS_IDX_9 361 `define rgen1_sigdet_ena_DP_RXPCS_IDX_0 362 `define riei_eios_priority_dis_DP_RXPCS_IDX_0 363 `define reserved_0_TB27_DP_RXPCS_IDX_0 364 `define reserved_0_TB27_DP_RXPCS_IDX_1 365 `define reserved_0_TB27_DP_RXPCS_IDX_2 366 `define reserved_0_TB27_DP_RXPCS_IDX_3 367 // TXPMA // Table28: PMA Per Channel TX Control Register 1 for Channel 0 `define rpowdnt_DP_TXPMA_IDX_0 0 `define rvod_seld_DP_TXPMA_IDX_0 1 `define rvod_seld_DP_TXPMA_IDX_1 2 `define rvod_seld_DP_TXPMA_IDX_2 3 `define rvod_selc_DP_TXPMA_IDX_0 4 `define rvod_selc_DP_TXPMA_IDX_1 5 `define rvod_selc_DP_TXPMA_IDX_2 6 `define rvod_selb_DP_TXPMA_IDX_0 7 `define rvod_selb_DP_TXPMA_IDX_1 8 `define rvod_selb_DP_TXPMA_IDX_2 9 `define rvod_sela_DP_TXPMA_IDX_0 10 `define rvod_sela_DP_TXPMA_IDX_1 11 `define rvod_sela_DP_TXPMA_IDX_2 12 `define rvod_sel_non_pcie_DP_TXPMA_IDX_0 13 `define rvod_sel_non_pcie_DP_TXPMA_IDX_1 14 `define rvod_sel_non_pcie_DP_TXPMA_IDX_2 15 // Table29: PMA Per Channel TX Control Register 2 for Channel 0 `define reserved_0_TB29_DP_TXPMA_IDX_0 16 `define rpre_em_1t_b_DP_TXPMA_IDX_0 17 `define rpre_em_1t_b_DP_TXPMA_IDX_1 18 `define rpre_em_1t_b_DP_TXPMA_IDX_2 19 `define rpre_em_1t_b_DP_TXPMA_IDX_3 20 `define rpre_em_1t_b_DP_TXPMA_IDX_4 21 `define rpre_em_1t_a_DP_TXPMA_IDX_0 22 `define rpre_em_1t_a_DP_TXPMA_IDX_1 23 `define rpre_em_1t_a_DP_TXPMA_IDX_2 24 `define rpre_em_1t_a_DP_TXPMA_IDX_3 25 `define rpre_em_1t_a_DP_TXPMA_IDX_4 26 `define rpre_em_1t_no_pcie_DP_TXPMA_IDX_0 27 `define rpre_em_1t_no_pcie_DP_TXPMA_IDX_1 28 `define rpre_em_1t_no_pcie_DP_TXPMA_IDX_2 29 `define rpre_em_1t_no_pcie_DP_TXPMA_IDX_3 30 `define rpre_em_1t_no_pcie_DP_TXPMA_IDX_4 31 // Table30: PMA Per Channel TX Control Register 3 for Channel 0 `define rpre_em_pt_DP_TXPMA_IDX_0 32 `define rpre_em_pt_DP_TXPMA_IDX_1 33 `define rpre_em_pt_DP_TXPMA_IDX_2 34 `define rpre_em_pt_DP_TXPMA_IDX_3 35 `define rpre_em_2t_DP_TXPMA_IDX_0 36 `define rpre_em_2t_DP_TXPMA_IDX_1 37 `define rpre_em_2t_DP_TXPMA_IDX_2 38 `define rpre_em_2t_DP_TXPMA_IDX_3 39 `define rpre_em_1t_c_DP_TXPMA_IDX_0 40 `define rpre_em_1t_c_DP_TXPMA_IDX_1 41 `define rpre_em_1t_c_DP_TXPMA_IDX_2 42 `define rpre_em_1t_c_DP_TXPMA_IDX_3 43 `define rpre_em_1t_c_DP_TXPMA_IDX_4 44 `define reserved_0_TB30_DP_TXPMA_IDX_0 45 `define reserved_0_TB30_DP_TXPMA_IDX_1 46 `define reserved_0_TB30_DP_TXPMA_IDX_2 47 // Table31: PMA Per Channel TX Control Register 4 for Channel 0 `define rlowv_DP_TXPMA_IDX_0 48 `define rrx_det_DP_TXPMA_IDX_0 49 `define rrx_det_DP_TXPMA_IDX_1 50 `define rsig_inv_2t_DP_TXPMA_IDX_0 51 `define rsig_inv_ptap_DP_TXPMA_IDX_0 52 `define rslew_DP_TXPMA_IDX_0 53 `define rslew_DP_TXPMA_IDX_1 54 `define rtx_lst_DP_TXPMA_IDX_0 55 `define rtx_lst_DP_TXPMA_IDX_1 56 `define rtx_lst_DP_TXPMA_IDX_2 57 `define rtx_lst_DP_TXPMA_IDX_3 58 `define rtx_vtt_DP_TXPMA_IDX_0 59 `define rtx_vtt_DP_TXPMA_IDX_1 60 `define rtx_term_sel_DP_TXPMA_IDX_0 61 `define rtx_term_sel_DP_TXPMA_IDX_1 62 `define rtx_term_sel_DP_TXPMA_IDX_2 63 // Table32: PMA Per Channel TX Control Register 5 for Channel 0 `define reserved_1_TB32_DP_TXPMA_IDX_0 64 `define reserved_1_TB32_DP_TXPMA_IDX_1 65 `define reserved_1_TB32_DP_TXPMA_IDX_2 66 `define reserved_1_TB32_DP_TXPMA_IDX_3 67 `define reserved_1_TB32_DP_TXPMA_IDX_4 68 `define reserved_1_TB32_DP_TXPMA_IDX_5 69 `define reserved_1_TB32_DP_TXPMA_IDX_6 70 `define reserved_1_TB32_DP_TXPMA_IDX_7 71 `define reserved_1_TB32_DP_TXPMA_IDX_8 72 `define reserved_1_TB32_DP_TXPMA_IDX_9 73 `define reserved_1_TB32_DP_TXPMA_IDX_10 74 `define rtx_ob_pdb_DP_TXPMA_IDX_0 75 `define reserved_0_TB32_DP_TXPMA_IDX_0 76 `define r_dft_sel_DP_TXPMA_IDX_0 77 `define r_dft_sel_DP_TXPMA_IDX_1 78 `define r_dft_sel_DP_TXPMA_IDX_2 79 // Table33: PMA Per Channel TX Control Register 6 for Channel 0 `define reserved_0_TB33_DP_TXPMA_IDX_0 80 `define reserved_0_TB33_DP_TXPMA_IDX_1 81 `define reserved_0_TB33_DP_TXPMA_IDX_2 82 `define reserved_0_TB33_DP_TXPMA_IDX_3 83 `define rtx_cgb_pdb_DP_TXPMA_IDX_0 84 `define rpclksel_DP_TXPMA_IDX_0 85 `define rdynamic_sw_DP_TXPMA_IDX_0 86 `define rs_lpbk_DP_TXPMA_IDX_0 87 `define rcgb_delay_sel_DP_TXPMA_IDX_0 88 `define rpmadwidth_tx_DP_TXPMA_IDX_0 89 `define rpma_doublewidth_tx_DP_TXPMA_IDX_0 90 `define rcgb_m_sel_DP_TXPMA_IDX_0 91 `define rcgb_m_sel_DP_TXPMA_IDX_1 92 `define rcgb_cmu_sel_DP_TXPMA_IDX_0 93 `define rcgb_x_en_DP_TXPMA_IDX_0 94 `define rcgb_x_en_DP_TXPMA_IDX_1 95 // Table34: PMA Per Channel TX Control Register 7 for Channel 0 `define reserved_1_TB34_DP_TXPMA_IDX_0 96 `define reserved_1_TB34_DP_TXPMA_IDX_1 97 `define reserved_1_TB34_DP_TXPMA_IDX_2 98 `define rpcs_sd_sel_DP_TXPMA_IDX_0 99 `define rrx_refclk_DP_TXPMA_IDX_0 100 `define rimpctrl_DP_TXPMA_IDX_0 101 `define reserved_0_TB34_DP_TXPMA_IDX_0 102 `define reserved_0_TB34_DP_TXPMA_IDX_1 103 `define reserved_0_TB34_DP_TXPMA_IDX_2 104 `define reserved_0_TB34_DP_TXPMA_IDX_3 105 `define rrevlb_sw_DP_TXPMA_IDX_0 106 `define rvcobypass_DP_TXPMA_IDX_0 107 `define rrefclk_sel_DP_TXPMA_IDX_0 108 `define rrefclk_sel_DP_TXPMA_IDX_1 109 `define riqclk_sel_DP_TXPMA_IDX_0 110 `define riqclk_sel_DP_TXPMA_IDX_1 111 // Table35: PMA Per Channel TX Control Register 8 for Channel 0 `define rpma_reserved_0_TB35_DP_TXPMA_IDX_0 112 `define rpma_reserved_0_TB35_DP_TXPMA_IDX_1 113 `define rpma_reserved_0_TB35_DP_TXPMA_IDX_2 114 `define rpma_reserved_0_TB35_DP_TXPMA_IDX_3 115 `define rpma_reserved_0_TB35_DP_TXPMA_IDX_4 116 `define rpma_reserved_0_TB35_DP_TXPMA_IDX_5 117 `define rpma_reserved_0_TB35_DP_TXPMA_IDX_6 118 `define rpma_reserved_0_TB35_DP_TXPMA_IDX_7 119 `define rpma_reserved_0_TB35_DP_TXPMA_IDX_8 120 `define rpma_reserved_0_TB35_DP_TXPMA_IDX_9 121 `define rpma_reserved_0_TB35_DP_TXPMA_IDX_10 122 `define rpma_reserved_0_TB35_DP_TXPMA_IDX_11 123 `define rpma_reserved_0_TB35_DP_TXPMA_IDX_12 124 `define rpma_reserved_0_TB35_DP_TXPMA_IDX_13 125 `define rpma_reserved_0_TB35_DP_TXPMA_IDX_14 126 `define rpma_reserved_0_TB35_DP_TXPMA_IDX_15 127 // Table36: PMA Per Channel RX Control Register 1 for Channel 0 `define rrx_term_sel_DP_RXPMA_IDX_0 0 `define rrx_term_sel_DP_RXPMA_IDX_1 1 `define rrx_term_sel_DP_RXPMA_IDX_2 2 `define rrx_vtt_DP_RXPMA_IDX_0 3 `define rrx_vtt_DP_RXPMA_IDX_1 4 `define rrx_vtt_DP_RXPMA_IDX_2 5 `define rrx_s_rdlpbk_DP_RXPMA_IDX_0 6 `define rrx_bit_dc_DP_RXPMA_IDX_0 7 `define rrx_bit_dc_DP_RXPMA_IDX_1 8 `define rrx_bit_dc_DP_RXPMA_IDX_2 9 `define rrx_bit_dc_DP_RXPMA_IDX_3 10 `define rrx_lst_DP_RXPMA_IDX_0 11 `define rrx_lst_DP_RXPMA_IDX_1 12 `define rrx_lst_DP_RXPMA_IDX_2 13 `define rrx_lst_DP_RXPMA_IDX_3 14 `define rrx_lst_DP_RXPMA_IDX_4 15 // Table37: PMA Per Channel RX Control Register 2 for Channel 0 `define rrxurstpma_DP_RXPMA_IDX_0 16 `define rrx_test_DP_RXPMA_IDX_0 17 `define rrx_sd_force_DP_RXPMA_IDX_0 18 `define rrx_oc_DP_RXPMA_IDX_0 19 `define rrx_oc_DP_RXPMA_IDX_1 20 `define rrx_oc_DP_RXPMA_IDX_2 21 `define rrx_oc_DP_RXPMA_IDX_3 22 `define rrx_oc_DP_RXPMA_IDX_4 23 `define rrx_oc_DP_RXPMA_IDX_5 24 `define rrx_oc_DP_RXPMA_IDX_6 25 `define rrx_oc_DP_RXPMA_IDX_7 26 `define rrx_oc_en_DP_RXPMA_IDX_0 27 `define rrx_sdlv_DP_RXPMA_IDX_0 28 `define rrx_sdlv_DP_RXPMA_IDX_1 29 `define rrx_sdlv_DP_RXPMA_IDX_2 30 `define rrx_sdlv_DP_RXPMA_IDX_3 31 // Table38: PMA Per Channel RX Control Register 3 for Channel 0 `define reserved_0_TB38_DP_RXPMA_IDX_0 32 `define reserved_0_TB38_DP_RXPMA_IDX_1 33 `define reserved_0_TB38_DP_RXPMA_IDX_2 34 `define rpowdnr_DP_RXPMA_IDX_0 35 `define rrx_ib_pdb_DP_RXPMA_IDX_0 36 `define rurx_pdb_DP_RXPMA_IDX_0 37 `define rrx_oc_calpd_DP_RXPMA_IDX_0 38 `define rrx_sd_off_DP_RXPMA_IDX_0 39 `define rrx_sd_off_DP_RXPMA_IDX_1 40 `define rrx_sd_off_DP_RXPMA_IDX_2 41 `define rrx_sd_off_DP_RXPMA_IDX_3 42 `define rrx_sd_off_DP_RXPMA_IDX_4 43 `define rrx_sd_on_DP_RXPMA_IDX_0 44 `define rrx_sd_on_DP_RXPMA_IDX_1 45 `define rrx_sd_on_DP_RXPMA_IDX_2 46 `define rrx_sd_on_DP_RXPMA_IDX_3 47 // Table39: PMA Per Channel RX Control Register 4 for Channel 0 (PLL) `define rcru_pdbwctrl_DP_PLL_IDX_0 0 `define rcru_pdbwctrl_DP_PLL_IDX_1 1 `define rcru_pfdbwctrl_DP_PLL_IDX_0 2 `define rcru_pfdbwctrl_DP_PLL_IDX_1 3 `define rcru_crplctrl_DP_PLL_IDX_0 4 `define rcru_crplctrl_DP_PLL_IDX_1 5 `define rcru_ctl0_DP_PLL_IDX_0 6 `define rcru_l_DP_PLL_IDX_0 7 `define rcru_l_DP_PLL_IDX_1 8 `define rcru_m_DP_PLL_IDX_0 9 `define rcru_m_DP_PLL_IDX_1 10 `define rcru_m_DP_PLL_IDX_2 11 `define rcru_m_DP_PLL_IDX_3 12 `define rcru_m_sel_DP_PLL_IDX_0 13 `define rcru_m_sel_DP_PLL_IDX_1 14 `define rcru_div2_DP_PLL_IDX_0 15 // Table40: PMA Per Channel RX Control Register 5 for Channel 0 (PLL) `define reserved_0_TB40_DP_PLL_IDX_0 16 `define reserved_0_TB40_DP_PLL_IDX_1 17 `define rcru_iselpd_DP_PLL_IDX_0 18 `define rcru_iselpd_DP_PLL_IDX_1 19 `define rcru_iselpd_DP_PLL_IDX_2 20 `define rcru_isel_DP_PLL_IDX_0 21 `define rcru_isel_DP_PLL_IDX_1 22 `define rcru_isel_DP_PLL_IDX_2 23 `define rcru_testdnen_DP_PLL_IDX_0 24 `define rcru_testupen_DP_PLL_IDX_0 25 `define rcru_testen_DP_PLL_IDX_0 26 `define rcru_lst_DP_PLL_IDX_0 27 `define rcru_lst_DP_PLL_IDX_1 28 `define rcru_lst_DP_PLL_IDX_2 29 `define rcru_lst_DP_PLL_IDX_3 30 `define rcru_rlbk_DP_PLL_IDX_0 31 // Table41: PMA Per Channel RX Control Register 6 for Channel 0 (PLL) `define rcru_rgla_isel_DP_PLL_IDX_0 32 `define rcru_rgla_isel_DP_PLL_IDX_1 33 `define rcru_rgla_isel_DP_PLL_IDX_2 34 `define rcru_pdof_test_DP_PLL_IDX_0 35 `define rcru_pdof_test_DP_PLL_IDX_1 36 `define rcru_pdof_test_DP_PLL_IDX_2 37 `define rcru_pdfl_DP_PLL_IDX_0 38 `define rcru_sd_sel_DP_PLL_IDX_0 39 `define reserved_0_TB41_DP_PLL_IDX_0 40 `define rcru_ignore_phslck_DP_PLL_IDX_0 41 `define rcru_cmu_mode_DP_PLL_IDX_0 42 `define rrx_cru_rst_DP_PLL_IDX_0 43 `define rrx_cru_pdb_DP_PLL_IDX_0 44 `define rltr_DP_PLL_IDX_0 45 `define rltd_DP_PLL_IDX_0 46 `define rcp_mode_DP_PLL_IDX_0 47 // Table42: PMA Per Channel RX Control Register 7 for Channel 0 (PLL) `define rcru_pdof_270i_DP_PLL_IDX_0 48 `define rcru_pdof_270i_DP_PLL_IDX_1 49 `define rcru_pdof_270i_DP_PLL_IDX_2 50 `define rcru_pdof_270i_DP_PLL_IDX_3 51 `define rcru_pdof_180i_DP_PLL_IDX_0 52 `define rcru_pdof_180i_DP_PLL_IDX_1 53 `define rcru_pdof_180i_DP_PLL_IDX_2 54 `define rcru_pdof_180i_DP_PLL_IDX_3 55 `define rcru_pdof_90i_DP_PLL_IDX_0 56 `define rcru_pdof_90i_DP_PLL_IDX_1 57 `define rcru_pdof_90i_DP_PLL_IDX_2 58 `define rcru_pdof_90i_DP_PLL_IDX_3 59 `define rcru_pdof_0i_DP_PLL_IDX_0 60 `define rcru_pdof_0i_DP_PLL_IDX_1 61 `define rcru_pdof_0i_DP_PLL_IDX_2 62 `define rcru_pdof_0i_DP_PLL_IDX_3 63 // Table43: PMA Per Channel RX Control Register 8 for Channel 0 `define reye_monitor_DP_RXPMA_IDX_0 112 `define reye_monitor_DP_RXPMA_IDX_1 113 `define reye_monitor_DP_RXPMA_IDX_2 114 `define reye_monitor_DP_RXPMA_IDX_3 115 `define reye_monitor_DP_RXPMA_IDX_4 116 `define reye_monitor_DP_RXPMA_IDX_5 117 `define reye_monitor_DP_RXPMA_IDX_6 118 `define reye_monitor_DP_RXPMA_IDX_7 119 `define reserved_0_TB43_DP_RXPMA_IDX_0 120 `define reserved_0_TB43_DP_RXPMA_IDX_1 121 `define reserved_0_TB43_DP_RXPMA_IDX_2 122 `define reserved_0_TB43_DP_RXPMA_IDX_3 123 `define reserved_0_TB43_DP_RXPMA_IDX_4 124 `define reserved_0_TB43_DP_RXPMA_IDX_5 125 `define reserved_0_TB43_DP_RXPMA_IDX_6 126 `define reserved_0_TB43_DP_RXPMA_IDX_7 127 // Table44: PMA Per Channel RX Control Register 9 for Channel 0 `define rpma_reserved_0_TB44_DP_RXPMA_IDX_0 128 `define rpma_reserved_0_TB44_DP_RXPMA_IDX_1 129 `define rpma_reserved_0_TB44_DP_RXPMA_IDX_2 130 `define rpma_reserved_0_TB44_DP_RXPMA_IDX_3 131 `define rpma_reserved_0_TB44_DP_RXPMA_IDX_4 132 `define rpma_reserved_0_TB44_DP_RXPMA_IDX_5 133 `define rpma_reserved_0_TB44_DP_RXPMA_IDX_6 134 `define rpma_reserved_0_TB44_DP_RXPMA_IDX_7 135 `define rpma_reserved_0_TB44_DP_RXPMA_IDX_8 136 `define rpma_reserved_0_TB44_DP_RXPMA_IDX_9 137 `define rpma_reserved_0_TB44_DP_RXPMA_IDX_10 138 `define rpma_reserved_0_TB44_DP_RXPMA_IDX_11 139 `define rpma_reserved_0_TB44_DP_RXPMA_IDX_12 140 `define rpma_reserved_0_TB44_DP_RXPMA_IDX_13 141 `define rpma_reserved_0_TB44_DP_RXPMA_IDX_14 142 `define rpma_reserved_0_TB44_DP_RXPMA_IDX_15 143 // Table45: PMA Per Channel RX Control Register 10 for Channel 0 `define rppm_cnt_reset_DP_RXPMA_IDX_0 144 `define rforce1_freqdet_DP_RXPMA_IDX_0 145 `define rforce0_freqdet_DP_RXPMA_IDX_0 146 `define rppmsel_DP_RXPMA_IDX_0 147 `define rppmsel_DP_RXPMA_IDX_1 148 `define rppmsel_DP_RXPMA_IDX_2 149 `define rppmsel_DP_RXPMA_IDX_3 150 `define rppmsel_DP_RXPMA_IDX_4 151 `define rppmsel_DP_RXPMA_IDX_5 152 `define rfastsd_DP_RXPMA_IDX_0 153 `define rfastsd_DP_RXPMA_IDX_1 154 `define rfastsd_DP_RXPMA_IDX_2 155 `define rfastsd_DP_RXPMA_IDX_3 156 `define rtest_fastsd_DP_RXPMA_IDX_0 157 `define rpmadwidth_rx_DP_RXPMA_IDX_0 158 `define rpma_doublewidth_rx_DP_RXPMA_IDX_0 159 // Table46: PMA Per Channel RX Control Register 11 for Channel 0 `define reserved_0_TB46_DP_RXPMA_IDX_0 160 `define reserved_0_TB46_DP_RXPMA_IDX_1 161 `define reserved_0_TB46_DP_RXPMA_IDX_2 162 `define reserved_0_TB46_DP_RXPMA_IDX_3 163 `define reserved_0_TB46_DP_RXPMA_IDX_4 164 `define reserved_0_TB46_DP_RXPMA_IDX_5 165 `define reserved_0_TB46_DP_RXPMA_IDX_6 166 `define reserved_0_TB46_DP_RXPMA_IDX_7 167 `define rppm_gen1_2xcnt_en_DP_RXPMA_IDX_0 168 `define rppm_post_eidle_del_DP_RXPMA_IDX_0 169 `define r_dfe_2t_DP_RXPMA_IDX_0 170 `define r_dfe_2t_DP_RXPMA_IDX_1 171 `define r_dfe_2t_DP_RXPMA_IDX_2 172 `define r_dfe_1t_DP_RXPMA_IDX_0 173 `define r_dfe_1t_DP_RXPMA_IDX_1 174 `define r_dfe_1t_DP_RXPMA_IDX_2 175 // Table47: PMA Per Channel RX Control Register 12 for Channel 0 `define reqv_set_DP_RXPMA_IDX_0 176 `define reqv_set_DP_RXPMA_IDX_1 177 `define reqv_set_DP_RXPMA_IDX_2 178 `define reqd_set_DP_RXPMA_IDX_0 179 `define reqd_set_DP_RXPMA_IDX_1 180 `define reqd_set_DP_RXPMA_IDX_2 181 `define reqc_set_DP_RXPMA_IDX_0 182 `define reqc_set_DP_RXPMA_IDX_1 183 `define reqc_set_DP_RXPMA_IDX_2 184 `define reqb_set_DP_RXPMA_IDX_0 185 `define reqb_set_DP_RXPMA_IDX_1 186 `define reqb_set_DP_RXPMA_IDX_2 187 `define reqa_set_DP_RXPMA_IDX_0 188 `define reqa_set_DP_RXPMA_IDX_1 189 `define reqa_set_DP_RXPMA_IDX_2 190 `define reserved_0_TB47_DP_RXPMA_IDX_0 191 // Table48: PMA Per Channel RX Control Register 13 for Channel 0 `define rdc_freq_DP_RXPMA_IDX_0 192 `define rdc_freq_DP_RXPMA_IDX_1 193 `define rhyst_lf_DP_RXPMA_IDX_0 194 `define rhyst_lf_DP_RXPMA_IDX_1 195 `define rhyst_lf_DP_RXPMA_IDX_2 196 `define rclkdiv_DP_RXPMA_IDX_0 197 `define rclkdiv_DP_RXPMA_IDX_1 198 `define rclkdiv_DP_RXPMA_IDX_2 199 `define rclkdiv_DP_RXPMA_IDX_3 200 `define rrgen_set_DP_RXPMA_IDX_0 201 `define rrgen_set_DP_RXPMA_IDX_1 202 `define rrgen_set_DP_RXPMA_IDX_2 203 `define radce_adapt_DP_RXPMA_IDX_0 204 `define rseq_sel_DP_RXPMA_IDX_0 205 `define rseq_sel_DP_RXPMA_IDX_1 206 `define rlock_lf_ovd_DP_RXPMA_IDX_0 207 // Table49: PMA Per Channel RX Control Register 14 for Channel 0 `define rrgen_vod_DP_RXPMA_IDX_0 208 `define rrgen_vod_DP_RXPMA_IDX_1 209 `define rrgen_vod_DP_RXPMA_IDX_2 210 `define rf_hpf_DP_RXPMA_IDX_0 211 `define rf_hpf_DP_RXPMA_IDX_1 212 `define rf_lpf_DP_RXPMA_IDX_0 213 `define rf_lpf_DP_RXPMA_IDX_1 214 `define reserved_1_TB49_DP_RXPMA_IDX_0 215 `define reserved_1_TB49_DP_RXPMA_IDX_1 216 `define reserved_1_TB49_DP_RXPMA_IDX_2 217 `define reserved_0_TB49_DP_RXPMA_IDX_0 218 `define reserved_0_TB49_DP_RXPMA_IDX_1 219 `define reserved_0_TB49_DP_RXPMA_IDX_2 220 `define rhyst_hf_DP_RXPMA_IDX_0 221 `define rhyst_hf_DP_RXPMA_IDX_1 222 `define rhyst_hf_DP_RXPMA_IDX_2 223 // Table50: PMA Per Channel RX Control Register 15 for Channel 0 `define radce_pdb_DP_RXPMA_IDX_0 224 `define radce_rst_DP_RXPMA_IDX_0 225 `define rhf_os_DP_RXPMA_IDX_0 226 `define rhf_os_DP_RXPMA_IDX_1 227 `define rhf_os_DP_RXPMA_IDX_2 228 `define rhf_os_DP_RXPMA_IDX_3 229 `define rlf_os_DP_RXPMA_IDX_0 230 `define rlf_os_DP_RXPMA_IDX_1 231 `define rlf_os_DP_RXPMA_IDX_2 232 `define rlf_os_DP_RXPMA_IDX_3 233 `define rd2a_res_DP_RXPMA_IDX_0 234 `define rd2a_res_DP_RXPMA_IDX_1 235 `define rrect_adj_DP_RXPMA_IDX_0 236 `define rrect_adj_DP_RXPMA_IDX_1 237 `define rrgen_bw_DP_RXPMA_IDX_0 238 `define rrgen_bw_DP_RXPMA_IDX_1 239 // Table51: PMA Per Channel RX Control Register 16 for Channel 0 `define radce_hflck_DP_RXPMA_IDX_0 240 `define radce_hflck_DP_RXPMA_IDX_1 241 `define radce_hflck_DP_RXPMA_IDX_2 242 `define radce_hflck_DP_RXPMA_IDX_3 243 `define radce_hflck_DP_RXPMA_IDX_4 244 `define radce_hflck_DP_RXPMA_IDX_5 245 `define radce_hflck_DP_RXPMA_IDX_6 246 `define radce_hflck_DP_RXPMA_IDX_7 247 `define radce_hflck_DP_RXPMA_IDX_8 248 `define radce_hflck_DP_RXPMA_IDX_9 249 `define radce_hflck_DP_RXPMA_IDX_10 250 `define radce_hflck_DP_RXPMA_IDX_11 251 `define radce_hflck_DP_RXPMA_IDX_12 252 `define radce_hflck_DP_RXPMA_IDX_13 253 `define radce_hflck_DP_RXPMA_IDX_14 254 `define reserved_0_TB51_DP_RXPMA_IDX_0 255 // Table52: PMA Per Channel RX Control Register 17 for Channel 0 `define radce_lflck_DP_RXPMA_IDX_0 256 `define radce_lflck_DP_RXPMA_IDX_1 257 `define radce_lflck_DP_RXPMA_IDX_2 258 `define radce_lflck_DP_RXPMA_IDX_3 259 `define radce_lflck_DP_RXPMA_IDX_4 260 `define radce_lflck_DP_RXPMA_IDX_5 261 `define radce_lflck_DP_RXPMA_IDX_6 262 `define radce_lflck_DP_RXPMA_IDX_7 263 `define radce_lflck_DP_RXPMA_IDX_8 264 `define radce_lflck_DP_RXPMA_IDX_9 265 `define radce_lflck_DP_RXPMA_IDX_10 266 `define radce_lflck_DP_RXPMA_IDX_11 267 `define radce_lflck_DP_RXPMA_IDX_12 268 `define radce_lflck_DP_RXPMA_IDX_13 269 `define radce_lflck_DP_RXPMA_IDX_14 270 `define reserved_0_TB52_DP_RXPMA_IDX_0 271 // Table53: PMA Per Channel RX Control Register 18 for Channel 0 `define radce_digital_DP_RXPMA_IDX_0 272 `define radce_digital_DP_RXPMA_IDX_1 273 `define radce_digital_DP_RXPMA_IDX_2 274 `define radce_digital_DP_RXPMA_IDX_3 275 `define radce_digital_DP_RXPMA_IDX_4 276 `define radce_digital_DP_RXPMA_IDX_5 277 `define radce_digital_DP_RXPMA_IDX_6 278 `define radce_digital_DP_RXPMA_IDX_7 279 `define radce_digital_DP_RXPMA_IDX_8 280 `define radce_digital_DP_RXPMA_IDX_9 281 `define reserved_0_TB53_DP_RXPMA_IDX_0 282 `define reserved_0_TB53_DP_RXPMA_IDX_1 283 `define reserved_0_TB53_DP_RXPMA_IDX_2 284 `define reserved_0_TB53_DP_RXPMA_IDX_3 285 `define reserved_0_TB53_DP_RXPMA_IDX_4 286 `define reserved_0_TB53_DP_RXPMA_IDX_5 287 // ---------------------------------------------------------------------------------------------------------------- // Manual section due to one ICD CRAM mapped to multiple Atoms // ---------------------------------------------------------------------------------------------------------------- // Manual: TX_PCS section ------------------------------------- `define rauto_speed_ena_DP_TXPCS_IDX 64 `define rendec_data_sel_tx_DP_TXPCS_IDX 65 `define rfreq_sel_DP_TXPCS_IDX 66 `define rhip_ena_DP_TXPCS_IDX 67 `define rindv_tx_DP_TXPCS_IDX 68 `define rphfifo_master_sel_tx_DP_TXPCS_IDX 69 `define rpma_doublewidth_tx_DP_TXPCS_IDX 70 `define rpmadwidth_tx_DP_TXPCS_IDX 71 `define rtx_cmu_sel_DP_TXPCS_IDX 72 `define rmaster_tx_DP_TXPCS_IDX 73 `define rmaster_up_tx_DP_TXPCS_IDX 74 // Manual: RX PMA section ------------------------------------- `define rrevlb_sw_DP_RXPMA_IDX 291 // cram_table33_tx_pma_reg6 =rs_lpbk maps to rx_pma.RRX_S_LPBK_RXPMA_IDX `define rs_lpbk_DP_RXPMA_IDX 292 // Manual: RX_PCS section ------------------------------------- `define rpmadwidth_rx_DP_RXPCS_IDX 368 `define rpma_doublewidth_rx_DP_RXPCS_IDX 369 // RX portion of global_ctrl 1 //`define rphfifo_master_sel_rx_DP_RXPCS_IDX `define rendec_data_sel_rx_DP_RXPCS_IDX 370 `define rdeskewen_DP_RXPCS_IDX 371 `define rindv_rx_DP_RXPCS_IDX 372 // RX portion of global_ctrl 2 `define rdskposdisp_DP_RXPCS_IDX 373 //`define ralgnopt_DP_RXPCS_IDX //`define rdskchrp[9:0] // RX portion of global_ctrl 3 `define rmaster_rx_DP_RXPCS_IDX 374 `define rmaster_up_rx_DP_RXPCS_IDX 375 // not used - legacy from rx_pcs.v `define rdwidth_rx_DP_RXPCS_IDX 380 `define rtx_idle_delay_DP_RXPCS_IDX_0 381 `define rtx_idle_delay_DP_RXPCS_IDX_1 382 `define rclkcmppos_DP_RXPCS_IDX 383 `define rppmsel_DP_RXPCS_IDX_0 384 `define rppmsel_DP_RXPCS_IDX_5 389 `define rforce0_freqdet_DP_RXPCS_IDX 390 `define rforce1_freqdet_DP_RXPCS_IDX 391 `define rs_lpbk_DP_RXPCS_IDX 392 `define rrx_revlb_sw_DP_RXPCS_IDX 393 // central clock divider section `define rfreerun_centrl_DP_CLOCK_DIV_IDX 10 `define rcentrl_clk_sel_DP_CLOCK_DIV_IDX 11 `define rrefclk_out_div2_DP_CLOCK_DIV_IDX 12 // CMU-central PCS section - (FIFO ptr, xaui sm) //`define rxaui_s2gx_en_rx_DP_CENTRL_PCS_IDX 10 //`define rxaui_s2gx_en_tx_DP_CENTRL_PCS_IDX 11 // Manual: PLL (only rx_cdr_pll uses it: table 33 & 59) -------------- `define rdynamic_sw_DP_PLL_IDX_0 70 // continue PLL index //==================================================================== // Manually added code to handle PLL clock select indices = //==================================================================== `define PFD_CLK_SELECT_DP_PLL_IDX_0 100 `define PFD_CLK_SELECT_DP_PLL_IDX_1 101 `define PFD_CLK_SELECT_DP_PLL_IDX_2 102 `define PFD_CLK_SELECT_DP_PLL_IDX_3 103 wire [3:0] pll0_init_pfd_clk_sel; // logical index from (log0)PLL_Atom wire [3:0] pll0_dp_pfd_clk_sel; // logical index to (Phy0)PLL_Atom wire [1:0] pll0_csr_riqclk_sel, pll0_csr_rrefclk_sel; // PHY to DPRIO wire [1:0] pll0_dp_riqclk_sel, pll0_dp_rrefclk_sel; // PHY from DPRIO wire [3:0] pll1_init_pfd_clk_sel; // logical index from PLL_Atom wire [3:0] pll1_dp_pfd_clk_sel; // logical index to PLL_Atom wire [1:0] pll1_csr_riqclk_sel, pll1_csr_rrefclk_sel; // PHY to DPRIO wire [1:0] pll1_dp_riqclk_sel, pll1_dp_rrefclk_sel; // PHY from DPRIO wire [3:0] pll2_init_pfd_clk_sel; // logical index from PLL_Atom wire [3:0] pll2_dp_pfd_clk_sel; // logical index to PLL_Atom wire [1:0] pll2_csr_riqclk_sel, pll2_csr_rrefclk_sel; // PHY to DPRIO wire [1:0] pll2_dp_riqclk_sel, pll2_dp_rrefclk_sel; // PHY from DPRIO wire [3:0] pll3_init_pfd_clk_sel; // logical index from PLL_Atom wire [3:0] pll3_dp_pfd_clk_sel; // logical index to PLL_Atom wire [1:0] pll3_csr_riqclk_sel, pll3_csr_rrefclk_sel; // PHY to DPRIO wire [1:0] pll3_dp_riqclk_sel, pll3_dp_rrefclk_sel; // PHY from DPRIO wire [3:0] pll4_init_pfd_clk_sel; // logical index from PLL_Atom wire [3:0] pll4_dp_pfd_clk_sel; // logical index to PLL_Atom wire [1:0] pll4_csr_riqclk_sel, pll4_csr_rrefclk_sel; // PHY to DPRIO wire [1:0] pll4_dp_riqclk_sel, pll4_dp_rrefclk_sel; // PHY from DPRIO wire [3:0] pll5_init_pfd_clk_sel; // logical index from PLL_Atom wire [3:0] pll5_dp_pfd_clk_sel; // logical index to PLL_Atom wire [1:0] pll5_csr_riqclk_sel, pll5_csr_rrefclk_sel; // PHY to DPRIO wire [1:0] pll5_dp_riqclk_sel, pll5_dp_rrefclk_sel; // PHY from DPRIO //==================================================================== // Manually added code to handle TXPMA clock select indices = //==================================================================== `define CLKIN_SELECT_DP_TXPMA_IDX_0 200 `define CLKIN_SELECT_DP_TXPMA_IDX_1 201 `define CLKIN_SELECT_DP_TXPMA_IDX_2 202 wire [2:0] txpma0_init_clkin_sel; // logical index from log0 Atom wire [2:0] txpma0_dp_clkin_sel; // logical index to PHY0 Atom wire [1:0] txpma0_csr_rcgb_x_en; // PHY to DPRIO wire [1:0] txpma0_dp_rcgb_x_en; // PHY from DPRIO wire [2:0] txpma1_init_clkin_sel; // logical index from PHY0 Atom wire [2:0] txpma1_dp_clkin_sel; // logical index to PHY0 Atom wire [1:0] txpma1_csr_rcgb_x_en; // PHY to DPRIO wire [1:0] txpma1_dp_rcgb_x_en; // PHY from DPRIO wire [2:0] txpma2_init_clkin_sel; // logical index from PHY0 Atom wire [2:0] txpma2_dp_clkin_sel; // logical index to PHY0 Atom wire [1:0] txpma2_csr_rcgb_x_en; // PHY to DPRIO wire [1:0] txpma2_dp_rcgb_x_en; // PHY from DPRIO wire [2:0] txpma3_init_clkin_sel; // logical index from PHY0 Atom wire [2:0] txpma3_dp_clkin_sel; // logical index to PHY0 Atom wire [1:0] txpma3_csr_rcgb_x_en; // PHY to DPRIO wire [1:0] txpma3_dp_rcgb_x_en; // PHY from DPRIO wire [2:0] txpma4_init_clkin_sel; // logical index from PHY0 Atom wire [2:0] txpma4_dp_clkin_sel; // logical index to PHY0 Atom wire [1:0] txpma4_csr_rcgb_x_en; // PHY to DPRIO wire [1:0] txpma4_dp_rcgb_x_en; // PHY from DPRIO wire [2:0] txpma5_init_clkin_sel; // logical index from PHY0 Atom wire [2:0] txpma5_dp_clkin_sel; // logical index to PHY0 Atom wire [1:0] txpma5_csr_rcgb_x_en; // PHY to DPRIO wire [1:0] txpma5_dp_rcgb_x_en; // PHY from DPRIO //==================================================================== // Manually added code to handle clkdiv PLL0/1 select = //==================================================================== `define INCLK_SELECT_DP_CLOCK_DIV_IDX 0 wire clkdiv0_init_inclk_select; // logical index from logic Atom wire clkdiv0_dp_inclk_select; // logical index to PHY Atom wire clkdiv0_csr_rcgb_cmu_sel; // PHY to DPRIO wire clkdiv0_dp_rcgb_cmu_sel; // PHY from DPRIO wire clkdiv1_init_inclk_select; // logical index from PHY1 Atom wire clkdiv1_dp_inclk_select; // logical index to PHY1 Atom wire clkdiv1_csr_rcgb_cmu_sel; // PHY to DPRIO wire clkdiv1_dp_rcgb_cmu_sel; // PHY from DPRIO wire clkdiv2_init_inclk_select; // logical index from PHY2 Atom wire clkdiv2_dp_inclk_select; // logical index to PHY2 Atom wire clkdiv2_csr_rcgb_cmu_sel; // PHY to DPRIO wire clkdiv2_dp_rcgb_cmu_sel; // PHY from DPRIO wire clkdiv3_init_inclk_select; // logical index from PHY3 Atom wire clkdiv3_dp_inclk_select; // logical index to PHY3 Atom wire clkdiv3_csr_rcgb_cmu_sel; // PHY to DPRIO wire clkdiv3_dp_rcgb_cmu_sel; // PHY from DPRIO wire clkdiv4_init_inclk_select; // logical index from PHY4 Atom wire clkdiv4_dp_inclk_select; // logical index to PHY4 Atom wire clkdiv4_csr_rcgb_cmu_sel; // PHY to DPRIO wire clkdiv4_dp_rcgb_cmu_sel; // PHY from DPRIO wire clkdiv5_init_inclk_select; // logical index from PHY5 Atom wire clkdiv5_dp_inclk_select; // logical index to PHY5 Atom wire clkdiv5_csr_rcgb_cmu_sel; // PHY to DPRIO wire clkdiv5_dp_rcgb_cmu_sel; // PHY from DPRIO //==================================================================== // Manually added code to handle 5th/6th PMA = // === begin = // use ch4/5_in_chnl ch4/5_out_chnl interacting with Quartus Int Con = // use cmu0 and cmu1 to interface ICD/Phy = //==================================================================== wire [15:0] ch4_in_chnl_ctrl_28, cmu0_in_centrl_ctrl_1; wire [15:0] ch4_in_chnl_ctrl_29, cmu0_in_centrl_ctrl_2; wire [15:0] ch4_in_chnl_ctrl_30, cmu0_in_centrl_ctrl_3; wire [15:0] ch4_in_chnl_ctrl_31, cmu0_in_centrl_ctrl_4; wire [15:0] ch4_in_chnl_ctrl_32, cmu0_in_centrl_ctrl_5; wire [15:0] ch4_in_chnl_ctrl_33, cmu0_in_centrl_ctrl_6; wire [15:0] ch4_in_chnl_ctrl_34, cmu0_in_centrl_ctrl_7; wire [15:0] ch4_in_chnl_ctrl_35, cmu0_in_centrl_ctrl_8; wire [15:0] ch4_in_chnl_ctrl_36, cmu0_in_centrl_ctrl_9; wire [15:0] ch4_in_chnl_ctrl_37, cmu0_in_centrl_ctrl_10; wire [15:0] ch4_in_chnl_ctrl_38, cmu0_in_centrl_ctrl_11; wire [15:0] ch4_in_chnl_ctrl_39, cmu0_in_centrl_ctrl_12; wire [15:0] ch4_in_chnl_ctrl_40, cmu0_in_centrl_ctrl_13; wire [15:0] ch4_in_chnl_ctrl_41, cmu0_in_centrl_ctrl_14; wire [15:0] ch4_in_chnl_ctrl_42, cmu0_in_centrl_ctrl_15; wire [15:0] ch4_in_chnl_ctrl_43, cmu0_in_centrl_ctrl_16; wire [15:0] ch4_in_chnl_ctrl_44, cmu0_in_centrl_ctrl_17; wire [15:0] ch4_in_chnl_ctrl_45, cmu0_in_centrl_ctrl_18; wire [15:0] ch4_in_chnl_ctrl_46, cmu0_in_centrl_ctrl_19; wire [15:0] ch4_in_chnl_ctrl_47, cmu0_in_centrl_ctrl_20; wire [15:0] ch5_in_chnl_ctrl_28, cmu1_in_centrl_ctrl_1; wire [15:0] ch5_in_chnl_ctrl_29, cmu1_in_centrl_ctrl_2; wire [15:0] ch5_in_chnl_ctrl_30, cmu1_in_centrl_ctrl_3; wire [15:0] ch5_in_chnl_ctrl_31, cmu1_in_centrl_ctrl_4; wire [15:0] ch5_in_chnl_ctrl_32, cmu1_in_centrl_ctrl_5; wire [15:0] ch5_in_chnl_ctrl_33, cmu1_in_centrl_ctrl_6; wire [15:0] ch5_in_chnl_ctrl_34, cmu1_in_centrl_ctrl_7; wire [15:0] ch5_in_chnl_ctrl_35, cmu1_in_centrl_ctrl_8; wire [15:0] ch5_in_chnl_ctrl_36, cmu1_in_centrl_ctrl_9; wire [15:0] ch5_in_chnl_ctrl_37, cmu1_in_centrl_ctrl_10; wire [15:0] ch5_in_chnl_ctrl_38, cmu1_in_centrl_ctrl_11; wire [15:0] ch5_in_chnl_ctrl_39, cmu1_in_centrl_ctrl_12; wire [15:0] ch5_in_chnl_ctrl_40, cmu1_in_centrl_ctrl_13; wire [15:0] ch5_in_chnl_ctrl_41, cmu1_in_centrl_ctrl_14; wire [15:0] ch5_in_chnl_ctrl_42, cmu1_in_centrl_ctrl_15; wire [15:0] ch5_in_chnl_ctrl_43, cmu1_in_centrl_ctrl_16; wire [15:0] ch5_in_chnl_ctrl_44, cmu1_in_centrl_ctrl_17; wire [15:0] ch5_in_chnl_ctrl_45, cmu1_in_centrl_ctrl_18; wire [15:0] ch5_in_chnl_ctrl_46, cmu1_in_centrl_ctrl_19; wire [15:0] ch5_in_chnl_ctrl_47, cmu1_in_centrl_ctrl_20; // CMU only or global wire [15:0] cmu0_in_centrl_ctrl_21, cmu1_in_centrl_ctrl_21; wire [15:0] cmu_in_centrl_global_0, cmu_in_centrl_global_1; wire [15:0] cmu_in_centrl_global_2, cmu_in_centrl_global_3; wire [15:0] ch4_out_chnl_ctrl_28, cmu0_out_centrl_ctrl_1; wire [15:0] ch4_out_chnl_ctrl_29, cmu0_out_centrl_ctrl_2; wire [15:0] ch4_out_chnl_ctrl_30, cmu0_out_centrl_ctrl_3; wire [15:0] ch4_out_chnl_ctrl_31, cmu0_out_centrl_ctrl_4; wire [15:0] ch4_out_chnl_ctrl_32, cmu0_out_centrl_ctrl_5; wire [15:0] ch4_out_chnl_ctrl_33, cmu0_out_centrl_ctrl_6; wire [15:0] ch4_out_chnl_ctrl_34, cmu0_out_centrl_ctrl_7; wire [15:0] ch4_out_chnl_ctrl_35, cmu0_out_centrl_ctrl_8; wire [15:0] ch4_out_chnl_ctrl_36, cmu0_out_centrl_ctrl_9; wire [15:0] ch4_out_chnl_ctrl_37, cmu0_out_centrl_ctrl_10; wire [15:0] ch4_out_chnl_ctrl_38, cmu0_out_centrl_ctrl_11; wire [15:0] ch4_out_chnl_ctrl_39, cmu0_out_centrl_ctrl_12; wire [15:0] ch4_out_chnl_ctrl_40, cmu0_out_centrl_ctrl_13; wire [15:0] ch4_out_chnl_ctrl_41, cmu0_out_centrl_ctrl_14; wire [15:0] ch4_out_chnl_ctrl_42, cmu0_out_centrl_ctrl_15; wire [15:0] ch4_out_chnl_ctrl_43, cmu0_out_centrl_ctrl_16; wire [15:0] ch4_out_chnl_ctrl_44, cmu0_out_centrl_ctrl_17; wire [15:0] ch4_out_chnl_ctrl_45, cmu0_out_centrl_ctrl_18; wire [15:0] ch4_out_chnl_ctrl_46, cmu0_out_centrl_ctrl_19; wire [15:0] ch4_out_chnl_ctrl_47, cmu0_out_centrl_ctrl_20; wire [15:0] ch5_out_chnl_ctrl_28, cmu1_out_centrl_ctrl_1; wire [15:0] ch5_out_chnl_ctrl_29, cmu1_out_centrl_ctrl_2; wire [15:0] ch5_out_chnl_ctrl_30, cmu1_out_centrl_ctrl_3; wire [15:0] ch5_out_chnl_ctrl_31, cmu1_out_centrl_ctrl_4; wire [15:0] ch5_out_chnl_ctrl_32, cmu1_out_centrl_ctrl_5; wire [15:0] ch5_out_chnl_ctrl_33, cmu1_out_centrl_ctrl_6; wire [15:0] ch5_out_chnl_ctrl_34, cmu1_out_centrl_ctrl_7; wire [15:0] ch5_out_chnl_ctrl_35, cmu1_out_centrl_ctrl_8; wire [15:0] ch5_out_chnl_ctrl_36, cmu1_out_centrl_ctrl_9; wire [15:0] ch5_out_chnl_ctrl_37, cmu1_out_centrl_ctrl_10; wire [15:0] ch5_out_chnl_ctrl_38, cmu1_out_centrl_ctrl_11; wire [15:0] ch5_out_chnl_ctrl_39, cmu1_out_centrl_ctrl_12; wire [15:0] ch5_out_chnl_ctrl_40, cmu1_out_centrl_ctrl_13; wire [15:0] ch5_out_chnl_ctrl_41, cmu1_out_centrl_ctrl_14; wire [15:0] ch5_out_chnl_ctrl_42, cmu1_out_centrl_ctrl_15; wire [15:0] ch5_out_chnl_ctrl_43, cmu1_out_centrl_ctrl_16; wire [15:0] ch5_out_chnl_ctrl_44, cmu1_out_centrl_ctrl_17; wire [15:0] ch5_out_chnl_ctrl_45, cmu1_out_centrl_ctrl_18; wire [15:0] ch5_out_chnl_ctrl_46, cmu1_out_centrl_ctrl_19; wire [15:0] ch5_out_chnl_ctrl_47, cmu1_out_centrl_ctrl_20; // CMU only or global wire [15:0] cmu0_out_centrl_ctrl_21, cmu1_out_centrl_ctrl_21; wire [15:0] cmu_out_centrl_global_0, cmu_out_centrl_global_1; wire [15:0] cmu_out_centrl_global_2, cmu_out_centrl_global_3; //============================================================ // Manually added code to handle 5th/6th PMA ================= // === end = //============================================================ //------------------------------------------------------------- // Phy channel in ICD ----------------------------------------- //------------------------------------------------------------- wire [15:0] ch0_in_chnl_ctrl_1; wire [15:0] ch1_in_chnl_ctrl_1; wire [15:0] ch2_in_chnl_ctrl_1; wire [15:0] ch3_in_chnl_ctrl_1; wire [15:0] ch0_out_chnl_ctrl_1; wire [15:0] ch1_out_chnl_ctrl_1; wire [15:0] ch2_out_chnl_ctrl_1; wire [15:0] ch3_out_chnl_ctrl_1; wire [15:0] ch0_in_chnl_ctrl_2; wire [15:0] ch1_in_chnl_ctrl_2; wire [15:0] ch2_in_chnl_ctrl_2; wire [15:0] ch3_in_chnl_ctrl_2; wire [15:0] ch0_out_chnl_ctrl_2; wire [15:0] ch1_out_chnl_ctrl_2; wire [15:0] ch2_out_chnl_ctrl_2; wire [15:0] ch3_out_chnl_ctrl_2; wire [15:0] ch0_in_chnl_ctrl_3; wire [15:0] ch1_in_chnl_ctrl_3; wire [15:0] ch2_in_chnl_ctrl_3; wire [15:0] ch3_in_chnl_ctrl_3; wire [15:0] ch0_out_chnl_ctrl_3; wire [15:0] ch1_out_chnl_ctrl_3; wire [15:0] ch2_out_chnl_ctrl_3; wire [15:0] ch3_out_chnl_ctrl_3; wire [15:0] ch0_in_chnl_ctrl_4; wire [15:0] ch1_in_chnl_ctrl_4; wire [15:0] ch2_in_chnl_ctrl_4; wire [15:0] ch3_in_chnl_ctrl_4; wire [15:0] ch0_out_chnl_ctrl_4; wire [15:0] ch1_out_chnl_ctrl_4; wire [15:0] ch2_out_chnl_ctrl_4; wire [15:0] ch3_out_chnl_ctrl_4; wire [15:0] ch0_in_chnl_ctrl_5; wire [15:0] ch1_in_chnl_ctrl_5; wire [15:0] ch2_in_chnl_ctrl_5; wire [15:0] ch3_in_chnl_ctrl_5; wire [15:0] ch0_out_chnl_ctrl_5; wire [15:0] ch1_out_chnl_ctrl_5; wire [15:0] ch2_out_chnl_ctrl_5; wire [15:0] ch3_out_chnl_ctrl_5; wire [15:0] ch0_in_chnl_ctrl_6; wire [15:0] ch1_in_chnl_ctrl_6; wire [15:0] ch2_in_chnl_ctrl_6; wire [15:0] ch3_in_chnl_ctrl_6; wire [15:0] ch0_out_chnl_ctrl_6; wire [15:0] ch1_out_chnl_ctrl_6; wire [15:0] ch2_out_chnl_ctrl_6; wire [15:0] ch3_out_chnl_ctrl_6; wire [15:0] ch0_in_chnl_ctrl_7; wire [15:0] ch1_in_chnl_ctrl_7; wire [15:0] ch2_in_chnl_ctrl_7; wire [15:0] ch3_in_chnl_ctrl_7; wire [15:0] ch0_out_chnl_ctrl_7; wire [15:0] ch1_out_chnl_ctrl_7; wire [15:0] ch2_out_chnl_ctrl_7; wire [15:0] ch3_out_chnl_ctrl_7; wire [15:0] ch0_in_chnl_ctrl_8; wire [15:0] ch1_in_chnl_ctrl_8; wire [15:0] ch2_in_chnl_ctrl_8; wire [15:0] ch3_in_chnl_ctrl_8; wire [15:0] ch0_out_chnl_ctrl_8; wire [15:0] ch1_out_chnl_ctrl_8; wire [15:0] ch2_out_chnl_ctrl_8; wire [15:0] ch3_out_chnl_ctrl_8; wire [15:0] ch0_in_chnl_ctrl_9; wire [15:0] ch1_in_chnl_ctrl_9; wire [15:0] ch2_in_chnl_ctrl_9; wire [15:0] ch3_in_chnl_ctrl_9; wire [15:0] ch0_out_chnl_ctrl_9; wire [15:0] ch1_out_chnl_ctrl_9; wire [15:0] ch2_out_chnl_ctrl_9; wire [15:0] ch3_out_chnl_ctrl_9; wire [15:0] ch0_in_chnl_ctrl_10; wire [15:0] ch1_in_chnl_ctrl_10; wire [15:0] ch2_in_chnl_ctrl_10; wire [15:0] ch3_in_chnl_ctrl_10; wire [15:0] ch0_out_chnl_ctrl_10; wire [15:0] ch1_out_chnl_ctrl_10; wire [15:0] ch2_out_chnl_ctrl_10; wire [15:0] ch3_out_chnl_ctrl_10; wire [15:0] ch0_in_chnl_ctrl_11; wire [15:0] ch1_in_chnl_ctrl_11; wire [15:0] ch2_in_chnl_ctrl_11; wire [15:0] ch3_in_chnl_ctrl_11; wire [15:0] ch0_out_chnl_ctrl_11; wire [15:0] ch1_out_chnl_ctrl_11; wire [15:0] ch2_out_chnl_ctrl_11; wire [15:0] ch3_out_chnl_ctrl_11; wire [15:0] ch0_in_chnl_ctrl_12; wire [15:0] ch1_in_chnl_ctrl_12; wire [15:0] ch2_in_chnl_ctrl_12; wire [15:0] ch3_in_chnl_ctrl_12; wire [15:0] ch0_out_chnl_ctrl_12; wire [15:0] ch1_out_chnl_ctrl_12; wire [15:0] ch2_out_chnl_ctrl_12; wire [15:0] ch3_out_chnl_ctrl_12; wire [15:0] ch0_in_chnl_ctrl_13; wire [15:0] ch1_in_chnl_ctrl_13; wire [15:0] ch2_in_chnl_ctrl_13; wire [15:0] ch3_in_chnl_ctrl_13; wire [15:0] ch0_out_chnl_ctrl_13; wire [15:0] ch1_out_chnl_ctrl_13; wire [15:0] ch2_out_chnl_ctrl_13; wire [15:0] ch3_out_chnl_ctrl_13; wire [15:0] ch0_in_chnl_ctrl_14; wire [15:0] ch1_in_chnl_ctrl_14; wire [15:0] ch2_in_chnl_ctrl_14; wire [15:0] ch3_in_chnl_ctrl_14; wire [15:0] ch0_out_chnl_ctrl_14; wire [15:0] ch1_out_chnl_ctrl_14; wire [15:0] ch2_out_chnl_ctrl_14; wire [15:0] ch3_out_chnl_ctrl_14; wire [15:0] ch0_in_chnl_ctrl_15; wire [15:0] ch1_in_chnl_ctrl_15; wire [15:0] ch2_in_chnl_ctrl_15; wire [15:0] ch3_in_chnl_ctrl_15; wire [15:0] ch0_out_chnl_ctrl_15; wire [15:0] ch1_out_chnl_ctrl_15; wire [15:0] ch2_out_chnl_ctrl_15; wire [15:0] ch3_out_chnl_ctrl_15; wire [15:0] ch0_in_chnl_ctrl_16; wire [15:0] ch1_in_chnl_ctrl_16; wire [15:0] ch2_in_chnl_ctrl_16; wire [15:0] ch3_in_chnl_ctrl_16; wire [15:0] ch0_out_chnl_ctrl_16; wire [15:0] ch1_out_chnl_ctrl_16; wire [15:0] ch2_out_chnl_ctrl_16; wire [15:0] ch3_out_chnl_ctrl_16; wire [15:0] ch0_in_chnl_ctrl_17; wire [15:0] ch1_in_chnl_ctrl_17; wire [15:0] ch2_in_chnl_ctrl_17; wire [15:0] ch3_in_chnl_ctrl_17; wire [15:0] ch0_out_chnl_ctrl_17; wire [15:0] ch1_out_chnl_ctrl_17; wire [15:0] ch2_out_chnl_ctrl_17; wire [15:0] ch3_out_chnl_ctrl_17; wire [15:0] ch0_in_chnl_ctrl_18; wire [15:0] ch1_in_chnl_ctrl_18; wire [15:0] ch2_in_chnl_ctrl_18; wire [15:0] ch3_in_chnl_ctrl_18; wire [15:0] ch0_out_chnl_ctrl_18; wire [15:0] ch1_out_chnl_ctrl_18; wire [15:0] ch2_out_chnl_ctrl_18; wire [15:0] ch3_out_chnl_ctrl_18; wire [15:0] ch0_in_chnl_ctrl_19; wire [15:0] ch1_in_chnl_ctrl_19; wire [15:0] ch2_in_chnl_ctrl_19; wire [15:0] ch3_in_chnl_ctrl_19; wire [15:0] ch0_out_chnl_ctrl_19; wire [15:0] ch1_out_chnl_ctrl_19; wire [15:0] ch2_out_chnl_ctrl_19; wire [15:0] ch3_out_chnl_ctrl_19; wire [15:0] ch0_in_chnl_ctrl_20; wire [15:0] ch1_in_chnl_ctrl_20; wire [15:0] ch2_in_chnl_ctrl_20; wire [15:0] ch3_in_chnl_ctrl_20; wire [15:0] ch0_out_chnl_ctrl_20; wire [15:0] ch1_out_chnl_ctrl_20; wire [15:0] ch2_out_chnl_ctrl_20; wire [15:0] ch3_out_chnl_ctrl_20; wire [15:0] ch0_in_chnl_ctrl_21; wire [15:0] ch1_in_chnl_ctrl_21; wire [15:0] ch2_in_chnl_ctrl_21; wire [15:0] ch3_in_chnl_ctrl_21; wire [15:0] ch0_out_chnl_ctrl_21; wire [15:0] ch1_out_chnl_ctrl_21; wire [15:0] ch2_out_chnl_ctrl_21; wire [15:0] ch3_out_chnl_ctrl_21; wire [15:0] ch0_in_chnl_ctrl_22; wire [15:0] ch1_in_chnl_ctrl_22; wire [15:0] ch2_in_chnl_ctrl_22; wire [15:0] ch3_in_chnl_ctrl_22; wire [15:0] ch0_out_chnl_ctrl_22; wire [15:0] ch1_out_chnl_ctrl_22; wire [15:0] ch2_out_chnl_ctrl_22; wire [15:0] ch3_out_chnl_ctrl_22; wire [15:0] ch0_in_chnl_ctrl_23; wire [15:0] ch1_in_chnl_ctrl_23; wire [15:0] ch2_in_chnl_ctrl_23; wire [15:0] ch3_in_chnl_ctrl_23; wire [15:0] ch0_out_chnl_ctrl_23; wire [15:0] ch1_out_chnl_ctrl_23; wire [15:0] ch2_out_chnl_ctrl_23; wire [15:0] ch3_out_chnl_ctrl_23; wire [15:0] ch0_in_chnl_ctrl_24; wire [15:0] ch1_in_chnl_ctrl_24; wire [15:0] ch2_in_chnl_ctrl_24; wire [15:0] ch3_in_chnl_ctrl_24; wire [15:0] ch0_out_chnl_ctrl_24; wire [15:0] ch1_out_chnl_ctrl_24; wire [15:0] ch2_out_chnl_ctrl_24; wire [15:0] ch3_out_chnl_ctrl_24; wire [15:0] ch0_in_chnl_ctrl_25; wire [15:0] ch1_in_chnl_ctrl_25; wire [15:0] ch2_in_chnl_ctrl_25; wire [15:0] ch3_in_chnl_ctrl_25; wire [15:0] ch0_out_chnl_ctrl_25; wire [15:0] ch1_out_chnl_ctrl_25; wire [15:0] ch2_out_chnl_ctrl_25; wire [15:0] ch3_out_chnl_ctrl_25; wire [15:0] ch0_in_chnl_ctrl_26; wire [15:0] ch1_in_chnl_ctrl_26; wire [15:0] ch2_in_chnl_ctrl_26; wire [15:0] ch3_in_chnl_ctrl_26; wire [15:0] ch0_out_chnl_ctrl_26; wire [15:0] ch1_out_chnl_ctrl_26; wire [15:0] ch2_out_chnl_ctrl_26; wire [15:0] ch3_out_chnl_ctrl_26; wire [15:0] ch0_in_chnl_ctrl_27; wire [15:0] ch1_in_chnl_ctrl_27; wire [15:0] ch2_in_chnl_ctrl_27; wire [15:0] ch3_in_chnl_ctrl_27; wire [15:0] ch0_out_chnl_ctrl_27; wire [15:0] ch1_out_chnl_ctrl_27; wire [15:0] ch2_out_chnl_ctrl_27; wire [15:0] ch3_out_chnl_ctrl_27; // TXPMA wire [15:0] ch0_in_chnl_ctrl_28; wire [15:0] ch1_in_chnl_ctrl_28; wire [15:0] ch2_in_chnl_ctrl_28; wire [15:0] ch3_in_chnl_ctrl_28; wire [15:0] ch0_out_chnl_ctrl_28; wire [15:0] ch1_out_chnl_ctrl_28; wire [15:0] ch2_out_chnl_ctrl_28; wire [15:0] ch3_out_chnl_ctrl_28; wire [15:0] ch0_in_chnl_ctrl_29; wire [15:0] ch1_in_chnl_ctrl_29; wire [15:0] ch2_in_chnl_ctrl_29; wire [15:0] ch3_in_chnl_ctrl_29; wire [15:0] ch0_out_chnl_ctrl_29; wire [15:0] ch1_out_chnl_ctrl_29; wire [15:0] ch2_out_chnl_ctrl_29; wire [15:0] ch3_out_chnl_ctrl_29; wire [15:0] ch0_in_chnl_ctrl_30; wire [15:0] ch1_in_chnl_ctrl_30; wire [15:0] ch2_in_chnl_ctrl_30; wire [15:0] ch3_in_chnl_ctrl_30; wire [15:0] ch0_out_chnl_ctrl_30; wire [15:0] ch1_out_chnl_ctrl_30; wire [15:0] ch2_out_chnl_ctrl_30; wire [15:0] ch3_out_chnl_ctrl_30; wire [15:0] ch0_in_chnl_ctrl_31; wire [15:0] ch1_in_chnl_ctrl_31; wire [15:0] ch2_in_chnl_ctrl_31; wire [15:0] ch3_in_chnl_ctrl_31; wire [15:0] ch0_out_chnl_ctrl_31; wire [15:0] ch1_out_chnl_ctrl_31; wire [15:0] ch2_out_chnl_ctrl_31; wire [15:0] ch3_out_chnl_ctrl_31; wire [15:0] ch0_in_chnl_ctrl_32; wire [15:0] ch1_in_chnl_ctrl_32; wire [15:0] ch2_in_chnl_ctrl_32; wire [15:0] ch3_in_chnl_ctrl_32; wire [15:0] ch0_out_chnl_ctrl_32; wire [15:0] ch1_out_chnl_ctrl_32; wire [15:0] ch2_out_chnl_ctrl_32; wire [15:0] ch3_out_chnl_ctrl_32; wire [15:0] ch0_in_chnl_ctrl_33; wire [15:0] ch1_in_chnl_ctrl_33; wire [15:0] ch2_in_chnl_ctrl_33; wire [15:0] ch3_in_chnl_ctrl_33; wire [15:0] ch0_out_chnl_ctrl_33; wire [15:0] ch1_out_chnl_ctrl_33; wire [15:0] ch2_out_chnl_ctrl_33; wire [15:0] ch3_out_chnl_ctrl_33; wire [15:0] ch0_in_chnl_ctrl_34; wire [15:0] ch1_in_chnl_ctrl_34; wire [15:0] ch2_in_chnl_ctrl_34; wire [15:0] ch3_in_chnl_ctrl_34; wire [15:0] ch0_out_chnl_ctrl_34; wire [15:0] ch1_out_chnl_ctrl_34; wire [15:0] ch2_out_chnl_ctrl_34; wire [15:0] ch3_out_chnl_ctrl_34; wire [15:0] ch0_in_chnl_ctrl_35; wire [15:0] ch1_in_chnl_ctrl_35; wire [15:0] ch2_in_chnl_ctrl_35; wire [15:0] ch3_in_chnl_ctrl_35; wire [15:0] ch0_out_chnl_ctrl_35; wire [15:0] ch1_out_chnl_ctrl_35; wire [15:0] ch2_out_chnl_ctrl_35; wire [15:0] ch3_out_chnl_ctrl_35; wire [15:0] ch0_in_chnl_ctrl_36; wire [15:0] ch1_in_chnl_ctrl_36; wire [15:0] ch2_in_chnl_ctrl_36; wire [15:0] ch3_in_chnl_ctrl_36; wire [15:0] ch0_out_chnl_ctrl_36; wire [15:0] ch1_out_chnl_ctrl_36; wire [15:0] ch2_out_chnl_ctrl_36; wire [15:0] ch3_out_chnl_ctrl_36; wire [15:0] ch0_in_chnl_ctrl_37; wire [15:0] ch1_in_chnl_ctrl_37; wire [15:0] ch2_in_chnl_ctrl_37; wire [15:0] ch3_in_chnl_ctrl_37; wire [15:0] ch0_out_chnl_ctrl_37; wire [15:0] ch1_out_chnl_ctrl_37; wire [15:0] ch2_out_chnl_ctrl_37; wire [15:0] ch3_out_chnl_ctrl_37; wire [15:0] ch0_in_chnl_ctrl_38; wire [15:0] ch1_in_chnl_ctrl_38; wire [15:0] ch2_in_chnl_ctrl_38; wire [15:0] ch3_in_chnl_ctrl_38; wire [15:0] ch0_out_chnl_ctrl_38; wire [15:0] ch1_out_chnl_ctrl_38; wire [15:0] ch2_out_chnl_ctrl_38; wire [15:0] ch3_out_chnl_ctrl_38; wire [15:0] ch0_in_chnl_ctrl_39; wire [15:0] ch1_in_chnl_ctrl_39; wire [15:0] ch2_in_chnl_ctrl_39; wire [15:0] ch3_in_chnl_ctrl_39; wire [15:0] ch0_out_chnl_ctrl_39; wire [15:0] ch1_out_chnl_ctrl_39; wire [15:0] ch2_out_chnl_ctrl_39; wire [15:0] ch3_out_chnl_ctrl_39; wire [15:0] ch0_in_chnl_ctrl_40; wire [15:0] ch1_in_chnl_ctrl_40; wire [15:0] ch2_in_chnl_ctrl_40; wire [15:0] ch3_in_chnl_ctrl_40; wire [15:0] ch0_out_chnl_ctrl_40; wire [15:0] ch1_out_chnl_ctrl_40; wire [15:0] ch2_out_chnl_ctrl_40; wire [15:0] ch3_out_chnl_ctrl_40; wire [15:0] ch0_in_chnl_ctrl_41; wire [15:0] ch1_in_chnl_ctrl_41; wire [15:0] ch2_in_chnl_ctrl_41; wire [15:0] ch3_in_chnl_ctrl_41; wire [15:0] ch0_out_chnl_ctrl_41; wire [15:0] ch1_out_chnl_ctrl_41; wire [15:0] ch2_out_chnl_ctrl_41; wire [15:0] ch3_out_chnl_ctrl_41; wire [15:0] ch0_in_chnl_ctrl_42; wire [15:0] ch1_in_chnl_ctrl_42; wire [15:0] ch2_in_chnl_ctrl_42; wire [15:0] ch3_in_chnl_ctrl_42; wire [15:0] ch0_out_chnl_ctrl_42; wire [15:0] ch1_out_chnl_ctrl_42; wire [15:0] ch2_out_chnl_ctrl_42; wire [15:0] ch3_out_chnl_ctrl_42; // reserved wire [15:0] ch0_in_chnl_ctrl_43; wire [15:0] ch1_in_chnl_ctrl_43; wire [15:0] ch2_in_chnl_ctrl_43; wire [15:0] ch3_in_chnl_ctrl_43; wire [15:0] ch0_out_chnl_ctrl_43; wire [15:0] ch1_out_chnl_ctrl_43; wire [15:0] ch2_out_chnl_ctrl_43; wire [15:0] ch3_out_chnl_ctrl_43; wire [15:0] ch0_in_chnl_ctrl_44; wire [15:0] ch1_in_chnl_ctrl_44; wire [15:0] ch2_in_chnl_ctrl_44; wire [15:0] ch3_in_chnl_ctrl_44; wire [15:0] ch0_out_chnl_ctrl_44; wire [15:0] ch1_out_chnl_ctrl_44; wire [15:0] ch2_out_chnl_ctrl_44; wire [15:0] ch3_out_chnl_ctrl_44; wire [15:0] ch0_in_chnl_ctrl_45; wire [15:0] ch1_in_chnl_ctrl_45; wire [15:0] ch2_in_chnl_ctrl_45; wire [15:0] ch3_in_chnl_ctrl_45; wire [15:0] ch0_out_chnl_ctrl_45; wire [15:0] ch1_out_chnl_ctrl_45; wire [15:0] ch2_out_chnl_ctrl_45; wire [15:0] ch3_out_chnl_ctrl_45; wire [15:0] ch0_in_chnl_ctrl_46; wire [15:0] ch1_in_chnl_ctrl_46; wire [15:0] ch2_in_chnl_ctrl_46; wire [15:0] ch3_in_chnl_ctrl_46; wire [15:0] ch0_out_chnl_ctrl_46; wire [15:0] ch1_out_chnl_ctrl_46; wire [15:0] ch2_out_chnl_ctrl_46; wire [15:0] ch3_out_chnl_ctrl_46; wire [15:0] ch0_in_chnl_ctrl_47; wire [15:0] ch1_in_chnl_ctrl_47; wire [15:0] ch2_in_chnl_ctrl_47; wire [15:0] ch3_in_chnl_ctrl_47; wire [15:0] ch0_out_chnl_ctrl_47; wire [15:0] ch1_out_chnl_ctrl_47; wire [15:0] ch2_out_chnl_ctrl_47; wire [15:0] ch3_out_chnl_ctrl_47; wire [15:0] ch0_in_chnl_ctrl_48; wire [15:0] ch1_in_chnl_ctrl_48; wire [15:0] ch2_in_chnl_ctrl_48; wire [15:0] ch3_in_chnl_ctrl_48; wire [15:0] ch0_out_chnl_ctrl_48; wire [15:0] ch1_out_chnl_ctrl_48; wire [15:0] ch2_out_chnl_ctrl_48; wire [15:0] ch3_out_chnl_ctrl_48; wire [15:0] ch0_in_chnl_ctrl_49; wire [15:0] ch1_in_chnl_ctrl_49; wire [15:0] ch2_in_chnl_ctrl_49; wire [15:0] ch3_in_chnl_ctrl_49; wire [15:0] ch0_out_chnl_ctrl_49; wire [15:0] ch1_out_chnl_ctrl_49; wire [15:0] ch2_out_chnl_ctrl_49; wire [15:0] ch3_out_chnl_ctrl_49; wire [15:0] ch0_in_chnl_ctrl_50; wire [15:0] ch1_in_chnl_ctrl_50; wire [15:0] ch2_in_chnl_ctrl_50; wire [15:0] ch3_in_chnl_ctrl_50; wire [15:0] ch0_out_chnl_ctrl_50; wire [15:0] ch1_out_chnl_ctrl_50; wire [15:0] ch2_out_chnl_ctrl_50; wire [15:0] ch3_out_chnl_ctrl_50; wire [15:0] ch0_in_chnl_ctrl_51; wire [15:0] ch1_in_chnl_ctrl_51; wire [15:0] ch2_in_chnl_ctrl_51; wire [15:0] ch3_in_chnl_ctrl_51; wire [15:0] ch0_out_chnl_ctrl_51; wire [15:0] ch1_out_chnl_ctrl_51; wire [15:0] ch2_out_chnl_ctrl_51; wire [15:0] ch3_out_chnl_ctrl_51; wire [15:0] ch0_in_chnl_ctrl_52; wire [15:0] ch1_in_chnl_ctrl_52; wire [15:0] ch2_in_chnl_ctrl_52; wire [15:0] ch3_in_chnl_ctrl_52; wire [15:0] ch0_out_chnl_ctrl_52; wire [15:0] ch1_out_chnl_ctrl_52; wire [15:0] ch2_out_chnl_ctrl_52; wire [15:0] ch3_out_chnl_ctrl_52; wire [15:0] ch0_in_chnl_ctrl_53; wire [15:0] ch1_in_chnl_ctrl_53; wire [15:0] ch2_in_chnl_ctrl_53; wire [15:0] ch3_in_chnl_ctrl_53; wire [15:0] ch0_out_chnl_ctrl_53; wire [15:0] ch1_out_chnl_ctrl_53; wire [15:0] ch2_out_chnl_ctrl_53; wire [15:0] ch3_out_chnl_ctrl_53; //------------------------------------------------------------- // TXPCS CRAM ------------------------------------------------- //------------------------------------------------------------- wire [149:0] ch0_txpcsdprioin_logic; wire [149:0] ch1_txpcsdprioin_logic; wire [149:0] ch2_txpcsdprioin_logic; wire [149:0] ch3_txpcsdprioin_logic; wire [149:0] ch0_txpcsdprioin_phy; wire [149:0] ch1_txpcsdprioin_phy; wire [149:0] ch2_txpcsdprioin_phy; wire [149:0] ch3_txpcsdprioin_phy; wire [149:0] ch0_txpcsdprioout_logic; wire [149:0] ch1_txpcsdprioout_logic; wire [149:0] ch2_txpcsdprioout_logic; wire [149:0] ch3_txpcsdprioout_logic; wire [149:0] ch0_txpcsdprioout_phy; wire [149:0] ch1_txpcsdprioout_phy; wire [149:0] ch2_txpcsdprioout_phy; wire [149:0] ch3_txpcsdprioout_phy; //------------------------------------------------------------- // RXPCS CRAM ------------------------------------------------- //------------------------------------------------------------- wire [399:0] ch0_rxpcsdprioin_logic; wire [399:0] ch1_rxpcsdprioin_logic; wire [399:0] ch2_rxpcsdprioin_logic; wire [399:0] ch3_rxpcsdprioin_logic; wire [399:0] ch0_rxpcsdprioin_phy; wire [399:0] ch1_rxpcsdprioin_phy; wire [399:0] ch2_rxpcsdprioin_phy; wire [399:0] ch3_rxpcsdprioin_phy; wire [399:0] ch0_rxpcsdprioout_logic; wire [399:0] ch1_rxpcsdprioout_logic; wire [399:0] ch2_rxpcsdprioout_logic; wire [399:0] ch3_rxpcsdprioout_logic; wire [399:0] ch0_rxpcsdprioout_phy; wire [399:0] ch1_rxpcsdprioout_phy; wire [399:0] ch2_rxpcsdprioout_phy; wire [399:0] ch3_rxpcsdprioout_phy; //------------------------------------------------------------- // PLL CRAM --------------------------------------------------- //------------------------------------------------------------- wire [299 : 0] ch0_rxplldprioin_logic; wire [299 : 0] ch1_rxplldprioin_logic; wire [299 : 0] ch2_rxplldprioin_logic; wire [299 : 0] ch3_rxplldprioin_logic; wire [299 : 0] ch4_rxtxplldprioin_logic; wire [299 : 0] ch5_rxtxplldprioin_logic; wire [299 : 0] ch0_rxplldprioin_phy; wire [299 : 0] ch1_rxplldprioin_phy; wire [299 : 0] ch2_rxplldprioin_phy; wire [299 : 0] ch3_rxplldprioin_phy; wire [299 : 0] ch4_rxtxplldprioin_phy; wire [299 : 0] ch5_rxtxplldprioin_phy; wire [299 : 0] ch0_rxplldprioout_logic; wire [299 : 0] ch1_rxplldprioout_logic; wire [299 : 0] ch2_rxplldprioout_logic; wire [299 : 0] ch3_rxplldprioout_logic; wire [299 : 0] ch4_rxtxplldprioout_logic; wire [299 : 0] ch5_rxtxplldprioout_logic; wire [299 : 0] ch0_rxplldprioout_phy; wire [299 : 0] ch1_rxplldprioout_phy; wire [299 : 0] ch2_rxplldprioout_phy; wire [299 : 0] ch3_rxplldprioout_phy; wire [299 : 0] ch4_rxtxplldprioout_phy; wire [299 : 0] ch5_rxtxplldprioout_phy; //------------------------------------------------------------- // TXPMA CRAM ------------------------------------------------- //------------------------------------------------------------- wire [299:0] ch0_txpmadprioin_logic; wire [299:0] ch1_txpmadprioin_logic; wire [299:0] ch2_txpmadprioin_logic; wire [299:0] ch3_txpmadprioin_logic; wire [299:0] ch4_txpmadprioin_logic; wire [299:0] ch5_txpmadprioin_logic; wire [299:0] ch0_txpmadprioin_phy; wire [299:0] ch1_txpmadprioin_phy; wire [299:0] ch2_txpmadprioin_phy; wire [299:0] ch3_txpmadprioin_phy; wire [299:0] ch4_txpmadprioin_phy; wire [299:0] ch5_txpmadprioin_phy; wire [299:0] ch0_txpmadprioout_logic; wire [299:0] ch1_txpmadprioout_logic; wire [299:0] ch2_txpmadprioout_logic; wire [299:0] ch3_txpmadprioout_logic; wire [299:0] ch4_txpmadprioout_logic; wire [299:0] ch5_txpmadprioout_logic; wire [299:0] ch0_txpmadprioout_phy; wire [299:0] ch1_txpmadprioout_phy; wire [299:0] ch2_txpmadprioout_phy; wire [299:0] ch3_txpmadprioout_phy; wire [299:0] ch4_txpmadprioout_phy; wire [299:0] ch5_txpmadprioout_phy; //------------------------------------------------------------- // RXPMA CRAM ------------------------------------------------- //------------------------------------------------------------- wire [299:0] ch0_rxpmadprioin_logic; wire [299:0] ch1_rxpmadprioin_logic; wire [299:0] ch2_rxpmadprioin_logic; wire [299:0] ch3_rxpmadprioin_logic; wire [299:0] ch4_rxpmadprioin_logic; wire [299:0] ch5_rxpmadprioin_logic; wire [299:0] ch0_rxpmadprioin_phy; wire [299:0] ch1_rxpmadprioin_phy; wire [299:0] ch2_rxpmadprioin_phy; wire [299:0] ch3_rxpmadprioin_phy; wire [299:0] ch4_rxpmadprioin_phy; wire [299:0] ch5_rxpmadprioin_phy; wire [299:0] ch0_rxpmadprioout_logic; wire [299:0] ch1_rxpmadprioout_logic; wire [299:0] ch2_rxpmadprioout_logic; wire [299:0] ch3_rxpmadprioout_logic; wire [299:0] ch4_rxpmadprioout_logic; wire [299:0] ch5_rxpmadprioout_logic; wire [299:0] ch0_rxpmadprioout_phy; wire [299:0] ch1_rxpmadprioout_phy; wire [299:0] ch2_rxpmadprioout_phy; wire [299:0] ch3_rxpmadprioout_phy; wire [299:0] ch4_rxpmadprioout_phy; wire [299:0] ch5_rxpmadprioout_phy; //------------------------------------------------------------- // CMUDivider CRAM ------------------------------------------- //------------------------------------------------------------- wire [99:0] ch0_cmudividerdprioin_logic; wire [99:0] ch1_cmudividerdprioin_logic; wire [99:0] ch2_cmudividerdprioin_logic; wire [99:0] ch3_cmudividerdprioin_logic; wire [99:0] ch4_cmudividerdprioin_logic; wire [99:0] ch5_cmudividerdprioin_logic; wire [99:0] ch0_cmudividerdprioin_phy; wire [99:0] ch1_cmudividerdprioin_phy; wire [99:0] ch2_cmudividerdprioin_phy; wire [99:0] ch3_cmudividerdprioin_phy; wire [99:0] ch4_cmudividerdprioin_phy; wire [99:0] ch5_cmudividerdprioin_phy; wire [99:0] ch0_cmudividerdprioout_logic; wire [99:0] ch1_cmudividerdprioout_logic; wire [99:0] ch2_cmudividerdprioout_logic; wire [99:0] ch3_cmudividerdprioout_logic; wire [99:0] ch4_cmudividerdprioout_logic; wire [99:0] ch5_cmudividerdprioout_logic; wire [99:0] ch0_cmudividerdprioout_phy; wire [99:0] ch1_cmudividerdprioout_phy; wire [99:0] ch2_cmudividerdprioout_phy; wire [99:0] ch3_cmudividerdprioout_phy; wire [99:0] ch4_cmudividerdprioout_phy; wire [99:0] ch5_cmudividerdprioout_phy; // debug dump reg [31:0] dbg_file; // ------------------------------------------------------------ // read in para and populate csr ------------------------------ // ------------------------------------------------------------ // TXPCS assign ch0_txpcsdprioin_logic = txpcsdprioin [149:0]; assign ch1_txpcsdprioin_logic = txpcsdprioin [299:150]; assign ch2_txpcsdprioin_logic = txpcsdprioin [449:300]; assign ch3_txpcsdprioin_logic = txpcsdprioin [599:450]; // RXPCS assign ch0_rxpcsdprioin_logic = rxpcsdprioin [399:0]; assign ch1_rxpcsdprioin_logic = rxpcsdprioin [799:400]; assign ch2_rxpcsdprioin_logic = rxpcsdprioin [1199:800]; assign ch3_rxpcsdprioin_logic = rxpcsdprioin [1599:1200]; //TXPMA assign ch0_txpmadprioin_logic = txpmadprioin [299:0]; assign ch1_txpmadprioin_logic = txpmadprioin [599:300]; assign ch2_txpmadprioin_logic = txpmadprioin [899:600]; assign ch3_txpmadprioin_logic = txpmadprioin [1199:900]; assign ch4_txpmadprioin_logic = txpmadprioin [1499:1200]; assign ch5_txpmadprioin_logic = txpmadprioin [1799:1500]; //RXPMA assign ch0_rxpmadprioin_logic = rxpmadprioin [299:0]; assign ch1_rxpmadprioin_logic = rxpmadprioin [599:300]; assign ch2_rxpmadprioin_logic = rxpmadprioin [899:600]; assign ch3_rxpmadprioin_logic = rxpmadprioin [1199:900]; assign ch4_rxpmadprioin_logic = rxpmadprioin [1499:1200]; assign ch5_rxpmadprioin_logic = rxpmadprioin [1799:1500]; // PLL assign ch0_rxplldprioin_logic = cmuplldprioin [ 299 : 0 ]; assign ch1_rxplldprioin_logic = cmuplldprioin [ 599 : 300 ]; assign ch2_rxplldprioin_logic = cmuplldprioin [ 899 : 600 ]; assign ch3_rxplldprioin_logic = cmuplldprioin [ 1199 : 900 ]; assign ch4_rxtxplldprioin_logic = cmuplldprioin [ 1499 : 1200 ]; assign ch5_rxtxplldprioin_logic = cmuplldprioin [ 1799 : 1500 ]; // CMUDivider assign ch0_cmudividerdprioin_logic = cmudividerdprioin [99:0]; assign ch1_cmudividerdprioin_logic = cmudividerdprioin [199:100]; assign ch2_cmudividerdprioin_logic = cmudividerdprioin [299:200]; assign ch3_cmudividerdprioin_logic = cmudividerdprioin [399:300]; assign ch4_cmudividerdprioin_logic = cmudividerdprioin [499:400]; assign ch5_cmudividerdprioin_logic = cmudividerdprioin [599:500]; // ------- logic to physical mapping ------------------------- // TXPCS assign ch0_txpcsdprioin_phy = (tx0_logical_to_physical_mapping == 0) ? ch0_txpcsdprioin_logic : (tx1_logical_to_physical_mapping == 0) ? ch1_txpcsdprioin_logic : (tx2_logical_to_physical_mapping == 0) ? ch2_txpcsdprioin_logic : (tx3_logical_to_physical_mapping == 0) ? ch3_txpcsdprioin_logic : ch0_txpcsdprioin_logic; assign ch1_txpcsdprioin_phy = (tx0_logical_to_physical_mapping == 1) ? ch0_txpcsdprioin_logic : (tx1_logical_to_physical_mapping == 1) ? ch1_txpcsdprioin_logic : (tx2_logical_to_physical_mapping == 1) ? ch2_txpcsdprioin_logic : (tx3_logical_to_physical_mapping == 1) ? ch3_txpcsdprioin_logic : ch1_txpcsdprioin_logic; assign ch2_txpcsdprioin_phy = (tx0_logical_to_physical_mapping == 2) ? ch0_txpcsdprioin_logic : (tx1_logical_to_physical_mapping == 2) ? ch1_txpcsdprioin_logic : (tx2_logical_to_physical_mapping == 2) ? ch2_txpcsdprioin_logic : (tx3_logical_to_physical_mapping == 2) ? ch3_txpcsdprioin_logic : ch2_txpcsdprioin_logic; assign ch3_txpcsdprioin_phy = (tx0_logical_to_physical_mapping == 3) ? ch0_txpcsdprioin_logic : (tx1_logical_to_physical_mapping == 3) ? ch1_txpcsdprioin_logic : (tx2_logical_to_physical_mapping == 3) ? ch2_txpcsdprioin_logic : (tx3_logical_to_physical_mapping == 3) ? ch3_txpcsdprioin_logic : ch3_txpcsdprioin_logic; // RXPCS assign ch0_rxpcsdprioin_phy = (rx0_logical_to_physical_mapping == 0) ? ch0_rxpcsdprioin_logic : (rx1_logical_to_physical_mapping == 0) ? ch1_rxpcsdprioin_logic : (rx2_logical_to_physical_mapping == 0) ? ch2_rxpcsdprioin_logic : (rx3_logical_to_physical_mapping == 0) ? ch3_rxpcsdprioin_logic : ch0_rxpcsdprioin_logic; assign ch1_rxpcsdprioin_phy = (rx0_logical_to_physical_mapping == 1) ? ch0_rxpcsdprioin_logic : (rx1_logical_to_physical_mapping == 1) ? ch1_rxpcsdprioin_logic : (rx2_logical_to_physical_mapping == 1) ? ch2_rxpcsdprioin_logic : (rx3_logical_to_physical_mapping == 1) ? ch3_rxpcsdprioin_logic : ch1_rxpcsdprioin_logic; assign ch2_rxpcsdprioin_phy = (rx0_logical_to_physical_mapping == 2) ? ch0_rxpcsdprioin_logic : (rx1_logical_to_physical_mapping == 2) ? ch1_rxpcsdprioin_logic : (rx2_logical_to_physical_mapping == 2) ? ch2_rxpcsdprioin_logic : (rx3_logical_to_physical_mapping == 2) ? ch3_rxpcsdprioin_logic : ch2_rxpcsdprioin_logic; assign ch3_rxpcsdprioin_phy = (rx0_logical_to_physical_mapping == 3) ? ch0_rxpcsdprioin_logic : (rx1_logical_to_physical_mapping == 3) ? ch1_rxpcsdprioin_logic : (rx2_logical_to_physical_mapping == 3) ? ch2_rxpcsdprioin_logic : (rx3_logical_to_physical_mapping == 3) ? ch3_rxpcsdprioin_logic : ch3_rxpcsdprioin_logic; //TXPMA assign ch0_txpmadprioin_phy = (tx0_logical_to_physical_mapping == 0) ? ch0_txpmadprioin_logic : (tx1_logical_to_physical_mapping == 0) ? ch1_txpmadprioin_logic : (tx2_logical_to_physical_mapping == 0) ? ch2_txpmadprioin_logic : (tx3_logical_to_physical_mapping == 0) ? ch3_txpmadprioin_logic : (tx4_logical_to_physical_mapping == 0) ? ch4_txpmadprioin_logic : (tx5_logical_to_physical_mapping == 0) ? ch5_txpmadprioin_logic : ch0_txpmadprioin_logic; assign ch1_txpmadprioin_phy = (tx0_logical_to_physical_mapping == 1) ? ch0_txpmadprioin_logic : (tx1_logical_to_physical_mapping == 1) ? ch1_txpmadprioin_logic : (tx2_logical_to_physical_mapping == 1) ? ch2_txpmadprioin_logic : (tx3_logical_to_physical_mapping == 1) ? ch3_txpmadprioin_logic : (tx4_logical_to_physical_mapping == 1) ? ch4_txpmadprioin_logic : (tx5_logical_to_physical_mapping == 1) ? ch5_txpmadprioin_logic : ch1_txpmadprioin_logic; assign ch2_txpmadprioin_phy = (tx0_logical_to_physical_mapping == 2) ? ch0_txpmadprioin_logic : (tx1_logical_to_physical_mapping == 2) ? ch1_txpmadprioin_logic : (tx2_logical_to_physical_mapping == 2) ? ch2_txpmadprioin_logic : (tx3_logical_to_physical_mapping == 2) ? ch3_txpmadprioin_logic : (tx4_logical_to_physical_mapping == 2) ? ch4_txpmadprioin_logic : (tx5_logical_to_physical_mapping == 2) ? ch5_txpmadprioin_logic : ch2_txpmadprioin_logic; assign ch3_txpmadprioin_phy = (tx0_logical_to_physical_mapping == 3) ? ch0_txpmadprioin_logic : (tx1_logical_to_physical_mapping == 3) ? ch1_txpmadprioin_logic : (tx2_logical_to_physical_mapping == 3) ? ch2_txpmadprioin_logic : (tx3_logical_to_physical_mapping == 3) ? ch3_txpmadprioin_logic : (tx4_logical_to_physical_mapping == 3) ? ch4_txpmadprioin_logic : (tx5_logical_to_physical_mapping == 3) ? ch5_txpmadprioin_logic : ch3_txpmadprioin_logic; assign ch4_txpmadprioin_phy = (tx0_logical_to_physical_mapping == 4) ? ch0_txpmadprioin_logic : (tx1_logical_to_physical_mapping == 4) ? ch1_txpmadprioin_logic : (tx2_logical_to_physical_mapping == 4) ? ch2_txpmadprioin_logic : (tx3_logical_to_physical_mapping == 4) ? ch3_txpmadprioin_logic : (tx4_logical_to_physical_mapping == 4) ? ch4_txpmadprioin_logic : (tx5_logical_to_physical_mapping == 4) ? ch5_txpmadprioin_logic : ch4_txpmadprioin_logic; assign ch5_txpmadprioin_phy = (tx0_logical_to_physical_mapping == 5) ? ch0_txpmadprioin_logic : (tx1_logical_to_physical_mapping == 5) ? ch1_txpmadprioin_logic : (tx2_logical_to_physical_mapping == 5) ? ch2_txpmadprioin_logic : (tx3_logical_to_physical_mapping == 5) ? ch3_txpmadprioin_logic : (tx4_logical_to_physical_mapping == 5) ? ch4_txpmadprioin_logic : (tx5_logical_to_physical_mapping == 5) ? ch5_txpmadprioin_logic : ch5_txpmadprioin_logic; //RXPMA assign ch0_rxpmadprioin_phy = (rx0_logical_to_physical_mapping == 0) ? ch0_rxpmadprioin_logic : (rx1_logical_to_physical_mapping == 0) ? ch1_rxpmadprioin_logic : (rx2_logical_to_physical_mapping == 0) ? ch2_rxpmadprioin_logic : (rx3_logical_to_physical_mapping == 0) ? ch3_rxpmadprioin_logic : (rx4_logical_to_physical_mapping == 0) ? ch4_rxpmadprioin_logic : (rx5_logical_to_physical_mapping == 0) ? ch5_rxpmadprioin_logic : ch0_rxpmadprioin_logic; assign ch1_rxpmadprioin_phy = (rx0_logical_to_physical_mapping == 1) ? ch0_rxpmadprioin_logic : (rx1_logical_to_physical_mapping == 1) ? ch1_rxpmadprioin_logic : (rx2_logical_to_physical_mapping == 1) ? ch2_rxpmadprioin_logic : (rx3_logical_to_physical_mapping == 1) ? ch3_rxpmadprioin_logic : (rx4_logical_to_physical_mapping == 1) ? ch4_rxpmadprioin_logic : (rx5_logical_to_physical_mapping == 1) ? ch5_rxpmadprioin_logic : ch1_rxpmadprioin_logic; assign ch2_rxpmadprioin_phy = (rx0_logical_to_physical_mapping == 2) ? ch0_rxpmadprioin_logic : (rx1_logical_to_physical_mapping == 2) ? ch1_rxpmadprioin_logic : (rx2_logical_to_physical_mapping == 2) ? ch2_rxpmadprioin_logic : (rx3_logical_to_physical_mapping == 2) ? ch3_rxpmadprioin_logic : (rx4_logical_to_physical_mapping == 2) ? ch4_rxpmadprioin_logic : (rx5_logical_to_physical_mapping == 2) ? ch5_rxpmadprioin_logic : ch2_rxpmadprioin_logic; assign ch3_rxpmadprioin_phy = (rx0_logical_to_physical_mapping == 3) ? ch0_rxpmadprioin_logic : (rx1_logical_to_physical_mapping == 3) ? ch1_rxpmadprioin_logic : (rx2_logical_to_physical_mapping == 3) ? ch2_rxpmadprioin_logic : (rx3_logical_to_physical_mapping == 3) ? ch3_rxpmadprioin_logic : (rx4_logical_to_physical_mapping == 3) ? ch4_rxpmadprioin_logic : (rx5_logical_to_physical_mapping == 3) ? ch5_rxpmadprioin_logic : ch3_rxpmadprioin_logic; assign ch4_rxpmadprioin_phy = (rx0_logical_to_physical_mapping == 4) ? ch0_rxpmadprioin_logic : (rx1_logical_to_physical_mapping == 4) ? ch1_rxpmadprioin_logic : (rx2_logical_to_physical_mapping == 4) ? ch2_rxpmadprioin_logic : (rx3_logical_to_physical_mapping == 4) ? ch3_rxpmadprioin_logic : (rx4_logical_to_physical_mapping == 4) ? ch4_rxpmadprioin_logic : (rx5_logical_to_physical_mapping == 4) ? ch5_rxpmadprioin_logic : ch4_rxpmadprioin_logic; assign ch5_rxpmadprioin_phy = (rx0_logical_to_physical_mapping == 5) ? ch0_rxpmadprioin_logic : (rx1_logical_to_physical_mapping == 5) ? ch1_rxpmadprioin_logic : (rx2_logical_to_physical_mapping == 5) ? ch2_rxpmadprioin_logic : (rx3_logical_to_physical_mapping == 5) ? ch3_rxpmadprioin_logic : (rx4_logical_to_physical_mapping == 5) ? ch4_rxpmadprioin_logic : (rx5_logical_to_physical_mapping == 5) ? ch5_rxpmadprioin_logic : ch5_rxpmadprioin_logic; // PLL assign ch0_rxplldprioin_phy = (pll0_logical_to_physical_mapping == 0) ? ch0_rxplldprioin_logic : (pll1_logical_to_physical_mapping == 0) ? ch1_rxplldprioin_logic : (pll2_logical_to_physical_mapping == 0) ? ch2_rxplldprioin_logic : (pll3_logical_to_physical_mapping == 0) ? ch3_rxplldprioin_logic : (pll4_logical_to_physical_mapping == 0) ? ch4_rxtxplldprioin_logic : (pll5_logical_to_physical_mapping == 0) ? ch5_rxtxplldprioin_logic : ch0_rxplldprioin_logic; assign ch1_rxplldprioin_phy = (pll0_logical_to_physical_mapping == 1) ? ch0_rxplldprioin_logic : (pll1_logical_to_physical_mapping == 1) ? ch1_rxplldprioin_logic : (pll2_logical_to_physical_mapping == 1) ? ch2_rxplldprioin_logic : (pll3_logical_to_physical_mapping == 1) ? ch3_rxplldprioin_logic : (pll4_logical_to_physical_mapping == 1) ? ch4_rxtxplldprioin_logic : (pll5_logical_to_physical_mapping == 1) ? ch5_rxtxplldprioin_logic : ch1_rxplldprioin_logic; assign ch2_rxplldprioin_phy = (pll0_logical_to_physical_mapping == 2) ? ch0_rxplldprioin_logic : (pll1_logical_to_physical_mapping == 2) ? ch1_rxplldprioin_logic : (pll2_logical_to_physical_mapping == 2) ? ch2_rxplldprioin_logic : (pll3_logical_to_physical_mapping == 2) ? ch3_rxplldprioin_logic : (pll4_logical_to_physical_mapping == 2) ? ch4_rxtxplldprioin_logic : (pll5_logical_to_physical_mapping == 2) ? ch5_rxtxplldprioin_logic : ch2_rxplldprioin_logic; assign ch3_rxplldprioin_phy = (pll0_logical_to_physical_mapping == 3) ? ch0_rxplldprioin_logic : (pll1_logical_to_physical_mapping == 3) ? ch1_rxplldprioin_logic : (pll2_logical_to_physical_mapping == 3) ? ch2_rxplldprioin_logic : (pll3_logical_to_physical_mapping == 3) ? ch3_rxplldprioin_logic : (pll4_logical_to_physical_mapping == 3) ? ch4_rxtxplldprioin_logic : (pll5_logical_to_physical_mapping == 3) ? ch5_rxtxplldprioin_logic : ch3_rxplldprioin_logic; // only pll4/5 _logical_to_phy = {4, 5} assign ch4_rxtxplldprioin_phy = (pll0_logical_to_physical_mapping == 4) ? ch0_rxplldprioin_logic : (pll1_logical_to_physical_mapping == 4) ? ch1_rxplldprioin_logic : (pll2_logical_to_physical_mapping == 4) ? ch2_rxplldprioin_logic : (pll3_logical_to_physical_mapping == 4) ? ch3_rxplldprioin_logic : (pll4_logical_to_physical_mapping == 4) ? ch4_rxtxplldprioin_logic : (pll5_logical_to_physical_mapping == 4) ? ch5_rxtxplldprioin_logic : ch4_rxtxplldprioin_logic; assign ch5_rxtxplldprioin_phy = (pll0_logical_to_physical_mapping == 5) ? ch0_rxplldprioin_logic : (pll1_logical_to_physical_mapping == 5) ? ch1_rxplldprioin_logic : (pll2_logical_to_physical_mapping == 5) ? ch2_rxplldprioin_logic : (pll3_logical_to_physical_mapping == 5) ? ch3_rxplldprioin_logic : (pll4_logical_to_physical_mapping == 5) ? ch4_rxtxplldprioin_logic : (pll5_logical_to_physical_mapping == 5) ? ch5_rxtxplldprioin_logic : ch5_rxtxplldprioin_logic; // CMUDivider assign ch0_cmudividerdprioin_phy = (tx0_logical_to_physical_mapping == 0) ? ch0_cmudividerdprioin_logic : (tx1_logical_to_physical_mapping == 0) ? ch1_cmudividerdprioin_logic : (tx2_logical_to_physical_mapping == 0) ? ch2_cmudividerdprioin_logic : (tx3_logical_to_physical_mapping == 0) ? ch3_cmudividerdprioin_logic : (tx4_logical_to_physical_mapping == 0) ? ch4_cmudividerdprioin_logic : (tx5_logical_to_physical_mapping == 0) ? ch5_cmudividerdprioin_logic : ch0_cmudividerdprioin_logic; assign ch1_cmudividerdprioin_phy = (tx0_logical_to_physical_mapping == 1) ? ch0_cmudividerdprioin_logic : (tx1_logical_to_physical_mapping == 1) ? ch1_cmudividerdprioin_logic : (tx2_logical_to_physical_mapping == 1) ? ch2_cmudividerdprioin_logic : (tx3_logical_to_physical_mapping == 1) ? ch3_cmudividerdprioin_logic : (tx4_logical_to_physical_mapping == 1) ? ch4_cmudividerdprioin_logic : (tx5_logical_to_physical_mapping == 1) ? ch5_cmudividerdprioin_logic : ch1_cmudividerdprioin_logic; assign ch2_cmudividerdprioin_phy = (tx0_logical_to_physical_mapping == 2) ? ch0_cmudividerdprioin_logic : (tx1_logical_to_physical_mapping == 2) ? ch1_cmudividerdprioin_logic : (tx2_logical_to_physical_mapping == 2) ? ch2_cmudividerdprioin_logic : (tx3_logical_to_physical_mapping == 2) ? ch3_cmudividerdprioin_logic : (tx4_logical_to_physical_mapping == 2) ? ch4_cmudividerdprioin_logic : (tx5_logical_to_physical_mapping == 2) ? ch5_cmudividerdprioin_logic : ch2_cmudividerdprioin_logic; assign ch3_cmudividerdprioin_phy = (tx0_logical_to_physical_mapping == 3) ? ch0_cmudividerdprioin_logic : (tx1_logical_to_physical_mapping == 3) ? ch1_cmudividerdprioin_logic : (tx2_logical_to_physical_mapping == 3) ? ch2_cmudividerdprioin_logic : (tx3_logical_to_physical_mapping == 3) ? ch3_cmudividerdprioin_logic : (tx4_logical_to_physical_mapping == 3) ? ch4_cmudividerdprioin_logic : (tx5_logical_to_physical_mapping == 3) ? ch5_cmudividerdprioin_logic : ch3_cmudividerdprioin_logic; assign ch4_cmudividerdprioin_phy = (tx0_logical_to_physical_mapping == 4) ? ch0_cmudividerdprioin_logic : (tx1_logical_to_physical_mapping == 4) ? ch1_cmudividerdprioin_logic : (tx2_logical_to_physical_mapping == 4) ? ch2_cmudividerdprioin_logic : (tx3_logical_to_physical_mapping == 4) ? ch3_cmudividerdprioin_logic : (tx4_logical_to_physical_mapping == 4) ? ch4_cmudividerdprioin_logic : (tx5_logical_to_physical_mapping == 4) ? ch5_cmudividerdprioin_logic : ch4_cmudividerdprioin_logic; assign ch5_cmudividerdprioin_phy = (tx0_logical_to_physical_mapping == 5) ? ch0_cmudividerdprioin_logic : (tx1_logical_to_physical_mapping == 5) ? ch1_cmudividerdprioin_logic : (tx2_logical_to_physical_mapping == 5) ? ch2_cmudividerdprioin_logic : (tx3_logical_to_physical_mapping == 5) ? ch3_cmudividerdprioin_logic : (tx4_logical_to_physical_mapping == 5) ? ch4_cmudividerdprioin_logic : (tx5_logical_to_physical_mapping == 5) ? ch5_cmudividerdprioin_logic : ch5_cmudividerdprioin_logic; // -------- SW ordering ------------------------------------ //TXPCS assign ch0_in_chnl_ctrl_1 = ch0_txpcsdprioin_phy[`rforce_kchar_DP_TXPCS_IDX_0 : `rforce_disp_DP_TXPCS_IDX_0]; assign ch1_in_chnl_ctrl_1 = ch1_txpcsdprioin_phy[`rforce_kchar_DP_TXPCS_IDX_0 : `rforce_disp_DP_TXPCS_IDX_0]; assign ch2_in_chnl_ctrl_1 = ch2_txpcsdprioin_phy[`rforce_kchar_DP_TXPCS_IDX_0 : `rforce_disp_DP_TXPCS_IDX_0]; assign ch3_in_chnl_ctrl_1 = ch3_txpcsdprioin_phy[`rforce_kchar_DP_TXPCS_IDX_0 : `rforce_disp_DP_TXPCS_IDX_0]; assign ch0_in_chnl_ctrl_2 = ch0_txpcsdprioin_phy[`rendec_tx_DP_TXPCS_IDX_0 : `rtxpcsbypass_en_DP_TXPCS_IDX_0]; assign ch1_in_chnl_ctrl_2 = ch1_txpcsdprioin_phy[`rendec_tx_DP_TXPCS_IDX_0 : `rtxpcsbypass_en_DP_TXPCS_IDX_0]; assign ch2_in_chnl_ctrl_2 = ch2_txpcsdprioin_phy[`rendec_tx_DP_TXPCS_IDX_0 : `rtxpcsbypass_en_DP_TXPCS_IDX_0]; assign ch3_in_chnl_ctrl_2 = ch3_txpcsdprioin_phy[`rendec_tx_DP_TXPCS_IDX_0 : `rtxpcsbypass_en_DP_TXPCS_IDX_0]; assign ch0_in_chnl_ctrl_3 = ch0_txpcsdprioin_phy[`rtx_pipe_enable_DP_TXPCS_IDX_0 : `reserved_0_TB3_DP_TXPCS_IDX_0]; assign ch1_in_chnl_ctrl_3 = ch1_txpcsdprioin_phy[`rtx_pipe_enable_DP_TXPCS_IDX_0 : `reserved_0_TB3_DP_TXPCS_IDX_0]; assign ch2_in_chnl_ctrl_3 = ch2_txpcsdprioin_phy[`rtx_pipe_enable_DP_TXPCS_IDX_0 : `reserved_0_TB3_DP_TXPCS_IDX_0]; assign ch3_in_chnl_ctrl_3 = ch3_txpcsdprioin_phy[`rtx_pipe_enable_DP_TXPCS_IDX_0 : `reserved_0_TB3_DP_TXPCS_IDX_0]; assign ch0_in_chnl_ctrl_4 = ch0_txpcsdprioin_phy[`rself_sw_en_tx_DP_TXPCS_IDX_0 : `reserved_0_TB4_DP_TXPCS_IDX_0]; assign ch1_in_chnl_ctrl_4 = ch1_txpcsdprioin_phy[`rself_sw_en_tx_DP_TXPCS_IDX_0 : `reserved_0_TB4_DP_TXPCS_IDX_0]; assign ch2_in_chnl_ctrl_4 = ch2_txpcsdprioin_phy[`rself_sw_en_tx_DP_TXPCS_IDX_0 : `reserved_0_TB4_DP_TXPCS_IDX_0]; assign ch3_in_chnl_ctrl_4 = ch3_txpcsdprioin_phy[`rself_sw_en_tx_DP_TXPCS_IDX_0 : `reserved_0_TB4_DP_TXPCS_IDX_0]; assign ch0_in_chnl_ctrl_5 = ch0_rxpcsdprioin_phy[`reserved_0_TB5_DP_RXPCS_IDX_0 : `rrxpcsbypass_en_DP_RXPCS_IDX_0]; assign ch1_in_chnl_ctrl_5 = ch1_rxpcsdprioin_phy[`reserved_0_TB5_DP_RXPCS_IDX_0 : `rrxpcsbypass_en_DP_RXPCS_IDX_0]; assign ch2_in_chnl_ctrl_5 = ch2_rxpcsdprioin_phy[`reserved_0_TB5_DP_RXPCS_IDX_0 : `rrxpcsbypass_en_DP_RXPCS_IDX_0]; assign ch3_in_chnl_ctrl_5 = ch3_rxpcsdprioin_phy[`reserved_0_TB5_DP_RXPCS_IDX_0 : `rrxpcsbypass_en_DP_RXPCS_IDX_0]; assign ch0_in_chnl_ctrl_6 = ch0_rxpcsdprioin_phy[`resync_badcg_en_DP_RXPCS_IDX_1 : `rcomp_pat_32_DP_RXPCS_IDX_0]; assign ch1_in_chnl_ctrl_6 = ch1_rxpcsdprioin_phy[`resync_badcg_en_DP_RXPCS_IDX_1 : `rcomp_pat_32_DP_RXPCS_IDX_0]; assign ch2_in_chnl_ctrl_6 = ch2_rxpcsdprioin_phy[`resync_badcg_en_DP_RXPCS_IDX_1 : `rcomp_pat_32_DP_RXPCS_IDX_0]; assign ch3_in_chnl_ctrl_6 = ch3_rxpcsdprioin_phy[`resync_badcg_en_DP_RXPCS_IDX_1 : `rcomp_pat_32_DP_RXPCS_IDX_0]; assign ch0_in_chnl_ctrl_7 = ch0_rxpcsdprioin_phy[`rcomp_pat_31_DP_RXPCS_IDX_0 : `rcomp_pat_16_DP_RXPCS_IDX_0]; assign ch1_in_chnl_ctrl_7 = ch1_rxpcsdprioin_phy[`rcomp_pat_31_DP_RXPCS_IDX_0 : `rcomp_pat_16_DP_RXPCS_IDX_0]; assign ch2_in_chnl_ctrl_7 = ch2_rxpcsdprioin_phy[`rcomp_pat_31_DP_RXPCS_IDX_0 : `rcomp_pat_16_DP_RXPCS_IDX_0]; assign ch3_in_chnl_ctrl_7 = ch3_rxpcsdprioin_phy[`rcomp_pat_31_DP_RXPCS_IDX_0 : `rcomp_pat_16_DP_RXPCS_IDX_0]; assign ch0_in_chnl_ctrl_8 = ch0_rxpcsdprioin_phy[`rcomp_pat_15_DP_RXPCS_IDX_0 : `rcomp_pat_0_DP_RXPCS_IDX_0]; assign ch1_in_chnl_ctrl_8 = ch1_rxpcsdprioin_phy[`rcomp_pat_15_DP_RXPCS_IDX_0 : `rcomp_pat_0_DP_RXPCS_IDX_0]; assign ch2_in_chnl_ctrl_8 = ch2_rxpcsdprioin_phy[`rcomp_pat_15_DP_RXPCS_IDX_0 : `rcomp_pat_0_DP_RXPCS_IDX_0]; assign ch3_in_chnl_ctrl_8 = ch3_rxpcsdprioin_phy[`rcomp_pat_15_DP_RXPCS_IDX_0 : `rcomp_pat_0_DP_RXPCS_IDX_0]; assign ch0_in_chnl_ctrl_9 = ch0_rxpcsdprioin_phy[`rsync_sm_dis_DP_RXPCS_IDX_0 : `rbitloc_rev_en_DP_RXPCS_IDX_0]; assign ch1_in_chnl_ctrl_9 = ch1_rxpcsdprioin_phy[`rsync_sm_dis_DP_RXPCS_IDX_0 : `rbitloc_rev_en_DP_RXPCS_IDX_0]; assign ch2_in_chnl_ctrl_9 = ch2_rxpcsdprioin_phy[`rsync_sm_dis_DP_RXPCS_IDX_0 : `rbitloc_rev_en_DP_RXPCS_IDX_0]; assign ch3_in_chnl_ctrl_9 = ch3_rxpcsdprioin_phy[`rsync_sm_dis_DP_RXPCS_IDX_0 : `rbitloc_rev_en_DP_RXPCS_IDX_0]; assign ch0_in_chnl_ctrl_10 = ch0_rxpcsdprioin_phy[`rgnumber_DP_RXPCS_IDX_7 : `rknumber_DP_RXPCS_IDX_0]; assign ch1_in_chnl_ctrl_10 = ch1_rxpcsdprioin_phy[`rgnumber_DP_RXPCS_IDX_7 : `rknumber_DP_RXPCS_IDX_0]; assign ch2_in_chnl_ctrl_10 = ch2_rxpcsdprioin_phy[`rgnumber_DP_RXPCS_IDX_7 : `rknumber_DP_RXPCS_IDX_0]; assign ch3_in_chnl_ctrl_10 = ch3_rxpcsdprioin_phy[`rgnumber_DP_RXPCS_IDX_7 : `rknumber_DP_RXPCS_IDX_0]; assign ch0_in_chnl_ctrl_11 = ch0_rxpcsdprioin_phy[`rrundisp_DP_RXPCS_IDX_5 : `renpolinv_rx_DP_RXPCS_IDX_0]; assign ch1_in_chnl_ctrl_11 = ch1_rxpcsdprioin_phy[`rrundisp_DP_RXPCS_IDX_5 : `renpolinv_rx_DP_RXPCS_IDX_0]; assign ch2_in_chnl_ctrl_11 = ch2_rxpcsdprioin_phy[`rrundisp_DP_RXPCS_IDX_5 : `renpolinv_rx_DP_RXPCS_IDX_0]; assign ch3_in_chnl_ctrl_11 = ch3_rxpcsdprioin_phy[`rrundisp_DP_RXPCS_IDX_5 : `renpolinv_rx_DP_RXPCS_IDX_0]; assign ch0_in_chnl_ctrl_12 = ch0_rxpcsdprioin_phy[`rmatchen_DP_RXPCS_IDX_0 : `rclkcmpsq1p_0_DP_RXPCS_IDX_0]; assign ch1_in_chnl_ctrl_12 = ch1_rxpcsdprioin_phy[`rmatchen_DP_RXPCS_IDX_0 : `rclkcmpsq1p_0_DP_RXPCS_IDX_0]; assign ch2_in_chnl_ctrl_12 = ch2_rxpcsdprioin_phy[`rmatchen_DP_RXPCS_IDX_0 : `rclkcmpsq1p_0_DP_RXPCS_IDX_0]; assign ch3_in_chnl_ctrl_12 = ch3_rxpcsdprioin_phy[`rmatchen_DP_RXPCS_IDX_0 : `rclkcmpsq1p_0_DP_RXPCS_IDX_0]; assign ch0_in_chnl_ctrl_13 = ch0_rxpcsdprioin_phy[`rclkcmpsq1n_19_DP_RXPCS_IDX_0 : `rclkcmpsq1p_10_DP_RXPCS_IDX_0]; assign ch1_in_chnl_ctrl_13 = ch1_rxpcsdprioin_phy[`rclkcmpsq1n_19_DP_RXPCS_IDX_0 : `rclkcmpsq1p_10_DP_RXPCS_IDX_0]; assign ch2_in_chnl_ctrl_13 = ch2_rxpcsdprioin_phy[`rclkcmpsq1n_19_DP_RXPCS_IDX_0 : `rclkcmpsq1p_10_DP_RXPCS_IDX_0]; assign ch3_in_chnl_ctrl_13 = ch3_rxpcsdprioin_phy[`rclkcmpsq1n_19_DP_RXPCS_IDX_0 : `rclkcmpsq1p_10_DP_RXPCS_IDX_0]; assign ch0_in_chnl_ctrl_14 = ch0_rxpcsdprioin_phy[`rclkcmpsq1n_14_DP_RXPCS_IDX_0 : `rclkcmpsq1n_0_DP_RXPCS_IDX_0]; assign ch1_in_chnl_ctrl_14 = ch1_rxpcsdprioin_phy[`rclkcmpsq1n_14_DP_RXPCS_IDX_0 : `rclkcmpsq1n_0_DP_RXPCS_IDX_0]; assign ch2_in_chnl_ctrl_14 = ch2_rxpcsdprioin_phy[`rclkcmpsq1n_14_DP_RXPCS_IDX_0 : `rclkcmpsq1n_0_DP_RXPCS_IDX_0]; assign ch3_in_chnl_ctrl_14 = ch3_rxpcsdprioin_phy[`rclkcmpsq1n_14_DP_RXPCS_IDX_0 : `rclkcmpsq1n_0_DP_RXPCS_IDX_0]; assign ch0_in_chnl_ctrl_15 = ch0_rxpcsdprioin_phy[`rclkcmp_pipe_en_DP_RXPCS_IDX_0 : `rfull_threshold_DP_RXPCS_IDX_0]; assign ch1_in_chnl_ctrl_15 = ch1_rxpcsdprioin_phy[`rclkcmp_pipe_en_DP_RXPCS_IDX_0 : `rfull_threshold_DP_RXPCS_IDX_0]; assign ch2_in_chnl_ctrl_15 = ch2_rxpcsdprioin_phy[`rclkcmp_pipe_en_DP_RXPCS_IDX_0 : `rfull_threshold_DP_RXPCS_IDX_0]; assign ch3_in_chnl_ctrl_15 = ch3_rxpcsdprioin_phy[`rclkcmp_pipe_en_DP_RXPCS_IDX_0 : `rfull_threshold_DP_RXPCS_IDX_0]; assign ch0_in_chnl_ctrl_16 = ch0_rxpcsdprioin_phy[`rempty_threshold_DP_RXPCS_IDX_2 : `rfreq_sel_DP_RXPCS_IDX_0]; assign ch1_in_chnl_ctrl_16 = ch1_rxpcsdprioin_phy[`rempty_threshold_DP_RXPCS_IDX_2 : `rfreq_sel_DP_RXPCS_IDX_0]; assign ch2_in_chnl_ctrl_16 = ch2_rxpcsdprioin_phy[`rempty_threshold_DP_RXPCS_IDX_2 : `rfreq_sel_DP_RXPCS_IDX_0]; assign ch3_in_chnl_ctrl_16 = ch3_rxpcsdprioin_phy[`rempty_threshold_DP_RXPCS_IDX_2 : `rfreq_sel_DP_RXPCS_IDX_0]; assign ch0_in_chnl_ctrl_17 = ch0_rxpcsdprioin_phy[`rrxfifo_dis_DP_RXPCS_IDX_0 : `rtest_bus_sel_DP_RXPCS_IDX_0]; assign ch1_in_chnl_ctrl_17 = ch1_rxpcsdprioin_phy[`rrxfifo_dis_DP_RXPCS_IDX_0 : `rtest_bus_sel_DP_RXPCS_IDX_0]; assign ch2_in_chnl_ctrl_17 = ch2_rxpcsdprioin_phy[`rrxfifo_dis_DP_RXPCS_IDX_0 : `rtest_bus_sel_DP_RXPCS_IDX_0]; assign ch3_in_chnl_ctrl_17 = ch3_rxpcsdprioin_phy[`rrxfifo_dis_DP_RXPCS_IDX_0 : `rtest_bus_sel_DP_RXPCS_IDX_0]; assign ch0_in_chnl_ctrl_18 = ch0_rxpcsdprioin_phy[`reserved_0_TB18_DP_RXPCS_IDX_5 : `rbytordpat_0_DP_RXPCS_IDX_0]; assign ch1_in_chnl_ctrl_18 = ch1_rxpcsdprioin_phy[`reserved_0_TB18_DP_RXPCS_IDX_5 : `rbytordpat_0_DP_RXPCS_IDX_0]; assign ch2_in_chnl_ctrl_18 = ch2_rxpcsdprioin_phy[`reserved_0_TB18_DP_RXPCS_IDX_5 : `rbytordpat_0_DP_RXPCS_IDX_0]; assign ch3_in_chnl_ctrl_18 = ch3_rxpcsdprioin_phy[`reserved_0_TB18_DP_RXPCS_IDX_5 : `rbytordpat_0_DP_RXPCS_IDX_0]; assign ch0_in_chnl_ctrl_19 = ch0_rxpcsdprioin_phy[`reserved_0_TB19_DP_RXPCS_IDX_5 : `rbytordpad_DP_RXPCS_IDX_0]; assign ch1_in_chnl_ctrl_19 = ch1_rxpcsdprioin_phy[`reserved_0_TB19_DP_RXPCS_IDX_5 : `rbytordpad_DP_RXPCS_IDX_0]; assign ch2_in_chnl_ctrl_19 = ch2_rxpcsdprioin_phy[`reserved_0_TB19_DP_RXPCS_IDX_5 : `rbytordpad_DP_RXPCS_IDX_0]; assign ch3_in_chnl_ctrl_19 = ch3_rxpcsdprioin_phy[`reserved_0_TB19_DP_RXPCS_IDX_5 : `rbytordpad_DP_RXPCS_IDX_0]; assign ch0_in_chnl_ctrl_20 = ch0_rxpcsdprioin_phy[`rrx_pipe_enable_DP_RXPCS_IDX_0 : `rload_shreg_del_DP_RXPCS_IDX_0]; assign ch1_in_chnl_ctrl_20 = ch1_rxpcsdprioin_phy[`rrx_pipe_enable_DP_RXPCS_IDX_0 : `rload_shreg_del_DP_RXPCS_IDX_0]; assign ch2_in_chnl_ctrl_20 = ch2_rxpcsdprioin_phy[`rrx_pipe_enable_DP_RXPCS_IDX_0 : `rload_shreg_del_DP_RXPCS_IDX_0]; assign ch3_in_chnl_ctrl_20 = ch3_rxpcsdprioin_phy[`rrx_pipe_enable_DP_RXPCS_IDX_0 : `rload_shreg_del_DP_RXPCS_IDX_0]; assign ch0_in_chnl_ctrl_21 = ch0_rxpcsdprioin_phy[`rpma_done_count_15_DP_RXPCS_IDX_0 : `rpma_done_count_0_DP_RXPCS_IDX_0]; assign ch1_in_chnl_ctrl_21 = ch1_rxpcsdprioin_phy[`rpma_done_count_15_DP_RXPCS_IDX_0 : `rpma_done_count_0_DP_RXPCS_IDX_0]; assign ch2_in_chnl_ctrl_21 = ch2_rxpcsdprioin_phy[`rpma_done_count_15_DP_RXPCS_IDX_0 : `rpma_done_count_0_DP_RXPCS_IDX_0]; assign ch3_in_chnl_ctrl_21 = ch3_rxpcsdprioin_phy[`rpma_done_count_15_DP_RXPCS_IDX_0 : `rpma_done_count_0_DP_RXPCS_IDX_0]; assign ch0_in_chnl_ctrl_22 = ch0_rxpcsdprioin_phy[`rerr_flags_sel_DP_RXPCS_IDX_0 : `rbytordpat_10_DP_RXPCS_IDX_0]; assign ch1_in_chnl_ctrl_22 = ch1_rxpcsdprioin_phy[`rerr_flags_sel_DP_RXPCS_IDX_0 : `rbytordpat_10_DP_RXPCS_IDX_0]; assign ch2_in_chnl_ctrl_22 = ch2_rxpcsdprioin_phy[`rerr_flags_sel_DP_RXPCS_IDX_0 : `rbytordpat_10_DP_RXPCS_IDX_0]; assign ch3_in_chnl_ctrl_22 = ch3_rxpcsdprioin_phy[`rerr_flags_sel_DP_RXPCS_IDX_0 : `rbytordpat_10_DP_RXPCS_IDX_0]; assign ch0_in_chnl_ctrl_23 = ch0_rxpcsdprioin_phy[`reserved_0_TB23_DP_RXPCS_IDX_7 : `rwait_count_DP_RXPCS_IDX_0]; assign ch1_in_chnl_ctrl_23 = ch1_rxpcsdprioin_phy[`reserved_0_TB23_DP_RXPCS_IDX_7 : `rwait_count_DP_RXPCS_IDX_0]; assign ch2_in_chnl_ctrl_23 = ch2_rxpcsdprioin_phy[`reserved_0_TB23_DP_RXPCS_IDX_7 : `rwait_count_DP_RXPCS_IDX_0]; assign ch3_in_chnl_ctrl_23 = ch3_rxpcsdprioin_phy[`reserved_0_TB23_DP_RXPCS_IDX_7 : `rwait_count_DP_RXPCS_IDX_0]; assign ch0_in_chnl_ctrl_24 = ch0_rxpcsdprioin_phy[`rwait_for_phfifo_cnt_DP_RXPCS_IDX_5 : `rfts_count_DP_RXPCS_IDX_0]; assign ch1_in_chnl_ctrl_24 = ch1_rxpcsdprioin_phy[`rwait_for_phfifo_cnt_DP_RXPCS_IDX_5 : `rfts_count_DP_RXPCS_IDX_0]; assign ch2_in_chnl_ctrl_24 = ch2_rxpcsdprioin_phy[`rwait_for_phfifo_cnt_DP_RXPCS_IDX_5 : `rfts_count_DP_RXPCS_IDX_0]; assign ch3_in_chnl_ctrl_24 = ch3_rxpcsdprioin_phy[`rwait_for_phfifo_cnt_DP_RXPCS_IDX_5 : `rfts_count_DP_RXPCS_IDX_0]; assign ch0_in_chnl_ctrl_25 = ch0_rxpcsdprioin_phy[`reserved_0_TB25_DP_RXPCS_IDX_4 : `rppm_meas_delay_DP_RXPCS_IDX_0]; assign ch1_in_chnl_ctrl_25 = ch1_rxpcsdprioin_phy[`reserved_0_TB25_DP_RXPCS_IDX_4 : `rppm_meas_delay_DP_RXPCS_IDX_0]; assign ch2_in_chnl_ctrl_25 = ch2_rxpcsdprioin_phy[`reserved_0_TB25_DP_RXPCS_IDX_4 : `rppm_meas_delay_DP_RXPCS_IDX_0]; assign ch3_in_chnl_ctrl_25 = ch3_rxpcsdprioin_phy[`reserved_0_TB25_DP_RXPCS_IDX_4 : `rppm_meas_delay_DP_RXPCS_IDX_0]; assign ch0_in_chnl_ctrl_26 = ch0_rxpcsdprioin_phy[`rphfifo_regmode_rx_DP_RXPCS_IDX_0 : `rauto_pc_en_cnt_DP_RXPCS_IDX_0]; assign ch1_in_chnl_ctrl_26 = ch1_rxpcsdprioin_phy[`rphfifo_regmode_rx_DP_RXPCS_IDX_0 : `rauto_pc_en_cnt_DP_RXPCS_IDX_0]; assign ch2_in_chnl_ctrl_26 = ch2_rxpcsdprioin_phy[`rphfifo_regmode_rx_DP_RXPCS_IDX_0 : `rauto_pc_en_cnt_DP_RXPCS_IDX_0]; assign ch3_in_chnl_ctrl_26 = ch3_rxpcsdprioin_phy[`rphfifo_regmode_rx_DP_RXPCS_IDX_0 : `rauto_pc_en_cnt_DP_RXPCS_IDX_0]; assign ch0_in_chnl_ctrl_27 = ch0_rxpcsdprioin_phy[`reserved_0_TB27_DP_RXPCS_IDX_3 : `rmask_count_DP_RXPCS_IDX_0]; assign ch1_in_chnl_ctrl_27 = ch1_rxpcsdprioin_phy[`reserved_0_TB27_DP_RXPCS_IDX_3 : `rmask_count_DP_RXPCS_IDX_0]; assign ch2_in_chnl_ctrl_27 = ch2_rxpcsdprioin_phy[`reserved_0_TB27_DP_RXPCS_IDX_3 : `rmask_count_DP_RXPCS_IDX_0]; assign ch3_in_chnl_ctrl_27 = ch3_rxpcsdprioin_phy[`reserved_0_TB27_DP_RXPCS_IDX_3 : `rmask_count_DP_RXPCS_IDX_0]; // TXPMA assign ch0_in_chnl_ctrl_28 = ch0_txpmadprioin_phy[`rvod_sel_non_pcie_DP_TXPMA_IDX_2 : `rpowdnt_DP_TXPMA_IDX_0]; assign ch1_in_chnl_ctrl_28 = ch1_txpmadprioin_phy[`rvod_sel_non_pcie_DP_TXPMA_IDX_2 : `rpowdnt_DP_TXPMA_IDX_0]; assign ch2_in_chnl_ctrl_28 = ch2_txpmadprioin_phy[`rvod_sel_non_pcie_DP_TXPMA_IDX_2 : `rpowdnt_DP_TXPMA_IDX_0]; assign ch3_in_chnl_ctrl_28 = ch3_txpmadprioin_phy[`rvod_sel_non_pcie_DP_TXPMA_IDX_2 : `rpowdnt_DP_TXPMA_IDX_0]; assign ch4_in_chnl_ctrl_28 = ch4_txpmadprioin_phy[`rvod_sel_non_pcie_DP_TXPMA_IDX_2 : `rpowdnt_DP_TXPMA_IDX_0]; assign ch5_in_chnl_ctrl_28 = ch5_txpmadprioin_phy[`rvod_sel_non_pcie_DP_TXPMA_IDX_2 : `rpowdnt_DP_TXPMA_IDX_0]; assign ch0_in_chnl_ctrl_29 = ch0_txpmadprioin_phy[`rpre_em_1t_no_pcie_DP_TXPMA_IDX_4 : `reserved_0_TB29_DP_TXPMA_IDX_0]; assign ch1_in_chnl_ctrl_29 = ch1_txpmadprioin_phy[`rpre_em_1t_no_pcie_DP_TXPMA_IDX_4 : `reserved_0_TB29_DP_TXPMA_IDX_0]; assign ch2_in_chnl_ctrl_29 = ch2_txpmadprioin_phy[`rpre_em_1t_no_pcie_DP_TXPMA_IDX_4 : `reserved_0_TB29_DP_TXPMA_IDX_0]; assign ch3_in_chnl_ctrl_29 = ch3_txpmadprioin_phy[`rpre_em_1t_no_pcie_DP_TXPMA_IDX_4 : `reserved_0_TB29_DP_TXPMA_IDX_0]; assign ch4_in_chnl_ctrl_29 = ch4_txpmadprioin_phy[`rpre_em_1t_no_pcie_DP_TXPMA_IDX_4 : `reserved_0_TB29_DP_TXPMA_IDX_0]; assign ch5_in_chnl_ctrl_29 = ch5_txpmadprioin_phy[`rpre_em_1t_no_pcie_DP_TXPMA_IDX_4 : `reserved_0_TB29_DP_TXPMA_IDX_0]; assign ch0_in_chnl_ctrl_30 = ch0_txpmadprioin_phy[`reserved_0_TB30_DP_TXPMA_IDX_2 : `rpre_em_pt_DP_TXPMA_IDX_0]; assign ch1_in_chnl_ctrl_30 = ch1_txpmadprioin_phy[`reserved_0_TB30_DP_TXPMA_IDX_2 : `rpre_em_pt_DP_TXPMA_IDX_0]; assign ch2_in_chnl_ctrl_30 = ch2_txpmadprioin_phy[`reserved_0_TB30_DP_TXPMA_IDX_2 : `rpre_em_pt_DP_TXPMA_IDX_0]; assign ch3_in_chnl_ctrl_30 = ch3_txpmadprioin_phy[`reserved_0_TB30_DP_TXPMA_IDX_2 : `rpre_em_pt_DP_TXPMA_IDX_0]; assign ch4_in_chnl_ctrl_30 = ch4_txpmadprioin_phy[`reserved_0_TB30_DP_TXPMA_IDX_2 : `rpre_em_pt_DP_TXPMA_IDX_0]; assign ch5_in_chnl_ctrl_30 = ch5_txpmadprioin_phy[`reserved_0_TB30_DP_TXPMA_IDX_2 : `rpre_em_pt_DP_TXPMA_IDX_0]; assign ch0_in_chnl_ctrl_31 = ch0_txpmadprioin_phy[`rtx_term_sel_DP_TXPMA_IDX_2 : `rlowv_DP_TXPMA_IDX_0]; assign ch1_in_chnl_ctrl_31 = ch1_txpmadprioin_phy[`rtx_term_sel_DP_TXPMA_IDX_2 : `rlowv_DP_TXPMA_IDX_0]; assign ch2_in_chnl_ctrl_31 = ch2_txpmadprioin_phy[`rtx_term_sel_DP_TXPMA_IDX_2 : `rlowv_DP_TXPMA_IDX_0]; assign ch3_in_chnl_ctrl_31 = ch3_txpmadprioin_phy[`rtx_term_sel_DP_TXPMA_IDX_2 : `rlowv_DP_TXPMA_IDX_0]; assign ch4_in_chnl_ctrl_31 = ch4_txpmadprioin_phy[`rtx_term_sel_DP_TXPMA_IDX_2 : `rlowv_DP_TXPMA_IDX_0]; assign ch5_in_chnl_ctrl_31 = ch5_txpmadprioin_phy[`rtx_term_sel_DP_TXPMA_IDX_2 : `rlowv_DP_TXPMA_IDX_0]; assign ch0_in_chnl_ctrl_32 = ch0_txpmadprioin_phy[`r_dft_sel_DP_TXPMA_IDX_2 : `reserved_1_TB32_DP_TXPMA_IDX_0]; assign ch1_in_chnl_ctrl_32 = ch1_txpmadprioin_phy[`r_dft_sel_DP_TXPMA_IDX_2 : `reserved_1_TB32_DP_TXPMA_IDX_0]; assign ch2_in_chnl_ctrl_32 = ch2_txpmadprioin_phy[`r_dft_sel_DP_TXPMA_IDX_2 : `reserved_1_TB32_DP_TXPMA_IDX_0]; assign ch3_in_chnl_ctrl_32 = ch3_txpmadprioin_phy[`r_dft_sel_DP_TXPMA_IDX_2 : `reserved_1_TB32_DP_TXPMA_IDX_0]; assign ch4_in_chnl_ctrl_32 = ch4_txpmadprioin_phy[`r_dft_sel_DP_TXPMA_IDX_2 : `reserved_1_TB32_DP_TXPMA_IDX_0]; assign ch5_in_chnl_ctrl_32 = ch5_txpmadprioin_phy[`r_dft_sel_DP_TXPMA_IDX_2 : `reserved_1_TB32_DP_TXPMA_IDX_0]; // Done in the manual section because of split between tx_pma and clock_divider //assign ch0_in_chnl_ctrl_33 = ch0_txpmadprioin_phy[`rcgb_x_en_DP_TXPMA_IDX_1 : `reserved_0_TB33_DP_TXPMA_IDX_0]; //assign ch1_in_chnl_ctrl_33 = ch1_txpmadprioin_phy[`rcgb_x_en_DP_TXPMA_IDX_1 : `reserved_0_TB33_DP_TXPMA_IDX_0]; //assign ch2_in_chnl_ctrl_33 = ch2_txpmadprioin_phy[`rcgb_x_en_DP_TXPMA_IDX_1 : `reserved_0_TB33_DP_TXPMA_IDX_0]; //assign ch3_in_chnl_ctrl_33 = ch3_txpmadprioin_phy[`rcgb_x_en_DP_TXPMA_IDX_1 : `reserved_0_TB33_DP_TXPMA_IDX_0]; //assign ch4_in_chnl_ctrl_33 = ch4_txpmadprioin_phy[`rcgb_x_en_DP_TXPMA_IDX_1 : `reserved_0_TB33_DP_TXPMA_IDX_0]; //assign ch5_in_chnl_ctrl_33 = ch5_txpmadprioin_phy[`rcgb_x_en_DP_TXPMA_IDX_1 : `reserved_0_TB33_DP_TXPMA_IDX_0]; // Done in manual section because of logical PLL indices //assign ch0_in_chnl_ctrl_34 = ch0_txpmadprioin_phy[`riqclk_sel_DP_TXPMA_IDX_1 : `reserved_1_TB34_DP_TXPMA_IDX_0]; //assign ch1_in_chnl_ctrl_34 = ch1_txpmadprioin_phy[`riqclk_sel_DP_TXPMA_IDX_1 : `reserved_1_TB34_DP_TXPMA_IDX_0]; //assign ch2_in_chnl_ctrl_34 = ch2_txpmadprioin_phy[`riqclk_sel_DP_TXPMA_IDX_1 : `reserved_1_TB34_DP_TXPMA_IDX_0]; //assign ch3_in_chnl_ctrl_34 = ch3_txpmadprioin_phy[`riqclk_sel_DP_TXPMA_IDX_1 : `reserved_1_TB34_DP_TXPMA_IDX_0]; //assign ch4_in_chnl_ctrl_34 = ch4_txpmadprioin_phy[`riqclk_sel_DP_TXPMA_IDX_1 : `reserved_1_TB34_DP_TXPMA_IDX_0]; //assign ch5_in_chnl_ctrl_34 = ch5_txpmadprioin_phy[`riqclk_sel_DP_TXPMA_IDX_1 : `reserved_1_TB34_DP_TXPMA_IDX_0]; assign ch0_in_chnl_ctrl_35 = ch0_txpmadprioin_phy[`rpma_reserved_0_TB35_DP_TXPMA_IDX_15 : `rpma_reserved_0_TB35_DP_TXPMA_IDX_0]; assign ch1_in_chnl_ctrl_35 = ch1_txpmadprioin_phy[`rpma_reserved_0_TB35_DP_TXPMA_IDX_15 : `rpma_reserved_0_TB35_DP_TXPMA_IDX_0]; assign ch2_in_chnl_ctrl_35 = ch2_txpmadprioin_phy[`rpma_reserved_0_TB35_DP_TXPMA_IDX_15 : `rpma_reserved_0_TB35_DP_TXPMA_IDX_0]; assign ch3_in_chnl_ctrl_35 = ch3_txpmadprioin_phy[`rpma_reserved_0_TB35_DP_TXPMA_IDX_15 : `rpma_reserved_0_TB35_DP_TXPMA_IDX_0]; assign ch4_in_chnl_ctrl_35 = ch4_txpmadprioin_phy[`rpma_reserved_0_TB35_DP_TXPMA_IDX_15 : `rpma_reserved_0_TB35_DP_TXPMA_IDX_0]; assign ch5_in_chnl_ctrl_35 = ch5_txpmadprioin_phy[`rpma_reserved_0_TB35_DP_TXPMA_IDX_15 : `rpma_reserved_0_TB35_DP_TXPMA_IDX_0]; assign ch0_in_chnl_ctrl_36 = ch0_rxpmadprioin_phy[`rrx_lst_DP_RXPMA_IDX_4 : `rrx_term_sel_DP_RXPMA_IDX_0]; assign ch1_in_chnl_ctrl_36 = ch1_rxpmadprioin_phy[`rrx_lst_DP_RXPMA_IDX_4 : `rrx_term_sel_DP_RXPMA_IDX_0]; assign ch2_in_chnl_ctrl_36 = ch2_rxpmadprioin_phy[`rrx_lst_DP_RXPMA_IDX_4 : `rrx_term_sel_DP_RXPMA_IDX_0]; assign ch3_in_chnl_ctrl_36 = ch3_rxpmadprioin_phy[`rrx_lst_DP_RXPMA_IDX_4 : `rrx_term_sel_DP_RXPMA_IDX_0]; assign ch4_in_chnl_ctrl_36 = ch4_rxpmadprioin_phy[`rrx_lst_DP_RXPMA_IDX_4 : `rrx_term_sel_DP_RXPMA_IDX_0]; assign ch5_in_chnl_ctrl_36 = ch5_rxpmadprioin_phy[`rrx_lst_DP_RXPMA_IDX_4 : `rrx_term_sel_DP_RXPMA_IDX_0]; assign ch0_in_chnl_ctrl_37 = ch0_rxpmadprioin_phy[`rrx_sdlv_DP_RXPMA_IDX_3 : `rrxurstpma_DP_RXPMA_IDX_0]; assign ch1_in_chnl_ctrl_37 = ch1_rxpmadprioin_phy[`rrx_sdlv_DP_RXPMA_IDX_3 : `rrxurstpma_DP_RXPMA_IDX_0]; assign ch2_in_chnl_ctrl_37 = ch2_rxpmadprioin_phy[`rrx_sdlv_DP_RXPMA_IDX_3 : `rrxurstpma_DP_RXPMA_IDX_0]; assign ch3_in_chnl_ctrl_37 = ch3_rxpmadprioin_phy[`rrx_sdlv_DP_RXPMA_IDX_3 : `rrxurstpma_DP_RXPMA_IDX_0]; assign ch4_in_chnl_ctrl_37 = ch4_rxpmadprioin_phy[`rrx_sdlv_DP_RXPMA_IDX_3 : `rrxurstpma_DP_RXPMA_IDX_0]; assign ch5_in_chnl_ctrl_37 = ch5_rxpmadprioin_phy[`rrx_sdlv_DP_RXPMA_IDX_3 : `rrxurstpma_DP_RXPMA_IDX_0]; assign ch0_in_chnl_ctrl_38 = ch0_rxpmadprioin_phy[`rrx_sd_on_DP_RXPMA_IDX_3 : `reserved_0_TB38_DP_RXPMA_IDX_0]; assign ch1_in_chnl_ctrl_38 = ch1_rxpmadprioin_phy[`rrx_sd_on_DP_RXPMA_IDX_3 : `reserved_0_TB38_DP_RXPMA_IDX_0]; assign ch2_in_chnl_ctrl_38 = ch2_rxpmadprioin_phy[`rrx_sd_on_DP_RXPMA_IDX_3 : `reserved_0_TB38_DP_RXPMA_IDX_0]; assign ch3_in_chnl_ctrl_38 = ch3_rxpmadprioin_phy[`rrx_sd_on_DP_RXPMA_IDX_3 : `reserved_0_TB38_DP_RXPMA_IDX_0]; assign ch4_in_chnl_ctrl_38 = ch4_rxpmadprioin_phy[`rrx_sd_on_DP_RXPMA_IDX_3 : `reserved_0_TB38_DP_RXPMA_IDX_0]; assign ch5_in_chnl_ctrl_38 = ch5_rxpmadprioin_phy[`rrx_sd_on_DP_RXPMA_IDX_3 : `reserved_0_TB38_DP_RXPMA_IDX_0]; // PLL assign ch0_in_chnl_ctrl_39 = ch0_rxplldprioin_phy[`rcru_div2_DP_PLL_IDX_0 : `rcru_pdbwctrl_DP_PLL_IDX_0]; assign ch1_in_chnl_ctrl_39 = ch1_rxplldprioin_phy[`rcru_div2_DP_PLL_IDX_0 : `rcru_pdbwctrl_DP_PLL_IDX_0]; assign ch2_in_chnl_ctrl_39 = ch2_rxplldprioin_phy[`rcru_div2_DP_PLL_IDX_0 : `rcru_pdbwctrl_DP_PLL_IDX_0]; assign ch3_in_chnl_ctrl_39 = ch3_rxplldprioin_phy[`rcru_div2_DP_PLL_IDX_0 : `rcru_pdbwctrl_DP_PLL_IDX_0]; assign ch4_in_chnl_ctrl_39 = ch4_rxtxplldprioin_phy[`rcru_div2_DP_PLL_IDX_0 : `rcru_pdbwctrl_DP_PLL_IDX_0]; assign ch5_in_chnl_ctrl_39 = ch5_rxtxplldprioin_phy[`rcru_div2_DP_PLL_IDX_0 : `rcru_pdbwctrl_DP_PLL_IDX_0]; // PLL - moved to Manual section as this CRAM sends to TX_PMA //assign ch0_in_chnl_ctrl_40 = ch0_rxplldprioin_phy[`rcru_rlbk_DP_PLL_IDX_0 : `reserved_0_TB40_DP_PLL_IDX_0]; //assign ch1_in_chnl_ctrl_40 = ch1_rxplldprioin_phy[`rcru_rlbk_DP_PLL_IDX_0 : `reserved_0_TB40_DP_PLL_IDX_0]; //assign ch2_in_chnl_ctrl_40 = ch2_rxplldprioin_phy[`rcru_rlbk_DP_PLL_IDX_0 : `reserved_0_TB40_DP_PLL_IDX_0]; //assign ch3_in_chnl_ctrl_40 = ch3_rxplldprioin_phy[`rcru_rlbk_DP_PLL_IDX_0 : `reserved_0_TB40_DP_PLL_IDX_0]; //assign ch4_in_chnl_ctrl_40 = ch4_rxtxplldprioin_phy[`rcru_rlbk_DP_PLL_IDX_0 : `reserved_0_TB40_DP_PLL_IDX_0]; //assign ch5_in_chnl_ctrl_40 = ch5_rxtxplldprioin_phy[`rcru_rlbk_DP_PLL_IDX_0 : `reserved_0_TB40_DP_PLL_IDX_0]; // PLL assign ch0_in_chnl_ctrl_41 = ch0_rxplldprioin_phy[`rcp_mode_DP_PLL_IDX_0 : `rcru_rgla_isel_DP_PLL_IDX_0]; assign ch1_in_chnl_ctrl_41 = ch1_rxplldprioin_phy[`rcp_mode_DP_PLL_IDX_0 : `rcru_rgla_isel_DP_PLL_IDX_0]; assign ch2_in_chnl_ctrl_41 = ch2_rxplldprioin_phy[`rcp_mode_DP_PLL_IDX_0 : `rcru_rgla_isel_DP_PLL_IDX_0]; assign ch3_in_chnl_ctrl_41 = ch3_rxplldprioin_phy[`rcp_mode_DP_PLL_IDX_0 : `rcru_rgla_isel_DP_PLL_IDX_0]; assign ch4_in_chnl_ctrl_41 = ch4_rxtxplldprioin_phy[`rcp_mode_DP_PLL_IDX_0 : `rcru_rgla_isel_DP_PLL_IDX_0]; assign ch5_in_chnl_ctrl_41 = ch5_rxtxplldprioin_phy[`rcp_mode_DP_PLL_IDX_0 : `rcru_rgla_isel_DP_PLL_IDX_0]; // PLL assign ch0_in_chnl_ctrl_42 = ch0_rxplldprioin_phy[`rcru_pdof_0i_DP_PLL_IDX_3 : `rcru_pdof_270i_DP_PLL_IDX_0]; assign ch1_in_chnl_ctrl_42 = ch1_rxplldprioin_phy[`rcru_pdof_0i_DP_PLL_IDX_3 : `rcru_pdof_270i_DP_PLL_IDX_0]; assign ch2_in_chnl_ctrl_42 = ch2_rxplldprioin_phy[`rcru_pdof_0i_DP_PLL_IDX_3 : `rcru_pdof_270i_DP_PLL_IDX_0]; assign ch3_in_chnl_ctrl_42 = ch3_rxplldprioin_phy[`rcru_pdof_0i_DP_PLL_IDX_3 : `rcru_pdof_270i_DP_PLL_IDX_0]; assign ch4_in_chnl_ctrl_42 = ch4_rxtxplldprioin_phy[`rcru_pdof_0i_DP_PLL_IDX_3 : `rcru_pdof_270i_DP_PLL_IDX_0]; assign ch5_in_chnl_ctrl_42 = ch5_rxtxplldprioin_phy[`rcru_pdof_0i_DP_PLL_IDX_3 : `rcru_pdof_270i_DP_PLL_IDX_0]; // reserved assign ch0_in_chnl_ctrl_43 = ch0_rxpmadprioin_phy[`reserved_0_TB43_DP_RXPMA_IDX_7 : `reye_monitor_DP_RXPMA_IDX_0]; assign ch1_in_chnl_ctrl_43 = ch1_rxpmadprioin_phy[`reserved_0_TB43_DP_RXPMA_IDX_7 : `reye_monitor_DP_RXPMA_IDX_0]; assign ch2_in_chnl_ctrl_43 = ch2_rxpmadprioin_phy[`reserved_0_TB43_DP_RXPMA_IDX_7 : `reye_monitor_DP_RXPMA_IDX_0]; assign ch3_in_chnl_ctrl_43 = ch3_rxpmadprioin_phy[`reserved_0_TB43_DP_RXPMA_IDX_7 : `reye_monitor_DP_RXPMA_IDX_0]; assign ch4_in_chnl_ctrl_43 = ch4_rxpmadprioin_phy[`reserved_0_TB43_DP_RXPMA_IDX_7 : `reye_monitor_DP_RXPMA_IDX_0]; assign ch5_in_chnl_ctrl_43 = ch5_rxpmadprioin_phy[`reserved_0_TB43_DP_RXPMA_IDX_7 : `reye_monitor_DP_RXPMA_IDX_0]; assign ch0_in_chnl_ctrl_44 = ch0_rxpmadprioin_phy[`rpma_reserved_0_TB44_DP_RXPMA_IDX_15 : `rpma_reserved_0_TB44_DP_RXPMA_IDX_0]; assign ch1_in_chnl_ctrl_44 = ch1_rxpmadprioin_phy[`rpma_reserved_0_TB44_DP_RXPMA_IDX_15 : `rpma_reserved_0_TB44_DP_RXPMA_IDX_0]; assign ch2_in_chnl_ctrl_44 = ch2_rxpmadprioin_phy[`rpma_reserved_0_TB44_DP_RXPMA_IDX_15 : `rpma_reserved_0_TB44_DP_RXPMA_IDX_0]; assign ch3_in_chnl_ctrl_44 = ch3_rxpmadprioin_phy[`rpma_reserved_0_TB44_DP_RXPMA_IDX_15 : `rpma_reserved_0_TB44_DP_RXPMA_IDX_0]; assign ch4_in_chnl_ctrl_44 = ch4_rxpmadprioin_phy[`rpma_reserved_0_TB44_DP_RXPMA_IDX_15 : `rpma_reserved_0_TB44_DP_RXPMA_IDX_0]; assign ch5_in_chnl_ctrl_44 = ch5_rxpmadprioin_phy[`rpma_reserved_0_TB44_DP_RXPMA_IDX_15 : `rpma_reserved_0_TB44_DP_RXPMA_IDX_0]; assign ch0_in_chnl_ctrl_45 = ch0_rxpmadprioin_phy[`rpma_doublewidth_rx_DP_RXPMA_IDX_0 : `rppm_cnt_reset_DP_RXPMA_IDX_0]; assign ch1_in_chnl_ctrl_45 = ch1_rxpmadprioin_phy[`rpma_doublewidth_rx_DP_RXPMA_IDX_0 : `rppm_cnt_reset_DP_RXPMA_IDX_0]; assign ch2_in_chnl_ctrl_45 = ch2_rxpmadprioin_phy[`rpma_doublewidth_rx_DP_RXPMA_IDX_0 : `rppm_cnt_reset_DP_RXPMA_IDX_0]; assign ch3_in_chnl_ctrl_45 = ch3_rxpmadprioin_phy[`rpma_doublewidth_rx_DP_RXPMA_IDX_0 : `rppm_cnt_reset_DP_RXPMA_IDX_0]; assign ch4_in_chnl_ctrl_45 = ch4_rxpmadprioin_phy[`rpma_doublewidth_rx_DP_RXPMA_IDX_0 : `rppm_cnt_reset_DP_RXPMA_IDX_0]; assign ch5_in_chnl_ctrl_45 = ch5_rxpmadprioin_phy[`rpma_doublewidth_rx_DP_RXPMA_IDX_0 : `rppm_cnt_reset_DP_RXPMA_IDX_0]; assign ch0_in_chnl_ctrl_46 = ch0_rxpmadprioin_phy[`r_dfe_1t_DP_RXPMA_IDX_2 : `reserved_0_TB46_DP_RXPMA_IDX_0]; assign ch1_in_chnl_ctrl_46 = ch1_rxpmadprioin_phy[`r_dfe_1t_DP_RXPMA_IDX_2 : `reserved_0_TB46_DP_RXPMA_IDX_0]; assign ch2_in_chnl_ctrl_46 = ch2_rxpmadprioin_phy[`r_dfe_1t_DP_RXPMA_IDX_2 : `reserved_0_TB46_DP_RXPMA_IDX_0]; assign ch3_in_chnl_ctrl_46 = ch3_rxpmadprioin_phy[`r_dfe_1t_DP_RXPMA_IDX_2 : `reserved_0_TB46_DP_RXPMA_IDX_0]; assign ch4_in_chnl_ctrl_46 = ch4_rxpmadprioin_phy[`r_dfe_1t_DP_RXPMA_IDX_2 : `reserved_0_TB46_DP_RXPMA_IDX_0]; assign ch5_in_chnl_ctrl_46 = ch5_rxpmadprioin_phy[`r_dfe_1t_DP_RXPMA_IDX_2 : `reserved_0_TB46_DP_RXPMA_IDX_0]; assign ch0_in_chnl_ctrl_47 = ch0_rxpmadprioin_phy[`reserved_0_TB47_DP_RXPMA_IDX_0 : `reqv_set_DP_RXPMA_IDX_0]; assign ch1_in_chnl_ctrl_47 = ch1_rxpmadprioin_phy[`reserved_0_TB47_DP_RXPMA_IDX_0 : `reqv_set_DP_RXPMA_IDX_0]; assign ch2_in_chnl_ctrl_47 = ch2_rxpmadprioin_phy[`reserved_0_TB47_DP_RXPMA_IDX_0 : `reqv_set_DP_RXPMA_IDX_0]; assign ch3_in_chnl_ctrl_47 = ch3_rxpmadprioin_phy[`reserved_0_TB47_DP_RXPMA_IDX_0 : `reqv_set_DP_RXPMA_IDX_0]; assign ch4_in_chnl_ctrl_47 = ch4_rxpmadprioin_phy[`reserved_0_TB47_DP_RXPMA_IDX_0 : `reqv_set_DP_RXPMA_IDX_0]; assign ch5_in_chnl_ctrl_47 = ch5_rxpmadprioin_phy[`reserved_0_TB47_DP_RXPMA_IDX_0 : `reqv_set_DP_RXPMA_IDX_0]; assign ch0_in_chnl_ctrl_48 = ch0_rxpmadprioin_phy[`rlock_lf_ovd_DP_RXPMA_IDX_0 : `rdc_freq_DP_RXPMA_IDX_0]; assign ch1_in_chnl_ctrl_48 = ch1_rxpmadprioin_phy[`rlock_lf_ovd_DP_RXPMA_IDX_0 : `rdc_freq_DP_RXPMA_IDX_0]; assign ch2_in_chnl_ctrl_48 = ch2_rxpmadprioin_phy[`rlock_lf_ovd_DP_RXPMA_IDX_0 : `rdc_freq_DP_RXPMA_IDX_0]; assign ch3_in_chnl_ctrl_48 = ch3_rxpmadprioin_phy[`rlock_lf_ovd_DP_RXPMA_IDX_0 : `rdc_freq_DP_RXPMA_IDX_0]; //assign ch4_in_chnl_ctrl_48 = ch4_rxpmadprioin_phy[`rlock_lf_ovd_DP_RXPMA_IDX_0 : `rdc_freq_DP_RXPMA_IDX_0]; Not exist on CMU //assign ch5_in_chnl_ctrl_48 = ch5_rxpmadprioin_phy[`rlock_lf_ovd_DP_RXPMA_IDX_0 : `rdc_freq_DP_RXPMA_IDX_0]; assign ch0_in_chnl_ctrl_49 = ch0_rxpmadprioin_phy[`rhyst_hf_DP_RXPMA_IDX_2 : `rrgen_vod_DP_RXPMA_IDX_0]; assign ch1_in_chnl_ctrl_49 = ch1_rxpmadprioin_phy[`rhyst_hf_DP_RXPMA_IDX_2 : `rrgen_vod_DP_RXPMA_IDX_0]; assign ch2_in_chnl_ctrl_49 = ch2_rxpmadprioin_phy[`rhyst_hf_DP_RXPMA_IDX_2 : `rrgen_vod_DP_RXPMA_IDX_0]; assign ch3_in_chnl_ctrl_49 = ch3_rxpmadprioin_phy[`rhyst_hf_DP_RXPMA_IDX_2 : `rrgen_vod_DP_RXPMA_IDX_0]; //assign ch4_in_chnl_ctrl_49 = ch4_rxpmadprioin_phy[`rhyst_hf_DP_RXPMA_IDX_2 : `rrgen_vod_DP_RXPMA_IDX_0]; //assign ch5_in_chnl_ctrl_49 = ch5_rxpmadprioin_phy[`rhyst_hf_DP_RXPMA_IDX_2 : `rrgen_vod_DP_RXPMA_IDX_0]; assign ch0_in_chnl_ctrl_50 = ch0_rxpmadprioin_phy[`rrgen_bw_DP_RXPMA_IDX_1 : `radce_pdb_DP_RXPMA_IDX_0]; assign ch1_in_chnl_ctrl_50 = ch1_rxpmadprioin_phy[`rrgen_bw_DP_RXPMA_IDX_1 : `radce_pdb_DP_RXPMA_IDX_0]; assign ch2_in_chnl_ctrl_50 = ch2_rxpmadprioin_phy[`rrgen_bw_DP_RXPMA_IDX_1 : `radce_pdb_DP_RXPMA_IDX_0]; assign ch3_in_chnl_ctrl_50 = ch3_rxpmadprioin_phy[`rrgen_bw_DP_RXPMA_IDX_1 : `radce_pdb_DP_RXPMA_IDX_0]; //assign ch4_in_chnl_ctrl_50 = ch4_rxpmadprioin_phy[`rrgen_bw_DP_RXPMA_IDX_1 : `radce_pdb_DP_RXPMA_IDX_0]; //assign ch5_in_chnl_ctrl_50 = ch5_rxpmadprioin_phy[`rrgen_bw_DP_RXPMA_IDX_1 : `radce_pdb_DP_RXPMA_IDX_0]; assign ch0_in_chnl_ctrl_51 = ch0_rxpmadprioin_phy[`reserved_0_TB51_DP_RXPMA_IDX_0 : `radce_hflck_DP_RXPMA_IDX_0]; assign ch1_in_chnl_ctrl_51 = ch1_rxpmadprioin_phy[`reserved_0_TB51_DP_RXPMA_IDX_0 : `radce_hflck_DP_RXPMA_IDX_0]; assign ch2_in_chnl_ctrl_51 = ch2_rxpmadprioin_phy[`reserved_0_TB51_DP_RXPMA_IDX_0 : `radce_hflck_DP_RXPMA_IDX_0]; assign ch3_in_chnl_ctrl_51 = ch3_rxpmadprioin_phy[`reserved_0_TB51_DP_RXPMA_IDX_0 : `radce_hflck_DP_RXPMA_IDX_0]; //assign ch4_in_chnl_ctrl_51 = ch4_rxpmadprioin_phy[`reserved_0_TB51_DP_RXPMA_IDX_0 : `radce_hflck_DP_RXPMA_IDX_0]; //assign ch5_in_chnl_ctrl_51 = ch5_rxpmadprioin_phy[`reserved_0_TB51_DP_RXPMA_IDX_0 : `radce_hflck_DP_RXPMA_IDX_0]; assign ch0_in_chnl_ctrl_52 = ch0_rxpmadprioin_phy[`reserved_0_TB52_DP_RXPMA_IDX_0 : `radce_lflck_DP_RXPMA_IDX_0]; assign ch1_in_chnl_ctrl_52 = ch1_rxpmadprioin_phy[`reserved_0_TB52_DP_RXPMA_IDX_0 : `radce_lflck_DP_RXPMA_IDX_0]; assign ch2_in_chnl_ctrl_52 = ch2_rxpmadprioin_phy[`reserved_0_TB52_DP_RXPMA_IDX_0 : `radce_lflck_DP_RXPMA_IDX_0]; assign ch3_in_chnl_ctrl_52 = ch3_rxpmadprioin_phy[`reserved_0_TB52_DP_RXPMA_IDX_0 : `radce_lflck_DP_RXPMA_IDX_0]; //assign ch4_in_chnl_ctrl_52 = ch4_rxpmadprioin_phy[`reserved_0_TB52_DP_RXPMA_IDX_0 : `radce_lflck_DP_RXPMA_IDX_0]; //assign ch5_in_chnl_ctrl_52 = ch5_rxpmadprioin_phy[`reserved_0_TB52_DP_RXPMA_IDX_0 : `radce_lflck_DP_RXPMA_IDX_0]; assign ch0_in_chnl_ctrl_53 = ch0_rxpmadprioin_phy[`reserved_0_TB53_DP_RXPMA_IDX_5 : `radce_digital_DP_RXPMA_IDX_0]; assign ch1_in_chnl_ctrl_53 = ch1_rxpmadprioin_phy[`reserved_0_TB53_DP_RXPMA_IDX_5 : `radce_digital_DP_RXPMA_IDX_0]; assign ch2_in_chnl_ctrl_53 = ch2_rxpmadprioin_phy[`reserved_0_TB53_DP_RXPMA_IDX_5 : `radce_digital_DP_RXPMA_IDX_0]; assign ch3_in_chnl_ctrl_53 = ch3_rxpmadprioin_phy[`reserved_0_TB53_DP_RXPMA_IDX_5 : `radce_digital_DP_RXPMA_IDX_0]; //assign ch4_in_chnl_ctrl_53 = ch4_rxpmadprioin_phy[`reserved_0_TB53_DP_RXPMA_IDX_5 : `radce_digital_DP_RXPMA_IDX_0]; //assign ch5_in_chnl_ctrl_53 = ch5_rxpmadprioin_phy[`reserved_0_TB53_DP_RXPMA_IDX_5 : `radce_digital_DP_RXPMA_IDX_0]; // -------- HW ordering -------------------------------------- //TXPCS assign ch0_csr_chnl_in[15:0] = ch0_in_chnl_ctrl_1; assign ch1_csr_chnl_in[15:0] = ch1_in_chnl_ctrl_1; assign ch2_csr_chnl_in[15:0] = ch2_in_chnl_ctrl_1; assign ch3_csr_chnl_in[15:0] = ch3_in_chnl_ctrl_1; assign ch0_csr_chnl_in[31:16] = ch0_in_chnl_ctrl_2; assign ch1_csr_chnl_in[31:16] = ch1_in_chnl_ctrl_2; assign ch2_csr_chnl_in[31:16] = ch2_in_chnl_ctrl_2; assign ch3_csr_chnl_in[31:16] = ch3_in_chnl_ctrl_2; assign ch0_csr_chnl_in[47:32] = ch0_in_chnl_ctrl_3; assign ch1_csr_chnl_in[47:32] = ch1_in_chnl_ctrl_3; assign ch2_csr_chnl_in[47:32] = ch2_in_chnl_ctrl_3; assign ch3_csr_chnl_in[47:32] = ch3_in_chnl_ctrl_3; assign ch0_csr_chnl_in[63:48] = ch0_in_chnl_ctrl_4; assign ch1_csr_chnl_in[63:48] = ch1_in_chnl_ctrl_4; assign ch2_csr_chnl_in[63:48] = ch2_in_chnl_ctrl_4; assign ch3_csr_chnl_in[63:48] = ch3_in_chnl_ctrl_4; assign ch0_csr_chnl_in[79:64] = ch0_in_chnl_ctrl_5; assign ch1_csr_chnl_in[79:64] = ch1_in_chnl_ctrl_5; assign ch2_csr_chnl_in[79:64] = ch2_in_chnl_ctrl_5; assign ch3_csr_chnl_in[79:64] = ch3_in_chnl_ctrl_5; assign ch0_csr_chnl_in[95:80] = ch0_in_chnl_ctrl_6; assign ch1_csr_chnl_in[95:80] = ch1_in_chnl_ctrl_6; assign ch2_csr_chnl_in[95:80] = ch2_in_chnl_ctrl_6; assign ch3_csr_chnl_in[95:80] = ch3_in_chnl_ctrl_6; assign ch0_csr_chnl_in[111:96] = ch0_in_chnl_ctrl_7; assign ch1_csr_chnl_in[111:96] = ch1_in_chnl_ctrl_7; assign ch2_csr_chnl_in[111:96] = ch2_in_chnl_ctrl_7; assign ch3_csr_chnl_in[111:96] = ch3_in_chnl_ctrl_7; assign ch0_csr_chnl_in[127:112] = ch0_in_chnl_ctrl_8; assign ch1_csr_chnl_in[127:112] = ch1_in_chnl_ctrl_8; assign ch2_csr_chnl_in[127:112] = ch2_in_chnl_ctrl_8; assign ch3_csr_chnl_in[127:112] = ch3_in_chnl_ctrl_8; assign ch0_csr_chnl_in[143:128] = ch0_in_chnl_ctrl_9; assign ch1_csr_chnl_in[143:128] = ch1_in_chnl_ctrl_9; assign ch2_csr_chnl_in[143:128] = ch2_in_chnl_ctrl_9; assign ch3_csr_chnl_in[143:128] = ch3_in_chnl_ctrl_9; assign ch0_csr_chnl_in[159:144] = ch0_in_chnl_ctrl_10; assign ch1_csr_chnl_in[159:144] = ch1_in_chnl_ctrl_10; assign ch2_csr_chnl_in[159:144] = ch2_in_chnl_ctrl_10; assign ch3_csr_chnl_in[159:144] = ch3_in_chnl_ctrl_10; assign ch0_csr_chnl_in[175:160] = ch0_in_chnl_ctrl_11; assign ch1_csr_chnl_in[175:160] = ch1_in_chnl_ctrl_11; assign ch2_csr_chnl_in[175:160] = ch2_in_chnl_ctrl_11; assign ch3_csr_chnl_in[175:160] = ch3_in_chnl_ctrl_11; assign ch0_csr_chnl_in[191:176] = ch0_in_chnl_ctrl_12; assign ch1_csr_chnl_in[191:176] = ch1_in_chnl_ctrl_12; assign ch2_csr_chnl_in[191:176] = ch2_in_chnl_ctrl_12; assign ch3_csr_chnl_in[191:176] = ch3_in_chnl_ctrl_12; assign ch0_csr_chnl_in[207:192] = ch0_in_chnl_ctrl_13; assign ch1_csr_chnl_in[207:192] = ch1_in_chnl_ctrl_13; assign ch2_csr_chnl_in[207:192] = ch2_in_chnl_ctrl_13; assign ch3_csr_chnl_in[207:192] = ch3_in_chnl_ctrl_13; assign ch0_csr_chnl_in[223:208] = ch0_in_chnl_ctrl_14; assign ch1_csr_chnl_in[223:208] = ch1_in_chnl_ctrl_14; assign ch2_csr_chnl_in[223:208] = ch2_in_chnl_ctrl_14; assign ch3_csr_chnl_in[223:208] = ch3_in_chnl_ctrl_14; assign ch0_csr_chnl_in[239:224] = ch0_in_chnl_ctrl_15; assign ch1_csr_chnl_in[239:224] = ch1_in_chnl_ctrl_15; assign ch2_csr_chnl_in[239:224] = ch2_in_chnl_ctrl_15; assign ch3_csr_chnl_in[239:224] = ch3_in_chnl_ctrl_15; assign ch0_csr_chnl_in[255:240] = ch0_in_chnl_ctrl_16; assign ch1_csr_chnl_in[255:240] = ch1_in_chnl_ctrl_16; assign ch2_csr_chnl_in[255:240] = ch2_in_chnl_ctrl_16; assign ch3_csr_chnl_in[255:240] = ch3_in_chnl_ctrl_16; assign ch0_csr_chnl_in[271:256] = ch0_in_chnl_ctrl_17; assign ch1_csr_chnl_in[271:256] = ch1_in_chnl_ctrl_17; assign ch2_csr_chnl_in[271:256] = ch2_in_chnl_ctrl_17; assign ch3_csr_chnl_in[271:256] = ch3_in_chnl_ctrl_17; assign ch0_csr_chnl_in[287:272] = ch0_in_chnl_ctrl_18; assign ch1_csr_chnl_in[287:272] = ch1_in_chnl_ctrl_18; assign ch2_csr_chnl_in[287:272] = ch2_in_chnl_ctrl_18; assign ch3_csr_chnl_in[287:272] = ch3_in_chnl_ctrl_18; assign ch0_csr_chnl_in[303:288] = ch0_in_chnl_ctrl_19; assign ch1_csr_chnl_in[303:288] = ch1_in_chnl_ctrl_19; assign ch2_csr_chnl_in[303:288] = ch2_in_chnl_ctrl_19; assign ch3_csr_chnl_in[303:288] = ch3_in_chnl_ctrl_19; assign ch0_csr_chnl_in[319:304] = ch0_in_chnl_ctrl_20; assign ch1_csr_chnl_in[319:304] = ch1_in_chnl_ctrl_20; assign ch2_csr_chnl_in[319:304] = ch2_in_chnl_ctrl_20; assign ch3_csr_chnl_in[319:304] = ch3_in_chnl_ctrl_20; assign ch0_csr_chnl_in[335:320] = ch0_in_chnl_ctrl_21; assign ch1_csr_chnl_in[335:320] = ch1_in_chnl_ctrl_21; assign ch2_csr_chnl_in[335:320] = ch2_in_chnl_ctrl_21; assign ch3_csr_chnl_in[335:320] = ch3_in_chnl_ctrl_21; assign ch0_csr_chnl_in[351:336] = ch0_in_chnl_ctrl_22; assign ch1_csr_chnl_in[351:336] = ch1_in_chnl_ctrl_22; assign ch2_csr_chnl_in[351:336] = ch2_in_chnl_ctrl_22; assign ch3_csr_chnl_in[351:336] = ch3_in_chnl_ctrl_22; assign ch0_csr_chnl_in[367:352] = ch0_in_chnl_ctrl_23; assign ch1_csr_chnl_in[367:352] = ch1_in_chnl_ctrl_23; assign ch2_csr_chnl_in[367:352] = ch2_in_chnl_ctrl_23; assign ch3_csr_chnl_in[367:352] = ch3_in_chnl_ctrl_23; assign ch0_csr_chnl_in[383:368] = ch0_in_chnl_ctrl_24; assign ch1_csr_chnl_in[383:368] = ch1_in_chnl_ctrl_24; assign ch2_csr_chnl_in[383:368] = ch2_in_chnl_ctrl_24; assign ch3_csr_chnl_in[383:368] = ch3_in_chnl_ctrl_24; assign ch0_csr_chnl_in[399:384] = ch0_in_chnl_ctrl_25; assign ch1_csr_chnl_in[399:384] = ch1_in_chnl_ctrl_25; assign ch2_csr_chnl_in[399:384] = ch2_in_chnl_ctrl_25; assign ch3_csr_chnl_in[399:384] = ch3_in_chnl_ctrl_25; assign ch0_csr_chnl_in[415:400] = ch0_in_chnl_ctrl_26; assign ch1_csr_chnl_in[415:400] = ch1_in_chnl_ctrl_26; assign ch2_csr_chnl_in[415:400] = ch2_in_chnl_ctrl_26; assign ch3_csr_chnl_in[415:400] = ch3_in_chnl_ctrl_26; assign ch0_csr_chnl_in[431:416] = ch0_in_chnl_ctrl_27; assign ch1_csr_chnl_in[431:416] = ch1_in_chnl_ctrl_27; assign ch2_csr_chnl_in[431:416] = ch2_in_chnl_ctrl_27; assign ch3_csr_chnl_in[431:416] = ch3_in_chnl_ctrl_27; // TXPMA assign ch0_csr_chnl_in[447:432] = ch0_in_chnl_ctrl_28; assign ch1_csr_chnl_in[447:432] = ch1_in_chnl_ctrl_28; assign ch2_csr_chnl_in[447:432] = ch2_in_chnl_ctrl_28; assign ch3_csr_chnl_in[447:432] = ch3_in_chnl_ctrl_28; //assign ch4_csr_chnl_in[447:432] = ch4_in_chnl_ctrl_28; HW is cmu0_csr_ //assign ch5_csr_chnl_in[447:432] = ch5_in_chnl_ctrl_28; CMU restarting from 1 - 20 assign ch0_csr_chnl_in[463:448] = ch0_in_chnl_ctrl_29; assign ch1_csr_chnl_in[463:448] = ch1_in_chnl_ctrl_29; assign ch2_csr_chnl_in[463:448] = ch2_in_chnl_ctrl_29; assign ch3_csr_chnl_in[463:448] = ch3_in_chnl_ctrl_29; //assign ch4_csr_chnl_in[463:448] = ch4_in_chnl_ctrl_29; //assign ch5_csr_chnl_in[463:448] = ch5_in_chnl_ctrl_29; assign ch0_csr_chnl_in[479:464] = ch0_in_chnl_ctrl_30; assign ch1_csr_chnl_in[479:464] = ch1_in_chnl_ctrl_30; assign ch2_csr_chnl_in[479:464] = ch2_in_chnl_ctrl_30; assign ch3_csr_chnl_in[479:464] = ch3_in_chnl_ctrl_30; //assign ch4_csr_chnl_in[479:464] = ch4_in_chnl_ctrl_30; //assign ch5_csr_chnl_in[479:464] = ch5_in_chnl_ctrl_30; assign ch0_csr_chnl_in[495:480] = ch0_in_chnl_ctrl_31; assign ch1_csr_chnl_in[495:480] = ch1_in_chnl_ctrl_31; assign ch2_csr_chnl_in[495:480] = ch2_in_chnl_ctrl_31; assign ch3_csr_chnl_in[495:480] = ch3_in_chnl_ctrl_31; //assign ch4_csr_chnl_in[495:480] = ch4_in_chnl_ctrl_31; //assign ch5_csr_chnl_in[495:480] = ch5_in_chnl_ctrl_31; assign ch0_csr_chnl_in[511:496] = ch0_in_chnl_ctrl_32; assign ch1_csr_chnl_in[511:496] = ch1_in_chnl_ctrl_32; assign ch2_csr_chnl_in[511:496] = ch2_in_chnl_ctrl_32; assign ch3_csr_chnl_in[511:496] = ch3_in_chnl_ctrl_32; //assign ch4_csr_chnl_in[511:496] = ch4_in_chnl_ctrl_32; //assign ch5_csr_chnl_in[511:496] = ch5_in_chnl_ctrl_32; assign ch0_csr_chnl_in[527:512] = ch0_in_chnl_ctrl_33; assign ch1_csr_chnl_in[527:512] = ch1_in_chnl_ctrl_33; assign ch2_csr_chnl_in[527:512] = ch2_in_chnl_ctrl_33; assign ch3_csr_chnl_in[527:512] = ch3_in_chnl_ctrl_33; //assign ch4_csr_chnl_in[527:512] = ch4_in_chnl_ctrl_33; //assign ch5_csr_chnl_in[527:512] = ch5_in_chnl_ctrl_33; assign ch0_csr_chnl_in[543:528] = ch0_in_chnl_ctrl_34; assign ch1_csr_chnl_in[543:528] = ch1_in_chnl_ctrl_34; assign ch2_csr_chnl_in[543:528] = ch2_in_chnl_ctrl_34; assign ch3_csr_chnl_in[543:528] = ch3_in_chnl_ctrl_34; //assign ch4_csr_chnl_in[543:528] = ch4_in_chnl_ctrl_34; //assign ch5_csr_chnl_in[543:528] = ch5_in_chnl_ctrl_34; assign ch0_csr_chnl_in[559:544] = ch0_in_chnl_ctrl_35; assign ch1_csr_chnl_in[559:544] = ch1_in_chnl_ctrl_35; assign ch2_csr_chnl_in[559:544] = ch2_in_chnl_ctrl_35; assign ch3_csr_chnl_in[559:544] = ch3_in_chnl_ctrl_35; //assign ch4_csr_chnl_in[559:544] = ch4_in_chnl_ctrl_35; //assign ch5_csr_chnl_in[559:544] = ch5_in_chnl_ctrl_35; assign ch0_csr_chnl_in[575:560] = ch0_in_chnl_ctrl_36; assign ch1_csr_chnl_in[575:560] = ch1_in_chnl_ctrl_36; assign ch2_csr_chnl_in[575:560] = ch2_in_chnl_ctrl_36; assign ch3_csr_chnl_in[575:560] = ch3_in_chnl_ctrl_36; //assign ch4_csr_chnl_in[575:560] = ch4_in_chnl_ctrl_36; //assign ch5_csr_chnl_in[575:560] = ch5_in_chnl_ctrl_36; assign ch0_csr_chnl_in[591:576] = ch0_in_chnl_ctrl_37; assign ch1_csr_chnl_in[591:576] = ch1_in_chnl_ctrl_37; assign ch2_csr_chnl_in[591:576] = ch2_in_chnl_ctrl_37; assign ch3_csr_chnl_in[591:576] = ch3_in_chnl_ctrl_37; //assign ch4_csr_chnl_in[591:576] = ch4_in_chnl_ctrl_37; //assign ch5_csr_chnl_in[591:576] = ch5_in_chnl_ctrl_37; assign ch0_csr_chnl_in[607:592] = ch0_in_chnl_ctrl_38; assign ch1_csr_chnl_in[607:592] = ch1_in_chnl_ctrl_38; assign ch2_csr_chnl_in[607:592] = ch2_in_chnl_ctrl_38; assign ch3_csr_chnl_in[607:592] = ch3_in_chnl_ctrl_38; //assign ch4_csr_chnl_in[607:592] = ch4_in_chnl_ctrl_38; //assign ch5_csr_chnl_in[607:592] = ch5_in_chnl_ctrl_38; assign ch0_csr_chnl_in[623:608] = ch0_in_chnl_ctrl_39; assign ch1_csr_chnl_in[623:608] = ch1_in_chnl_ctrl_39; assign ch2_csr_chnl_in[623:608] = ch2_in_chnl_ctrl_39; assign ch3_csr_chnl_in[623:608] = ch3_in_chnl_ctrl_39; //assign ch4_csr_chnl_in[623:608] = ch4_in_chnl_ctrl_39; //assign ch5_csr_chnl_in[623:608] = ch5_in_chnl_ctrl_39; assign ch0_csr_chnl_in[639:624] = ch0_in_chnl_ctrl_40; assign ch1_csr_chnl_in[639:624] = ch1_in_chnl_ctrl_40; assign ch2_csr_chnl_in[639:624] = ch2_in_chnl_ctrl_40; assign ch3_csr_chnl_in[639:624] = ch3_in_chnl_ctrl_40; //assign ch4_csr_chnl_in[639:624] = ch4_in_chnl_ctrl_40; //assign ch5_csr_chnl_in[639:624] = ch5_in_chnl_ctrl_40; assign ch0_csr_chnl_in[655:640] = ch0_in_chnl_ctrl_41; assign ch1_csr_chnl_in[655:640] = ch1_in_chnl_ctrl_41; assign ch2_csr_chnl_in[655:640] = ch2_in_chnl_ctrl_41; assign ch3_csr_chnl_in[655:640] = ch3_in_chnl_ctrl_41; //assign ch4_csr_chnl_in[655:640] = ch4_in_chnl_ctrl_41; //assign ch5_csr_chnl_in[655:640] = ch5_in_chnl_ctrl_41; assign ch0_csr_chnl_in[671:656] = ch0_in_chnl_ctrl_42; assign ch1_csr_chnl_in[671:656] = ch1_in_chnl_ctrl_42; assign ch2_csr_chnl_in[671:656] = ch2_in_chnl_ctrl_42; assign ch3_csr_chnl_in[671:656] = ch3_in_chnl_ctrl_42; //assign ch4_csr_chnl_in[671:656] = ch4_in_chnl_ctrl_42; //assign ch5_csr_chnl_in[671:656] = ch5_in_chnl_ctrl_42; // reserved assign ch0_csr_chnl_in_reserved[15:0] = ch0_in_chnl_ctrl_43; assign ch1_csr_chnl_in_reserved[15:0] = ch1_in_chnl_ctrl_43; assign ch2_csr_chnl_in_reserved[15:0] = ch2_in_chnl_ctrl_43; assign ch3_csr_chnl_in_reserved[15:0] = ch3_in_chnl_ctrl_43; //assign ch4_csr_chnl_in[15:0] = ch4_in_chnl_ctrl_43; //assign ch5_csr_chnl_in[15:0] = ch5_in_chnl_ctrl_43; assign ch0_csr_chnl_in[687:672] = ch0_in_chnl_ctrl_44; assign ch1_csr_chnl_in[687:672] = ch1_in_chnl_ctrl_44; assign ch2_csr_chnl_in[687:672] = ch2_in_chnl_ctrl_44; assign ch3_csr_chnl_in[687:672] = ch3_in_chnl_ctrl_44; //assign ch4_csr_chnl_in[687:672] = ch4_in_chnl_ctrl_44; //assign ch5_csr_chnl_in[687:672] = ch5_in_chnl_ctrl_44; assign ch0_csr_chnl_in[703:688] = ch0_in_chnl_ctrl_45; assign ch1_csr_chnl_in[703:688] = ch1_in_chnl_ctrl_45; assign ch2_csr_chnl_in[703:688] = ch2_in_chnl_ctrl_45; assign ch3_csr_chnl_in[703:688] = ch3_in_chnl_ctrl_45; //assign ch4_csr_chnl_in[703:688] = ch4_in_chnl_ctrl_45; //assign ch5_csr_chnl_in[703:688] = ch5_in_chnl_ctrl_45; assign ch0_csr_chnl_in[719:704] = ch0_in_chnl_ctrl_46; assign ch1_csr_chnl_in[719:704] = ch1_in_chnl_ctrl_46; assign ch2_csr_chnl_in[719:704] = ch2_in_chnl_ctrl_46; assign ch3_csr_chnl_in[719:704] = ch3_in_chnl_ctrl_46; //assign ch4_csr_chnl_in[719:704] = ch4_in_chnl_ctrl_46; //assign ch5_csr_chnl_in[719:704] = ch5_in_chnl_ctrl_46; assign ch0_csr_chnl_in[735:720] = ch0_in_chnl_ctrl_47; assign ch1_csr_chnl_in[735:720] = ch1_in_chnl_ctrl_47; assign ch2_csr_chnl_in[735:720] = ch2_in_chnl_ctrl_47; assign ch3_csr_chnl_in[735:720] = ch3_in_chnl_ctrl_47; //assign ch4_csr_chnl_in[735:720] = ch4_in_chnl_ctrl_47; //assign ch5_csr_chnl_in[735:720] = ch5_in_chnl_ctrl_47; assign ch0_csr_chnl_in[751:736] = ch0_in_chnl_ctrl_48; assign ch1_csr_chnl_in[751:736] = ch1_in_chnl_ctrl_48; assign ch2_csr_chnl_in[751:736] = ch2_in_chnl_ctrl_48; assign ch3_csr_chnl_in[751:736] = ch3_in_chnl_ctrl_48; //assign ch4_csr_chnl_in[751:736] = ch4_in_chnl_ctrl_48; //assign ch5_csr_chnl_in[751:736] = ch5_in_chnl_ctrl_48; assign ch0_csr_chnl_in[767:752] = ch0_in_chnl_ctrl_49; assign ch1_csr_chnl_in[767:752] = ch1_in_chnl_ctrl_49; assign ch2_csr_chnl_in[767:752] = ch2_in_chnl_ctrl_49; assign ch3_csr_chnl_in[767:752] = ch3_in_chnl_ctrl_49; //assign ch4_csr_chnl_in[767:752] = ch4_in_chnl_ctrl_49; //assign ch5_csr_chnl_in[767:752] = ch5_in_chnl_ctrl_49; assign ch0_csr_chnl_in[783:768] = ch0_in_chnl_ctrl_50; assign ch1_csr_chnl_in[783:768] = ch1_in_chnl_ctrl_50; assign ch2_csr_chnl_in[783:768] = ch2_in_chnl_ctrl_50; assign ch3_csr_chnl_in[783:768] = ch3_in_chnl_ctrl_50; //assign ch4_csr_chnl_in[783:768] = ch4_in_chnl_ctrl_50; //assign ch5_csr_chnl_in[783:768] = ch5_in_chnl_ctrl_50; assign ch0_csr_chnl_in[799:784] = ch0_in_chnl_ctrl_51; assign ch1_csr_chnl_in[799:784] = ch1_in_chnl_ctrl_51; assign ch2_csr_chnl_in[799:784] = ch2_in_chnl_ctrl_51; assign ch3_csr_chnl_in[799:784] = ch3_in_chnl_ctrl_51; //assign ch4_csr_chnl_in[799:784] = ch4_in_chnl_ctrl_51; //assign ch5_csr_chnl_in[799:784] = ch5_in_chnl_ctrl_51; assign ch0_csr_chnl_in[815:800] = ch0_in_chnl_ctrl_52; assign ch1_csr_chnl_in[815:800] = ch1_in_chnl_ctrl_52; assign ch2_csr_chnl_in[815:800] = ch2_in_chnl_ctrl_52; assign ch3_csr_chnl_in[815:800] = ch3_in_chnl_ctrl_52; //assign ch4_csr_chnl_in[815:800] = ch4_in_chnl_ctrl_52; //assign ch5_csr_chnl_in[815:800] = ch5_in_chnl_ctrl_52; assign ch0_csr_chnl_in[831:816] = ch0_in_chnl_ctrl_53; assign ch1_csr_chnl_in[831:816] = ch1_in_chnl_ctrl_53; assign ch2_csr_chnl_in[831:816] = ch2_in_chnl_ctrl_53; assign ch3_csr_chnl_in[831:816] = ch3_in_chnl_ctrl_53; //assign ch4_csr_chnl_in[831:816] = ch4_in_chnl_ctrl_53; //assign ch5_csr_chnl_in[831:816] = ch5_in_chnl_ctrl_53; // ------------------------------------------------------------ // Read DPRIOIN ----------------------------------------------- // ------------------------------------------------------------ // -------- HW ordering -------------------------------------- //TXPCS assign ch0_out_chnl_ctrl_1 = ch0_dp_chnl_out[15:0]; assign ch1_out_chnl_ctrl_1 = ch1_dp_chnl_out[15:0]; assign ch2_out_chnl_ctrl_1 = ch2_dp_chnl_out[15:0]; assign ch3_out_chnl_ctrl_1 = ch3_dp_chnl_out[15:0]; assign ch0_out_chnl_ctrl_2 = ch0_dp_chnl_out[31:16]; assign ch1_out_chnl_ctrl_2 = ch1_dp_chnl_out[31:16]; assign ch2_out_chnl_ctrl_2 = ch2_dp_chnl_out[31:16]; assign ch3_out_chnl_ctrl_2 = ch3_dp_chnl_out[31:16]; assign ch0_out_chnl_ctrl_3 = ch0_dp_chnl_out[47:32]; assign ch1_out_chnl_ctrl_3 = ch1_dp_chnl_out[47:32]; assign ch2_out_chnl_ctrl_3 = ch2_dp_chnl_out[47:32]; assign ch3_out_chnl_ctrl_3 = ch3_dp_chnl_out[47:32]; assign ch0_out_chnl_ctrl_4 = ch0_dp_chnl_out[63:48]; assign ch1_out_chnl_ctrl_4 = ch1_dp_chnl_out[63:48]; assign ch2_out_chnl_ctrl_4 = ch2_dp_chnl_out[63:48]; assign ch3_out_chnl_ctrl_4 = ch3_dp_chnl_out[63:48]; assign ch0_out_chnl_ctrl_5 = ch0_dp_chnl_out[79:64]; assign ch1_out_chnl_ctrl_5 = ch1_dp_chnl_out[79:64]; assign ch2_out_chnl_ctrl_5 = ch2_dp_chnl_out[79:64]; assign ch3_out_chnl_ctrl_5 = ch3_dp_chnl_out[79:64]; assign ch0_out_chnl_ctrl_6 = ch0_dp_chnl_out[95:80]; assign ch1_out_chnl_ctrl_6 = ch1_dp_chnl_out[95:80]; assign ch2_out_chnl_ctrl_6 = ch2_dp_chnl_out[95:80]; assign ch3_out_chnl_ctrl_6 = ch3_dp_chnl_out[95:80]; assign ch0_out_chnl_ctrl_7 = ch0_dp_chnl_out[111:96]; assign ch1_out_chnl_ctrl_7 = ch1_dp_chnl_out[111:96]; assign ch2_out_chnl_ctrl_7 = ch2_dp_chnl_out[111:96]; assign ch3_out_chnl_ctrl_7 = ch3_dp_chnl_out[111:96]; assign ch0_out_chnl_ctrl_8 = ch0_dp_chnl_out[127:112]; assign ch1_out_chnl_ctrl_8 = ch1_dp_chnl_out[127:112]; assign ch2_out_chnl_ctrl_8 = ch2_dp_chnl_out[127:112]; assign ch3_out_chnl_ctrl_8 = ch3_dp_chnl_out[127:112]; assign ch0_out_chnl_ctrl_9 = ch0_dp_chnl_out[143:128]; assign ch1_out_chnl_ctrl_9 = ch1_dp_chnl_out[143:128]; assign ch2_out_chnl_ctrl_9 = ch2_dp_chnl_out[143:128]; assign ch3_out_chnl_ctrl_9 = ch3_dp_chnl_out[143:128]; assign ch0_out_chnl_ctrl_10 = ch0_dp_chnl_out[159:144]; assign ch1_out_chnl_ctrl_10 = ch1_dp_chnl_out[159:144]; assign ch2_out_chnl_ctrl_10 = ch2_dp_chnl_out[159:144]; assign ch3_out_chnl_ctrl_10 = ch3_dp_chnl_out[159:144]; assign ch0_out_chnl_ctrl_11 = ch0_dp_chnl_out[175:160]; assign ch1_out_chnl_ctrl_11 = ch1_dp_chnl_out[175:160]; assign ch2_out_chnl_ctrl_11 = ch2_dp_chnl_out[175:160]; assign ch3_out_chnl_ctrl_11 = ch3_dp_chnl_out[175:160]; assign ch0_out_chnl_ctrl_12 = ch0_dp_chnl_out[191:176]; assign ch1_out_chnl_ctrl_12 = ch1_dp_chnl_out[191:176]; assign ch2_out_chnl_ctrl_12 = ch2_dp_chnl_out[191:176]; assign ch3_out_chnl_ctrl_12 = ch3_dp_chnl_out[191:176]; assign ch0_out_chnl_ctrl_13 = ch0_dp_chnl_out[207:192]; assign ch1_out_chnl_ctrl_13 = ch1_dp_chnl_out[207:192]; assign ch2_out_chnl_ctrl_13 = ch2_dp_chnl_out[207:192]; assign ch3_out_chnl_ctrl_13 = ch3_dp_chnl_out[207:192]; assign ch0_out_chnl_ctrl_14 = ch0_dp_chnl_out[223:208]; assign ch1_out_chnl_ctrl_14 = ch1_dp_chnl_out[223:208]; assign ch2_out_chnl_ctrl_14 = ch2_dp_chnl_out[223:208]; assign ch3_out_chnl_ctrl_14 = ch3_dp_chnl_out[223:208]; assign ch0_out_chnl_ctrl_15 = ch0_dp_chnl_out[239:224]; assign ch1_out_chnl_ctrl_15 = ch1_dp_chnl_out[239:224]; assign ch2_out_chnl_ctrl_15 = ch2_dp_chnl_out[239:224]; assign ch3_out_chnl_ctrl_15 = ch3_dp_chnl_out[239:224]; assign ch0_out_chnl_ctrl_16 = ch0_dp_chnl_out[255:240]; assign ch1_out_chnl_ctrl_16 = ch1_dp_chnl_out[255:240]; assign ch2_out_chnl_ctrl_16 = ch2_dp_chnl_out[255:240]; assign ch3_out_chnl_ctrl_16 = ch3_dp_chnl_out[255:240]; assign ch0_out_chnl_ctrl_17 = ch0_dp_chnl_out[271:256]; assign ch1_out_chnl_ctrl_17 = ch1_dp_chnl_out[271:256]; assign ch2_out_chnl_ctrl_17 = ch2_dp_chnl_out[271:256]; assign ch3_out_chnl_ctrl_17 = ch3_dp_chnl_out[271:256]; assign ch0_out_chnl_ctrl_18 = ch0_dp_chnl_out[287:272]; assign ch1_out_chnl_ctrl_18 = ch1_dp_chnl_out[287:272]; assign ch2_out_chnl_ctrl_18 = ch2_dp_chnl_out[287:272]; assign ch3_out_chnl_ctrl_18 = ch3_dp_chnl_out[287:272]; assign ch0_out_chnl_ctrl_19 = ch0_dp_chnl_out[303:288]; assign ch1_out_chnl_ctrl_19 = ch1_dp_chnl_out[303:288]; assign ch2_out_chnl_ctrl_19 = ch2_dp_chnl_out[303:288]; assign ch3_out_chnl_ctrl_19 = ch3_dp_chnl_out[303:288]; assign ch0_out_chnl_ctrl_20 = ch0_dp_chnl_out[319:304]; assign ch1_out_chnl_ctrl_20 = ch1_dp_chnl_out[319:304]; assign ch2_out_chnl_ctrl_20 = ch2_dp_chnl_out[319:304]; assign ch3_out_chnl_ctrl_20 = ch3_dp_chnl_out[319:304]; assign ch0_out_chnl_ctrl_21 = ch0_dp_chnl_out[335:320]; assign ch1_out_chnl_ctrl_21 = ch1_dp_chnl_out[335:320]; assign ch2_out_chnl_ctrl_21 = ch2_dp_chnl_out[335:320]; assign ch3_out_chnl_ctrl_21 = ch3_dp_chnl_out[335:320]; assign ch0_out_chnl_ctrl_22 = ch0_dp_chnl_out[351:336]; assign ch1_out_chnl_ctrl_22 = ch1_dp_chnl_out[351:336]; assign ch2_out_chnl_ctrl_22 = ch2_dp_chnl_out[351:336]; assign ch3_out_chnl_ctrl_22 = ch3_dp_chnl_out[351:336]; assign ch0_out_chnl_ctrl_23 = ch0_dp_chnl_out[367:352]; assign ch1_out_chnl_ctrl_23 = ch1_dp_chnl_out[367:352]; assign ch2_out_chnl_ctrl_23 = ch2_dp_chnl_out[367:352]; assign ch3_out_chnl_ctrl_23 = ch3_dp_chnl_out[367:352]; assign ch0_out_chnl_ctrl_24 = ch0_dp_chnl_out[383:368]; assign ch1_out_chnl_ctrl_24 = ch1_dp_chnl_out[383:368]; assign ch2_out_chnl_ctrl_24 = ch2_dp_chnl_out[383:368]; assign ch3_out_chnl_ctrl_24 = ch3_dp_chnl_out[383:368]; assign ch0_out_chnl_ctrl_25 = ch0_dp_chnl_out[399:384]; assign ch1_out_chnl_ctrl_25 = ch1_dp_chnl_out[399:384]; assign ch2_out_chnl_ctrl_25 = ch2_dp_chnl_out[399:384]; assign ch3_out_chnl_ctrl_25 = ch3_dp_chnl_out[399:384]; assign ch0_out_chnl_ctrl_26 = ch0_dp_chnl_out[415:400]; assign ch1_out_chnl_ctrl_26 = ch1_dp_chnl_out[415:400]; assign ch2_out_chnl_ctrl_26 = ch2_dp_chnl_out[415:400]; assign ch3_out_chnl_ctrl_26 = ch3_dp_chnl_out[415:400]; assign ch0_out_chnl_ctrl_27 = ch0_dp_chnl_out[431:416]; assign ch1_out_chnl_ctrl_27 = ch1_dp_chnl_out[431:416]; assign ch2_out_chnl_ctrl_27 = ch2_dp_chnl_out[431:416]; assign ch3_out_chnl_ctrl_27 = ch3_dp_chnl_out[431:416]; // TXPMA assign ch0_out_chnl_ctrl_28 = ch0_dp_chnl_out[447:432]; assign ch1_out_chnl_ctrl_28 = ch1_dp_chnl_out[447:432]; assign ch2_out_chnl_ctrl_28 = ch2_dp_chnl_out[447:432]; assign ch3_out_chnl_ctrl_28 = ch3_dp_chnl_out[447:432]; //assign ch4_out_chnl_ctrl_28 = ch4_dp_chnl_out[447:432]; //assign ch5_out_chnl_ctrl_28 = ch5_dp_chnl_out[447:432]; assign ch0_out_chnl_ctrl_29 = ch0_dp_chnl_out[463:448]; assign ch1_out_chnl_ctrl_29 = ch1_dp_chnl_out[463:448]; assign ch2_out_chnl_ctrl_29 = ch2_dp_chnl_out[463:448]; assign ch3_out_chnl_ctrl_29 = ch3_dp_chnl_out[463:448]; //assign ch4_out_chnl_ctrl_29 = ch4_dp_chnl_out[463:448]; //assign ch5_out_chnl_ctrl_29 = ch5_dp_chnl_out[463:448]; assign ch0_out_chnl_ctrl_30 = ch0_dp_chnl_out[479:464]; assign ch1_out_chnl_ctrl_30 = ch1_dp_chnl_out[479:464]; assign ch2_out_chnl_ctrl_30 = ch2_dp_chnl_out[479:464]; assign ch3_out_chnl_ctrl_30 = ch3_dp_chnl_out[479:464]; //assign ch4_out_chnl_ctrl_30 = ch4_dp_chnl_out[479:464]; //assign ch5_out_chnl_ctrl_30 = ch5_dp_chnl_out[479:464]; assign ch0_out_chnl_ctrl_31 = ch0_dp_chnl_out[495:480]; assign ch1_out_chnl_ctrl_31 = ch1_dp_chnl_out[495:480]; assign ch2_out_chnl_ctrl_31 = ch2_dp_chnl_out[495:480]; assign ch3_out_chnl_ctrl_31 = ch3_dp_chnl_out[495:480]; //assign ch4_out_chnl_ctrl_31 = ch4_dp_chnl_out[495:480]; //assign ch5_out_chnl_ctrl_31 = ch5_dp_chnl_out[495:480]; assign ch0_out_chnl_ctrl_32 = ch0_dp_chnl_out[511:496]; assign ch1_out_chnl_ctrl_32 = ch1_dp_chnl_out[511:496]; assign ch2_out_chnl_ctrl_32 = ch2_dp_chnl_out[511:496]; assign ch3_out_chnl_ctrl_32 = ch3_dp_chnl_out[511:496]; //assign ch4_out_chnl_ctrl_32 = ch4_dp_chnl_out[511:496]; //assign ch5_out_chnl_ctrl_32 = ch5_dp_chnl_out[511:496]; assign ch0_out_chnl_ctrl_33 = ch0_dp_chnl_out[527:512]; assign ch1_out_chnl_ctrl_33 = ch1_dp_chnl_out[527:512]; assign ch2_out_chnl_ctrl_33 = ch2_dp_chnl_out[527:512]; assign ch3_out_chnl_ctrl_33 = ch3_dp_chnl_out[527:512]; //assign ch4_out_chnl_ctrl_33 = ch4_dp_chnl_out[527:512]; //assign ch5_out_chnl_ctrl_33 = ch5_dp_chnl_out[527:512]; assign ch0_out_chnl_ctrl_34 = ch0_dp_chnl_out[543:528]; assign ch1_out_chnl_ctrl_34 = ch1_dp_chnl_out[543:528]; assign ch2_out_chnl_ctrl_34 = ch2_dp_chnl_out[543:528]; assign ch3_out_chnl_ctrl_34 = ch3_dp_chnl_out[543:528]; //assign ch4_out_chnl_ctrl_34 = ch4_dp_chnl_out[543:528]; //assign ch5_out_chnl_ctrl_34 = ch5_dp_chnl_out[543:528]; assign ch0_out_chnl_ctrl_35 = ch0_dp_chnl_out[559:544]; assign ch1_out_chnl_ctrl_35 = ch1_dp_chnl_out[559:544]; assign ch2_out_chnl_ctrl_35 = ch2_dp_chnl_out[559:544]; assign ch3_out_chnl_ctrl_35 = ch3_dp_chnl_out[559:544]; //assign ch4_out_chnl_ctrl_35 = ch4_dp_chnl_out[559:544]; //assign ch5_out_chnl_ctrl_35 = ch5_dp_chnl_out[559:544]; assign ch0_out_chnl_ctrl_36 = ch0_dp_chnl_out[575:560]; assign ch1_out_chnl_ctrl_36 = ch1_dp_chnl_out[575:560]; assign ch2_out_chnl_ctrl_36 = ch2_dp_chnl_out[575:560]; assign ch3_out_chnl_ctrl_36 = ch3_dp_chnl_out[575:560]; //assign ch4_out_chnl_ctrl_36 = ch4_dp_chnl_out[575:560]; //assign ch5_out_chnl_ctrl_36 = ch5_dp_chnl_out[575:560]; assign ch0_out_chnl_ctrl_37 = ch0_dp_chnl_out[591:576]; assign ch1_out_chnl_ctrl_37 = ch1_dp_chnl_out[591:576]; assign ch2_out_chnl_ctrl_37 = ch2_dp_chnl_out[591:576]; assign ch3_out_chnl_ctrl_37 = ch3_dp_chnl_out[591:576]; //assign ch4_out_chnl_ctrl_37 = ch4_dp_chnl_out[591:576]; //assign ch5_out_chnl_ctrl_37 = ch5_dp_chnl_out[591:576]; assign ch0_out_chnl_ctrl_38 = ch0_dp_chnl_out[607:592]; assign ch1_out_chnl_ctrl_38 = ch1_dp_chnl_out[607:592]; assign ch2_out_chnl_ctrl_38 = ch2_dp_chnl_out[607:592]; assign ch3_out_chnl_ctrl_38 = ch3_dp_chnl_out[607:592]; //assign ch4_out_chnl_ctrl_38 = ch4_dp_chnl_out[607:592]; //assign ch5_out_chnl_ctrl_38 = ch5_dp_chnl_out[607:592]; assign ch0_out_chnl_ctrl_39 = ch0_dp_chnl_out[623:608]; assign ch1_out_chnl_ctrl_39 = ch1_dp_chnl_out[623:608]; assign ch2_out_chnl_ctrl_39 = ch2_dp_chnl_out[623:608]; assign ch3_out_chnl_ctrl_39 = ch3_dp_chnl_out[623:608]; //assign ch4_out_chnl_ctrl_39 = ch4_dp_chnl_out[623:608]; //assign ch5_out_chnl_ctrl_39 = ch5_dp_chnl_out[623:608]; assign ch0_out_chnl_ctrl_40 = ch0_dp_chnl_out[639:624]; assign ch1_out_chnl_ctrl_40 = ch1_dp_chnl_out[639:624]; assign ch2_out_chnl_ctrl_40 = ch2_dp_chnl_out[639:624]; assign ch3_out_chnl_ctrl_40 = ch3_dp_chnl_out[639:624]; //assign ch4_out_chnl_ctrl_40 = ch4_dp_chnl_out[639:624]; //assign ch5_out_chnl_ctrl_40 = ch5_dp_chnl_out[639:624]; assign ch0_out_chnl_ctrl_41 = ch0_dp_chnl_out[655:640]; assign ch1_out_chnl_ctrl_41 = ch1_dp_chnl_out[655:640]; assign ch2_out_chnl_ctrl_41 = ch2_dp_chnl_out[655:640]; assign ch3_out_chnl_ctrl_41 = ch3_dp_chnl_out[655:640]; //assign ch4_out_chnl_ctrl_41 = ch4_dp_chnl_out[655:640]; //assign ch5_out_chnl_ctrl_41 = ch5_dp_chnl_out[655:640]; assign ch0_out_chnl_ctrl_42 = ch0_dp_chnl_out[671:656]; assign ch1_out_chnl_ctrl_42 = ch1_dp_chnl_out[671:656]; assign ch2_out_chnl_ctrl_42 = ch2_dp_chnl_out[671:656]; assign ch3_out_chnl_ctrl_42 = ch3_dp_chnl_out[671:656]; //assign ch4_out_chnl_ctrl_42 = ch4_dp_chnl_out[671:656]; //assign ch5_out_chnl_ctrl_42 = ch5_dp_chnl_out[671:656]; // reserved assign ch0_out_chnl_ctrl_43 = ch0_dp_chnl_out_reserved[15:0]; assign ch1_out_chnl_ctrl_43 = ch1_dp_chnl_out_reserved[15:0]; assign ch2_out_chnl_ctrl_43 = ch2_dp_chnl_out_reserved[15:0]; assign ch3_out_chnl_ctrl_43 = ch3_dp_chnl_out_reserved[15:0]; //assign ch4_out_chnl_ctrl_43 = ch4_dp_chnl_out[15:0]; //assign ch5_out_chnl_ctrl_43 = ch5_dp_chnl_out[15:0]; assign ch0_out_chnl_ctrl_44 = ch0_dp_chnl_out[687:672]; assign ch1_out_chnl_ctrl_44 = ch1_dp_chnl_out[687:672]; assign ch2_out_chnl_ctrl_44 = ch2_dp_chnl_out[687:672]; assign ch3_out_chnl_ctrl_44 = ch3_dp_chnl_out[687:672]; //assign ch4_out_chnl_ctrl_44 = ch4_dp_chnl_out[687:672]; //assign ch5_out_chnl_ctrl_44 = ch5_dp_chnl_out[687:672]; assign ch0_out_chnl_ctrl_45 = ch0_dp_chnl_out[703:688]; assign ch1_out_chnl_ctrl_45 = ch1_dp_chnl_out[703:688]; assign ch2_out_chnl_ctrl_45 = ch2_dp_chnl_out[703:688]; assign ch3_out_chnl_ctrl_45 = ch3_dp_chnl_out[703:688]; //assign ch4_out_chnl_ctrl_45 = ch4_dp_chnl_out[703:688]; //assign ch5_out_chnl_ctrl_45 = ch5_dp_chnl_out[703:688]; assign ch0_out_chnl_ctrl_46 = ch0_dp_chnl_out[719:704]; assign ch1_out_chnl_ctrl_46 = ch1_dp_chnl_out[719:704]; assign ch2_out_chnl_ctrl_46 = ch2_dp_chnl_out[719:704]; assign ch3_out_chnl_ctrl_46 = ch3_dp_chnl_out[719:704]; //assign ch4_out_chnl_ctrl_46 = ch4_dp_chnl_out[719:704]; //assign ch5_out_chnl_ctrl_46 = ch5_dp_chnl_out[719:704]; assign ch0_out_chnl_ctrl_47 = ch0_dp_chnl_out[735:720]; assign ch1_out_chnl_ctrl_47 = ch1_dp_chnl_out[735:720]; assign ch2_out_chnl_ctrl_47 = ch2_dp_chnl_out[735:720]; assign ch3_out_chnl_ctrl_47 = ch3_dp_chnl_out[735:720]; //assign ch4_out_chnl_ctrl_47 = ch4_dp_chnl_out[735:720]; //assign ch5_out_chnl_ctrl_47 = ch5_dp_chnl_out[735:720]; assign ch0_out_chnl_ctrl_48 = ch0_dp_chnl_out[751:736]; assign ch1_out_chnl_ctrl_48 = ch1_dp_chnl_out[751:736]; assign ch2_out_chnl_ctrl_48 = ch2_dp_chnl_out[751:736]; assign ch3_out_chnl_ctrl_48 = ch3_dp_chnl_out[751:736]; //assign ch4_out_chnl_ctrl_48 = ch4_dp_chnl_out[751:736]; //assign ch5_out_chnl_ctrl_48 = ch5_dp_chnl_out[751:736]; assign ch0_out_chnl_ctrl_49 = ch0_dp_chnl_out[767:752]; assign ch1_out_chnl_ctrl_49 = ch1_dp_chnl_out[767:752]; assign ch2_out_chnl_ctrl_49 = ch2_dp_chnl_out[767:752]; assign ch3_out_chnl_ctrl_49 = ch3_dp_chnl_out[767:752]; //assign ch4_out_chnl_ctrl_49 = ch4_dp_chnl_out[767:752]; //assign ch5_out_chnl_ctrl_49 = ch5_dp_chnl_out[767:752]; assign ch0_out_chnl_ctrl_50 = ch0_dp_chnl_out[783:768]; assign ch1_out_chnl_ctrl_50 = ch1_dp_chnl_out[783:768]; assign ch2_out_chnl_ctrl_50 = ch2_dp_chnl_out[783:768]; assign ch3_out_chnl_ctrl_50 = ch3_dp_chnl_out[783:768]; //assign ch4_out_chnl_ctrl_50 = ch4_dp_chnl_out[783:768]; //assign ch5_out_chnl_ctrl_50 = ch5_dp_chnl_out[783:768]; assign ch0_out_chnl_ctrl_51 = ch0_dp_chnl_out[799:784]; assign ch1_out_chnl_ctrl_51 = ch1_dp_chnl_out[799:784]; assign ch2_out_chnl_ctrl_51 = ch2_dp_chnl_out[799:784]; assign ch3_out_chnl_ctrl_51 = ch3_dp_chnl_out[799:784]; //assign ch4_out_chnl_ctrl_51 = ch4_dp_chnl_out[799:784]; //assign ch5_out_chnl_ctrl_51 = ch5_dp_chnl_out[799:784]; assign ch0_out_chnl_ctrl_52 = ch0_dp_chnl_out[815:800]; assign ch1_out_chnl_ctrl_52 = ch1_dp_chnl_out[815:800]; assign ch2_out_chnl_ctrl_52 = ch2_dp_chnl_out[815:800]; assign ch3_out_chnl_ctrl_52 = ch3_dp_chnl_out[815:800]; //assign ch4_out_chnl_ctrl_52 = ch4_dp_chnl_out[815:800]; //assign ch5_out_chnl_ctrl_52 = ch5_dp_chnl_out[815:800]; assign ch0_out_chnl_ctrl_53 = ch0_dp_chnl_out[831:816]; assign ch1_out_chnl_ctrl_53 = ch1_dp_chnl_out[831:816]; assign ch2_out_chnl_ctrl_53 = ch2_dp_chnl_out[831:816]; assign ch3_out_chnl_ctrl_53 = ch3_dp_chnl_out[831:816]; //assign ch4_out_chnl_ctrl_53 = ch4_dp_chnl_out[831:816]; //assign ch5_out_chnl_ctrl_53 = ch5_dp_chnl_out[831:816]; // -------- SW ordering ------------------------------------- //TXPCS assign ch0_txpcsdprioout_phy[`rforce_kchar_DP_TXPCS_IDX_0 : `rforce_disp_DP_TXPCS_IDX_0] = ch0_out_chnl_ctrl_1; assign ch1_txpcsdprioout_phy[`rforce_kchar_DP_TXPCS_IDX_0 : `rforce_disp_DP_TXPCS_IDX_0] = ch1_out_chnl_ctrl_1; assign ch2_txpcsdprioout_phy[`rforce_kchar_DP_TXPCS_IDX_0 : `rforce_disp_DP_TXPCS_IDX_0] = ch2_out_chnl_ctrl_1; assign ch3_txpcsdprioout_phy[`rforce_kchar_DP_TXPCS_IDX_0 : `rforce_disp_DP_TXPCS_IDX_0] = ch3_out_chnl_ctrl_1; assign ch0_txpcsdprioout_phy[`rendec_tx_DP_TXPCS_IDX_0 : `rtxpcsbypass_en_DP_TXPCS_IDX_0] = ch0_out_chnl_ctrl_2; assign ch1_txpcsdprioout_phy[`rendec_tx_DP_TXPCS_IDX_0 : `rtxpcsbypass_en_DP_TXPCS_IDX_0] = ch1_out_chnl_ctrl_2; assign ch2_txpcsdprioout_phy[`rendec_tx_DP_TXPCS_IDX_0 : `rtxpcsbypass_en_DP_TXPCS_IDX_0] = ch2_out_chnl_ctrl_2; assign ch3_txpcsdprioout_phy[`rendec_tx_DP_TXPCS_IDX_0 : `rtxpcsbypass_en_DP_TXPCS_IDX_0] = ch3_out_chnl_ctrl_2; assign ch0_txpcsdprioout_phy[`rtx_pipe_enable_DP_TXPCS_IDX_0 : `reserved_0_TB3_DP_TXPCS_IDX_0] = ch0_out_chnl_ctrl_3; assign ch1_txpcsdprioout_phy[`rtx_pipe_enable_DP_TXPCS_IDX_0 : `reserved_0_TB3_DP_TXPCS_IDX_0] = ch1_out_chnl_ctrl_3; assign ch2_txpcsdprioout_phy[`rtx_pipe_enable_DP_TXPCS_IDX_0 : `reserved_0_TB3_DP_TXPCS_IDX_0] = ch2_out_chnl_ctrl_3; assign ch3_txpcsdprioout_phy[`rtx_pipe_enable_DP_TXPCS_IDX_0 : `reserved_0_TB3_DP_TXPCS_IDX_0] = ch3_out_chnl_ctrl_3; assign ch0_txpcsdprioout_phy[`rself_sw_en_tx_DP_TXPCS_IDX_0 : `reserved_0_TB4_DP_TXPCS_IDX_0] = ch0_out_chnl_ctrl_4; assign ch1_txpcsdprioout_phy[`rself_sw_en_tx_DP_TXPCS_IDX_0 : `reserved_0_TB4_DP_TXPCS_IDX_0] = ch1_out_chnl_ctrl_4; assign ch2_txpcsdprioout_phy[`rself_sw_en_tx_DP_TXPCS_IDX_0 : `reserved_0_TB4_DP_TXPCS_IDX_0] = ch2_out_chnl_ctrl_4; assign ch3_txpcsdprioout_phy[`rself_sw_en_tx_DP_TXPCS_IDX_0 : `reserved_0_TB4_DP_TXPCS_IDX_0] = ch3_out_chnl_ctrl_4; assign ch0_rxpcsdprioout_phy[`reserved_0_TB5_DP_RXPCS_IDX_0 : `rrxpcsbypass_en_DP_RXPCS_IDX_0] = ch0_out_chnl_ctrl_5; assign ch1_rxpcsdprioout_phy[`reserved_0_TB5_DP_RXPCS_IDX_0 : `rrxpcsbypass_en_DP_RXPCS_IDX_0] = ch1_out_chnl_ctrl_5; assign ch2_rxpcsdprioout_phy[`reserved_0_TB5_DP_RXPCS_IDX_0 : `rrxpcsbypass_en_DP_RXPCS_IDX_0] = ch2_out_chnl_ctrl_5; assign ch3_rxpcsdprioout_phy[`reserved_0_TB5_DP_RXPCS_IDX_0 : `rrxpcsbypass_en_DP_RXPCS_IDX_0] = ch3_out_chnl_ctrl_5; assign ch0_rxpcsdprioout_phy[`resync_badcg_en_DP_RXPCS_IDX_1 : `rcomp_pat_32_DP_RXPCS_IDX_0] = ch0_out_chnl_ctrl_6; assign ch1_rxpcsdprioout_phy[`resync_badcg_en_DP_RXPCS_IDX_1 : `rcomp_pat_32_DP_RXPCS_IDX_0] = ch1_out_chnl_ctrl_6; assign ch2_rxpcsdprioout_phy[`resync_badcg_en_DP_RXPCS_IDX_1 : `rcomp_pat_32_DP_RXPCS_IDX_0] = ch2_out_chnl_ctrl_6; assign ch3_rxpcsdprioout_phy[`resync_badcg_en_DP_RXPCS_IDX_1 : `rcomp_pat_32_DP_RXPCS_IDX_0] = ch3_out_chnl_ctrl_6; assign ch0_rxpcsdprioout_phy[`rcomp_pat_31_DP_RXPCS_IDX_0 : `rcomp_pat_16_DP_RXPCS_IDX_0] = ch0_out_chnl_ctrl_7; assign ch1_rxpcsdprioout_phy[`rcomp_pat_31_DP_RXPCS_IDX_0 : `rcomp_pat_16_DP_RXPCS_IDX_0] = ch1_out_chnl_ctrl_7; assign ch2_rxpcsdprioout_phy[`rcomp_pat_31_DP_RXPCS_IDX_0 : `rcomp_pat_16_DP_RXPCS_IDX_0] = ch2_out_chnl_ctrl_7; assign ch3_rxpcsdprioout_phy[`rcomp_pat_31_DP_RXPCS_IDX_0 : `rcomp_pat_16_DP_RXPCS_IDX_0] = ch3_out_chnl_ctrl_7; assign ch0_rxpcsdprioout_phy[`rcomp_pat_15_DP_RXPCS_IDX_0 : `rcomp_pat_0_DP_RXPCS_IDX_0] = ch0_out_chnl_ctrl_8; assign ch1_rxpcsdprioout_phy[`rcomp_pat_15_DP_RXPCS_IDX_0 : `rcomp_pat_0_DP_RXPCS_IDX_0] = ch1_out_chnl_ctrl_8; assign ch2_rxpcsdprioout_phy[`rcomp_pat_15_DP_RXPCS_IDX_0 : `rcomp_pat_0_DP_RXPCS_IDX_0] = ch2_out_chnl_ctrl_8; assign ch3_rxpcsdprioout_phy[`rcomp_pat_15_DP_RXPCS_IDX_0 : `rcomp_pat_0_DP_RXPCS_IDX_0] = ch3_out_chnl_ctrl_8; assign ch0_rxpcsdprioout_phy[`rsync_sm_dis_DP_RXPCS_IDX_0 : `rbitloc_rev_en_DP_RXPCS_IDX_0] = ch0_out_chnl_ctrl_9; assign ch1_rxpcsdprioout_phy[`rsync_sm_dis_DP_RXPCS_IDX_0 : `rbitloc_rev_en_DP_RXPCS_IDX_0] = ch1_out_chnl_ctrl_9; assign ch2_rxpcsdprioout_phy[`rsync_sm_dis_DP_RXPCS_IDX_0 : `rbitloc_rev_en_DP_RXPCS_IDX_0] = ch2_out_chnl_ctrl_9; assign ch3_rxpcsdprioout_phy[`rsync_sm_dis_DP_RXPCS_IDX_0 : `rbitloc_rev_en_DP_RXPCS_IDX_0] = ch3_out_chnl_ctrl_9; assign ch0_rxpcsdprioout_phy[`rgnumber_DP_RXPCS_IDX_7 : `rknumber_DP_RXPCS_IDX_0] = ch0_out_chnl_ctrl_10; assign ch1_rxpcsdprioout_phy[`rgnumber_DP_RXPCS_IDX_7 : `rknumber_DP_RXPCS_IDX_0] = ch1_out_chnl_ctrl_10; assign ch2_rxpcsdprioout_phy[`rgnumber_DP_RXPCS_IDX_7 : `rknumber_DP_RXPCS_IDX_0] = ch2_out_chnl_ctrl_10; assign ch3_rxpcsdprioout_phy[`rgnumber_DP_RXPCS_IDX_7 : `rknumber_DP_RXPCS_IDX_0] = ch3_out_chnl_ctrl_10; assign ch0_rxpcsdprioout_phy[`rrundisp_DP_RXPCS_IDX_5 : `renpolinv_rx_DP_RXPCS_IDX_0] = ch0_out_chnl_ctrl_11; assign ch1_rxpcsdprioout_phy[`rrundisp_DP_RXPCS_IDX_5 : `renpolinv_rx_DP_RXPCS_IDX_0] = ch1_out_chnl_ctrl_11; assign ch2_rxpcsdprioout_phy[`rrundisp_DP_RXPCS_IDX_5 : `renpolinv_rx_DP_RXPCS_IDX_0] = ch2_out_chnl_ctrl_11; assign ch3_rxpcsdprioout_phy[`rrundisp_DP_RXPCS_IDX_5 : `renpolinv_rx_DP_RXPCS_IDX_0] = ch3_out_chnl_ctrl_11; assign ch0_rxpcsdprioout_phy[`rmatchen_DP_RXPCS_IDX_0 : `rclkcmpsq1p_0_DP_RXPCS_IDX_0] = ch0_out_chnl_ctrl_12; assign ch1_rxpcsdprioout_phy[`rmatchen_DP_RXPCS_IDX_0 : `rclkcmpsq1p_0_DP_RXPCS_IDX_0] = ch1_out_chnl_ctrl_12; assign ch2_rxpcsdprioout_phy[`rmatchen_DP_RXPCS_IDX_0 : `rclkcmpsq1p_0_DP_RXPCS_IDX_0] = ch2_out_chnl_ctrl_12; assign ch3_rxpcsdprioout_phy[`rmatchen_DP_RXPCS_IDX_0 : `rclkcmpsq1p_0_DP_RXPCS_IDX_0] = ch3_out_chnl_ctrl_12; assign ch0_rxpcsdprioout_phy[`rclkcmpsq1n_19_DP_RXPCS_IDX_0 : `rclkcmpsq1p_10_DP_RXPCS_IDX_0] = ch0_out_chnl_ctrl_13; assign ch1_rxpcsdprioout_phy[`rclkcmpsq1n_19_DP_RXPCS_IDX_0 : `rclkcmpsq1p_10_DP_RXPCS_IDX_0] = ch1_out_chnl_ctrl_13; assign ch2_rxpcsdprioout_phy[`rclkcmpsq1n_19_DP_RXPCS_IDX_0 : `rclkcmpsq1p_10_DP_RXPCS_IDX_0] = ch2_out_chnl_ctrl_13; assign ch3_rxpcsdprioout_phy[`rclkcmpsq1n_19_DP_RXPCS_IDX_0 : `rclkcmpsq1p_10_DP_RXPCS_IDX_0] = ch3_out_chnl_ctrl_13; assign ch0_rxpcsdprioout_phy[`rclkcmpsq1n_14_DP_RXPCS_IDX_0 : `rclkcmpsq1n_0_DP_RXPCS_IDX_0] = ch0_out_chnl_ctrl_14; assign ch1_rxpcsdprioout_phy[`rclkcmpsq1n_14_DP_RXPCS_IDX_0 : `rclkcmpsq1n_0_DP_RXPCS_IDX_0] = ch1_out_chnl_ctrl_14; assign ch2_rxpcsdprioout_phy[`rclkcmpsq1n_14_DP_RXPCS_IDX_0 : `rclkcmpsq1n_0_DP_RXPCS_IDX_0] = ch2_out_chnl_ctrl_14; assign ch3_rxpcsdprioout_phy[`rclkcmpsq1n_14_DP_RXPCS_IDX_0 : `rclkcmpsq1n_0_DP_RXPCS_IDX_0] = ch3_out_chnl_ctrl_14; assign ch0_rxpcsdprioout_phy[`rclkcmp_pipe_en_DP_RXPCS_IDX_0 : `rfull_threshold_DP_RXPCS_IDX_0] = ch0_out_chnl_ctrl_15; assign ch1_rxpcsdprioout_phy[`rclkcmp_pipe_en_DP_RXPCS_IDX_0 : `rfull_threshold_DP_RXPCS_IDX_0] = ch1_out_chnl_ctrl_15; assign ch2_rxpcsdprioout_phy[`rclkcmp_pipe_en_DP_RXPCS_IDX_0 : `rfull_threshold_DP_RXPCS_IDX_0] = ch2_out_chnl_ctrl_15; assign ch3_rxpcsdprioout_phy[`rclkcmp_pipe_en_DP_RXPCS_IDX_0 : `rfull_threshold_DP_RXPCS_IDX_0] = ch3_out_chnl_ctrl_15; assign ch0_rxpcsdprioout_phy[`rempty_threshold_DP_RXPCS_IDX_2 : `rfreq_sel_DP_RXPCS_IDX_0] = ch0_out_chnl_ctrl_16; assign ch1_rxpcsdprioout_phy[`rempty_threshold_DP_RXPCS_IDX_2 : `rfreq_sel_DP_RXPCS_IDX_0] = ch1_out_chnl_ctrl_16; assign ch2_rxpcsdprioout_phy[`rempty_threshold_DP_RXPCS_IDX_2 : `rfreq_sel_DP_RXPCS_IDX_0] = ch2_out_chnl_ctrl_16; assign ch3_rxpcsdprioout_phy[`rempty_threshold_DP_RXPCS_IDX_2 : `rfreq_sel_DP_RXPCS_IDX_0] = ch3_out_chnl_ctrl_16; assign ch0_rxpcsdprioout_phy[`rrxfifo_dis_DP_RXPCS_IDX_0 : `rtest_bus_sel_DP_RXPCS_IDX_0] = ch0_out_chnl_ctrl_17; assign ch1_rxpcsdprioout_phy[`rrxfifo_dis_DP_RXPCS_IDX_0 : `rtest_bus_sel_DP_RXPCS_IDX_0] = ch1_out_chnl_ctrl_17; assign ch2_rxpcsdprioout_phy[`rrxfifo_dis_DP_RXPCS_IDX_0 : `rtest_bus_sel_DP_RXPCS_IDX_0] = ch2_out_chnl_ctrl_17; assign ch3_rxpcsdprioout_phy[`rrxfifo_dis_DP_RXPCS_IDX_0 : `rtest_bus_sel_DP_RXPCS_IDX_0] = ch3_out_chnl_ctrl_17; assign ch0_rxpcsdprioout_phy[`reserved_0_TB18_DP_RXPCS_IDX_5 : `rbytordpat_0_DP_RXPCS_IDX_0] = ch0_out_chnl_ctrl_18; assign ch1_rxpcsdprioout_phy[`reserved_0_TB18_DP_RXPCS_IDX_5 : `rbytordpat_0_DP_RXPCS_IDX_0] = ch1_out_chnl_ctrl_18; assign ch2_rxpcsdprioout_phy[`reserved_0_TB18_DP_RXPCS_IDX_5 : `rbytordpat_0_DP_RXPCS_IDX_0] = ch2_out_chnl_ctrl_18; assign ch3_rxpcsdprioout_phy[`reserved_0_TB18_DP_RXPCS_IDX_5 : `rbytordpat_0_DP_RXPCS_IDX_0] = ch3_out_chnl_ctrl_18; assign ch0_rxpcsdprioout_phy[`reserved_0_TB19_DP_RXPCS_IDX_5 : `rbytordpad_DP_RXPCS_IDX_0] = ch0_out_chnl_ctrl_19; assign ch1_rxpcsdprioout_phy[`reserved_0_TB19_DP_RXPCS_IDX_5 : `rbytordpad_DP_RXPCS_IDX_0] = ch1_out_chnl_ctrl_19; assign ch2_rxpcsdprioout_phy[`reserved_0_TB19_DP_RXPCS_IDX_5 : `rbytordpad_DP_RXPCS_IDX_0] = ch2_out_chnl_ctrl_19; assign ch3_rxpcsdprioout_phy[`reserved_0_TB19_DP_RXPCS_IDX_5 : `rbytordpad_DP_RXPCS_IDX_0] = ch3_out_chnl_ctrl_19; assign ch0_rxpcsdprioout_phy[`rrx_pipe_enable_DP_RXPCS_IDX_0 : `rload_shreg_del_DP_RXPCS_IDX_0] = ch0_out_chnl_ctrl_20; assign ch1_rxpcsdprioout_phy[`rrx_pipe_enable_DP_RXPCS_IDX_0 : `rload_shreg_del_DP_RXPCS_IDX_0] = ch1_out_chnl_ctrl_20; assign ch2_rxpcsdprioout_phy[`rrx_pipe_enable_DP_RXPCS_IDX_0 : `rload_shreg_del_DP_RXPCS_IDX_0] = ch2_out_chnl_ctrl_20; assign ch3_rxpcsdprioout_phy[`rrx_pipe_enable_DP_RXPCS_IDX_0 : `rload_shreg_del_DP_RXPCS_IDX_0] = ch3_out_chnl_ctrl_20; assign ch0_rxpcsdprioout_phy[`rpma_done_count_15_DP_RXPCS_IDX_0 : `rpma_done_count_0_DP_RXPCS_IDX_0] = ch0_out_chnl_ctrl_21; assign ch1_rxpcsdprioout_phy[`rpma_done_count_15_DP_RXPCS_IDX_0 : `rpma_done_count_0_DP_RXPCS_IDX_0] = ch1_out_chnl_ctrl_21; assign ch2_rxpcsdprioout_phy[`rpma_done_count_15_DP_RXPCS_IDX_0 : `rpma_done_count_0_DP_RXPCS_IDX_0] = ch2_out_chnl_ctrl_21; assign ch3_rxpcsdprioout_phy[`rpma_done_count_15_DP_RXPCS_IDX_0 : `rpma_done_count_0_DP_RXPCS_IDX_0] = ch3_out_chnl_ctrl_21; assign ch0_rxpcsdprioout_phy[`rerr_flags_sel_DP_RXPCS_IDX_0 : `rbytordpat_10_DP_RXPCS_IDX_0] = ch0_out_chnl_ctrl_22; assign ch1_rxpcsdprioout_phy[`rerr_flags_sel_DP_RXPCS_IDX_0 : `rbytordpat_10_DP_RXPCS_IDX_0] = ch1_out_chnl_ctrl_22; assign ch2_rxpcsdprioout_phy[`rerr_flags_sel_DP_RXPCS_IDX_0 : `rbytordpat_10_DP_RXPCS_IDX_0] = ch2_out_chnl_ctrl_22; assign ch3_rxpcsdprioout_phy[`rerr_flags_sel_DP_RXPCS_IDX_0 : `rbytordpat_10_DP_RXPCS_IDX_0] = ch3_out_chnl_ctrl_22; assign ch0_rxpcsdprioout_phy[`reserved_0_TB23_DP_RXPCS_IDX_7 : `rwait_count_DP_RXPCS_IDX_0] = ch0_out_chnl_ctrl_23; assign ch1_rxpcsdprioout_phy[`reserved_0_TB23_DP_RXPCS_IDX_7 : `rwait_count_DP_RXPCS_IDX_0] = ch1_out_chnl_ctrl_23; assign ch2_rxpcsdprioout_phy[`reserved_0_TB23_DP_RXPCS_IDX_7 : `rwait_count_DP_RXPCS_IDX_0] = ch2_out_chnl_ctrl_23; assign ch3_rxpcsdprioout_phy[`reserved_0_TB23_DP_RXPCS_IDX_7 : `rwait_count_DP_RXPCS_IDX_0] = ch3_out_chnl_ctrl_23; assign ch0_rxpcsdprioout_phy[`rwait_for_phfifo_cnt_DP_RXPCS_IDX_5 : `rfts_count_DP_RXPCS_IDX_0] = ch0_out_chnl_ctrl_24; assign ch1_rxpcsdprioout_phy[`rwait_for_phfifo_cnt_DP_RXPCS_IDX_5 : `rfts_count_DP_RXPCS_IDX_0] = ch1_out_chnl_ctrl_24; assign ch2_rxpcsdprioout_phy[`rwait_for_phfifo_cnt_DP_RXPCS_IDX_5 : `rfts_count_DP_RXPCS_IDX_0] = ch2_out_chnl_ctrl_24; assign ch3_rxpcsdprioout_phy[`rwait_for_phfifo_cnt_DP_RXPCS_IDX_5 : `rfts_count_DP_RXPCS_IDX_0] = ch3_out_chnl_ctrl_24; assign ch0_rxpcsdprioout_phy[`reserved_0_TB25_DP_RXPCS_IDX_4 : `rppm_meas_delay_DP_RXPCS_IDX_0] = ch0_out_chnl_ctrl_25; assign ch1_rxpcsdprioout_phy[`reserved_0_TB25_DP_RXPCS_IDX_4 : `rppm_meas_delay_DP_RXPCS_IDX_0] = ch1_out_chnl_ctrl_25; assign ch2_rxpcsdprioout_phy[`reserved_0_TB25_DP_RXPCS_IDX_4 : `rppm_meas_delay_DP_RXPCS_IDX_0] = ch2_out_chnl_ctrl_25; assign ch3_rxpcsdprioout_phy[`reserved_0_TB25_DP_RXPCS_IDX_4 : `rppm_meas_delay_DP_RXPCS_IDX_0] = ch3_out_chnl_ctrl_25; assign ch0_rxpcsdprioout_phy[`rphfifo_regmode_rx_DP_RXPCS_IDX_0 : `rauto_pc_en_cnt_DP_RXPCS_IDX_0] = ch0_out_chnl_ctrl_26; assign ch1_rxpcsdprioout_phy[`rphfifo_regmode_rx_DP_RXPCS_IDX_0 : `rauto_pc_en_cnt_DP_RXPCS_IDX_0] = ch1_out_chnl_ctrl_26; assign ch2_rxpcsdprioout_phy[`rphfifo_regmode_rx_DP_RXPCS_IDX_0 : `rauto_pc_en_cnt_DP_RXPCS_IDX_0] = ch2_out_chnl_ctrl_26; assign ch3_rxpcsdprioout_phy[`rphfifo_regmode_rx_DP_RXPCS_IDX_0 : `rauto_pc_en_cnt_DP_RXPCS_IDX_0] = ch3_out_chnl_ctrl_26; assign ch0_rxpcsdprioout_phy[`reserved_0_TB27_DP_RXPCS_IDX_3 : `rmask_count_DP_RXPCS_IDX_0] = ch0_out_chnl_ctrl_27; assign ch1_rxpcsdprioout_phy[`reserved_0_TB27_DP_RXPCS_IDX_3 : `rmask_count_DP_RXPCS_IDX_0] = ch1_out_chnl_ctrl_27; assign ch2_rxpcsdprioout_phy[`reserved_0_TB27_DP_RXPCS_IDX_3 : `rmask_count_DP_RXPCS_IDX_0] = ch2_out_chnl_ctrl_27; assign ch3_rxpcsdprioout_phy[`reserved_0_TB27_DP_RXPCS_IDX_3 : `rmask_count_DP_RXPCS_IDX_0] = ch3_out_chnl_ctrl_27; // TXPMA assign ch0_txpmadprioout_phy[`rvod_sel_non_pcie_DP_TXPMA_IDX_2 : `rpowdnt_DP_TXPMA_IDX_0] = ch0_out_chnl_ctrl_28; assign ch1_txpmadprioout_phy[`rvod_sel_non_pcie_DP_TXPMA_IDX_2 : `rpowdnt_DP_TXPMA_IDX_0] = ch1_out_chnl_ctrl_28; assign ch2_txpmadprioout_phy[`rvod_sel_non_pcie_DP_TXPMA_IDX_2 : `rpowdnt_DP_TXPMA_IDX_0] = ch2_out_chnl_ctrl_28; assign ch3_txpmadprioout_phy[`rvod_sel_non_pcie_DP_TXPMA_IDX_2 : `rpowdnt_DP_TXPMA_IDX_0] = ch3_out_chnl_ctrl_28; assign ch4_txpmadprioout_phy[`rvod_sel_non_pcie_DP_TXPMA_IDX_2 : `rpowdnt_DP_TXPMA_IDX_0] = ch4_out_chnl_ctrl_28; assign ch5_txpmadprioout_phy[`rvod_sel_non_pcie_DP_TXPMA_IDX_2 : `rpowdnt_DP_TXPMA_IDX_0] = ch5_out_chnl_ctrl_28; assign ch0_txpmadprioout_phy[`rpre_em_1t_no_pcie_DP_TXPMA_IDX_4 : `reserved_0_TB29_DP_TXPMA_IDX_0] = ch0_out_chnl_ctrl_29; assign ch1_txpmadprioout_phy[`rpre_em_1t_no_pcie_DP_TXPMA_IDX_4 : `reserved_0_TB29_DP_TXPMA_IDX_0] = ch1_out_chnl_ctrl_29; assign ch2_txpmadprioout_phy[`rpre_em_1t_no_pcie_DP_TXPMA_IDX_4 : `reserved_0_TB29_DP_TXPMA_IDX_0] = ch2_out_chnl_ctrl_29; assign ch3_txpmadprioout_phy[`rpre_em_1t_no_pcie_DP_TXPMA_IDX_4 : `reserved_0_TB29_DP_TXPMA_IDX_0] = ch3_out_chnl_ctrl_29; assign ch4_txpmadprioout_phy[`rpre_em_1t_no_pcie_DP_TXPMA_IDX_4 : `reserved_0_TB29_DP_TXPMA_IDX_0] = ch4_out_chnl_ctrl_29; assign ch5_txpmadprioout_phy[`rpre_em_1t_no_pcie_DP_TXPMA_IDX_4 : `reserved_0_TB29_DP_TXPMA_IDX_0] = ch5_out_chnl_ctrl_29; assign ch0_txpmadprioout_phy[`reserved_0_TB30_DP_TXPMA_IDX_2 : `rpre_em_pt_DP_TXPMA_IDX_0] = ch0_out_chnl_ctrl_30; assign ch1_txpmadprioout_phy[`reserved_0_TB30_DP_TXPMA_IDX_2 : `rpre_em_pt_DP_TXPMA_IDX_0] = ch1_out_chnl_ctrl_30; assign ch2_txpmadprioout_phy[`reserved_0_TB30_DP_TXPMA_IDX_2 : `rpre_em_pt_DP_TXPMA_IDX_0] = ch2_out_chnl_ctrl_30; assign ch3_txpmadprioout_phy[`reserved_0_TB30_DP_TXPMA_IDX_2 : `rpre_em_pt_DP_TXPMA_IDX_0] = ch3_out_chnl_ctrl_30; assign ch4_txpmadprioout_phy[`reserved_0_TB30_DP_TXPMA_IDX_2 : `rpre_em_pt_DP_TXPMA_IDX_0] = ch4_out_chnl_ctrl_30; assign ch5_txpmadprioout_phy[`reserved_0_TB30_DP_TXPMA_IDX_2 : `rpre_em_pt_DP_TXPMA_IDX_0] = ch5_out_chnl_ctrl_30; assign ch0_txpmadprioout_phy[`rtx_term_sel_DP_TXPMA_IDX_2 : `rlowv_DP_TXPMA_IDX_0] = ch0_out_chnl_ctrl_31; assign ch1_txpmadprioout_phy[`rtx_term_sel_DP_TXPMA_IDX_2 : `rlowv_DP_TXPMA_IDX_0] = ch1_out_chnl_ctrl_31; assign ch2_txpmadprioout_phy[`rtx_term_sel_DP_TXPMA_IDX_2 : `rlowv_DP_TXPMA_IDX_0] = ch2_out_chnl_ctrl_31; assign ch3_txpmadprioout_phy[`rtx_term_sel_DP_TXPMA_IDX_2 : `rlowv_DP_TXPMA_IDX_0] = ch3_out_chnl_ctrl_31; assign ch4_txpmadprioout_phy[`rtx_term_sel_DP_TXPMA_IDX_2 : `rlowv_DP_TXPMA_IDX_0] = ch4_out_chnl_ctrl_31; assign ch5_txpmadprioout_phy[`rtx_term_sel_DP_TXPMA_IDX_2 : `rlowv_DP_TXPMA_IDX_0] = ch5_out_chnl_ctrl_31; assign ch0_txpmadprioout_phy[`r_dft_sel_DP_TXPMA_IDX_2 : `reserved_1_TB32_DP_TXPMA_IDX_0] = ch0_out_chnl_ctrl_32; assign ch1_txpmadprioout_phy[`r_dft_sel_DP_TXPMA_IDX_2 : `reserved_1_TB32_DP_TXPMA_IDX_0] = ch1_out_chnl_ctrl_32; assign ch2_txpmadprioout_phy[`r_dft_sel_DP_TXPMA_IDX_2 : `reserved_1_TB32_DP_TXPMA_IDX_0] = ch2_out_chnl_ctrl_32; assign ch3_txpmadprioout_phy[`r_dft_sel_DP_TXPMA_IDX_2 : `reserved_1_TB32_DP_TXPMA_IDX_0] = ch3_out_chnl_ctrl_32; assign ch4_txpmadprioout_phy[`r_dft_sel_DP_TXPMA_IDX_2 : `reserved_1_TB32_DP_TXPMA_IDX_0] = ch4_out_chnl_ctrl_32; assign ch5_txpmadprioout_phy[`r_dft_sel_DP_TXPMA_IDX_2 : `reserved_1_TB32_DP_TXPMA_IDX_0] = ch5_out_chnl_ctrl_32; // does not hurt for tx_pma to receiver clock_divider cram - bit[7] goes to rx_pma - manual section //assign ch0_txpmadprioout_phy[`rcgb_x_en_DP_TXPMA_IDX_1 : `reserved_0_TB33_DP_TXPMA_IDX_0] = ch0_out_chnl_ctrl_33; //assign ch1_txpmadprioout_phy[`rcgb_x_en_DP_TXPMA_IDX_1 : `reserved_0_TB33_DP_TXPMA_IDX_0] = ch1_out_chnl_ctrl_33; //assign ch2_txpmadprioout_phy[`rcgb_x_en_DP_TXPMA_IDX_1 : `reserved_0_TB33_DP_TXPMA_IDX_0] = ch2_out_chnl_ctrl_33; //assign ch3_txpmadprioout_phy[`rcgb_x_en_DP_TXPMA_IDX_1 : `reserved_0_TB33_DP_TXPMA_IDX_0] = ch3_out_chnl_ctrl_33; //assign ch4_txpmadprioout_phy[`rcgb_x_en_DP_TXPMA_IDX_1 : `reserved_0_TB33_DP_TXPMA_IDX_0] = ch4_out_chnl_ctrl_33; //assign ch5_txpmadprioout_phy[`rcgb_x_en_DP_TXPMA_IDX_1 : `reserved_0_TB33_DP_TXPMA_IDX_0] = ch5_out_chnl_ctrl_33; assign ch0_txpmadprioout_phy[`riqclk_sel_DP_TXPMA_IDX_1 : `reserved_1_TB34_DP_TXPMA_IDX_0] = ch0_out_chnl_ctrl_34; assign ch1_txpmadprioout_phy[`riqclk_sel_DP_TXPMA_IDX_1 : `reserved_1_TB34_DP_TXPMA_IDX_0] = ch1_out_chnl_ctrl_34; assign ch2_txpmadprioout_phy[`riqclk_sel_DP_TXPMA_IDX_1 : `reserved_1_TB34_DP_TXPMA_IDX_0] = ch2_out_chnl_ctrl_34; assign ch3_txpmadprioout_phy[`riqclk_sel_DP_TXPMA_IDX_1 : `reserved_1_TB34_DP_TXPMA_IDX_0] = ch3_out_chnl_ctrl_34; assign ch4_txpmadprioout_phy[`riqclk_sel_DP_TXPMA_IDX_1 : `reserved_1_TB34_DP_TXPMA_IDX_0] = ch4_out_chnl_ctrl_34; assign ch5_txpmadprioout_phy[`riqclk_sel_DP_TXPMA_IDX_1 : `reserved_1_TB34_DP_TXPMA_IDX_0] = ch5_out_chnl_ctrl_34; assign ch0_txpmadprioout_phy[`rpma_reserved_0_TB35_DP_TXPMA_IDX_15 : `rpma_reserved_0_TB35_DP_TXPMA_IDX_0] = ch0_out_chnl_ctrl_35; assign ch1_txpmadprioout_phy[`rpma_reserved_0_TB35_DP_TXPMA_IDX_15 : `rpma_reserved_0_TB35_DP_TXPMA_IDX_0] = ch1_out_chnl_ctrl_35; assign ch2_txpmadprioout_phy[`rpma_reserved_0_TB35_DP_TXPMA_IDX_15 : `rpma_reserved_0_TB35_DP_TXPMA_IDX_0] = ch2_out_chnl_ctrl_35; assign ch3_txpmadprioout_phy[`rpma_reserved_0_TB35_DP_TXPMA_IDX_15 : `rpma_reserved_0_TB35_DP_TXPMA_IDX_0] = ch3_out_chnl_ctrl_35; assign ch4_txpmadprioout_phy[`rpma_reserved_0_TB35_DP_TXPMA_IDX_15 : `rpma_reserved_0_TB35_DP_TXPMA_IDX_0] = ch4_out_chnl_ctrl_35; assign ch5_txpmadprioout_phy[`rpma_reserved_0_TB35_DP_TXPMA_IDX_15 : `rpma_reserved_0_TB35_DP_TXPMA_IDX_0] = ch5_out_chnl_ctrl_35; assign ch0_rxpmadprioout_phy[`rrx_lst_DP_RXPMA_IDX_4 : `rrx_term_sel_DP_RXPMA_IDX_0] = ch0_out_chnl_ctrl_36; assign ch1_rxpmadprioout_phy[`rrx_lst_DP_RXPMA_IDX_4 : `rrx_term_sel_DP_RXPMA_IDX_0] = ch1_out_chnl_ctrl_36; assign ch2_rxpmadprioout_phy[`rrx_lst_DP_RXPMA_IDX_4 : `rrx_term_sel_DP_RXPMA_IDX_0] = ch2_out_chnl_ctrl_36; assign ch3_rxpmadprioout_phy[`rrx_lst_DP_RXPMA_IDX_4 : `rrx_term_sel_DP_RXPMA_IDX_0] = ch3_out_chnl_ctrl_36; assign ch4_rxpmadprioout_phy[`rrx_lst_DP_RXPMA_IDX_4 : `rrx_term_sel_DP_RXPMA_IDX_0] = ch4_out_chnl_ctrl_36; assign ch5_rxpmadprioout_phy[`rrx_lst_DP_RXPMA_IDX_4 : `rrx_term_sel_DP_RXPMA_IDX_0] = ch5_out_chnl_ctrl_36; assign ch0_rxpmadprioout_phy[`rrx_sdlv_DP_RXPMA_IDX_3 : `rrxurstpma_DP_RXPMA_IDX_0] = ch0_out_chnl_ctrl_37; assign ch1_rxpmadprioout_phy[`rrx_sdlv_DP_RXPMA_IDX_3 : `rrxurstpma_DP_RXPMA_IDX_0] = ch1_out_chnl_ctrl_37; assign ch2_rxpmadprioout_phy[`rrx_sdlv_DP_RXPMA_IDX_3 : `rrxurstpma_DP_RXPMA_IDX_0] = ch2_out_chnl_ctrl_37; assign ch3_rxpmadprioout_phy[`rrx_sdlv_DP_RXPMA_IDX_3 : `rrxurstpma_DP_RXPMA_IDX_0] = ch3_out_chnl_ctrl_37; assign ch4_rxpmadprioout_phy[`rrx_sdlv_DP_RXPMA_IDX_3 : `rrxurstpma_DP_RXPMA_IDX_0] = ch4_out_chnl_ctrl_37; assign ch5_rxpmadprioout_phy[`rrx_sdlv_DP_RXPMA_IDX_3 : `rrxurstpma_DP_RXPMA_IDX_0] = ch5_out_chnl_ctrl_37; assign ch0_rxpmadprioout_phy[`rrx_sd_on_DP_RXPMA_IDX_3 : `reserved_0_TB38_DP_RXPMA_IDX_0] = ch0_out_chnl_ctrl_38; assign ch1_rxpmadprioout_phy[`rrx_sd_on_DP_RXPMA_IDX_3 : `reserved_0_TB38_DP_RXPMA_IDX_0] = ch1_out_chnl_ctrl_38; assign ch2_rxpmadprioout_phy[`rrx_sd_on_DP_RXPMA_IDX_3 : `reserved_0_TB38_DP_RXPMA_IDX_0] = ch2_out_chnl_ctrl_38; assign ch3_rxpmadprioout_phy[`rrx_sd_on_DP_RXPMA_IDX_3 : `reserved_0_TB38_DP_RXPMA_IDX_0] = ch3_out_chnl_ctrl_38; assign ch4_rxpmadprioout_phy[`rrx_sd_on_DP_RXPMA_IDX_3 : `reserved_0_TB38_DP_RXPMA_IDX_0] = ch4_out_chnl_ctrl_38; assign ch5_rxpmadprioout_phy[`rrx_sd_on_DP_RXPMA_IDX_3 : `reserved_0_TB38_DP_RXPMA_IDX_0] = ch5_out_chnl_ctrl_38; // PLL assign ch0_rxplldprioout_phy[`rcru_div2_DP_PLL_IDX_0 : `rcru_pdbwctrl_DP_PLL_IDX_0] = ch0_out_chnl_ctrl_39; assign ch1_rxplldprioout_phy[`rcru_div2_DP_PLL_IDX_0 : `rcru_pdbwctrl_DP_PLL_IDX_0] = ch1_out_chnl_ctrl_39; assign ch2_rxplldprioout_phy[`rcru_div2_DP_PLL_IDX_0 : `rcru_pdbwctrl_DP_PLL_IDX_0] = ch2_out_chnl_ctrl_39; assign ch3_rxplldprioout_phy[`rcru_div2_DP_PLL_IDX_0 : `rcru_pdbwctrl_DP_PLL_IDX_0] = ch3_out_chnl_ctrl_39; assign ch4_rxtxplldprioout_phy[`rcru_div2_DP_PLL_IDX_0 : `rcru_pdbwctrl_DP_PLL_IDX_0] = ch4_out_chnl_ctrl_39; assign ch5_rxtxplldprioout_phy[`rcru_div2_DP_PLL_IDX_0 : `rcru_pdbwctrl_DP_PLL_IDX_0] = ch5_out_chnl_ctrl_39; // PLL - also sending some bit[15] to tx_pma assign ch0_rxplldprioout_phy[`rcru_rlbk_DP_PLL_IDX_0 : `reserved_0_TB40_DP_PLL_IDX_0] = ch0_out_chnl_ctrl_40; assign ch1_rxplldprioout_phy[`rcru_rlbk_DP_PLL_IDX_0 : `reserved_0_TB40_DP_PLL_IDX_0] = ch1_out_chnl_ctrl_40; assign ch2_rxplldprioout_phy[`rcru_rlbk_DP_PLL_IDX_0 : `reserved_0_TB40_DP_PLL_IDX_0] = ch2_out_chnl_ctrl_40; assign ch3_rxplldprioout_phy[`rcru_rlbk_DP_PLL_IDX_0 : `reserved_0_TB40_DP_PLL_IDX_0] = ch3_out_chnl_ctrl_40; assign ch4_rxtxplldprioout_phy[`rcru_rlbk_DP_PLL_IDX_0 : `reserved_0_TB40_DP_PLL_IDX_0] = ch4_out_chnl_ctrl_40; assign ch5_rxtxplldprioout_phy[`rcru_rlbk_DP_PLL_IDX_0 : `reserved_0_TB40_DP_PLL_IDX_0] = ch5_out_chnl_ctrl_40; // PLL assign ch0_rxplldprioout_phy[`rcp_mode_DP_PLL_IDX_0 : `rcru_rgla_isel_DP_PLL_IDX_0] = ch0_out_chnl_ctrl_41; assign ch1_rxplldprioout_phy[`rcp_mode_DP_PLL_IDX_0 : `rcru_rgla_isel_DP_PLL_IDX_0] = ch1_out_chnl_ctrl_41; assign ch2_rxplldprioout_phy[`rcp_mode_DP_PLL_IDX_0 : `rcru_rgla_isel_DP_PLL_IDX_0] = ch2_out_chnl_ctrl_41; assign ch3_rxplldprioout_phy[`rcp_mode_DP_PLL_IDX_0 : `rcru_rgla_isel_DP_PLL_IDX_0] = ch3_out_chnl_ctrl_41; assign ch4_rxtxplldprioout_phy[`rcp_mode_DP_PLL_IDX_0 : `rcru_rgla_isel_DP_PLL_IDX_0] = ch4_out_chnl_ctrl_41; assign ch5_rxtxplldprioout_phy[`rcp_mode_DP_PLL_IDX_0 : `rcru_rgla_isel_DP_PLL_IDX_0] = ch5_out_chnl_ctrl_41; // PLL assign ch0_rxplldprioout_phy[`rcru_pdof_0i_DP_PLL_IDX_3 : `rcru_pdof_270i_DP_PLL_IDX_0] = ch0_out_chnl_ctrl_42; assign ch1_rxplldprioout_phy[`rcru_pdof_0i_DP_PLL_IDX_3 : `rcru_pdof_270i_DP_PLL_IDX_0] = ch1_out_chnl_ctrl_42; assign ch2_rxplldprioout_phy[`rcru_pdof_0i_DP_PLL_IDX_3 : `rcru_pdof_270i_DP_PLL_IDX_0] = ch2_out_chnl_ctrl_42; assign ch3_rxplldprioout_phy[`rcru_pdof_0i_DP_PLL_IDX_3 : `rcru_pdof_270i_DP_PLL_IDX_0] = ch3_out_chnl_ctrl_42; assign ch4_rxtxplldprioout_phy[`rcru_pdof_0i_DP_PLL_IDX_3 : `rcru_pdof_270i_DP_PLL_IDX_0] = ch4_out_chnl_ctrl_42; assign ch5_rxtxplldprioout_phy[`rcru_pdof_0i_DP_PLL_IDX_3 : `rcru_pdof_270i_DP_PLL_IDX_0] = ch5_out_chnl_ctrl_42; // reserved assign ch0_rxpmadprioout_phy[`reserved_0_TB43_DP_RXPMA_IDX_7 : `reye_monitor_DP_RXPMA_IDX_0] = ch0_out_chnl_ctrl_43; assign ch1_rxpmadprioout_phy[`reserved_0_TB43_DP_RXPMA_IDX_7 : `reye_monitor_DP_RXPMA_IDX_0] = ch1_out_chnl_ctrl_43; assign ch2_rxpmadprioout_phy[`reserved_0_TB43_DP_RXPMA_IDX_7 : `reye_monitor_DP_RXPMA_IDX_0] = ch2_out_chnl_ctrl_43; assign ch3_rxpmadprioout_phy[`reserved_0_TB43_DP_RXPMA_IDX_7 : `reye_monitor_DP_RXPMA_IDX_0] = ch3_out_chnl_ctrl_43; assign ch4_rxpmadprioout_phy[`reserved_0_TB43_DP_RXPMA_IDX_7 : `reye_monitor_DP_RXPMA_IDX_0] = ch4_out_chnl_ctrl_43; assign ch5_rxpmadprioout_phy[`reserved_0_TB43_DP_RXPMA_IDX_7 : `reye_monitor_DP_RXPMA_IDX_0] = ch5_out_chnl_ctrl_43; assign ch0_rxpmadprioout_phy[`rpma_reserved_0_TB44_DP_RXPMA_IDX_15 : `rpma_reserved_0_TB44_DP_RXPMA_IDX_0] = ch0_out_chnl_ctrl_44; assign ch1_rxpmadprioout_phy[`rpma_reserved_0_TB44_DP_RXPMA_IDX_15 : `rpma_reserved_0_TB44_DP_RXPMA_IDX_0] = ch1_out_chnl_ctrl_44; assign ch2_rxpmadprioout_phy[`rpma_reserved_0_TB44_DP_RXPMA_IDX_15 : `rpma_reserved_0_TB44_DP_RXPMA_IDX_0] = ch2_out_chnl_ctrl_44; assign ch3_rxpmadprioout_phy[`rpma_reserved_0_TB44_DP_RXPMA_IDX_15 : `rpma_reserved_0_TB44_DP_RXPMA_IDX_0] = ch3_out_chnl_ctrl_44; assign ch4_rxpmadprioout_phy[`rpma_reserved_0_TB44_DP_RXPMA_IDX_15 : `rpma_reserved_0_TB44_DP_RXPMA_IDX_0] = ch4_out_chnl_ctrl_44; assign ch5_rxpmadprioout_phy[`rpma_reserved_0_TB44_DP_RXPMA_IDX_15 : `rpma_reserved_0_TB44_DP_RXPMA_IDX_0] = ch5_out_chnl_ctrl_44; assign ch0_rxpmadprioout_phy[`rpma_doublewidth_rx_DP_RXPMA_IDX_0 : `rppm_cnt_reset_DP_RXPMA_IDX_0] = ch0_out_chnl_ctrl_45; assign ch1_rxpmadprioout_phy[`rpma_doublewidth_rx_DP_RXPMA_IDX_0 : `rppm_cnt_reset_DP_RXPMA_IDX_0] = ch1_out_chnl_ctrl_45; assign ch2_rxpmadprioout_phy[`rpma_doublewidth_rx_DP_RXPMA_IDX_0 : `rppm_cnt_reset_DP_RXPMA_IDX_0] = ch2_out_chnl_ctrl_45; assign ch3_rxpmadprioout_phy[`rpma_doublewidth_rx_DP_RXPMA_IDX_0 : `rppm_cnt_reset_DP_RXPMA_IDX_0] = ch3_out_chnl_ctrl_45; assign ch4_rxpmadprioout_phy[`rpma_doublewidth_rx_DP_RXPMA_IDX_0 : `rppm_cnt_reset_DP_RXPMA_IDX_0] = ch4_out_chnl_ctrl_45; assign ch5_rxpmadprioout_phy[`rpma_doublewidth_rx_DP_RXPMA_IDX_0 : `rppm_cnt_reset_DP_RXPMA_IDX_0] = ch5_out_chnl_ctrl_45; assign ch0_rxpmadprioout_phy[`r_dfe_1t_DP_RXPMA_IDX_2 : `reserved_0_TB46_DP_RXPMA_IDX_0] = ch0_out_chnl_ctrl_46; assign ch1_rxpmadprioout_phy[`r_dfe_1t_DP_RXPMA_IDX_2 : `reserved_0_TB46_DP_RXPMA_IDX_0] = ch1_out_chnl_ctrl_46; assign ch2_rxpmadprioout_phy[`r_dfe_1t_DP_RXPMA_IDX_2 : `reserved_0_TB46_DP_RXPMA_IDX_0] = ch2_out_chnl_ctrl_46; assign ch3_rxpmadprioout_phy[`r_dfe_1t_DP_RXPMA_IDX_2 : `reserved_0_TB46_DP_RXPMA_IDX_0] = ch3_out_chnl_ctrl_46; assign ch4_rxpmadprioout_phy[`r_dfe_1t_DP_RXPMA_IDX_2 : `reserved_0_TB46_DP_RXPMA_IDX_0] = ch4_out_chnl_ctrl_46; assign ch5_rxpmadprioout_phy[`r_dfe_1t_DP_RXPMA_IDX_2 : `reserved_0_TB46_DP_RXPMA_IDX_0] = ch5_out_chnl_ctrl_46; assign ch0_rxpmadprioout_phy[`reserved_0_TB47_DP_RXPMA_IDX_0 : `reqv_set_DP_RXPMA_IDX_0] = ch0_out_chnl_ctrl_47; assign ch1_rxpmadprioout_phy[`reserved_0_TB47_DP_RXPMA_IDX_0 : `reqv_set_DP_RXPMA_IDX_0] = ch1_out_chnl_ctrl_47; assign ch2_rxpmadprioout_phy[`reserved_0_TB47_DP_RXPMA_IDX_0 : `reqv_set_DP_RXPMA_IDX_0] = ch2_out_chnl_ctrl_47; assign ch3_rxpmadprioout_phy[`reserved_0_TB47_DP_RXPMA_IDX_0 : `reqv_set_DP_RXPMA_IDX_0] = ch3_out_chnl_ctrl_47; assign ch4_rxpmadprioout_phy[`reserved_0_TB47_DP_RXPMA_IDX_0 : `reqv_set_DP_RXPMA_IDX_0] = ch4_out_chnl_ctrl_47; assign ch5_rxpmadprioout_phy[`reserved_0_TB47_DP_RXPMA_IDX_0 : `reqv_set_DP_RXPMA_IDX_0] = ch5_out_chnl_ctrl_47; assign ch0_rxpmadprioout_phy[`rlock_lf_ovd_DP_RXPMA_IDX_0 : `rdc_freq_DP_RXPMA_IDX_0] = ch0_out_chnl_ctrl_48; assign ch1_rxpmadprioout_phy[`rlock_lf_ovd_DP_RXPMA_IDX_0 : `rdc_freq_DP_RXPMA_IDX_0] = ch1_out_chnl_ctrl_48; assign ch2_rxpmadprioout_phy[`rlock_lf_ovd_DP_RXPMA_IDX_0 : `rdc_freq_DP_RXPMA_IDX_0] = ch2_out_chnl_ctrl_48; assign ch3_rxpmadprioout_phy[`rlock_lf_ovd_DP_RXPMA_IDX_0 : `rdc_freq_DP_RXPMA_IDX_0] = ch3_out_chnl_ctrl_48; //assign ch4_rxpmadprioout_phy[`rlock_lf_ovd_DP_RXPMA_IDX_0 : `rdc_freq_DP_RXPMA_IDX_0] = ch4_out_chnl_ctrl_48; //assign ch5_rxpmadprioout_phy[`rlock_lf_ovd_DP_RXPMA_IDX_0 : `rdc_freq_DP_RXPMA_IDX_0] = ch5_out_chnl_ctrl_48; assign ch0_rxpmadprioout_phy[`rhyst_hf_DP_RXPMA_IDX_2 : `rrgen_vod_DP_RXPMA_IDX_0] = ch0_out_chnl_ctrl_49; assign ch1_rxpmadprioout_phy[`rhyst_hf_DP_RXPMA_IDX_2 : `rrgen_vod_DP_RXPMA_IDX_0] = ch1_out_chnl_ctrl_49; assign ch2_rxpmadprioout_phy[`rhyst_hf_DP_RXPMA_IDX_2 : `rrgen_vod_DP_RXPMA_IDX_0] = ch2_out_chnl_ctrl_49; assign ch3_rxpmadprioout_phy[`rhyst_hf_DP_RXPMA_IDX_2 : `rrgen_vod_DP_RXPMA_IDX_0] = ch3_out_chnl_ctrl_49; //assign ch4_rxpmadprioout_phy[`rhyst_hf_DP_RXPMA_IDX_2 : `rrgen_vod_DP_RXPMA_IDX_0] = ch4_out_chnl_ctrl_49; //assign ch5_rxpmadprioout_phy[`rhyst_hf_DP_RXPMA_IDX_2 : `rrgen_vod_DP_RXPMA_IDX_0] = ch5_out_chnl_ctrl_49; assign ch0_rxpmadprioout_phy[`rrgen_bw_DP_RXPMA_IDX_1 : `radce_pdb_DP_RXPMA_IDX_0] = ch0_out_chnl_ctrl_50; assign ch1_rxpmadprioout_phy[`rrgen_bw_DP_RXPMA_IDX_1 : `radce_pdb_DP_RXPMA_IDX_0] = ch1_out_chnl_ctrl_50; assign ch2_rxpmadprioout_phy[`rrgen_bw_DP_RXPMA_IDX_1 : `radce_pdb_DP_RXPMA_IDX_0] = ch2_out_chnl_ctrl_50; assign ch3_rxpmadprioout_phy[`rrgen_bw_DP_RXPMA_IDX_1 : `radce_pdb_DP_RXPMA_IDX_0] = ch3_out_chnl_ctrl_50; //assign ch4_rxpmadprioout_phy[`rrgen_bw_DP_RXPMA_IDX_1 : `radce_pdb_DP_RXPMA_IDX_0] = ch4_out_chnl_ctrl_50; //assign ch5_rxpmadprioout_phy[`rrgen_bw_DP_RXPMA_IDX_1 : `radce_pdb_DP_RXPMA_IDX_0] = ch5_out_chnl_ctrl_50; assign ch0_rxpmadprioout_phy[`reserved_0_TB51_DP_RXPMA_IDX_0 : `radce_hflck_DP_RXPMA_IDX_0] = ch0_out_chnl_ctrl_51; assign ch1_rxpmadprioout_phy[`reserved_0_TB51_DP_RXPMA_IDX_0 : `radce_hflck_DP_RXPMA_IDX_0] = ch1_out_chnl_ctrl_51; assign ch2_rxpmadprioout_phy[`reserved_0_TB51_DP_RXPMA_IDX_0 : `radce_hflck_DP_RXPMA_IDX_0] = ch2_out_chnl_ctrl_51; assign ch3_rxpmadprioout_phy[`reserved_0_TB51_DP_RXPMA_IDX_0 : `radce_hflck_DP_RXPMA_IDX_0] = ch3_out_chnl_ctrl_51; //assign ch4_rxpmadprioout_phy[`reserved_0_TB51_DP_RXPMA_IDX_0 : `radce_hflck_DP_RXPMA_IDX_0] = ch4_out_chnl_ctrl_51; //assign ch5_rxpmadprioout_phy[`reserved_0_TB51_DP_RXPMA_IDX_0 : `radce_hflck_DP_RXPMA_IDX_0] = ch5_out_chnl_ctrl_51; assign ch0_rxpmadprioout_phy[`reserved_0_TB52_DP_RXPMA_IDX_0 : `radce_lflck_DP_RXPMA_IDX_0] = ch0_out_chnl_ctrl_52; assign ch1_rxpmadprioout_phy[`reserved_0_TB52_DP_RXPMA_IDX_0 : `radce_lflck_DP_RXPMA_IDX_0] = ch1_out_chnl_ctrl_52; assign ch2_rxpmadprioout_phy[`reserved_0_TB52_DP_RXPMA_IDX_0 : `radce_lflck_DP_RXPMA_IDX_0] = ch2_out_chnl_ctrl_52; assign ch3_rxpmadprioout_phy[`reserved_0_TB52_DP_RXPMA_IDX_0 : `radce_lflck_DP_RXPMA_IDX_0] = ch3_out_chnl_ctrl_52; //assign ch4_rxpmadprioout_phy[`reserved_0_TB52_DP_RXPMA_IDX_0 : `radce_lflck_DP_RXPMA_IDX_0] = ch4_out_chnl_ctrl_52; //assign ch5_rxpmadprioout_phy[`reserved_0_TB52_DP_RXPMA_IDX_0 : `radce_lflck_DP_RXPMA_IDX_0] = ch5_out_chnl_ctrl_52; assign ch0_rxpmadprioout_phy[`reserved_0_TB53_DP_RXPMA_IDX_5 : `radce_digital_DP_RXPMA_IDX_0] = ch0_out_chnl_ctrl_53; assign ch1_rxpmadprioout_phy[`reserved_0_TB53_DP_RXPMA_IDX_5 : `radce_digital_DP_RXPMA_IDX_0] = ch1_out_chnl_ctrl_53; assign ch2_rxpmadprioout_phy[`reserved_0_TB53_DP_RXPMA_IDX_5 : `radce_digital_DP_RXPMA_IDX_0] = ch2_out_chnl_ctrl_53; assign ch3_rxpmadprioout_phy[`reserved_0_TB53_DP_RXPMA_IDX_5 : `radce_digital_DP_RXPMA_IDX_0] = ch3_out_chnl_ctrl_53; //assign ch4_rxpmadprioout_phy[`reserved_0_TB53_DP_RXPMA_IDX_5 : `radce_digital_DP_RXPMA_IDX_0] = ch4_out_chnl_ctrl_53; //assign ch5_rxpmadprioout_phy[`reserved_0_TB53_DP_RXPMA_IDX_5 : `radce_digital_DP_RXPMA_IDX_0] = ch5_out_chnl_ctrl_53; // ---------------------------------------------------------------------------------------------------------------- // Manual section due to one ICD CRAM mapped to multiple Atoms // ---------------------------------------------------------------------------------------------------------------- // RX_PCS ---------------------------------------------------------------------- assign ch0_rxpcsdprioout_phy[`rpmadwidth_rx_DP_RXPCS_IDX] = ch0_out_chnl_ctrl_45[14]; assign ch1_rxpcsdprioout_phy[`rpmadwidth_rx_DP_RXPCS_IDX] = ch1_out_chnl_ctrl_45[14]; assign ch2_rxpcsdprioout_phy[`rpmadwidth_rx_DP_RXPCS_IDX] = ch2_out_chnl_ctrl_45[14]; assign ch3_rxpcsdprioout_phy[`rpmadwidth_rx_DP_RXPCS_IDX] = ch3_out_chnl_ctrl_45[14]; assign ch0_rxpcsdprioout_phy[`rpma_doublewidth_rx_DP_RXPCS_IDX] = ch0_out_chnl_ctrl_45[15]; assign ch1_rxpcsdprioout_phy[`rpma_doublewidth_rx_DP_RXPCS_IDX] = ch1_out_chnl_ctrl_45[15]; assign ch2_rxpcsdprioout_phy[`rpma_doublewidth_rx_DP_RXPCS_IDX] = ch2_out_chnl_ctrl_45[15]; assign ch3_rxpcsdprioout_phy[`rpma_doublewidth_rx_DP_RXPCS_IDX] = ch3_out_chnl_ctrl_45[15]; // ---------------------------------------------------------------------------------------------------------------- // Manual section - global CRAMs to individual channels // ---------------------------------------------------------------------------------------------------------------- // global ctrl 1 - centrl_ctrl_44 assign ch0_rxpcsdprioout_phy[`rendec_data_sel_rx_DP_RXPCS_IDX] = cmu_out_centrl_global_1[6]; assign ch1_rxpcsdprioout_phy[`rendec_data_sel_rx_DP_RXPCS_IDX] = cmu_out_centrl_global_1[6]; assign ch2_rxpcsdprioout_phy[`rendec_data_sel_rx_DP_RXPCS_IDX] = cmu_out_centrl_global_1[6]; assign ch3_rxpcsdprioout_phy[`rendec_data_sel_rx_DP_RXPCS_IDX] = cmu_out_centrl_global_1[6]; assign ch0_rxpcsdprioout_phy[`rdeskewen_DP_RXPCS_IDX] = cmu_out_centrl_global_1[2]; assign ch1_rxpcsdprioout_phy[`rdeskewen_DP_RXPCS_IDX] = cmu_out_centrl_global_1[2]; assign ch2_rxpcsdprioout_phy[`rdeskewen_DP_RXPCS_IDX] = cmu_out_centrl_global_1[2]; assign ch3_rxpcsdprioout_phy[`rdeskewen_DP_RXPCS_IDX] = cmu_out_centrl_global_1[2]; assign ch0_rxpcsdprioout_phy[`rindv_rx_DP_RXPCS_IDX] = cmu_out_centrl_global_1[0]; assign ch1_rxpcsdprioout_phy[`rindv_rx_DP_RXPCS_IDX] = cmu_out_centrl_global_1[0]; assign ch2_rxpcsdprioout_phy[`rindv_rx_DP_RXPCS_IDX] = cmu_out_centrl_global_1[0]; assign ch3_rxpcsdprioout_phy[`rindv_rx_DP_RXPCS_IDX] = cmu_out_centrl_global_1[0]; // global ctrl 2 - centrl_ctrl_45 assign ch0_rxpcsdprioout_phy[`rdskposdisp_DP_RXPCS_IDX] = cmu_out_centrl_global_2[10]; assign ch1_rxpcsdprioout_phy[`rdskposdisp_DP_RXPCS_IDX] = cmu_out_centrl_global_2[10]; assign ch2_rxpcsdprioout_phy[`rdskposdisp_DP_RXPCS_IDX] = cmu_out_centrl_global_2[10]; assign ch3_rxpcsdprioout_phy[`rdskposdisp_DP_RXPCS_IDX] = cmu_out_centrl_global_2[10]; // global ctrl 3 - centrl_ctrl_46 assign ch0_rxpcsdprioout_phy[`rmaster_rx_DP_RXPCS_IDX] = cmu_out_centrl_global_3[3]; assign ch1_rxpcsdprioout_phy[`rmaster_rx_DP_RXPCS_IDX] = cmu_out_centrl_global_3[3]; assign ch2_rxpcsdprioout_phy[`rmaster_rx_DP_RXPCS_IDX] = cmu_out_centrl_global_3[3]; assign ch3_rxpcsdprioout_phy[`rmaster_rx_DP_RXPCS_IDX] = cmu_out_centrl_global_3[3]; assign ch0_rxpcsdprioout_phy[`rmaster_up_rx_DP_RXPCS_IDX] = cmu_out_centrl_global_3[2]; assign ch1_rxpcsdprioout_phy[`rmaster_up_rx_DP_RXPCS_IDX] = cmu_out_centrl_global_3[2]; assign ch2_rxpcsdprioout_phy[`rmaster_up_rx_DP_RXPCS_IDX] = cmu_out_centrl_global_3[2]; assign ch3_rxpcsdprioout_phy[`rmaster_up_rx_DP_RXPCS_IDX] = cmu_out_centrl_global_3[2]; // TX_PCS ---------------------------------------------------------------------- assign ch0_txpcsdprioout_phy[`rauto_speed_ena_DP_TXPCS_IDX] = ch0_out_chnl_ctrl_16[1]; assign ch1_txpcsdprioout_phy[`rauto_speed_ena_DP_TXPCS_IDX] = ch1_out_chnl_ctrl_16[1]; assign ch2_txpcsdprioout_phy[`rauto_speed_ena_DP_TXPCS_IDX] = ch2_out_chnl_ctrl_16[1]; assign ch3_txpcsdprioout_phy[`rauto_speed_ena_DP_TXPCS_IDX] = ch3_out_chnl_ctrl_16[1]; assign ch0_txpcsdprioout_phy[`rfreq_sel_DP_TXPCS_IDX] = ch0_out_chnl_ctrl_16[0]; assign ch1_txpcsdprioout_phy[`rfreq_sel_DP_TXPCS_IDX] = ch1_out_chnl_ctrl_16[0]; assign ch2_txpcsdprioout_phy[`rfreq_sel_DP_TXPCS_IDX] = ch2_out_chnl_ctrl_16[0]; assign ch3_txpcsdprioout_phy[`rfreq_sel_DP_TXPCS_IDX] = ch3_out_chnl_ctrl_16[0]; assign ch0_txpcsdprioout_phy[`rhip_ena_DP_TXPCS_IDX] = ch0_out_chnl_ctrl_16[2]; assign ch1_txpcsdprioout_phy[`rhip_ena_DP_TXPCS_IDX] = ch1_out_chnl_ctrl_16[2]; assign ch2_txpcsdprioout_phy[`rhip_ena_DP_TXPCS_IDX] = ch2_out_chnl_ctrl_16[2]; assign ch3_txpcsdprioout_phy[`rhip_ena_DP_TXPCS_IDX] = ch3_out_chnl_ctrl_16[2]; assign ch0_txpcsdprioout_phy[`rpma_doublewidth_tx_DP_TXPCS_IDX] = ch0_out_chnl_ctrl_33[10]; assign ch1_txpcsdprioout_phy[`rpma_doublewidth_tx_DP_TXPCS_IDX] = ch1_out_chnl_ctrl_33[10]; assign ch2_txpcsdprioout_phy[`rpma_doublewidth_tx_DP_TXPCS_IDX] = ch2_out_chnl_ctrl_33[10]; assign ch3_txpcsdprioout_phy[`rpma_doublewidth_tx_DP_TXPCS_IDX] = ch3_out_chnl_ctrl_33[10]; assign ch0_txpcsdprioout_phy[`rpmadwidth_tx_DP_TXPCS_IDX] = ch0_out_chnl_ctrl_33[9]; assign ch1_txpcsdprioout_phy[`rpmadwidth_tx_DP_TXPCS_IDX] = ch1_out_chnl_ctrl_33[9]; assign ch2_txpcsdprioout_phy[`rpmadwidth_tx_DP_TXPCS_IDX] = ch2_out_chnl_ctrl_33[9]; assign ch3_txpcsdprioout_phy[`rpmadwidth_tx_DP_TXPCS_IDX] = ch3_out_chnl_ctrl_33[9]; // global control 1 - cetnrl_ctrl_44 assign ch0_txpcsdprioout_phy[`rendec_data_sel_tx_DP_TXPCS_IDX] = cmu_out_centrl_global_1[7]; assign ch1_txpcsdprioout_phy[`rendec_data_sel_tx_DP_TXPCS_IDX] = cmu_out_centrl_global_1[7]; assign ch2_txpcsdprioout_phy[`rendec_data_sel_tx_DP_TXPCS_IDX] = cmu_out_centrl_global_1[7]; assign ch3_txpcsdprioout_phy[`rendec_data_sel_tx_DP_TXPCS_IDX] = cmu_out_centrl_global_1[7]; assign ch0_txpcsdprioout_phy[`rindv_tx_DP_TXPCS_IDX] = cmu_out_centrl_global_1[1]; assign ch1_txpcsdprioout_phy[`rindv_tx_DP_TXPCS_IDX] = cmu_out_centrl_global_1[1]; assign ch2_txpcsdprioout_phy[`rindv_tx_DP_TXPCS_IDX] = cmu_out_centrl_global_1[1]; assign ch3_txpcsdprioout_phy[`rindv_tx_DP_TXPCS_IDX] = cmu_out_centrl_global_1[1]; // global control 3 - cetnrl_ctrl_46 assign ch0_txpcsdprioout_phy[`rmaster_tx_DP_TXPCS_IDX] = cmu_out_centrl_global_3[1]; assign ch1_txpcsdprioout_phy[`rmaster_tx_DP_TXPCS_IDX] = cmu_out_centrl_global_3[1]; assign ch2_txpcsdprioout_phy[`rmaster_tx_DP_TXPCS_IDX] = cmu_out_centrl_global_3[1]; assign ch3_txpcsdprioout_phy[`rmaster_tx_DP_TXPCS_IDX] = cmu_out_centrl_global_3[1]; assign ch0_txpcsdprioout_phy[`rmaster_up_tx_DP_TXPCS_IDX] = cmu_out_centrl_global_3[0]; assign ch1_txpcsdprioout_phy[`rmaster_up_tx_DP_TXPCS_IDX] = cmu_out_centrl_global_3[0]; assign ch2_txpcsdprioout_phy[`rmaster_up_tx_DP_TXPCS_IDX] = cmu_out_centrl_global_3[0]; assign ch3_txpcsdprioout_phy[`rmaster_up_tx_DP_TXPCS_IDX] = cmu_out_centrl_global_3[0]; // global control 2 - cetnrl_ctrl_44 to central clock divider only assign ch4_cmudividerdprioout_phy[`rfreerun_centrl_DP_CLOCK_DIV_IDX] = cmu_out_centrl_global_2[15]; assign ch5_cmudividerdprioout_phy[`rfreerun_centrl_DP_CLOCK_DIV_IDX] = cmu_out_centrl_global_2[15]; assign ch4_cmudividerdprioout_phy[`rcentrl_clk_sel_DP_CLOCK_DIV_IDX] = cmu_out_centrl_global_2[14]; assign ch5_cmudividerdprioout_phy[`rcentrl_clk_sel_DP_CLOCK_DIV_IDX] = cmu_out_centrl_global_2[14]; assign ch4_cmudividerdprioout_phy[`rrefclk_out_div2_DP_CLOCK_DIV_IDX] = cmu_out_centrl_global_2[13]; assign ch5_cmudividerdprioout_phy[`rrefclk_out_div2_DP_CLOCK_DIV_IDX] = cmu_out_centrl_global_2[13]; //------------------------------------------------------------------------------ // RX_PMA ---------------------------------------------------------------------- //------------------------------------------------------------------------------ assign ch0_rxpmadprioout_phy[`rs_lpbk_DP_RXPMA_IDX] = ch0_out_chnl_ctrl_33[7]; assign ch1_rxpmadprioout_phy[`rs_lpbk_DP_RXPMA_IDX] = ch1_out_chnl_ctrl_33[7]; assign ch2_rxpmadprioout_phy[`rs_lpbk_DP_RXPMA_IDX] = ch2_out_chnl_ctrl_33[7]; assign ch3_rxpmadprioout_phy[`rs_lpbk_DP_RXPMA_IDX] = ch3_out_chnl_ctrl_33[7]; assign ch4_rxpmadprioout_phy[`rs_lpbk_DP_RXPMA_IDX] = ch4_out_chnl_ctrl_33[7]; assign ch5_rxpmadprioout_phy[`rs_lpbk_DP_RXPMA_IDX] = ch5_out_chnl_ctrl_33[7]; assign ch0_rxpmadprioout_phy[`rrevlb_sw_DP_RXPMA_IDX] = ch0_out_chnl_ctrl_34[10]; assign ch1_rxpmadprioout_phy[`rrevlb_sw_DP_RXPMA_IDX] = ch1_out_chnl_ctrl_34[10]; assign ch2_rxpmadprioout_phy[`rrevlb_sw_DP_RXPMA_IDX] = ch2_out_chnl_ctrl_34[10]; assign ch3_rxpmadprioout_phy[`rrevlb_sw_DP_RXPMA_IDX] = ch3_out_chnl_ctrl_34[10]; assign ch4_rxpmadprioout_phy[`rrevlb_sw_DP_RXPMA_IDX] = ch4_out_chnl_ctrl_34[10]; assign ch5_rxpmadprioout_phy[`rrevlb_sw_DP_RXPMA_IDX] = ch5_out_chnl_ctrl_34[10]; // table40[15] = rcru_rlbk (revere_lpbk) using rs_lpbk_DP_IDX to map to tx_pam.rtx_rlpbk RTL name assign ch0_txpmadprioout_phy[`rs_lpbk_DP_TXPMA_IDX_0] = ch0_out_chnl_ctrl_40[15]; assign ch1_txpmadprioout_phy[`rs_lpbk_DP_TXPMA_IDX_0] = ch1_out_chnl_ctrl_40[15]; assign ch2_txpmadprioout_phy[`rs_lpbk_DP_TXPMA_IDX_0] = ch2_out_chnl_ctrl_40[15]; assign ch3_txpmadprioout_phy[`rs_lpbk_DP_TXPMA_IDX_0] = ch3_out_chnl_ctrl_40[15]; assign ch4_txpmadprioout_phy[`rs_lpbk_DP_TXPMA_IDX_0] = ch4_out_chnl_ctrl_40[15]; assign ch5_txpmadprioout_phy[`rs_lpbk_DP_TXPMA_IDX_0] = ch5_out_chnl_ctrl_40[15]; // CMUDivider -------------------------------------------------------------------------- // Table33: PMA Per Channel TX Control Register 6 for Channel 0 // Table33 is split between clock divider and TX_PMA and also has tx_pma.clkin_select // Output - CMU Clock Divider Portion assign ch0_cmudividerdprioout_phy[`rdynamic_sw_DP_TXPMA_IDX_0] = ch0_out_chnl_ctrl_33[6]; assign ch1_cmudividerdprioout_phy[`rdynamic_sw_DP_TXPMA_IDX_0] = ch1_out_chnl_ctrl_33[6]; assign ch2_cmudividerdprioout_phy[`rdynamic_sw_DP_TXPMA_IDX_0] = ch2_out_chnl_ctrl_33[6]; assign ch3_cmudividerdprioout_phy[`rdynamic_sw_DP_TXPMA_IDX_0] = ch3_out_chnl_ctrl_33[6]; assign ch4_cmudividerdprioout_phy[`rdynamic_sw_DP_TXPMA_IDX_0] = ch4_out_chnl_ctrl_33[6]; assign ch5_cmudividerdprioout_phy[`rdynamic_sw_DP_TXPMA_IDX_0] = ch5_out_chnl_ctrl_33[6]; assign ch0_cmudividerdprioout_phy[`rpmadwidth_tx_DP_TXPMA_IDX_0] = ch0_out_chnl_ctrl_33[9]; assign ch1_cmudividerdprioout_phy[`rpmadwidth_tx_DP_TXPMA_IDX_0] = ch1_out_chnl_ctrl_33[9]; assign ch2_cmudividerdprioout_phy[`rpmadwidth_tx_DP_TXPMA_IDX_0] = ch2_out_chnl_ctrl_33[9]; assign ch3_cmudividerdprioout_phy[`rpmadwidth_tx_DP_TXPMA_IDX_0] = ch3_out_chnl_ctrl_33[9]; assign ch4_cmudividerdprioout_phy[`rpmadwidth_tx_DP_TXPMA_IDX_0] = ch4_out_chnl_ctrl_33[9]; assign ch5_cmudividerdprioout_phy[`rpmadwidth_tx_DP_TXPMA_IDX_0] = ch5_out_chnl_ctrl_33[9]; assign ch0_cmudividerdprioout_phy[`rpma_doublewidth_tx_DP_TXPMA_IDX_0] = ch0_out_chnl_ctrl_33[10]; assign ch1_cmudividerdprioout_phy[`rpma_doublewidth_tx_DP_TXPMA_IDX_0] = ch1_out_chnl_ctrl_33[10]; assign ch2_cmudividerdprioout_phy[`rpma_doublewidth_tx_DP_TXPMA_IDX_0] = ch2_out_chnl_ctrl_33[10]; assign ch3_cmudividerdprioout_phy[`rpma_doublewidth_tx_DP_TXPMA_IDX_0] = ch3_out_chnl_ctrl_33[10]; assign ch4_cmudividerdprioout_phy[`rpma_doublewidth_tx_DP_TXPMA_IDX_0] = ch4_out_chnl_ctrl_33[10]; assign ch5_cmudividerdprioout_phy[`rpma_doublewidth_tx_DP_TXPMA_IDX_0] = ch5_out_chnl_ctrl_33[10]; assign ch0_cmudividerdprioout_phy[`rcgb_m_sel_DP_TXPMA_IDX_1 : `rcgb_m_sel_DP_TXPMA_IDX_0] = ch0_out_chnl_ctrl_33[12:11]; assign ch1_cmudividerdprioout_phy[`rcgb_m_sel_DP_TXPMA_IDX_1 : `rcgb_m_sel_DP_TXPMA_IDX_0] = ch1_out_chnl_ctrl_33[12:11]; assign ch2_cmudividerdprioout_phy[`rcgb_m_sel_DP_TXPMA_IDX_1 : `rcgb_m_sel_DP_TXPMA_IDX_0] = ch2_out_chnl_ctrl_33[12:11]; assign ch3_cmudividerdprioout_phy[`rcgb_m_sel_DP_TXPMA_IDX_1 : `rcgb_m_sel_DP_TXPMA_IDX_0] = ch3_out_chnl_ctrl_33[12:11]; assign ch4_cmudividerdprioout_phy[`rcgb_m_sel_DP_TXPMA_IDX_1 : `rcgb_m_sel_DP_TXPMA_IDX_0] = ch4_out_chnl_ctrl_33[12:11]; assign ch5_cmudividerdprioout_phy[`rcgb_m_sel_DP_TXPMA_IDX_1 : `rcgb_m_sel_DP_TXPMA_IDX_0] = ch5_out_chnl_ctrl_33[12:11]; assign ch0_cmudividerdprioout_phy[`rcgb_cmu_sel_DP_TXPMA_IDX_0] = ch0_out_chnl_ctrl_33[13]; assign ch1_cmudividerdprioout_phy[`rcgb_cmu_sel_DP_TXPMA_IDX_0] = ch1_out_chnl_ctrl_33[13]; assign ch2_cmudividerdprioout_phy[`rcgb_cmu_sel_DP_TXPMA_IDX_0] = ch2_out_chnl_ctrl_33[13]; assign ch3_cmudividerdprioout_phy[`rcgb_cmu_sel_DP_TXPMA_IDX_0] = ch3_out_chnl_ctrl_33[13]; assign ch4_cmudividerdprioout_phy[`rcgb_cmu_sel_DP_TXPMA_IDX_0] = ch4_out_chnl_ctrl_33[13]; assign ch5_cmudividerdprioout_phy[`rcgb_cmu_sel_DP_TXPMA_IDX_0] = ch5_out_chnl_ctrl_33[13]; // TX_PMA portion // bit[7] goes to rx_pma assign ch0_txpmadprioout_phy[`rcgb_x_en_DP_TXPMA_IDX_1 : `rcgb_delay_sel_DP_TXPMA_IDX_0] = ch0_out_chnl_ctrl_33[15:8]; assign ch1_txpmadprioout_phy[`rcgb_x_en_DP_TXPMA_IDX_1 : `rcgb_delay_sel_DP_TXPMA_IDX_0] = ch1_out_chnl_ctrl_33[15:8]; assign ch2_txpmadprioout_phy[`rcgb_x_en_DP_TXPMA_IDX_1 : `rcgb_delay_sel_DP_TXPMA_IDX_0] = ch2_out_chnl_ctrl_33[15:8]; assign ch3_txpmadprioout_phy[`rcgb_x_en_DP_TXPMA_IDX_1 : `rcgb_delay_sel_DP_TXPMA_IDX_0] = ch3_out_chnl_ctrl_33[15:8]; assign ch4_txpmadprioout_phy[`rcgb_x_en_DP_TXPMA_IDX_1 : `rcgb_delay_sel_DP_TXPMA_IDX_0] = ch4_out_chnl_ctrl_33[15:8]; assign ch5_txpmadprioout_phy[`rcgb_x_en_DP_TXPMA_IDX_1 : `rcgb_delay_sel_DP_TXPMA_IDX_0] = ch5_out_chnl_ctrl_33[15:8]; // this bit is from table_40 (rx_pma) bit[15] //assign ch0_txpmadprioout_phy[`rs_lpbk_DP_TXPMA_IDX_0] = ch0_out_chnl_ctrl_33[7]; assign ch0_txpmadprioout_phy[`rdynamic_sw_DP_TXPMA_IDX_0 : `reserved_0_TB33_DP_TXPMA_IDX_0] = ch0_out_chnl_ctrl_33[6:0]; assign ch1_txpmadprioout_phy[`rdynamic_sw_DP_TXPMA_IDX_0 : `reserved_0_TB33_DP_TXPMA_IDX_0] = ch1_out_chnl_ctrl_33[6:0]; assign ch2_txpmadprioout_phy[`rdynamic_sw_DP_TXPMA_IDX_0 : `reserved_0_TB33_DP_TXPMA_IDX_0] = ch2_out_chnl_ctrl_33[6:0]; assign ch3_txpmadprioout_phy[`rdynamic_sw_DP_TXPMA_IDX_0 : `reserved_0_TB33_DP_TXPMA_IDX_0] = ch3_out_chnl_ctrl_33[6:0]; assign ch4_txpmadprioout_phy[`rdynamic_sw_DP_TXPMA_IDX_0 : `reserved_0_TB33_DP_TXPMA_IDX_0] = ch4_out_chnl_ctrl_33[6:0]; assign ch5_txpmadprioout_phy[`rdynamic_sw_DP_TXPMA_IDX_0 : `reserved_0_TB33_DP_TXPMA_IDX_0] = ch5_out_chnl_ctrl_33[6:0]; // PLL portion - rx_cdr needs dynamic_sw for gating // For x4 gen2: there is no channel clock divider so one has to use centrl_clk_div (to get init_) // For HIP genx1: centrl clk div sets enable_dynamic_divider = true and tied rate=1 (293245) - incompatible with rx_pll // using centrl clk_div data in x4 and chl_div in x1 - here cmu_out_centrl_global[0] = rx[0].rindv_rx assign ch0_rxplldprioout_phy[`rdynamic_sw_DP_PLL_IDX_0] = (cmu_out_centrl_global_1[0] === 1'b0) ? ch4_out_chnl_ctrl_33[6] : ch0_out_chnl_ctrl_33[6]; assign ch1_rxplldprioout_phy[`rdynamic_sw_DP_PLL_IDX_0] = (cmu_out_centrl_global_1[0] === 1'b0) ? ch4_out_chnl_ctrl_33[6] : ch1_out_chnl_ctrl_33[6]; assign ch2_rxplldprioout_phy[`rdynamic_sw_DP_PLL_IDX_0] = (cmu_out_centrl_global_1[0] === 1'b0) ? ch4_out_chnl_ctrl_33[6] : ch2_out_chnl_ctrl_33[6]; assign ch3_rxplldprioout_phy[`rdynamic_sw_DP_PLL_IDX_0] = (cmu_out_centrl_global_1[0] === 1'b0) ? ch4_out_chnl_ctrl_33[6] : ch3_out_chnl_ctrl_33[6]; // not needed below if we do not switch rx_cdr_pll into txpll assign ch4_rxtxplldprioout_phy[`rdynamic_sw_DP_PLL_IDX_0] = ch4_out_chnl_ctrl_33[6]; assign ch5_rxtxplldprioout_phy[`rdynamic_sw_DP_PLL_IDX_0] = ch5_out_chnl_ctrl_33[6]; // ---------------------------------------------------------------------------------------------------------------- // Manual section - inputs: due to tx_pma and clk_divider atoms share same DPRIO word // ---------------------------------------------------------------------------------------------------------------- // Input: portion of CLOCK_DIVIDER in table 33 assign ch0_in_chnl_ctrl_33[6] = ch0_cmudividerdprioin_phy[`rdynamic_sw_DP_TXPMA_IDX_0] ; assign ch1_in_chnl_ctrl_33[6] = ch1_cmudividerdprioin_phy[`rdynamic_sw_DP_TXPMA_IDX_0] ; assign ch2_in_chnl_ctrl_33[6] = ch2_cmudividerdprioin_phy[`rdynamic_sw_DP_TXPMA_IDX_0] ; assign ch3_in_chnl_ctrl_33[6] = ch3_cmudividerdprioin_phy[`rdynamic_sw_DP_TXPMA_IDX_0] ; assign ch4_in_chnl_ctrl_33[6] = ch4_cmudividerdprioin_phy[`rdynamic_sw_DP_TXPMA_IDX_0] ; assign ch5_in_chnl_ctrl_33[6] = ch5_cmudividerdprioin_phy[`rdynamic_sw_DP_TXPMA_IDX_0] ; assign ch0_in_chnl_ctrl_33[12:11] = ch0_cmudividerdprioin_phy[`rcgb_m_sel_DP_TXPMA_IDX_1 : `rcgb_m_sel_DP_TXPMA_IDX_0] ; assign ch1_in_chnl_ctrl_33[12:11] = ch1_cmudividerdprioin_phy[`rcgb_m_sel_DP_TXPMA_IDX_1 : `rcgb_m_sel_DP_TXPMA_IDX_0] ; assign ch2_in_chnl_ctrl_33[12:11] = ch2_cmudividerdprioin_phy[`rcgb_m_sel_DP_TXPMA_IDX_1 : `rcgb_m_sel_DP_TXPMA_IDX_0] ; assign ch3_in_chnl_ctrl_33[12:11] = ch3_cmudividerdprioin_phy[`rcgb_m_sel_DP_TXPMA_IDX_1 : `rcgb_m_sel_DP_TXPMA_IDX_0] ; assign ch4_in_chnl_ctrl_33[12:11] = ch4_cmudividerdprioin_phy[`rcgb_m_sel_DP_TXPMA_IDX_1 : `rcgb_m_sel_DP_TXPMA_IDX_0] ; assign ch5_in_chnl_ctrl_33[12:11] = ch5_cmudividerdprioin_phy[`rcgb_m_sel_DP_TXPMA_IDX_1 : `rcgb_m_sel_DP_TXPMA_IDX_0] ; // Handled in inclk_select manual section of clock_div //assign ch0_in_chnl_ctrl_33[13] = ch0_cmudividerdprioin_phy[`rcgb_cmu_sel_DP_TXPMA_IDX_0] ; //assign ch1_in_chnl_ctrl_33[13] = ch1_cmudividerdprioin_phy[`rcgb_cmu_sel_DP_TXPMA_IDX_0] ; //assign ch2_in_chnl_ctrl_33[13] = ch2_cmudividerdprioin_phy[`rcgb_cmu_sel_DP_TXPMA_IDX_0] ; //assign ch3_in_chnl_ctrl_33[13] = ch3_cmudividerdprioin_phy[`rcgb_cmu_sel_DP_TXPMA_IDX_0] ; //assign ch4_in_chnl_ctrl_33[13] = ch4_cmudividerdprioin_phy[`rcgb_cmu_sel_DP_TXPMA_IDX_0] ; //assign ch5_in_chnl_ctrl_33[13] = ch5_cmudividerdprioin_phy[`rcgb_cmu_sel_DP_TXPMA_IDX_0] ; // Input: portion of TX_PMA in table 33 assign ch0_in_chnl_ctrl_33[3:0] = ch0_txpmadprioin_phy[`reserved_0_TB33_DP_TXPMA_IDX_3 : `reserved_0_TB33_DP_TXPMA_IDX_0]; assign ch1_in_chnl_ctrl_33[3:0] = ch1_txpmadprioin_phy[`reserved_0_TB33_DP_TXPMA_IDX_3 : `reserved_0_TB33_DP_TXPMA_IDX_0]; assign ch2_in_chnl_ctrl_33[3:0] = ch2_txpmadprioin_phy[`reserved_0_TB33_DP_TXPMA_IDX_3 : `reserved_0_TB33_DP_TXPMA_IDX_0]; assign ch3_in_chnl_ctrl_33[3:0] = ch3_txpmadprioin_phy[`reserved_0_TB33_DP_TXPMA_IDX_3 : `reserved_0_TB33_DP_TXPMA_IDX_0]; assign ch4_in_chnl_ctrl_33[3:0] = ch4_txpmadprioin_phy[`reserved_0_TB33_DP_TXPMA_IDX_3 : `reserved_0_TB33_DP_TXPMA_IDX_0]; assign ch5_in_chnl_ctrl_33[3:0] = ch5_txpmadprioin_phy[`reserved_0_TB33_DP_TXPMA_IDX_3 : `reserved_0_TB33_DP_TXPMA_IDX_0]; assign ch0_in_chnl_ctrl_33[4] = ch0_txpmadprioin_phy[`rtx_cgb_pdb_DP_TXPMA_IDX_0]; assign ch1_in_chnl_ctrl_33[4] = ch1_txpmadprioin_phy[`rtx_cgb_pdb_DP_TXPMA_IDX_0]; assign ch2_in_chnl_ctrl_33[4] = ch2_txpmadprioin_phy[`rtx_cgb_pdb_DP_TXPMA_IDX_0]; assign ch3_in_chnl_ctrl_33[4] = ch3_txpmadprioin_phy[`rtx_cgb_pdb_DP_TXPMA_IDX_0]; assign ch4_in_chnl_ctrl_33[4] = ch4_txpmadprioin_phy[`rtx_cgb_pdb_DP_TXPMA_IDX_0]; assign ch5_in_chnl_ctrl_33[4] = ch5_txpmadprioin_phy[`rtx_cgb_pdb_DP_TXPMA_IDX_0]; assign ch0_in_chnl_ctrl_33[5] = ch0_txpmadprioin_phy[`rpclksel_DP_TXPMA_IDX_0]; assign ch1_in_chnl_ctrl_33[5] = ch1_txpmadprioin_phy[`rpclksel_DP_TXPMA_IDX_0]; assign ch2_in_chnl_ctrl_33[5] = ch2_txpmadprioin_phy[`rpclksel_DP_TXPMA_IDX_0]; assign ch3_in_chnl_ctrl_33[5] = ch3_txpmadprioin_phy[`rpclksel_DP_TXPMA_IDX_0]; assign ch4_in_chnl_ctrl_33[5] = ch4_txpmadprioin_phy[`rpclksel_DP_TXPMA_IDX_0]; assign ch5_in_chnl_ctrl_33[5] = ch5_txpmadprioin_phy[`rpclksel_DP_TXPMA_IDX_0]; // clock divide[6] // allow_serial_loopback mapped into rx_pma.RRX_S_LPBK_RXPMA_IDX - ICD XLS cram doc error assign ch0_in_chnl_ctrl_33[7] = ch0_rxpmadprioin_phy[`rs_lpbk_DP_RXPMA_IDX]; assign ch1_in_chnl_ctrl_33[7] = ch1_rxpmadprioin_phy[`rs_lpbk_DP_RXPMA_IDX]; assign ch2_in_chnl_ctrl_33[7] = ch2_rxpmadprioin_phy[`rs_lpbk_DP_RXPMA_IDX]; assign ch3_in_chnl_ctrl_33[7] = ch3_rxpmadprioin_phy[`rs_lpbk_DP_RXPMA_IDX]; assign ch4_in_chnl_ctrl_33[7] = ch4_rxpmadprioin_phy[`rs_lpbk_DP_RXPMA_IDX]; assign ch5_in_chnl_ctrl_33[7] = ch5_rxpmadprioin_phy[`rs_lpbk_DP_RXPMA_IDX]; assign ch0_in_chnl_ctrl_33[8] = ch0_txpmadprioin_phy[`rcgb_delay_sel_DP_TXPMA_IDX_0]; assign ch1_in_chnl_ctrl_33[8] = ch1_txpmadprioin_phy[`rcgb_delay_sel_DP_TXPMA_IDX_0]; assign ch2_in_chnl_ctrl_33[8] = ch2_txpmadprioin_phy[`rcgb_delay_sel_DP_TXPMA_IDX_0]; assign ch3_in_chnl_ctrl_33[8] = ch3_txpmadprioin_phy[`rcgb_delay_sel_DP_TXPMA_IDX_0]; assign ch4_in_chnl_ctrl_33[8] = ch4_txpmadprioin_phy[`rcgb_delay_sel_DP_TXPMA_IDX_0]; assign ch5_in_chnl_ctrl_33[8] = ch5_txpmadprioin_phy[`rcgb_delay_sel_DP_TXPMA_IDX_0]; assign ch0_in_chnl_ctrl_33[9] = ch0_txpmadprioin_phy[`rpmadwidth_tx_DP_TXPMA_IDX_0]; assign ch1_in_chnl_ctrl_33[9] = ch1_txpmadprioin_phy[`rpmadwidth_tx_DP_TXPMA_IDX_0]; assign ch2_in_chnl_ctrl_33[9] = ch2_txpmadprioin_phy[`rpmadwidth_tx_DP_TXPMA_IDX_0]; assign ch3_in_chnl_ctrl_33[9] = ch3_txpmadprioin_phy[`rpmadwidth_tx_DP_TXPMA_IDX_0]; // spr 317392 - when clock divider is used as global (x4) but corresponding tx_pma not available // ch4, 5 <--> with corresponding CMU_CTRL registers (in this case table 59) assign ch4_in_chnl_ctrl_33[9] = ch4_cmudividerdprioin_phy[`rpmadwidth_tx_DP_TXPMA_IDX_0]; assign ch5_in_chnl_ctrl_33[9] = ch5_cmudividerdprioin_phy[`rpmadwidth_tx_DP_TXPMA_IDX_0]; assign ch0_in_chnl_ctrl_33[10] = ch0_txpmadprioin_phy[`rpma_doublewidth_tx_DP_TXPMA_IDX_0]; assign ch1_in_chnl_ctrl_33[10] = ch1_txpmadprioin_phy[`rpma_doublewidth_tx_DP_TXPMA_IDX_0]; assign ch2_in_chnl_ctrl_33[10] = ch2_txpmadprioin_phy[`rpma_doublewidth_tx_DP_TXPMA_IDX_0]; assign ch3_in_chnl_ctrl_33[10] = ch3_txpmadprioin_phy[`rpma_doublewidth_tx_DP_TXPMA_IDX_0]; // same as rpmadwidth assign ch4_in_chnl_ctrl_33[10] = ch4_cmudividerdprioin_phy[`rpma_doublewidth_tx_DP_TXPMA_IDX_0]; assign ch5_in_chnl_ctrl_33[10] = ch5_cmudividerdprioin_phy[`rpma_doublewidth_tx_DP_TXPMA_IDX_0]; // clock_divider[12:11] // clock_divider[13] // Handled in clkin_select manual section next //assign ch0_in_chnl_ctrl_33[15:14] = ch0_txpmadprioin_phy[`rcgb_x_en_DP_TXPMA_IDX_1 : `rcgb_x_en_DP_TXPMA_IDX_0]; //assign ch1_in_chnl_ctrl_33[15:14] = ch1_txpmadprioin_phy[`rcgb_x_en_DP_TXPMA_IDX_1 : `rcgb_x_en_DP_TXPMA_IDX_0]; //assign ch2_in_chnl_ctrl_33[15:14] = ch2_txpmadprioin_phy[`rcgb_x_en_DP_TXPMA_IDX_1 : `rcgb_x_en_DP_TXPMA_IDX_0]; //assign ch3_in_chnl_ctrl_33[15:14] = ch3_txpmadprioin_phy[`rcgb_x_en_DP_TXPMA_IDX_1 : `rcgb_x_en_DP_TXPMA_IDX_0]; //assign ch4_in_chnl_ctrl_33[15:14] = ch4_txpmadprioin_phy[`rcgb_x_en_DP_TXPMA_IDX_1 : `rcgb_x_en_DP_TXPMA_IDX_0]; //assign ch5_in_chnl_ctrl_33[15:14] = ch5_txpmadprioin_phy[`rcgb_x_en_DP_TXPMA_IDX_1 : `rcgb_x_en_DP_TXPMA_IDX_0]; // Table34: PMA Per Channel TX Control Register 7 for Channel 0 // rrevlb_sw is modeled at rx_pma assign ch0_in_chnl_ctrl_34[10] = ch0_rxpmadprioin_phy[`rrevlb_sw_DP_RXPMA_IDX]; assign ch1_in_chnl_ctrl_34[10] = ch1_rxpmadprioin_phy[`rrevlb_sw_DP_RXPMA_IDX]; assign ch2_in_chnl_ctrl_34[10] = ch2_rxpmadprioin_phy[`rrevlb_sw_DP_RXPMA_IDX]; assign ch3_in_chnl_ctrl_34[10] = ch3_rxpmadprioin_phy[`rrevlb_sw_DP_RXPMA_IDX]; assign ch4_in_chnl_ctrl_34[10] = ch4_rxpmadprioin_phy[`rrevlb_sw_DP_RXPMA_IDX]; assign ch5_in_chnl_ctrl_34[10] = ch5_rxpmadprioin_phy[`rrevlb_sw_DP_RXPMA_IDX]; // Table 40: // bit[15] goes to TX_PMA - moved to Manual section as this CRAM sends to TX_PMA // table40[15] = rcru_rlbk (revere_lpbk) using rs_lpbk_DP_IDX to map to tx_pam.rtx_rlpbk RTL name assign ch0_in_chnl_ctrl_40[15] = ch0_txpmadprioin_phy[`rs_lpbk_DP_TXPMA_IDX_0]; assign ch1_in_chnl_ctrl_40[15] = ch1_txpmadprioin_phy[`rs_lpbk_DP_TXPMA_IDX_0]; assign ch2_in_chnl_ctrl_40[15] = ch2_txpmadprioin_phy[`rs_lpbk_DP_TXPMA_IDX_0]; assign ch3_in_chnl_ctrl_40[15] = ch3_txpmadprioin_phy[`rs_lpbk_DP_TXPMA_IDX_0]; assign ch4_in_chnl_ctrl_40[15] = ch4_txpmadprioin_phy[`rs_lpbk_DP_TXPMA_IDX_0]; assign ch5_in_chnl_ctrl_40[15] = ch5_txpmadprioin_phy[`rs_lpbk_DP_TXPMA_IDX_0]; // rest bits from RX_PLL assign ch0_in_chnl_ctrl_40[14:0] = ch0_rxplldprioin_phy[`rcru_lst_DP_PLL_IDX_3 : `reserved_0_TB40_DP_PLL_IDX_0]; assign ch1_in_chnl_ctrl_40[14:0] = ch1_rxplldprioin_phy[`rcru_lst_DP_PLL_IDX_3 : `reserved_0_TB40_DP_PLL_IDX_0]; assign ch2_in_chnl_ctrl_40[14:0] = ch2_rxplldprioin_phy[`rcru_lst_DP_PLL_IDX_3 : `reserved_0_TB40_DP_PLL_IDX_0]; assign ch3_in_chnl_ctrl_40[14:0] = ch3_rxplldprioin_phy[`rcru_lst_DP_PLL_IDX_3 : `reserved_0_TB40_DP_PLL_IDX_0]; assign ch4_in_chnl_ctrl_40[14:0] = ch4_rxtxplldprioin_phy[`rcru_lst_DP_PLL_IDX_3 : `reserved_0_TB40_DP_PLL_IDX_0]; assign ch5_in_chnl_ctrl_40[14:0] = ch5_rxtxplldprioin_phy[`rcru_lst_DP_PLL_IDX_3 : `reserved_0_TB40_DP_PLL_IDX_0]; // ---------------------------------------------------------------------------------------------------------------- // Manual section - inputs: only ch0 --> global CRAMs // ---------------------------------------------------------------------------------------------------------------- // Extra word in CMU (no correspondence in channel) - not modeled in MIF and SIM assign cmu0_in_centrl_ctrl_21 = 16'h0000; assign cmu1_in_centrl_ctrl_21 = 16'h0000; // global ctrl 0 - centrl_ctrl_43 - table 75 assign cmu_in_centrl_global_0 = 16'h0000; // global ctrl 1 - centrl_ctrl_44 assign cmu_in_centrl_global_1[15:8] = 8'h00; assign cmu_in_centrl_global_1[7] = ch0_txpcsdprioin_phy[`rendec_data_sel_tx_DP_TXPCS_IDX]; assign cmu_in_centrl_global_1[6] = ch0_rxpcsdprioin_phy[`rendec_data_sel_rx_DP_RXPCS_IDX]; assign cmu_in_centrl_global_1[5:3] = 3'b000; assign cmu_in_centrl_global_1[2] = ch0_rxpcsdprioin_phy[`rdeskewen_DP_RXPCS_IDX]; assign cmu_in_centrl_global_1[1] = ch0_txpcsdprioin_phy[`rindv_tx_DP_TXPCS_IDX]; assign cmu_in_centrl_global_1[0] = ch0_rxpcsdprioin_phy[`rindv_rx_DP_RXPCS_IDX]; // global ctrl 2 - centrl_ctrl_45 assign cmu_in_centrl_global_2[15] = ch4_cmudividerdprioin_phy[`rfreerun_centrl_DP_CLOCK_DIV_IDX]; assign cmu_in_centrl_global_2[14] = ch4_cmudividerdprioin_phy[`rcentrl_clk_sel_DP_CLOCK_DIV_IDX]; assign cmu_in_centrl_global_2[13] = ch4_cmudividerdprioin_phy[`rrefclk_out_div2_DP_CLOCK_DIV_IDX]; assign cmu_in_centrl_global_2[12:11] = 2'b00; assign cmu_in_centrl_global_2[10] = ch0_rxpcsdprioin_phy[`rdskposdisp_DP_RXPCS_IDX]; assign cmu_in_centrl_global_2[9:0] = 10'h000; // global ctrl 3 - centrl_ctrl_46 assign cmu_in_centrl_global_3[15:4] = 12'h000; assign cmu_in_centrl_global_3[3] = ch0_rxpcsdprioin_phy[`rmaster_rx_DP_RXPCS_IDX]; assign cmu_in_centrl_global_3[2] = ch0_rxpcsdprioin_phy[`rmaster_up_rx_DP_RXPCS_IDX]; assign cmu_in_centrl_global_3[1] = ch0_txpcsdprioin_phy[`rmaster_tx_DP_TXPCS_IDX]; assign cmu_in_centrl_global_3[0] = ch0_txpcsdprioin_phy[`rmaster_up_tx_DP_TXPCS_IDX]; //==================================================================== // Manually added code to handle PLL clock select = //==================================================================== // Table 34 - pll's pfd_clk_select ----------------------------------- // preparing inputs to index_cram_map assign pll0_init_pfd_clk_sel = ch0_rxplldprioin_logic[`PFD_CLK_SELECT_DP_PLL_IDX_3 : `PFD_CLK_SELECT_DP_PLL_IDX_0]; assign pll0_dp_riqclk_sel = ch0_out_chnl_ctrl_34[15:14]; assign pll0_dp_rrefclk_sel = ch0_out_chnl_ctrl_34[13:12]; // using outputs from index_cram_map assign ch0_rxplldprioout_phy[`PFD_CLK_SELECT_DP_PLL_IDX_3 : `PFD_CLK_SELECT_DP_PLL_IDX_0] = pll0_dp_pfd_clk_sel; assign ch0_in_chnl_ctrl_34[15:14] = pll0_csr_riqclk_sel; assign ch0_in_chnl_ctrl_34[13:12] = pll0_csr_rrefclk_sel; // preparing inputs to index_cram_map assign pll1_init_pfd_clk_sel = ch1_rxplldprioin_logic[`PFD_CLK_SELECT_DP_PLL_IDX_3 : `PFD_CLK_SELECT_DP_PLL_IDX_0]; assign pll1_dp_riqclk_sel = ch1_out_chnl_ctrl_34[15:14]; assign pll1_dp_rrefclk_sel = ch1_out_chnl_ctrl_34[13:12]; // using outputs from index_cram_map assign ch1_rxplldprioout_phy[`PFD_CLK_SELECT_DP_PLL_IDX_3 : `PFD_CLK_SELECT_DP_PLL_IDX_0] = pll1_dp_pfd_clk_sel; assign ch1_in_chnl_ctrl_34[15:14] = pll1_csr_riqclk_sel; assign ch1_in_chnl_ctrl_34[13:12] = pll1_csr_rrefclk_sel; // preparing inputs to index_cram_map assign pll2_init_pfd_clk_sel = ch2_rxplldprioin_logic[`PFD_CLK_SELECT_DP_PLL_IDX_3 : `PFD_CLK_SELECT_DP_PLL_IDX_0]; assign pll2_dp_riqclk_sel = ch2_out_chnl_ctrl_34[15:14]; assign pll2_dp_rrefclk_sel = ch2_out_chnl_ctrl_34[13:12]; // using outputs from index_cram_map assign ch2_rxplldprioout_phy[`PFD_CLK_SELECT_DP_PLL_IDX_3 : `PFD_CLK_SELECT_DP_PLL_IDX_0] = pll2_dp_pfd_clk_sel; assign ch2_in_chnl_ctrl_34[15:14] = pll2_csr_riqclk_sel; assign ch2_in_chnl_ctrl_34[13:12] = pll2_csr_rrefclk_sel; // preparing inputs to index_cram_map assign pll3_init_pfd_clk_sel = ch3_rxplldprioin_logic[`PFD_CLK_SELECT_DP_PLL_IDX_3 : `PFD_CLK_SELECT_DP_PLL_IDX_0]; assign pll3_dp_riqclk_sel = ch3_out_chnl_ctrl_34[15:14]; assign pll3_dp_rrefclk_sel = ch3_out_chnl_ctrl_34[13:12]; // using outputs from index_cram_map assign ch3_rxplldprioout_phy[`PFD_CLK_SELECT_DP_PLL_IDX_3 : `PFD_CLK_SELECT_DP_PLL_IDX_0] = pll3_dp_pfd_clk_sel; assign ch3_in_chnl_ctrl_34[15:14] = pll3_csr_riqclk_sel; assign ch3_in_chnl_ctrl_34[13:12] = pll3_csr_rrefclk_sel; // preparing inputs to index_cram_map assign pll4_init_pfd_clk_sel = ch4_rxtxplldprioin_logic[`PFD_CLK_SELECT_DP_PLL_IDX_3 : `PFD_CLK_SELECT_DP_PLL_IDX_0]; assign pll4_dp_riqclk_sel = ch4_out_chnl_ctrl_34[15:14]; assign pll4_dp_rrefclk_sel = ch4_out_chnl_ctrl_34[13:12]; // using outputs from index_cram_map assign ch4_rxtxplldprioout_phy[`PFD_CLK_SELECT_DP_PLL_IDX_3 : `PFD_CLK_SELECT_DP_PLL_IDX_0] = pll4_dp_pfd_clk_sel; assign ch4_in_chnl_ctrl_34[15:14] = pll4_csr_riqclk_sel; assign ch4_in_chnl_ctrl_34[13:12] = pll4_csr_rrefclk_sel; // preparing inputs to index_cram_map assign pll5_init_pfd_clk_sel = ch5_rxtxplldprioin_logic[`PFD_CLK_SELECT_DP_PLL_IDX_3 : `PFD_CLK_SELECT_DP_PLL_IDX_0]; assign pll5_dp_riqclk_sel = ch5_out_chnl_ctrl_34[15:14]; assign pll5_dp_rrefclk_sel = ch5_out_chnl_ctrl_34[13:12]; // using outputs from index_cram_map assign ch5_rxtxplldprioout_phy[`PFD_CLK_SELECT_DP_PLL_IDX_3 : `PFD_CLK_SELECT_DP_PLL_IDX_0] = pll5_dp_pfd_clk_sel; assign ch5_in_chnl_ctrl_34[15:14] = pll5_csr_riqclk_sel; assign ch5_in_chnl_ctrl_34[13:12] = pll5_csr_rrefclk_sel; //==================================================================== // Manually added code to handle TX PMA clock select = //==================================================================== // Table 33 - TX PMA's clkin_select --------------------------------- // preparing inputs to index_cram_map assign txpma0_init_clkin_sel = ch0_txpmadprioin_logic[`CLKIN_SELECT_DP_TXPMA_IDX_2 : `CLKIN_SELECT_DP_TXPMA_IDX_0]; assign txpma0_dp_rcgb_x_en = ch0_out_chnl_ctrl_33[15:14]; // using outputs from index_cram_map assign ch0_txpmadprioout_phy[`CLKIN_SELECT_DP_TXPMA_IDX_2 : `CLKIN_SELECT_DP_TXPMA_IDX_0] = txpma0_dp_clkin_sel; assign ch0_in_chnl_ctrl_33[15:14] = txpma0_csr_rcgb_x_en; // preparing inputs to index_cram_map assign txpma1_init_clkin_sel = ch1_txpmadprioin_logic[`CLKIN_SELECT_DP_TXPMA_IDX_2 : `CLKIN_SELECT_DP_TXPMA_IDX_0]; assign txpma1_dp_rcgb_x_en = ch1_out_chnl_ctrl_33[15:14]; // using outputs from index_cram_map assign ch1_txpmadprioout_phy[`CLKIN_SELECT_DP_TXPMA_IDX_2 : `CLKIN_SELECT_DP_TXPMA_IDX_0] = txpma1_dp_clkin_sel; assign ch1_in_chnl_ctrl_33[15:14] = txpma1_csr_rcgb_x_en; // preparing inputs to index_cram_map assign txpma2_init_clkin_sel = ch2_txpmadprioin_logic[`CLKIN_SELECT_DP_TXPMA_IDX_2 : `CLKIN_SELECT_DP_TXPMA_IDX_0]; assign txpma2_dp_rcgb_x_en = ch2_out_chnl_ctrl_33[15:14]; // using outputs from index_cram_map assign ch2_txpmadprioout_phy[`CLKIN_SELECT_DP_TXPMA_IDX_2 : `CLKIN_SELECT_DP_TXPMA_IDX_0] = txpma2_dp_clkin_sel; assign ch2_in_chnl_ctrl_33[15:14] = txpma2_csr_rcgb_x_en; // preparing inputs to index_cram_map assign txpma3_init_clkin_sel = ch3_txpmadprioin_logic[`CLKIN_SELECT_DP_TXPMA_IDX_2 : `CLKIN_SELECT_DP_TXPMA_IDX_0]; assign txpma3_dp_rcgb_x_en = ch3_out_chnl_ctrl_33[15:14]; // using outputs from index_cram_map assign ch3_txpmadprioout_phy[`CLKIN_SELECT_DP_TXPMA_IDX_2 : `CLKIN_SELECT_DP_TXPMA_IDX_0] = txpma3_dp_clkin_sel; assign ch3_in_chnl_ctrl_33[15:14] = txpma3_csr_rcgb_x_en; // preparing inputs to index_cram_map assign txpma4_init_clkin_sel = ch4_txpmadprioin_logic[`CLKIN_SELECT_DP_TXPMA_IDX_2 : `CLKIN_SELECT_DP_TXPMA_IDX_0]; assign txpma4_dp_rcgb_x_en = ch4_out_chnl_ctrl_33[15:14]; // using outputs from index_cram_map assign ch4_txpmadprioout_phy[`CLKIN_SELECT_DP_TXPMA_IDX_2 : `CLKIN_SELECT_DP_TXPMA_IDX_0] = txpma4_dp_clkin_sel; assign ch4_in_chnl_ctrl_33[15:14] = txpma4_csr_rcgb_x_en; // preparing inputs to index_cram_map assign txpma5_init_clkin_sel = ch5_txpmadprioin_logic[`CLKIN_SELECT_DP_TXPMA_IDX_2 : `CLKIN_SELECT_DP_TXPMA_IDX_0]; assign txpma5_dp_rcgb_x_en = ch5_out_chnl_ctrl_33[15:14]; // using outputs from index_cram_map assign ch5_txpmadprioout_phy[`CLKIN_SELECT_DP_TXPMA_IDX_2 : `CLKIN_SELECT_DP_TXPMA_IDX_0] = txpma5_dp_clkin_sel; assign ch5_in_chnl_ctrl_33[15:14] = txpma5_csr_rcgb_x_en; //==================================================================== // Manually added code to handle clkdiv PLL0/1 select = //==================================================================== // Table 33 - clock divider's inclk_select -------------------------- // preparing inputs to index_cram_map assign clkdiv0_init_inclk_select = ch0_cmudividerdprioin_logic[`INCLK_SELECT_DP_CLOCK_DIV_IDX]; assign clkdiv0_dp_rcgb_cmu_sel = ch0_out_chnl_ctrl_33[13]; // using outputs from index_cram_map assign ch0_cmudividerdprioout_phy[`INCLK_SELECT_DP_CLOCK_DIV_IDX] = clkdiv0_dp_inclk_select; assign ch0_in_chnl_ctrl_33[13] = clkdiv0_csr_rcgb_cmu_sel; // preparing inputs to index_cram_map assign clkdiv1_init_inclk_select = ch1_cmudividerdprioin_logic[`INCLK_SELECT_DP_CLOCK_DIV_IDX]; assign clkdiv1_dp_rcgb_cmu_sel = ch1_out_chnl_ctrl_33[13]; // using outputs from index_cram_map assign ch1_cmudividerdprioout_phy[`INCLK_SELECT_DP_CLOCK_DIV_IDX] = clkdiv1_dp_inclk_select; assign ch1_in_chnl_ctrl_33[13] = clkdiv1_csr_rcgb_cmu_sel; // preparing inputs to index_cram_map assign clkdiv2_init_inclk_select = ch2_cmudividerdprioin_logic[`INCLK_SELECT_DP_CLOCK_DIV_IDX]; assign clkdiv2_dp_rcgb_cmu_sel = ch2_out_chnl_ctrl_33[13]; // using outputs from index_cram_map assign ch2_cmudividerdprioout_phy[`INCLK_SELECT_DP_CLOCK_DIV_IDX] = clkdiv2_dp_inclk_select; assign ch2_in_chnl_ctrl_33[13] = clkdiv2_csr_rcgb_cmu_sel; // preparing inputs to index_cram_map assign clkdiv3_init_inclk_select = ch3_cmudividerdprioin_logic[`INCLK_SELECT_DP_CLOCK_DIV_IDX]; assign clkdiv3_dp_rcgb_cmu_sel = ch3_out_chnl_ctrl_33[13]; // using outputs from index_cram_map assign ch3_cmudividerdprioout_phy[`INCLK_SELECT_DP_CLOCK_DIV_IDX] = clkdiv3_dp_inclk_select; assign ch3_in_chnl_ctrl_33[13] = clkdiv3_csr_rcgb_cmu_sel; // preparing inputs to index_cram_map assign clkdiv4_init_inclk_select = ch4_cmudividerdprioin_logic[`INCLK_SELECT_DP_CLOCK_DIV_IDX]; assign clkdiv4_dp_rcgb_cmu_sel = ch4_out_chnl_ctrl_33[13]; // using outputs from index_cram_map assign ch4_cmudividerdprioout_phy[`INCLK_SELECT_DP_CLOCK_DIV_IDX] = clkdiv4_dp_inclk_select; assign ch4_in_chnl_ctrl_33[13] = clkdiv4_csr_rcgb_cmu_sel; // preparing inputs to index_cram_map assign clkdiv5_init_inclk_select = ch5_cmudividerdprioin_logic[`INCLK_SELECT_DP_CLOCK_DIV_IDX]; assign clkdiv5_dp_rcgb_cmu_sel = ch5_out_chnl_ctrl_33[13]; // using outputs from index_cram_map assign ch5_cmudividerdprioout_phy[`INCLK_SELECT_DP_CLOCK_DIV_IDX] = clkdiv5_dp_inclk_select; assign ch5_in_chnl_ctrl_33[13] = clkdiv5_csr_rcgb_cmu_sel; //==================================================================== // Instantiating the map resolver = //==================================================================== stratixiv_hssi_cmu_dprio_map_index m_clksel_index_cram_map ( .pll0_init_pfd_clk_sel (pll0_init_pfd_clk_sel), // input .pll0_csr_riqclk_sel (pll0_csr_riqclk_sel), .pll0_csr_rrefclk_sel (pll0_csr_rrefclk_sel), .pll0_dp_riqclk_sel (pll0_dp_riqclk_sel), // input .pll0_dp_rrefclk_sel (pll0_dp_rrefclk_sel), // input .pll0_dp_pfd_clk_sel (pll0_dp_pfd_clk_sel), .pll1_init_pfd_clk_sel (pll1_init_pfd_clk_sel), // input .pll1_csr_riqclk_sel (pll1_csr_riqclk_sel), .pll1_csr_rrefclk_sel (pll1_csr_rrefclk_sel), .pll1_dp_riqclk_sel (pll1_dp_riqclk_sel), // input .pll1_dp_rrefclk_sel (pll1_dp_rrefclk_sel), // input .pll1_dp_pfd_clk_sel (pll1_dp_pfd_clk_sel), .pll2_init_pfd_clk_sel (pll2_init_pfd_clk_sel), // input .pll2_csr_riqclk_sel (pll2_csr_riqclk_sel), .pll2_csr_rrefclk_sel (pll2_csr_rrefclk_sel), .pll2_dp_riqclk_sel (pll2_dp_riqclk_sel), // input .pll2_dp_rrefclk_sel (pll2_dp_rrefclk_sel), // input .pll2_dp_pfd_clk_sel (pll2_dp_pfd_clk_sel), .pll3_init_pfd_clk_sel (pll3_init_pfd_clk_sel), // input .pll3_csr_riqclk_sel (pll3_csr_riqclk_sel), .pll3_csr_rrefclk_sel (pll3_csr_rrefclk_sel), .pll3_dp_riqclk_sel (pll3_dp_riqclk_sel), // input .pll3_dp_rrefclk_sel (pll3_dp_rrefclk_sel), // input .pll3_dp_pfd_clk_sel (pll3_dp_pfd_clk_sel), .pll4_init_pfd_clk_sel (pll4_init_pfd_clk_sel), // input .pll4_csr_riqclk_sel (pll4_csr_riqclk_sel), .pll4_csr_rrefclk_sel (pll4_csr_rrefclk_sel), .pll4_dp_riqclk_sel (pll4_dp_riqclk_sel), // input .pll4_dp_rrefclk_sel (pll4_dp_rrefclk_sel), // input .pll4_dp_pfd_clk_sel (pll4_dp_pfd_clk_sel), .pll5_init_pfd_clk_sel (pll5_init_pfd_clk_sel), // input .pll5_csr_riqclk_sel (pll5_csr_riqclk_sel), .pll5_csr_rrefclk_sel (pll5_csr_rrefclk_sel), .pll5_dp_riqclk_sel (pll5_dp_riqclk_sel), // input .pll5_dp_rrefclk_sel (pll5_dp_rrefclk_sel), // input .pll5_dp_pfd_clk_sel (pll5_dp_pfd_clk_sel), .txpma0_init_clkin_sel (txpma0_init_clkin_sel), // input .txpma0_csr_rcgb_x_en (txpma0_csr_rcgb_x_en), .txpma0_dp_rcgb_x_en (txpma0_dp_rcgb_x_en), // input .txpma0_dp_clkin_sel (txpma0_dp_clkin_sel), .txpma1_init_clkin_sel (txpma1_init_clkin_sel), // input .txpma1_csr_rcgb_x_en (txpma1_csr_rcgb_x_en), .txpma1_dp_rcgb_x_en (txpma1_dp_rcgb_x_en), // input .txpma1_dp_clkin_sel (txpma1_dp_clkin_sel), .txpma2_init_clkin_sel (txpma2_init_clkin_sel), // input .txpma2_csr_rcgb_x_en (txpma2_csr_rcgb_x_en), .txpma2_dp_rcgb_x_en (txpma2_dp_rcgb_x_en), // input .txpma2_dp_clkin_sel (txpma2_dp_clkin_sel), .txpma3_init_clkin_sel (txpma3_init_clkin_sel), // input .txpma3_csr_rcgb_x_en (txpma3_csr_rcgb_x_en), .txpma3_dp_rcgb_x_en (txpma3_dp_rcgb_x_en), // input .txpma3_dp_clkin_sel (txpma3_dp_clkin_sel), .txpma4_init_clkin_sel (txpma4_init_clkin_sel), // input .txpma4_csr_rcgb_x_en (txpma4_csr_rcgb_x_en), .txpma4_dp_rcgb_x_en (txpma4_dp_rcgb_x_en), // input .txpma4_dp_clkin_sel (txpma4_dp_clkin_sel), .txpma5_init_clkin_sel (txpma5_init_clkin_sel), // input .txpma5_csr_rcgb_x_en (txpma5_csr_rcgb_x_en), .txpma5_dp_rcgb_x_en (txpma5_dp_rcgb_x_en), // input .txpma5_dp_clkin_sel (txpma5_dp_clkin_sel) , .clkdiv0_init_inclk_select (clkdiv0_init_inclk_select), .clkdiv0_csr_rcgb_cmu_sel (clkdiv0_csr_rcgb_cmu_sel), .clkdiv0_dp_rcgb_cmu_sel (clkdiv0_dp_rcgb_cmu_sel), .clkdiv0_dp_inclk_select (clkdiv0_dp_inclk_select), .clkdiv1_init_inclk_select (clkdiv1_init_inclk_select), .clkdiv1_csr_rcgb_cmu_sel (clkdiv1_csr_rcgb_cmu_sel), .clkdiv1_dp_rcgb_cmu_sel (clkdiv1_dp_rcgb_cmu_sel), .clkdiv1_dp_inclk_select (clkdiv1_dp_inclk_select), .clkdiv2_init_inclk_select (clkdiv2_init_inclk_select), .clkdiv2_csr_rcgb_cmu_sel (clkdiv2_csr_rcgb_cmu_sel), .clkdiv2_dp_rcgb_cmu_sel (clkdiv2_dp_rcgb_cmu_sel), .clkdiv2_dp_inclk_select (clkdiv2_dp_inclk_select), .clkdiv3_init_inclk_select (clkdiv3_init_inclk_select), .clkdiv3_csr_rcgb_cmu_sel (clkdiv3_csr_rcgb_cmu_sel), .clkdiv3_dp_rcgb_cmu_sel (clkdiv3_dp_rcgb_cmu_sel), .clkdiv3_dp_inclk_select (clkdiv3_dp_inclk_select), .clkdiv4_init_inclk_select (clkdiv4_init_inclk_select), .clkdiv4_csr_rcgb_cmu_sel (clkdiv4_csr_rcgb_cmu_sel), .clkdiv4_dp_rcgb_cmu_sel (clkdiv4_dp_rcgb_cmu_sel), .clkdiv4_dp_inclk_select (clkdiv4_dp_inclk_select), .clkdiv5_init_inclk_select (clkdiv5_init_inclk_select), .clkdiv5_csr_rcgb_cmu_sel (clkdiv5_csr_rcgb_cmu_sel), .clkdiv5_dp_rcgb_cmu_sel (clkdiv5_dp_rcgb_cmu_sel), .clkdiv5_dp_inclk_select (clkdiv5_dp_inclk_select) ); defparam m_clksel_index_cram_map.clkdiv0_inclk0_logical_to_physical_mapping = clkdiv0_inclk0_logical_to_physical_mapping; defparam m_clksel_index_cram_map.clkdiv0_inclk1_logical_to_physical_mapping = clkdiv0_inclk1_logical_to_physical_mapping; defparam m_clksel_index_cram_map.clkdiv1_inclk0_logical_to_physical_mapping = clkdiv1_inclk0_logical_to_physical_mapping; defparam m_clksel_index_cram_map.clkdiv1_inclk1_logical_to_physical_mapping = clkdiv1_inclk1_logical_to_physical_mapping; defparam m_clksel_index_cram_map.clkdiv2_inclk0_logical_to_physical_mapping = clkdiv2_inclk0_logical_to_physical_mapping; defparam m_clksel_index_cram_map.clkdiv2_inclk1_logical_to_physical_mapping = clkdiv2_inclk1_logical_to_physical_mapping; defparam m_clksel_index_cram_map.clkdiv3_inclk0_logical_to_physical_mapping = clkdiv3_inclk0_logical_to_physical_mapping; defparam m_clksel_index_cram_map.clkdiv3_inclk1_logical_to_physical_mapping = clkdiv3_inclk1_logical_to_physical_mapping; defparam m_clksel_index_cram_map.clkdiv4_inclk0_logical_to_physical_mapping = clkdiv4_inclk0_logical_to_physical_mapping; defparam m_clksel_index_cram_map.clkdiv4_inclk1_logical_to_physical_mapping = clkdiv4_inclk1_logical_to_physical_mapping; defparam m_clksel_index_cram_map.clkdiv5_inclk0_logical_to_physical_mapping = clkdiv5_inclk0_logical_to_physical_mapping; defparam m_clksel_index_cram_map.clkdiv5_inclk1_logical_to_physical_mapping = clkdiv5_inclk1_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll0_inclk0_logical_to_physical_mapping = pll0_inclk0_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll0_inclk1_logical_to_physical_mapping = pll0_inclk1_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll0_inclk2_logical_to_physical_mapping = pll0_inclk2_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll0_inclk3_logical_to_physical_mapping = pll0_inclk3_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll0_inclk4_logical_to_physical_mapping = pll0_inclk4_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll0_inclk5_logical_to_physical_mapping = pll0_inclk5_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll0_inclk6_logical_to_physical_mapping = pll0_inclk6_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll0_inclk7_logical_to_physical_mapping = pll0_inclk7_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll0_inclk8_logical_to_physical_mapping = pll0_inclk8_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll0_inclk9_logical_to_physical_mapping = pll0_inclk9_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll1_inclk0_logical_to_physical_mapping = pll1_inclk0_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll1_inclk1_logical_to_physical_mapping = pll1_inclk1_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll1_inclk2_logical_to_physical_mapping = pll1_inclk2_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll1_inclk3_logical_to_physical_mapping = pll1_inclk3_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll1_inclk4_logical_to_physical_mapping = pll1_inclk4_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll1_inclk5_logical_to_physical_mapping = pll1_inclk5_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll1_inclk6_logical_to_physical_mapping = pll1_inclk6_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll1_inclk7_logical_to_physical_mapping = pll1_inclk7_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll1_inclk8_logical_to_physical_mapping = pll1_inclk8_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll1_inclk9_logical_to_physical_mapping = pll1_inclk9_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll2_inclk0_logical_to_physical_mapping = pll2_inclk0_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll2_inclk1_logical_to_physical_mapping = pll2_inclk1_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll2_inclk2_logical_to_physical_mapping = pll2_inclk2_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll2_inclk3_logical_to_physical_mapping = pll2_inclk3_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll2_inclk4_logical_to_physical_mapping = pll2_inclk4_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll2_inclk5_logical_to_physical_mapping = pll2_inclk5_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll2_inclk6_logical_to_physical_mapping = pll2_inclk6_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll2_inclk7_logical_to_physical_mapping = pll2_inclk7_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll2_inclk8_logical_to_physical_mapping = pll2_inclk8_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll2_inclk9_logical_to_physical_mapping = pll2_inclk9_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll3_inclk0_logical_to_physical_mapping = pll3_inclk0_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll3_inclk1_logical_to_physical_mapping = pll3_inclk1_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll3_inclk2_logical_to_physical_mapping = pll3_inclk2_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll3_inclk3_logical_to_physical_mapping = pll3_inclk3_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll3_inclk4_logical_to_physical_mapping = pll3_inclk4_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll3_inclk5_logical_to_physical_mapping = pll3_inclk5_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll3_inclk6_logical_to_physical_mapping = pll3_inclk6_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll3_inclk7_logical_to_physical_mapping = pll3_inclk7_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll3_inclk8_logical_to_physical_mapping = pll3_inclk8_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll3_inclk9_logical_to_physical_mapping = pll3_inclk9_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll4_inclk0_logical_to_physical_mapping = pll4_inclk0_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll4_inclk1_logical_to_physical_mapping = pll4_inclk1_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll4_inclk2_logical_to_physical_mapping = pll4_inclk2_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll4_inclk3_logical_to_physical_mapping = pll4_inclk3_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll4_inclk4_logical_to_physical_mapping = pll4_inclk4_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll4_inclk5_logical_to_physical_mapping = pll4_inclk5_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll4_inclk6_logical_to_physical_mapping = pll4_inclk6_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll4_inclk7_logical_to_physical_mapping = pll4_inclk7_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll4_inclk8_logical_to_physical_mapping = pll4_inclk8_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll4_inclk9_logical_to_physical_mapping = pll4_inclk9_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll5_inclk0_logical_to_physical_mapping = pll5_inclk0_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll5_inclk1_logical_to_physical_mapping = pll5_inclk1_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll5_inclk2_logical_to_physical_mapping = pll5_inclk2_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll5_inclk3_logical_to_physical_mapping = pll5_inclk3_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll5_inclk4_logical_to_physical_mapping = pll5_inclk4_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll5_inclk5_logical_to_physical_mapping = pll5_inclk5_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll5_inclk6_logical_to_physical_mapping = pll5_inclk6_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll5_inclk7_logical_to_physical_mapping = pll5_inclk7_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll5_inclk8_logical_to_physical_mapping = pll5_inclk8_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll5_inclk9_logical_to_physical_mapping = pll5_inclk9_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll0_logical_to_physical_mapping = pll0_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll1_logical_to_physical_mapping = pll1_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll2_logical_to_physical_mapping = pll2_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll3_logical_to_physical_mapping = pll3_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll4_logical_to_physical_mapping = pll4_logical_to_physical_mapping; defparam m_clksel_index_cram_map.pll5_logical_to_physical_mapping = pll5_logical_to_physical_mapping; defparam m_clksel_index_cram_map.refclk_divider0_logical_to_physical_mapping = refclk_divider0_logical_to_physical_mapping; defparam m_clksel_index_cram_map.refclk_divider1_logical_to_physical_mapping = refclk_divider1_logical_to_physical_mapping; defparam m_clksel_index_cram_map.rx0_logical_to_physical_mapping = rx0_logical_to_physical_mapping; defparam m_clksel_index_cram_map.rx1_logical_to_physical_mapping = rx1_logical_to_physical_mapping; defparam m_clksel_index_cram_map.rx2_logical_to_physical_mapping = rx2_logical_to_physical_mapping; defparam m_clksel_index_cram_map.rx3_logical_to_physical_mapping = rx3_logical_to_physical_mapping; defparam m_clksel_index_cram_map.rx4_logical_to_physical_mapping = rx4_logical_to_physical_mapping; defparam m_clksel_index_cram_map.rx5_logical_to_physical_mapping = rx5_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx0_logical_to_physical_mapping = tx0_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx1_logical_to_physical_mapping = tx1_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx2_logical_to_physical_mapping = tx2_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx3_logical_to_physical_mapping = tx3_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx4_logical_to_physical_mapping = tx4_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx5_logical_to_physical_mapping = tx5_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx0_pma_inclk0_logical_to_physical_mapping = tx0_pma_inclk0_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx0_pma_inclk1_logical_to_physical_mapping = tx0_pma_inclk1_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx0_pma_inclk2_logical_to_physical_mapping = tx0_pma_inclk2_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx0_pma_inclk3_logical_to_physical_mapping = tx0_pma_inclk3_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx0_pma_inclk4_logical_to_physical_mapping = tx0_pma_inclk4_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx1_pma_inclk0_logical_to_physical_mapping = tx1_pma_inclk0_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx1_pma_inclk1_logical_to_physical_mapping = tx1_pma_inclk1_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx1_pma_inclk2_logical_to_physical_mapping = tx1_pma_inclk2_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx1_pma_inclk3_logical_to_physical_mapping = tx1_pma_inclk3_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx1_pma_inclk4_logical_to_physical_mapping = tx1_pma_inclk4_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx2_pma_inclk0_logical_to_physical_mapping = tx2_pma_inclk0_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx2_pma_inclk1_logical_to_physical_mapping = tx2_pma_inclk1_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx2_pma_inclk2_logical_to_physical_mapping = tx2_pma_inclk2_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx2_pma_inclk3_logical_to_physical_mapping = tx2_pma_inclk3_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx2_pma_inclk4_logical_to_physical_mapping = tx2_pma_inclk4_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx3_pma_inclk0_logical_to_physical_mapping = tx3_pma_inclk0_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx3_pma_inclk1_logical_to_physical_mapping = tx3_pma_inclk1_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx3_pma_inclk2_logical_to_physical_mapping = tx3_pma_inclk2_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx3_pma_inclk3_logical_to_physical_mapping = tx3_pma_inclk3_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx3_pma_inclk4_logical_to_physical_mapping = tx3_pma_inclk4_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx4_pma_inclk0_logical_to_physical_mapping = tx4_pma_inclk0_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx4_pma_inclk1_logical_to_physical_mapping = tx4_pma_inclk1_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx4_pma_inclk2_logical_to_physical_mapping = tx4_pma_inclk2_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx4_pma_inclk3_logical_to_physical_mapping = tx4_pma_inclk3_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx4_pma_inclk4_logical_to_physical_mapping = tx4_pma_inclk4_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx5_pma_inclk0_logical_to_physical_mapping = tx5_pma_inclk0_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx5_pma_inclk1_logical_to_physical_mapping = tx5_pma_inclk1_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx5_pma_inclk2_logical_to_physical_mapping = tx5_pma_inclk2_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx5_pma_inclk3_logical_to_physical_mapping = tx5_pma_inclk3_logical_to_physical_mapping; defparam m_clksel_index_cram_map.tx5_pma_inclk4_logical_to_physical_mapping = tx5_pma_inclk4_logical_to_physical_mapping; //==================================================================== // Manually added code to handle logical indices = // === end = //==================================================================== // ---------------------------------------------------------------------------------------------------------------- // ------- physical to logic mapping ------------------------- // TXPCS assign ch0_txpcsdprioout_logic = (tx0_logical_to_physical_mapping == 0) ? ch0_txpcsdprioout_phy : (tx0_logical_to_physical_mapping == 1) ? ch1_txpcsdprioout_phy : (tx0_logical_to_physical_mapping == 2) ? ch2_txpcsdprioout_phy : (tx0_logical_to_physical_mapping == 3) ? ch3_txpcsdprioout_phy : ch0_txpcsdprioout_phy; assign ch1_txpcsdprioout_logic = (tx1_logical_to_physical_mapping == 0) ? ch0_txpcsdprioout_phy : (tx1_logical_to_physical_mapping == 1) ? ch1_txpcsdprioout_phy : (tx1_logical_to_physical_mapping == 2) ? ch2_txpcsdprioout_phy : (tx1_logical_to_physical_mapping == 3) ? ch3_txpcsdprioout_phy : ch1_txpcsdprioout_phy; assign ch2_txpcsdprioout_logic = (tx2_logical_to_physical_mapping == 0) ? ch0_txpcsdprioout_phy : (tx2_logical_to_physical_mapping == 1) ? ch1_txpcsdprioout_phy : (tx2_logical_to_physical_mapping == 2) ? ch2_txpcsdprioout_phy : (tx2_logical_to_physical_mapping == 3) ? ch3_txpcsdprioout_phy : ch2_txpcsdprioout_phy; assign ch3_txpcsdprioout_logic = (tx3_logical_to_physical_mapping == 0) ? ch0_txpcsdprioout_phy : (tx3_logical_to_physical_mapping == 1) ? ch1_txpcsdprioout_phy : (tx3_logical_to_physical_mapping == 2) ? ch2_txpcsdprioout_phy : (tx3_logical_to_physical_mapping == 3) ? ch3_txpcsdprioout_phy : ch3_txpcsdprioout_phy; // RXPCS assign ch0_rxpcsdprioout_logic = (rx0_logical_to_physical_mapping == 0) ? ch0_rxpcsdprioout_phy : (rx0_logical_to_physical_mapping == 1) ? ch1_rxpcsdprioout_phy : (rx0_logical_to_physical_mapping == 2) ? ch2_rxpcsdprioout_phy : (rx0_logical_to_physical_mapping == 3) ? ch3_rxpcsdprioout_phy : ch0_rxpcsdprioout_phy; assign ch1_rxpcsdprioout_logic = (rx1_logical_to_physical_mapping == 0) ? ch0_rxpcsdprioout_phy : (rx1_logical_to_physical_mapping == 1) ? ch1_rxpcsdprioout_phy : (rx1_logical_to_physical_mapping == 2) ? ch2_rxpcsdprioout_phy : (rx1_logical_to_physical_mapping == 3) ? ch3_rxpcsdprioout_phy : ch1_rxpcsdprioout_phy; assign ch2_rxpcsdprioout_logic = (rx2_logical_to_physical_mapping == 0) ? ch0_rxpcsdprioout_phy : (rx2_logical_to_physical_mapping == 1) ? ch1_rxpcsdprioout_phy : (rx2_logical_to_physical_mapping == 2) ? ch2_rxpcsdprioout_phy : (rx2_logical_to_physical_mapping == 3) ? ch3_rxpcsdprioout_phy : ch2_rxpcsdprioout_phy; assign ch3_rxpcsdprioout_logic = (rx3_logical_to_physical_mapping == 0) ? ch0_rxpcsdprioout_phy : (rx3_logical_to_physical_mapping == 1) ? ch1_rxpcsdprioout_phy : (rx3_logical_to_physical_mapping == 2) ? ch2_rxpcsdprioout_phy : (rx3_logical_to_physical_mapping == 3) ? ch3_rxpcsdprioout_phy : ch3_rxpcsdprioout_phy; // TXPMA assign ch0_txpmadprioout_logic = (tx0_logical_to_physical_mapping == 0)? ch0_txpmadprioout_phy : (tx0_logical_to_physical_mapping == 1)? ch1_txpmadprioout_phy : (tx0_logical_to_physical_mapping == 2)? ch2_txpmadprioout_phy : (tx0_logical_to_physical_mapping == 3)? ch3_txpmadprioout_phy : (tx0_logical_to_physical_mapping == 4)? ch4_txpmadprioout_phy : (tx0_logical_to_physical_mapping == 5)? ch5_txpmadprioout_phy : ch0_txpmadprioout_phy; assign ch1_txpmadprioout_logic = (tx1_logical_to_physical_mapping == 0)? ch0_txpmadprioout_phy : (tx1_logical_to_physical_mapping == 1)? ch1_txpmadprioout_phy : (tx1_logical_to_physical_mapping == 2)? ch2_txpmadprioout_phy : (tx1_logical_to_physical_mapping == 3)? ch3_txpmadprioout_phy : (tx1_logical_to_physical_mapping == 4)? ch4_txpmadprioout_phy : (tx1_logical_to_physical_mapping == 5)? ch5_txpmadprioout_phy : ch1_txpmadprioout_phy; assign ch2_txpmadprioout_logic = (tx2_logical_to_physical_mapping == 0)? ch0_txpmadprioout_phy : (tx2_logical_to_physical_mapping == 1)? ch1_txpmadprioout_phy : (tx2_logical_to_physical_mapping == 2)? ch2_txpmadprioout_phy : (tx2_logical_to_physical_mapping == 3)? ch3_txpmadprioout_phy : (tx2_logical_to_physical_mapping == 4)? ch4_txpmadprioout_phy : (tx2_logical_to_physical_mapping == 5)? ch5_txpmadprioout_phy : ch2_txpmadprioout_phy; assign ch3_txpmadprioout_logic = (tx3_logical_to_physical_mapping == 0)? ch0_txpmadprioout_phy : (tx3_logical_to_physical_mapping == 1)? ch1_txpmadprioout_phy : (tx3_logical_to_physical_mapping == 2)? ch2_txpmadprioout_phy : (tx3_logical_to_physical_mapping == 3)? ch3_txpmadprioout_phy : (tx3_logical_to_physical_mapping == 4)? ch4_txpmadprioout_phy : (tx3_logical_to_physical_mapping == 5)? ch5_txpmadprioout_phy : ch3_txpmadprioout_phy; assign ch4_txpmadprioout_logic = (tx4_logical_to_physical_mapping == 0)? ch0_txpmadprioout_phy : (tx4_logical_to_physical_mapping == 1)? ch1_txpmadprioout_phy : (tx4_logical_to_physical_mapping == 2)? ch2_txpmadprioout_phy : (tx4_logical_to_physical_mapping == 3)? ch3_txpmadprioout_phy : (tx4_logical_to_physical_mapping == 4)? ch4_txpmadprioout_phy : (tx4_logical_to_physical_mapping == 5)? ch5_txpmadprioout_phy : ch4_txpmadprioout_phy; assign ch5_txpmadprioout_logic = (tx5_logical_to_physical_mapping == 0)? ch0_txpmadprioout_phy : (tx5_logical_to_physical_mapping == 1)? ch1_txpmadprioout_phy : (tx5_logical_to_physical_mapping == 2)? ch2_txpmadprioout_phy : (tx5_logical_to_physical_mapping == 3)? ch3_txpmadprioout_phy : (tx5_logical_to_physical_mapping == 4)? ch4_txpmadprioout_phy : (tx5_logical_to_physical_mapping == 5)? ch5_txpmadprioout_phy : ch5_txpmadprioout_phy; //RXPMA assign ch0_rxpmadprioout_logic = (rx0_logical_to_physical_mapping == 0)? ch0_rxpmadprioout_phy : (rx0_logical_to_physical_mapping == 1)? ch1_rxpmadprioout_phy : (rx0_logical_to_physical_mapping == 2)? ch2_rxpmadprioout_phy : (rx0_logical_to_physical_mapping == 3)? ch3_rxpmadprioout_phy : (rx0_logical_to_physical_mapping == 4)? ch4_rxpmadprioout_phy : (rx0_logical_to_physical_mapping == 5)? ch5_rxpmadprioout_phy : ch0_rxpmadprioout_phy; assign ch1_rxpmadprioout_logic = (rx1_logical_to_physical_mapping == 0)? ch0_rxpmadprioout_phy : (rx1_logical_to_physical_mapping == 1)? ch1_rxpmadprioout_phy : (rx1_logical_to_physical_mapping == 2)? ch2_rxpmadprioout_phy : (rx1_logical_to_physical_mapping == 3)? ch3_rxpmadprioout_phy : (rx1_logical_to_physical_mapping == 4)? ch4_rxpmadprioout_phy : (rx1_logical_to_physical_mapping == 5)? ch5_rxpmadprioout_phy : ch1_rxpmadprioout_phy; assign ch2_rxpmadprioout_logic = (rx2_logical_to_physical_mapping == 0)? ch0_rxpmadprioout_phy : (rx2_logical_to_physical_mapping == 1)? ch1_rxpmadprioout_phy : (rx2_logical_to_physical_mapping == 2)? ch2_rxpmadprioout_phy : (rx2_logical_to_physical_mapping == 3)? ch3_rxpmadprioout_phy : (rx2_logical_to_physical_mapping == 4)? ch4_rxpmadprioout_phy : (rx2_logical_to_physical_mapping == 5)? ch5_rxpmadprioout_phy : ch2_rxpmadprioout_phy; assign ch3_rxpmadprioout_logic = (rx3_logical_to_physical_mapping == 0)? ch0_rxpmadprioout_phy : (rx3_logical_to_physical_mapping == 1)? ch1_rxpmadprioout_phy : (rx3_logical_to_physical_mapping == 2)? ch2_rxpmadprioout_phy : (rx3_logical_to_physical_mapping == 3)? ch3_rxpmadprioout_phy : (rx3_logical_to_physical_mapping == 4)? ch4_rxpmadprioout_phy : (rx3_logical_to_physical_mapping == 5)? ch5_rxpmadprioout_phy : ch3_rxpmadprioout_phy; assign ch4_rxpmadprioout_logic = (rx4_logical_to_physical_mapping == 0)? ch0_rxpmadprioout_phy : (rx4_logical_to_physical_mapping == 1)? ch1_rxpmadprioout_phy : (rx4_logical_to_physical_mapping == 2)? ch2_rxpmadprioout_phy : (rx4_logical_to_physical_mapping == 3)? ch3_rxpmadprioout_phy : (rx4_logical_to_physical_mapping == 4)? ch4_rxpmadprioout_phy : (rx4_logical_to_physical_mapping == 5)? ch5_rxpmadprioout_phy : ch4_rxpmadprioout_phy; assign ch5_rxpmadprioout_logic = (rx5_logical_to_physical_mapping == 0)? ch0_rxpmadprioout_phy : (rx5_logical_to_physical_mapping == 1)? ch1_rxpmadprioout_phy : (rx5_logical_to_physical_mapping == 2)? ch2_rxpmadprioout_phy : (rx5_logical_to_physical_mapping == 3)? ch3_rxpmadprioout_phy : (rx5_logical_to_physical_mapping == 4)? ch4_rxpmadprioout_phy : (rx5_logical_to_physical_mapping == 5)? ch5_rxpmadprioout_phy : ch5_rxpmadprioout_phy; // PLL assign ch0_rxplldprioout_logic = (pll0_logical_to_physical_mapping == 0) ? ch0_rxplldprioout_phy : (pll0_logical_to_physical_mapping == 1) ? ch1_rxplldprioout_phy : (pll0_logical_to_physical_mapping == 2) ? ch2_rxplldprioout_phy : (pll0_logical_to_physical_mapping == 3) ? ch3_rxplldprioout_phy : ch0_rxplldprioout_phy; assign ch1_rxplldprioout_logic = (pll1_logical_to_physical_mapping == 0) ? ch0_rxplldprioout_phy : (pll1_logical_to_physical_mapping == 1) ? ch1_rxplldprioout_phy : (pll1_logical_to_physical_mapping == 2) ? ch2_rxplldprioout_phy : (pll1_logical_to_physical_mapping == 3) ? ch3_rxplldprioout_phy : ch1_rxplldprioout_phy; assign ch2_rxplldprioout_logic = (pll2_logical_to_physical_mapping == 0) ? ch0_rxplldprioout_phy : (pll2_logical_to_physical_mapping == 1) ? ch1_rxplldprioout_phy : (pll2_logical_to_physical_mapping == 2) ? ch2_rxplldprioout_phy : (pll2_logical_to_physical_mapping == 3) ? ch3_rxplldprioout_phy : ch2_rxplldprioout_phy; assign ch3_rxplldprioout_logic = (pll3_logical_to_physical_mapping == 0) ? ch0_rxplldprioout_phy : (pll3_logical_to_physical_mapping == 1) ? ch1_rxplldprioout_phy : (pll3_logical_to_physical_mapping == 2) ? ch2_rxplldprioout_phy : (pll3_logical_to_physical_mapping == 3) ? ch3_rxplldprioout_phy : ch3_rxplldprioout_phy; assign ch4_rxtxplldprioout_logic = (pll4_logical_to_physical_mapping == 4) ? ch4_rxtxplldprioout_phy : ch5_rxtxplldprioin_phy; assign ch5_rxtxplldprioout_logic = (pll5_logical_to_physical_mapping == 5) ? ch5_rxtxplldprioout_phy : ch4_rxtxplldprioin_phy; // CMUDivider assign ch0_cmudividerdprioout_logic = (tx0_logical_to_physical_mapping == 0)? ch0_cmudividerdprioout_phy : (tx0_logical_to_physical_mapping == 1)? ch1_cmudividerdprioout_phy : (tx0_logical_to_physical_mapping == 2)? ch2_cmudividerdprioout_phy : (tx0_logical_to_physical_mapping == 3)? ch3_cmudividerdprioout_phy : (tx0_logical_to_physical_mapping == 4)? ch4_cmudividerdprioout_phy : (tx0_logical_to_physical_mapping == 5)? ch5_cmudividerdprioout_phy : ch0_cmudividerdprioout_phy; assign ch1_cmudividerdprioout_logic = (tx1_logical_to_physical_mapping == 0)? ch0_cmudividerdprioout_phy : (tx1_logical_to_physical_mapping == 1)? ch1_cmudividerdprioout_phy : (tx1_logical_to_physical_mapping == 2)? ch2_cmudividerdprioout_phy : (tx1_logical_to_physical_mapping == 3)? ch3_cmudividerdprioout_phy : (tx1_logical_to_physical_mapping == 4)? ch4_cmudividerdprioout_phy : (tx1_logical_to_physical_mapping == 5)? ch5_cmudividerdprioout_phy : ch1_cmudividerdprioout_phy; assign ch2_cmudividerdprioout_logic = (tx2_logical_to_physical_mapping == 0)? ch0_cmudividerdprioout_phy : (tx2_logical_to_physical_mapping == 1)? ch1_cmudividerdprioout_phy : (tx2_logical_to_physical_mapping == 2)? ch2_cmudividerdprioout_phy : (tx2_logical_to_physical_mapping == 3)? ch3_cmudividerdprioout_phy : (tx2_logical_to_physical_mapping == 4)? ch4_cmudividerdprioout_phy : (tx2_logical_to_physical_mapping == 5)? ch5_cmudividerdprioout_phy : ch2_cmudividerdprioout_phy; assign ch3_cmudividerdprioout_logic = (tx3_logical_to_physical_mapping == 0)? ch0_cmudividerdprioout_phy : (tx3_logical_to_physical_mapping == 1)? ch1_cmudividerdprioout_phy : (tx3_logical_to_physical_mapping == 2)? ch2_cmudividerdprioout_phy : (tx3_logical_to_physical_mapping == 3)? ch3_cmudividerdprioout_phy : (tx3_logical_to_physical_mapping == 4)? ch4_cmudividerdprioout_phy : (tx3_logical_to_physical_mapping == 5)? ch5_cmudividerdprioout_phy : ch3_cmudividerdprioout_phy; assign ch4_cmudividerdprioout_logic = (tx4_logical_to_physical_mapping == 0)? ch0_cmudividerdprioout_phy : (tx4_logical_to_physical_mapping == 1)? ch1_cmudividerdprioout_phy : (tx4_logical_to_physical_mapping == 2)? ch2_cmudividerdprioout_phy : (tx4_logical_to_physical_mapping == 3)? ch3_cmudividerdprioout_phy : (tx4_logical_to_physical_mapping == 4)? ch4_cmudividerdprioout_phy : (tx4_logical_to_physical_mapping == 5)? ch5_cmudividerdprioout_phy : ch4_cmudividerdprioout_phy; assign ch5_cmudividerdprioout_logic = (tx5_logical_to_physical_mapping == 0)? ch0_cmudividerdprioout_phy : (tx5_logical_to_physical_mapping == 1)? ch1_cmudividerdprioout_phy : (tx5_logical_to_physical_mapping == 2)? ch2_cmudividerdprioout_phy : (tx5_logical_to_physical_mapping == 3)? ch3_cmudividerdprioout_phy : (tx5_logical_to_physical_mapping == 4)? ch4_cmudividerdprioout_phy : (tx5_logical_to_physical_mapping == 5)? ch5_cmudividerdprioout_phy : ch5_cmudividerdprioout_phy; // ------- output -------------------------------------------- // TXPCS assign txpcsdprioout [149 : 0] = ch0_txpcsdprioout_logic; assign txpcsdprioout [299 : 150] = ch1_txpcsdprioout_logic; assign txpcsdprioout [449 : 300] = ch2_txpcsdprioout_logic; assign txpcsdprioout [599 : 450] = ch3_txpcsdprioout_logic; // RXPCS assign rxpcsdprioout [399 : 0] = ch0_rxpcsdprioout_logic; assign rxpcsdprioout [799 : 400] = ch1_rxpcsdprioout_logic; assign rxpcsdprioout [1199 : 800] = ch2_rxpcsdprioout_logic; assign rxpcsdprioout [1599 : 1200] = ch3_rxpcsdprioout_logic; // TXPMA assign txpmadprioout [299 : 0] = ch0_txpmadprioout_logic; assign txpmadprioout [599 : 300] = ch1_txpmadprioout_logic; assign txpmadprioout [899 : 600] = ch2_txpmadprioout_logic; assign txpmadprioout [1199 : 900] = ch3_txpmadprioout_logic; assign txpmadprioout [1499 : 1200] = ch4_txpmadprioout_logic; assign txpmadprioout [1799 : 1500] = ch5_txpmadprioout_logic; //RXPMA assign rxpmadprioout [299 : 0] = ch0_rxpmadprioout_logic; assign rxpmadprioout [599 : 300] = ch1_rxpmadprioout_logic; assign rxpmadprioout [899 : 600] = ch2_rxpmadprioout_logic; assign rxpmadprioout [1199 : 900] = ch3_rxpmadprioout_logic; assign rxpmadprioout [1499 : 1200] = ch4_rxpmadprioout_logic; assign rxpmadprioout [1799 : 1500] = ch5_rxpmadprioout_logic; // PLL assign cmuplldprioout [ 299 : 0 ] = ch0_rxplldprioout_logic; assign cmuplldprioout [ 599 : 300 ] = ch1_rxplldprioout_logic; assign cmuplldprioout [ 899 : 600 ] = ch2_rxplldprioout_logic; assign cmuplldprioout [ 1199 : 900 ] = ch3_rxplldprioout_logic; assign cmuplldprioout [ 1499 : 1200 ] = ch4_rxtxplldprioout_logic; assign cmuplldprioout [ 1799 : 1500 ] = ch5_rxtxplldprioout_logic; // CMUDivider assign cmudividerdprioout [99 : 0] = ch0_cmudividerdprioout_logic; assign cmudividerdprioout [199 : 100] = ch1_cmudividerdprioout_logic; assign cmudividerdprioout [299 : 200] = ch2_cmudividerdprioout_logic; assign cmudividerdprioout [399 : 300] = ch3_cmudividerdprioout_logic; assign cmudividerdprioout [499 : 400] = ch4_cmudividerdprioout_logic; assign cmudividerdprioout [599 : 500] = ch5_cmudividerdprioout_logic; //============================================================ // Manually added code to handle 5th/6th PMA ================= // === begin = //============================================================ // centrl CSR physcial --------------------------------------- assign cmu0_in_centrl_ctrl_1 = ch4_in_chnl_ctrl_28; assign cmu0_in_centrl_ctrl_2 = ch4_in_chnl_ctrl_29; assign cmu0_in_centrl_ctrl_3 = ch4_in_chnl_ctrl_30; assign cmu0_in_centrl_ctrl_4 = ch4_in_chnl_ctrl_31; assign cmu0_in_centrl_ctrl_5 = ch4_in_chnl_ctrl_32; assign cmu0_in_centrl_ctrl_6 = ch4_in_chnl_ctrl_33; assign cmu0_in_centrl_ctrl_7 = ch4_in_chnl_ctrl_34; assign cmu0_in_centrl_ctrl_8 = ch4_in_chnl_ctrl_35; assign cmu0_in_centrl_ctrl_9 = ch4_in_chnl_ctrl_36; assign cmu0_in_centrl_ctrl_10 = ch4_in_chnl_ctrl_37; assign cmu0_in_centrl_ctrl_11 = ch4_in_chnl_ctrl_38; assign cmu0_in_centrl_ctrl_12 = ch4_in_chnl_ctrl_39; assign cmu0_in_centrl_ctrl_13 = ch4_in_chnl_ctrl_40; assign cmu0_in_centrl_ctrl_14 = ch4_in_chnl_ctrl_41; assign cmu0_in_centrl_ctrl_15 = ch4_in_chnl_ctrl_42; assign cmu0_in_centrl_ctrl_16 = ch4_in_chnl_ctrl_43; assign cmu0_in_centrl_ctrl_17 = ch4_in_chnl_ctrl_44; assign cmu0_in_centrl_ctrl_18 = ch4_in_chnl_ctrl_45; assign cmu0_in_centrl_ctrl_19 = ch4_in_chnl_ctrl_46; assign cmu0_in_centrl_ctrl_20 = ch4_in_chnl_ctrl_47; assign cmu1_in_centrl_ctrl_1 = ch5_in_chnl_ctrl_28; assign cmu1_in_centrl_ctrl_2 = ch5_in_chnl_ctrl_29; assign cmu1_in_centrl_ctrl_3 = ch5_in_chnl_ctrl_30; assign cmu1_in_centrl_ctrl_4 = ch5_in_chnl_ctrl_31; assign cmu1_in_centrl_ctrl_5 = ch5_in_chnl_ctrl_32; assign cmu1_in_centrl_ctrl_6 = ch5_in_chnl_ctrl_33; assign cmu1_in_centrl_ctrl_7 = ch5_in_chnl_ctrl_34; assign cmu1_in_centrl_ctrl_8 = ch5_in_chnl_ctrl_35; assign cmu1_in_centrl_ctrl_9 = ch5_in_chnl_ctrl_36; assign cmu1_in_centrl_ctrl_10 = ch5_in_chnl_ctrl_37; assign cmu1_in_centrl_ctrl_11 = ch5_in_chnl_ctrl_38; assign cmu1_in_centrl_ctrl_12 = ch5_in_chnl_ctrl_39; assign cmu1_in_centrl_ctrl_13 = ch5_in_chnl_ctrl_40; assign cmu1_in_centrl_ctrl_14 = ch5_in_chnl_ctrl_41; assign cmu1_in_centrl_ctrl_15 = ch5_in_chnl_ctrl_42; assign cmu1_in_centrl_ctrl_16 = ch5_in_chnl_ctrl_43; assign cmu1_in_centrl_ctrl_17 = ch5_in_chnl_ctrl_44; assign cmu1_in_centrl_ctrl_18 = ch5_in_chnl_ctrl_45; assign cmu1_in_centrl_ctrl_19 = ch5_in_chnl_ctrl_46; assign cmu1_in_centrl_ctrl_20 = ch5_in_chnl_ctrl_47; assign csr_centrl_in[15:0] = cmu0_in_centrl_ctrl_1; assign csr_centrl_in[31:16] = cmu0_in_centrl_ctrl_2; assign csr_centrl_in[47:32] = cmu0_in_centrl_ctrl_3; assign csr_centrl_in[63:48] = cmu0_in_centrl_ctrl_4; assign csr_centrl_in[79:64] = cmu0_in_centrl_ctrl_5; assign csr_centrl_in[95:80] = cmu0_in_centrl_ctrl_6; assign csr_centrl_in[111:96] = cmu0_in_centrl_ctrl_7; assign csr_centrl_in[127:112] = cmu0_in_centrl_ctrl_8; assign csr_centrl_in[143:128] = cmu0_in_centrl_ctrl_9; assign csr_centrl_in[159:144] = cmu0_in_centrl_ctrl_10; assign csr_centrl_in[175:160] = cmu0_in_centrl_ctrl_11; assign csr_centrl_in[191:176] = cmu0_in_centrl_ctrl_12; assign csr_centrl_in[207:192] = cmu0_in_centrl_ctrl_13; assign csr_centrl_in[223:208] = cmu0_in_centrl_ctrl_14; assign csr_centrl_in[239:224] = cmu0_in_centrl_ctrl_15; assign csr_centrl_in_reserved[15:0] = cmu0_in_centrl_ctrl_16; assign csr_centrl_in[255:240] = cmu0_in_centrl_ctrl_17; assign csr_centrl_in[271:256] = cmu0_in_centrl_ctrl_18; assign csr_centrl_in[287:272] = cmu0_in_centrl_ctrl_19; assign csr_centrl_in[303:288] = cmu0_in_centrl_ctrl_20; assign csr_centrl_in[319:304] = cmu0_in_centrl_ctrl_21; // cmu only assign csr_centrl_in[335:320] = cmu1_in_centrl_ctrl_1; assign csr_centrl_in[351:336] = cmu1_in_centrl_ctrl_2; assign csr_centrl_in[367:352] = cmu1_in_centrl_ctrl_3; assign csr_centrl_in[383:368] = cmu1_in_centrl_ctrl_4; assign csr_centrl_in[399:384] = cmu1_in_centrl_ctrl_5; assign csr_centrl_in[415:400] = cmu1_in_centrl_ctrl_6; assign csr_centrl_in[431:416] = cmu1_in_centrl_ctrl_7; assign csr_centrl_in[447:432] = cmu1_in_centrl_ctrl_8; assign csr_centrl_in[463:448] = cmu1_in_centrl_ctrl_9; assign csr_centrl_in[479:464] = cmu1_in_centrl_ctrl_10; assign csr_centrl_in[495:480] = cmu1_in_centrl_ctrl_11; assign csr_centrl_in[511:496] = cmu1_in_centrl_ctrl_12; assign csr_centrl_in[527:512] = cmu1_in_centrl_ctrl_13; assign csr_centrl_in[543:528] = cmu1_in_centrl_ctrl_14; assign csr_centrl_in[559:544] = cmu1_in_centrl_ctrl_15; assign csr_centrl_in_reserved[31:16] = cmu1_in_centrl_ctrl_16; assign csr_centrl_in[575:560] = cmu1_in_centrl_ctrl_17; assign csr_centrl_in[591:576] = cmu1_in_centrl_ctrl_18; assign csr_centrl_in[607:592] = cmu1_in_centrl_ctrl_19; assign csr_centrl_in[623:608] = cmu1_in_centrl_ctrl_20; assign csr_centrl_in[639:624] = cmu1_in_centrl_ctrl_21; // cmu only Table 74 assign csr_centrl_in[655:640] = cmu_in_centrl_global_0; // global XAUI etc. Table 75 assign csr_centrl_in[671:656] = cmu_in_centrl_global_1; assign csr_centrl_in[687:672] = cmu_in_centrl_global_2; assign csr_centrl_in[703:688] = cmu_in_centrl_global_3; // centrl DPRIO out physcial --------------------------------- assign cmu0_out_centrl_ctrl_1 = dp_centrl_out[15:0] ; assign cmu0_out_centrl_ctrl_2 = dp_centrl_out[31:16] ; assign cmu0_out_centrl_ctrl_3 = dp_centrl_out[47:32] ; assign cmu0_out_centrl_ctrl_4 = dp_centrl_out[63:48] ; assign cmu0_out_centrl_ctrl_5 = dp_centrl_out[79:64] ; assign cmu0_out_centrl_ctrl_6 = dp_centrl_out[95:80] ; assign cmu0_out_centrl_ctrl_7 = dp_centrl_out[111:96] ; assign cmu0_out_centrl_ctrl_8 = dp_centrl_out[127:112] ; assign cmu0_out_centrl_ctrl_9 = dp_centrl_out[143:128] ; assign cmu0_out_centrl_ctrl_10 = dp_centrl_out[159:144] ; assign cmu0_out_centrl_ctrl_11 = dp_centrl_out[175:160] ; assign cmu0_out_centrl_ctrl_12 = dp_centrl_out[191:176] ; assign cmu0_out_centrl_ctrl_13 = dp_centrl_out[207:192] ; assign cmu0_out_centrl_ctrl_14 = dp_centrl_out[223:208] ; assign cmu0_out_centrl_ctrl_15 = dp_centrl_out[239:224] ; assign cmu0_out_centrl_ctrl_16 = dp_centrl_out_reserved[15:0]; assign cmu0_out_centrl_ctrl_17 = dp_centrl_out[255:240] ; assign cmu0_out_centrl_ctrl_18 = dp_centrl_out[271:256] ; assign cmu0_out_centrl_ctrl_19 = dp_centrl_out[287:272] ; assign cmu0_out_centrl_ctrl_20 = dp_centrl_out[303:288] ; assign cmu0_out_centrl_ctrl_21 = dp_centrl_out[319:304] ; assign cmu1_out_centrl_ctrl_1 = dp_centrl_out[335:320] ; assign cmu1_out_centrl_ctrl_2 = dp_centrl_out[351:336] ; assign cmu1_out_centrl_ctrl_3 = dp_centrl_out[367:352] ; assign cmu1_out_centrl_ctrl_4 = dp_centrl_out[383:368] ; assign cmu1_out_centrl_ctrl_5 = dp_centrl_out[399:384] ; assign cmu1_out_centrl_ctrl_6 = dp_centrl_out[415:400] ; assign cmu1_out_centrl_ctrl_7 = dp_centrl_out[431:416] ; assign cmu1_out_centrl_ctrl_8 = dp_centrl_out[447:432] ; assign cmu1_out_centrl_ctrl_9 = dp_centrl_out[463:448] ; assign cmu1_out_centrl_ctrl_10 = dp_centrl_out[479:464] ; assign cmu1_out_centrl_ctrl_11 = dp_centrl_out[495:480] ; assign cmu1_out_centrl_ctrl_12 = dp_centrl_out[511:496] ; assign cmu1_out_centrl_ctrl_13 = dp_centrl_out[527:512] ; assign cmu1_out_centrl_ctrl_14 = dp_centrl_out[543:528] ; assign cmu1_out_centrl_ctrl_15 = dp_centrl_out[559:544] ; assign cmu1_out_centrl_ctrl_16 = dp_centrl_out_reserved[31:16]; assign cmu1_out_centrl_ctrl_17 = dp_centrl_out[575:560] ; assign cmu1_out_centrl_ctrl_18 = dp_centrl_out[591:576] ; assign cmu1_out_centrl_ctrl_19 = dp_centrl_out[607:592] ; assign cmu1_out_centrl_ctrl_20 = dp_centrl_out[623:608] ; assign cmu1_out_centrl_ctrl_21 = dp_centrl_out[639:624] ; assign cmu_out_centrl_global_0 = dp_centrl_out[655:640] ; // global XAUI etc. Tables 75 assign cmu_out_centrl_global_1 = dp_centrl_out[671:656] ; assign cmu_out_centrl_global_2 = dp_centrl_out[687:672] ; assign cmu_out_centrl_global_3 = dp_centrl_out[703:688] ; assign ch4_out_chnl_ctrl_28 = cmu0_out_centrl_ctrl_1; assign ch4_out_chnl_ctrl_29 = cmu0_out_centrl_ctrl_2; assign ch4_out_chnl_ctrl_30 = cmu0_out_centrl_ctrl_3; assign ch4_out_chnl_ctrl_31 = cmu0_out_centrl_ctrl_4; assign ch4_out_chnl_ctrl_32 = cmu0_out_centrl_ctrl_5; assign ch4_out_chnl_ctrl_33 = cmu0_out_centrl_ctrl_6; assign ch4_out_chnl_ctrl_34 = cmu0_out_centrl_ctrl_7; assign ch4_out_chnl_ctrl_35 = cmu0_out_centrl_ctrl_8; assign ch4_out_chnl_ctrl_36 = cmu0_out_centrl_ctrl_9; assign ch4_out_chnl_ctrl_37 = cmu0_out_centrl_ctrl_10; assign ch4_out_chnl_ctrl_38 = cmu0_out_centrl_ctrl_11; assign ch4_out_chnl_ctrl_39 = cmu0_out_centrl_ctrl_12; assign ch4_out_chnl_ctrl_40 = cmu0_out_centrl_ctrl_13; assign ch4_out_chnl_ctrl_41 = cmu0_out_centrl_ctrl_14; assign ch4_out_chnl_ctrl_42 = cmu0_out_centrl_ctrl_15; assign ch4_out_chnl_ctrl_43 = cmu0_out_centrl_ctrl_16; assign ch4_out_chnl_ctrl_44 = cmu0_out_centrl_ctrl_17; assign ch4_out_chnl_ctrl_45 = cmu0_out_centrl_ctrl_18; assign ch4_out_chnl_ctrl_46 = cmu0_out_centrl_ctrl_19; assign ch4_out_chnl_ctrl_47 = cmu0_out_centrl_ctrl_20; assign ch5_out_chnl_ctrl_28 = cmu1_out_centrl_ctrl_1; assign ch5_out_chnl_ctrl_29 = cmu1_out_centrl_ctrl_2; assign ch5_out_chnl_ctrl_30 = cmu1_out_centrl_ctrl_3; assign ch5_out_chnl_ctrl_31 = cmu1_out_centrl_ctrl_4; assign ch5_out_chnl_ctrl_32 = cmu1_out_centrl_ctrl_5; assign ch5_out_chnl_ctrl_33 = cmu1_out_centrl_ctrl_6; assign ch5_out_chnl_ctrl_34 = cmu1_out_centrl_ctrl_7; assign ch5_out_chnl_ctrl_35 = cmu1_out_centrl_ctrl_8; assign ch5_out_chnl_ctrl_36 = cmu1_out_centrl_ctrl_9; assign ch5_out_chnl_ctrl_37 = cmu1_out_centrl_ctrl_10; assign ch5_out_chnl_ctrl_38 = cmu1_out_centrl_ctrl_11; assign ch5_out_chnl_ctrl_39 = cmu1_out_centrl_ctrl_12; assign ch5_out_chnl_ctrl_40 = cmu1_out_centrl_ctrl_13; assign ch5_out_chnl_ctrl_41 = cmu1_out_centrl_ctrl_14; assign ch5_out_chnl_ctrl_42 = cmu1_out_centrl_ctrl_15; assign ch5_out_chnl_ctrl_43 = cmu1_out_centrl_ctrl_16; assign ch5_out_chnl_ctrl_44 = cmu1_out_centrl_ctrl_17; assign ch5_out_chnl_ctrl_45 = cmu1_out_centrl_ctrl_18; assign ch5_out_chnl_ctrl_46 = cmu1_out_centrl_ctrl_19; assign ch5_out_chnl_ctrl_47 = cmu1_out_centrl_ctrl_20; //;============================================================ //; Manually added code to handle 5th/6th PMA ================= //; === end = //;============================================================ // --------------------------------------------------------------------------- // dbg dump // --------------------------------------------------------------------------- initial begin #sim_dump_dprio_internal_reg_at_time; if (sim_dump_dprio_internal_reg_at_time != 0) begin dbg_file = $fopen(sim_dump_filename); $fdisplay(dbg_file, "The CRAM values of %m at simulation time %d", sim_dump_dprio_internal_reg_at_time); $fdisplay(dbg_file, ""); //auto generated dump code - begin $fdisplay(dbg_file, "Table1: TXPCS Control Register 1"); $fdisplay(dbg_file, "%b //ch0 Table 1", ch0_out_chnl_ctrl_1); $fdisplay(dbg_file, "%b //ch1 Table 1", ch1_out_chnl_ctrl_1); $fdisplay(dbg_file, "%b //ch2 Table 1", ch2_out_chnl_ctrl_1); $fdisplay(dbg_file, "%b //ch3 Table 1", ch3_out_chnl_ctrl_1); $fdisplay(dbg_file, "Table2: TXPCS Control Register 2"); $fdisplay(dbg_file, "%b //ch0 Table 2", ch0_out_chnl_ctrl_2); $fdisplay(dbg_file, "%b //ch1 Table 2", ch1_out_chnl_ctrl_2); $fdisplay(dbg_file, "%b //ch2 Table 2", ch2_out_chnl_ctrl_2); $fdisplay(dbg_file, "%b //ch3 Table 2", ch3_out_chnl_ctrl_2); $fdisplay(dbg_file, "Table3: TXPCS Control Register 3"); $fdisplay(dbg_file, "%b //ch0 Table 3", ch0_out_chnl_ctrl_3); $fdisplay(dbg_file, "%b //ch1 Table 3", ch1_out_chnl_ctrl_3); $fdisplay(dbg_file, "%b //ch2 Table 3", ch2_out_chnl_ctrl_3); $fdisplay(dbg_file, "%b //ch3 Table 3", ch3_out_chnl_ctrl_3); $fdisplay(dbg_file, "Table4: TXPCS Control Register 4"); $fdisplay(dbg_file, "%b //ch0 Table 4", ch0_out_chnl_ctrl_4); $fdisplay(dbg_file, "%b //ch1 Table 4", ch1_out_chnl_ctrl_4); $fdisplay(dbg_file, "%b //ch2 Table 4", ch2_out_chnl_ctrl_4); $fdisplay(dbg_file, "%b //ch3 Table 4", ch3_out_chnl_ctrl_4); $fdisplay(dbg_file, "Table5: RXPCS Control Register 1"); $fdisplay(dbg_file, "%b //ch0 Table 5", ch0_out_chnl_ctrl_5); $fdisplay(dbg_file, "%b //ch1 Table 5", ch1_out_chnl_ctrl_5); $fdisplay(dbg_file, "%b //ch2 Table 5", ch2_out_chnl_ctrl_5); $fdisplay(dbg_file, "%b //ch3 Table 5", ch3_out_chnl_ctrl_5); $fdisplay(dbg_file, "Table6: RXPCS Control Register 2"); $fdisplay(dbg_file, "%b //ch0 Table 6", ch0_out_chnl_ctrl_6); $fdisplay(dbg_file, "%b //ch1 Table 6", ch1_out_chnl_ctrl_6); $fdisplay(dbg_file, "%b //ch2 Table 6", ch2_out_chnl_ctrl_6); $fdisplay(dbg_file, "%b //ch3 Table 6", ch3_out_chnl_ctrl_6); $fdisplay(dbg_file, "Table7: RXPCS Control Register 3"); $fdisplay(dbg_file, "%b //ch0 Table 7", ch0_out_chnl_ctrl_7); $fdisplay(dbg_file, "%b //ch1 Table 7", ch1_out_chnl_ctrl_7); $fdisplay(dbg_file, "%b //ch2 Table 7", ch2_out_chnl_ctrl_7); $fdisplay(dbg_file, "%b //ch3 Table 7", ch3_out_chnl_ctrl_7); $fdisplay(dbg_file, "Table8: RXPCS Control Register 4"); $fdisplay(dbg_file, "%b //ch0 Table 8", ch0_out_chnl_ctrl_8); $fdisplay(dbg_file, "%b //ch1 Table 8", ch1_out_chnl_ctrl_8); $fdisplay(dbg_file, "%b //ch2 Table 8", ch2_out_chnl_ctrl_8); $fdisplay(dbg_file, "%b //ch3 Table 8", ch3_out_chnl_ctrl_8); $fdisplay(dbg_file, "Table9: RXPCS Control Register 5"); $fdisplay(dbg_file, "%b //ch0 Table 9", ch0_out_chnl_ctrl_9); $fdisplay(dbg_file, "%b //ch1 Table 9", ch1_out_chnl_ctrl_9); $fdisplay(dbg_file, "%b //ch2 Table 9", ch2_out_chnl_ctrl_9); $fdisplay(dbg_file, "%b //ch3 Table 9", ch3_out_chnl_ctrl_9); $fdisplay(dbg_file, "Table10: RXPCS Control Register 6"); $fdisplay(dbg_file, "%b //ch0 Table 10", ch0_out_chnl_ctrl_10); $fdisplay(dbg_file, "%b //ch1 Table 10", ch1_out_chnl_ctrl_10); $fdisplay(dbg_file, "%b //ch2 Table 10", ch2_out_chnl_ctrl_10); $fdisplay(dbg_file, "%b //ch3 Table 10", ch3_out_chnl_ctrl_10); $fdisplay(dbg_file, "Table11: RXPCS Control Register 7"); $fdisplay(dbg_file, "%b //ch0 Table 11", ch0_out_chnl_ctrl_11); $fdisplay(dbg_file, "%b //ch1 Table 11", ch1_out_chnl_ctrl_11); $fdisplay(dbg_file, "%b //ch2 Table 11", ch2_out_chnl_ctrl_11); $fdisplay(dbg_file, "%b //ch3 Table 11", ch3_out_chnl_ctrl_11); $fdisplay(dbg_file, "Table12: RXPCS Control Register 8"); $fdisplay(dbg_file, "%b //ch0 Table 12", ch0_out_chnl_ctrl_12); $fdisplay(dbg_file, "%b //ch1 Table 12", ch1_out_chnl_ctrl_12); $fdisplay(dbg_file, "%b //ch2 Table 12", ch2_out_chnl_ctrl_12); $fdisplay(dbg_file, "%b //ch3 Table 12", ch3_out_chnl_ctrl_12); $fdisplay(dbg_file, "Table13: RXPCS Control Register 9"); $fdisplay(dbg_file, "%b //ch0 Table 13", ch0_out_chnl_ctrl_13); $fdisplay(dbg_file, "%b //ch1 Table 13", ch1_out_chnl_ctrl_13); $fdisplay(dbg_file, "%b //ch2 Table 13", ch2_out_chnl_ctrl_13); $fdisplay(dbg_file, "%b //ch3 Table 13", ch3_out_chnl_ctrl_13); $fdisplay(dbg_file, "Table14: RXPCS Control Register 10"); $fdisplay(dbg_file, "%b //ch0 Table 14", ch0_out_chnl_ctrl_14); $fdisplay(dbg_file, "%b //ch1 Table 14", ch1_out_chnl_ctrl_14); $fdisplay(dbg_file, "%b //ch2 Table 14", ch2_out_chnl_ctrl_14); $fdisplay(dbg_file, "%b //ch3 Table 14", ch3_out_chnl_ctrl_14); $fdisplay(dbg_file, "Table15: RXPCS Control Register 11"); $fdisplay(dbg_file, "%b //ch0 Table 15", ch0_out_chnl_ctrl_15); $fdisplay(dbg_file, "%b //ch1 Table 15", ch1_out_chnl_ctrl_15); $fdisplay(dbg_file, "%b //ch2 Table 15", ch2_out_chnl_ctrl_15); $fdisplay(dbg_file, "%b //ch3 Table 15", ch3_out_chnl_ctrl_15); $fdisplay(dbg_file, "Table16: RXPCS Control Register 12"); $fdisplay(dbg_file, "%b //ch0 Table 16", ch0_out_chnl_ctrl_16); $fdisplay(dbg_file, "%b //ch1 Table 16", ch1_out_chnl_ctrl_16); $fdisplay(dbg_file, "%b //ch2 Table 16", ch2_out_chnl_ctrl_16); $fdisplay(dbg_file, "%b //ch3 Table 16", ch3_out_chnl_ctrl_16); $fdisplay(dbg_file, "Table17: RXPCS Control Register 13"); $fdisplay(dbg_file, "%b //ch0 Table 17", ch0_out_chnl_ctrl_17); $fdisplay(dbg_file, "%b //ch1 Table 17", ch1_out_chnl_ctrl_17); $fdisplay(dbg_file, "%b //ch2 Table 17", ch2_out_chnl_ctrl_17); $fdisplay(dbg_file, "%b //ch3 Table 17", ch3_out_chnl_ctrl_17); $fdisplay(dbg_file, "Table18: RXPCS Control Register 14"); $fdisplay(dbg_file, "%b //ch0 Table 18", ch0_out_chnl_ctrl_18); $fdisplay(dbg_file, "%b //ch1 Table 18", ch1_out_chnl_ctrl_18); $fdisplay(dbg_file, "%b //ch2 Table 18", ch2_out_chnl_ctrl_18); $fdisplay(dbg_file, "%b //ch3 Table 18", ch3_out_chnl_ctrl_18); $fdisplay(dbg_file, "Table19: RXPCS Control Register 15"); $fdisplay(dbg_file, "%b //ch0 Table 19", ch0_out_chnl_ctrl_19); $fdisplay(dbg_file, "%b //ch1 Table 19", ch1_out_chnl_ctrl_19); $fdisplay(dbg_file, "%b //ch2 Table 19", ch2_out_chnl_ctrl_19); $fdisplay(dbg_file, "%b //ch3 Table 19", ch3_out_chnl_ctrl_19); $fdisplay(dbg_file, "Table20: RXPCS Control Register 16"); $fdisplay(dbg_file, "%b //ch0 Table 20", ch0_out_chnl_ctrl_20); $fdisplay(dbg_file, "%b //ch1 Table 20", ch1_out_chnl_ctrl_20); $fdisplay(dbg_file, "%b //ch2 Table 20", ch2_out_chnl_ctrl_20); $fdisplay(dbg_file, "%b //ch3 Table 20", ch3_out_chnl_ctrl_20); $fdisplay(dbg_file, "Table21: RXPCS Control Register 17"); $fdisplay(dbg_file, "%b //ch0 Table 21", ch0_out_chnl_ctrl_21); $fdisplay(dbg_file, "%b //ch1 Table 21", ch1_out_chnl_ctrl_21); $fdisplay(dbg_file, "%b //ch2 Table 21", ch2_out_chnl_ctrl_21); $fdisplay(dbg_file, "%b //ch3 Table 21", ch3_out_chnl_ctrl_21); $fdisplay(dbg_file, "Table22: RXPCS Control Register 18"); $fdisplay(dbg_file, "%b //ch0 Table 22", ch0_out_chnl_ctrl_22); $fdisplay(dbg_file, "%b //ch1 Table 22", ch1_out_chnl_ctrl_22); $fdisplay(dbg_file, "%b //ch2 Table 22", ch2_out_chnl_ctrl_22); $fdisplay(dbg_file, "%b //ch3 Table 22", ch3_out_chnl_ctrl_22); $fdisplay(dbg_file, "Table23: RXPCS Control Register 19"); $fdisplay(dbg_file, "%b //ch0 Table 23", ch0_out_chnl_ctrl_23); $fdisplay(dbg_file, "%b //ch1 Table 23", ch1_out_chnl_ctrl_23); $fdisplay(dbg_file, "%b //ch2 Table 23", ch2_out_chnl_ctrl_23); $fdisplay(dbg_file, "%b //ch3 Table 23", ch3_out_chnl_ctrl_23); $fdisplay(dbg_file, "Table24: RXPCS Control Register 20"); $fdisplay(dbg_file, "%b //ch0 Table 24", ch0_out_chnl_ctrl_24); $fdisplay(dbg_file, "%b //ch1 Table 24", ch1_out_chnl_ctrl_24); $fdisplay(dbg_file, "%b //ch2 Table 24", ch2_out_chnl_ctrl_24); $fdisplay(dbg_file, "%b //ch3 Table 24", ch3_out_chnl_ctrl_24); $fdisplay(dbg_file, "Table25: RXPCS Control Register 21"); $fdisplay(dbg_file, "%b //ch0 Table 25", ch0_out_chnl_ctrl_25); $fdisplay(dbg_file, "%b //ch1 Table 25", ch1_out_chnl_ctrl_25); $fdisplay(dbg_file, "%b //ch2 Table 25", ch2_out_chnl_ctrl_25); $fdisplay(dbg_file, "%b //ch3 Table 25", ch3_out_chnl_ctrl_25); $fdisplay(dbg_file, "Table26: RXPCS Control Register 22"); $fdisplay(dbg_file, "%b //ch0 Table 26", ch0_out_chnl_ctrl_26); $fdisplay(dbg_file, "%b //ch1 Table 26", ch1_out_chnl_ctrl_26); $fdisplay(dbg_file, "%b //ch2 Table 26", ch2_out_chnl_ctrl_26); $fdisplay(dbg_file, "%b //ch3 Table 26", ch3_out_chnl_ctrl_26); $fdisplay(dbg_file, "Table27: RXPCS Control Register 23"); $fdisplay(dbg_file, "%b //ch0 Table 27", ch0_out_chnl_ctrl_27); $fdisplay(dbg_file, "%b //ch1 Table 27", ch1_out_chnl_ctrl_27); $fdisplay(dbg_file, "%b //ch2 Table 27", ch2_out_chnl_ctrl_27); $fdisplay(dbg_file, "%b //ch3 Table 27", ch3_out_chnl_ctrl_27); $fdisplay(dbg_file, "Table28: TXPMA Control Register 1"); $fdisplay(dbg_file, "%b //ch0 Table 28", ch0_out_chnl_ctrl_28); $fdisplay(dbg_file, "%b //ch1 Table 28", ch1_out_chnl_ctrl_28); $fdisplay(dbg_file, "%b //ch2 Table 28", ch2_out_chnl_ctrl_28); $fdisplay(dbg_file, "%b //ch3 Table 28", ch3_out_chnl_ctrl_28); $fdisplay(dbg_file, "Table29: TXPMA Control Register 2"); $fdisplay(dbg_file, "%b //ch0 Table 29", ch0_out_chnl_ctrl_29); $fdisplay(dbg_file, "%b //ch1 Table 29", ch1_out_chnl_ctrl_29); $fdisplay(dbg_file, "%b //ch2 Table 29", ch2_out_chnl_ctrl_29); $fdisplay(dbg_file, "%b //ch3 Table 29", ch3_out_chnl_ctrl_29); $fdisplay(dbg_file, "Table30: TXPMA Control Register 3"); $fdisplay(dbg_file, "%b //ch0 Table 30", ch0_out_chnl_ctrl_30); $fdisplay(dbg_file, "%b //ch1 Table 30", ch1_out_chnl_ctrl_30); $fdisplay(dbg_file, "%b //ch2 Table 30", ch2_out_chnl_ctrl_30); $fdisplay(dbg_file, "%b //ch3 Table 30", ch3_out_chnl_ctrl_30); $fdisplay(dbg_file, "Table31: TXPMA Control Register 4"); $fdisplay(dbg_file, "%b //ch0 Table 31", ch0_out_chnl_ctrl_31); $fdisplay(dbg_file, "%b //ch1 Table 31", ch1_out_chnl_ctrl_31); $fdisplay(dbg_file, "%b //ch2 Table 31", ch2_out_chnl_ctrl_31); $fdisplay(dbg_file, "%b //ch3 Table 31", ch3_out_chnl_ctrl_31); $fdisplay(dbg_file, "Table32: TXPMA Control Register 5"); $fdisplay(dbg_file, "%b //ch0 Table 32", ch0_out_chnl_ctrl_32); $fdisplay(dbg_file, "%b //ch1 Table 32", ch1_out_chnl_ctrl_32); $fdisplay(dbg_file, "%b //ch2 Table 32", ch2_out_chnl_ctrl_32); $fdisplay(dbg_file, "%b //ch3 Table 32", ch3_out_chnl_ctrl_32); $fdisplay(dbg_file, "Table33: TXPMA Control Register 6"); $fdisplay(dbg_file, "%b //ch0 Table 33", ch0_out_chnl_ctrl_33); $fdisplay(dbg_file, "%b //ch1 Table 33", ch1_out_chnl_ctrl_33); $fdisplay(dbg_file, "%b //ch2 Table 33", ch2_out_chnl_ctrl_33); $fdisplay(dbg_file, "%b //ch3 Table 33", ch3_out_chnl_ctrl_33); $fdisplay(dbg_file, "Table34: TXPMA Control Register 7"); $fdisplay(dbg_file, "%b //ch0 Table 34", ch0_out_chnl_ctrl_34); $fdisplay(dbg_file, "%b //ch1 Table 34", ch1_out_chnl_ctrl_34); $fdisplay(dbg_file, "%b //ch2 Table 34", ch2_out_chnl_ctrl_34); $fdisplay(dbg_file, "%b //ch3 Table 34", ch3_out_chnl_ctrl_34); $fdisplay(dbg_file, "Table35: TXPMA Control Register 8"); $fdisplay(dbg_file, "%b //ch0 Table 35", ch0_out_chnl_ctrl_35); $fdisplay(dbg_file, "%b //ch1 Table 35", ch1_out_chnl_ctrl_35); $fdisplay(dbg_file, "%b //ch2 Table 35", ch2_out_chnl_ctrl_35); $fdisplay(dbg_file, "%b //ch3 Table 35", ch3_out_chnl_ctrl_35); $fdisplay(dbg_file, "Table36: RXPMA Control Register 1"); $fdisplay(dbg_file, "%b //ch0 Table 36", ch0_out_chnl_ctrl_36); $fdisplay(dbg_file, "%b //ch1 Table 36", ch1_out_chnl_ctrl_36); $fdisplay(dbg_file, "%b //ch2 Table 36", ch2_out_chnl_ctrl_36); $fdisplay(dbg_file, "%b //ch3 Table 36", ch3_out_chnl_ctrl_36); $fdisplay(dbg_file, "Table37: RXPMA Control Register 2"); $fdisplay(dbg_file, "%b //ch0 Table 37", ch0_out_chnl_ctrl_37); $fdisplay(dbg_file, "%b //ch1 Table 37", ch1_out_chnl_ctrl_37); $fdisplay(dbg_file, "%b //ch2 Table 37", ch2_out_chnl_ctrl_37); $fdisplay(dbg_file, "%b //ch3 Table 37", ch3_out_chnl_ctrl_37); $fdisplay(dbg_file, "Table38: RXPMA Control Register 3"); $fdisplay(dbg_file, "%b //ch0 Table 38", ch0_out_chnl_ctrl_38); $fdisplay(dbg_file, "%b //ch1 Table 38", ch1_out_chnl_ctrl_38); $fdisplay(dbg_file, "%b //ch2 Table 38", ch2_out_chnl_ctrl_38); $fdisplay(dbg_file, "%b //ch3 Table 38", ch3_out_chnl_ctrl_38); $fdisplay(dbg_file, "Table39: RXPMA Control Register 4"); $fdisplay(dbg_file, "%b //ch0 Table 39", ch0_out_chnl_ctrl_39); $fdisplay(dbg_file, "%b //ch1 Table 39", ch1_out_chnl_ctrl_39); $fdisplay(dbg_file, "%b //ch2 Table 39", ch2_out_chnl_ctrl_39); $fdisplay(dbg_file, "%b //ch3 Table 39", ch3_out_chnl_ctrl_39); $fdisplay(dbg_file, "Table40: RXPMA Control Register 5"); $fdisplay(dbg_file, "%b //ch0 Table 40", ch0_out_chnl_ctrl_40); $fdisplay(dbg_file, "%b //ch1 Table 40", ch1_out_chnl_ctrl_40); $fdisplay(dbg_file, "%b //ch2 Table 40", ch2_out_chnl_ctrl_40); $fdisplay(dbg_file, "%b //ch3 Table 40", ch3_out_chnl_ctrl_40); $fdisplay(dbg_file, "Table41: RXPMA Control Register 6"); $fdisplay(dbg_file, "%b //ch0 Table 41", ch0_out_chnl_ctrl_41); $fdisplay(dbg_file, "%b //ch1 Table 41", ch1_out_chnl_ctrl_41); $fdisplay(dbg_file, "%b //ch2 Table 41", ch2_out_chnl_ctrl_41); $fdisplay(dbg_file, "%b //ch3 Table 41", ch3_out_chnl_ctrl_41); $fdisplay(dbg_file, "Table42: RXPMA Control Register 7"); $fdisplay(dbg_file, "%b //ch0 Table 42", ch0_out_chnl_ctrl_42); $fdisplay(dbg_file, "%b //ch1 Table 42", ch1_out_chnl_ctrl_42); $fdisplay(dbg_file, "%b //ch2 Table 42", ch2_out_chnl_ctrl_42); $fdisplay(dbg_file, "%b //ch3 Table 42", ch3_out_chnl_ctrl_42); //$fdisplay(dbg_file, "Table43: RXPMA Control Register 8"); //$fdisplay(dbg_file, "%b //ch0 Table 43", ch0_out_chnl_ctrl_43); //$fdisplay(dbg_file, "%b //ch1 Table 43", ch1_out_chnl_ctrl_43); //$fdisplay(dbg_file, "%b //ch2 Table 43", ch2_out_chnl_ctrl_43); //$fdisplay(dbg_file, "%b //ch3 Table 43", ch3_out_chnl_ctrl_43); $fdisplay(dbg_file, "Table44: RXPMA Control Register 9"); $fdisplay(dbg_file, "%b //ch0 Table 44", ch0_out_chnl_ctrl_44); $fdisplay(dbg_file, "%b //ch1 Table 44", ch1_out_chnl_ctrl_44); $fdisplay(dbg_file, "%b //ch2 Table 44", ch2_out_chnl_ctrl_44); $fdisplay(dbg_file, "%b //ch3 Table 44", ch3_out_chnl_ctrl_44); $fdisplay(dbg_file, "Table45: RXPMA Control Register 10"); $fdisplay(dbg_file, "%b //ch0 Table 45", ch0_out_chnl_ctrl_45); $fdisplay(dbg_file, "%b //ch1 Table 45", ch1_out_chnl_ctrl_45); $fdisplay(dbg_file, "%b //ch2 Table 45", ch2_out_chnl_ctrl_45); $fdisplay(dbg_file, "%b //ch3 Table 45", ch3_out_chnl_ctrl_45); $fdisplay(dbg_file, "Table46: RXPMA Control Register 11"); $fdisplay(dbg_file, "%b //ch0 Table 46", ch0_out_chnl_ctrl_46); $fdisplay(dbg_file, "%b //ch1 Table 46", ch1_out_chnl_ctrl_46); $fdisplay(dbg_file, "%b //ch2 Table 46", ch2_out_chnl_ctrl_46); $fdisplay(dbg_file, "%b //ch3 Table 46", ch3_out_chnl_ctrl_46); $fdisplay(dbg_file, "Table47: RXPMA Control Register 12"); $fdisplay(dbg_file, "%b //ch0 Table 47", ch0_out_chnl_ctrl_47); $fdisplay(dbg_file, "%b //ch1 Table 47", ch1_out_chnl_ctrl_47); $fdisplay(dbg_file, "%b //ch2 Table 47", ch2_out_chnl_ctrl_47); $fdisplay(dbg_file, "%b //ch3 Table 47", ch3_out_chnl_ctrl_47); $fdisplay(dbg_file, "Table48: RXPMA Control Register 13"); $fdisplay(dbg_file, "%b //ch0 Table 48", ch0_out_chnl_ctrl_48); $fdisplay(dbg_file, "%b //ch1 Table 48", ch1_out_chnl_ctrl_48); $fdisplay(dbg_file, "%b //ch2 Table 48", ch2_out_chnl_ctrl_48); $fdisplay(dbg_file, "%b //ch3 Table 48", ch3_out_chnl_ctrl_48); $fdisplay(dbg_file, "Table49: RXPMA Control Register 14"); $fdisplay(dbg_file, "%b //ch0 Table 49", ch0_out_chnl_ctrl_49); $fdisplay(dbg_file, "%b //ch1 Table 49", ch1_out_chnl_ctrl_49); $fdisplay(dbg_file, "%b //ch2 Table 49", ch2_out_chnl_ctrl_49); $fdisplay(dbg_file, "%b //ch3 Table 49", ch3_out_chnl_ctrl_49); $fdisplay(dbg_file, "Table50: RXPMA Control Register 15"); $fdisplay(dbg_file, "%b //ch0 Table 50", ch0_out_chnl_ctrl_50); $fdisplay(dbg_file, "%b //ch1 Table 50", ch1_out_chnl_ctrl_50); $fdisplay(dbg_file, "%b //ch2 Table 50", ch2_out_chnl_ctrl_50); $fdisplay(dbg_file, "%b //ch3 Table 50", ch3_out_chnl_ctrl_50); $fdisplay(dbg_file, "Table51: RXPMA Control Register 16"); $fdisplay(dbg_file, "%b //ch0 Table 51", ch0_out_chnl_ctrl_51); $fdisplay(dbg_file, "%b //ch1 Table 51", ch1_out_chnl_ctrl_51); $fdisplay(dbg_file, "%b //ch2 Table 51", ch2_out_chnl_ctrl_51); $fdisplay(dbg_file, "%b //ch3 Table 51", ch3_out_chnl_ctrl_51); $fdisplay(dbg_file, "Table52: RXPMA Control Register 17"); $fdisplay(dbg_file, "%b //ch0 Table 52", ch0_out_chnl_ctrl_52); $fdisplay(dbg_file, "%b //ch1 Table 52", ch1_out_chnl_ctrl_52); $fdisplay(dbg_file, "%b //ch2 Table 52", ch2_out_chnl_ctrl_52); $fdisplay(dbg_file, "%b //ch3 Table 52", ch3_out_chnl_ctrl_52); $fdisplay(dbg_file, "Table53: RXPMA Control Register 18"); $fdisplay(dbg_file, "%b //ch0 Table 53", ch0_out_chnl_ctrl_53); $fdisplay(dbg_file, "%b //ch1 Table 53", ch1_out_chnl_ctrl_53); $fdisplay(dbg_file, "%b //ch2 Table 53", ch2_out_chnl_ctrl_53); $fdisplay(dbg_file, "%b //ch3 Table 53", ch3_out_chnl_ctrl_53); $fdisplay(dbg_file, ""); $fclose(dbg_file); // auto generated dump code - end end end endmodule `timescale 1 ps / 1 ps module stratixiv_hssi_cmu_dprio_top( sync_status, align_status, mdio_in, mdc, port_addr, dev_addr, mdio_dis, dprioload, mdio_rst, cmudividerdprioin, cmuplldprioin, // cmudprioin, refclkdividerdprioin, rxpcsdprioin, rxpmadprioin, txpcsdprioin, txpmadprioin, cmudividerdprioout, cmuplldprioout, // cmudprioout, refclkdividerdprioout, rxpcsdprioout, rxpmadprioout, txpcsdprioout, txpmadprioout, mdio_out, data_enable_n, mdio_curr_st ); // -------------------- Simulation only parameters ---------------------------- parameter clkdiv0_inclk0_logical_to_physical_mapping = "pll0"; parameter clkdiv0_inclk1_logical_to_physical_mapping = "pll1"; parameter clkdiv1_inclk0_logical_to_physical_mapping = "pll0"; parameter clkdiv1_inclk1_logical_to_physical_mapping = "pll1"; parameter clkdiv2_inclk0_logical_to_physical_mapping = "pll0"; parameter clkdiv2_inclk1_logical_to_physical_mapping = "pll1"; parameter clkdiv3_inclk0_logical_to_physical_mapping = "pll0"; parameter clkdiv3_inclk1_logical_to_physical_mapping = "pll1"; parameter clkdiv4_inclk0_logical_to_physical_mapping = "pll0"; parameter clkdiv4_inclk1_logical_to_physical_mapping = "pll1"; parameter clkdiv5_inclk0_logical_to_physical_mapping = "pll0"; parameter clkdiv5_inclk1_logical_to_physical_mapping = "pll1"; parameter pll0_inclk0_logical_to_physical_mapping = "clkrefclk0"; parameter pll0_inclk1_logical_to_physical_mapping = "clkrefclk1"; parameter pll0_inclk2_logical_to_physical_mapping = "iq2"; parameter pll0_inclk3_logical_to_physical_mapping = "iq3"; parameter pll0_inclk4_logical_to_physical_mapping = "iq4"; parameter pll0_inclk5_logical_to_physical_mapping = "iq5"; parameter pll0_inclk6_logical_to_physical_mapping = "iq6"; parameter pll0_inclk7_logical_to_physical_mapping = "iq7"; parameter pll0_inclk8_logical_to_physical_mapping = "pld_clk"; parameter pll0_inclk9_logical_to_physical_mapping = "gpll_clk"; parameter pll1_inclk0_logical_to_physical_mapping = "clkrefclk0"; parameter pll1_inclk1_logical_to_physical_mapping = "clkrefclk1"; parameter pll1_inclk2_logical_to_physical_mapping = "iq2"; parameter pll1_inclk3_logical_to_physical_mapping = "iq3"; parameter pll1_inclk4_logical_to_physical_mapping = "iq4"; parameter pll1_inclk5_logical_to_physical_mapping = "iq5"; parameter pll1_inclk6_logical_to_physical_mapping = "iq6"; parameter pll1_inclk7_logical_to_physical_mapping = "iq7"; parameter pll1_inclk8_logical_to_physical_mapping = "pld_clk"; parameter pll1_inclk9_logical_to_physical_mapping = "gpll_clk"; parameter pll2_inclk0_logical_to_physical_mapping = "clkrefclk0"; parameter pll2_inclk1_logical_to_physical_mapping = "clkrefclk1"; parameter pll2_inclk2_logical_to_physical_mapping = "iq2"; parameter pll2_inclk3_logical_to_physical_mapping = "iq3"; parameter pll2_inclk4_logical_to_physical_mapping = "iq4"; parameter pll2_inclk5_logical_to_physical_mapping = "iq5"; parameter pll2_inclk6_logical_to_physical_mapping = "iq6"; parameter pll2_inclk7_logical_to_physical_mapping = "iq7"; parameter pll2_inclk8_logical_to_physical_mapping = "pld_clk"; parameter pll2_inclk9_logical_to_physical_mapping = "gpll_clk"; parameter pll3_inclk0_logical_to_physical_mapping = "clkrefclk0"; parameter pll3_inclk1_logical_to_physical_mapping = "clkrefclk1"; parameter pll3_inclk2_logical_to_physical_mapping = "iq2"; parameter pll3_inclk3_logical_to_physical_mapping = "iq3"; parameter pll3_inclk4_logical_to_physical_mapping = "iq4"; parameter pll3_inclk5_logical_to_physical_mapping = "iq5"; parameter pll3_inclk6_logical_to_physical_mapping = "iq6"; parameter pll3_inclk7_logical_to_physical_mapping = "iq7"; parameter pll3_inclk8_logical_to_physical_mapping = "pld_clk"; parameter pll3_inclk9_logical_to_physical_mapping = "gpll_clk"; parameter pll4_inclk0_logical_to_physical_mapping = "clkrefclk0"; parameter pll4_inclk1_logical_to_physical_mapping = "clkrefclk1"; parameter pll4_inclk2_logical_to_physical_mapping = "iq2"; parameter pll4_inclk3_logical_to_physical_mapping = "iq3"; parameter pll4_inclk4_logical_to_physical_mapping = "iq4"; parameter pll4_inclk5_logical_to_physical_mapping = "iq5"; parameter pll4_inclk6_logical_to_physical_mapping = "iq6"; parameter pll4_inclk7_logical_to_physical_mapping = "iq7"; parameter pll4_inclk8_logical_to_physical_mapping = "pld_clk"; parameter pll4_inclk9_logical_to_physical_mapping = "gpll_clk"; parameter pll5_inclk0_logical_to_physical_mapping = "clkrefclk0"; parameter pll5_inclk1_logical_to_physical_mapping = "clkrefclk1"; parameter pll5_inclk2_logical_to_physical_mapping = "iq2"; parameter pll5_inclk3_logical_to_physical_mapping = "iq3"; parameter pll5_inclk4_logical_to_physical_mapping = "iq4"; parameter pll5_inclk5_logical_to_physical_mapping = "iq5"; parameter pll5_inclk6_logical_to_physical_mapping = "iq6"; parameter pll5_inclk7_logical_to_physical_mapping = "iq7"; parameter pll5_inclk8_logical_to_physical_mapping = "pld_clk"; parameter pll5_inclk9_logical_to_physical_mapping = "gpll_clk"; parameter pll0_logical_to_physical_mapping = 0 ; parameter pll1_logical_to_physical_mapping = 1 ; parameter pll2_logical_to_physical_mapping = 2 ; parameter pll3_logical_to_physical_mapping = 3 ; parameter pll4_logical_to_physical_mapping = 4 ; parameter pll5_logical_to_physical_mapping = 5 ; parameter refclk_divider0_logical_to_physical_mapping = 0 ; parameter refclk_divider1_logical_to_physical_mapping = 1 ; parameter rx0_logical_to_physical_mapping = 0 ; parameter rx1_logical_to_physical_mapping = 1 ; parameter rx2_logical_to_physical_mapping = 2 ; parameter rx3_logical_to_physical_mapping = 3 ; parameter rx4_logical_to_physical_mapping = 4 ; parameter rx5_logical_to_physical_mapping = 5 ; parameter tx0_logical_to_physical_mapping = 0 ; parameter tx1_logical_to_physical_mapping = 1 ; parameter tx2_logical_to_physical_mapping = 2 ; parameter tx3_logical_to_physical_mapping = 3 ; parameter tx4_logical_to_physical_mapping = 4 ; parameter tx5_logical_to_physical_mapping = 5 ; parameter tx0_pma_inclk0_logical_to_physical_mapping = "x1"; parameter tx0_pma_inclk1_logical_to_physical_mapping = "x4"; parameter tx0_pma_inclk2_logical_to_physical_mapping = "xn_top"; parameter tx0_pma_inclk3_logical_to_physical_mapping = "xn_bottom"; parameter tx0_pma_inclk4_logical_to_physical_mapping = "hypertransport"; parameter tx1_pma_inclk0_logical_to_physical_mapping = "x1"; parameter tx1_pma_inclk1_logical_to_physical_mapping = "x4"; parameter tx1_pma_inclk2_logical_to_physical_mapping = "xn_top"; parameter tx1_pma_inclk3_logical_to_physical_mapping = "xn_bottom"; parameter tx1_pma_inclk4_logical_to_physical_mapping = "hypertransport"; parameter tx2_pma_inclk0_logical_to_physical_mapping = "x1"; parameter tx2_pma_inclk1_logical_to_physical_mapping = "x4"; parameter tx2_pma_inclk2_logical_to_physical_mapping = "xn_top"; parameter tx2_pma_inclk3_logical_to_physical_mapping = "xn_bottom"; parameter tx2_pma_inclk4_logical_to_physical_mapping = "hypertransport"; parameter tx3_pma_inclk0_logical_to_physical_mapping = "x1"; parameter tx3_pma_inclk1_logical_to_physical_mapping = "x4"; parameter tx3_pma_inclk2_logical_to_physical_mapping = "xn_top"; parameter tx3_pma_inclk3_logical_to_physical_mapping = "xn_bottom"; parameter tx3_pma_inclk4_logical_to_physical_mapping = "hypertransport"; parameter tx4_pma_inclk0_logical_to_physical_mapping = "x1"; parameter tx4_pma_inclk1_logical_to_physical_mapping = "x4"; parameter tx4_pma_inclk2_logical_to_physical_mapping = "xn_top"; parameter tx4_pma_inclk3_logical_to_physical_mapping = "xn_bottom"; parameter tx4_pma_inclk4_logical_to_physical_mapping = "hypertransport"; parameter tx5_pma_inclk0_logical_to_physical_mapping = "x1"; parameter tx5_pma_inclk1_logical_to_physical_mapping = "x4"; parameter tx5_pma_inclk2_logical_to_physical_mapping = "xn_top"; parameter tx5_pma_inclk3_logical_to_physical_mapping = "xn_bottom"; parameter tx5_pma_inclk4_logical_to_physical_mapping = "hypertransport"; // external parameters // DEBUG dump parameter sim_dump_dprio_internal_reg_at_time = 0; // in ps parameter sim_dump_filename = "sim_dprio_dump.txt"; input [3:0] sync_status; input align_status; // MDIO inputs/outpus input mdio_in; input mdc; input [4:0] port_addr; input [4:0] dev_addr; input mdio_rst; input mdio_dis; // 1'b1=output CRAM (para), 1'b0=output MDIO control register input dprioload; // load MDIO control register with CRAM_ext (parameter). SER_SHFIT_LOAD? input [599 : 0] cmudividerdprioin; input [1799 : 0] cmuplldprioin; input [1 : 0] refclkdividerdprioin; input [1599 : 0] rxpcsdprioin; input [1799 : 0] rxpmadprioin; input [599 : 0] txpcsdprioin; input [1799 : 0] txpmadprioin; output [599 : 0] cmudividerdprioout; output [1799 : 0] cmuplldprioout; output [1 : 0] refclkdividerdprioout; output [1599 : 0] rxpcsdprioout; output [1799 : 0] rxpmadprioout; output [599 : 0] txpcsdprioout; output [1799 : 0] txpmadprioout; output mdio_out; output data_enable_n; output [2:0] mdio_curr_st; // -------------------------------------------------------------------- // status reg --------------------------------------------------------- // -------------------------------------------------------------------- wire gnd_wire; wire vcc_wire; wire so_status; wire rxs_link_status_set; wire rtx_rx_local_fault_clr; // -------------------------------------------------------------------- // interface to channel ----------------------------------------------- // -------------------------------------------------------------------- wire [831:0] csr_chnl_in_ch0; // CSR inputs wire [831:0] csr_chnl_in_ch1; // CSR inputs wire [831:0] csr_chnl_in_ch2; // CSR inputs wire [831:0] csr_chnl_in_ch3; // CSR inputs wire [15:0] csr_chnl_in_reserved_ch0; wire [15:0] csr_chnl_in_reserved_ch1; wire [15:0] csr_chnl_in_reserved_ch2; wire [15:0] csr_chnl_in_reserved_ch3; wire [3:0] dprio_chnl_id0; // DPRIO channel base address ID wire [3:0] dprio_chnl_id1; // DPRIO channel base address ID wire [3:0] dprio_chnl_id2; // DPRIO channel base address ID wire [3:0] dprio_chnl_id3; // DPRIO channel base address ID wire si_ch0; wire si_ch1; wire si_ch2; wire si_ch3; wire [831:0] dp_chnl_out_ch0; // wire [831:0] dp_chnl_out_ch1; // wire [831:0] dp_chnl_out_ch2; // wire [831:0] dp_chnl_out_ch3; // wire [15:0] dp_chnl_out_reserved_ch0; wire [15:0] dp_chnl_out_reserved_ch1; wire [15:0] dp_chnl_out_reserved_ch2; wire [15:0] dp_chnl_out_reserved_ch3; wire so_ch0; wire so_ch1; wire so_ch2; wire so_ch3; wire [15:0] mbus_out_ch0; wire [15:0] mbus_out_ch1; wire [15:0] mbus_out_ch2; wire [15:0] mbus_out_ch3; // -------------------------------------------------------------------- // interface to cmu --------------------------------------------------- // -------------------------------------------------------------------- wire [703:0] csr_centrl_in; // CSR inputs wire [31:0] csr_centrl_in_reserved; wire si_centrl; wire [703:0] dp_centrl_out; // CSR inputs wire [31:0] dp_centrl_out_reserved; wire [15:0] mbus_out_centrl; wire so_centrl; // -------------------------------------------------------------------- // new in STRATIXIV common -------------------------------------------------- // -------------------------------------------------------------------- // input -------------------- // PLD dynamic signal for PMA DPRIO cell for coverage for PE/TE wire pma_cram_test; wire serial_mode; // unused ports to be moved into reg wire jtag_mode; wire jtag_shift_load; wire jtag_si; wire jtag_so; // wire // status signals generated by PCS wire tx_local_fault; // from tx_sm wire rx_local_fault; // from rcv_sm wire xs_link_status; // from rcv_sm wire local_fault_ext; // Status signal wire wire xs_link_status_ext; // Status signal wire wire rx_local_fault_ext; // Status signal wire wire tx_local_fault_ext; // Status signal wire // interconnect wires -------------------------------------------------- // wires from addr wire [15:0] reg_addr; // addr --> reg // wires from sm wire shift_addr; // sm --> addr wire incr_addr; // sm --> addr wire ld_cnt; // sm --> cnt wire [4:0] cnt_val; // sm --> cnt wire ld_data; // sm --> cnt wire shift_in; // sm --> ctl_data wire shift_out; // sm --> ctl_data wire latch_ctl; // sm --> ctl_data wire valid_addr_lt; // sm --> ctl_data wire mdio_wr; // sm --> reg wire mdio_rd; // sm --> reg wire [2:0] curr_state; // sm --> top (../../pcs_central_testbus in central_chnnl) // wires from cnt wire cnt_eq_0; // cnt --> sm // wires from ctl_data wire [15:0] mbus_in; // ctl_data --> reg wire valid_addr; // ctl_data --> sm wire [1:0] opcode; // ctl_data --> sm wire mdio_out; // ctl_data --> top wire data_enable_n; // ctl_data --> top // wires from reg wire [15:0] mbus_out; // reg --> ctl_data //wires to reg wire dev_addr_0; // primary input/output connections --------------------------------------- // outputs assign mdio_curr_st = curr_state; // from SM // module instantiatations ------------------------------------------------ stratixiv_hssi_cmu_dprio_addr mdio_addr_1 ( .reset (mdio_rst), // from top .mdc (mdc), // from top .mdio_in (mdio_in), // from top .shift_addr (shift_addr), // from sm .incr_addr (incr_addr), // from sm .reg_addr (reg_addr) // To (16-bit reg addr) reg ); stratixiv_hssi_cmu_dprio_cnt mdio_cnt_1 ( .reset (mdio_rst), .mdc (mdc), .ld_cnt (ld_cnt), // from sm .cnt_val (cnt_val), // from sm .cnt_eq_0 (cnt_eq_0) // to sm ); stratixiv_hssi_cmu_dprio_sm mdio_sm_1 ( .reset (mdio_rst), .mdio_in (mdio_in), // from top .mdc (mdc), .opcode (opcode), // from ctl_data .valid_addr (valid_addr), // from ctl_data .cnt_eq_0 (cnt_eq_0), // from cnt .shift_addr (shift_addr), // to addr .incr_addr (incr_addr), // to addr .mdio_wr (mdio_wr), // to reg .mdio_rd (mdio_rd), // to reg .shift_in (shift_in), // to ctl_data .shift_out (shift_out), // to ctl_data .latch_ctl (latch_ctl), // to ctl_data .ld_data (ld_data), // to ctl_data .valid_addr_lt(valid_addr_lt), // to cnt_data .ld_cnt (ld_cnt), // to cnt .cnt_val (cnt_val), // to cnt (5-bit) .curr_state (curr_state) // to top ); stratixiv_hssi_cmu_dprio_ctl_data mdio_ctl_data_1 ( .reset (mdio_rst), .mdc (mdc), .mdio_in (mdio_in), .shift_in (shift_in), // from sm .shift_out (shift_out), // frm sm .ld_data (ld_data), // from sm .latch_ctl (latch_ctl), // from sm .port_addr (port_addr), .dev_addr (dev_addr), .valid_addr_lt(valid_addr_lt), // from sm .mbus_out (mbus_out), // from reg .mdio_out (mdio_out), // to top .mbus_in (mbus_in), // to reg .opcode (opcode), // to sm .valid_addr (valid_addr), // to sm .data_enable_n (data_enable_n) // to top ); // -------------------------------------------------------------------- // Status registers and MBUS_OUT muxing for whole QUAD ---------------- // -------------------------------------------------------------------- assign gnd_wire = 1'b0; assign vcc_wire = 1'b1; assign dev_addr_0 = dev_addr[0]; stratixiv_hssi_cmu_dprio_status status_reg ( .mdio_rst(mdio_rst), .mdio_rd(mdio_rd), .reg_addr(reg_addr), .dev_addr_0(dev_addr[0]), .mdc(mdc), .serial_mode(gnd_wire), .ser_shift_load(1'b0), .si(1'b0), .mbus_out_ch0(mbus_out_ch0), .mbus_out_ch1(mbus_out_ch1), .mbus_out_ch2(mbus_out_ch2), .mbus_out_ch3(mbus_out_ch3), .mbus_out_centrl(mbus_out_centrl), .align_status(align_status), .sync_status(sync_status), .xs_link_status(xs_link_status), .rx_local_fault(rx_local_fault), .tx_local_fault(tx_local_fault), .rxs_link_status_set(rxs_link_status_set), .rtx_rx_local_fault_clr(rtx_rx_local_fault_clr), .mbus_out(mbus_out), // to ctrl_data .so(so_status) ); // -------------------------------------------------------------------- // common ------------------------------------------------------------- // -------------------------------------------------------------------- assign pma_cram_test = 1'b0; assign serial_mode = 1'b0; // -------------------------------------------------------------------- // cmu --------------------------------------------------------------- // -------------------------------------------------------------------- assign si_centrl = 1'bx; stratixiv_hssi_cmu_dprio_centrl_top md_reg_centrl ( .mdio_rst(mdio_rst), // from top .mdio_wr(mdio_wr), // from sm .reg_addr(reg_addr), // from addr .mdc(mdc), // from top .mbus_in(mbus_in), // from ctrl_data .serial_mode(serial_mode), // new: .mdio_dis (mdio_dis), // from top .pma_cram_test (pma_cram_test), // new: // .dprioload(dprioload), // from top .ser_shift_load(dprioload), // from top .si(si_centrl), // new .csr_centrl_in(csr_centrl_in), // new - from map .csr_centrl_in_reserved(csr_centrl_in_reserved), // .align_status (align_status), // moved to status_reg_ctrl // .sync_status (sync_status), // moved to status_reg_ctrl // .mdio_rd(mdio_rd), // moved to status_reg_ctrl // .dev_addr_0 (dev_addr_0), // moved to status_reg_ctrl .dp_centrl_out(dp_centrl_out), // to map then to others .dp_centrl_out_reserved(dp_centrl_out_reserved), .so(so_centrl), // to ctrl_data .mbus_out(mbus_out_centrl) // to status_reg ); // -------------------------------------------------------------------- // channel ------------------------------------------------------------ // -------------------------------------------------------------------- assign dprio_chnl_id0 = 4'h0; assign dprio_chnl_id1 = 4'h1; assign dprio_chnl_id2 = 4'h2; assign dprio_chnl_id3 = 4'h3; assign si_ch0 = 1'bx; assign si_ch1 = 1'bx; assign si_ch2 = 1'bx; assign si_ch3 = 1'bx; stratixiv_hssi_cmu_dprio_chnl_top md_reg_ch0 ( .mdio_rst(mdio_rst), // from top .mdio_wr(mdio_wr), // from sm .reg_addr(reg_addr), // from addr .mdc(mdc), // from top .mbus_in(mbus_in), // from ctrl_data .serial_mode(serial_mode), // new: .mdio_dis (mdio_dis), // from top .pma_cram_test (pma_cram_test), // new: .ser_shift_load(dprioload), // from top .si(si_ch0), // new .csr_chnl_in(csr_chnl_in_ch0), // new - from map .csr_chnl_in_reserved(csr_chnl_in_reserved_ch0), .dprio_chnl_id(dprio_chnl_id0), // new - not in centrl .dp_chnl_out(dp_chnl_out_ch0), // to map then others .dp_chnl_out_reserved(dp_chnl_out_reserved_ch0), .so(so_ch0), // to ctrl_data .mbus_out(mbus_out_ch0) // to status_reg ); stratixiv_hssi_cmu_dprio_chnl_top md_reg_ch1 ( .mdio_rst(mdio_rst), // from top .mdio_wr(mdio_wr), // from sm .reg_addr(reg_addr), // from addr .mdc(mdc), // from top .mbus_in(mbus_in), // from ctrl_data .serial_mode(serial_mode), // new: .mdio_dis (mdio_dis), // from top .pma_cram_test (pma_cram_test), // new: .ser_shift_load(dprioload), // from top .si(si_ch1), // new .csr_chnl_in(csr_chnl_in_ch1), // new .csr_chnl_in_reserved(csr_chnl_in_reserved_ch1), .dprio_chnl_id(dprio_chnl_id1), // new - not in centrl .dp_chnl_out(dp_chnl_out_ch1), // to top .dp_chnl_out_reserved(dp_chnl_out_reserved_ch1), .so(so_ch1), // to ctrl_data .mbus_out(mbus_out_ch1) // to status_reg ); stratixiv_hssi_cmu_dprio_chnl_top md_reg_ch2 ( .mdio_rst(mdio_rst), // from top .mdio_wr(mdio_wr), // from sm .reg_addr(reg_addr), // from addr .mdc(mdc), // from top .mbus_in(mbus_in), // from ctrl_data .serial_mode(serial_mode), // new: .mdio_dis (mdio_dis), // from top .pma_cram_test (pma_cram_test), // new: .ser_shift_load(dprioload), // from top .si(si_ch2), // new .csr_chnl_in(csr_chnl_in_ch2), // new .csr_chnl_in_reserved(csr_chnl_in_reserved_ch2), .dprio_chnl_id(dprio_chnl_id2), // new - not in centrl .dp_chnl_out(dp_chnl_out_ch2), // to top .dp_chnl_out_reserved(dp_chnl_out_reserved_ch2), .so(so_ch2), // to ctrl_data .mbus_out(mbus_out_ch2) // to status_reg ); stratixiv_hssi_cmu_dprio_chnl_top md_reg_ch3 ( .mdio_rst(mdio_rst), // from top .mdio_wr(mdio_wr), // from sm .reg_addr(reg_addr), // from addr .mdc(mdc), // from top .mbus_in(mbus_in), // from ctrl_data .serial_mode(serial_mode), // new: .mdio_dis (mdio_dis), // from top .pma_cram_test (pma_cram_test), // new: .ser_shift_load(dprioload), // from top .si(si_ch3), // new .csr_chnl_in(csr_chnl_in_ch3), // new .csr_chnl_in_reserved(csr_chnl_in_reserved_ch3), .dprio_chnl_id(dprio_chnl_id3), // new - not in centrl .dp_chnl_out(dp_chnl_out_ch3), // to top .dp_chnl_out_reserved(dp_chnl_out_reserved_ch3), .so(so_ch3), // to ctrl_data .mbus_out(mbus_out_ch3) // to status_reg ); // -------------------------------------------------------------------- // DPRIO SW <--> ICD ------------------------------------------------- // -------------------------------------------------------------------- stratixiv_hssi_cmu_dprio_map m_map( .cmudividerdprioin (cmudividerdprioin), .cmuplldprioin (cmuplldprioin), .refclkdividerdprioin (refclkdividerdprioin), .rxpcsdprioin (rxpcsdprioin), .rxpmadprioin (rxpmadprioin), .txpcsdprioin (txpcsdprioin), .txpmadprioin (txpmadprioin), .ch0_dp_chnl_out (dp_chnl_out_ch0), .ch1_dp_chnl_out (dp_chnl_out_ch1), .ch2_dp_chnl_out (dp_chnl_out_ch2), .ch3_dp_chnl_out (dp_chnl_out_ch3), .ch0_dp_chnl_out_reserved (dp_chnl_out_reserved_ch0), .ch1_dp_chnl_out_reserved (dp_chnl_out_reserved_ch1), .ch2_dp_chnl_out_reserved (dp_chnl_out_reserved_ch2), .ch3_dp_chnl_out_reserved (dp_chnl_out_reserved_ch3), .dp_centrl_out (dp_centrl_out), .dp_centrl_out_reserved (dp_centrl_out_reserved), .ch0_csr_chnl_in (csr_chnl_in_ch0), .ch1_csr_chnl_in (csr_chnl_in_ch1), .ch2_csr_chnl_in (csr_chnl_in_ch2), .ch3_csr_chnl_in (csr_chnl_in_ch3), .ch0_csr_chnl_in_reserved(csr_chnl_in_reserved_ch0), .ch1_csr_chnl_in_reserved(csr_chnl_in_reserved_ch1), .ch2_csr_chnl_in_reserved(csr_chnl_in_reserved_ch2), .ch3_csr_chnl_in_reserved(csr_chnl_in_reserved_ch3), .csr_centrl_in (csr_centrl_in), .csr_centrl_in_reserved (csr_centrl_in_reserved), .cmudividerdprioout (cmudividerdprioout), .cmuplldprioout (cmuplldprioout), .refclkdividerdprioout (refclkdividerdprioout), .rxpcsdprioout (rxpcsdprioout), .rxpmadprioout (rxpmadprioout), .txpcsdprioout (txpcsdprioout), .txpmadprioout (txpmadprioout) ); defparam m_map.clkdiv0_inclk0_logical_to_physical_mapping = clkdiv0_inclk0_logical_to_physical_mapping; defparam m_map.clkdiv0_inclk1_logical_to_physical_mapping = clkdiv0_inclk1_logical_to_physical_mapping; defparam m_map.clkdiv1_inclk0_logical_to_physical_mapping = clkdiv1_inclk0_logical_to_physical_mapping; defparam m_map.clkdiv1_inclk1_logical_to_physical_mapping = clkdiv1_inclk1_logical_to_physical_mapping; defparam m_map.clkdiv2_inclk0_logical_to_physical_mapping = clkdiv2_inclk0_logical_to_physical_mapping; defparam m_map.clkdiv2_inclk1_logical_to_physical_mapping = clkdiv2_inclk1_logical_to_physical_mapping; defparam m_map.clkdiv3_inclk0_logical_to_physical_mapping = clkdiv3_inclk0_logical_to_physical_mapping; defparam m_map.clkdiv3_inclk1_logical_to_physical_mapping = clkdiv3_inclk1_logical_to_physical_mapping; defparam m_map.clkdiv4_inclk0_logical_to_physical_mapping = clkdiv4_inclk0_logical_to_physical_mapping; defparam m_map.clkdiv4_inclk1_logical_to_physical_mapping = clkdiv4_inclk1_logical_to_physical_mapping; defparam m_map.clkdiv5_inclk0_logical_to_physical_mapping = clkdiv5_inclk0_logical_to_physical_mapping; defparam m_map.clkdiv5_inclk1_logical_to_physical_mapping = clkdiv5_inclk1_logical_to_physical_mapping; defparam m_map.pll0_inclk0_logical_to_physical_mapping = pll0_inclk0_logical_to_physical_mapping; defparam m_map.pll0_inclk1_logical_to_physical_mapping = pll0_inclk1_logical_to_physical_mapping; defparam m_map.pll0_inclk2_logical_to_physical_mapping = pll0_inclk2_logical_to_physical_mapping; defparam m_map.pll0_inclk3_logical_to_physical_mapping = pll0_inclk3_logical_to_physical_mapping; defparam m_map.pll0_inclk4_logical_to_physical_mapping = pll0_inclk4_logical_to_physical_mapping; defparam m_map.pll0_inclk5_logical_to_physical_mapping = pll0_inclk5_logical_to_physical_mapping; defparam m_map.pll0_inclk6_logical_to_physical_mapping = pll0_inclk6_logical_to_physical_mapping; defparam m_map.pll0_inclk7_logical_to_physical_mapping = pll0_inclk7_logical_to_physical_mapping; defparam m_map.pll0_inclk8_logical_to_physical_mapping = pll0_inclk8_logical_to_physical_mapping; defparam m_map.pll0_inclk9_logical_to_physical_mapping = pll0_inclk9_logical_to_physical_mapping; defparam m_map.pll1_inclk0_logical_to_physical_mapping = pll1_inclk0_logical_to_physical_mapping; defparam m_map.pll1_inclk1_logical_to_physical_mapping = pll1_inclk1_logical_to_physical_mapping; defparam m_map.pll1_inclk2_logical_to_physical_mapping = pll1_inclk2_logical_to_physical_mapping; defparam m_map.pll1_inclk3_logical_to_physical_mapping = pll1_inclk3_logical_to_physical_mapping; defparam m_map.pll1_inclk4_logical_to_physical_mapping = pll1_inclk4_logical_to_physical_mapping; defparam m_map.pll1_inclk5_logical_to_physical_mapping = pll1_inclk5_logical_to_physical_mapping; defparam m_map.pll1_inclk6_logical_to_physical_mapping = pll1_inclk6_logical_to_physical_mapping; defparam m_map.pll1_inclk7_logical_to_physical_mapping = pll1_inclk7_logical_to_physical_mapping; defparam m_map.pll1_inclk8_logical_to_physical_mapping = pll1_inclk8_logical_to_physical_mapping; defparam m_map.pll1_inclk9_logical_to_physical_mapping = pll1_inclk9_logical_to_physical_mapping; defparam m_map.pll2_inclk0_logical_to_physical_mapping = pll2_inclk0_logical_to_physical_mapping; defparam m_map.pll2_inclk1_logical_to_physical_mapping = pll2_inclk1_logical_to_physical_mapping; defparam m_map.pll2_inclk2_logical_to_physical_mapping = pll2_inclk2_logical_to_physical_mapping; defparam m_map.pll2_inclk3_logical_to_physical_mapping = pll2_inclk3_logical_to_physical_mapping; defparam m_map.pll2_inclk4_logical_to_physical_mapping = pll2_inclk4_logical_to_physical_mapping; defparam m_map.pll2_inclk5_logical_to_physical_mapping = pll2_inclk5_logical_to_physical_mapping; defparam m_map.pll2_inclk6_logical_to_physical_mapping = pll2_inclk6_logical_to_physical_mapping; defparam m_map.pll2_inclk7_logical_to_physical_mapping = pll2_inclk7_logical_to_physical_mapping; defparam m_map.pll2_inclk8_logical_to_physical_mapping = pll2_inclk8_logical_to_physical_mapping; defparam m_map.pll2_inclk9_logical_to_physical_mapping = pll2_inclk9_logical_to_physical_mapping; defparam m_map.pll3_inclk0_logical_to_physical_mapping = pll3_inclk0_logical_to_physical_mapping; defparam m_map.pll3_inclk1_logical_to_physical_mapping = pll3_inclk1_logical_to_physical_mapping; defparam m_map.pll3_inclk2_logical_to_physical_mapping = pll3_inclk2_logical_to_physical_mapping; defparam m_map.pll3_inclk3_logical_to_physical_mapping = pll3_inclk3_logical_to_physical_mapping; defparam m_map.pll3_inclk4_logical_to_physical_mapping = pll3_inclk4_logical_to_physical_mapping; defparam m_map.pll3_inclk5_logical_to_physical_mapping = pll3_inclk5_logical_to_physical_mapping; defparam m_map.pll3_inclk6_logical_to_physical_mapping = pll3_inclk6_logical_to_physical_mapping; defparam m_map.pll3_inclk7_logical_to_physical_mapping = pll3_inclk7_logical_to_physical_mapping; defparam m_map.pll3_inclk8_logical_to_physical_mapping = pll3_inclk8_logical_to_physical_mapping; defparam m_map.pll3_inclk9_logical_to_physical_mapping = pll3_inclk9_logical_to_physical_mapping; defparam m_map.pll4_inclk0_logical_to_physical_mapping = pll4_inclk0_logical_to_physical_mapping; defparam m_map.pll4_inclk1_logical_to_physical_mapping = pll4_inclk1_logical_to_physical_mapping; defparam m_map.pll4_inclk2_logical_to_physical_mapping = pll4_inclk2_logical_to_physical_mapping; defparam m_map.pll4_inclk3_logical_to_physical_mapping = pll4_inclk3_logical_to_physical_mapping; defparam m_map.pll4_inclk4_logical_to_physical_mapping = pll4_inclk4_logical_to_physical_mapping; defparam m_map.pll4_inclk5_logical_to_physical_mapping = pll4_inclk5_logical_to_physical_mapping; defparam m_map.pll4_inclk6_logical_to_physical_mapping = pll4_inclk6_logical_to_physical_mapping; defparam m_map.pll4_inclk7_logical_to_physical_mapping = pll4_inclk7_logical_to_physical_mapping; defparam m_map.pll4_inclk8_logical_to_physical_mapping = pll4_inclk8_logical_to_physical_mapping; defparam m_map.pll4_inclk9_logical_to_physical_mapping = pll4_inclk9_logical_to_physical_mapping; defparam m_map.pll5_inclk0_logical_to_physical_mapping = pll5_inclk0_logical_to_physical_mapping; defparam m_map.pll5_inclk1_logical_to_physical_mapping = pll5_inclk1_logical_to_physical_mapping; defparam m_map.pll5_inclk2_logical_to_physical_mapping = pll5_inclk2_logical_to_physical_mapping; defparam m_map.pll5_inclk3_logical_to_physical_mapping = pll5_inclk3_logical_to_physical_mapping; defparam m_map.pll5_inclk4_logical_to_physical_mapping = pll5_inclk4_logical_to_physical_mapping; defparam m_map.pll5_inclk5_logical_to_physical_mapping = pll5_inclk5_logical_to_physical_mapping; defparam m_map.pll5_inclk6_logical_to_physical_mapping = pll5_inclk6_logical_to_physical_mapping; defparam m_map.pll5_inclk7_logical_to_physical_mapping = pll5_inclk7_logical_to_physical_mapping; defparam m_map.pll5_inclk8_logical_to_physical_mapping = pll5_inclk8_logical_to_physical_mapping; defparam m_map.pll5_inclk9_logical_to_physical_mapping = pll5_inclk9_logical_to_physical_mapping; defparam m_map.pll0_logical_to_physical_mapping = pll0_logical_to_physical_mapping; defparam m_map.pll1_logical_to_physical_mapping = pll1_logical_to_physical_mapping; defparam m_map.pll2_logical_to_physical_mapping = pll2_logical_to_physical_mapping; defparam m_map.pll3_logical_to_physical_mapping = pll3_logical_to_physical_mapping; defparam m_map.pll4_logical_to_physical_mapping = pll4_logical_to_physical_mapping; defparam m_map.pll5_logical_to_physical_mapping = pll5_logical_to_physical_mapping; defparam m_map.refclk_divider0_logical_to_physical_mapping = refclk_divider0_logical_to_physical_mapping; defparam m_map.refclk_divider1_logical_to_physical_mapping = refclk_divider1_logical_to_physical_mapping; defparam m_map.rx0_logical_to_physical_mapping = rx0_logical_to_physical_mapping; defparam m_map.rx1_logical_to_physical_mapping = rx1_logical_to_physical_mapping; defparam m_map.rx2_logical_to_physical_mapping = rx2_logical_to_physical_mapping; defparam m_map.rx3_logical_to_physical_mapping = rx3_logical_to_physical_mapping; defparam m_map.rx4_logical_to_physical_mapping = rx4_logical_to_physical_mapping; defparam m_map.rx5_logical_to_physical_mapping = rx5_logical_to_physical_mapping; defparam m_map.tx0_logical_to_physical_mapping = tx0_logical_to_physical_mapping; defparam m_map.tx1_logical_to_physical_mapping = tx1_logical_to_physical_mapping; defparam m_map.tx2_logical_to_physical_mapping = tx2_logical_to_physical_mapping; defparam m_map.tx3_logical_to_physical_mapping = tx3_logical_to_physical_mapping; defparam m_map.tx4_logical_to_physical_mapping = tx4_logical_to_physical_mapping; defparam m_map.tx5_logical_to_physical_mapping = tx5_logical_to_physical_mapping; defparam m_map.tx0_pma_inclk0_logical_to_physical_mapping = tx0_pma_inclk0_logical_to_physical_mapping; defparam m_map.tx0_pma_inclk1_logical_to_physical_mapping = tx0_pma_inclk1_logical_to_physical_mapping; defparam m_map.tx0_pma_inclk2_logical_to_physical_mapping = tx0_pma_inclk2_logical_to_physical_mapping; defparam m_map.tx0_pma_inclk3_logical_to_physical_mapping = tx0_pma_inclk3_logical_to_physical_mapping; defparam m_map.tx0_pma_inclk4_logical_to_physical_mapping = tx0_pma_inclk4_logical_to_physical_mapping; defparam m_map.tx1_pma_inclk0_logical_to_physical_mapping = tx1_pma_inclk0_logical_to_physical_mapping; defparam m_map.tx1_pma_inclk1_logical_to_physical_mapping = tx1_pma_inclk1_logical_to_physical_mapping; defparam m_map.tx1_pma_inclk2_logical_to_physical_mapping = tx1_pma_inclk2_logical_to_physical_mapping; defparam m_map.tx1_pma_inclk3_logical_to_physical_mapping = tx1_pma_inclk3_logical_to_physical_mapping; defparam m_map.tx1_pma_inclk4_logical_to_physical_mapping = tx1_pma_inclk4_logical_to_physical_mapping; defparam m_map.tx2_pma_inclk0_logical_to_physical_mapping = tx2_pma_inclk0_logical_to_physical_mapping; defparam m_map.tx2_pma_inclk1_logical_to_physical_mapping = tx2_pma_inclk1_logical_to_physical_mapping; defparam m_map.tx2_pma_inclk2_logical_to_physical_mapping = tx2_pma_inclk2_logical_to_physical_mapping; defparam m_map.tx2_pma_inclk3_logical_to_physical_mapping = tx2_pma_inclk3_logical_to_physical_mapping; defparam m_map.tx2_pma_inclk4_logical_to_physical_mapping = tx2_pma_inclk4_logical_to_physical_mapping; defparam m_map.tx3_pma_inclk0_logical_to_physical_mapping = tx3_pma_inclk0_logical_to_physical_mapping; defparam m_map.tx3_pma_inclk1_logical_to_physical_mapping = tx3_pma_inclk1_logical_to_physical_mapping; defparam m_map.tx3_pma_inclk2_logical_to_physical_mapping = tx3_pma_inclk2_logical_to_physical_mapping; defparam m_map.tx3_pma_inclk3_logical_to_physical_mapping = tx3_pma_inclk3_logical_to_physical_mapping; defparam m_map.tx3_pma_inclk4_logical_to_physical_mapping = tx3_pma_inclk4_logical_to_physical_mapping; defparam m_map.tx4_pma_inclk0_logical_to_physical_mapping = tx4_pma_inclk0_logical_to_physical_mapping; defparam m_map.tx4_pma_inclk1_logical_to_physical_mapping = tx4_pma_inclk1_logical_to_physical_mapping; defparam m_map.tx4_pma_inclk2_logical_to_physical_mapping = tx4_pma_inclk2_logical_to_physical_mapping; defparam m_map.tx4_pma_inclk3_logical_to_physical_mapping = tx4_pma_inclk3_logical_to_physical_mapping; defparam m_map.tx4_pma_inclk4_logical_to_physical_mapping = tx4_pma_inclk4_logical_to_physical_mapping; defparam m_map.tx5_pma_inclk0_logical_to_physical_mapping = tx5_pma_inclk0_logical_to_physical_mapping; defparam m_map.tx5_pma_inclk1_logical_to_physical_mapping = tx5_pma_inclk1_logical_to_physical_mapping; defparam m_map.tx5_pma_inclk2_logical_to_physical_mapping = tx5_pma_inclk2_logical_to_physical_mapping; defparam m_map.tx5_pma_inclk3_logical_to_physical_mapping = tx5_pma_inclk3_logical_to_physical_mapping; defparam m_map.tx5_pma_inclk4_logical_to_physical_mapping = tx5_pma_inclk4_logical_to_physical_mapping; defparam m_map.sim_dump_dprio_internal_reg_at_time = sim_dump_dprio_internal_reg_at_time; defparam m_map.sim_dump_filename = sim_dump_filename; endmodule `timescale 1 ps / 1 ps module stratixiv_hssi_cmu ( adet, cmudividerdprioin, cmuplldprioin, dpclk, dpriodisable, dprioin, dprioload, extra10gin, fixedclk, lccmurtestbussel, pmacramtest, nonuserfromcal, quadreset, rateswitch, rateswitchdonein, rdalign, rdenablesync, recovclk, refclkdividerdprioin, rxanalogreset, rxclk, rxcoreclk, rxctrl, rxdatain, rxdatavalid, rxdigitalreset, rxpcsdprioin, rxphfifordenable, rxphfiforeset, rxphfifowrdisable, rxpmadprioin, rxpowerdown, rxrunningdisp, scanclk, scanin, scanmode, scanshift, syncstatus, testin, txclk, txcoreclk, txctrl, txdatain, txdigitalreset, txpcsdprioin, txphfiforddisable, txphfiforeset, txphfifowrenable, txpllreset, txpmadprioin, alignstatus, autospdx4configsel, autospdx4rateswitchout, autospdx4spdchg, clkdivpowerdn, cmudividerdprioout, cmuplldprioout, digitaltestout, dpriodisableout, dpriooe, dprioout, enabledeskew, extra10gout, fiforesetrd, lccmutestbus, phfifiox4ptrsreset, pllpowerdn, pllresetout, quadresetout, refclkdividerdprioout, rxadcepowerdown, rxadceresetout, rxanalogresetout, rxcrupowerdown, rxcruresetout, rxctrlout, rxdataout, rxdigitalresetout, rxibpowerdown, rxpcsdprioout, rxphfifox4byteselout, rxphfifox4wrclkout, rxphfifox4rdenableout, rxphfifox4wrenableout, rxpmadprioout, scanout, testout, txanalogresetout, txctrlout, txdataout, txdetectrxpowerdown, txdigitalresetout, txdividerpowerdown, txobpowerdown, txpcsdprioout, txphfifox4byteselout, txphfifox4rdclkout, txphfifox4rdenableout, txphfifox4wrenableout, txpmadprioout ); `define STRATIXIV_HSSI_CMU_ALPHA_TOLOWER_WORD_LENGTH 25 parameter lpm_type = "stratixiv_hssi_cmu"; parameter analog_test_bus_enable = "false"; parameter auto_spd_deassert_ph_fifo_rst_count = 0 ; parameter auto_spd_phystatus_notify_count = 0 ; parameter bonded_quad_mode = "none"; parameter bypass_bandgap = "false"; parameter central_test_bus_select = 0 ; parameter cmu_type = "regular"; parameter devaddr = 1 ; parameter dprio_config_mode = 6'h00; parameter in_xaui_mode = "false"; parameter num_con_align_chars_for_align = 4 ; parameter num_con_errors_for_align_loss = 2 ; parameter num_con_good_data_for_align_approach = 3 ; parameter offset_all_errors_align = "false"; parameter pipe_auto_speed_nego_enable = "false"; parameter pipe_freq_scale_mode = "data width"; parameter pma_done_count = 0 ; parameter portaddr = 1 ; parameter rx0_auto_spd_self_switch_enable = "false"; parameter rx0_channel_bonding = "none"; parameter rx0_clk1_mux_select = "recovered clock"; parameter rx0_clk2_mux_select = "recovered clock"; parameter rx0_clk_pd_enable = "false"; parameter rx0_ph_fifo_reg_mode = "false"; parameter rx0_ph_fifo_reset_enable = "false"; parameter rx0_ph_fifo_user_ctrl_enable = "false"; parameter rx0_phfifo_wait_cnt = 0 ; parameter rx0_rd_clk_mux_select = "int clock"; parameter rx0_recovered_clk_mux_select = "recovered clock"; parameter rx0_reset_clock_output_during_digital_reset = "false"; parameter rx0_use_double_data_mode = "false"; parameter rx_master_direction = "none"; parameter rx_xaui_sm_backward_compatible_enable = "false"; parameter test_mode = "false"; parameter tx0_auto_spd_self_switch_enable = "false"; parameter tx0_channel_bonding = "none"; parameter tx0_clk_pd_enable = "false"; parameter tx0_ph_fifo_reg_mode = "false"; parameter tx0_ph_fifo_reset_enable = "false"; parameter tx0_ph_fifo_user_ctrl_enable = "false"; parameter tx0_rd_clk_mux_select = "int clock"; parameter tx0_reset_clock_output_during_digital_reset = "false"; parameter tx0_use_double_data_mode = "false"; parameter tx0_wr_clk_mux_select = "int_clk"; parameter tx_master_direction = "none"; parameter tx_pll0_used_as_rx_cdr = "false"; parameter tx_pll1_used_as_rx_cdr = "false"; parameter tx_xaui_sm_backward_compatible_enable = "false"; parameter use_deskew_fifo = "false"; parameter vcceh_voltage = "3.0V"; // SIMULATION_ONLY_PARAMETERS_BEGIN parameter migrated_from_prev_family = "false"; parameter protocol_hint = "basic"; parameter vcceh_voltage_user_specified_auto = "true"; // -------------------- Simulation only parameters ---------------------------- parameter clkdiv0_inclk0_logical_to_physical_mapping = "pll0"; parameter clkdiv0_inclk1_logical_to_physical_mapping = "pll1"; parameter clkdiv1_inclk0_logical_to_physical_mapping = "pll0"; parameter clkdiv1_inclk1_logical_to_physical_mapping = "pll1"; parameter clkdiv2_inclk0_logical_to_physical_mapping = "pll0"; parameter clkdiv2_inclk1_logical_to_physical_mapping = "pll1"; parameter clkdiv3_inclk0_logical_to_physical_mapping = "pll0"; parameter clkdiv3_inclk1_logical_to_physical_mapping = "pll1"; parameter clkdiv4_inclk0_logical_to_physical_mapping = "pll0"; parameter clkdiv4_inclk1_logical_to_physical_mapping = "pll1"; parameter clkdiv5_inclk0_logical_to_physical_mapping = "pll0"; parameter clkdiv5_inclk1_logical_to_physical_mapping = "pll1"; // to remove - covered by clkdiv[4-5]_inclk and tx_pma[4-5]_inclk[0-4] parameter cmu_divider0_inclk0_physical_mapping = "pll0"; parameter cmu_divider0_inclk1_physical_mapping = "pll1"; parameter cmu_divider0_inclk2_physical_mapping = "x4"; parameter cmu_divider0_inclk3_physical_mapping = "xn_t"; parameter cmu_divider0_inclk4_physical_mapping = "xn_b"; parameter cmu_divider1_inclk0_physical_mapping = "pll0"; parameter cmu_divider1_inclk1_physical_mapping = "pll1"; parameter cmu_divider1_inclk2_physical_mapping = "x4"; parameter cmu_divider1_inclk3_physical_mapping = "xn_t"; parameter cmu_divider1_inclk4_physical_mapping = "xn_b"; parameter cmu_divider2_inclk0_physical_mapping = "pll0"; parameter cmu_divider2_inclk1_physical_mapping = "pll1"; parameter cmu_divider2_inclk2_physical_mapping = "x4"; parameter cmu_divider2_inclk3_physical_mapping = "xn_t"; parameter cmu_divider2_inclk4_physical_mapping = "xn_b"; parameter cmu_divider3_inclk0_physical_mapping = "pll0"; parameter cmu_divider3_inclk1_physical_mapping = "pll1"; parameter cmu_divider3_inclk2_physical_mapping = "x4"; parameter cmu_divider3_inclk3_physical_mapping = "xn_t"; parameter cmu_divider3_inclk4_physical_mapping = "xn_b"; parameter cmu_divider4_inclk0_physical_mapping = "pll0"; parameter cmu_divider4_inclk1_physical_mapping = "pll1"; parameter cmu_divider4_inclk2_physical_mapping = "x4"; parameter cmu_divider4_inclk3_physical_mapping = "xn_t"; parameter cmu_divider4_inclk4_physical_mapping = "xn_b"; parameter cmu_divider5_inclk0_physical_mapping = "pll0"; parameter cmu_divider5_inclk1_physical_mapping = "pll1"; parameter cmu_divider5_inclk2_physical_mapping = "x4"; parameter cmu_divider5_inclk3_physical_mapping = "xn_t"; parameter cmu_divider5_inclk4_physical_mapping = "xn_b"; parameter pll0_inclk0_logical_to_physical_mapping = "clkrefclk0"; parameter pll0_inclk1_logical_to_physical_mapping = "clkrefclk1"; parameter pll0_inclk2_logical_to_physical_mapping = "iq2"; parameter pll0_inclk3_logical_to_physical_mapping = "iq3"; parameter pll0_inclk4_logical_to_physical_mapping = "iq4"; parameter pll0_inclk5_logical_to_physical_mapping = "iq5"; parameter pll0_inclk6_logical_to_physical_mapping = "iq6"; parameter pll0_inclk7_logical_to_physical_mapping = "iq7"; parameter pll0_inclk8_logical_to_physical_mapping = "pld_clk"; parameter pll0_inclk9_logical_to_physical_mapping = "gpll_clk"; parameter pll1_inclk0_logical_to_physical_mapping = "clkrefclk0"; parameter pll1_inclk1_logical_to_physical_mapping = "clkrefclk1"; parameter pll1_inclk2_logical_to_physical_mapping = "iq2"; parameter pll1_inclk3_logical_to_physical_mapping = "iq3"; parameter pll1_inclk4_logical_to_physical_mapping = "iq4"; parameter pll1_inclk5_logical_to_physical_mapping = "iq5"; parameter pll1_inclk6_logical_to_physical_mapping = "iq6"; parameter pll1_inclk7_logical_to_physical_mapping = "iq7"; parameter pll1_inclk8_logical_to_physical_mapping = "pld_clk"; parameter pll1_inclk9_logical_to_physical_mapping = "gpll_clk"; parameter pll2_inclk0_logical_to_physical_mapping = "clkrefclk0"; parameter pll2_inclk1_logical_to_physical_mapping = "clkrefclk1"; parameter pll2_inclk2_logical_to_physical_mapping = "iq2"; parameter pll2_inclk3_logical_to_physical_mapping = "iq3"; parameter pll2_inclk4_logical_to_physical_mapping = "iq4"; parameter pll2_inclk5_logical_to_physical_mapping = "iq5"; parameter pll2_inclk6_logical_to_physical_mapping = "iq6"; parameter pll2_inclk7_logical_to_physical_mapping = "iq7"; parameter pll2_inclk8_logical_to_physical_mapping = "pld_clk"; parameter pll2_inclk9_logical_to_physical_mapping = "gpll_clk"; parameter pll3_inclk0_logical_to_physical_mapping = "clkrefclk0"; parameter pll3_inclk1_logical_to_physical_mapping = "clkrefclk1"; parameter pll3_inclk2_logical_to_physical_mapping = "iq2"; parameter pll3_inclk3_logical_to_physical_mapping = "iq3"; parameter pll3_inclk4_logical_to_physical_mapping = "iq4"; parameter pll3_inclk5_logical_to_physical_mapping = "iq5"; parameter pll3_inclk6_logical_to_physical_mapping = "iq6"; parameter pll3_inclk7_logical_to_physical_mapping = "iq7"; parameter pll3_inclk8_logical_to_physical_mapping = "pld_clk"; parameter pll3_inclk9_logical_to_physical_mapping = "gpll_clk"; parameter pll4_inclk0_logical_to_physical_mapping = "clkrefclk0"; parameter pll4_inclk1_logical_to_physical_mapping = "clkrefclk1"; parameter pll4_inclk2_logical_to_physical_mapping = "iq2"; parameter pll4_inclk3_logical_to_physical_mapping = "iq3"; parameter pll4_inclk4_logical_to_physical_mapping = "iq4"; parameter pll4_inclk5_logical_to_physical_mapping = "iq5"; parameter pll4_inclk6_logical_to_physical_mapping = "iq6"; parameter pll4_inclk7_logical_to_physical_mapping = "iq7"; parameter pll4_inclk8_logical_to_physical_mapping = "pld_clk"; parameter pll4_inclk9_logical_to_physical_mapping = "gpll_clk"; parameter pll5_inclk0_logical_to_physical_mapping = "clkrefclk0"; parameter pll5_inclk1_logical_to_physical_mapping = "clkrefclk1"; parameter pll5_inclk2_logical_to_physical_mapping = "iq2"; parameter pll5_inclk3_logical_to_physical_mapping = "iq3"; parameter pll5_inclk4_logical_to_physical_mapping = "iq4"; parameter pll5_inclk5_logical_to_physical_mapping = "iq5"; parameter pll5_inclk6_logical_to_physical_mapping = "iq6"; parameter pll5_inclk7_logical_to_physical_mapping = "iq7"; parameter pll5_inclk8_logical_to_physical_mapping = "pld_clk"; parameter pll5_inclk9_logical_to_physical_mapping = "gpll_clk"; parameter pll0_logical_to_physical_mapping = 0 ; parameter pll1_logical_to_physical_mapping = 1 ; parameter pll2_logical_to_physical_mapping = 2 ; parameter pll3_logical_to_physical_mapping = 3 ; parameter pll4_logical_to_physical_mapping = 4 ; parameter pll5_logical_to_physical_mapping = 5 ; parameter refclk_divider0_logical_to_physical_mapping = 0 ; parameter refclk_divider1_logical_to_physical_mapping = 1 ; parameter rx0_logical_to_physical_mapping = 0 ; parameter rx1_logical_to_physical_mapping = 1 ; parameter rx2_logical_to_physical_mapping = 2 ; parameter rx3_logical_to_physical_mapping = 3 ; parameter rx4_logical_to_physical_mapping = 4 ; parameter rx5_logical_to_physical_mapping = 5 ; parameter tx0_logical_to_physical_mapping = 0 ; parameter tx1_logical_to_physical_mapping = 1 ; parameter tx2_logical_to_physical_mapping = 2 ; parameter tx3_logical_to_physical_mapping = 3 ; parameter tx4_logical_to_physical_mapping = 4 ; parameter tx5_logical_to_physical_mapping = 5 ; parameter tx0_pma_inclk0_logical_to_physical_mapping = "x1"; parameter tx0_pma_inclk1_logical_to_physical_mapping = "x4"; parameter tx0_pma_inclk2_logical_to_physical_mapping = "xn_top"; parameter tx0_pma_inclk3_logical_to_physical_mapping = "xn_bottom"; parameter tx0_pma_inclk4_logical_to_physical_mapping = "hypertransport"; parameter tx1_pma_inclk0_logical_to_physical_mapping = "x1"; parameter tx1_pma_inclk1_logical_to_physical_mapping = "x4"; parameter tx1_pma_inclk2_logical_to_physical_mapping = "xn_top"; parameter tx1_pma_inclk3_logical_to_physical_mapping = "xn_bottom"; parameter tx1_pma_inclk4_logical_to_physical_mapping = "hypertransport"; parameter tx2_pma_inclk0_logical_to_physical_mapping = "x1"; parameter tx2_pma_inclk1_logical_to_physical_mapping = "x4"; parameter tx2_pma_inclk2_logical_to_physical_mapping = "xn_top"; parameter tx2_pma_inclk3_logical_to_physical_mapping = "xn_bottom"; parameter tx2_pma_inclk4_logical_to_physical_mapping = "hypertransport"; parameter tx3_pma_inclk0_logical_to_physical_mapping = "x1"; parameter tx3_pma_inclk1_logical_to_physical_mapping = "x4"; parameter tx3_pma_inclk2_logical_to_physical_mapping = "xn_top"; parameter tx3_pma_inclk3_logical_to_physical_mapping = "xn_bottom"; parameter tx3_pma_inclk4_logical_to_physical_mapping = "hypertransport"; parameter tx4_pma_inclk0_logical_to_physical_mapping = "x1"; parameter tx4_pma_inclk1_logical_to_physical_mapping = "x4"; parameter tx4_pma_inclk2_logical_to_physical_mapping = "xn_top"; parameter tx4_pma_inclk3_logical_to_physical_mapping = "xn_bottom"; parameter tx4_pma_inclk4_logical_to_physical_mapping = "hypertransport"; parameter tx5_pma_inclk0_logical_to_physical_mapping = "x1"; parameter tx5_pma_inclk1_logical_to_physical_mapping = "x4"; parameter tx5_pma_inclk2_logical_to_physical_mapping = "xn_top"; parameter tx5_pma_inclk3_logical_to_physical_mapping = "xn_bottom"; parameter tx5_pma_inclk4_logical_to_physical_mapping = "hypertransport"; // DEBUG dump parameter sim_dump_dprio_internal_reg_at_time = 0; // in ps parameter sim_dump_filename = "sim_dprio_dump.txt"; // over-write when multiple CMUs // SIMULATION_ONLY_PARAMETERS_END input [3:0] adet; input dpclk; input dpriodisable; input dprioin; input dprioload; input [6:0] extra10gin; input [5:0] fixedclk; input [2:0] lccmurtestbussel; input nonuserfromcal; input pmacramtest; input quadreset; input rateswitch; input rateswitchdonein; input [3:0] rdalign; input rdenablesync; input recovclk; input [5:0] rxanalogreset; input rxclk; input rxcoreclk; input [3:0] rxctrl; input [31:0] rxdatain; input [3:0] rxdatavalid; input [3:0] rxdigitalreset; input rxphfifordenable; input rxphfiforeset; input rxphfifowrdisable; input [5:0] rxpowerdown; input [3:0] rxrunningdisp; input scanclk; input [22:0] scanin; input scanmode; input scanshift; input [3:0] syncstatus; input [9999:0] testin; input txclk; input txcoreclk; input [3:0] txctrl; input [31:0] txdatain; input [3:0] txdigitalreset; input txphfiforddisable; input txphfiforeset; input txphfifowrenable; input [1:0] txpllreset; output alignstatus; output autospdx4configsel; output autospdx4rateswitchout; output autospdx4spdchg; output [1:0] clkdivpowerdn; output dpriodisableout; output dpriooe; output dprioout; output enabledeskew; output extra10gout; output [9:0] digitaltestout; output fiforesetrd; output [7:0] lccmutestbus; output phfifiox4ptrsreset; output [1:0] pllpowerdn; output [1:0] pllresetout; output quadresetout; output [3:0] rxadcepowerdown; output [3:0] rxadceresetout; output [5:0] rxanalogresetout; output [5:0] rxcrupowerdown; output [5:0] rxcruresetout; output [3:0] rxctrlout; output [31:0] rxdataout; output [3:0] rxdigitalresetout; output [5:0] rxibpowerdown; output rxphfifox4byteselout; output rxphfifox4wrclkout; output rxphfifox4rdenableout; output rxphfifox4wrenableout; output [22:0] scanout; output [6999:0] testout; output [5:0] txanalogresetout; output [3:0] txctrlout; output [31:0] txdataout; output [5:0] txdetectrxpowerdown; output [3:0] txdigitalresetout; output [5:0] txdividerpowerdown; output [5:0] txobpowerdown; output txphfifox4byteselout; output txphfifox4rdclkout; output txphfifox4rdenableout; output txphfifox4wrenableout; //dprio ports - all in one input [599 : 0] cmudividerdprioin; input [1799 : 0] cmuplldprioin; input [1 : 0] refclkdividerdprioin; input [1599 : 0] rxpcsdprioin; input [1799 : 0] rxpmadprioin; input [599 : 0] txpcsdprioin; input [1799 : 0] txpmadprioin; output [599 : 0] cmudividerdprioout; output [1799 : 0] cmuplldprioout; output [1 : 0] refclkdividerdprioout; output [1599 : 0] rxpcsdprioout; output [1799 : 0] rxpmadprioout; output [599 : 0] txpcsdprioout; output [1799 : 0] txpmadprioout; wire dpriodisableout; /////////////////////////////////////////////////////////////////////////// // const wire ---------------------------------------------------------- // /////////////////////////////////////////////////////////////////////////// wire vcc_wire; wire gnd_wire; wire dummy_wire; /////////////////////////////////////////////////////////////////////////// // optimization -------------------------------------------------------- // /////////////////////////////////////////////////////////////////////////// reg init_in_xaui_mode; /////////////////////////////////////////////////////////////////////////// // ww47 new CRAMs ------------------------------------------------------ // /////////////////////////////////////////////////////////////////////////// reg [3:0] init_rauto_deassert_pc_rst_cnt; reg [4:0] init_rauto_pc_en_cnt; reg init_rauto_speed_ena; reg [1:0] init_rclk_1_sel; reg [1:0] init_rclk_2_sel; reg init_rdwidth_rx; reg init_rdwidth_tx; reg init_rfreerun_rx; reg init_rfreerun_tx; reg init_rfreq_sel; reg init_rindv_rx; reg init_rindv_tx; reg init_rmaster_rx; reg init_rmaster_tx; reg init_rmaster_up_rx; reg init_rmaster_up_tx; reg init_rphfifo_regmode_rx; reg [17:0] init_rpma_done_count; reg [1:0] init_rrcvd_clk_sel; reg init_rrx_rd_clk_sel; reg init_rrxfifo_urst_en; reg init_rrxpcsclkpwdn; reg init_rrxphfifopldctl_en; reg init_rself_sw_en_rx; reg init_rself_sw_en_tx; reg init_rtxpcsclkpwdn; reg init_rtxphfifopldctl_en; reg init_rtxrdclksel; reg init_rtxwrclksel; reg init_scan_mode; // cram used in centrl_clk_ctl but not in WYS reg init_rfreerun_centrl; reg init_rcentrl_clk_sel; reg init_rrefclk_out_div2; reg init_rtxfifo_urst_en; // used in txctrl wire [3:0] cram_rauto_deassert_pc_rst_cnt; wire [4:0] cram_rauto_pc_en_cnt; wire cram_rauto_speed_ena; wire [1:0] cram_rclk_1_sel; wire [1:0] cram_rclk_2_sel; wire cram_rdwidth_rx; wire cram_rdwidth_tx; wire cram_rfreerun_rx; wire cram_rfreerun_tx; wire cram_rfreq_sel; wire cram_rindv_rx; wire cram_rindv_tx; wire cram_rmaster_rx; wire cram_rmaster_tx; wire cram_rmaster_up_rx; wire cram_rmaster_up_tx; wire cram_rphfifo_regmode_rx; wire [17:0] cram_rpma_done_count; wire [1:0] cram_rrcvd_clk_sel; wire cram_rrx_rd_clk_sel; wire cram_rrxfifo_urst_en; wire cram_rrxpcsclkpwdn; wire cram_rrxphfifopldctl_en; wire cram_rself_sw_en_rx; wire cram_rself_sw_en_tx; wire cram_rtxpcsclkpwdn; wire cram_rtxphfifopldctl_en; wire cram_rtxrdclksel; wire cram_rtxwrclksel; wire cram_scan_mode; // cram used in centrl_clk_ctl but not in WYS wire cram_rfreerun_centrl; wire cram_rcentrl_clk_sel; wire cram_rrefclk_out_div2; wire cram_rtxfifo_urst_en; // used in txctrl //ww12_RTL update reg init_rxaui_s2gx_en_rx; reg init_rxaui_s2gx_en_tx; wire cram_rxaui_s2gx_en_rx; wire cram_rxaui_s2gx_en_tx; reg [5:0] init_rwait_for_phfifo_cnt; wire [5:0] cram_rwait_for_phfifo_cnt; //////////////////////////////////////////////////////////////////////////////// // INPUT Filtering -----------------------------------------------------------// //////////////////////////////////////////////////////////////////////////////// wire dpclk_in; wire dpriodisable_in; wire dprioin_in; wire dprioload_in; wire [5:0] fixedclk_in; wire quadreset_in; wire [5:0] rxanalogreset_in; wire rxclk_in; wire [3:0] rxdigitalreset_in; wire [5:0] rxpowerdown_in; wire txclk_in; wire [3:0] txdigitalreset_in; wire [1:0] txpllreset_in; wire rateswitch_in; wire rateswitchdonein_in; wire rxcoreclk_in; wire rxphfifordenable_in; wire rxphfiforeset_in; wire rxphfifowrdisable_in; wire scanclk_in; wire [22:0] scanin_in; wire scanmode_in; wire scanshift_in; wire txcoreclk_in; wire txphfiforddisable_in; wire txphfiforeset_in; wire txphfifowrenable_in; //////////////////////////////////////////////////////////////////////////////// // TIMING // //////////////////////////////////////////////////////////////////////////////// wire dprioout_tim; wire dpriooe_tim; /////////////////////////////////////////////////////////////////////////// // quad_reset ---------------------------------------------------------- // /////////////////////////////////////////////////////////////////////////// wire qr_in_entest; // Test mode control from Control block wire qr_in_plniotri; // PLL output enable wire qr_in_npor; // Power on reset wire qr_in_frzreg; // Freeze register during power-up wire qr_in_pllurst; // PLL user reset // Reset CRAMs wire qr_cram_rpllurst; // Gating CRAM for PLLURST wire qr_cram_rpowerdown; // Quad power down CRAM wire qr_cram_rreset; // Quad reset CRAM // Reset outputs wire qr_out_cmu_rstb; // CMU reset wire qr_out_mdio_rst; // MDIO reset wire qr_out_hard_reset; // Output HARD_RESET signal for other MDIO modules wire qr_out_soft_reset_all_hssi; // Quad soft reset output // new in ww47 ------------------------------------------- // CMU reset inputs wire [1:0] qr_in_rxurstcmu; // Dynamic signal for CMU[1:0]_RXPMA_RSTB // CMU qr_cram_reset CRAMs wire [1:0] qr_cram_rrxurstcmu; // Gating CRAM for dynamic signal qr_cram_rxurstcmu wire [1:0] qr_cram_rrx_cmu_rst; // TXPLL / qr_cram_rXPLL qr_cram_reset // CMU powerdown inputs wire [1:0] qr_in_ucmurx_pdb; // Dynamic signal for CMU[1:0]_RX_PDB // CMU powerdown CRAMs wire [1:0] qr_cram_rclk_pdb; wire [1:0] qr_cram_rcmu_powdnr; wire [1:0] qr_cram_rcmu_cru_pdb; wire [1:0] qr_cram_rcmu_urx_pdb; wire [1:0] qr_cram_rcmu_rx_ib_pdb; wire [1:0] qr_cram_rcmu_powdnt; wire [1:0] qr_cram_rcmu_tx_ob_pdb; wire [1:0] qr_cram_rcmu_tx_cgb_pdb; wire [1:0] qr_cram_rcmu_rx_det_pdb; // CMU reset outputs - moved to chnl reset wire qr_out_cmu0_rxpma_rstb; wire qr_out_cmu0_txpma_rstb; wire qr_out_cmu0_cru_rstb; wire qr_out_cmu1_rxpma_rstb; wire qr_out_cmu1_txpma_rstb; wire qr_out_cmu1_cru_rstb; // CMU powerdown outputs - moved to chnl reset wire qr_out_cmu0_rx_pdb; wire qr_out_cmu0_cru_pdb; wire qr_out_cmu0_clk_pdb; wire qr_out_cmu0_tx_pdb; wire qr_out_cmu0_cgb_pdb; wire qr_out_cmu0_rx_det_pdb; wire qr_out_cmu1_rx_pdb; wire qr_out_cmu1_cru_pdb; wire qr_out_cmu1_clk_pdb; wire qr_out_cmu1_tx_pdb; wire qr_out_cmu1_cgb_pdb; wire qr_out_cmu1_rx_det_pdb; /////////////////////////////////////////////////////////////////////////// // channel_reset ------------------------------------------------------- // /////////////////////////////////////////////////////////////////////////// // Inputs from QUAD reset module wire chr_in_hard_reset; // hardreset signal wire chr_in_soft_reset_all_hssi;// soft reset for all channel wire chr_in_rreset; // Quad reset CRAM wire chr_in_rpowerdown; // Quad power down CRAM // Channel Reset inputs wire [5:0] chr_in_rxurstpma; // RX PMA user reset - all ch wire [3:0] chr_in_rxurstpcs; // RX PCS user reset wire [3:0] chr_in_txurstpcs; // TX PCS user reset // Channel Reset CRAMs wire chr_in_rpowdnr; // RX channel power down CRAM wire chr_in_rpowdnt; // TX channel power down CRAM wire chr_in_rrxurstpcs; // Gating CRAM for RXURSTPCS wire chr_in_rtxurstpcs; // Gating CRAM for TXURSTPCS wire chr_in_rrxurstpma; // Gating CRAM for RXURSTPMA wire chr_in_rrx_cru_rst; // Channel RX PLL reset CRAMs wire chr_in_radce_rst; // Channel Adaptive block reset CRAMs // Powerdown inputs wire [5:0] chr_in_urx_pdb; // RX user powerdown signal - all ch // Powerdown CRAMs wire chr_in_rurx_pdb; // Gating CRAM for urx_pdb signals wire chr_in_radce_pdb; // Adaptive block powerdown CRAMs wire chr_in_rrx_ib_pdb; // RX Input buffer and PLL powerdown CRAMs wire chr_in_rtx_ob_pdb; // TX Output buffer powerdown CRAMs wire chr_in_rtx_cgb_pdb; // TX clock generator powerdown CRAMs wire chr_in_rrx_cru_pdb; // RX PLL powerdown CRAMs // PIPE Inputs wire chr_in_rtx_pipe_en; // PIPE enable CRAMs wire chr_in_p0_state; // PIPE P0 state indicators wire chr_in_p0s_state; // PIPE P0S state indicators wire chr_in_p2_state; // PIPE P2 state indicators // Channel Reset outputs wire [5:0] chr_out_rxpma_rstb; // RX PMA resets (powerdown) wire [5:0] chr_out_txpma_rstb; // TX PMA resets (powerdown) wire [3:0] chr_out_rxpcs_rst; // RX PCS resets - extra dummy for 4/5 wire [3:0] chr_out_txpcs_rst; // TX PCS resets - extra dummy for 4/5 wire [5:0] chr_out_cru_rstb; // RX PLL resets wire [3:0] chr_out_adce_rstb; // Adaptive block resets //ww47 rem wire [3:0] chr_out_soft_rxrst; // SIPO reset // Channel Powerdown outputs wire [3:0] chr_out_adce_pdb; // Adaptive block powerdown wire [5:0] chr_out_cru_pdb; // RX PLL powerdown wire [5:0] chr_out_rx_pdb; // RX powerdown wire [5:0] chr_out_tx_pdb; // TX driver powerdown wire [5:0] chr_out_cgb_pdb; // Clock generator powerdown wire [5:0] chr_out_rx_det_pdb; // Receiver detector powerdown /////////////////////////////////////////////////////////////////////////// // centrl_clk_ctl ------------------------------------------------------ // /////////////////////////////////////////////////////////////////////////// // S2GX style wire refclk_pma_out; // output - Global TX PCS clock wire mdc_b; // MD Clock // refclk_out moved to clock_divider wire centrlclk_ctl_in_pclk_pma; // x4 PCLK from PMA CMU wire centrlclk_ctl_in_refclk_dig; // External digital clock wire centrlclk_ctl_in_mdc; // MDIO input clock wire centrlclk_ctl_in_ser_clk; // Serial clock wire centrlclk_ctl_in_ser_mode; // Serial shift configuration mode wire centrlclk_ctl_in_scan_mode; // Scan mode wire centrlclk_ctl_in_scan_clk; // Scan mode wire centrlclk_ctl_in_rfreerun_centrl; // REFCLK_OUT free running enable CRAM wire centrlclk_ctl_in_rcentrl_clk_sel; // REFCLK_PMA global clock selection CRAM wire centrlclk_ctl_in_rrefclk_out_div2; // REFCLK_OUT divide by 2 enable CRAM wire centrlclk_ctl_in_hard_reset; // Hard reset input wire centrlclk_ctl_in_txrst; wire centrlclk_ctl_in_gen2ngen1_bundle; wire centrlclk_ctl_out_refclk_pma_out; // Global TX PCS clock wire centrlclk_ctl_out_mdc_b; // Configuration output clock wire centrlclk_ctl_out_refclk_out; // REFCLK_OUT output clk /////////////////////////////////////////////////////////////////////////// // rxclk_ctl_ctrl ------------------------------------------------------ // /////////////////////////////////////////////////////////////////////////// // S2GX portion ---------------------------------------------------------- wire clk_1_b; // output - feeding to Deskew SM only wire clk_2_b; // output - to RCV_SM, centrl_reset wire rxclk_ctl_in_pld_rx_clk; wire rxclk_ctl_in_rcvd_clk0_pma; wire rxclk_ctl_in_refclk_pma; wire rxclk_ctl_in_scan_mode; wire rxclk_ctl_in_gen2ngen1_bundle; wire rxclk_ctl_in_rx_div2_sync_centrl; wire [1:0] rxclk_ctl_in_rrcvd_clk_sel; wire [1:0] rxclk_ctl_in_rclk_1_sel; wire [1:0] rxclk_ctl_in_rclk_2_sel; wire rxclk_ctl_in_rrx_rd_clk_sel; wire rxclk_ctl_in_rxrst; wire rxclk_ctl_in_rindv_rx; wire rxclk_ctl_in_rdwidth_rx; wire rxclk_ctl_in_rfreerun_rx; wire rxclk_ctl_in_rauto_speed_ena; wire rxclk_ctl_in_rfreq_sel; wire rxclk_ctl_in_rrxpcsclkpwdn; wire rxclk_ctl_in_rmaster_rx; wire rxclk_ctl_in_rmaster_up_rx; wire rxclk_ctl_out_clk_1_b; wire rxclk_ctl_out_clk_2_b; wire rxclk_ctl_out_rx_wr_clk; wire rxclk_ctl_out_rx_rd_clk; wire rxclk_ctl_out_rx_div2_sync_out; //unused outputs - connected for VHDL convertions and non-x (no single dummy) wire rxclk_ctl_out_fref_muxed; wire rxclk_ctl_out_clklow_muxed; wire rxclk_ctl_out_rcvd_clk; wire rxclk_ctl_out_rx_clk; wire rxclk_ctl_out_rcvd_clk_pma_b; wire rxclk_ctl_out_clk_2_b_raw; wire rxclk_ctl_out_rx_wr_clk_raw; wire rxclk_ctl_out_rx_rd_clk_raw; /////////////////////////////////////////////////////////////////////////// // txclk_ctl_ctrl ------------------------------------------------------ // /////////////////////////////////////////////////////////////////////////// // s2gx portion wire refclk_b; // output to centrl_reset and TX_SM // STRATIXIV for bundling wire txclk_ctl_in_pld_tx_clk; wire txclk_ctl_in_refclk_pma; wire txclk_ctl_in_txrst; wire txclk_ctl_in_scan_mode; wire txclk_ctl_in_gen2ngen1_bundle; wire txclk_ctl_in_tx_div2_sync_centrl; wire txclk_ctl_out_refclk_b; wire txclk_ctl_out_wr_clk_pos; wire txclk_ctl_out_fifo_rd_clk; wire txclk_ctl_out_tx_div2_sync_out; //unused outputs - connected for VHDL convertions and non-x (no single dummy) wire txclk_ctl_out_tx_clk_out; wire txclk_ctl_out_refclk_b_raw; wire txclk_ctl_out_wr_clk_pos_raw; wire txclk_ctl_out_fifo_rd_clk_raw; /////////////////////////////////////////////////////////////////////////// // centrl_reset -------------------------------------------------------- // /////////////////////////////////////////////////////////////////////////// wire rxrst_int; // to DSKW,RCV_SM, div2 on rxclk_sel (ignore) wire txrst_int; reg txrst_sync1, txrst_sync2; reg rxrst_sync1, rxrst_sync2; /////////////////////////////////////////////////////////////////////////// // auto_speed_neg ------------------------------------------------------ // /////////////////////////////////////////////////////////////////////////// wire auto_in_refclk; wire auto_in_rxpcs_rst_int; wire auto_in_rate; // high gen2 and low gen1 wire auto_in_gen2ngen1; wire auto_in_config_sel_centrl; wire auto_in_config_sel_quad_up; wire auto_in_config_sel_quad_down; wire auto_in_singleorbundle; // control signal output for bundle mode high is gen2, low is gen1 wire auto_out_config_sel; // PMA rate change control wire auto_out_pcie_switch; // RX Phase Comp // Handshake signal to PIPE interface to assert PhyStatus wire auto_out_speed_change; // Phase Comp and byte ser/deser control signals wire auto_out_dis_pc_byte; wire auto_out_reset_pc_ptrs; wire [3:0] auto_out_cs; /////////////////////////////////////////////////////////////////////////// // rx_ctl_ctrl --------------------------------------------------------- // /////////////////////////////////////////////////////////////////////////// wire rxctrl_in_soft_reset; wire rxctrl_in_clk_2; wire rxctrl_in_rx_rd_clk; // This replaces PLD_RX_CLK wire rxctrl_in_rx_wr_clk; // divided by 1 or 2 write clockwire rxctrl_in_ wire rxctrl_in_scan_mode; // scan enable wire rxctrl_in_rxfifo_urst; // User reset exclusive to rx_ctrl & below wire rxctrl_in_pld_wr_dis; // PLD write disable wire rxctrl_in_pld_re; // PLD read eanble wire rxctrl_in_dis_pc_byte; wire rxctrl_out_rx_we_out; wire rxctrl_out_wr_enable_out; wire rxctrl_out_rd_enable_out; /////////////////////////////////////////////////////////////////////////// // tx_ctl_ctrl --------------------------------------------------------- // /////////////////////////////////////////////////////////////////////////// wire txctrl_in_soft_reset; // Reset wire txctrl_in_fifo_wr_clk; // Used to be wr_clk_pos wire txctrl_in_fifo_rd_clk; // Coming from txclk_xg_ctl wire txctrl_in_refclk_b_in; // The local reference clock used by the internal wire txctrl_in_scan_mode; // scan enable wire txctrl_in_txfifo_urst; // user reset wire txctrl_in_pld_we; // PLD phase compwire txctrl_in_ fifo we, level active wire txctrl_in_pld_rd_dis; // PLD phase compwire txctrl_in_ fifo rd dis, edge active wire txctrl_in_dis_pc_byte; wire txctrl_out_wr_enable_out; // ch0 wr_enable1 output for X4/X8 mode wire txctrl_out_rd_enable_out; // ch0 rd_enable1 output for X4/X8 mode wire txctrl_out_fifo_select_out; // New output for Revwire txctrl_in_B /////////////////////////////////////////////////////////////////////////// // DSKW SM ------------------------------------------------------------- // /////////////////////////////////////////////////////////////////////////// wire [3:0] dskw_curr_st; wire alignstatus_int; // feeding to PLD and DPRIO wire dskw_sm_clk; /////////////////////////////////////////////////////////////////////////// // TX SM --------------------------------------------------------------- // /////////////////////////////////////////////////////////////////////////// wire rtx_rx_local_fault_clr_int; // from DPRIO wire rindv_tx_int; wire [3:0] tx_curr_st; wire tx_local_fault_det; // output to rx_sm wire tx_local_fault_int; // feeding nowhere wire tx_sm_clk; wire [31:0] tx_sm_datain; wire [3:0] tx_sm_ctrlin; wire tx_sm_rdenablesyncin; /////////////////////////////////////////////////////////////////////////// // RX SM --------------------------------------------------------------- // /////////////////////////////////////////////////////////////////////////// wire rindv_rx_int; // from DPRIO wire rxs_link_status_set_int; // from DPRIO wire xs_link_status_int; wire rx_local_fault_int; // feeding DPRIO wire xlink_status_int; // feeding DPRIO wire [1:0] rcv_curr_st; wire rcv_sm_clk; wire [3:0] rcv_sm_decdatavalid; wire [31:0] rcv_sm_decdata; wire [3:0] rcv_sm_decctl; wire [3:0] rcv_sm_rxrunningdisp; /////////////////////////////////////////////////////////////////////////// // DPRIO --------------------------------------------------------------- // /////////////////////////////////////////////////////////////////////////// wire [4:0] port_addr; // convert from top parameter wire [31:0] port_addr_bin; // use in int2bin function wire [4:0] dev_addr; // convert from top parameter wire [31:0] dev_addr_bin; // use in int2bin function wire mdio_rst; wire [29:0] cmudprioin; //local wrt cmu todo: rem wire [29:0] cmudprioout; //local wrt cmu todo: rem wire [2:0] mdio_curr_st; wire mdio_in; reg mdio_rst_reg; //////////////////////////////////////////////////////////////////////////////// // Const wires ---------------------------------------------------------------// //////////////////////////////////////////////////////////////////////////////// assign vcc_wire = 1'b1; assign gnd_wire = 1'b0; //////////////////////////////////////////////////////////////////////////////// // function ---------------------------------------------------------------// //////////////////////////////////////////////////////////////////////////////// function [8*`STRATIXIV_HSSI_CMU_ALPHA_TOLOWER_WORD_LENGTH:1] alpha_tolower; input [8*`STRATIXIV_HSSI_CMU_ALPHA_TOLOWER_WORD_LENGTH:1] input_string; reg [8*`STRATIXIV_HSSI_CMU_ALPHA_TOLOWER_WORD_LENGTH:1] return_string; reg [8*`STRATIXIV_HSSI_CMU_ALPHA_TOLOWER_WORD_LENGTH:1] reg_string; reg [8:1] tmp; reg [8:1] conv_char; integer byte_count; begin reg_string = input_string; for (byte_count = `STRATIXIV_HSSI_CMU_ALPHA_TOLOWER_WORD_LENGTH; byte_count >= 1; byte_count = byte_count - 1) begin tmp = reg_string[8*`STRATIXIV_HSSI_CMU_ALPHA_TOLOWER_WORD_LENGTH:(8*(`STRATIXIV_HSSI_CMU_ALPHA_TOLOWER_WORD_LENGTH-1)+1)]; reg_string = reg_string << 8; if ((tmp >= 65) && (tmp <= 90)) // ASCII number of 'A' is 65, 'Z' is 90 begin conv_char = tmp + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set return_string = {return_string, conv_char}; end else return_string = {return_string, tmp}; end alpha_tolower = return_string; end endfunction // function int2bin function [31:0] int2bin; input input_value; integer input_value; integer i; begin for (i = 0; i <= 31; i = i + 1) begin if (input_value % 2 == 0) int2bin[i] = 1'b0; else int2bin[i] = 1'b1; input_value = input_value / 2; end end endfunction // end function //////////////////////////////////////////////////////////////////////////////// // process param -------------------------------------------------------------// //////////////////////////////////////////////////////////////////////////////// initial begin init_rauto_deassert_pc_rst_cnt = auto_spd_deassert_ph_fifo_rst_count; init_rauto_pc_en_cnt = auto_spd_phystatus_notify_count; init_rauto_speed_ena = (pipe_auto_speed_nego_enable == "true") ? 1'b1 : 1'b0; init_rclk_1_sel = (rx0_clk1_mux_select == "recvd_clk" || rx0_clk1_mux_select == "recovered clock") ? 2'b00 : (rx0_clk1_mux_select == "digital_refclk" || rx0_clk1_mux_select == "digital reference clock") ? 2'b01 : (rx0_clk1_mux_select == "local_refclk" || rx0_clk1_mux_select == "local reference clock") ? 2'b10 : (rx0_clk1_mux_select == "master_clk" || rx0_clk1_mux_select == "master clock") ? 2'b11 : 2'bzz; init_rclk_2_sel = (rx0_clk2_mux_select == "recvd_clk" || rx0_clk2_mux_select == "recovered clock") ? 2'b00 : (rx0_clk2_mux_select == "digital_refclk" || rx0_clk2_mux_select == "digital reference clock") ? 2'b10 : (rx0_clk2_mux_select == "local_refclk" || rx0_clk2_mux_select == "local reference clock") ? 2'b01 : (rx0_clk2_mux_select == "core_clk" || rx0_clk2_mux_select == "core clk" || rx0_clk2_mux_select == "core clock") ? 2'b11 : 2'bzz; init_rdwidth_rx = (rx0_use_double_data_mode == "true") ? 1'b1 : 1'b0; init_rdwidth_tx = (tx0_use_double_data_mode == "true") ? 1'b1 : 1'b0; init_rfreerun_rx = (rx0_reset_clock_output_during_digital_reset == "false") ? 1'b1 : 1'b0; init_rfreerun_tx = (tx0_reset_clock_output_during_digital_reset == "false") ? 1'b1 : 1'b0; init_rfreq_sel = (alpha_tolower(pipe_freq_scale_mode) == "data width") ? 1'b0 : 1'b1; // "Data width" init_rindv_rx = (rx0_channel_bonding == "x4" || rx0_channel_bonding == "x8" || in_xaui_mode == "true") ? 1'b0 : 1'b1; init_rindv_tx = (tx0_channel_bonding == "x4" || tx0_channel_bonding == "x8" || in_xaui_mode == "true") ? 1'b0 : 1'b1; init_rmaster_rx = (rx_master_direction == "none") ? 1'b1 : 1'b0; init_rmaster_tx = (tx_master_direction == "none") ? 1'b1 : 1'b0; init_rmaster_up_rx = (rx_master_direction == "up") ? 1'b1 : 1'b0; init_rmaster_up_tx = (tx_master_direction == "up") ? 1'b1 : 1'b0; init_rphfifo_regmode_rx = (rx0_ph_fifo_reg_mode == "true") ? 1'b1 : 1'b0; init_rpma_done_count = 18'd15; // short it in simulations - pma_done_count; init_rrcvd_clk_sel = (rx0_recovered_clk_mux_select == "recvd_clk" || rx0_recovered_clk_mux_select == "recovered clock") ? 2'b00 : (rx0_recovered_clk_mux_select == "digital_refclk" || rx0_recovered_clk_mux_select == "digital reference clock") ? 2'b01 : (rx0_recovered_clk_mux_select == "local_refclk" || rx0_recovered_clk_mux_select == "local reference clock") ? 2'b10 : 2'bzz; init_rrx_rd_clk_sel = (rx0_rd_clk_mux_select == "core_clk" || rx0_rd_clk_mux_select == "core clk" || rx0_rd_clk_mux_select == "core clock") ? 1'b1 : 1'b0; init_rrxfifo_urst_en = (rx0_ph_fifo_reset_enable == "true") ? 1'b1 : 1'b0; init_rrxpcsclkpwdn = (rx0_clk_pd_enable == "true") ? 1'b1 : 1'b0; init_rrxphfifopldctl_en = (rx0_ph_fifo_user_ctrl_enable == "true") ? 1'b1 : 1'b0; init_rself_sw_en_rx = (rx0_auto_spd_self_switch_enable == "true") ? 1'b1 : 1'b0; init_rself_sw_en_tx = (tx0_auto_spd_self_switch_enable == "true") ? 1'b1 : 1'b0; init_rtxpcsclkpwdn = (tx0_clk_pd_enable == "true") ? 1'b1 : 1'b0; init_rtxphfifopldctl_en = (tx0_ph_fifo_user_ctrl_enable == "true") ? 1'b1 : 1'b0; init_rtxrdclksel = (tx0_rd_clk_mux_select == "cmu_clock_divider" || tx0_rd_clk_mux_select == "cmu clock divider") ? 1'b1 : 1'b0; // TxFifo Rd clock 1=refclk_pma, 0=local_refclk_pma init_rtxwrclksel = (tx0_wr_clk_mux_select == "int_clk" || tx0_wr_clk_mux_select == "int clk" || tx0_wr_clk_mux_select == "internal clock") ? 1'b1 : 1'b0; // TxFifo Write clk. 1=int_clk; 0=pld_tx_clk init_scan_mode = 1'b0; // cram used in centrl_clk_ctl but not in WYS init_rfreerun_centrl = init_rfreerun_rx; // REFCLK_OUT free running enable CRAM init_rcentrl_clk_sel = 1'b0; //1 - select digi_ref REFCLK_PMA global clock selection CRAM init_rrefclk_out_div2 = 1'b0; // REFCLK_OUT divide by 2 enable CRAM init_rtxfifo_urst_en = (tx0_ph_fifo_reset_enable == "true") ? 1'b1 : 1'b0; //ww12_RTL init_rxaui_s2gx_en_rx = (rx_xaui_sm_backward_compatible_enable == "true") ? 1'b1 : 1'b0; init_rxaui_s2gx_en_tx = (tx_xaui_sm_backward_compatible_enable == "true") ? 1'b1 : 1'b0; init_rwait_for_phfifo_cnt = 6'b100000; //ww12_rtl todo: rx0_phfifo_wait_cnt (295112) end //////////////////////////////////////////////////////////////////////////////// // CRAM ----------------------------------------------------------------------// //////////////////////////////////////////////////////////////////////////////// assign cram_rauto_deassert_pc_rst_cnt = init_rauto_deassert_pc_rst_cnt; assign cram_rauto_pc_en_cnt = init_rauto_pc_en_cnt; assign cram_rauto_speed_ena = init_rauto_speed_ena; assign cram_rclk_1_sel = init_rclk_1_sel; assign cram_rclk_2_sel = init_rclk_2_sel; assign cram_rdwidth_rx = init_rdwidth_rx; assign cram_rdwidth_tx = init_rdwidth_tx; assign cram_rfreerun_rx = init_rfreerun_rx; assign cram_rfreerun_tx = init_rfreerun_tx; assign cram_rfreq_sel = init_rfreq_sel; assign cram_rindv_rx = init_rindv_rx; assign cram_rindv_tx = init_rindv_tx; assign cram_rmaster_rx = init_rmaster_rx; assign cram_rmaster_tx = init_rmaster_tx; assign cram_rmaster_up_rx = init_rmaster_up_rx; assign cram_rmaster_up_tx = init_rmaster_up_tx; assign cram_rphfifo_regmode_rx = init_rphfifo_regmode_rx; assign cram_rpma_done_count = init_rpma_done_count; assign cram_rrcvd_clk_sel = init_rrcvd_clk_sel; assign cram_rrx_rd_clk_sel = init_rrx_rd_clk_sel; assign cram_rrxfifo_urst_en = init_rrxfifo_urst_en; assign cram_rrxpcsclkpwdn = init_rrxpcsclkpwdn; assign cram_rrxphfifopldctl_en = init_rrxphfifopldctl_en; assign cram_rself_sw_en_rx = init_rself_sw_en_rx; assign cram_rself_sw_en_tx = init_rself_sw_en_tx; assign cram_rtxpcsclkpwdn = init_rtxpcsclkpwdn; assign cram_rtxphfifopldctl_en = init_rtxphfifopldctl_en; assign cram_rtxrdclksel = init_rtxrdclksel; assign cram_rtxwrclksel = init_rtxwrclksel; assign cram_scan_mode = init_scan_mode; // cram used in centrl_clk_ctl but not in WYS assign cram_rfreerun_centrl = init_rfreerun_centrl; assign cram_rcentrl_clk_sel = init_rcentrl_clk_sel; assign cram_rrefclk_out_div2 = init_rrefclk_out_div2; assign cram_rtxfifo_urst_en = init_rtxfifo_urst_en; // used in txctrl //ww12_RTL assign cram_rxaui_s2gx_en_rx = init_rxaui_s2gx_en_rx; assign cram_rxaui_s2gx_en_tx = init_rxaui_s2gx_en_tx; assign cram_rwait_for_phfifo_cnt = init_rwait_for_phfifo_cnt; //////////////////////////////////////////////////////////////////////////////// // INPUT Filtering -----------------------------------------------------------// //////////////////////////////////////////////////////////////////////////////// assign dpclk_in = (dpclk === 1'b1) ? 1'b1 : 1'b0; assign dpriodisable_in = (dpriodisable === 1'b0) ? 1'b0 : 1'b1; assign dprioin_in = dprioin; // z is part of protocol assign dprioload_in = (dprioload === 1'b1) ? 1'b1 : 1'b0; assign fixedclk_in[0] = (fixedclk[0] === 1'b1) ? 1'b1 : 1'b0; assign fixedclk_in[1] = (fixedclk[1] === 1'b1) ? 1'b1 : 1'b0; assign fixedclk_in[2] = (fixedclk[2] === 1'b1) ? 1'b1 : 1'b0; assign fixedclk_in[3] = (fixedclk[3] === 1'b1) ? 1'b1 : 1'b0; assign fixedclk_in[4] = (fixedclk[4] === 1'b1) ? 1'b1 : 1'b0; assign fixedclk_in[5] = (fixedclk[5] === 1'b1) ? 1'b1 : 1'b0; assign quadreset_in = (quadreset === 1'b1) ? 1'b1 : 1'b0; assign rxanalogreset_in[0] = (rxanalogreset[0] === 1'b1) ? 1'b1 : 1'b0; assign rxanalogreset_in[1] = (rxanalogreset[1] === 1'b1) ? 1'b1 : 1'b0; assign rxanalogreset_in[2] = (rxanalogreset[2] === 1'b1) ? 1'b1 : 1'b0; assign rxanalogreset_in[3] = (rxanalogreset[3] === 1'b1) ? 1'b1 : 1'b0; assign rxanalogreset_in[4] = (rxanalogreset[4] === 1'b1) ? 1'b1 : 1'b0; assign rxanalogreset_in[5] = (rxanalogreset[5] === 1'b1) ? 1'b1 : 1'b0; assign rxclk_in = (rxclk === 1'b1) ? 1'b1 : 1'b0; assign rxdigitalreset_in[0] = (rxdigitalreset[0] === 1'b1) ? 1'b1 : 1'b0; assign rxdigitalreset_in[1] = (rxdigitalreset[1] === 1'b1) ? 1'b1 : 1'b0; assign rxdigitalreset_in[2] = (rxdigitalreset[2] === 1'b1) ? 1'b1 : 1'b0; assign rxdigitalreset_in[3] = (rxdigitalreset[3] === 1'b1) ? 1'b1 : 1'b0; assign rxpowerdown_in[0] = (rxpowerdown[0] === 1'b1) ? 1'b0 : 1'b1; //inverted assign rxpowerdown_in[1] = (rxpowerdown[1] === 1'b1) ? 1'b0 : 1'b1; //inverted assign rxpowerdown_in[2] = (rxpowerdown[2] === 1'b1) ? 1'b0 : 1'b1; //inverted assign rxpowerdown_in[3] = (rxpowerdown[3] === 1'b1) ? 1'b0 : 1'b1; //inverted assign rxpowerdown_in[4] = (rxpowerdown[4] === 1'b1) ? 1'b0 : 1'b1; //inverted assign rxpowerdown_in[5] = (rxpowerdown[5] === 1'b1) ? 1'b0 : 1'b1; //inverted assign txclk_in = (txclk === 1'b1) ? 1'b1 : 1'b0; assign txdigitalreset_in[0] = (txdigitalreset[0] === 1'b1) ? 1'b1 : 1'b0; assign txdigitalreset_in[1] = (txdigitalreset[1] === 1'b1) ? 1'b1 : 1'b0; assign txdigitalreset_in[2] = (txdigitalreset[2] === 1'b1) ? 1'b1 : 1'b0; assign txdigitalreset_in[3] = (txdigitalreset[3] === 1'b1) ? 1'b1 : 1'b0; assign txpllreset_in[0] = (txpllreset[0] === 1'b1) ? 1'b1 : 1'b0; assign txpllreset_in[1] = (txpllreset[1] === 1'b1) ? 1'b1 : 1'b0; // new one added in ww47 assign rateswitch_in = rateswitch; assign rateswitchdonein_in = rateswitchdonein; assign rxcoreclk_in = rxcoreclk; assign rxphfifordenable_in = rxphfifordenable; assign rxphfiforeset_in = rxphfiforeset; assign rxphfifowrdisable_in = rxphfifowrdisable; assign scanclk_in = (scanclk === 1'b1) ? 1'b1 : 1'b0; assign scanin_in = (scanin === 1'b1) ? 1'b1 : 1'b0; assign scanmode_in = (scanmode === 1'b1) ? 1'b1 : 1'b0; assign scanshift_in = (scanshift === 1'b1) ? 1'b1 : 1'b0; assign txcoreclk_in = txcoreclk; assign txphfiforddisable_in = txphfiforddisable; assign txphfiforeset_in = txphfiforeset; assign txphfifowrenable_in = txphfifowrenable; //////////////////////////////////////////////////////////////////////////////// // TIMING -- TCO/TSU/HOLD // //////////////////////////////////////////////////////////////////////////////// specify $setuphold(posedge dpclk, dprioin, 0, 0); (posedge dpclk => (dprioout +: dprioout_tim)) = (0, 0); (posedge dpclk => (dpriooe +: dpriooe_tim)) = (0, 0); endspecify //assign dprioout = dprioout_tim; //assign dpriooe = dpriooe_tim; /////////////////////////////////////////////////////////////////////////// // quad_reset inst ----------------------------------------------------- // /////////////////////////////////////////////////////////////////////////// assign qr_in_entest = 1'b0; // Test mode control from Control block assign qr_in_plniotri = 1'b1; // PLL output enable assign qr_in_npor = 1'b1; // Power on reset assign qr_in_frzreg = 1'b0; // Freeze register during power-up assign qr_in_pllurst = (quadreset_in === 1'b1) ? 1'b1 : 1'b0; // PLL user reset // enable corresponding port by default in simulation assign qr_cram_rpllurst = 1'b1; // Gating CRAM for PLLURST assign qr_cram_rpowerdown = 1'b0; // Quad power down CRAM assign qr_cram_rreset = 1'b0; // Quad reset CRAM - scan_mode ? 1'b0 : rreset; // CMU0/1 reset - moved rx_pll, rx_pma and tx_pma resets to chnl reset [4:5] // but kept CMU_PLL (LC_PLL) resets in Quadreset assign qr_in_rxurstcmu = txpllreset_in; assign qr_in_ucmurx_pdb = 2'b00; // no WYS ports for txpll powerdn // CMU qr_cram_reset CRAMs assign qr_cram_rrxurstcmu = 2'b11; // Gating CRAM for dynamic signal rxurstcmu assign qr_cram_rrx_cmu_rst = 2'b00; // TXPLL / RXPLL reset // CMU powerdown CRAMs assign qr_cram_rclk_pdb = 2'b00; //generating cmu0/1_clk_pdb assign qr_cram_rcmu_powdnr = 2'b00; assign qr_cram_rcmu_cru_pdb = 2'b11; assign qr_cram_rcmu_urx_pdb = 2'b11; assign qr_cram_rcmu_rx_ib_pdb = 2'b11; assign qr_cram_rcmu_powdnt = 2'b00; assign qr_cram_rcmu_tx_ob_pdb = 2'b11; assign qr_cram_rcmu_tx_cgb_pdb = 2'b11; assign qr_cram_rcmu_rx_det_pdb = 2'b11; // Moved cmu0/cmu1 reset/powerdown out to channel reset // still controls cmu_pll/cmu_clk_divider and hardreset stratixiv_hssi_cmu_quad_reset quad_reset_1 ( .entest (qr_in_entest ), .plniotri (qr_in_plniotri ), .npor (qr_in_npor ), .frzreg (qr_in_frzreg ), .pllurst (qr_in_pllurst ), .rpllurst (qr_cram_rpllurst ), .rreset (qr_cram_rreset ), .rpowerdown (qr_cram_rpowerdown ), // CMU reset inputs .rxurstcmu (qr_in_rxurstcmu ), // CMU reset CRAMs .rrxurstcmu (qr_cram_rrxurstcmu ), .rrx_cmu_rst (qr_cram_rrx_cmu_rst ), // CMU powerdown inputs .ucmurx_pdb (qr_in_ucmurx_pdb ), // CMU powerdown CRAMs .rclk_pdb (qr_cram_rclk_pdb ), .rcmu_powdnr (qr_cram_rcmu_powdnr ), .rcmu_cru_pdb (qr_cram_rcmu_cru_pdb ), .rcmu_urx_pdb (qr_cram_rcmu_urx_pdb ), .rcmu_rx_ib_pdb (qr_cram_rcmu_rx_ib_pdb ), .rcmu_powdnt (qr_cram_rcmu_powdnt ), .rcmu_tx_ob_pdb (qr_cram_rcmu_tx_ob_pdb ), .rcmu_tx_cgb_pdb (qr_cram_rcmu_tx_cgb_pdb ), .rcmu_rx_det_pdb (qr_cram_rcmu_rx_det_pdb ), // CMU reset outputs .cmu0_rxpma_rstb (qr_out_cmu0_rxpma_rstb ), .cmu0_txpma_rstb (qr_out_cmu0_txpma_rstb ), .cmu0_cru_rstb (qr_out_cmu0_cru_rstb ), .cmu1_rxpma_rstb (qr_out_cmu1_rxpma_rstb ), .cmu1_txpma_rstb (qr_out_cmu1_txpma_rstb ), .cmu1_cru_rstb (qr_out_cmu1_cru_rstb ), // CMU powerdown outputs .cmu0_rx_pdb (qr_out_cmu0_rx_pdb ), .cmu0_cru_pdb (qr_out_cmu0_cru_pdb ), .cmu0_clk_pdb (qr_out_cmu0_clk_pdb ), .cmu0_tx_pdb (qr_out_cmu0_tx_pdb ), .cmu0_cgb_pdb (qr_out_cmu0_cgb_pdb ), .cmu0_rx_det_pdb (qr_out_cmu0_rx_det_pdb ), .cmu1_rx_pdb (qr_out_cmu1_rx_pdb ), .cmu1_cru_pdb (qr_out_cmu1_cru_pdb ), .cmu1_clk_pdb (qr_out_cmu1_clk_pdb ), .cmu1_tx_pdb (qr_out_cmu1_tx_pdb ), .cmu1_cgb_pdb (qr_out_cmu1_cgb_pdb ), .cmu1_rx_det_pdb (qr_out_cmu1_rx_det_pdb ), // Other outputs .mdio_rst (qr_out_mdio_rst ), .hard_reset (qr_out_hard_reset ), .soft_reset_all_hssi (qr_out_soft_reset_all_hssi) ); /////////////////////////////////////////////////////////////////////////// // chnl_reset inst ----------------------------------------------------- // /////////////////////////////////////////////////////////////////////////// assign chr_in_hard_reset = qr_out_hard_reset; // hardreset signal assign chr_in_soft_reset_all_hssi = qr_out_soft_reset_all_hssi;// soft reset for all channel assign chr_in_rreset = qr_cram_rreset; // Quad reset CRAM assign chr_in_rpowerdown = qr_cram_rpowerdown; // Quad power down CRAM // Channel Reset inputs assign chr_in_rxurstpma = rxanalogreset_in; // RX PMA user reset assign chr_in_rxurstpcs = rxdigitalreset_in; // RX PCS user reset assign chr_in_txurstpcs = txdigitalreset_in; // TX PCS user reset // Channel Reset CRAMs assign chr_in_rpowdnr = 1'b0; // RX channel power down CRAM assign chr_in_rpowdnt = 1'b0; // TX channel power down CRAM assign chr_in_rrxurstpcs = 1'b1; // Gating CRAM for RXURSTPCS assign chr_in_rtxurstpcs = 1'b1; // Gating CRAM for TXURSTPCS assign chr_in_rrxurstpma = 1'b1; // Gating CRAM for RXURSTPMA assign chr_in_rrx_cru_rst = 1'b0; // Channel RX PLL reset CRAMs assign chr_in_radce_rst = 1'b0; // Channel Adaptive block reset CRAMs // Powerdown inputs assign chr_in_urx_pdb = rxpowerdown_in; // RX user powerdown signal // Powerdown CRAMs - active low assign chr_in_rurx_pdb = 1'b1; // Gating CRAM for urx_pdb signals assign chr_in_radce_pdb = 1'b1; // Adaptive block powerdown CRAMs assign chr_in_rrx_ib_pdb = 1'b1; // RX Input buffer and PLL powerdown CRAMs assign chr_in_rtx_ob_pdb = 1'b1; // TX Output buffer powerdown CRAMs assign chr_in_rtx_cgb_pdb = 1'b1; // TX clock generator powerdown CRAMs assign chr_in_rrx_cru_pdb = 1'b1; // RX PLL powerdown CRAMs // PIPE Inputs assign chr_in_rtx_pipe_en = 1'b0; // PIPE enable CRAMs //todo: revisit - signal from tx_PIPE_INTERFACE_TOP assign chr_in_p0_state = 1'b0; // PIPE P0 state indicators assign chr_in_p0s_state = 1'b0; // PIPE P0S state indicators assign chr_in_p2_state = 1'b0; // PIPE P2 state indicators // Channel-based reset logic (for both PCS and PMA channel) stratixiv_hssi_cmu_chnl_reset chnl_reset0 ( .hard_reset (chr_in_hard_reset), .soft_reset_all_hssi (chr_in_soft_reset_all_hssi), .rreset (chr_in_rreset), .rpowerdown (chr_in_rpowerdown), .rxurstpma (chr_in_rxurstpma[0]), .rxurstpcs (chr_in_rxurstpcs[0]), .txurstpcs (chr_in_txurstpcs[0]), .rpowdnr (chr_in_rpowdnr), .rpowdnt (chr_in_rpowdnt), .rrxurstpcs (chr_in_rrxurstpcs), .rtxurstpcs (chr_in_rtxurstpcs), .rrxurstpma (chr_in_rrxurstpma), .rrx_cru_rst (chr_in_rrx_cru_rst), .radce_rst (chr_in_radce_rst), .urx_pdb (chr_in_urx_pdb[0]), .rurx_pdb (chr_in_rurx_pdb), .radce_pdb (chr_in_radce_pdb), .rrx_ib_pdb (chr_in_rrx_ib_pdb), .rtx_ob_pdb (chr_in_rtx_ob_pdb), .rtx_cgb_pdb (chr_in_rtx_cgb_pdb), .rrx_cru_pdb (chr_in_rrx_cru_pdb), .rtx_pipe_en (chr_in_rtx_pipe_en), .p0_state (chr_in_p0_state), .p0s_state (chr_in_p0s_state), .p2_state (chr_in_p2_state), .rxpma_rstb (chr_out_rxpma_rstb[0]), .txpma_rstb (chr_out_txpma_rstb[0]), .rxpcs_rst (chr_out_rxpcs_rst[0]), .txpcs_rst (chr_out_txpcs_rst[0]), .cru_rstb (chr_out_cru_rstb[0]), .adce_rstb (chr_out_adce_rstb[0]), .adce_pdb (chr_out_adce_pdb[0]), .cru_pdb (chr_out_cru_pdb[0]), .rx_pdb (chr_out_rx_pdb[0]), .tx_pdb (chr_out_tx_pdb[0]), .cgb_pdb (chr_out_cgb_pdb[0]), .rx_det_pdb (chr_out_rx_det_pdb[0]) ); stratixiv_hssi_cmu_chnl_reset chnl_reset1 ( .hard_reset (chr_in_hard_reset), .soft_reset_all_hssi (chr_in_soft_reset_all_hssi), .rreset (chr_in_rreset), .rpowerdown (chr_in_rpowerdown), .rxurstpma (chr_in_rxurstpma[1]), .rxurstpcs (chr_in_rxurstpcs[1]), .txurstpcs (chr_in_txurstpcs[1]), .rpowdnr (chr_in_rpowdnr), .rpowdnt (chr_in_rpowdnt), .rrxurstpcs (chr_in_rrxurstpcs), .rtxurstpcs (chr_in_rtxurstpcs), .rrxurstpma (chr_in_rrxurstpma), .rrx_cru_rst (chr_in_rrx_cru_rst), .radce_rst (chr_in_radce_rst), .urx_pdb (chr_in_urx_pdb[1]), .rurx_pdb (chr_in_rurx_pdb), .radce_pdb (chr_in_radce_pdb), .rrx_ib_pdb (chr_in_rrx_ib_pdb), .rtx_ob_pdb (chr_in_rtx_ob_pdb), .rtx_cgb_pdb (chr_in_rtx_cgb_pdb), .rrx_cru_pdb (chr_in_rrx_cru_pdb), .rtx_pipe_en (chr_in_rtx_pipe_en), .p0_state (chr_in_p0_state), .p0s_state (chr_in_p0s_state), .p2_state (chr_in_p2_state), .rxpma_rstb (chr_out_rxpma_rstb[1]), .txpma_rstb (chr_out_txpma_rstb[1]), .rxpcs_rst (chr_out_rxpcs_rst[1]), .txpcs_rst (chr_out_txpcs_rst[1]), .cru_rstb (chr_out_cru_rstb[1]), .adce_rstb (chr_out_adce_rstb[1]), .adce_pdb (chr_out_adce_pdb[1]), .cru_pdb (chr_out_cru_pdb[1]), .rx_pdb (chr_out_rx_pdb[1]), .tx_pdb (chr_out_tx_pdb[1]), .cgb_pdb (chr_out_cgb_pdb[1]), .rx_det_pdb (chr_out_rx_det_pdb[1]) ); stratixiv_hssi_cmu_chnl_reset chnl_reset2 ( .hard_reset (chr_in_hard_reset), .soft_reset_all_hssi (chr_in_soft_reset_all_hssi), .rreset (chr_in_rreset), .rpowerdown (chr_in_rpowerdown), .rxurstpma (chr_in_rxurstpma[2]), .rxurstpcs (chr_in_rxurstpcs[2]), .txurstpcs (chr_in_txurstpcs[2]), .rpowdnr (chr_in_rpowdnr), .rpowdnt (chr_in_rpowdnt), .rrxurstpcs (chr_in_rrxurstpcs), .rtxurstpcs (chr_in_rtxurstpcs), .rrxurstpma (chr_in_rrxurstpma), .rrx_cru_rst (chr_in_rrx_cru_rst), .radce_rst (chr_in_radce_rst), .urx_pdb (chr_in_urx_pdb[2]), .rurx_pdb (chr_in_rurx_pdb), .radce_pdb (chr_in_radce_pdb), .rrx_ib_pdb (chr_in_rrx_ib_pdb), .rtx_ob_pdb (chr_in_rtx_ob_pdb), .rtx_cgb_pdb (chr_in_rtx_cgb_pdb), .rrx_cru_pdb (chr_in_rrx_cru_pdb), .rtx_pipe_en (chr_in_rtx_pipe_en), .p0_state (chr_in_p0_state), .p0s_state (chr_in_p0s_state), .p2_state (chr_in_p2_state), .rxpma_rstb (chr_out_rxpma_rstb[2]), .txpma_rstb (chr_out_txpma_rstb[2]), .rxpcs_rst (chr_out_rxpcs_rst[2]), .txpcs_rst (chr_out_txpcs_rst[2]), .cru_rstb (chr_out_cru_rstb[2]), .adce_rstb (chr_out_adce_rstb[2]), .adce_pdb (chr_out_adce_pdb[2]), .cru_pdb (chr_out_cru_pdb[2]), .rx_pdb (chr_out_rx_pdb[2]), .tx_pdb (chr_out_tx_pdb[2]), .cgb_pdb (chr_out_cgb_pdb[2]), .rx_det_pdb (chr_out_rx_det_pdb[2]) ); stratixiv_hssi_cmu_chnl_reset chnl_reset3 ( .hard_reset (chr_in_hard_reset), .soft_reset_all_hssi (chr_in_soft_reset_all_hssi), .rreset (chr_in_rreset), .rpowerdown (chr_in_rpowerdown), .rxurstpma (chr_in_rxurstpma[3]), .rxurstpcs (chr_in_rxurstpcs[3]), .txurstpcs (chr_in_txurstpcs[3]), .rpowdnr (chr_in_rpowdnr), .rpowdnt (chr_in_rpowdnt), .rrxurstpcs (chr_in_rrxurstpcs), .rtxurstpcs (chr_in_rtxurstpcs), .rrxurstpma (chr_in_rrxurstpma), .rrx_cru_rst (chr_in_rrx_cru_rst), .radce_rst (chr_in_radce_rst), .urx_pdb (chr_in_urx_pdb[3]), .rurx_pdb (chr_in_rurx_pdb), .radce_pdb (chr_in_radce_pdb), .rrx_ib_pdb (chr_in_rrx_ib_pdb), .rtx_ob_pdb (chr_in_rtx_ob_pdb), .rtx_cgb_pdb (chr_in_rtx_cgb_pdb), .rrx_cru_pdb (chr_in_rrx_cru_pdb), .rtx_pipe_en (chr_in_rtx_pipe_en), .p0_state (chr_in_p0_state), .p0s_state (chr_in_p0s_state), .p2_state (chr_in_p2_state), .rxpma_rstb (chr_out_rxpma_rstb[3]), .txpma_rstb (chr_out_txpma_rstb[3]), .rxpcs_rst (chr_out_rxpcs_rst[3]), .txpcs_rst (chr_out_txpcs_rst[3]), .cru_rstb (chr_out_cru_rstb[3]), .adce_rstb (chr_out_adce_rstb[3]), .adce_pdb (chr_out_adce_pdb[3]), .cru_pdb (chr_out_cru_pdb[3]), .rx_pdb (chr_out_rx_pdb[3]), .tx_pdb (chr_out_tx_pdb[3]), .cgb_pdb (chr_out_cgb_pdb[3]), .rx_det_pdb (chr_out_rx_det_pdb[3]) ); // channel 4 stratixiv_hssi_cmu_chnl_reset cmu0_reset ( .hard_reset (chr_in_hard_reset), .soft_reset_all_hssi (chr_in_soft_reset_all_hssi), .rreset (chr_in_rreset), .rpowerdown (chr_in_rpowerdown), .rxurstpma (chr_in_rxurstpma[4]), .rxurstpcs (gnd_wire), .txurstpcs (gnd_wire), .rpowdnr (chr_in_rpowdnr), .rpowdnt (chr_in_rpowdnt), .rrxurstpcs (chr_in_rrxurstpcs), .rtxurstpcs (chr_in_rtxurstpcs), .rrxurstpma (chr_in_rrxurstpma), .rrx_cru_rst (chr_in_rrx_cru_rst), .radce_rst (chr_in_radce_rst), .urx_pdb (chr_in_urx_pdb[4]), .rurx_pdb (chr_in_rurx_pdb), .radce_pdb (chr_in_radce_pdb), .rrx_ib_pdb (chr_in_rrx_ib_pdb), .rtx_ob_pdb (chr_in_rtx_ob_pdb), .rtx_cgb_pdb (chr_in_rtx_cgb_pdb), .rrx_cru_pdb (chr_in_rrx_cru_pdb), .rtx_pipe_en (chr_in_rtx_pipe_en), .p0_state (chr_in_p0_state), .p0s_state (chr_in_p0s_state), .p2_state (chr_in_p2_state), .rxpma_rstb (chr_out_rxpma_rstb[4]), .txpma_rstb (chr_out_txpma_rstb[4]), .rxpcs_rst (dummy_wire), .txpcs_rst (dummy_wire), .cru_rstb (chr_out_cru_rstb[4]), .adce_rstb (dummy_wire), .adce_pdb (dummy_wire), .cru_pdb (chr_out_cru_pdb[4]), .rx_pdb (chr_out_rx_pdb[4]), .tx_pdb (chr_out_tx_pdb[4]), .cgb_pdb (chr_out_cgb_pdb[4]), .rx_det_pdb (chr_out_rx_det_pdb[4]) ); // channel 5 stratixiv_hssi_cmu_chnl_reset cmu1_reset ( .hard_reset (chr_in_hard_reset), .soft_reset_all_hssi (chr_in_soft_reset_all_hssi), .rreset (chr_in_rreset), .rpowerdown (chr_in_rpowerdown), .rxurstpma (chr_in_rxurstpma[5]), .rxurstpcs (gnd_wire), .txurstpcs (gnd_wire), .rpowdnr (chr_in_rpowdnr), .rpowdnt (chr_in_rpowdnt), .rrxurstpcs (chr_in_rrxurstpcs), .rtxurstpcs (chr_in_rtxurstpcs), .rrxurstpma (chr_in_rrxurstpma), .rrx_cru_rst (chr_in_rrx_cru_rst), .radce_rst (chr_in_radce_rst), .urx_pdb (chr_in_urx_pdb[5]), .rurx_pdb (chr_in_rurx_pdb), .radce_pdb (chr_in_radce_pdb), .rrx_ib_pdb (chr_in_rrx_ib_pdb), .rtx_ob_pdb (chr_in_rtx_ob_pdb), .rtx_cgb_pdb (chr_in_rtx_cgb_pdb), .rrx_cru_pdb (chr_in_rrx_cru_pdb), .rtx_pipe_en (chr_in_rtx_pipe_en), .p0_state (chr_in_p0_state), .p0s_state (chr_in_p0s_state), .p2_state (chr_in_p2_state), .rxpma_rstb (chr_out_rxpma_rstb[5]), .txpma_rstb (chr_out_txpma_rstb[5]), .rxpcs_rst (dummy_wire), .txpcs_rst (dummy_wire), .cru_rstb (chr_out_cru_rstb[5]), .adce_rstb (dummy_wire), .adce_pdb (dummy_wire), .cru_pdb (chr_out_cru_pdb[5]), .rx_pdb (chr_out_rx_pdb[5]), .tx_pdb (chr_out_tx_pdb[5]), .cgb_pdb (chr_out_cgb_pdb[5]), .rx_det_pdb (chr_out_rx_det_pdb[5]) ); /////////////////////////////////////////////////////////////////////////// // centrl_clk_ctl ------------------------------------------------------ // /////////////////////////////////////////////////////////////////////////// assign refclk_pma_out = centrlclk_ctl_out_refclk_pma_out; // txclk_in <= pclk/digitalrefclkout assign mdc_b = centrlclk_ctl_out_mdc_b; // dpclk_in; // refclk_out is moved to (cmu) clock_divider atom: // it has /2 and gen2ngen1 bundle logic and rfreq_sel control assign centrlclk_ctl_in_pclk_pma = txclk_in; //todo: WYS to add x4 PCLK from PMA CMU assign centrlclk_ctl_in_refclk_dig = txclk_in; //todo: External digital clock - moved to cmu_clock_divider assign centrlclk_ctl_in_mdc = dpclk_in; // MDIO input clock assign centrlclk_ctl_in_ser_clk = 1'b0; // Serial clock assign centrlclk_ctl_in_ser_mode = 1'b0; // Serial shift configuration mode assign centrlclk_ctl_in_scan_mode = scanmode_in; // Scan mode assign centrlclk_ctl_in_scan_clk = scanclk_in; // Scan mode assign centrlclk_ctl_in_hard_reset = qr_out_hard_reset; // Hard reset input assign centrlclk_ctl_in_txrst = txrst_int; assign centrlclk_ctl_in_gen2ngen1_bundle = rateswitchdonein_in; stratixiv_hssi_cmu_clk_ctl mcmu_centrlclk_ctl ( .pclk_pma (centrlclk_ctl_in_pclk_pma), .refclk_dig (centrlclk_ctl_in_refclk_dig), .mdc (centrlclk_ctl_in_mdc), .ser_clk (centrlclk_ctl_in_ser_clk), .ser_mode (centrlclk_ctl_in_ser_mode), .scan_mode (centrlclk_ctl_in_scan_mode), .scan_clk (centrlclk_ctl_in_scan_clk), .rfreerun_centrl (cram_rfreerun_centrl), .rcentrl_clk_sel (cram_rcentrl_clk_sel), .rrefclk_out_div2 (cram_rrefclk_out_div2), .hard_reset (centrlclk_ctl_in_hard_reset), .txrst (centrlclk_ctl_in_txrst), .rauto_speed_ena (cram_rauto_speed_ena), .rfreq_sel (cram_rfreq_sel), .gen2ngen1_bundle (centrlclk_ctl_in_gen2ngen1_bundle), .refclk_pma_out (centrlclk_ctl_out_refclk_pma_out), .mdc_b (centrlclk_ctl_out_mdc_b), .refclk_out (centrlclk_ctl_out_refclk_out) ); /////////////////////////////////////////////////////////////////////////// // rxclk_ctl_ctrl inst ------------------------------------------------- // /////////////////////////////////////////////////////////////////////////// // for S2GX portion assign clk_1_b = rxclk_ctl_out_clk_1_b; //recovclk - from ch0 of recover_clk assign clk_2_b = rxclk_ctl_out_clk_2_b; //rxclk_in - masterclk in XAUI, not work for other x4 // for STRATIXIV bundling - // - copy rx_ch0 clocking select info here to generate FIFO_bundle_ptrs_centrl assign rxclk_ctl_in_pld_rx_clk = rxcoreclk_in; assign rxclk_ctl_in_rcvd_clk0_pma = recovclk; assign rxclk_ctl_in_refclk_pma = centrlclk_ctl_out_refclk_pma_out; assign rxclk_ctl_in_scan_mode = scanmode_in; assign rxclk_ctl_in_gen2ngen1_bundle = rateswitchdonein_in; assign rxclk_ctl_in_rx_div2_sync_centrl = rxclk_ctl_out_rx_div2_sync_out; assign rxclk_ctl_in_rxrst = txrst_int; // from centrl_reset stratixiv_hssi_cmu_rxclk_ctl mcmu_rxclk_ctl ( .pld_rx_clk (rxclk_ctl_in_pld_rx_clk), .rcvd_clk_pma (gnd_wire), .rcvd_clk0_pma (rxclk_ctl_in_rcvd_clk0_pma), .tx_pma_clk (gnd_wire), .refclk_pma (rxclk_ctl_in_refclk_pma), .fref (gnd_wire), .clklow (gnd_wire), .scan_mode (rxclk_ctl_in_scan_mode), .gen2ngen1 (rxclk_ctl_in_gen2ngen1_bundle), // ww35.2008 (gnd_wire), .gen2ngen1_bundle (rxclk_ctl_in_gen2ngen1_bundle), .rx_div2_sync_centrl (rxclk_ctl_in_rx_div2_sync_centrl), .rx_div2_sync_quad_up (gnd_wire), .rx_div2_sync_quad_down (gnd_wire), .rrcvd_clk_sel (cram_rrcvd_clk_sel), .rclk_1_sel (cram_rclk_1_sel), .rclk_2_sel (cram_rclk_2_sel), .rrx_rd_clk_sel (cram_rrx_rd_clk_sel), .rxrst (rxclk_ctl_in_rxrst), .rindv_rx (vcc_wire), // ww35.2008 (cram_rindv_rx), .rdwidth_rx (cram_rdwidth_rx), .rfreerun_rx (cram_rfreerun_rx), .rauto_speed_ena (cram_rauto_speed_ena), .rfreq_sel (cram_rfreq_sel), .rrxpcsclkpwdn (gnd_wire), .rmaster_rx (vcc_wire), // ww35.2008 (cram_rmaster_rx), .rmaster_up_rx (cram_rmaster_up_rx), .rself_sw_en_rx (gnd_wire), .fref_muxed (rxclk_ctl_out_fref_muxed), .clklow_muxed (rxclk_ctl_out_clklow_muxed), .rcvd_clk (rxclk_ctl_out_rcvd_clk), .clk_1_b (rxclk_ctl_out_clk_1_b), .clk_2_b (rxclk_ctl_out_clk_2_b), .rx_wr_clk (rxclk_ctl_out_rx_wr_clk), .rx_rd_clk (rxclk_ctl_out_rx_rd_clk), .rx_clk (rxclk_ctl_out_rx_clk), .rcvd_clk_pma_b (rxclk_ctl_out_rcvd_clk_pma_b), .clk_2_b_raw (rxclk_ctl_out_clk_2_b_raw), .rx_wr_clk_raw (rxclk_ctl_out_rx_wr_clk_raw), .rx_rd_clk_raw (rxclk_ctl_out_rx_rd_clk_raw), .rx_div2_sync_out (rxclk_ctl_out_rx_div2_sync_out) ); /////////////////////////////////////////////////////////////////////////// // txclk_ctl_centrl inst ------------------------------------------------- // /////////////////////////////////////////////////////////////////////////// // s2gx style assign refclk_b = refclk_pma_out; // output to centrl_reset and TX_SM // STRATIXIV for bundling assign txclk_ctl_in_pld_tx_clk = txcoreclk_in; assign txclk_ctl_in_refclk_pma = centrlclk_ctl_out_refclk_pma_out; assign txclk_ctl_in_txrst = txrst_int; assign txclk_ctl_in_scan_mode = scanmode_in; assign txclk_ctl_in_gen2ngen1_bundle = rateswitchdonein_in; assign txclk_ctl_in_tx_div2_sync_centrl = txclk_ctl_out_tx_div2_sync_out; // Clock selection logic and muxes for refclk_b stratixiv_hssi_cmu_txclk_ctl mcmu_txclk_ctl( .pld_tx_clk (txclk_ctl_in_pld_tx_clk), .refclk_pma (txclk_ctl_in_refclk_pma), .txpma_local_clk (gnd_wire), .txrst (txclk_ctl_in_txrst), .scan_mode (txclk_ctl_in_scan_mode), .gen2ngen1 (txclk_ctl_in_gen2ngen1_bundle), // ww35.2008 (gnd_wire), .gen2ngen1_bundle (txclk_ctl_in_gen2ngen1_bundle), .tx_div2_sync_centrl (txclk_ctl_out_tx_div2_sync_out), .tx_div2_sync_quad_up (gnd_wire), .tx_div2_sync_quad_down (gnd_wire), .rindv_tx (vcc_wire), // ww35.2008 (cram_rindv_tx), .rtxwrclksel (cram_rtxwrclksel), .rtxrdclksel (cram_rtxrdclksel), .rdwidth_tx (cram_rdwidth_tx), .rfreerun_tx (cram_rfreerun_tx), .rauto_speed_ena (cram_rauto_speed_ena), .rfreq_sel (cram_rfreq_sel), .rtxpcsclkpwdn (gnd_wire), .rmaster_tx (vcc_wire), // ww35.2008 (cram_rmaster_tx), .rmaster_up_tx (cram_rmaster_up_tx), .rself_sw_en_tx (gnd_wire), .refclk_b (txclk_ctl_out_refclk_b), .wr_clk_pos (txclk_ctl_out_wr_clk_pos), .fifo_rd_clk (txclk_ctl_out_fifo_rd_clk), .tx_clk_out (txclk_ctl_out_tx_clk_out), .refclk_b_raw (txclk_ctl_out_refclk_b_raw), .wr_clk_pos_raw (txclk_ctl_out_wr_clk_pos_raw), .fifo_rd_clk_raw (txclk_ctl_out_fifo_rd_clk_raw), .tx_div2_sync_out (txclk_ctl_out_tx_div2_sync_out) ); /////////////////////////////////////////////////////////////////////////// // centrl_reset -------------------------------------------------------- // /////////////////////////////////////////////////////////////////////////// initial begin rxrst_sync2 = 1'b0; rxrst_sync1 = 1'b0; txrst_sync2 = 1'b0; txrst_sync1 = 1'b0; end always @(posedge qr_out_hard_reset or posedge clk_2_b) begin if (qr_out_hard_reset === 1'b1) begin rxrst_sync2 <= 1'b1; rxrst_sync1 <= 1'b1; end else begin rxrst_sync2 <= #1 rxrst_sync1; rxrst_sync1 <= chr_out_rxpcs_rst[0]; end end always @(posedge qr_out_hard_reset or posedge refclk_b) begin if (qr_out_hard_reset === 1'b1) begin txrst_sync2 <= 1'b1; txrst_sync1 <= 1'b1; end else begin txrst_sync2 <= #1 txrst_sync1; txrst_sync1 <= chr_out_txpcs_rst[0]; end end assign txrst_int = txrst_sync2; assign rxrst_int = rxrst_sync2; /////////////////////////////////////////////////////////////////////////// // auto_speed_neg ------------------------------------------------------ // /////////////////////////////////////////////////////////////////////////// assign auto_in_refclk = rxclk_ctl_out_clk_2_b; assign auto_in_rxpcs_rst_int = rxrst_int; assign auto_in_rate = rateswitch_in; // high gen2 and low gen1 assign auto_in_gen2ngen1 = rateswitchdonein_in; assign auto_in_config_sel_centrl = auto_out_config_sel; assign auto_in_config_sel_quad_up = 1'b0; assign auto_in_config_sel_quad_down = 1'b0; assign auto_in_singleorbundle = (~cram_rindv_rx & cram_rmaster_rx); stratixiv_hssi_cmu_auto_speed_neg mcmu_auto ( .refclk (auto_in_refclk), .rxpcs_rst_int (auto_in_rxpcs_rst_int), .rate (auto_in_rate), .gen2ngen1 (auto_in_gen2ngen1), .config_sel_centrl (auto_in_config_sel_centrl), .config_sel_quad_up (auto_in_config_sel_quad_up), .config_sel_quad_down (auto_in_config_sel_quad_down), .rindv_rx (cram_rindv_rx), .rmaster_rx (cram_rmaster_rx), .rmaster_up_rx (cram_rmaster_up_rx), .rauto_speed_ena (cram_rauto_speed_ena), .singleorbundle (auto_in_singleorbundle), .rphfifo_regmode_rx (cram_rphfifo_regmode_rx), .rpma_done_count (cram_rpma_done_count), .rauto_deassert_pc_rst_cnt(cram_rauto_deassert_pc_rst_cnt), .rauto_pc_en_cnt (cram_rauto_pc_en_cnt), .rwait_for_phfifo_cnt (cram_rwait_for_phfifo_cnt), .config_sel (auto_out_config_sel), .pcie_switch (auto_out_pcie_switch), .speed_change (auto_out_speed_change), .dis_pc_byte (auto_out_dis_pc_byte), .reset_pc_ptrs (auto_out_reset_pc_ptrs), .cs (auto_out_cs) ); /////////////////////////////////////////////////////////////////////////// // rx_ctl_ctrl --------------------------------------------------------- // /////////////////////////////////////////////////////////////////////////// assign rxctrl_in_soft_reset = rxrst_int; // from centrl_reset assign rxctrl_in_clk_2 = rxclk_ctl_out_clk_2_b; assign rxctrl_in_rx_rd_clk = rxclk_ctl_out_rx_rd_clk; assign rxctrl_in_rx_wr_clk = rxclk_ctl_out_rx_wr_clk; assign rxctrl_in_scan_mode = scanmode_in; assign rxctrl_in_rxfifo_urst = rxphfiforeset_in; assign rxctrl_in_pld_wr_dis = rxphfifowrdisable_in; assign rxctrl_in_pld_re = rxphfifordenable_in; assign rxctrl_in_dis_pc_byte = auto_out_dis_pc_byte; stratixiv_hssi_cmu_rx_ctrl mcmu_rx_ctrl ( .soft_reset (rxctrl_in_soft_reset ), .clk_2 (rxctrl_in_clk_2 ), .rx_rd_clk (rxctrl_in_rx_rd_clk ), .rx_wr_clk (rxctrl_in_rx_wr_clk ), .scan_mode (rxctrl_in_scan_mode ), .rrxfifo_urst_en (cram_rrxfifo_urst_en), .rxfifo_urst (rxctrl_in_rxfifo_urst ), .rrxphfifopldctl_en (cram_rrxphfifopldctl_en), .pld_wr_dis (rxctrl_in_pld_wr_dis ), .pld_re (rxctrl_in_pld_re ), .dis_pc_byte (rxctrl_in_dis_pc_byte ), .rauto_speed_ena (cram_rauto_speed_ena), .rx_we_out (rxctrl_out_rx_we_out), .wr_enable_out (rxctrl_out_wr_enable_out), .rd_enable_out (rxctrl_out_rd_enable_out) ); /////////////////////////////////////////////////////////////////////////// // rx_ctl_ctrl --------------------------------------------------------- // /////////////////////////////////////////////////////////////////////////// assign txctrl_in_soft_reset = txrst_int; assign txctrl_in_fifo_wr_clk = txclk_ctl_out_wr_clk_pos; assign txctrl_in_fifo_rd_clk = txclk_ctl_out_fifo_rd_clk; assign txctrl_in_refclk_b_in = txclk_ctl_out_refclk_b; assign txctrl_in_scan_mode = scanmode_in; assign txctrl_in_txfifo_urst = txphfiforeset_in; assign txctrl_in_pld_we = txphfifowrenable_in; assign txctrl_in_pld_rd_dis = txphfiforddisable_in; assign txctrl_in_dis_pc_byte = auto_out_dis_pc_byte; stratixiv_hssi_cmu_tx_ctrl mcmu_tx_ctrl ( .soft_reset (txctrl_in_soft_reset), .fifo_wr_clk (txctrl_in_fifo_wr_clk), .fifo_rd_clk (txctrl_in_fifo_rd_clk), .refclk_b_in (txctrl_in_refclk_b_in), .scan_mode (txctrl_in_scan_mode), .rtxfifo_urst_en (cram_rtxfifo_urst_en), .txfifo_urst (txctrl_in_txfifo_urst), .rtxphfifopldctl_en (cram_rtxphfifopldctl_en), .pld_we (txctrl_in_pld_we), .pld_rd_dis (txctrl_in_pld_rd_dis), .dis_pc_byte (txctrl_in_dis_pc_byte), .rauto_speed_ena (cram_rauto_speed_ena), .wr_enable_out (txctrl_out_wr_enable_out), .rd_enable_out (txctrl_out_rd_enable_out), .fifo_select_out (txctrl_out_fifo_select_out) ); /////////////////////////////////////////////////////////////////////////// // optimization --------------------------------------------------------// /////////////////////////////////////////////////////////////////////////// initial begin init_in_xaui_mode = (in_xaui_mode == "true" || use_deskew_fifo == "true") ? 1'b1 : 1'b0; end /////////////////////////////////////////////////////////////////////////// // instantiate DSKW SM ------------------------------------------------- // /////////////////////////////////////////////////////////////////////////// assign dskw_sm_clk = (init_in_xaui_mode === 1'b1) ? clk_1_b : 1'b0; stratixiv_hssi_dskw_sm dskw_sm_1 ( .soft_reset (rxrst_int), .clk_1 (dskw_sm_clk), .octal_mode (1'b0), .align_det_sync ({4'b1111, adet}), .rd_align ({4'b1111, rdalign}), .sync_status ({4'b1111,syncstatus}), .align_status (alignstatus_int), .enable_deskew (enabledeskew), .fifo_reset_rd (fiforesetrd), .curr_state (dskw_curr_st) ); /////////////////////////////////////////////////////////////////////////// // instantiate TX SM --------------------------------------------------- // /////////////////////////////////////////////////////////////////////////// assign tx_sm_clk = (init_in_xaui_mode === 1'b1) ? refclk_b : 1'b0; assign tx_sm_datain = (init_in_xaui_mode === 1'b1) ? txdatain : 'b0; assign tx_sm_ctrlin = (init_in_xaui_mode === 1'b1) ? txctrl : 4'h0; assign tx_sm_rdenablesyncin = (init_in_xaui_mode === 1'b1) ? rdenablesync : 1'b0; assign rtx_rx_local_fault_clr_int = 1'b0; assign rindv_tx_int = 1'b0; // tx sm just sends K when set stratixiv_hssi_tx_sm tx_sm_1 ( .tx_clk (tx_sm_clk), .soft_reset (txrst_int), .indv (rindv_tx_int), .tx_data (tx_sm_datain), .tx_ctl (tx_sm_ctrlin), .rd_enable_sync (tx_sm_rdenablesyncin), .tx_local_fault_clr (1'b0), //ww12_RTL rtx_rx_local_fault_clr_int), //shared with tx_sm .sm_data (txdataout), .sm_ctl (txctrlout), .tx_local_fault_det (tx_local_fault_det), // to rcv_sm .tx_local_fault (tx_local_fault_int), .curr_state (tx_curr_st), .rxaui_s2gx_en (cram_rxaui_s2gx_en_tx) //ww12_RTL ); /////////////////////////////////////////////////////////////////////////// // instantiate RX SM --------------------------------------------------- // /////////////////////////////////////////////////////////////////////////// assign rcv_sm_clk = (init_in_xaui_mode === 1'b1) ? clk_2_b : 1'b0; assign rcv_sm_decdatavalid = (init_in_xaui_mode === 1'b1) ? rxdatavalid : 4'b0001; assign rcv_sm_decdata = (init_in_xaui_mode === 1'b1) ? rxdatain : 'b0; assign rcv_sm_decctl = (init_in_xaui_mode === 1'b1) ? rxctrl : 4'b0000; assign rcv_sm_rxrunningdisp = (init_in_xaui_mode === 1'b1) ? rxrunningdisp : 4'b0000; assign rindv_rx_int = 1'b0; assign rxs_link_status_set_int = 1'b0; stratixiv_hssi_rcv_sm rcv_sm_1 ( .clk_2 (rcv_sm_clk), .soft_reset (rxrst_int), .indv (rindv_rx_int), .dec_data_valid (rcv_sm_decdatavalid), .dec_data (rcv_sm_decdata), .dec_ctl (rcv_sm_decctl), .running_disp (rcv_sm_rxrunningdisp), .rx_local_fault_clr (1'b0), // ww12_RTL rtx_rx_local_fault_clr_int), //shared with tx_sm .xs_link_status_set (1'b0), // ww12 RTL rxs_link_status_set_int), .tx_local_fault_det (tx_local_fault_det), // from tx_sm .rx_data_rs (rxdataout), .rx_ctl_rs (rxctrlout), .rx_local_fault (rx_local_fault_int), .xs_link_status (xs_link_status_int), .curr_state (rcv_curr_st), .rxaui_s2gx_en (cram_rxaui_s2gx_en_rx) //ww12_RTL ); /////////////////////////////////////////////////////////////////////////// // instantiate DPRIO_CONTROL_TOP --------------------------------------- // /////////////////////////////////////////////////////////////////////////// assign port_addr_bin = int2bin(portaddr-1); assign port_addr = port_addr_bin[4:0]; //port_address-1; int (1-based into 0-based) to 5'b conversion assign dev_addr_bin = int2bin(devaddr-1); assign dev_addr = dev_addr_bin[4:0]; //device_address-1; int (1-based into 0-based)to 5'b conversion assign #1 mdio_in = dprioin_in; assign mdio_rst = mdio_rst_reg; // ~(plniotri & ~entest & npor); initial begin mdio_rst_reg = 1'b1; #1000 mdio_rst_reg = 1'b0; end assign cmudprioin = 30'hxxxxxxxx; stratixiv_hssi_cmu_dprio_top control_top_0 ( .cmudividerdprioin(cmudividerdprioin), .cmuplldprioin (cmuplldprioin), .refclkdividerdprioin(refclkdividerdprioin), .rxpcsdprioin (rxpcsdprioin), .rxpmadprioin (rxpmadprioin), .txpcsdprioin (txpcsdprioin), .txpmadprioin (txpmadprioin), .cmudividerdprioout(cmudividerdprioout), .cmuplldprioout (cmuplldprioout), .refclkdividerdprioout(refclkdividerdprioout), .rxpcsdprioout (rxpcsdprioout), .rxpmadprioout (rxpmadprioout), .txpcsdprioout (txpcsdprioout), .txpmadprioout (txpmadprioout), .sync_status (syncstatus), // from top .align_status (alignstatus_int), // from dskw_sm .dprioload (dprioload_in), // from top .mdio_in (mdio_in), // delayed from top .mdc (dpclk_in), // from top .port_addr (port_addr), // from top para .dev_addr (dev_addr), // from top para .mdio_dis (dpriodisable_in), // from top .mdio_rst (mdio_rst), // not user control .mdio_out (dprioout_tim), // to top .data_enable_n (dpriooe_tim), // to top (L) .mdio_curr_st (mdio_curr_st) // to local observe ); defparam control_top_0.clkdiv0_inclk0_logical_to_physical_mapping = clkdiv0_inclk0_logical_to_physical_mapping; defparam control_top_0.clkdiv0_inclk1_logical_to_physical_mapping = clkdiv0_inclk1_logical_to_physical_mapping; defparam control_top_0.clkdiv1_inclk0_logical_to_physical_mapping = clkdiv1_inclk0_logical_to_physical_mapping; defparam control_top_0.clkdiv1_inclk1_logical_to_physical_mapping = clkdiv1_inclk1_logical_to_physical_mapping; defparam control_top_0.clkdiv2_inclk0_logical_to_physical_mapping = clkdiv2_inclk0_logical_to_physical_mapping; defparam control_top_0.clkdiv2_inclk1_logical_to_physical_mapping = clkdiv2_inclk1_logical_to_physical_mapping; defparam control_top_0.clkdiv3_inclk0_logical_to_physical_mapping = clkdiv3_inclk0_logical_to_physical_mapping; defparam control_top_0.clkdiv3_inclk1_logical_to_physical_mapping = clkdiv3_inclk1_logical_to_physical_mapping; defparam control_top_0.clkdiv4_inclk0_logical_to_physical_mapping = clkdiv4_inclk0_logical_to_physical_mapping; defparam control_top_0.clkdiv4_inclk1_logical_to_physical_mapping = clkdiv4_inclk1_logical_to_physical_mapping; defparam control_top_0.clkdiv5_inclk0_logical_to_physical_mapping = clkdiv5_inclk0_logical_to_physical_mapping; defparam control_top_0.clkdiv5_inclk1_logical_to_physical_mapping = clkdiv5_inclk1_logical_to_physical_mapping; defparam control_top_0.pll0_inclk0_logical_to_physical_mapping = pll0_inclk0_logical_to_physical_mapping; defparam control_top_0.pll0_inclk1_logical_to_physical_mapping = pll0_inclk1_logical_to_physical_mapping; defparam control_top_0.pll0_inclk2_logical_to_physical_mapping = pll0_inclk2_logical_to_physical_mapping; defparam control_top_0.pll0_inclk3_logical_to_physical_mapping = pll0_inclk3_logical_to_physical_mapping; defparam control_top_0.pll0_inclk4_logical_to_physical_mapping = pll0_inclk4_logical_to_physical_mapping; defparam control_top_0.pll0_inclk5_logical_to_physical_mapping = pll0_inclk5_logical_to_physical_mapping; defparam control_top_0.pll0_inclk6_logical_to_physical_mapping = pll0_inclk6_logical_to_physical_mapping; defparam control_top_0.pll0_inclk7_logical_to_physical_mapping = pll0_inclk7_logical_to_physical_mapping; defparam control_top_0.pll0_inclk8_logical_to_physical_mapping = pll0_inclk8_logical_to_physical_mapping; defparam control_top_0.pll0_inclk9_logical_to_physical_mapping = pll0_inclk9_logical_to_physical_mapping; defparam control_top_0.pll1_inclk0_logical_to_physical_mapping = pll1_inclk0_logical_to_physical_mapping; defparam control_top_0.pll1_inclk1_logical_to_physical_mapping = pll1_inclk1_logical_to_physical_mapping; defparam control_top_0.pll1_inclk2_logical_to_physical_mapping = pll1_inclk2_logical_to_physical_mapping; defparam control_top_0.pll1_inclk3_logical_to_physical_mapping = pll1_inclk3_logical_to_physical_mapping; defparam control_top_0.pll1_inclk4_logical_to_physical_mapping = pll1_inclk4_logical_to_physical_mapping; defparam control_top_0.pll1_inclk5_logical_to_physical_mapping = pll1_inclk5_logical_to_physical_mapping; defparam control_top_0.pll1_inclk6_logical_to_physical_mapping = pll1_inclk6_logical_to_physical_mapping; defparam control_top_0.pll1_inclk7_logical_to_physical_mapping = pll1_inclk7_logical_to_physical_mapping; defparam control_top_0.pll1_inclk8_logical_to_physical_mapping = pll1_inclk8_logical_to_physical_mapping; defparam control_top_0.pll1_inclk9_logical_to_physical_mapping = pll1_inclk9_logical_to_physical_mapping; defparam control_top_0.pll2_inclk0_logical_to_physical_mapping = pll2_inclk0_logical_to_physical_mapping; defparam control_top_0.pll2_inclk1_logical_to_physical_mapping = pll2_inclk1_logical_to_physical_mapping; defparam control_top_0.pll2_inclk2_logical_to_physical_mapping = pll2_inclk2_logical_to_physical_mapping; defparam control_top_0.pll2_inclk3_logical_to_physical_mapping = pll2_inclk3_logical_to_physical_mapping; defparam control_top_0.pll2_inclk4_logical_to_physical_mapping = pll2_inclk4_logical_to_physical_mapping; defparam control_top_0.pll2_inclk5_logical_to_physical_mapping = pll2_inclk5_logical_to_physical_mapping; defparam control_top_0.pll2_inclk6_logical_to_physical_mapping = pll2_inclk6_logical_to_physical_mapping; defparam control_top_0.pll2_inclk7_logical_to_physical_mapping = pll2_inclk7_logical_to_physical_mapping; defparam control_top_0.pll2_inclk8_logical_to_physical_mapping = pll2_inclk8_logical_to_physical_mapping; defparam control_top_0.pll2_inclk9_logical_to_physical_mapping = pll2_inclk9_logical_to_physical_mapping; defparam control_top_0.pll3_inclk0_logical_to_physical_mapping = pll3_inclk0_logical_to_physical_mapping; defparam control_top_0.pll3_inclk1_logical_to_physical_mapping = pll3_inclk1_logical_to_physical_mapping; defparam control_top_0.pll3_inclk2_logical_to_physical_mapping = pll3_inclk2_logical_to_physical_mapping; defparam control_top_0.pll3_inclk3_logical_to_physical_mapping = pll3_inclk3_logical_to_physical_mapping; defparam control_top_0.pll3_inclk4_logical_to_physical_mapping = pll3_inclk4_logical_to_physical_mapping; defparam control_top_0.pll3_inclk5_logical_to_physical_mapping = pll3_inclk5_logical_to_physical_mapping; defparam control_top_0.pll3_inclk6_logical_to_physical_mapping = pll3_inclk6_logical_to_physical_mapping; defparam control_top_0.pll3_inclk7_logical_to_physical_mapping = pll3_inclk7_logical_to_physical_mapping; defparam control_top_0.pll3_inclk8_logical_to_physical_mapping = pll3_inclk8_logical_to_physical_mapping; defparam control_top_0.pll3_inclk9_logical_to_physical_mapping = pll3_inclk9_logical_to_physical_mapping; defparam control_top_0.pll4_inclk0_logical_to_physical_mapping = pll4_inclk0_logical_to_physical_mapping; defparam control_top_0.pll4_inclk1_logical_to_physical_mapping = pll4_inclk1_logical_to_physical_mapping; defparam control_top_0.pll4_inclk2_logical_to_physical_mapping = pll4_inclk2_logical_to_physical_mapping; defparam control_top_0.pll4_inclk3_logical_to_physical_mapping = pll4_inclk3_logical_to_physical_mapping; defparam control_top_0.pll4_inclk4_logical_to_physical_mapping = pll4_inclk4_logical_to_physical_mapping; defparam control_top_0.pll4_inclk5_logical_to_physical_mapping = pll4_inclk5_logical_to_physical_mapping; defparam control_top_0.pll4_inclk6_logical_to_physical_mapping = pll4_inclk6_logical_to_physical_mapping; defparam control_top_0.pll4_inclk7_logical_to_physical_mapping = pll4_inclk7_logical_to_physical_mapping; defparam control_top_0.pll4_inclk8_logical_to_physical_mapping = pll4_inclk8_logical_to_physical_mapping; defparam control_top_0.pll4_inclk9_logical_to_physical_mapping = pll4_inclk9_logical_to_physical_mapping; defparam control_top_0.pll5_inclk0_logical_to_physical_mapping = pll5_inclk0_logical_to_physical_mapping; defparam control_top_0.pll5_inclk1_logical_to_physical_mapping = pll5_inclk1_logical_to_physical_mapping; defparam control_top_0.pll5_inclk2_logical_to_physical_mapping = pll5_inclk2_logical_to_physical_mapping; defparam control_top_0.pll5_inclk3_logical_to_physical_mapping = pll5_inclk3_logical_to_physical_mapping; defparam control_top_0.pll5_inclk4_logical_to_physical_mapping = pll5_inclk4_logical_to_physical_mapping; defparam control_top_0.pll5_inclk5_logical_to_physical_mapping = pll5_inclk5_logical_to_physical_mapping; defparam control_top_0.pll5_inclk6_logical_to_physical_mapping = pll5_inclk6_logical_to_physical_mapping; defparam control_top_0.pll5_inclk7_logical_to_physical_mapping = pll5_inclk7_logical_to_physical_mapping; defparam control_top_0.pll5_inclk8_logical_to_physical_mapping = pll5_inclk8_logical_to_physical_mapping; defparam control_top_0.pll5_inclk9_logical_to_physical_mapping = pll5_inclk9_logical_to_physical_mapping; defparam control_top_0.pll0_logical_to_physical_mapping = pll0_logical_to_physical_mapping; defparam control_top_0.pll1_logical_to_physical_mapping = pll1_logical_to_physical_mapping; defparam control_top_0.pll2_logical_to_physical_mapping = pll2_logical_to_physical_mapping; defparam control_top_0.pll3_logical_to_physical_mapping = pll3_logical_to_physical_mapping; defparam control_top_0.pll4_logical_to_physical_mapping = pll4_logical_to_physical_mapping; defparam control_top_0.pll5_logical_to_physical_mapping = pll5_logical_to_physical_mapping; defparam control_top_0.refclk_divider0_logical_to_physical_mapping = refclk_divider0_logical_to_physical_mapping; defparam control_top_0.refclk_divider1_logical_to_physical_mapping = refclk_divider1_logical_to_physical_mapping; defparam control_top_0.rx0_logical_to_physical_mapping = rx0_logical_to_physical_mapping; defparam control_top_0.rx1_logical_to_physical_mapping = rx1_logical_to_physical_mapping; defparam control_top_0.rx2_logical_to_physical_mapping = rx2_logical_to_physical_mapping; defparam control_top_0.rx3_logical_to_physical_mapping = rx3_logical_to_physical_mapping; defparam control_top_0.rx4_logical_to_physical_mapping = rx4_logical_to_physical_mapping; defparam control_top_0.rx5_logical_to_physical_mapping = rx5_logical_to_physical_mapping; defparam control_top_0.tx0_logical_to_physical_mapping = tx0_logical_to_physical_mapping; defparam control_top_0.tx1_logical_to_physical_mapping = tx1_logical_to_physical_mapping; defparam control_top_0.tx2_logical_to_physical_mapping = tx2_logical_to_physical_mapping; defparam control_top_0.tx3_logical_to_physical_mapping = tx3_logical_to_physical_mapping; defparam control_top_0.tx4_logical_to_physical_mapping = tx4_logical_to_physical_mapping; defparam control_top_0.tx5_logical_to_physical_mapping = tx5_logical_to_physical_mapping; defparam control_top_0.tx0_pma_inclk0_logical_to_physical_mapping = tx0_pma_inclk0_logical_to_physical_mapping; defparam control_top_0.tx0_pma_inclk1_logical_to_physical_mapping = tx0_pma_inclk1_logical_to_physical_mapping; defparam control_top_0.tx0_pma_inclk2_logical_to_physical_mapping = tx0_pma_inclk2_logical_to_physical_mapping; defparam control_top_0.tx0_pma_inclk3_logical_to_physical_mapping = tx0_pma_inclk3_logical_to_physical_mapping; defparam control_top_0.tx0_pma_inclk4_logical_to_physical_mapping = tx0_pma_inclk4_logical_to_physical_mapping; defparam control_top_0.tx1_pma_inclk0_logical_to_physical_mapping = tx1_pma_inclk0_logical_to_physical_mapping; defparam control_top_0.tx1_pma_inclk1_logical_to_physical_mapping = tx1_pma_inclk1_logical_to_physical_mapping; defparam control_top_0.tx1_pma_inclk2_logical_to_physical_mapping = tx1_pma_inclk2_logical_to_physical_mapping; defparam control_top_0.tx1_pma_inclk3_logical_to_physical_mapping = tx1_pma_inclk3_logical_to_physical_mapping; defparam control_top_0.tx1_pma_inclk4_logical_to_physical_mapping = tx1_pma_inclk4_logical_to_physical_mapping; defparam control_top_0.tx2_pma_inclk0_logical_to_physical_mapping = tx2_pma_inclk0_logical_to_physical_mapping; defparam control_top_0.tx2_pma_inclk1_logical_to_physical_mapping = tx2_pma_inclk1_logical_to_physical_mapping; defparam control_top_0.tx2_pma_inclk2_logical_to_physical_mapping = tx2_pma_inclk2_logical_to_physical_mapping; defparam control_top_0.tx2_pma_inclk3_logical_to_physical_mapping = tx2_pma_inclk3_logical_to_physical_mapping; defparam control_top_0.tx2_pma_inclk4_logical_to_physical_mapping = tx2_pma_inclk4_logical_to_physical_mapping; defparam control_top_0.tx3_pma_inclk0_logical_to_physical_mapping = tx3_pma_inclk0_logical_to_physical_mapping; defparam control_top_0.tx3_pma_inclk1_logical_to_physical_mapping = tx3_pma_inclk1_logical_to_physical_mapping; defparam control_top_0.tx3_pma_inclk2_logical_to_physical_mapping = tx3_pma_inclk2_logical_to_physical_mapping; defparam control_top_0.tx3_pma_inclk3_logical_to_physical_mapping = tx3_pma_inclk3_logical_to_physical_mapping; defparam control_top_0.tx3_pma_inclk4_logical_to_physical_mapping = tx3_pma_inclk4_logical_to_physical_mapping; defparam control_top_0.tx4_pma_inclk0_logical_to_physical_mapping = tx4_pma_inclk0_logical_to_physical_mapping; defparam control_top_0.tx4_pma_inclk1_logical_to_physical_mapping = tx4_pma_inclk1_logical_to_physical_mapping; defparam control_top_0.tx4_pma_inclk2_logical_to_physical_mapping = tx4_pma_inclk2_logical_to_physical_mapping; defparam control_top_0.tx4_pma_inclk3_logical_to_physical_mapping = tx4_pma_inclk3_logical_to_physical_mapping; defparam control_top_0.tx4_pma_inclk4_logical_to_physical_mapping = tx4_pma_inclk4_logical_to_physical_mapping; defparam control_top_0.tx5_pma_inclk0_logical_to_physical_mapping = tx5_pma_inclk0_logical_to_physical_mapping; defparam control_top_0.tx5_pma_inclk1_logical_to_physical_mapping = tx5_pma_inclk1_logical_to_physical_mapping; defparam control_top_0.tx5_pma_inclk2_logical_to_physical_mapping = tx5_pma_inclk2_logical_to_physical_mapping; defparam control_top_0.tx5_pma_inclk3_logical_to_physical_mapping = tx5_pma_inclk3_logical_to_physical_mapping; defparam control_top_0.tx5_pma_inclk4_logical_to_physical_mapping = tx5_pma_inclk4_logical_to_physical_mapping; defparam control_top_0.sim_dump_dprio_internal_reg_at_time = sim_dump_dprio_internal_reg_at_time; defparam control_top_0.sim_dump_filename = sim_dump_filename; /////////////////////////////////////////////////////////////////////////// // establish outputs --------------------------------------------------- // /////////////////////////////////////////////////////////////////////////// assign alignstatus = alignstatus_int; // from dskw_sm assign dpriodisableout = dpriodisable_in; // from top //assign digitaltestout = 10'hxxx; // 10 Test ports // for pcie_rateswitch assign pcie_tmp = ( (rx0_channel_bonding == "x4") || (rx0_channel_bonding == "x8")) ? auto_out_pcie_switch : adet[0]; assign digitaltestout = {{7{1'bx}},pcie_tmp,2'bxx}; assign dprioout = dprioout_tim; assign dpriooe = dpriooe_tim; // reset and powerdown - everything turns into Active High --------------- assign pllresetout = {(~qr_out_cmu1_cru_rstb) | (~qr_out_cmu1_rxpma_rstb), (~qr_out_cmu0_cru_rstb) | (~qr_out_cmu0_rxpma_rstb)}; assign quadresetout = qr_out_hard_reset; assign rxadceresetout = ~chr_out_adce_rstb; assign rxanalogresetout = ~chr_out_rxpma_rstb; assign rxcruresetout = (~chr_out_cru_rstb) | (~chr_out_rxpma_rstb); // or is implemented in PMA assign rxdigitalresetout = chr_out_rxpcs_rst; assign txanalogresetout = ~chr_out_txpma_rstb; assign txdigitalresetout = chr_out_txpcs_rst; assign clkdivpowerdn = {~qr_out_cmu1_cgb_pdb, ~qr_out_cmu0_cgb_pdb}; assign pllpowerdn = {~qr_out_cmu1_cru_pdb,~qr_out_cmu0_cru_pdb }; assign rxadcepowerdown = ~chr_out_adce_pdb; assign rxcrupowerdown = ~chr_out_cru_pdb; assign rxibpowerdown = ~chr_out_rx_pdb; assign txdetectrxpowerdown = ~chr_out_rx_det_pdb; assign txdividerpowerdown = ~chr_out_cgb_pdb; assign txobpowerdown = ~chr_out_tx_pdb; // ww47_out assign autospdx4configsel = auto_out_config_sel; assign autospdx4rateswitchout = auto_out_pcie_switch; assign autospdx4spdchg = auto_out_speed_change; assign phfifiox4ptrsreset = auto_out_reset_pc_ptrs; assign rxphfifox4byteselout = rxctrl_out_rx_we_out; assign rxphfifox4wrclkout = rxclk_ctl_out_rx_div2_sync_out; assign rxphfifox4rdenableout = rxctrl_out_rd_enable_out; assign rxphfifox4wrenableout = rxctrl_out_wr_enable_out; assign scanout = 23'hzzzzzz; assign txphfifox4byteselout = txctrl_out_fifo_select_out; assign txphfifox4rdclkout = txclk_ctl_out_tx_div2_sync_out; assign txphfifox4rdenableout = txctrl_out_rd_enable_out; assign txphfifox4wrenableout = txctrl_out_wr_enable_out; endmodule // *********************************************************** // This WYSIWYG atom header was automatically generated by the // Atmgen build tool. To change it, alter data stored in the // corresponding WYS file(s) in the tools/atmgen subdirectory. // *********************************************************** // *** Section 1 -- Header *** // ----------------------------------------------------------- // // Module Name : stratixiv_hssi_calibration_block // // Description : DEV_FAMILY_STRATIXIV stratixiv_hssi_calibration_block Verilog simulation model // // ----------------------------------------------------------- `timescale 1 ps/1 ps // *** End of Section 1 *** // *** Section 3 -- Module declaration *** module stratixiv_hssi_calibration_block( clk, enabletestbus, powerdn, testctrl, calibrationstatus, nonusertocmu ); // *** End of Section 3 *** // *** Section 4 -- Port size declarations *** // Note: Variable port sizes dictated by parameters are not currently defined in // the WYS file data. Busses are marked with the VARIABLE notation as a reminder. /* `define CALIBRATIONSTATUS_PORTSIZE_CONST_stratixiv_hssi_calibration_block 5 // * VARIABLE `define CLK_PORTSIZE_CONST_stratixiv_hssi_calibration_block 1 `define ENABLETESTBUS_PORTSIZE_CONST_stratixiv_hssi_calibration_block 1 `define NONUSERTOCMU_PORTSIZE_CONST_stratixiv_hssi_calibration_block 1 `define POWERDN_PORTSIZE_CONST_stratixiv_hssi_calibration_block 1 `define TESTCTRL_PORTSIZE_CONST_stratixiv_hssi_calibration_block 1 */ // *** End of Section 4 *** // *** Section 5 -- Port declarations *** input clk; input enabletestbus; input powerdn; input testctrl; output [4 : 0] calibrationstatus; output nonusertocmu; // *** End of Section 5 *** // *** Section 6 -- Parameter declarations and default values *** parameter lpm_type = "stratixiv_hssi_calibration_block"; parameter cont_cal_mode = "false"; parameter enable_rx_cal_tw = "false"; parameter enable_tx_cal_tw = "false"; parameter rtest = "false"; parameter rx_cal_wt_value = 0 ; parameter send_rx_cal_status = "false"; parameter tx_cal_wt_value = 1 ; // SIMULATION_ONLY_PARAMETERS_BEGIN parameter migrated_from_prev_family = "false"; // SIMULATION_ONLY_PARAMETERS_END // *** End of Section 6 *** // *** Section 7 -- Port declarations with defaults, if any *** // This section will always be empty for WYSIWYG atoms // tri1 devclrn; //sample // *** End of Section 7 *** endmodule // *********************************************************** // This WYSIWYG atom header was automatically generated by the // Atmgen build tool. To change it, alter data stored in the // corresponding WYS file(s) in the tools/atmgen subdirectory. // *********************************************************** // *** Section 1 -- Header *** // ----------------------------------------------------------- // // Module Name : stratixiv_hssi_refclk_divider // // Description : DEV_FAMILY_STRATIXIV stratixiv_hssi_refclk_divider Verilog simulation model // // ----------------------------------------------------------- `timescale 1 ps/1 ps // *** End of Section 1 *** // *** Section 3 -- Module declaration *** module stratixiv_hssi_refclk_divider( dpriodisable, dprioin, inclk, clkout, dprioout ); // *** End of Section 3 *** // *** Section 4 -- Port size declarations *** // Note: Variable port sizes dictated by parameters are not currently defined in // the WYS file data. Busses are marked with the VARIABLE notation as a reminder. `define CLKOUT_PORTSIZE_CONST_stratixiv_hssi_refclk_divider 1 `define DPRIODISABLE_PORTSIZE_CONST_stratixiv_hssi_refclk_divider 1 `define DPRIOIN_PORTSIZE_CONST_stratixiv_hssi_refclk_divider 1 `define DPRIOOUT_PORTSIZE_CONST_stratixiv_hssi_refclk_divider 1 `define INCLK_PORTSIZE_CONST_stratixiv_hssi_refclk_divider 1 // *** End of Section 4 *** // *** Section 5 -- Port declarations *** input dpriodisable; input dprioin; input inclk; output clkout; output dprioout; // *** End of Section 5 *** // *** Section 6 -- Parameter declarations and default values *** parameter lpm_type = "stratixiv_hssi_refclk_divider"; parameter divider_number = 0 ; parameter enable_divider = "false"; parameter refclk_coupling_termination = "normal_100_ohm_termination"; // SIMULATION_ONLY_PARAMETERS_BEGIN parameter protocol_hint = "basic"; // SIMULATION_ONLY_PARAMETERS_END // *** End of Section 6 *** // *** Section 7 -- Port declarations with defaults, if any *** // This section will always be empty for WYSIWYG atoms // tri1 devclrn; //sample // *** End of Section 7 *** wire inclk_ipd; wire dprioin_ipd; wire dpriodisable_ipd; assign inclk_ipd = (inclk === 1'b1) ? 1'b1 : 1'b0; assign dprioin_ipd = (dprioin === 1'b1) ? 1'b1 : 1'b0; assign dpriodisable_ipd = (dpriodisable === 1'b1) ? 1'b1 : 1'b0; specify (inclk => clkout) = (0,0); endspecify wire divide_by_2_clk; wire divide_by_2_out; assign divide_by_2_clk = (enable_divider == "false") ? 1'b0 : inclk_ipd; stratixiv_hssi_aux_clock_div divide_by_2 ( .clk(divide_by_2_clk), .reset(1'b0), .enable_d (1'b0), // enable dprio .d (8'h01), // dprio .clkout(divide_by_2_out) ); defparam divide_by_2.clk_divide_by = 2; defparam divide_by_2.extra_latency = 0; assign clkout = (enable_divider == "false") ? inclk_ipd : divide_by_2_out; assign dprioout = (dpriodisable_ipd == 1'b1) ? 1'b0 : dprioin_ipd; endmodule //IP Functional Simulation Model //VERSION_BEGIN 12.0 cbx_mgl 2012:05:31:20:09:47:SJ cbx_simgen 2012:05:31:20:08:35:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 // Copyright (C) 1991-2012 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // You may only use these simulation model output files for simulation // purposes and expressly not for synthesis or any other purposes (in which // event Altera disclaims all warranties of any kind). //synopsys translate_off //synthesis_resources = io_buf_tri 264 lut 176 mux21 86 tri_bus 62 `timescale 1 ps / 1 ps module stratixiv_hssi_pma_c_adce ( adapt_capture, adapt_done, atb0, atb1, atb_0, atb_1, atben, atbsel, e_clk, eqa_ctrl, eqa_set, eqb_ctrl, eqb_set, eqc_ctrl, eqc_set, eqctrlout, eqd_ctrl, eqd_set, eqin_n, eqin_p, eqv_ctrl, eqv_set, fine_d2aout, fixed_clk, hf_adapt_done, hfclk_macro, hfmac_cnt0_nclr, hfmac_cnt2_nclr, ib50u_c, ib50u_t, ibrgen1, ibrgen2, lf_adapt_done, lfclk_macro, lfmac_cnt0_nclr, lfmac_cnt2_nclr, lock_lf_ovd, lst, outeqn, outeqp, r_clk, radce_adapt, radce_digital, radce_hflck, radce_lflck, radce_pdb, radce_rstb, radce_vod_int, radce_vod_lsb, rbit_dc, rclkdiv, rd2a_res, rdc_freq, rdfe_en, rf_hpf, rf_lpf, rgenctrlout, rhf_os, rhyst_hf, rhyst_lf, rlf_os, rrect_adj, rrgen_bw, rrgen_set, rrgen_vod, rseq_sel, standby, tmxselan, tmxselbn, tmxselcn, tmxseldn, tmxselvn, updnn_hf, updnn_lf, vbn, vccehxqyx, vccerxqyx, vctl_quiet, vssexqyx) /* synthesis synthesis_clearbox=1 */; input adapt_capture; output adapt_done; inout atb0; inout atb1; inout atb_0; inout atb_1; input atben; input [23:0] atbsel; output e_clk; output eqa_ctrl; input [2:0] eqa_set; output eqb_ctrl; input [2:0] eqb_set; output eqc_ctrl; input [2:0] eqc_set; output [5:0] eqctrlout; output eqd_ctrl; input [2:0] eqd_set; input eqin_n; input eqin_p; output eqv_ctrl; input [2:0] eqv_set; output fine_d2aout; input fixed_clk; output hf_adapt_done; output hfclk_macro; output hfmac_cnt0_nclr; output hfmac_cnt2_nclr; inout ib50u_c; inout ib50u_t; output ibrgen1; output ibrgen2; output lf_adapt_done; output lfclk_macro; output lfmac_cnt0_nclr; output lfmac_cnt2_nclr; input lock_lf_ovd; input [4:0] lst; inout outeqn; inout outeqp; output r_clk; input radce_adapt; input [9:0] radce_digital; input [14:0] radce_hflck; input [14:0] radce_lflck; input radce_pdb; input radce_rstb; input [2:0] radce_vod_int; input radce_vod_lsb; input rbit_dc; input [3:0] rclkdiv; input [1:0] rd2a_res; input [1:0] rdc_freq; input rdfe_en; input [1:0] rf_hpf; input [1:0] rf_lpf; output [5:0] rgenctrlout; input [3:0] rhf_os; input [2:0] rhyst_hf; input [2:0] rhyst_lf; input [3:0] rlf_os; input [1:0] rrect_adj; input [1:0] rrgen_bw; input [2:0] rrgen_set; input [2:0] rrgen_vod; input [1:0] rseq_sel; input standby; output tmxselan; output tmxselbn; output tmxselcn; output tmxseldn; output tmxselvn; output updnn_hf; output updnn_lf; input vbn; inout vccehxqyx; inout vccerxqyx; inout vctl_quiet; inout vssexqyx; reg n0i0il69; reg n0i0il70; reg n0i0iO67; reg n0i0iO68; reg n0i0ll65; reg n0i0ll66; reg n0i0lO63; reg n0i0lO64; reg n0i10O79; reg n0i10O80; reg n0i1ii77; reg n0i1ii78; reg n0i1il75; reg n0i1il76; reg n0i1iO73; reg n0i1iO74; reg n0i1li71; reg n0i1li72; reg n0ii0l59; reg n0ii0l60; reg n0ii1i61; reg n0ii1i62; reg n0iiiO57; reg n0iiiO58; reg n0iiOi55; reg n0iiOi56; reg n0il0i51; reg n0il0i52; reg n0il0l49; reg n0il0l50; reg n0il1O53; reg n0il1O54; reg n0iliO47; reg n0iliO48; reg n0illi45; reg n0illi46; reg n0illO43; reg n0illO44; reg n0ilOi41; reg n0ilOi42; reg n0iO0O37; reg n0iO0O38; reg n0iO1l39; reg n0iO1l40; reg n0iOii35; reg n0iOii36; reg n0iOiO33; reg n0iOiO34; reg n0iOll31; reg n0iOll32; reg n0iOlO29; reg n0iOlO30; reg n0l00i1; reg n0l00i2; reg n0l01i7; reg n0l01i8; reg n0l01l5; reg n0l01l6; reg n0l01O3; reg n0l01O4; reg n0l10i23; reg n0l10i24; reg n0l10l21; reg n0l10l22; reg n0l10O19; reg n0l10O20; reg n0l11l27; reg n0l11l28; reg n0l11O25; reg n0l11O26; reg n0l1ii17; reg n0l1ii18; reg n0l1iO15; reg n0l1iO16; reg n0l1ll13; reg n0l1ll14; reg n0l1Ol11; reg n0l1Ol12; reg n0l1OO10; reg n0l1OO9; reg n011O; reg n01il; reg n1O0O; reg n1O1l; reg n1Oli; reg n1OOl; reg n01ii_clk_prev; wire wire_n01ii_CLRN; wire wire_n01ii_PRN; reg n010i; reg n01li; reg n1O1O; reg n1Oii; reg n1Oll; reg n1OOO; reg n01iO_clk_prev; wire wire_n01iO_CLRN; wire wire_n01iO_PRN; reg n0lili; reg n0liOO; reg n0ll0l; reg n0llll; reg n0lill; reg n0ll0O; reg n0ll1i; reg n0llOi; reg n0O00O; reg n0O10l; reg n0O1li; reg n0O1OO; reg n0O01i; reg n0O0il; reg n0O10O; reg n0O1ll; reg n0Oill; wire wire_n0Oili_CLK; reg n0OiOi; wire wire_n0OilO_CLK; reg n0Ol0i; reg n0OliO; reg n0OlOl; reg n0OO0l; reg n0Ol0l; reg n0Olli; reg n0OlOO; reg n0OOii; reg n100i; reg n10li; reg n1i1l; wire wire_n1i1i_CLRN; reg n100l; reg n10ll; reg n1i0i; reg n1l0l; wire wire_n1l0i_CLRN; reg n1l1O; reg n1l1l_clk_prev; wire wire_n1l1l_CLRN; wire wire_n1l1l_PRN; reg n1llO; reg n1lOl; reg ni00iO; reg ni00il_clk_prev; wire wire_ni00il_CLRN; reg ni00ll; reg ni00li_clk_prev; wire wire_ni00li_PRN; reg ni010l; reg ni010i_clk_prev; wire wire_ni010i_CLRN; reg ni01ii; reg ni010O_clk_prev; wire wire_ni010O_PRN; reg ni0iOi; reg ni0ilO_clk_prev; wire wire_ni0ilO_CLRN; reg ni0iOO; reg ni0iOl_clk_prev; wire wire_ni0iOl_PRN; reg ni0O1l; reg ni0O1i_clk_prev; wire wire_ni0O1i_CLRN; reg ni0O0i; reg ni0O1O_clk_prev; wire wire_ni0O1O_PRN; reg ni100i; reg ni10iO; reg ni10OO; reg ni11Ol; reg ni100l; reg ni10li; reg ni11OO; reg ni1i1l; reg ni1l0l; wire wire_ni1l0i_CLK; reg ni1lii; wire wire_ni1l0O_CLK; reg ni1O1i; reg ni1lOO_clk_prev; wire wire_ni1lOO_CLRN; reg ni1O1O; reg ni1O1l_clk_prev; wire wire_ni1O1l_PRN; reg nii0li; reg nii0iO_clk_prev; wire wire_nii0iO_CLRN; reg nii0lO; reg nii0ll_clk_prev; wire wire_nii0ll_PRN; reg nii10O; reg nii10l_clk_prev; wire wire_nii10l_CLRN; reg nii1il; reg nii1ii_clk_prev; wire wire_nii1ii_PRN; reg niiiOl; reg niiiOi_clk_prev; wire wire_niiiOi_CLRN; reg niil1i; reg niiiOO_clk_prev; wire wire_niiiOO_PRN; reg niiO0l; reg niiO0i_clk_prev; wire wire_niiO0i_PRN; reg niiO1O; reg niiO1l_clk_prev; wire wire_niiO1l_CLRN; reg nl10OO; reg nl10Ol_clk_prev; wire wire_nl10Ol_CLRN; wire wire_nl10Ol_PRN; reg nl111i; reg nl11ii; reg nl11Ol; reg nl11Oi_clk_prev; wire wire_nl11Oi_CLRN; wire wire_nl11Oi_PRN; reg nl101i; reg nl111l; reg nl11il; reg nl11OO_clk_prev; wire wire_nl11OO_CLRN; reg nl1i1l; wire wire_nl1i1i_CLRN; reg nll01O; reg nll01l_clk_prev; wire wire_nll01l_PRN; reg nll01i; reg nll1OO_clk_prev; wire wire_nll1OO_CLRN; reg nlli0l; reg nlli0i_clk_prev; wire wire_nlli0i_CLRN; wire wire_nlli0i_PRN; reg nlliii; reg nlli0O_clk_prev; wire wire_nlli0O_PRN; reg nllliO; reg nlllil_clk_prev; wire wire_nlllil_CLRN; wire wire_nlllil_PRN; reg nlllll; reg nlllli_clk_prev; wire wire_nlllli_PRN; reg nllOOi; reg nllOlO_clk_prev; wire wire_nllOlO_CLRN; reg nllOOO; reg nllOOl_clk_prev; wire wire_nllOOl_CLRN; wire wire_nllOOl_PRN; reg nlO01l; reg nlO01i_clk_prev; wire wire_nlO01i_CLRN; reg nlO00i; reg nlO01O_clk_prev; wire wire_nlO01O_PRN; reg nlOi0O; reg nlOi0l_clk_prev; wire wire_nlOi0l_CLRN; reg nlOiil; reg nlOiii_clk_prev; wire wire_nlOiii_CLRN; wire wire_nlOiii_PRN; wire wire_n00il_dataout; wire wire_n00iO_dataout; wire wire_n00li_dataout; wire wire_n00ll_dataout; wire wire_n00lO_dataout; wire wire_n00Oi_dataout; wire wire_n00Ol_dataout; wire wire_n00OO_dataout; wire wire_n010l_dataout; wire wire_n011i_dataout; wire wire_n0ili_dataout; wire wire_n0ill_dataout; wire wire_n0ilO_dataout; wire wire_n0iOi_dataout; wire wire_n0iOl_dataout; wire wire_n0iOO_dataout; wire wire_n0l1i_dataout; wire wire_n0l1l_dataout; wire wire_n0liil_dataout; wire wire_n0liOi_dataout; wire wire_n0ll1O_dataout; wire wire_n0llil_dataout; wire wire_n0O01O_dataout; wire wire_n0O11O_dataout; wire wire_n0O1il_dataout; wire wire_n0O1Oi_dataout; wire wire_n0Ol1l_dataout; wire wire_n0Olii_dataout; wire wire_n0OllO_dataout; wire wire_n0OO1l_dataout; wire wire_n100O_dataout; wire wire_n101l_dataout; wire wire_n10il_dataout; wire wire_n10lO_dataout; wire wire_n10Ol_dataout; wire wire_n11OO_dataout; wire wire_n1l0O_dataout; wire wire_n1lil_dataout; wire wire_n1lOO_dataout; wire wire_n1O0i_dataout; wire wire_n1Oil_dataout; wire wire_n1OlO_dataout; wire wire_ni00lO_dataout; wire wire_ni00Ol_dataout; wire wire_ni01i_dataout; wire wire_ni01il_dataout; wire wire_ni01li_dataout; wire wire_ni01lO_dataout; wire wire_ni01Oi_dataout; wire wire_ni01Ol_dataout; wire wire_ni01OO_dataout; wire wire_ni0i0i_dataout; wire wire_ni0i1i_dataout; wire wire_ni0i1l_dataout; wire wire_ni0i1O_dataout; wire wire_ni0l0l_dataout; wire wire_ni0l0O_dataout; wire wire_ni0l1i_dataout; wire wire_ni0l1O_dataout; wire wire_ni0lii_dataout; wire wire_ni0lil_dataout; wire wire_ni0O0l_dataout; wire wire_ni0Oii_dataout; wire wire_ni0OiO_dataout; wire wire_ni0Oli_dataout; wire wire_ni0Oll_dataout; wire wire_ni0OlO_dataout; wire wire_ni101l_dataout; wire wire_ni10ii_dataout; wire wire_ni10lO_dataout; wire wire_ni11lO_dataout; wire wire_ni1ii_dataout; wire wire_ni1il_dataout; wire wire_ni1iO_dataout; wire wire_ni1li_dataout; wire wire_ni1ll_dataout; wire wire_ni1lO_dataout; wire wire_ni1O0i_dataout; wire wire_ni1O0O_dataout; wire wire_ni1Oi_dataout; wire wire_ni1Oil_dataout; wire wire_ni1OiO_dataout; wire wire_ni1Ol_dataout; wire wire_ni1Oli_dataout; wire wire_ni1Oll_dataout; wire wire_ni1OO_dataout; wire wire_nii01i_dataout; wire wire_nii0Oi_dataout; wire wire_nii0OO_dataout; wire wire_nii1iO_dataout; wire wire_nii1ll_dataout; wire wire_nii1Oi_dataout; wire wire_nii1Ol_dataout; wire wire_nii1OO_dataout; wire wire_niii0i_dataout; wire wire_niii0l_dataout; wire wire_niii1l_dataout; wire wire_niii1O_dataout; wire wire_niil0i_dataout; wire wire_niil0O_dataout; wire wire_niil1l_dataout; wire wire_niilii_dataout; wire wire_niilil_dataout; wire wire_niiliO_dataout; wire wire_niiO0O_dataout; wire wire_niiOil_dataout; wire wire_niiOli_dataout; wire wire_niiOll_dataout; wire wire_niiOlO_dataout; wire wire_niiOOi_dataout; wire wire_nil01l_dataout; wire wire_nil10l_dataout; wire wire_nil1ii_dataout; wire wire_nil1iO_dataout; wire wire_nil1ll_dataout; wire wire_nil1Oi_dataout; wire wire_nil1OO_dataout; wire wire_niO0ll_dataout; wire wire_niO0lO_dataout; wire wire_niO0Oi_dataout; wire wire_niO0Ol_dataout; wire wire_niO0OO_dataout; wire wire_niOi0i_dataout; wire wire_niOi0l_dataout; wire wire_niOi0O_dataout; wire wire_niOi1i_dataout; wire wire_niOi1l_dataout; wire wire_niOi1O_dataout; wire wire_niOiiO_dataout; wire wire_niOili_dataout; wire wire_niOill_dataout; wire wire_niOilO_dataout; wire wire_niOiOi_dataout; wire wire_niOiOl_dataout; wire wire_niOiOO_dataout; wire wire_niOl0i_dataout; wire wire_niOl1i_dataout; wire wire_niOl1l_dataout; wire wire_niOl1O_dataout; wire wire_niOlii_dataout; wire wire_niOlil_dataout; wire wire_niOliO_dataout; wire wire_niOlli_dataout; wire wire_niOlll_dataout; wire wire_niOllO_dataout; wire wire_niOlOi_dataout; wire wire_niOlOl_dataout; wire wire_niOlOO_dataout; wire wire_niOO0l_dataout; wire wire_niOO1i_dataout; wire wire_niOO1l_dataout; wire wire_niOOlO_dataout; wire wire_niOOOl_dataout; wire wire_nl000i_dataout; wire wire_nl000l_dataout; wire wire_nl000O_dataout; wire wire_nl001i_dataout; wire wire_nl001l_dataout; wire wire_nl001O_dataout; wire wire_nl00ii_dataout; wire wire_nl00il_dataout; wire wire_nl00li_dataout; wire wire_nl00ll_dataout; wire wire_nl00lO_dataout; wire wire_nl00Oi_dataout; wire wire_nl00Ol_dataout; wire wire_nl0lll_dataout; wire wire_nl0llO_dataout; wire wire_nl0lOi_dataout; wire wire_nl0lOl_dataout; wire wire_nl0lOO_dataout; wire wire_nl0O0l_dataout; wire wire_nl0O0O_dataout; wire wire_nl0O1i_dataout; wire wire_nl0O1l_dataout; wire wire_nl0O1O_dataout; wire wire_nl0Oii_dataout; wire wire_nl0Oil_dataout; wire wire_nl0OiO_dataout; wire wire_nl110l_dataout; wire wire_nl111O_dataout; wire wire_nl11iO_dataout; wire wire_nl11ll_dataout; wire wire_nl1i0l_dataout; wire wire_nl1i1O_dataout; wire wire_nl1l0i_dataout; wire wire_nl1l0l_dataout; wire wire_nl1l0O_dataout; wire wire_nl1l1O_dataout; wire wire_nl1lii_dataout; wire wire_nl1lil_dataout; wire wire_nl1liO_dataout; wire wire_nl1lli_dataout; wire wire_nl1lOl_dataout; wire wire_nl1lOO_dataout; wire wire_nl1O1i_dataout; wire wire_nl1O1l_dataout; wire wire_nl1O1O_dataout; wire wire_nli00i_dataout; wire wire_nli00l_dataout; wire wire_nli00O_dataout; wire wire_nli01l_dataout; wire wire_nli01O_dataout; wire wire_nli0ii_dataout; wire wire_nli0il_dataout; wire wire_nli0iO_dataout; wire wire_nli0ll_dataout; wire wire_nli0lO_dataout; wire wire_nli0Oi_dataout; wire wire_nli0Ol_dataout; wire wire_nli0OO_dataout; wire wire_nliOil_dataout; wire wire_nliOiO_dataout; wire wire_nliOli_dataout; wire wire_nliOll_dataout; wire wire_nliOlO_dataout; wire wire_nliOOi_dataout; wire wire_nliOOl_dataout; wire wire_nliOOO_dataout; wire wire_nll00i_dataout; wire wire_nll00O_dataout; wire wire_nll0il_dataout; wire wire_nll0iO_dataout; wire wire_nll0li_dataout; wire wire_nll0ll_dataout; wire wire_nll10i_dataout; wire wire_nll11l_dataout; wire wire_nll11O_dataout; wire wire_nlliil_dataout; wire wire_nllili_dataout; wire wire_nllilO_dataout; wire wire_nlliOi_dataout; wire wire_nlliOl_dataout; wire wire_nlliOO_dataout; wire wire_nllllO_dataout; wire wire_nlllOl_dataout; wire wire_nllO0i_dataout; wire wire_nllO1i_dataout; wire wire_nllO1l_dataout; wire wire_nllO1O_dataout; wire wire_nlO00l_dataout; wire wire_nlO0ii_dataout; wire wire_nlO0iO_dataout; wire wire_nlO0li_dataout; wire wire_nlO0ll_dataout; wire wire_nlO0lO_dataout; wire wire_nlO10l_dataout; wire wire_nlO10O_dataout; wire wire_nlO11i_dataout; wire wire_nlO11O_dataout; wire wire_nlO1ii_dataout; wire wire_nlO1il_dataout; wire wire_nlOiiO_dataout; wire wire_nlOill_dataout; wire wire_nlOiOi_dataout; wire wire_nlOiOl_dataout; wire wire_nlOiOO_dataout; wire wire_nlOl1i_dataout; wire wire_nlOlil_dataout; wire wire_nlOlli_dataout; wire wire_nlOllO_dataout; wire wire_nlOlOl_dataout; wire wire_nlOO1i_dataout; wire wire_nlOO1O_dataout; wire wire_n010O_dataout; wire wire_n011l_dataout; wire wire_n0liiO_dataout; wire wire_n0liOl_dataout; wire wire_n0ll0i_dataout; wire wire_n0lliO_dataout; wire wire_n0O00i_dataout; wire wire_n0O10i_dataout; wire wire_n0O1iO_dataout; wire wire_n0O1Ol_dataout; wire wire_n0Ol1O_dataout; wire wire_n0Olil_dataout; wire wire_n0OlOi_dataout; wire wire_n0OO1O_dataout; wire wire_n101i_dataout; wire wire_n101O_dataout; wire wire_n10ii_dataout; wire wire_n10iO_dataout; wire wire_n10Oi_dataout; wire wire_n10OO_dataout; wire wire_n1lii_dataout; wire wire_n1liO_dataout; wire wire_n1O0l_dataout; wire wire_n1O1i_dataout; wire wire_n1OiO_dataout; wire wire_n1OOi_dataout; wire wire_ni00Oi_dataout; wire wire_ni00OO_dataout; wire wire_ni01iO_dataout; wire wire_ni01ll_dataout; wire wire_ni0l0i_dataout; wire wire_ni0l1l_dataout; wire wire_ni0O0O_dataout; wire wire_ni0Oil_dataout; wire wire_ni101O_dataout; wire wire_ni10il_dataout; wire wire_ni10Oi_dataout; wire wire_ni11Oi_dataout; wire wire_ni1O0l_dataout; wire wire_ni1Oii_dataout; wire wire_nii0Ol_dataout; wire wire_nii1li_dataout; wire wire_nii1lO_dataout; wire wire_niii1i_dataout; wire wire_niil0l_dataout; wire wire_niil1O_dataout; wire wire_niiOii_dataout; wire wire_niiOiO_dataout; wire wire_nil01i_dataout; wire wire_nil01O_dataout; wire wire_nil10O_dataout; wire wire_nil1il_dataout; wire wire_nil1li_dataout; wire wire_nil1lO_dataout; wire wire_nil1Ol_dataout; wire wire_niOO0O_dataout; wire wire_niOOOi_dataout; wire wire_niOOOO_dataout; wire wire_nl00OO_dataout; wire wire_nl0Oli_dataout; wire wire_nl110i_dataout; wire wire_nl110O_dataout; wire wire_nl11li_dataout; wire wire_nl11lO_dataout; wire wire_nl1i0i_dataout; wire wire_nl1i0O_dataout; wire wire_nl1O0i_dataout; wire wire_nlii1i_dataout; wire wire_nll00l_dataout; wire wire_nll0ii_dataout; wire wire_nlliiO_dataout; wire wire_nllill_dataout; wire wire_nlllOi_dataout; wire wire_nlllOO_dataout; wire wire_nlO00O_dataout; wire wire_nlO0il_dataout; wire wire_nlO10i_dataout; wire wire_nlO11l_dataout; wire wire_nlOili_dataout; wire wire_nlOilO_dataout; wire wire_nlOliO_dataout; wire wire_nlOlll_dataout; wire wire_nlOlOi_dataout; wire wire_nlOlOO_dataout; wire wire_nlOO0i_dataout; wire wire_nlOO1l_dataout; wire [0:0] wire_n0i1i_dataout; wire [0:0] wire_n0l1O_dataout; wire [0:0] wire_ni001i_dataout; wire [0:0] wire_ni001l_dataout; wire [0:0] wire_ni01l_dataout; wire [0:0] wire_ni01O_dataout; wire [0:0] wire_ni0i0l_dataout; wire [0:0] wire_ni0i0O_dataout; wire [0:0] wire_ni0liO_dataout; wire [0:0] wire_ni0ll_dataout; wire [0:0] wire_ni0lli_dataout; wire [0:0] wire_ni0lO_dataout; wire [0:0] wire_ni0Oi_dataout; wire [0:0] wire_ni0Ol_dataout; wire [0:0] wire_ni0OO_dataout; wire [0:0] wire_ni0OOi_dataout; wire [0:0] wire_ni0OOl_dataout; wire [0:0] wire_ni1OlO_dataout; wire [0:0] wire_ni1OOi_dataout; wire [0:0] wire_nii01l_dataout; wire [0:0] wire_nii01O_dataout; wire [0:0] wire_nii0i_dataout; wire [0:0] wire_nii0l_dataout; wire [0:0] wire_nii0O_dataout; wire [0:0] wire_nii1i_dataout; wire [0:0] wire_nii1l_dataout; wire [0:0] wire_nii1O_dataout; wire [0:0] wire_niii0O_dataout; wire [0:0] wire_niiiii_dataout; wire [0:0] wire_niilli_dataout; wire [0:0] wire_niilll_dataout; wire [0:0] wire_niiOOl_dataout; wire [0:0] wire_niiOOO_dataout; wire [0:0] wire_niOiii_dataout; wire [0:0] wire_niOiil_dataout; wire [0:0] wire_niOl0l_dataout; wire [0:0] wire_niOl0O_dataout; wire [0:0] wire_niOO0i_dataout; wire [0:0] wire_niOO1O_dataout; wire [0:0] wire_nl00iO_dataout; wire [0:0] wire_nl0i1i_dataout; wire [0:0] wire_nl0O0i_dataout; wire [0:0] wire_nl0Oll_dataout; wire [0:0] wire_nl1lll_dataout; wire [0:0] wire_nl1llO_dataout; wire [0:0] wire_nl1lOi_dataout; wire [0:0] wire_nl1O0l_dataout; wire [0:0] wire_nli0li_dataout; wire [0:0] wire_nlii1l_dataout; wire [0:0] wire_nll0lO_dataout; wire [0:0] wire_nll0Oi_dataout; wire [0:0] wire_nll11i_dataout; wire [0:0] wire_nlll1i_dataout; wire [0:0] wire_nlll1l_dataout; wire [0:0] wire_nllO0l_dataout; wire [0:0] wire_nllO0O_dataout; wire [0:0] wire_nlO0Oi_dataout; wire [0:0] wire_nlO0Ol_dataout; wire [0:0] wire_nlO1iO_dataout; wire [0:0] wire_nlO1li_dataout; wire [0:0] wire_nlOl1l_dataout; wire [0:0] wire_nlOl1O_dataout; wire n000il; wire n000iO; wire n000li; wire n000ll; wire n000lO; wire n000Oi; wire n000Ol; wire n000OO; wire n00i0i; wire n00i0l; wire n00i0O; wire n00i1i; wire n00i1l; wire n00i1O; wire n00iii; wire n00iil; wire n00iiO; wire n00ili; wire n00ill; wire n00ilO; wire n00iOi; wire n00iOl; wire n00iOO; wire n00l0i; wire n00l0l; wire n00l0O; wire n00l1i; wire n00l1l; wire n00l1O; wire n00lii; wire n00lil; wire n00liO; wire n00lli; wire n00lll; wire n00llO; wire n00lOi; wire n00lOl; wire n00lOO; wire n00O0i; wire n00O0l; wire n00O0O; wire n00O1i; wire n00O1l; wire n00O1O; wire n00Oii; wire n00Oil; wire n00OiO; wire n00Oli; wire n00Oll; wire n00OlO; wire n00OOi; wire n00OOl; wire n00OOO; wire n0i00i; wire n0i00l; wire n0i00O; wire n0i01i; wire n0i01l; wire n0i01O; wire n0i0ii; wire n0i0li; wire n0i0Oi; wire n0i0Ol; wire n0i0OO; wire n0i10i; wire n0i10l; wire n0i11i; wire n0i11l; wire n0i11O; wire n0i1ll; wire n0i1lO; wire n0i1Oi; wire n0i1Ol; wire n0i1OO; wire n0ii0i; wire n0ii0O; wire n0ii1l; wire n0ii1O; wire n0iiii; wire n0iiil; wire n0iili; wire n0iill; wire n0iilO; wire n0iiOl; wire n0iiOO; wire n0il0O; wire n0il1i; wire n0il1l; wire n0ilii; wire n0ilil; wire n0illl; wire n0ilOl; wire n0ilOO; wire n0iO0i; wire n0iO0l; wire n0iO1i; wire n0iO1O; wire n0iOil; wire n0iOli; wire n0iOOl; wire n0iOOO; wire n0l00l; wire n0l00O; wire n0l0ii; wire n0l0il; wire n0l0iO; wire n0l0li; wire n0l0ll; wire n0l0lO; wire n0l0Oi; wire n0l0Ol; wire n0l0OO; wire n0l11i; wire n0l1il; wire n0l1Oi; wire n0li0i; wire n0li1i; wire n0li1l; wire n0li1O; wire n0liii; initial n0i0il69 = 0; always @ ( posedge wire_nl1i0l_dataout) n0i0il69 <= n0i0il70; event n0i0il69_event; initial #1 ->n0i0il69_event; always @(n0i0il69_event) n0i0il69 <= {1{1'b1}}; initial n0i0il70 = 0; always @ ( posedge wire_nl1i0l_dataout) n0i0il70 <= n0i0il69; initial n0i0iO67 = 0; always @ ( posedge wire_nl1i0l_dataout) n0i0iO67 <= n0i0iO68; event n0i0iO67_event; initial #1 ->n0i0iO67_event; always @(n0i0iO67_event) n0i0iO67 <= {1{1'b1}}; initial n0i0iO68 = 0; always @ ( posedge wire_nl1i0l_dataout) n0i0iO68 <= n0i0iO67; initial n0i0ll65 = 0; always @ ( posedge wire_nl1i0l_dataout) n0i0ll65 <= n0i0ll66; event n0i0ll65_event; initial #1 ->n0i0ll65_event; always @(n0i0ll65_event) n0i0ll65 <= {1{1'b1}}; initial n0i0ll66 = 0; always @ ( posedge wire_nl1i0l_dataout) n0i0ll66 <= n0i0ll65; initial n0i0lO63 = 0; always @ ( posedge wire_nl1i0l_dataout) n0i0lO63 <= n0i0lO64; event n0i0lO63_event; initial #1 ->n0i0lO63_event; always @(n0i0lO63_event) n0i0lO63 <= {1{1'b1}}; initial n0i0lO64 = 0; always @ ( posedge wire_nl1i0l_dataout) n0i0lO64 <= n0i0lO63; initial n0i10O79 = 0; always @ ( posedge wire_nl1i0l_dataout) n0i10O79 <= n0i10O80; event n0i10O79_event; initial #1 ->n0i10O79_event; always @(n0i10O79_event) n0i10O79 <= {1{1'b1}}; initial n0i10O80 = 0; always @ ( posedge wire_nl1i0l_dataout) n0i10O80 <= n0i10O79; initial n0i1ii77 = 0; always @ ( posedge wire_nl1i0l_dataout) n0i1ii77 <= n0i1ii78; event n0i1ii77_event; initial #1 ->n0i1ii77_event; always @(n0i1ii77_event) n0i1ii77 <= {1{1'b1}}; initial n0i1ii78 = 0; always @ ( posedge wire_nl1i0l_dataout) n0i1ii78 <= n0i1ii77; initial n0i1il75 = 0; always @ ( posedge wire_nl1i0l_dataout) n0i1il75 <= n0i1il76; event n0i1il75_event; initial #1 ->n0i1il75_event; always @(n0i1il75_event) n0i1il75 <= {1{1'b1}}; initial n0i1il76 = 0; always @ ( posedge wire_nl1i0l_dataout) n0i1il76 <= n0i1il75; initial n0i1iO73 = 0; always @ ( posedge wire_nl1i0l_dataout) n0i1iO73 <= n0i1iO74; event n0i1iO73_event; initial #1 ->n0i1iO73_event; always @(n0i1iO73_event) n0i1iO73 <= {1{1'b1}}; initial n0i1iO74 = 0; always @ ( posedge wire_nl1i0l_dataout) n0i1iO74 <= n0i1iO73; initial n0i1li71 = 0; always @ ( posedge wire_nl1i0l_dataout) n0i1li71 <= n0i1li72; event n0i1li71_event; initial #1 ->n0i1li71_event; always @(n0i1li71_event) n0i1li71 <= {1{1'b1}}; initial n0i1li72 = 0; always @ ( posedge wire_nl1i0l_dataout) n0i1li72 <= n0i1li71; initial n0ii0l59 = 0; always @ ( posedge wire_nl1i0l_dataout) n0ii0l59 <= n0ii0l60; event n0ii0l59_event; initial #1 ->n0ii0l59_event; always @(n0ii0l59_event) n0ii0l59 <= {1{1'b1}}; initial n0ii0l60 = 0; always @ ( posedge wire_nl1i0l_dataout) n0ii0l60 <= n0ii0l59; initial n0ii1i61 = 0; always @ ( posedge wire_nl1i0l_dataout) n0ii1i61 <= n0ii1i62; event n0ii1i61_event; initial #1 ->n0ii1i61_event; always @(n0ii1i61_event) n0ii1i61 <= {1{1'b1}}; initial n0ii1i62 = 0; always @ ( posedge wire_nl1i0l_dataout) n0ii1i62 <= n0ii1i61; initial n0iiiO57 = 0; always @ ( posedge wire_nl1i0l_dataout) n0iiiO57 <= n0iiiO58; event n0iiiO57_event; initial #1 ->n0iiiO57_event; always @(n0iiiO57_event) n0iiiO57 <= {1{1'b1}}; initial n0iiiO58 = 0; always @ ( posedge wire_nl1i0l_dataout) n0iiiO58 <= n0iiiO57; initial n0iiOi55 = 0; always @ ( posedge wire_nl1i0l_dataout) n0iiOi55 <= n0iiOi56; event n0iiOi55_event; initial #1 ->n0iiOi55_event; always @(n0iiOi55_event) n0iiOi55 <= {1{1'b1}}; initial n0iiOi56 = 0; always @ ( posedge wire_nl1i0l_dataout) n0iiOi56 <= n0iiOi55; initial n0il0i51 = 0; always @ ( posedge wire_nl1i0l_dataout) n0il0i51 <= n0il0i52; event n0il0i51_event; initial #1 ->n0il0i51_event; always @(n0il0i51_event) n0il0i51 <= {1{1'b1}}; initial n0il0i52 = 0; always @ ( posedge wire_nl1i0l_dataout) n0il0i52 <= n0il0i51; initial n0il0l49 = 0; always @ ( posedge wire_nl1i0l_dataout) n0il0l49 <= n0il0l50; event n0il0l49_event; initial #1 ->n0il0l49_event; always @(n0il0l49_event) n0il0l49 <= {1{1'b1}}; initial n0il0l50 = 0; always @ ( posedge wire_nl1i0l_dataout) n0il0l50 <= n0il0l49; initial n0il1O53 = 0; always @ ( posedge wire_nl1i0l_dataout) n0il1O53 <= n0il1O54; event n0il1O53_event; initial #1 ->n0il1O53_event; always @(n0il1O53_event) n0il1O53 <= {1{1'b1}}; initial n0il1O54 = 0; always @ ( posedge wire_nl1i0l_dataout) n0il1O54 <= n0il1O53; initial n0iliO47 = 0; always @ ( posedge wire_nl1i0l_dataout) n0iliO47 <= n0iliO48; event n0iliO47_event; initial #1 ->n0iliO47_event; always @(n0iliO47_event) n0iliO47 <= {1{1'b1}}; initial n0iliO48 = 0; always @ ( posedge wire_nl1i0l_dataout) n0iliO48 <= n0iliO47; initial n0illi45 = 0; always @ ( posedge wire_nl1i0l_dataout) n0illi45 <= n0illi46; event n0illi45_event; initial #1 ->n0illi45_event; always @(n0illi45_event) n0illi45 <= {1{1'b1}}; initial n0illi46 = 0; always @ ( posedge wire_nl1i0l_dataout) n0illi46 <= n0illi45; initial n0illO43 = 0; always @ ( posedge wire_nl1i0l_dataout) n0illO43 <= n0illO44; event n0illO43_event; initial #1 ->n0illO43_event; always @(n0illO43_event) n0illO43 <= {1{1'b1}}; initial n0illO44 = 0; always @ ( posedge wire_nl1i0l_dataout) n0illO44 <= n0illO43; initial n0ilOi41 = 0; always @ ( posedge wire_nl1i0l_dataout) n0ilOi41 <= n0ilOi42; event n0ilOi41_event; initial #1 ->n0ilOi41_event; always @(n0ilOi41_event) n0ilOi41 <= {1{1'b1}}; initial n0ilOi42 = 0; always @ ( posedge wire_nl1i0l_dataout) n0ilOi42 <= n0ilOi41; initial n0iO0O37 = 0; always @ ( posedge wire_nl1i0l_dataout) n0iO0O37 <= n0iO0O38; event n0iO0O37_event; initial #1 ->n0iO0O37_event; always @(n0iO0O37_event) n0iO0O37 <= {1{1'b1}}; initial n0iO0O38 = 0; always @ ( posedge wire_nl1i0l_dataout) n0iO0O38 <= n0iO0O37; initial n0iO1l39 = 0; always @ ( posedge wire_nl1i0l_dataout) n0iO1l39 <= n0iO1l40; event n0iO1l39_event; initial #1 ->n0iO1l39_event; always @(n0iO1l39_event) n0iO1l39 <= {1{1'b1}}; initial n0iO1l40 = 0; always @ ( posedge wire_nl1i0l_dataout) n0iO1l40 <= n0iO1l39; initial n0iOii35 = 0; always @ ( posedge wire_nl1i0l_dataout) n0iOii35 <= n0iOii36; event n0iOii35_event; initial #1 ->n0iOii35_event; always @(n0iOii35_event) n0iOii35 <= {1{1'b1}}; initial n0iOii36 = 0; always @ ( posedge wire_nl1i0l_dataout) n0iOii36 <= n0iOii35; initial n0iOiO33 = 0; always @ ( posedge wire_nl1i0l_dataout) n0iOiO33 <= n0iOiO34; event n0iOiO33_event; initial #1 ->n0iOiO33_event; always @(n0iOiO33_event) n0iOiO33 <= {1{1'b1}}; initial n0iOiO34 = 0; always @ ( posedge wire_nl1i0l_dataout) n0iOiO34 <= n0iOiO33; initial n0iOll31 = 0; always @ ( posedge wire_nl1i0l_dataout) n0iOll31 <= n0iOll32; event n0iOll31_event; initial #1 ->n0iOll31_event; always @(n0iOll31_event) n0iOll31 <= {1{1'b1}}; initial n0iOll32 = 0; always @ ( posedge wire_nl1i0l_dataout) n0iOll32 <= n0iOll31; initial n0iOlO29 = 0; always @ ( posedge wire_nl1i0l_dataout) n0iOlO29 <= n0iOlO30; event n0iOlO29_event; initial #1 ->n0iOlO29_event; always @(n0iOlO29_event) n0iOlO29 <= {1{1'b1}}; initial n0iOlO30 = 0; always @ ( posedge wire_nl1i0l_dataout) n0iOlO30 <= n0iOlO29; initial n0l00i1 = 0; always @ ( posedge wire_nl1i0l_dataout) n0l00i1 <= n0l00i2; event n0l00i1_event; initial #1 ->n0l00i1_event; always @(n0l00i1_event) n0l00i1 <= {1{1'b1}}; initial n0l00i2 = 0; always @ ( posedge wire_nl1i0l_dataout) n0l00i2 <= n0l00i1; initial n0l01i7 = 0; always @ ( posedge wire_nl1i0l_dataout) n0l01i7 <= n0l01i8; event n0l01i7_event; initial #1 ->n0l01i7_event; always @(n0l01i7_event) n0l01i7 <= {1{1'b1}}; initial n0l01i8 = 0; always @ ( posedge wire_nl1i0l_dataout) n0l01i8 <= n0l01i7; initial n0l01l5 = 0; always @ ( posedge wire_nl1i0l_dataout) n0l01l5 <= n0l01l6; event n0l01l5_event; initial #1 ->n0l01l5_event; always @(n0l01l5_event) n0l01l5 <= {1{1'b1}}; initial n0l01l6 = 0; always @ ( posedge wire_nl1i0l_dataout) n0l01l6 <= n0l01l5; initial n0l01O3 = 0; always @ ( posedge wire_nl1i0l_dataout) n0l01O3 <= n0l01O4; event n0l01O3_event; initial #1 ->n0l01O3_event; always @(n0l01O3_event) n0l01O3 <= {1{1'b1}}; initial n0l01O4 = 0; always @ ( posedge wire_nl1i0l_dataout) n0l01O4 <= n0l01O3; initial n0l10i23 = 0; always @ ( posedge wire_nl1i0l_dataout) n0l10i23 <= n0l10i24; event n0l10i23_event; initial #1 ->n0l10i23_event; always @(n0l10i23_event) n0l10i23 <= {1{1'b1}}; initial n0l10i24 = 0; always @ ( posedge wire_nl1i0l_dataout) n0l10i24 <= n0l10i23; initial n0l10l21 = 0; always @ ( posedge wire_nl1i0l_dataout) n0l10l21 <= n0l10l22; event n0l10l21_event; initial #1 ->n0l10l21_event; always @(n0l10l21_event) n0l10l21 <= {1{1'b1}}; initial n0l10l22 = 0; always @ ( posedge wire_nl1i0l_dataout) n0l10l22 <= n0l10l21; initial n0l10O19 = 0; always @ ( posedge wire_nl1i0l_dataout) n0l10O19 <= n0l10O20; event n0l10O19_event; initial #1 ->n0l10O19_event; always @(n0l10O19_event) n0l10O19 <= {1{1'b1}}; initial n0l10O20 = 0; always @ ( posedge wire_nl1i0l_dataout) n0l10O20 <= n0l10O19; initial n0l11l27 = 0; always @ ( posedge wire_nl1i0l_dataout) n0l11l27 <= n0l11l28; event n0l11l27_event; initial #1 ->n0l11l27_event; always @(n0l11l27_event) n0l11l27 <= {1{1'b1}}; initial n0l11l28 = 0; always @ ( posedge wire_nl1i0l_dataout) n0l11l28 <= n0l11l27; initial n0l11O25 = 0; always @ ( posedge wire_nl1i0l_dataout) n0l11O25 <= n0l11O26; event n0l11O25_event; initial #1 ->n0l11O25_event; always @(n0l11O25_event) n0l11O25 <= {1{1'b1}}; initial n0l11O26 = 0; always @ ( posedge wire_nl1i0l_dataout) n0l11O26 <= n0l11O25; initial n0l1ii17 = 0; always @ ( posedge wire_nl1i0l_dataout) n0l1ii17 <= n0l1ii18; event n0l1ii17_event; initial #1 ->n0l1ii17_event; always @(n0l1ii17_event) n0l1ii17 <= {1{1'b1}}; initial n0l1ii18 = 0; always @ ( posedge wire_nl1i0l_dataout) n0l1ii18 <= n0l1ii17; initial n0l1iO15 = 0; always @ ( posedge wire_nl1i0l_dataout) n0l1iO15 <= n0l1iO16; event n0l1iO15_event; initial #1 ->n0l1iO15_event; always @(n0l1iO15_event) n0l1iO15 <= {1{1'b1}}; initial n0l1iO16 = 0; always @ ( posedge wire_nl1i0l_dataout) n0l1iO16 <= n0l1iO15; initial n0l1ll13 = 0; always @ ( posedge wire_nl1i0l_dataout) n0l1ll13 <= n0l1ll14; event n0l1ll13_event; initial #1 ->n0l1ll13_event; always @(n0l1ll13_event) n0l1ll13 <= {1{1'b1}}; initial n0l1ll14 = 0; always @ ( posedge wire_nl1i0l_dataout) n0l1ll14 <= n0l1ll13; initial n0l1Ol11 = 0; always @ ( posedge wire_nl1i0l_dataout) n0l1Ol11 <= n0l1Ol12; event n0l1Ol11_event; initial #1 ->n0l1Ol11_event; always @(n0l1Ol11_event) n0l1Ol11 <= {1{1'b1}}; initial n0l1Ol12 = 0; always @ ( posedge wire_nl1i0l_dataout) n0l1Ol12 <= n0l1Ol11; initial n0l1OO10 = 0; always @ ( posedge wire_nl1i0l_dataout) n0l1OO10 <= n0l1OO9; initial n0l1OO9 = 0; always @ ( posedge wire_nl1i0l_dataout) n0l1OO9 <= n0l1OO10; event n0l1OO9_event; initial #1 ->n0l1OO9_event; always @(n0l1OO9_event) n0l1OO9 <= {1{1'b1}}; initial begin n011O = 0; n01il = 0; n1O0O = 0; n1O1l = 0; n1Oli = 0; n1OOl = 0; end always @ (n0l1il or wire_n01ii_PRN or wire_n01ii_CLRN) begin if (wire_n01ii_PRN == 1'b0) begin n011O <= 1; n01il <= 1; n1O0O <= 1; n1O1l <= 1; n1Oli <= 1; n1OOl <= 1; end else if (wire_n01ii_CLRN == 1'b0) begin n011O <= 0; n01il <= 0; n1O0O <= 0; n1O1l <= 0; n1Oli <= 0; n1OOl <= 0; end else if (n0l1il != n01ii_clk_prev && n0l1il == 1'b1) begin n011O <= wire_n011i_dataout; n01il <= wire_n010l_dataout; n1O0O <= wire_n1O0i_dataout; n1O1l <= wire_n1lOO_dataout; n1Oli <= wire_n1Oil_dataout; n1OOl <= wire_n1OlO_dataout; end n01ii_clk_prev <= n0l1il; end assign wire_n01ii_CLRN = ((n0illi46 ^ n0illi45) & radce_rstb), wire_n01ii_PRN = (n0iliO48 ^ n0iliO47); initial begin n010i = 0; n01li = 0; n1O1O = 0; n1Oii = 0; n1Oll = 0; n1OOO = 0; end always @ (n0l1il or wire_n01iO_PRN or wire_n01iO_CLRN) begin if (wire_n01iO_PRN == 1'b0) begin n010i <= 1; n01li <= 1; n1O1O <= 1; n1Oii <= 1; n1Oll <= 1; n1OOO <= 1; end else if (wire_n01iO_CLRN == 1'b0) begin n010i <= 0; n01li <= 0; n1O1O <= 0; n1Oii <= 0; n1Oll <= 0; n1OOO <= 0; end else if (n0l1il != n01iO_clk_prev && n0l1il == 1'b1) begin n010i <= (~ wire_n011i_dataout); n01li <= (~ wire_n010l_dataout); n1O1O <= (~ wire_n1lOO_dataout); n1Oii <= (~ wire_n1O0i_dataout); n1Oll <= (~ wire_n1Oil_dataout); n1OOO <= (~ wire_n1OlO_dataout); end n01iO_clk_prev <= n0l1il; end assign wire_n01iO_CLRN = (n0ilOi42 ^ n0ilOi41), wire_n01iO_PRN = ((n0illO44 ^ n0illO43) & radce_rstb); event n010i_event; event n01li_event; event n1O1O_event; event n1Oii_event; event n1Oll_event; event n1OOO_event; initial #1 ->n010i_event; initial #1 ->n01li_event; initial #1 ->n1O1O_event; initial #1 ->n1Oii_event; initial #1 ->n1Oll_event; initial #1 ->n1OOO_event; always @(n010i_event) n010i <= 1; always @(n01li_event) n01li <= 1; always @(n1O1O_event) n1O1O <= 1; always @(n1Oii_event) n1Oii <= 1; always @(n1Oll_event) n1Oll <= 1; always @(n1OOO_event) n1OOO <= 1; initial begin n0lili = 0; n0liOO = 0; n0ll0l = 0; n0llll = 0; end always @ ( posedge n000li or negedge n0li1l) begin if (n0li1l == 1'b0) begin n0lili <= 0; n0liOO <= 0; n0ll0l <= 0; n0llll <= 0; end else begin n0lili <= wire_n0liil_dataout; n0liOO <= wire_n0liOi_dataout; n0ll0l <= wire_n0ll1O_dataout; n0llll <= wire_n0llil_dataout; end end initial begin n0lill = 0; n0ll0O = 0; n0ll1i = 0; n0llOi = 0; end always @ ( posedge n000li or negedge n0li1l) begin if (n0li1l == 1'b0) begin n0lill <= 1; n0ll0O <= 1; n0ll1i <= 1; n0llOi <= 1; end else begin n0lill <= (~ wire_n0liil_dataout); n0ll0O <= (~ wire_n0ll1O_dataout); n0ll1i <= (~ wire_n0liOi_dataout); n0llOi <= (~ wire_n0llil_dataout); end end event n0lill_event; event n0ll0O_event; event n0ll1i_event; event n0llOi_event; initial #1 ->n0lill_event; initial #1 ->n0ll0O_event; initial #1 ->n0ll1i_event; initial #1 ->n0llOi_event; always @(n0lill_event) n0lill <= 1; always @(n0ll0O_event) n0ll0O <= 1; always @(n0ll1i_event) n0ll1i <= 1; always @(n0llOi_event) n0llOi <= 1; initial begin n0O00O = 0; n0O10l = 0; n0O1li = 0; n0O1OO = 0; end always @ ( posedge n000Oi or negedge n0li1i) begin if (n0li1i == 1'b0) begin n0O00O <= 0; n0O10l <= 0; n0O1li <= 0; n0O1OO <= 0; end else begin n0O00O <= wire_n0O01O_dataout; n0O10l <= wire_n0O11O_dataout; n0O1li <= wire_n0O1il_dataout; n0O1OO <= wire_n0O1Oi_dataout; end end initial begin n0O01i = 0; n0O0il = 0; n0O10O = 0; n0O1ll = 0; end always @ ( posedge n000Oi or negedge n0li1i) begin if (n0li1i == 1'b0) begin n0O01i <= 1; n0O0il <= 1; n0O10O <= 1; n0O1ll <= 1; end else begin n0O01i <= (~ wire_n0O1Oi_dataout); n0O0il <= (~ wire_n0O01O_dataout); n0O10O <= (~ wire_n0O11O_dataout); n0O1ll <= (~ wire_n0O1il_dataout); end end event n0O01i_event; event n0O0il_event; event n0O10O_event; event n0O1ll_event; initial #1 ->n0O01i_event; initial #1 ->n0O0il_event; initial #1 ->n0O10O_event; initial #1 ->n0O1ll_event; always @(n0O01i_event) n0O01i <= 1; always @(n0O0il_event) n0O0il <= 1; always @(n0O10O_event) n0O10O <= 1; always @(n0O1ll_event) n0O1ll <= 1; initial begin n0Oill = 0; end always @ ( posedge wire_n0Oili_CLK or negedge radce_rstb) begin if (radce_rstb == 1'b0) begin n0Oill <= 0; end else begin n0Oill <= n000Ol; end end assign wire_n0Oili_CLK = (~ wire_n0i1i_dataout[0]); initial begin n0OiOi = 0; end always @ ( posedge wire_n0OilO_CLK or negedge radce_rstb) begin if (radce_rstb == 1'b0) begin n0OiOi <= 0; end else begin n0OiOi <= (~ n000OO); end end assign wire_n0OilO_CLK = wire_n0i1i_dataout[0]; initial begin n0Ol0i = 0; n0OliO = 0; n0OlOl = 0; n0OO0l = 0; end always @ ( posedge n00i1O or negedge n0l0Ol) begin if (n0l0Ol == 1'b0) begin n0Ol0i <= 0; n0OliO <= 0; n0OlOl <= 0; n0OO0l <= 0; end else begin n0Ol0i <= wire_n0Ol1l_dataout; n0OliO <= wire_n0Olii_dataout; n0OlOl <= wire_n0OllO_dataout; n0OO0l <= wire_n0OO1l_dataout; end end initial begin n0Ol0l = 0; n0Olli = 0; n0OlOO = 0; n0OOii = 0; end always @ ( posedge n00i1O or negedge n0l0Ol) begin if (n0l0Ol == 1'b0) begin n0Ol0l <= 1; n0Olli <= 1; n0OlOO <= 1; n0OOii <= 1; end else begin n0Ol0l <= (~ wire_n0Ol1l_dataout); n0Olli <= (~ wire_n0Olii_dataout); n0OlOO <= (~ wire_n0OllO_dataout); n0OOii <= (~ wire_n0OO1l_dataout); end end event n0Ol0l_event; event n0Olli_event; event n0OlOO_event; event n0OOii_event; initial #1 ->n0Ol0l_event; initial #1 ->n0Olli_event; initial #1 ->n0OlOO_event; initial #1 ->n0OOii_event; always @(n0Ol0l_event) n0Ol0l <= 1; always @(n0Olli_event) n0Olli <= 1; always @(n0OlOO_event) n0OlOO <= 1; always @(n0OOii_event) n0OOii <= 1; initial begin n100i = 0; n10li = 0; n1i1l = 0; end always @ ( posedge n0l0lO or negedge wire_n1i1i_CLRN) begin if (wire_n1i1i_CLRN == 1'b0) begin n100i <= 0; n10li <= 0; n1i1l <= 0; end else begin n100i <= wire_n101l_dataout; n10li <= wire_n10il_dataout; n1i1l <= wire_n10Ol_dataout; end end assign wire_n1i1i_CLRN = ((n0il1O54 ^ n0il1O53) & n0ilil); initial begin n100l = 0; n10ll = 0; n1i0i = 0; end always @ ( posedge n0l0lO or negedge n0ilil) begin if (n0ilil == 1'b0) begin n100l <= 1; n10ll <= 1; n1i0i <= 1; end else begin n100l <= (~ wire_n101l_dataout); n10ll <= (~ wire_n10il_dataout); n1i0i <= (~ wire_n10Ol_dataout); end end event n100l_event; event n10ll_event; event n1i0i_event; initial #1 ->n100l_event; initial #1 ->n10ll_event; initial #1 ->n1i0i_event; always @(n100l_event) n100l <= 1; always @(n10ll_event) n10ll <= 1; always @(n1i0i_event) n1i0i <= 1; initial begin n1l0l = 0; end always @ ( negedge n0l0lO or negedge wire_n1l0i_CLRN) begin if (wire_n1l0i_CLRN == 1'b0) begin n1l0l <= 0; end else begin n1l0l <= n0il0O; end end assign wire_n1l0i_CLRN = ((n0il0l50 ^ n0il0l49) & radce_rstb); initial begin n1l1O = 0; end always @ (wire_n1l0O_dataout or wire_n1l1l_PRN or wire_n1l1l_CLRN) begin if (wire_n1l1l_PRN == 1'b0) begin n1l1O <= 1; end else if (wire_n1l1l_CLRN == 1'b0) begin n1l1O <= 0; end else if (wire_n1l0O_dataout != n1l1l_clk_prev && wire_n1l0O_dataout == 1'b1) begin n1l1O <= (~ n0l00l); end n1l1l_clk_prev <= wire_n1l0O_dataout; end assign wire_n1l1l_CLRN = wire_nl1lOi_dataout[0], wire_n1l1l_PRN = ((n0il0i52 ^ n0il0i51) & (~ ((~ radce_rstb) & wire_nl1lOi_dataout[0]))); initial begin n1llO = 0; n1lOl = 0; end always @ ( negedge fixed_clk or negedge radce_rstb) begin if (radce_rstb == 1'b0) begin n1llO <= 0; n1lOl <= 0; end else begin n1llO <= (~ ((adapt_capture | standby) | (n0liii & (~ ((~ radce_adapt) | radce_pdb))))); n1lOl <= n1llO; end end initial begin ni00iO = 0; end always @ (wire_nl1i0l_dataout or n00iOi or wire_ni00il_CLRN) begin if (n00iOi == 1'b1) begin ni00iO <= 1; end else if (wire_ni00il_CLRN == 1'b0) begin ni00iO <= 0; end else if (wire_nl1i0l_dataout != ni00il_clk_prev && wire_nl1i0l_dataout == 1'b1) begin ni00iO <= wire_ni00Ol_dataout; end ni00il_clk_prev <= wire_nl1i0l_dataout; end assign wire_ni00il_CLRN = wire_ni0i0O_dataout[0]; initial begin ni00ll = 0; end always @ (wire_nl1i0l_dataout or wire_ni00li_PRN or n00iOi) begin if (wire_ni00li_PRN == 1'b0) begin ni00ll <= 1; end else if (n00iOi == 1'b1) begin ni00ll <= 0; end else if (wire_nl1i0l_dataout != ni00li_clk_prev && wire_nl1i0l_dataout == 1'b1) begin ni00ll <= (~ wire_ni00Ol_dataout); end ni00li_clk_prev <= wire_nl1i0l_dataout; end assign wire_ni00li_PRN = wire_ni0i0O_dataout[0]; initial begin ni010l = 0; end always @ (wire_nl1i0l_dataout or n00ili or wire_ni010i_CLRN) begin if (n00ili == 1'b1) begin ni010l <= 1; end else if (wire_ni010i_CLRN == 1'b0) begin ni010l <= 0; end else if (wire_nl1i0l_dataout != ni010i_clk_prev && wire_nl1i0l_dataout == 1'b1) begin ni010l <= wire_ni01li_dataout; end ni010i_clk_prev <= wire_nl1i0l_dataout; end assign wire_ni010i_CLRN = wire_ni001l_dataout[0]; initial begin ni01ii = 0; end always @ (wire_nl1i0l_dataout or wire_ni010O_PRN or n00ili) begin if (wire_ni010O_PRN == 1'b0) begin ni01ii <= 1; end else if (n00ili == 1'b1) begin ni01ii <= 0; end else if (wire_nl1i0l_dataout != ni010O_clk_prev && wire_nl1i0l_dataout == 1'b1) begin ni01ii <= (~ wire_ni01li_dataout); end ni010O_clk_prev <= wire_nl1i0l_dataout; end assign wire_ni010O_PRN = wire_ni001l_dataout[0]; initial begin ni0iOi = 0; end always @ (wire_nl1i0l_dataout or n00l1i or wire_ni0ilO_CLRN) begin if (n00l1i == 1'b1) begin ni0iOi <= 1; end else if (wire_ni0ilO_CLRN == 1'b0) begin ni0iOi <= 0; end else if (wire_nl1i0l_dataout != ni0ilO_clk_prev && wire_nl1i0l_dataout == 1'b1) begin ni0iOi <= wire_ni0l1O_dataout; end ni0ilO_clk_prev <= wire_nl1i0l_dataout; end assign wire_ni0ilO_CLRN = wire_ni0lli_dataout[0]; initial begin ni0iOO = 0; end always @ (wire_nl1i0l_dataout or wire_ni0iOl_PRN or n00l1i) begin if (wire_ni0iOl_PRN == 1'b0) begin ni0iOO <= 1; end else if (n00l1i == 1'b1) begin ni0iOO <= 0; end else if (wire_nl1i0l_dataout != ni0iOl_clk_prev && wire_nl1i0l_dataout == 1'b1) begin ni0iOO <= (~ wire_ni0l1O_dataout); end ni0iOl_clk_prev <= wire_nl1i0l_dataout; end assign wire_ni0iOl_PRN = wire_ni0lli_dataout[0]; initial begin ni0O1l = 0; end always @ (wire_nl1i0l_dataout or n00l0i or wire_ni0O1i_CLRN) begin if (n00l0i == 1'b1) begin ni0O1l <= 1; end else if (wire_ni0O1i_CLRN == 1'b0) begin ni0O1l <= 0; end else if (wire_nl1i0l_dataout != ni0O1i_clk_prev && wire_nl1i0l_dataout == 1'b1) begin ni0O1l <= wire_ni0Oii_dataout; end ni0O1i_clk_prev <= wire_nl1i0l_dataout; end assign wire_ni0O1i_CLRN = wire_ni0OOl_dataout[0]; initial begin ni0O0i = 0; end always @ (wire_nl1i0l_dataout or wire_ni0O1O_PRN or n00l0i) begin if (wire_ni0O1O_PRN == 1'b0) begin ni0O0i <= 1; end else if (n00l0i == 1'b1) begin ni0O0i <= 0; end else if (wire_nl1i0l_dataout != ni0O1O_clk_prev && wire_nl1i0l_dataout == 1'b1) begin ni0O0i <= (~ wire_ni0Oii_dataout); end ni0O1O_clk_prev <= wire_nl1i0l_dataout; end assign wire_ni0O1O_PRN = wire_ni0OOl_dataout[0]; initial begin ni100i = 0; ni10iO = 0; ni10OO = 0; ni11Ol = 0; end always @ ( posedge n00i0O or negedge n0l0Oi) begin if (n0l0Oi == 1'b0) begin ni100i <= 0; ni10iO <= 0; ni10OO <= 0; ni11Ol <= 0; end else begin ni100i <= wire_ni101l_dataout; ni10iO <= wire_ni10ii_dataout; ni10OO <= wire_ni10lO_dataout; ni11Ol <= wire_ni11lO_dataout; end end initial begin ni100l = 0; ni10li = 0; ni11OO = 0; ni1i1l = 0; end always @ ( posedge n00i0O or negedge n0l0Oi) begin if (n0l0Oi == 1'b0) begin ni100l <= 1; ni10li <= 1; ni11OO <= 1; ni1i1l <= 1; end else begin ni100l <= (~ wire_ni101l_dataout); ni10li <= (~ wire_ni10ii_dataout); ni11OO <= (~ wire_ni11lO_dataout); ni1i1l <= (~ wire_ni10lO_dataout); end end event ni100l_event; event ni10li_event; event ni11OO_event; event ni1i1l_event; initial #1 ->ni100l_event; initial #1 ->ni10li_event; initial #1 ->ni11OO_event; initial #1 ->ni1i1l_event; always @(ni100l_event) ni100l <= 1; always @(ni10li_event) ni10li <= 1; always @(ni11OO_event) ni11OO <= 1; always @(ni1i1l_event) ni1i1l <= 1; initial begin ni1l0l = 0; end always @ ( posedge wire_ni1l0i_CLK or negedge radce_rstb) begin if (radce_rstb == 1'b0) begin ni1l0l <= 0; end else begin ni1l0l <= n00iii; end end assign wire_ni1l0i_CLK = (~ wire_n0l1O_dataout[0]); initial begin ni1lii = 0; end always @ ( posedge wire_ni1l0O_CLK or negedge radce_rstb) begin if (radce_rstb == 1'b0) begin ni1lii <= 0; end else begin ni1lii <= (~ n00iil); end end assign wire_ni1l0O_CLK = wire_n0l1O_dataout[0]; initial begin ni1O1i = 0; end always @ (wire_nl1i0l_dataout or n00iiO or wire_ni1lOO_CLRN) begin if (n00iiO == 1'b1) begin ni1O1i <= 1; end else if (wire_ni1lOO_CLRN == 1'b0) begin ni1O1i <= 0; end else if (wire_nl1i0l_dataout != ni1lOO_clk_prev && wire_nl1i0l_dataout == 1'b1) begin ni1O1i <= wire_ni1O0O_dataout; end ni1lOO_clk_prev <= wire_nl1i0l_dataout; end assign wire_ni1lOO_CLRN = wire_ni1OOi_dataout[0]; initial begin ni1O1O = 0; end always @ (wire_nl1i0l_dataout or wire_ni1O1l_PRN or n00iiO) begin if (wire_ni1O1l_PRN == 1'b0) begin ni1O1O <= 1; end else if (n00iiO == 1'b1) begin ni1O1O <= 0; end else if (wire_nl1i0l_dataout != ni1O1l_clk_prev && wire_nl1i0l_dataout == 1'b1) begin ni1O1O <= (~ wire_ni1O0O_dataout); end ni1O1l_clk_prev <= wire_nl1i0l_dataout; end assign wire_ni1O1l_PRN = wire_ni1OOi_dataout[0]; initial begin nii0li = 0; end always @ (wire_nl1i0l_dataout or n00lli or wire_nii0iO_CLRN) begin if (n00lli == 1'b1) begin nii0li <= 1; end else if (wire_nii0iO_CLRN == 1'b0) begin nii0li <= 0; end else if (wire_nl1i0l_dataout != nii0iO_clk_prev && wire_nl1i0l_dataout == 1'b1) begin nii0li <= wire_nii0OO_dataout; end nii0iO_clk_prev <= wire_nl1i0l_dataout; end assign wire_nii0iO_CLRN = wire_niiiii_dataout[0]; initial begin nii0lO = 0; end always @ (wire_nl1i0l_dataout or wire_nii0ll_PRN or n00lli) begin if (wire_nii0ll_PRN == 1'b0) begin nii0lO <= 1; end else if (n00lli == 1'b1) begin nii0lO <= 0; end else if (wire_nl1i0l_dataout != nii0ll_clk_prev && wire_nl1i0l_dataout == 1'b1) begin nii0lO <= (~ wire_nii0OO_dataout); end nii0ll_clk_prev <= wire_nl1i0l_dataout; end assign wire_nii0ll_PRN = wire_niiiii_dataout[0]; initial begin nii10O = 0; end always @ (wire_nl1i0l_dataout or n00lii or wire_nii10l_CLRN) begin if (n00lii == 1'b1) begin nii10O <= 1; end else if (wire_nii10l_CLRN == 1'b0) begin nii10O <= 0; end else if (wire_nl1i0l_dataout != nii10l_clk_prev && wire_nl1i0l_dataout == 1'b1) begin nii10O <= wire_nii1ll_dataout; end nii10l_clk_prev <= wire_nl1i0l_dataout; end assign wire_nii10l_CLRN = wire_nii01O_dataout[0]; initial begin nii1il = 0; end always @ (wire_nl1i0l_dataout or wire_nii1ii_PRN or n00lii) begin if (wire_nii1ii_PRN == 1'b0) begin nii1il <= 1; end else if (n00lii == 1'b1) begin nii1il <= 0; end else if (wire_nl1i0l_dataout != nii1ii_clk_prev && wire_nl1i0l_dataout == 1'b1) begin nii1il <= (~ wire_nii1ll_dataout); end nii1ii_clk_prev <= wire_nl1i0l_dataout; end assign wire_nii1ii_PRN = wire_nii01O_dataout[0]; initial begin niiiOl = 0; end always @ (wire_nl1i0l_dataout or n00lll or wire_niiiOi_CLRN) begin if (n00lll == 1'b1) begin niiiOl <= 1; end else if (wire_niiiOi_CLRN == 1'b0) begin niiiOl <= 0; end else if (wire_nl1i0l_dataout != niiiOi_clk_prev && wire_nl1i0l_dataout == 1'b1) begin niiiOl <= wire_niil0i_dataout; end niiiOi_clk_prev <= wire_nl1i0l_dataout; end assign wire_niiiOi_CLRN = wire_niilll_dataout[0]; initial begin niil1i = 0; end always @ (wire_nl1i0l_dataout or wire_niiiOO_PRN or n00lll) begin if (wire_niiiOO_PRN == 1'b0) begin niil1i <= 1; end else if (n00lll == 1'b1) begin niil1i <= 0; end else if (wire_nl1i0l_dataout != niiiOO_clk_prev && wire_nl1i0l_dataout == 1'b1) begin niil1i <= (~ wire_niil0i_dataout); end niiiOO_clk_prev <= wire_nl1i0l_dataout; end assign wire_niiiOO_PRN = wire_niilll_dataout[0]; initial begin niiO0l = 0; end always @ (wire_nl1i0l_dataout or wire_niiO0i_PRN or n00lOl) begin if (wire_niiO0i_PRN == 1'b0) begin niiO0l <= 1; end else if (n00lOl == 1'b1) begin niiO0l <= 0; end else if (wire_nl1i0l_dataout != niiO0i_clk_prev && wire_nl1i0l_dataout == 1'b1) begin niiO0l <= (~ wire_niiOil_dataout); end niiO0i_clk_prev <= wire_nl1i0l_dataout; end assign wire_niiO0i_PRN = wire_niiOOO_dataout[0]; initial begin niiO1O = 0; end always @ (wire_nl1i0l_dataout or n00lOl or wire_niiO1l_CLRN) begin if (n00lOl == 1'b1) begin niiO1O <= 1; end else if (wire_niiO1l_CLRN == 1'b0) begin niiO1O <= 0; end else if (wire_nl1i0l_dataout != niiO1l_clk_prev && wire_nl1i0l_dataout == 1'b1) begin niiO1O <= wire_niiOil_dataout; end niiO1l_clk_prev <= wire_nl1i0l_dataout; end assign wire_niiO1l_CLRN = wire_niiOOO_dataout[0]; initial begin nl10OO = 0; end always @ (wire_nl1i1O_dataout or wire_nl10Ol_PRN or wire_nl10Ol_CLRN) begin if (wire_nl10Ol_PRN == 1'b0) begin nl10OO <= 1; end else if (wire_nl10Ol_CLRN == 1'b0) begin nl10OO <= 0; end else if (wire_nl1i1O_dataout != nl10Ol_clk_prev && wire_nl1i1O_dataout == 1'b1) begin nl10OO <= n0l00O; end nl10Ol_clk_prev <= wire_nl1i1O_dataout; end assign wire_nl10Ol_CLRN = wire_nl1lOi_dataout[0], wire_nl10Ol_PRN = ((n0i1iO74 ^ n0i1iO73) & (~ ((~ radce_rstb) & wire_nl1lOi_dataout[0]))); initial begin nl111i = 0; nl11ii = 0; nl11Ol = 0; end always @ (n0li0i or wire_nl11Oi_PRN or wire_nl11Oi_CLRN) begin if (wire_nl11Oi_PRN == 1'b0) begin nl111i <= 1; nl11ii <= 1; nl11Ol <= 1; end else if (wire_nl11Oi_CLRN == 1'b0) begin nl111i <= 0; nl11ii <= 0; nl11Ol <= 0; end else if (n0li0i != nl11Oi_clk_prev && n0li0i == 1'b1) begin nl111i <= wire_niOOOl_dataout; nl11ii <= wire_nl110l_dataout; nl11Ol <= wire_nl11ll_dataout; end nl11Oi_clk_prev <= n0li0i; end assign wire_nl11Oi_CLRN = ((n0i1ii78 ^ n0i1ii77) & n0i1Oi), wire_nl11Oi_PRN = (n0i10O80 ^ n0i10O79); initial begin nl101i = 0; nl111l = 0; nl11il = 0; end always @ (n0li0i or n0i1Oi or wire_nl11OO_CLRN) begin if (n0i1Oi == 1'b0) begin nl101i <= 1; nl111l <= 1; nl11il <= 1; end else if (wire_nl11OO_CLRN == 1'b0) begin nl101i <= 0; nl111l <= 0; nl11il <= 0; end else if (n0li0i != nl11OO_clk_prev && n0li0i == 1'b1) begin nl101i <= (~ wire_nl11ll_dataout); nl111l <= (~ wire_niOOOl_dataout); nl11il <= (~ wire_nl110l_dataout); end nl11OO_clk_prev <= n0li0i; end assign wire_nl11OO_CLRN = (n0i1il76 ^ n0i1il75); event nl101i_event; event nl111l_event; event nl11il_event; initial #1 ->nl101i_event; initial #1 ->nl111l_event; initial #1 ->nl11il_event; always @(nl101i_event) nl101i <= 1; always @(nl111l_event) nl111l <= 1; always @(nl11il_event) nl11il <= 1; initial begin nl1i1l = 0; end always @ ( negedge n0li0i or negedge wire_nl1i1i_CLRN) begin if (wire_nl1i1i_CLRN == 1'b0) begin nl1i1l <= 0; end else begin nl1i1l <= n0i1ll; end end assign wire_nl1i1i_CLRN = ((n0i1li72 ^ n0i1li71) & radce_rstb); initial begin nll01O = 0; end always @ (wire_n1lil_dataout or wire_nll01l_PRN or n0i0li) begin if (wire_nll01l_PRN == 1'b0) begin nll01O <= 1; end else if (n0i0li == 1'b1) begin nll01O <= 0; end else if (wire_n1lil_dataout != nll01l_clk_prev && wire_n1lil_dataout == 1'b1) begin nll01O <= (~ wire_nll00O_dataout); end nll01l_clk_prev <= wire_n1lil_dataout; end assign wire_nll01l_PRN = ((n0i0iO68 ^ n0i0iO67) & wire_nll0Oi_dataout[0]); initial begin nll01i = 0; end always @ (wire_n1lil_dataout or n0i0li or wire_nll1OO_CLRN) begin if (n0i0li == 1'b1) begin nll01i <= 1; end else if (wire_nll1OO_CLRN == 1'b0) begin nll01i <= 0; end else if (wire_n1lil_dataout != nll1OO_clk_prev && wire_n1lil_dataout == 1'b1) begin nll01i <= wire_nll00O_dataout; end nll1OO_clk_prev <= wire_n1lil_dataout; end assign wire_nll1OO_CLRN = ((n0i0il70 ^ n0i0il69) & wire_nll0Oi_dataout[0]); initial begin nlli0l = 0; end always @ (wire_n1lil_dataout or wire_nlli0i_PRN or wire_nlli0i_CLRN) begin if (wire_nlli0i_PRN == 1'b0) begin nlli0l <= 1; end else if (wire_nlli0i_CLRN == 1'b0) begin nlli0l <= 0; end else if (wire_n1lil_dataout != nlli0i_clk_prev && wire_n1lil_dataout == 1'b1) begin nlli0l <= wire_nllili_dataout; end nlli0i_clk_prev <= wire_n1lil_dataout; end assign wire_nlli0i_CLRN = wire_nlll1l_dataout[0], wire_nlli0i_PRN = ((n0i0ll66 ^ n0i0ll65) & (~ n0i0Oi)); initial begin nlliii = 0; end always @ (wire_n1lil_dataout or wire_nlli0O_PRN or n0i0Oi) begin if (wire_nlli0O_PRN == 1'b0) begin nlliii <= 1; end else if (n0i0Oi == 1'b1) begin nlliii <= 0; end else if (wire_n1lil_dataout != nlli0O_clk_prev && wire_n1lil_dataout == 1'b1) begin nlliii <= (~ wire_nllili_dataout); end nlli0O_clk_prev <= wire_n1lil_dataout; end assign wire_nlli0O_PRN = ((n0i0lO64 ^ n0i0lO63) & wire_nlll1l_dataout[0]); initial begin nllliO = 0; end always @ (wire_n1lil_dataout or wire_nlllil_PRN or wire_nlllil_CLRN) begin if (wire_nlllil_PRN == 1'b0) begin nllliO <= 1; end else if (wire_nlllil_CLRN == 1'b0) begin nllliO <= 0; end else if (wire_n1lil_dataout != nlllil_clk_prev && wire_n1lil_dataout == 1'b1) begin nllliO <= wire_nlllOl_dataout; end nlllil_clk_prev <= wire_n1lil_dataout; end assign wire_nlllil_CLRN = wire_nllO0O_dataout[0], wire_nlllil_PRN = ((n0ii1i62 ^ n0ii1i61) & (~ n0ii1l)); initial begin nlllll = 0; end always @ (wire_n1lil_dataout or wire_nlllli_PRN or n0ii1l) begin if (wire_nlllli_PRN == 1'b0) begin nlllll <= 1; end else if (n0ii1l == 1'b1) begin nlllll <= 0; end else if (wire_n1lil_dataout != nlllli_clk_prev && wire_n1lil_dataout == 1'b1) begin nlllll <= (~ wire_nlllOl_dataout); end nlllli_clk_prev <= wire_n1lil_dataout; end assign wire_nlllli_PRN = wire_nllO0O_dataout[0]; initial begin nllOOi = 0; end always @ (wire_n1lil_dataout or n0ii0O or wire_nllOlO_CLRN) begin if (n0ii0O == 1'b1) begin nllOOi <= 1; end else if (wire_nllOlO_CLRN == 1'b0) begin nllOOi <= 0; end else if (wire_n1lil_dataout != nllOlO_clk_prev && wire_n1lil_dataout == 1'b1) begin nllOOi <= wire_nlO11O_dataout; end nllOlO_clk_prev <= wire_n1lil_dataout; end assign wire_nllOlO_CLRN = wire_nlO1li_dataout[0]; initial begin nllOOO = 0; end always @ (wire_n1lil_dataout or wire_nllOOl_PRN or wire_nllOOl_CLRN) begin if (wire_nllOOl_PRN == 1'b0) begin nllOOO <= 1; end else if (wire_nllOOl_CLRN == 1'b0) begin nllOOO <= 0; end else if (wire_n1lil_dataout != nllOOl_clk_prev && wire_n1lil_dataout == 1'b1) begin nllOOO <= (~ wire_nlO11O_dataout); end nllOOl_clk_prev <= wire_n1lil_dataout; end assign wire_nllOOl_CLRN = ((n0ii0l60 ^ n0ii0l59) & (~ n0ii0O)), wire_nllOOl_PRN = wire_nlO1li_dataout[0]; initial begin nlO01l = 0; end always @ (wire_n1lil_dataout or n0iili or wire_nlO01i_CLRN) begin if (n0iili == 1'b1) begin nlO01l <= 1; end else if (wire_nlO01i_CLRN == 1'b0) begin nlO01l <= 0; end else if (wire_n1lil_dataout != nlO01i_clk_prev && wire_n1lil_dataout == 1'b1) begin nlO01l <= wire_nlO0ii_dataout; end nlO01i_clk_prev <= wire_n1lil_dataout; end assign wire_nlO01i_CLRN = wire_nlO0Ol_dataout[0]; initial begin nlO00i = 0; end always @ (wire_n1lil_dataout or wire_nlO01O_PRN or n0iili) begin if (wire_nlO01O_PRN == 1'b0) begin nlO00i <= 1; end else if (n0iili == 1'b1) begin nlO00i <= 0; end else if (wire_n1lil_dataout != nlO01O_clk_prev && wire_n1lil_dataout == 1'b1) begin nlO00i <= (~ wire_nlO0ii_dataout); end nlO01O_clk_prev <= wire_n1lil_dataout; end assign wire_nlO01O_PRN = ((n0iiiO58 ^ n0iiiO57) & wire_nlO0Ol_dataout[0]); initial begin nlOi0O = 0; end always @ (wire_n1lil_dataout or n0iiOl or wire_nlOi0l_CLRN) begin if (n0iiOl == 1'b1) begin nlOi0O <= 1; end else if (wire_nlOi0l_CLRN == 1'b0) begin nlOi0O <= 0; end else if (wire_n1lil_dataout != nlOi0l_clk_prev && wire_n1lil_dataout == 1'b1) begin nlOi0O <= wire_nlOill_dataout; end nlOi0l_clk_prev <= wire_n1lil_dataout; end assign wire_nlOi0l_CLRN = wire_nlOl1O_dataout[0]; initial begin nlOiil = 0; end always @ (wire_n1lil_dataout or wire_nlOiii_PRN or wire_nlOiii_CLRN) begin if (wire_nlOiii_PRN == 1'b0) begin nlOiil <= 1; end else if (wire_nlOiii_CLRN == 1'b0) begin nlOiil <= 0; end else if (wire_n1lil_dataout != nlOiii_clk_prev && wire_n1lil_dataout == 1'b1) begin nlOiil <= (~ wire_nlOill_dataout); end nlOiii_clk_prev <= wire_n1lil_dataout; end assign wire_nlOiii_CLRN = ((n0iiOi56 ^ n0iiOi55) & (~ n0iiOl)), wire_nlOiii_PRN = wire_nlOl1O_dataout[0]; io_buf_tri n00il ( .datain(wire_nl1llO_dataout[0]), .dataout(wire_n00il_dataout), .oe(((radce_hflck[0] & radce_hflck[1]) & radce_hflck[2]))); io_buf_tri n00iO ( .datain(n01il), .dataout(wire_n00iO_dataout), .oe((((~ radce_hflck[0]) & radce_hflck[1]) & radce_hflck[2]))); io_buf_tri n00li ( .datain(n011O), .dataout(wire_n00li_dataout), .oe(((radce_hflck[0] & (~ radce_hflck[1])) & radce_hflck[2]))); io_buf_tri n00ll ( .datain(n1OOl), .dataout(wire_n00ll_dataout), .oe((((~ radce_hflck[0]) & (~ radce_hflck[1])) & radce_hflck[2]))); io_buf_tri n00lO ( .datain(n1Oli), .dataout(wire_n00lO_dataout), .oe(((radce_hflck[0] & radce_hflck[1]) & (~ radce_hflck[2])))); io_buf_tri n00Oi ( .datain(n1O0O), .dataout(wire_n00Oi_dataout), .oe((((~ radce_hflck[0]) & radce_hflck[1]) & (~ radce_hflck[2])))); io_buf_tri n00Ol ( .datain(n1O1l), .dataout(wire_n00Ol_dataout), .oe(((radce_hflck[0] & (~ radce_hflck[1])) & (~ radce_hflck[2])))); io_buf_tri n00OO ( .datain(n0l1il), .dataout(wire_n00OO_dataout), .oe((((~ radce_hflck[0]) & (~ radce_hflck[1])) & (~ radce_hflck[2])))); io_buf_tri n010l ( .datain(wire_n010O_dataout), .dataout(wire_n010l_dataout), .oe(1'b1)); io_buf_tri n011i ( .datain(wire_n011l_dataout), .dataout(wire_n011i_dataout), .oe(1'b1)); io_buf_tri n0ili ( .datain(wire_nl1llO_dataout[0]), .dataout(wire_n0ili_dataout), .oe(((radce_lflck[0] & radce_lflck[1]) & radce_lflck[2]))); io_buf_tri n0ill ( .datain(n01il), .dataout(wire_n0ill_dataout), .oe((((~ radce_lflck[0]) & radce_lflck[1]) & radce_lflck[2]))); io_buf_tri n0ilO ( .datain(n011O), .dataout(wire_n0ilO_dataout), .oe(((radce_lflck[0] & (~ radce_lflck[1])) & radce_lflck[2]))); io_buf_tri n0iOi ( .datain(n1OOl), .dataout(wire_n0iOi_dataout), .oe((((~ radce_lflck[0]) & (~ radce_lflck[1])) & radce_lflck[2]))); io_buf_tri n0iOl ( .datain(n1Oli), .dataout(wire_n0iOl_dataout), .oe(((radce_lflck[0] & radce_lflck[1]) & (~ radce_lflck[2])))); io_buf_tri n0iOO ( .datain(n1O0O), .dataout(wire_n0iOO_dataout), .oe((((~ radce_lflck[0]) & radce_lflck[1]) & (~ radce_lflck[2])))); io_buf_tri n0l1i ( .datain(n1O1l), .dataout(wire_n0l1i_dataout), .oe(((radce_lflck[0] & (~ radce_lflck[1])) & (~ radce_lflck[2])))); io_buf_tri n0l1l ( .datain(n0l1il), .dataout(wire_n0l1l_dataout), .oe((((~ radce_lflck[0]) & (~ radce_lflck[1])) & (~ radce_lflck[2])))); io_buf_tri n0liil ( .datain(wire_n0liiO_dataout), .dataout(wire_n0liil_dataout), .oe(1'b1)); io_buf_tri n0liOi ( .datain(wire_n0liOl_dataout), .dataout(wire_n0liOi_dataout), .oe(1'b1)); io_buf_tri n0ll1O ( .datain(wire_n0ll0i_dataout), .dataout(wire_n0ll1O_dataout), .oe(1'b1)); io_buf_tri n0llil ( .datain(wire_n0lliO_dataout), .dataout(wire_n0llil_dataout), .oe(1'b1)); io_buf_tri n0O01O ( .datain(wire_n0O00i_dataout), .dataout(wire_n0O01O_dataout), .oe(1'b1)); io_buf_tri n0O11O ( .datain(wire_n0O10i_dataout), .dataout(wire_n0O11O_dataout), .oe(1'b1)); io_buf_tri n0O1il ( .datain(wire_n0O1iO_dataout), .dataout(wire_n0O1il_dataout), .oe(1'b1)); io_buf_tri n0O1Oi ( .datain(wire_n0O1Ol_dataout), .dataout(wire_n0O1Oi_dataout), .oe(1'b1)); io_buf_tri n0Ol1l ( .datain(wire_n0Ol1O_dataout), .dataout(wire_n0Ol1l_dataout), .oe(1'b1)); io_buf_tri n0Olii ( .datain(wire_n0Olil_dataout), .dataout(wire_n0Olii_dataout), .oe(1'b1)); io_buf_tri n0OllO ( .datain(wire_n0OlOi_dataout), .dataout(wire_n0OllO_dataout), .oe(1'b1)); io_buf_tri n0OO1l ( .datain(wire_n0OO1O_dataout), .dataout(wire_n0OO1l_dataout), .oe(1'b1)); io_buf_tri n100O ( .datain(wire_n10ii_dataout), .dataout(wire_n100O_dataout), .oe(1'b1)); io_buf_tri n101l ( .datain(wire_n101O_dataout), .dataout(wire_n101l_dataout), .oe(1'b1)); io_buf_tri n10il ( .datain(wire_n10iO_dataout), .dataout(wire_n10il_dataout), .oe(1'b1)); io_buf_tri n10lO ( .datain(wire_n10Oi_dataout), .dataout(wire_n10lO_dataout), .oe(1'b1)); io_buf_tri n10Ol ( .datain(wire_n10OO_dataout), .dataout(wire_n10Ol_dataout), .oe(1'b1)); io_buf_tri n11OO ( .datain(wire_n101i_dataout), .dataout(wire_n11OO_dataout), .oe(1'b1)); io_buf_tri n1l0O ( .datain(wire_n1lii_dataout), .dataout(wire_n1l0O_dataout), .oe(1'b1)); io_buf_tri n1lil ( .datain(wire_n1liO_dataout), .dataout(wire_n1lil_dataout), .oe(1'b1)); io_buf_tri n1lOO ( .datain(wire_n1O1i_dataout), .dataout(wire_n1lOO_dataout), .oe(1'b1)); io_buf_tri n1O0i ( .datain(wire_n1O0l_dataout), .dataout(wire_n1O0i_dataout), .oe(1'b1)); io_buf_tri n1Oil ( .datain(wire_n1OiO_dataout), .dataout(wire_n1Oil_dataout), .oe(1'b1)); io_buf_tri n1OlO ( .datain(wire_n1OOi_dataout), .dataout(wire_n1OlO_dataout), .oe(1'b1)); io_buf_tri ni00lO ( .datain(wire_ni00Oi_dataout), .dataout(wire_ni00lO_dataout), .oe(1'b1)); io_buf_tri ni00Ol ( .datain(wire_ni00OO_dataout), .dataout(wire_ni00Ol_dataout), .oe(1'b1)); io_buf_tri ni01i ( .datain(((n0l11l28 ^ n0l11l27) & n1O0O)), .dataout(wire_ni01i_dataout), .oe((~ (((~ wire_nl1llO_dataout[0]) & (~ (((~ n0l11i) | (~ n0iOOO)) | (~ n0iOOl)))) & (n0iOlO30 ^ n0iOlO29))))); io_buf_tri ni01il ( .datain(wire_ni01iO_dataout), .dataout(wire_ni01il_dataout), .oe(1'b1)); io_buf_tri ni01li ( .datain(wire_ni01ll_dataout), .dataout(wire_ni01li_dataout), .oe(1'b1)); io_buf_tri ni01lO ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_ni01lO_dataout), .oe(wire_nl1lOi_dataout[0])); io_buf_tri ni01Oi ( .datain(radce_rstb), .dataout(wire_ni01Oi_dataout), .oe((~ wire_nl1lOi_dataout[0]))); io_buf_tri ni01Ol ( .datain(radce_rstb), .dataout(wire_ni01Ol_dataout), .oe(wire_nl1lOi_dataout[0])); io_buf_tri ni01OO ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_ni01OO_dataout), .oe((~ wire_nl1lOi_dataout[0]))); io_buf_tri ni0i0i ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_ni0i0i_dataout), .oe((~ wire_nl1lOi_dataout[0]))); io_buf_tri ni0i1i ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_ni0i1i_dataout), .oe(wire_nl1lOi_dataout[0])); io_buf_tri ni0i1l ( .datain(radce_rstb), .dataout(wire_ni0i1l_dataout), .oe((~ wire_nl1lOi_dataout[0]))); io_buf_tri ni0i1O ( .datain(radce_rstb), .dataout(wire_ni0i1O_dataout), .oe(wire_nl1lOi_dataout[0])); io_buf_tri ni0l0l ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_ni0l0l_dataout), .oe((~ wire_niOiil_dataout[0]))); io_buf_tri ni0l0O ( .datain(radce_rstb), .dataout(wire_ni0l0O_dataout), .oe(wire_niOiil_dataout[0])); io_buf_tri ni0l1i ( .datain(wire_ni0l1l_dataout), .dataout(wire_ni0l1i_dataout), .oe(1'b1)); io_buf_tri ni0l1O ( .datain(wire_ni0l0i_dataout), .dataout(wire_ni0l1O_dataout), .oe(1'b1)); io_buf_tri ni0lii ( .datain(radce_rstb), .dataout(wire_ni0lii_dataout), .oe((~ wire_niOiil_dataout[0]))); io_buf_tri ni0lil ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_ni0lil_dataout), .oe(wire_niOiil_dataout[0])); io_buf_tri ni0O0l ( .datain(wire_ni0O0O_dataout), .dataout(wire_ni0O0l_dataout), .oe(1'b1)); io_buf_tri ni0Oii ( .datain(wire_ni0Oil_dataout), .dataout(wire_ni0Oii_dataout), .oe(1'b1)); io_buf_tri ni0OiO ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_ni0OiO_dataout), .oe((~ wire_niOl0O_dataout[0]))); io_buf_tri ni0Oli ( .datain(radce_rstb), .dataout(wire_ni0Oli_dataout), .oe(wire_niOl0O_dataout[0])); io_buf_tri ni0Oll ( .datain(radce_rstb), .dataout(wire_ni0Oll_dataout), .oe((~ wire_niOl0O_dataout[0]))); io_buf_tri ni0OlO ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_ni0OlO_dataout), .oe(wire_niOl0O_dataout[0])); io_buf_tri ni101l ( .datain(wire_ni101O_dataout), .dataout(wire_ni101l_dataout), .oe(1'b1)); io_buf_tri ni10ii ( .datain(wire_ni10il_dataout), .dataout(wire_ni10ii_dataout), .oe(1'b1)); io_buf_tri ni10lO ( .datain(wire_ni10Oi_dataout), .dataout(wire_ni10lO_dataout), .oe(1'b1)); io_buf_tri ni11lO ( .datain(wire_ni11Oi_dataout), .dataout(wire_ni11lO_dataout), .oe(1'b1)); io_buf_tri ni1ii ( .datain(n1Oli), .dataout(wire_ni1ii_dataout), .oe((wire_nl1llO_dataout[0] | (~ n0iOil)))); io_buf_tri ni1il ( .datain(n011O), .dataout(wire_ni1il_dataout), .oe(((wire_nl1llO_dataout[0] | (~ n0iO0l)) | (~ n0iO1O)))); io_buf_tri ni1iO ( .datain(n01il), .dataout(wire_ni1iO_dataout), .oe((~ ((~ wire_nl1llO_dataout[0]) & (~ (wire_nl1llO_dataout[0] | (~ n0iO0i))))))); io_buf_tri ni1li ( .datain(n0l1il), .dataout(wire_ni1li_dataout), .oe((~ n0iOli))); io_buf_tri ni1ll ( .datain(n1O0O), .dataout(wire_ni1ll_dataout), .oe(((n0iO1l40 ^ n0iO1l39) & (((~ n0l11i) | (~ n0iO0i)) | (~ n0iO1O))))); io_buf_tri ni1lO ( .datain(((n0iO0O38 ^ n0iO0O37) & n1Oli)), .dataout(wire_ni1lO_dataout), .oe((wire_nl1llO_dataout[0] | (~ n0iO0l)))); io_buf_tri ni1O0i ( .datain(wire_ni1O0l_dataout), .dataout(wire_ni1O0i_dataout), .oe(1'b1)); io_buf_tri ni1O0O ( .datain(wire_ni1Oii_dataout), .dataout(wire_ni1O0O_dataout), .oe(1'b1)); io_buf_tri ni1Oi ( .datain(n011O), .dataout(wire_ni1Oi_dataout), .oe(((n0iOii36 ^ n0iOii35) & ((wire_nl1llO_dataout[0] | (~ n0iOil)) | (~ n0iOOl))))); io_buf_tri ni1Oil ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_ni1Oil_dataout), .oe(wire_nl1lOi_dataout[0])); io_buf_tri ni1OiO ( .datain(radce_rstb), .dataout(wire_ni1OiO_dataout), .oe((~ wire_nl1lOi_dataout[0]))); io_buf_tri ni1Ol ( .datain(n01il), .dataout(wire_ni1Ol_dataout), .oe(((n0iOiO34 ^ n0iOiO33) & (~ n0iOOO)))); io_buf_tri ni1Oli ( .datain(radce_rstb), .dataout(wire_ni1Oli_dataout), .oe(wire_nl1lOi_dataout[0])); io_buf_tri ni1Oll ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_ni1Oll_dataout), .oe((~ wire_nl1lOi_dataout[0]))); io_buf_tri ni1OO ( .datain(((n0iOll32 ^ n0iOll31) & n0l1il)), .dataout(wire_ni1OO_dataout), .oe((~ n0iOli))); io_buf_tri nii01i ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_nii01i_dataout), .oe(wire_niOO0i_dataout[0])); io_buf_tri nii0Oi ( .datain(wire_nii0Ol_dataout), .dataout(wire_nii0Oi_dataout), .oe(1'b1)); io_buf_tri nii0OO ( .datain(wire_niii1i_dataout), .dataout(wire_nii0OO_dataout), .oe(1'b1)); io_buf_tri nii1iO ( .datain(wire_nii1li_dataout), .dataout(wire_nii1iO_dataout), .oe(1'b1)); io_buf_tri nii1ll ( .datain(wire_nii1lO_dataout), .dataout(wire_nii1ll_dataout), .oe(1'b1)); io_buf_tri nii1Oi ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_nii1Oi_dataout), .oe((~ wire_niOO0i_dataout[0]))); io_buf_tri nii1Ol ( .datain(radce_rstb), .dataout(wire_nii1Ol_dataout), .oe(wire_niOO0i_dataout[0])); io_buf_tri nii1OO ( .datain(radce_rstb), .dataout(wire_nii1OO_dataout), .oe((~ wire_niOO0i_dataout[0]))); io_buf_tri niii0i ( .datain(radce_rstb), .dataout(wire_niii0i_dataout), .oe(wire_nl1llO_dataout[0])); io_buf_tri niii0l ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_niii0l_dataout), .oe((~ wire_nl1llO_dataout[0]))); io_buf_tri niii1l ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_niii1l_dataout), .oe(wire_nl1llO_dataout[0])); io_buf_tri niii1O ( .datain(radce_rstb), .dataout(wire_niii1O_dataout), .oe((~ wire_nl1llO_dataout[0]))); io_buf_tri niil0i ( .datain(wire_niil0l_dataout), .dataout(wire_niil0i_dataout), .oe(1'b1)); io_buf_tri niil0O ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_niil0O_dataout), .oe(wire_nl1llO_dataout[0])); io_buf_tri niil1l ( .datain(wire_niil1O_dataout), .dataout(wire_niil1l_dataout), .oe(1'b1)); io_buf_tri niilii ( .datain(radce_rstb), .dataout(wire_niilii_dataout), .oe((~ wire_nl1llO_dataout[0]))); io_buf_tri niilil ( .datain(radce_rstb), .dataout(wire_niilil_dataout), .oe(wire_nl1llO_dataout[0])); io_buf_tri niiliO ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_niiliO_dataout), .oe((~ wire_nl1llO_dataout[0]))); io_buf_tri niiO0O ( .datain(wire_niiOii_dataout), .dataout(wire_niiO0O_dataout), .oe(1'b1)); io_buf_tri niiOil ( .datain(wire_niiOiO_dataout), .dataout(wire_niiOil_dataout), .oe(1'b1)); io_buf_tri niiOli ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_niiOli_dataout), .oe(wire_nl1lOi_dataout[0])); io_buf_tri niiOll ( .datain(radce_rstb), .dataout(wire_niiOll_dataout), .oe((~ wire_nl1lOi_dataout[0]))); io_buf_tri niiOlO ( .datain(radce_rstb), .dataout(wire_niiOlO_dataout), .oe(wire_nl1lOi_dataout[0])); io_buf_tri niiOOi ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_niiOOi_dataout), .oe((~ wire_nl1lOi_dataout[0]))); io_buf_tri nil01l ( .datain(wire_nil01O_dataout), .dataout(wire_nil01l_dataout), .oe(1'b1)); io_buf_tri nil10l ( .datain(wire_nil10O_dataout), .dataout(wire_nil10l_dataout), .oe(1'b1)); io_buf_tri nil1ii ( .datain(wire_nil1il_dataout), .dataout(wire_nil1ii_dataout), .oe(1'b1)); io_buf_tri nil1iO ( .datain(wire_nil1li_dataout), .dataout(wire_nil1iO_dataout), .oe(1'b1)); io_buf_tri nil1ll ( .datain(wire_nil1lO_dataout), .dataout(wire_nil1ll_dataout), .oe(1'b1)); io_buf_tri nil1Oi ( .datain(wire_nil1Ol_dataout), .dataout(wire_nil1Oi_dataout), .oe(1'b1)); io_buf_tri nil1OO ( .datain(wire_nil01i_dataout), .dataout(wire_nil1OO_dataout), .oe(1'b1)); io_buf_tri niO0ll ( .datain((~ eqa_set[0])), .dataout(wire_niO0ll_dataout), .oe((~ n0l0ll))); io_buf_tri niO0lO ( .datain((~ eqb_set[0])), .dataout(wire_niO0lO_dataout), .oe((~ n0l0li))); io_buf_tri niO0Oi ( .datain((~ eqc_set[0])), .dataout(wire_niO0Oi_dataout), .oe((~ n0l0iO))); io_buf_tri niO0Ol ( .datain((~ eqd_set[0])), .dataout(wire_niO0Ol_dataout), .oe((~ n0l0il))); io_buf_tri niO0OO ( .datain((~ eqa_set[0])), .dataout(wire_niO0OO_dataout), .oe((~ n00Oli))); io_buf_tri niOi0i ( .datain(wire_nl1llO_dataout[0]), .dataout(wire_niOi0i_dataout), .oe((~ n00OOl))); io_buf_tri niOi0l ( .datain((~ eqv_set[0])), .dataout(wire_niOi0l_dataout), .oe((~ n00OOO))); io_buf_tri niOi0O ( .datain((~ eqv_set[0])), .dataout(wire_niOi0O_dataout), .oe(n0l0ii)); io_buf_tri niOi1i ( .datain((~ eqb_set[0])), .dataout(wire_niOi1i_dataout), .oe((~ n00Oll))); io_buf_tri niOi1l ( .datain((~ eqc_set[0])), .dataout(wire_niOi1l_dataout), .oe(n00OlO)); io_buf_tri niOi1O ( .datain((~ eqd_set[0])), .dataout(wire_niOi1O_dataout), .oe(n00OOi)); io_buf_tri niOiiO ( .datain((~ eqa_set[1])), .dataout(wire_niOiiO_dataout), .oe((~ n0l0ll))); io_buf_tri niOili ( .datain((~ eqb_set[1])), .dataout(wire_niOili_dataout), .oe((~ n0l0li))); io_buf_tri niOill ( .datain((~ eqc_set[1])), .dataout(wire_niOill_dataout), .oe((~ n0l0iO))); io_buf_tri niOilO ( .datain((~ eqd_set[1])), .dataout(wire_niOilO_dataout), .oe((~ n0l0il))); io_buf_tri niOiOi ( .datain((~ eqa_set[1])), .dataout(wire_niOiOi_dataout), .oe((~ n00Oli))); io_buf_tri niOiOl ( .datain((~ eqb_set[1])), .dataout(wire_niOiOl_dataout), .oe((~ n00Oll))); io_buf_tri niOiOO ( .datain((~ eqc_set[1])), .dataout(wire_niOiOO_dataout), .oe(n00OlO)); io_buf_tri niOl0i ( .datain((~ eqv_set[1])), .dataout(wire_niOl0i_dataout), .oe(n0l0ii)); io_buf_tri niOl1i ( .datain((~ eqd_set[1])), .dataout(wire_niOl1i_dataout), .oe(n00OOi)); io_buf_tri niOl1l ( .datain(wire_nl1llO_dataout[0]), .dataout(wire_niOl1l_dataout), .oe((~ n00OOl))); io_buf_tri niOl1O ( .datain((~ eqv_set[1])), .dataout(wire_niOl1O_dataout), .oe((~ n00OOO))); io_buf_tri niOlii ( .datain((~ eqa_set[2])), .dataout(wire_niOlii_dataout), .oe((~ n0l0ll))); io_buf_tri niOlil ( .datain((~ eqb_set[2])), .dataout(wire_niOlil_dataout), .oe((~ n0l0li))); io_buf_tri niOliO ( .datain((~ eqc_set[2])), .dataout(wire_niOliO_dataout), .oe((~ n0l0iO))); io_buf_tri niOlli ( .datain((~ eqd_set[2])), .dataout(wire_niOlli_dataout), .oe((~ n0l0il))); io_buf_tri niOlll ( .datain((~ eqa_set[2])), .dataout(wire_niOlll_dataout), .oe((~ n00Oli))); io_buf_tri niOllO ( .datain((~ eqb_set[2])), .dataout(wire_niOllO_dataout), .oe((~ n00Oll))); io_buf_tri niOlOi ( .datain((~ eqc_set[2])), .dataout(wire_niOlOi_dataout), .oe(n00OlO)); io_buf_tri niOlOl ( .datain((~ eqd_set[2])), .dataout(wire_niOlOl_dataout), .oe(n00OOi)); io_buf_tri niOlOO ( .datain(wire_nl1llO_dataout[0]), .dataout(wire_niOlOO_dataout), .oe((~ n00OOl))); io_buf_tri niOO0l ( .datain(wire_niOO0O_dataout), .dataout(wire_niOO0l_dataout), .oe(1'b1)); io_buf_tri niOO1i ( .datain((~ eqv_set[2])), .dataout(wire_niOO1i_dataout), .oe((~ n00OOO))); io_buf_tri niOO1l ( .datain((~ eqv_set[2])), .dataout(wire_niOO1l_dataout), .oe(n0l0ii)); io_buf_tri niOOlO ( .datain(wire_niOOOi_dataout), .dataout(wire_niOOlO_dataout), .oe(1'b1)); io_buf_tri niOOOl ( .datain(wire_niOOOO_dataout), .dataout(wire_niOOOl_dataout), .oe(1'b1)); io_buf_tri nl000i ( .datain(1'b0), .dataout(wire_nl000i_dataout), .oe((((~ eqb_set[0]) & (~ eqb_set[1])) & eqb_set[2]))); io_buf_tri nl000l ( .datain(1'b0), .dataout(wire_nl000l_dataout), .oe(((eqb_set[0] & eqb_set[1]) & (~ eqb_set[2])))); io_buf_tri nl000O ( .datain(1'b0), .dataout(wire_nl000O_dataout), .oe((((~ eqb_set[0]) & eqb_set[1]) & (~ eqb_set[2])))); io_buf_tri nl001i ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_nl001i_dataout), .oe(((eqb_set[0] & eqb_set[1]) & eqb_set[2]))); io_buf_tri nl001l ( .datain(1'b0), .dataout(wire_nl001l_dataout), .oe((((~ eqb_set[0]) & eqb_set[1]) & eqb_set[2]))); io_buf_tri nl001O ( .datain(1'b0), .dataout(wire_nl001O_dataout), .oe(((eqb_set[0] & (~ eqb_set[1])) & eqb_set[2]))); io_buf_tri nl00ii ( .datain(1'b0), .dataout(wire_nl00ii_dataout), .oe(((eqb_set[0] & (~ eqb_set[1])) & (~ eqb_set[2])))); io_buf_tri nl00il ( .datain(wire_nl1llO_dataout[0]), .dataout(wire_nl00il_dataout), .oe((((~ eqb_set[0]) & (~ eqb_set[1])) & (~ eqb_set[2])))); io_buf_tri nl00li ( .datain(1'b0), .dataout(wire_nl00li_dataout), .oe((radce_adapt & (~ n0l0li)))); io_buf_tri nl00ll ( .datain(wire_nl00iO_dataout[0]), .dataout(wire_nl00ll_dataout), .oe(((~ (radce_adapt | (~ radce_pdb))) | ((radce_adapt & n0l0li) & (~ ((~ (((~ n0l0il) | (~ n0l0iO)) & (~ n0i01l))) & (~ (((n0l0ii | (~ n0l0il)) | (~ n0l0iO)) & n0i01l)))))))); io_buf_tri nl00lO ( .datain(wire_nl1llO_dataout[0]), .dataout(wire_nl00lO_dataout), .oe((~ n0i01O))); io_buf_tri nl00Oi ( .datain(wire_nl00Ol_dataout), .dataout(wire_nl00Oi_dataout), .oe((n0i01O & ((radce_adapt & n0l0li) & (~ ((~ ((~ n0l0ll) & n0i01l)) & (~ ((~ n0i01l) & ((~ n0l0ll) | n0l0ii))))))))); io_buf_tri nl00Ol ( .datain(wire_nl00OO_dataout), .dataout(wire_nl00Ol_dataout), .oe(1'b1)); io_buf_tri nl0lll ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_nl0lll_dataout), .oe(((eqc_set[0] & eqc_set[1]) & eqc_set[2]))); io_buf_tri nl0llO ( .datain(1'b0), .dataout(wire_nl0llO_dataout), .oe((((~ eqc_set[0]) & eqc_set[1]) & eqc_set[2]))); io_buf_tri nl0lOi ( .datain(1'b0), .dataout(wire_nl0lOi_dataout), .oe(((eqc_set[0] & (~ eqc_set[1])) & eqc_set[2]))); io_buf_tri nl0lOl ( .datain(1'b0), .dataout(wire_nl0lOl_dataout), .oe((((~ eqc_set[0]) & (~ eqc_set[1])) & eqc_set[2]))); io_buf_tri nl0lOO ( .datain(1'b0), .dataout(wire_nl0lOO_dataout), .oe(((eqc_set[0] & eqc_set[1]) & (~ eqc_set[2])))); io_buf_tri nl0O0l ( .datain(1'b0), .dataout(wire_nl0O0l_dataout), .oe((radce_adapt & (~ n0l0iO)))); io_buf_tri nl0O0O ( .datain(wire_nl0O0i_dataout[0]), .dataout(wire_nl0O0O_dataout), .oe(((~ (radce_adapt | (~ radce_pdb))) | ((radce_adapt & n0l0iO) & (~ ((~ (rseq_sel[1] & (n0l0ii | (~ n0l0il)))) & (~ ((~ rseq_sel[1]) & (~ n0l0il))))))))); io_buf_tri nl0O1i ( .datain(1'b0), .dataout(wire_nl0O1i_dataout), .oe((((~ eqc_set[0]) & eqc_set[1]) & (~ eqc_set[2])))); io_buf_tri nl0O1l ( .datain(1'b0), .dataout(wire_nl0O1l_dataout), .oe(((eqc_set[0] & (~ eqc_set[1])) & (~ eqc_set[2])))); io_buf_tri nl0O1O ( .datain(wire_nl1llO_dataout[0]), .dataout(wire_nl0O1O_dataout), .oe((((~ eqc_set[0]) & (~ eqc_set[1])) & (~ eqc_set[2])))); io_buf_tri nl0Oii ( .datain(wire_nl1llO_dataout[0]), .dataout(wire_nl0Oii_dataout), .oe((~ n0i00i))); io_buf_tri nl0Oil ( .datain(wire_nl0OiO_dataout), .dataout(wire_nl0Oil_dataout), .oe((n0i00i & ((radce_adapt & n0l0iO) & (~ ((~ ((~ rseq_sel[1]) & (((~ n0l0ll) | n0l0ii) | (~ n0l0li)))) & (~ (rseq_sel[1] & ((~ n0l0ll) | (~ n0l0li)))))))))); io_buf_tri nl0OiO ( .datain(wire_nl0Oli_dataout), .dataout(wire_nl0OiO_dataout), .oe(1'b1)); io_buf_tri nl110l ( .datain(wire_nl110O_dataout), .dataout(wire_nl110l_dataout), .oe(1'b1)); io_buf_tri nl111O ( .datain(wire_nl110i_dataout), .dataout(wire_nl111O_dataout), .oe(1'b1)); io_buf_tri nl11iO ( .datain(wire_nl11li_dataout), .dataout(wire_nl11iO_dataout), .oe(1'b1)); io_buf_tri nl11ll ( .datain(wire_nl11lO_dataout), .dataout(wire_nl11ll_dataout), .oe(1'b1)); io_buf_tri nl1i0l ( .datain(wire_nl1i0O_dataout), .dataout(wire_nl1i0l_dataout), .oe(1'b1)); io_buf_tri nl1i1O ( .datain(wire_nl1i0i_dataout), .dataout(wire_nl1i1O_dataout), .oe(1'b1)); io_buf_tri nl1l0i ( .datain(1'b0), .dataout(wire_nl1l0i_dataout), .oe((((~ eqa_set[0]) & eqa_set[1]) & eqa_set[2]))); io_buf_tri nl1l0l ( .datain(1'b0), .dataout(wire_nl1l0l_dataout), .oe(((eqa_set[0] & (~ eqa_set[1])) & eqa_set[2]))); io_buf_tri nl1l0O ( .datain(1'b0), .dataout(wire_nl1l0O_dataout), .oe((((~ eqa_set[0]) & (~ eqa_set[1])) & eqa_set[2]))); io_buf_tri nl1l1O ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_nl1l1O_dataout), .oe(((eqa_set[0] & eqa_set[1]) & eqa_set[2]))); io_buf_tri nl1lii ( .datain(1'b0), .dataout(wire_nl1lii_dataout), .oe(((eqa_set[0] & eqa_set[1]) & (~ eqa_set[2])))); io_buf_tri nl1lil ( .datain(1'b0), .dataout(wire_nl1lil_dataout), .oe((((~ eqa_set[0]) & eqa_set[1]) & (~ eqa_set[2])))); io_buf_tri nl1liO ( .datain(1'b0), .dataout(wire_nl1liO_dataout), .oe(((eqa_set[0] & (~ eqa_set[1])) & (~ eqa_set[2])))); io_buf_tri nl1lli ( .datain(wire_nl1llO_dataout[0]), .dataout(wire_nl1lli_dataout), .oe((((~ eqa_set[0]) & (~ eqa_set[1])) & (~ eqa_set[2])))); io_buf_tri nl1lOl ( .datain(1'b0), .dataout(wire_nl1lOl_dataout), .oe((radce_adapt & (~ n0l0ll)))); io_buf_tri nl1lOO ( .datain(wire_nl1lll_dataout[0]), .dataout(wire_nl1lOO_dataout), .oe(((~ (radce_adapt | (~ radce_pdb))) | ((radce_adapt & n0l0ll) & wire_nl1lOi_dataout[0])))); io_buf_tri nl1O1i ( .datain(wire_nl1llO_dataout[0]), .dataout(wire_nl1O1i_dataout), .oe((~ n0i01i))); io_buf_tri nl1O1l ( .datain(wire_nl1O1O_dataout), .dataout(wire_nl1O1l_dataout), .oe((n0i01i & ((radce_adapt & n0l0ll) & wire_nl1llO_dataout[0])))); io_buf_tri nl1O1O ( .datain(wire_nl1O0i_dataout), .dataout(wire_nl1O1O_dataout), .oe(1'b1)); io_buf_tri nli00i ( .datain(1'b0), .dataout(wire_nli00i_dataout), .oe(((eqd_set[0] & (~ eqd_set[1])) & eqd_set[2]))); io_buf_tri nli00l ( .datain(1'b0), .dataout(wire_nli00l_dataout), .oe((((~ eqd_set[0]) & (~ eqd_set[1])) & eqd_set[2]))); io_buf_tri nli00O ( .datain(1'b0), .dataout(wire_nli00O_dataout), .oe(((eqd_set[0] & eqd_set[1]) & (~ eqd_set[2])))); io_buf_tri nli01l ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_nli01l_dataout), .oe(((eqd_set[0] & eqd_set[1]) & eqd_set[2]))); io_buf_tri nli01O ( .datain(1'b0), .dataout(wire_nli01O_dataout), .oe((((~ eqd_set[0]) & eqd_set[1]) & eqd_set[2]))); io_buf_tri nli0ii ( .datain(1'b0), .dataout(wire_nli0ii_dataout), .oe((((~ eqd_set[0]) & eqd_set[1]) & (~ eqd_set[2])))); io_buf_tri nli0il ( .datain(1'b0), .dataout(wire_nli0il_dataout), .oe(((eqd_set[0] & (~ eqd_set[1])) & (~ eqd_set[2])))); io_buf_tri nli0iO ( .datain(wire_nl1llO_dataout[0]), .dataout(wire_nli0iO_dataout), .oe((((~ eqd_set[0]) & (~ eqd_set[1])) & (~ eqd_set[2])))); io_buf_tri nli0ll ( .datain(1'b0), .dataout(wire_nli0ll_dataout), .oe((radce_adapt & (~ n0l0il)))); io_buf_tri nli0lO ( .datain(wire_nli0li_dataout[0]), .dataout(wire_nli0lO_dataout), .oe(((~ (radce_adapt | (~ radce_pdb))) | ((radce_adapt & n0l0il) & (n0l0ii & n0i00l))))); io_buf_tri nli0Oi ( .datain(wire_nl1llO_dataout[0]), .dataout(wire_nli0Oi_dataout), .oe((~ n0i00O))); io_buf_tri nli0Ol ( .datain(wire_nli0OO_dataout), .dataout(wire_nli0Ol_dataout), .oe((n0i00O & ((radce_adapt & n0l0il) & (~ ((~ ((~ n0l0ll) | (~ n0i00l))) & (~ ((~ n0l0li) | (~ n0l0iO))))))))); io_buf_tri nli0OO ( .datain(wire_nlii1i_dataout), .dataout(wire_nli0OO_dataout), .oe(1'b1)); io_buf_tri nliOil ( .datain(1'b0), .dataout(wire_nliOil_dataout), .oe((((~ eqv_set[0]) & (~ eqv_set[1])) & (~ eqv_set[2])))); io_buf_tri nliOiO ( .datain(1'b0), .dataout(wire_nliOiO_dataout), .oe(((eqv_set[0] & (~ eqv_set[1])) & (~ eqv_set[2])))); io_buf_tri nliOli ( .datain(1'b0), .dataout(wire_nliOli_dataout), .oe((((~ eqv_set[0]) & eqv_set[1]) & (~ eqv_set[2])))); io_buf_tri nliOll ( .datain(1'b0), .dataout(wire_nliOll_dataout), .oe(((eqv_set[0] & eqv_set[1]) & (~ eqv_set[2])))); io_buf_tri nliOlO ( .datain(1'b0), .dataout(wire_nliOlO_dataout), .oe((((~ eqv_set[0]) & (~ eqv_set[1])) & eqv_set[2]))); io_buf_tri nliOOi ( .datain(1'b0), .dataout(wire_nliOOi_dataout), .oe(((eqv_set[0] & (~ eqv_set[1])) & eqv_set[2]))); io_buf_tri nliOOl ( .datain(1'b0), .dataout(wire_nliOOl_dataout), .oe((((~ eqv_set[0]) & eqv_set[1]) & eqv_set[2]))); io_buf_tri nliOOO ( .datain(wire_nl1llO_dataout[0]), .dataout(wire_nliOOO_dataout), .oe(((eqv_set[0] & eqv_set[1]) & eqv_set[2]))); io_buf_tri nll00i ( .datain(wire_nll00l_dataout), .dataout(wire_nll00i_dataout), .oe(1'b1)); io_buf_tri nll00O ( .datain(wire_nll0ii_dataout), .dataout(wire_nll00O_dataout), .oe(1'b1)); io_buf_tri nll0il ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_nll0il_dataout), .oe(wire_nl1lOi_dataout[0])); io_buf_tri nll0iO ( .datain(radce_rstb), .dataout(wire_nll0iO_dataout), .oe((~ wire_nl1lOi_dataout[0]))); io_buf_tri nll0li ( .datain(radce_rstb), .dataout(wire_nll0li_dataout), .oe(wire_nl1lOi_dataout[0])); io_buf_tri nll0ll ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_nll0ll_dataout), .oe((~ wire_nl1lOi_dataout[0]))); io_buf_tri nll10i ( .datain(wire_nll11i_dataout[0]), .dataout(wire_nll10i_dataout), .oe(((~ (radce_adapt | (~ radce_pdb))) | ((radce_adapt & (~ n0l0ii)) & (~ (((~ ((~ n0l0il) & ((~ rseq_sel[0]) & rseq_sel[1]))) & (~ ((((~ n0l0li) | (~ n0l0il)) | (~ n0l0iO)) & (~ n0i0ii)))) & ((~ (rseq_sel[0] & (~ rseq_sel[1]))) | (~ ((~ n0l0il) | (~ n0l0iO)))))))))); io_buf_tri nll11l ( .datain(1'b0), .dataout(wire_nll11l_dataout), .oe((radce_adapt & n0l0ii))); io_buf_tri nll11O ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_nll11O_dataout), .oe(((~ (radce_adapt | radce_pdb)) | ((radce_adapt & (~ n0l0ii)) & ((~ ((~ (rseq_sel[0] & rseq_sel[1])) & ((~ ((~ rseq_sel[0]) & rseq_sel[1])) | (~ (((~ n0l0ll) | (~ n0l0li)) | (~ n0l0iO)))))) | (~ (((~ (rseq_sel[0] & (~ rseq_sel[1]))) | (~ ((~ n0l0ll) | (~ n0l0li)))) & (~ ((~ n0l0ll) & (~ n0i0ii)))))))))); io_buf_tri nlliil ( .datain(wire_nlliiO_dataout), .dataout(wire_nlliil_dataout), .oe(1'b1)); io_buf_tri nllili ( .datain(wire_nllill_dataout), .dataout(wire_nllili_dataout), .oe(1'b1)); io_buf_tri nllilO ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_nllilO_dataout), .oe(wire_nl1lOi_dataout[0])); io_buf_tri nlliOi ( .datain(radce_rstb), .dataout(wire_nlliOi_dataout), .oe((~ wire_nl1lOi_dataout[0]))); io_buf_tri nlliOl ( .datain(radce_rstb), .dataout(wire_nlliOl_dataout), .oe(wire_nl1lOi_dataout[0])); io_buf_tri nlliOO ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_nlliOO_dataout), .oe((~ wire_nl1lOi_dataout[0]))); io_buf_tri nllllO ( .datain(wire_nlllOi_dataout), .dataout(wire_nllllO_dataout), .oe(1'b1)); io_buf_tri nlllOl ( .datain(wire_nlllOO_dataout), .dataout(wire_nlllOl_dataout), .oe(1'b1)); io_buf_tri nllO0i ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_nllO0i_dataout), .oe((~ wire_nl1lOi_dataout[0]))); io_buf_tri nllO1i ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_nllO1i_dataout), .oe(wire_nl1lOi_dataout[0])); io_buf_tri nllO1l ( .datain(radce_rstb), .dataout(wire_nllO1l_dataout), .oe((~ wire_nl1lOi_dataout[0]))); io_buf_tri nllO1O ( .datain(radce_rstb), .dataout(wire_nllO1O_dataout), .oe(wire_nl1lOi_dataout[0])); io_buf_tri nlO00l ( .datain(wire_nlO00O_dataout), .dataout(wire_nlO00l_dataout), .oe(1'b1)); io_buf_tri nlO0ii ( .datain(wire_nlO0il_dataout), .dataout(wire_nlO0ii_dataout), .oe(1'b1)); io_buf_tri nlO0iO ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_nlO0iO_dataout), .oe(radce_vod_int[1])); io_buf_tri nlO0li ( .datain(radce_rstb), .dataout(wire_nlO0li_dataout), .oe((~ radce_vod_int[1]))); io_buf_tri nlO0ll ( .datain(radce_rstb), .dataout(wire_nlO0ll_dataout), .oe(radce_vod_int[1])); io_buf_tri nlO0lO ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_nlO0lO_dataout), .oe((~ radce_vod_int[1]))); io_buf_tri nlO10l ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_nlO10l_dataout), .oe(radce_vod_int[0])); io_buf_tri nlO10O ( .datain(radce_rstb), .dataout(wire_nlO10O_dataout), .oe((~ radce_vod_int[0]))); io_buf_tri nlO11i ( .datain(wire_nlO11l_dataout), .dataout(wire_nlO11i_dataout), .oe(1'b1)); io_buf_tri nlO11O ( .datain(wire_nlO10i_dataout), .dataout(wire_nlO11O_dataout), .oe(1'b1)); io_buf_tri nlO1ii ( .datain(radce_rstb), .dataout(wire_nlO1ii_dataout), .oe(radce_vod_int[0])); io_buf_tri nlO1il ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_nlO1il_dataout), .oe((~ radce_vod_int[0]))); io_buf_tri nlOiiO ( .datain(wire_nlOili_dataout), .dataout(wire_nlOiiO_dataout), .oe(1'b1)); io_buf_tri nlOill ( .datain(wire_nlOilO_dataout), .dataout(wire_nlOill_dataout), .oe(1'b1)); io_buf_tri nlOiOi ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_nlOiOi_dataout), .oe(radce_vod_int[2])); io_buf_tri nlOiOl ( .datain(radce_rstb), .dataout(wire_nlOiOl_dataout), .oe((~ radce_vod_int[2]))); io_buf_tri nlOiOO ( .datain(radce_rstb), .dataout(wire_nlOiOO_dataout), .oe(radce_vod_int[2])); io_buf_tri nlOl1i ( .datain(wire_nl1lOi_dataout[0]), .dataout(wire_nlOl1i_dataout), .oe((~ radce_vod_int[2]))); io_buf_tri nlOlil ( .datain(wire_nlOliO_dataout), .dataout(wire_nlOlil_dataout), .oe(1'b1)); io_buf_tri nlOlli ( .datain(wire_nlOlll_dataout), .dataout(wire_nlOlli_dataout), .oe(1'b1)); io_buf_tri nlOllO ( .datain(wire_nlOlOi_dataout), .dataout(wire_nlOllO_dataout), .oe(1'b1)); io_buf_tri nlOlOl ( .datain(wire_nlOlOO_dataout), .dataout(wire_nlOlOl_dataout), .oe(1'b1)); io_buf_tri nlOO1i ( .datain(wire_nlOO1l_dataout), .dataout(wire_nlOO1i_dataout), .oe(1'b1)); io_buf_tri nlOO1O ( .datain(wire_nlOO0i_dataout), .dataout(wire_nlOO1O_dataout), .oe(1'b1)); assign wire_n010O_dataout = ((~ (n0ilOO & n011O)) === 1'b1) ? n01il : n01li; assign wire_n011l_dataout = ((~ n0ilOO) === 1'b1) ? n011O : n010i; assign wire_n0liiO_dataout = ((~ wire_nl1lOi_dataout[0]) === 1'b1) ? n0lili : n0lill; assign wire_n0liOl_dataout = ((~ n000il) === 1'b1) ? n0liOO : n0ll1i; assign wire_n0ll0i_dataout = ((~ n000iO) === 1'b1) ? n0ll0l : n0ll0O; assign wire_n0lliO_dataout = ((~ (n000iO & n0ll0l)) === 1'b1) ? n0llll : n0llOi; assign wire_n0O00i_dataout = ((~ (n000lO & n0O1OO)) === 1'b1) ? n0O00O : n0O0il; assign wire_n0O10i_dataout = ((~ wire_nl1lOi_dataout[0]) === 1'b1) ? n0O10l : n0O10O; assign wire_n0O1iO_dataout = ((~ n000ll) === 1'b1) ? n0O1li : n0O1ll; assign wire_n0O1Ol_dataout = ((~ n000lO) === 1'b1) ? n0O1OO : n0O01i; assign wire_n0Ol1O_dataout = ((~ wire_nl1lOi_dataout[0]) === 1'b1) ? n0Ol0i : n0Ol0l; assign wire_n0Olil_dataout = ((~ n00i1i) === 1'b1) ? n0OliO : n0Olli; assign wire_n0OlOi_dataout = ((~ n00i1l) === 1'b1) ? n0OlOl : n0OlOO; assign wire_n0OO1O_dataout = ((~ (n00i1l & n0OlOl)) === 1'b1) ? n0OO0l : n0OOii; assign wire_n101i_dataout = ((~ wire_nl1lOi_dataout[0]) === 1'b1) ? n100i : n100l; assign wire_n101O_dataout = ((~ n0il0O) === 1'b1) ? wire_nl1llO_dataout[0] : wire_n11OO_dataout; assign wire_n10ii_dataout = ((~ n100i) === 1'b1) ? n10li : n10ll; assign wire_n10iO_dataout = ((~ n0il0O) === 1'b1) ? wire_nl1llO_dataout[0] : wire_n100O_dataout; assign wire_n10Oi_dataout = ((~ (n100i & n10li)) === 1'b1) ? n1i1l : n1i0i; assign wire_n10OO_dataout = ((~ n0il0O) === 1'b1) ? wire_nl1llO_dataout[0] : wire_n10lO_dataout; assign wire_n1lii_dataout = ((~ n0ilii) === 1'b1) ? (~ n0l0lO) : (~ n1l0l); assign wire_n1liO_dataout = ((~ n0ilii) === 1'b1) ? n0l0lO : n1l0l; assign wire_n1O0l_dataout = ((~ n1O1l) === 1'b1) ? n1O0O : n1Oii; assign wire_n1O1i_dataout = ((~ wire_nl1lOi_dataout[0]) === 1'b1) ? n1O1l : n1O1O; assign wire_n1OiO_dataout = ((~ n0ilOl) === 1'b1) ? n1Oli : n1Oll; assign wire_n1OOi_dataout = ((~ n0iO1i) === 1'b1) ? n1OOl : n1OOO; assign wire_ni00Oi_dataout = (((~ ((~ n00l1O) & (~ n00l1l))) & (~ n00O1l)) === 1'b1) ? ni00ll : ni00iO; assign wire_ni00OO_dataout = (n00O1O === 1'b1) ? (~ wire_nil01l_dataout) : wire_ni00lO_dataout; assign wire_ni01iO_dataout = (((~ ((~ n00iOO) & (~ n00iOl))) & (~ n00O1l)) === 1'b1) ? ni01ii : ni010l; assign wire_ni01ll_dataout = (n00O1O === 1'b1) ? (~ wire_nil01l_dataout) : wire_ni01il_dataout; assign wire_ni0l0i_dataout = (n00O1O === 1'b1) ? wire_niOO0l_dataout : wire_ni0l1i_dataout; assign wire_ni0l1l_dataout = (((~ ((~ n00l0O) & (~ n00l0l))) & (~ n00O1l)) === 1'b1) ? ni0iOO : ni0iOi; assign wire_ni0O0O_dataout = (((~ ((~ n00liO) & (~ n00lil))) & (~ n00O1l)) === 1'b1) ? ni0O0i : ni0O1l; assign wire_ni0Oil_dataout = (n00O1O === 1'b1) ? ((~ n0i10l) & (~ wire_niOl0l_dataout[0])) : wire_ni0O0l_dataout; assign wire_ni101O_dataout = ((~ n00i0i) === 1'b1) ? ni100i : ni100l; assign wire_ni10il_dataout = ((~ n00i0l) === 1'b1) ? ni10iO : ni10li; assign wire_ni10Oi_dataout = ((~ (n00i0l & ni10iO)) === 1'b1) ? ni10OO : ni1i1l; assign wire_ni11Oi_dataout = ((~ wire_nl1lOi_dataout[0]) === 1'b1) ? ni11Ol : ni11OO; assign wire_ni1O0l_dataout = (((~ ((~ n00ilO) & (~ n00ill))) & (~ n00O1l)) === 1'b1) ? ni1O1O : ni1O1i; assign wire_ni1Oii_dataout = (n00O1O === 1'b1) ? (~ wire_nil01l_dataout) : wire_ni1O0i_dataout; assign wire_nii0Ol_dataout = (((~ ((~ n00lOi) & (~ n00llO))) & (~ n00O1l)) === 1'b1) ? nii0lO : nii0li; assign wire_nii1li_dataout = (((~ ((~ (n00liO & ni0O0i)) & (~ (n00lil & ni0O1l)))) & (~ n00O1l)) === 1'b1) ? nii1il : nii10O; assign wire_nii1lO_dataout = (n00O1O === 1'b1) ? ((~ n0i10l) & (~ wire_niOO1O_dataout[0])) : wire_nii1iO_dataout; and(wire_niii1i_dataout, wire_nii0Oi_dataout, ~((~ wire_nl1lOi_dataout[0]))); and(wire_niil0l_dataout, wire_niil1l_dataout, ~((~ wire_nl1lOi_dataout[0]))); assign wire_niil1O_dataout = (((~ ((~ n00O1i) & (~ n00lOO))) & (~ n00O1l)) === 1'b1) ? niil1i : niiiOl; assign wire_niiOii_dataout = (((~ ((~ (n00O1i & niil1i)) & (~ (n00lOO & niiiOl)))) & (~ n00O1l)) === 1'b1) ? niiO0l : niiO1O; and(wire_niiOiO_dataout, wire_niiO0O_dataout, ~((~ wire_nl1lOi_dataout[0]))); assign wire_nil01i_dataout = ((~ nl10OO) === 1'b1) ? wire_nl1llO_dataout[0] : (~ wire_niOO0i_dataout[0]); assign wire_nil01O_dataout = ((~ nl10OO) === 1'b1) ? wire_nl1llO_dataout[0] : wire_nl1lOi_dataout[0]; assign wire_nil10O_dataout = ((~ nl10OO) === 1'b1) ? wire_nl1llO_dataout[0] : wire_nl1lOi_dataout[0]; assign wire_nil1il_dataout = ((~ nl10OO) === 1'b1) ? wire_nl1llO_dataout[0] : wire_nl1lOi_dataout[0]; assign wire_nil1li_dataout = ((~ nl10OO) === 1'b1) ? wire_nil1ll_dataout : (~ wire_niOiil_dataout[0]); assign wire_nil1lO_dataout = (n0l0ii === 1'b1) ? wire_nl1llO_dataout[0] : radce_digital[7]; assign wire_nil1Ol_dataout = ((~ nl10OO) === 1'b1) ? wire_nl1llO_dataout[0] : (~ wire_niOl0O_dataout[0]); assign wire_niOO0O_dataout = (((~ n0i10l) | (~ ((~ ((~ ((~ ((~ n0l0ll) & (~ n0i10i))) & (~ ((~ n0i11O) & (~ n0l0li))))) | (~ ((~ ((~ n0i11l) & (~ n0l0iO))) & (~ ((~ n0l0il) & n0i11i)))))) | (~ nl10OO)))) === 1'b1) ? ((~ n0i10l) & (~ wire_niOiii_dataout[0])) : radce_digital[7]; assign wire_niOOOi_dataout = ((~ wire_nl1lOi_dataout[0]) === 1'b1) ? nl111i : nl111l; assign wire_niOOOO_dataout = ((~ n0i1ll) === 1'b1) ? wire_nl1llO_dataout[0] : wire_niOOlO_dataout; and(wire_nl00OO_dataout, wire_nl1llO_dataout[0], (~ radce_digital[7])); and(wire_nl0Oli_dataout, wire_nl1llO_dataout[0], (~ radce_digital[7])); assign wire_nl110i_dataout = ((~ nl111i) === 1'b1) ? nl11ii : nl11il; assign wire_nl110O_dataout = ((~ n0i1ll) === 1'b1) ? wire_nl1llO_dataout[0] : wire_nl111O_dataout; assign wire_nl11li_dataout = ((~ (nl111i & nl11ii)) === 1'b1) ? nl11Ol : nl101i; assign wire_nl11lO_dataout = ((~ n0i1ll) === 1'b1) ? wire_nl1llO_dataout[0] : wire_nl11iO_dataout; assign wire_nl1i0i_dataout = ((~ n0i1lO) === 1'b1) ? (~ n0li0i) : (~ nl1i1l); assign wire_nl1i0O_dataout = ((~ n0i1lO) === 1'b1) ? n0li0i : nl1i1l; and(wire_nl1O0i_dataout, wire_nl1llO_dataout[0], (~ radce_digital[7])); and(wire_nlii1i_dataout, wire_nl1llO_dataout[0], (~ radce_digital[7])); assign wire_nll00l_dataout = (((~ ((~ n0i0OO) & (~ n0i0Ol))) & (~ n0il1l)) === 1'b1) ? nll01O : nll01i; and(wire_nll0ii_dataout, wire_nll00i_dataout, ~((~ wire_nl1lOi_dataout[0]))); assign wire_nlliiO_dataout = (((~ ((~ n0ii0i) & (~ n0ii1O))) & (~ n0il1l)) === 1'b1) ? nlliii : nlli0l; and(wire_nllill_dataout, wire_nlliil_dataout, ~((~ wire_nl1lOi_dataout[0]))); assign wire_nlllOi_dataout = (((~ ((~ n0iiil) & (~ n0iiii))) & (~ n0il1l)) === 1'b1) ? nlllll : nllliO; and(wire_nlllOO_dataout, wire_nllllO_dataout, ~((~ wire_nl1lOi_dataout[0]))); assign wire_nlO00O_dataout = (((~ ((~ n0il1i) & (~ n0iiOO))) & (~ n0il1l)) === 1'b1) ? nlO00i : nlO01l; and(wire_nlO0il_dataout, wire_nlO00l_dataout, ~((~ wire_nl1lOi_dataout[0]))); and(wire_nlO10i_dataout, wire_nlO11i_dataout, ~((~ wire_nl1lOi_dataout[0]))); assign wire_nlO11l_dataout = (((~ ((~ n0iilO) & (~ n0iill))) & (~ n0il1l)) === 1'b1) ? nllOOO : nllOOi; assign wire_nlOili_dataout = (((~ ((~ (n0il1i & nlO00i)) & (~ (n0iiOO & nlO01l)))) & (~ n0il1l)) === 1'b1) ? nlOiil : nlOi0O; and(wire_nlOilO_dataout, wire_nlOiiO_dataout, ~((~ wire_nl1lOi_dataout[0]))); assign wire_nlOliO_dataout = ((~ n1l1O) === 1'b1) ? wire_nl1llO_dataout[0] : wire_nl1lOi_dataout[0]; assign wire_nlOlll_dataout = ((~ n1l1O) === 1'b1) ? wire_nl1llO_dataout[0] : wire_nl1lOi_dataout[0]; assign wire_nlOlOi_dataout = ((~ n1l1O) === 1'b1) ? radce_vod_lsb : rrgen_set[0]; assign wire_nlOlOO_dataout = ((~ n1l1O) === 1'b1) ? radce_digital[8] : rrgen_set[1]; assign wire_nlOO0i_dataout = ((~ n1l1O) === 1'b1) ? wire_nl1llO_dataout[0] : wire_nl1lOi_dataout[0]; assign wire_nlOO1l_dataout = ((~ n1l1O) === 1'b1) ? radce_digital[9] : rrgen_set[2]; tri_bus n0i1i ( .datain({wire_n00OO_dataout, wire_n00Ol_dataout, wire_n00Oi_dataout, wire_n00lO_dataout, wire_n00ll_dataout, wire_n00li_dataout, wire_n00iO_dataout, wire_n00il_dataout}), .dataout(wire_n0i1i_dataout)); defparam n0i1i.width_datain = 8, n0i1i.width_dataout = 1; tri_bus n0l1O ( .datain({wire_n0l1l_dataout, wire_n0l1i_dataout, wire_n0iOO_dataout, wire_n0iOl_dataout, wire_n0iOi_dataout, wire_n0ilO_dataout, wire_n0ill_dataout, wire_n0ili_dataout}), .dataout(wire_n0l1O_dataout)); defparam n0l1O.width_datain = 8, n0l1O.width_dataout = 1; tri_bus ni001i ( .datain({wire_ni01Oi_dataout, wire_ni01lO_dataout}), .dataout(wire_ni001i_dataout)); defparam ni001i.width_datain = 2, ni001i.width_dataout = 1; tri_bus ni001l ( .datain({wire_ni01OO_dataout, wire_ni01Ol_dataout}), .dataout(wire_ni001l_dataout)); defparam ni001l.width_datain = 2, ni001l.width_dataout = 1; tri_bus ni01l ( .datain({((n0l11O26 ^ n0l11O25) & wire_ni1Ol_dataout), ((n0l10i24 ^ n0l10i23) & wire_ni1Oi_dataout), wire_ni1lO_dataout, ((n0l10l22 ^ n0l10l21) & wire_ni1ll_dataout), wire_ni1li_dataout}), .dataout(wire_ni01l_dataout)); defparam ni01l.width_datain = 5, ni01l.width_dataout = 1; tri_bus ni01O ( .datain({wire_ni01i_dataout, ((n0l10O20 ^ n0l10O19) & wire_ni1OO_dataout), ((n0l1ii18 ^ n0l1ii17) & wire_ni1iO_dataout), wire_ni1il_dataout, wire_ni1ii_dataout}), .dataout(wire_ni01O_dataout)); defparam ni01O.width_datain = 5, ni01O.width_dataout = 1; tri_bus ni0i0l ( .datain({wire_ni0i1l_dataout, wire_ni0i1i_dataout}), .dataout(wire_ni0i0l_dataout)); defparam ni0i0l.width_datain = 2, ni0i0l.width_dataout = 1; tri_bus ni0i0O ( .datain({wire_ni0i0i_dataout, wire_ni0i1O_dataout}), .dataout(wire_ni0i0O_dataout)); defparam ni0i0O.width_datain = 2, ni0i0O.width_dataout = 1; tri_bus ni0liO ( .datain({wire_ni0l0O_dataout, wire_ni0l0l_dataout}), .dataout(wire_ni0liO_dataout)); defparam ni0liO.width_datain = 2, ni0liO.width_dataout = 1; tri_bus ni0ll ( .datain({wire_nll10i_dataout, ((n0l1Ol12 ^ n0l1Ol11) & wire_nll11O_dataout), wire_nll11l_dataout}), .dataout(wire_ni0ll_dataout)); defparam ni0ll.width_datain = 3, ni0ll.width_dataout = 1; tri_bus ni0lli ( .datain({wire_ni0lil_dataout, wire_ni0lii_dataout}), .dataout(wire_ni0lli_dataout)); defparam ni0lli.width_datain = 2, ni0lli.width_dataout = 1; tri_bus ni0lO ( .datain({vctl_quiet}), .dataout(wire_ni0lO_dataout)); defparam ni0lO.width_datain = 1, ni0lO.width_dataout = 1; tri_bus ni0Oi ( .datain({vccehxqyx}), .dataout(wire_ni0Oi_dataout)); defparam ni0Oi.width_datain = 1, ni0Oi.width_dataout = 1; tri_bus ni0Ol ( .datain({((n0l1OO10 ^ n0l1OO9) & outeqp)}), .dataout(wire_ni0Ol_dataout)); defparam ni0Ol.width_datain = 1, ni0Ol.width_dataout = 1; tri_bus ni0OO ( .datain({outeqn}), .dataout(wire_ni0OO_dataout)); defparam ni0OO.width_datain = 1, ni0OO.width_dataout = 1; tri_bus ni0OOi ( .datain({wire_ni0Oli_dataout, wire_ni0OiO_dataout}), .dataout(wire_ni0OOi_dataout)); defparam ni0OOi.width_datain = 2, ni0OOi.width_dataout = 1; tri_bus ni0OOl ( .datain({wire_ni0OlO_dataout, wire_ni0Oll_dataout}), .dataout(wire_ni0OOl_dataout)); defparam ni0OOl.width_datain = 2, ni0OOl.width_dataout = 1; tri_bus ni1OlO ( .datain({wire_ni1OiO_dataout, wire_ni1Oil_dataout}), .dataout(wire_ni1OlO_dataout)); defparam ni1OlO.width_datain = 2, ni1OlO.width_dataout = 1; tri_bus ni1OOi ( .datain({wire_ni1Oll_dataout, wire_ni1Oli_dataout}), .dataout(wire_ni1OOi_dataout)); defparam ni1OOi.width_datain = 2, ni1OOi.width_dataout = 1; tri_bus nii01l ( .datain({wire_nii1Ol_dataout, wire_nii1Oi_dataout}), .dataout(wire_nii01l_dataout)); defparam nii01l.width_datain = 2, nii01l.width_dataout = 1; tri_bus nii01O ( .datain({wire_nii01i_dataout, wire_nii1OO_dataout}), .dataout(wire_nii01O_dataout)); defparam nii01O.width_datain = 2, nii01O.width_dataout = 1; tri_bus nii0i ( .datain({atb_0}), .dataout(wire_nii0i_dataout)); defparam nii0i.width_datain = 1, nii0i.width_dataout = 1; tri_bus nii0l ( .datain({1'b0, atb1}), .dataout(wire_nii0l_dataout)); defparam nii0l.width_datain = 2, nii0l.width_dataout = 1; tri_bus nii0O ( .datain({1'b0, ((n0l00i2 ^ n0l00i1) & atb0)}), .dataout(wire_nii0O_dataout)); defparam nii0O.width_datain = 2, nii0O.width_dataout = 1; tri_bus nii1i ( .datain({((n0l01i8 ^ n0l01i7) & ib50u_t)}), .dataout(wire_nii1i_dataout)); defparam nii1i.width_datain = 1, nii1i.width_dataout = 1; tri_bus nii1l ( .datain({((n0l01l6 ^ n0l01l5) & ib50u_c)}), .dataout(wire_nii1l_dataout)); defparam nii1l.width_datain = 1, nii1l.width_dataout = 1; tri_bus nii1O ( .datain({((n0l01O4 ^ n0l01O3) & atb_1)}), .dataout(wire_nii1O_dataout)); defparam nii1O.width_datain = 1, nii1O.width_dataout = 1; tri_bus niii0O ( .datain({wire_niii1O_dataout, wire_niii1l_dataout}), .dataout(wire_niii0O_dataout)); defparam niii0O.width_datain = 2, niii0O.width_dataout = 1; tri_bus niiiii ( .datain({wire_niii0l_dataout, wire_niii0i_dataout}), .dataout(wire_niiiii_dataout)); defparam niiiii.width_datain = 2, niiiii.width_dataout = 1; tri_bus niilli ( .datain({wire_niilii_dataout, wire_niil0O_dataout}), .dataout(wire_niilli_dataout)); defparam niilli.width_datain = 2, niilli.width_dataout = 1; tri_bus niilll ( .datain({wire_niiliO_dataout, wire_niilil_dataout}), .dataout(wire_niilll_dataout)); defparam niilll.width_datain = 2, niilll.width_dataout = 1; tri_bus niiOOl ( .datain({wire_niiOll_dataout, wire_niiOli_dataout}), .dataout(wire_niiOOl_dataout)); defparam niiOOl.width_datain = 2, niiOOl.width_dataout = 1; tri_bus niiOOO ( .datain({wire_niiOOi_dataout, wire_niiOlO_dataout}), .dataout(wire_niiOOO_dataout)); defparam niiOOO.width_datain = 2, niiOOO.width_dataout = 1; tri_bus niOiii ( .datain({wire_niOi0l_dataout, wire_niOi0i_dataout, wire_niOi1O_dataout, wire_niOi1l_dataout, wire_niOi1i_dataout, wire_niO0OO_dataout}), .dataout(wire_niOiii_dataout)); defparam niOiii.width_datain = 6, niOiii.width_dataout = 1; tri_bus niOiil ( .datain({wire_niOi0O_dataout, wire_niO0Ol_dataout, wire_niO0Oi_dataout, wire_niO0lO_dataout, wire_niO0ll_dataout}), .dataout(wire_niOiil_dataout)); defparam niOiil.width_datain = 5, niOiil.width_dataout = 1; tri_bus niOl0l ( .datain({wire_niOl1O_dataout, wire_niOl1l_dataout, wire_niOl1i_dataout, wire_niOiOO_dataout, wire_niOiOl_dataout, wire_niOiOi_dataout}), .dataout(wire_niOl0l_dataout)); defparam niOl0l.width_datain = 6, niOl0l.width_dataout = 1; tri_bus niOl0O ( .datain({wire_niOl0i_dataout, wire_niOilO_dataout, wire_niOill_dataout, wire_niOili_dataout, wire_niOiiO_dataout}), .dataout(wire_niOl0O_dataout)); defparam niOl0O.width_datain = 5, niOl0O.width_dataout = 1; tri_bus niOO0i ( .datain({wire_niOO1l_dataout, wire_niOlli_dataout, wire_niOliO_dataout, wire_niOlil_dataout, wire_niOlii_dataout}), .dataout(wire_niOO0i_dataout)); defparam niOO0i.width_datain = 5, niOO0i.width_dataout = 1; tri_bus niOO1O ( .datain({wire_niOO1i_dataout, wire_niOlOO_dataout, wire_niOlOl_dataout, wire_niOlOi_dataout, wire_niOllO_dataout, wire_niOlll_dataout}), .dataout(wire_niOO1O_dataout)); defparam niOO1O.width_datain = 6, niOO1O.width_dataout = 1; tri_bus nl00iO ( .datain({wire_nl00il_dataout, wire_nl00ii_dataout, wire_nl000O_dataout, wire_nl000l_dataout, wire_nl000i_dataout, wire_nl001O_dataout, wire_nl001l_dataout, wire_nl001i_dataout}), .dataout(wire_nl00iO_dataout)); defparam nl00iO.width_datain = 8, nl00iO.width_dataout = 1; tri_bus nl0i1i ( .datain({wire_nl00Oi_dataout, wire_nl00lO_dataout, wire_nl00ll_dataout, wire_nl00li_dataout}), .dataout(wire_nl0i1i_dataout)); defparam nl0i1i.width_datain = 4, nl0i1i.width_dataout = 1; tri_bus nl0O0i ( .datain({wire_nl0O1O_dataout, wire_nl0O1l_dataout, wire_nl0O1i_dataout, wire_nl0lOO_dataout, wire_nl0lOl_dataout, wire_nl0lOi_dataout, wire_nl0llO_dataout, wire_nl0lll_dataout}), .dataout(wire_nl0O0i_dataout)); defparam nl0O0i.width_datain = 8, nl0O0i.width_dataout = 1; tri_bus nl0Oll ( .datain({wire_nl0Oil_dataout, wire_nl0Oii_dataout, wire_nl0O0O_dataout, wire_nl0O0l_dataout}), .dataout(wire_nl0Oll_dataout)); defparam nl0Oll.width_datain = 4, nl0Oll.width_dataout = 1; tri_bus nl1lll ( .datain({wire_nl1lli_dataout, wire_nl1liO_dataout, wire_nl1lil_dataout, wire_nl1lii_dataout, wire_nl1l0O_dataout, wire_nl1l0l_dataout, wire_nl1l0i_dataout, wire_nl1l1O_dataout}), .dataout(wire_nl1lll_dataout)); defparam nl1lll.width_datain = 8, nl1lll.width_dataout = 1; tri_bus nl1llO ( .datain({vssexqyx}), .dataout(wire_nl1llO_dataout)); defparam nl1llO.width_datain = 1, nl1llO.width_dataout = 1; tri_bus nl1lOi ( .datain({vccerxqyx}), .dataout(wire_nl1lOi_dataout)); defparam nl1lOi.width_datain = 1, nl1lOi.width_dataout = 1; tri_bus nl1O0l ( .datain({wire_nl1O1l_dataout, wire_nl1O1i_dataout, wire_nl1lOO_dataout, wire_nl1lOl_dataout}), .dataout(wire_nl1O0l_dataout)); defparam nl1O0l.width_datain = 4, nl1O0l.width_dataout = 1; tri_bus nli0li ( .datain({wire_nli0iO_dataout, wire_nli0il_dataout, wire_nli0ii_dataout, wire_nli00O_dataout, wire_nli00l_dataout, wire_nli00i_dataout, wire_nli01O_dataout, wire_nli01l_dataout}), .dataout(wire_nli0li_dataout)); defparam nli0li.width_datain = 8, nli0li.width_dataout = 1; tri_bus nlii1l ( .datain({wire_nli0Ol_dataout, wire_nli0Oi_dataout, wire_nli0lO_dataout, wire_nli0ll_dataout}), .dataout(wire_nlii1l_dataout)); defparam nlii1l.width_datain = 4, nlii1l.width_dataout = 1; tri_bus nll0lO ( .datain({wire_nll0iO_dataout, wire_nll0il_dataout}), .dataout(wire_nll0lO_dataout)); defparam nll0lO.width_datain = 2, nll0lO.width_dataout = 1; tri_bus nll0Oi ( .datain({wire_nll0ll_dataout, wire_nll0li_dataout}), .dataout(wire_nll0Oi_dataout)); defparam nll0Oi.width_datain = 2, nll0Oi.width_dataout = 1; tri_bus nll11i ( .datain({wire_nliOOO_dataout, wire_nliOOl_dataout, wire_nliOOi_dataout, wire_nliOlO_dataout, wire_nliOll_dataout, wire_nliOli_dataout, wire_nliOiO_dataout, wire_nliOil_dataout}), .dataout(wire_nll11i_dataout)); defparam nll11i.width_datain = 8, nll11i.width_dataout = 1; tri_bus nlll1i ( .datain({wire_nlliOi_dataout, wire_nllilO_dataout}), .dataout(wire_nlll1i_dataout)); defparam nlll1i.width_datain = 2, nlll1i.width_dataout = 1; tri_bus nlll1l ( .datain({wire_nlliOO_dataout, wire_nlliOl_dataout}), .dataout(wire_nlll1l_dataout)); defparam nlll1l.width_datain = 2, nlll1l.width_dataout = 1; tri_bus nllO0l ( .datain({wire_nllO1l_dataout, wire_nllO1i_dataout}), .dataout(wire_nllO0l_dataout)); defparam nllO0l.width_datain = 2, nllO0l.width_dataout = 1; tri_bus nllO0O ( .datain({wire_nllO0i_dataout, wire_nllO1O_dataout}), .dataout(wire_nllO0O_dataout)); defparam nllO0O.width_datain = 2, nllO0O.width_dataout = 1; tri_bus nlO0Oi ( .datain({wire_nlO0li_dataout, wire_nlO0iO_dataout}), .dataout(wire_nlO0Oi_dataout)); defparam nlO0Oi.width_datain = 2, nlO0Oi.width_dataout = 1; tri_bus nlO0Ol ( .datain({wire_nlO0lO_dataout, wire_nlO0ll_dataout}), .dataout(wire_nlO0Ol_dataout)); defparam nlO0Ol.width_datain = 2, nlO0Ol.width_dataout = 1; tri_bus nlO1iO ( .datain({wire_nlO10O_dataout, wire_nlO10l_dataout}), .dataout(wire_nlO1iO_dataout)); defparam nlO1iO.width_datain = 2, nlO1iO.width_dataout = 1; tri_bus nlO1li ( .datain({wire_nlO1il_dataout, wire_nlO1ii_dataout}), .dataout(wire_nlO1li_dataout)); defparam nlO1li.width_datain = 2, nlO1li.width_dataout = 1; tri_bus nlOl1l ( .datain({wire_nlOiOl_dataout, wire_nlOiOi_dataout}), .dataout(wire_nlOl1l_dataout)); defparam nlOl1l.width_datain = 2, nlOl1l.width_dataout = 1; tri_bus nlOl1O ( .datain({wire_nlOl1i_dataout, wire_nlOiOO_dataout}), .dataout(wire_nlOl1O_dataout)); defparam nlOl1O.width_datain = 2, nlOl1O.width_dataout = 1; assign adapt_done = n0liii, atb0 = wire_nii0O_dataout[0], atb1 = wire_nii0l_dataout[0], atb_0 = wire_nii0i_dataout[0], atb_1 = wire_nii1O_dataout[0], e_clk = n0li0i, eqa_ctrl = wire_nl1O0l_dataout[0], eqb_ctrl = wire_nl0i1i_dataout[0], eqc_ctrl = wire_nl0Oll_dataout[0], eqctrlout = {nii10O, ni0O1l, ni0iOi, ni00iO, ni010l, ni1O1i}, eqd_ctrl = wire_nlii1l_dataout[0], eqv_ctrl = wire_ni0ll_dataout[0], fine_d2aout = 1'b0, hf_adapt_done = n0li1O, hfclk_macro = wire_n0i1i_dataout[0], hfmac_cnt0_nclr = n0li1l, hfmac_cnt2_nclr = n0li1i, ib50u_c = wire_nii1l_dataout[0], ib50u_t = wire_nii1i_dataout[0], ibrgen1 = 1'b0, ibrgen2 = 1'b0, lf_adapt_done = n0l0OO, lfclk_macro = wire_n0l1O_dataout[0], lfmac_cnt0_nclr = n0l0Ol, lfmac_cnt2_nclr = n0l0Oi, n000il = (n0lili & wire_nl1lOi_dataout[0]), n000iO = (n000il & n0liOO), n000li = ((~ wire_nl1llO_dataout[0]) & wire_n0i1i_dataout[0]), n000ll = (n0O10l & wire_nl1lOi_dataout[0]), n000lO = (n000ll & n0O1li), n000Oi = (n000Ol & (~ n0li1O)), n000Ol = ((~ (radce_hflck[7] | radce_hflck[8])) & (~ (radce_hflck[9] | radce_hflck[10]))), n000OO = ((~ ((~ ((~ ((~ radce_hflck[3]) & n0lili)) & (~ (radce_hflck[3] & (~ n0lili))))) | (~ ((~ ((~ radce_hflck[4]) & n0liOO)) & (~ (radce_hflck[4] & (~ n0liOO))))))) & (~ ((~ ((~ ((~ radce_hflck[5]) & n0ll0l)) & (~ (radce_hflck[5] & (~ n0ll0l))))) | (~ ((~ ((~ radce_hflck[6]) & n0llll)) & (~ (radce_hflck[6] & (~ n0llll)))))))), n00i0i = (ni11Ol & wire_nl1lOi_dataout[0]), n00i0l = (n00i0i & ni100i), n00i0O = (n00iii & (~ n0l0OO)), n00i1i = (n0Ol0i & wire_nl1lOi_dataout[0]), n00i1l = (n00i1i & n0OliO), n00i1O = ((~ wire_nl1llO_dataout[0]) & wire_n0l1O_dataout[0]), n00iii = ((~ (radce_lflck[7] | radce_lflck[8])) & (~ (radce_lflck[9] | radce_lflck[10]))), n00iil = ((~ ((~ ((~ ((~ radce_lflck[3]) & n0Ol0i)) & (~ (radce_lflck[3] & (~ n0Ol0i))))) | (~ ((~ ((~ radce_lflck[4]) & n0OliO)) & (~ (radce_lflck[4] & (~ n0OliO))))))) & (~ ((~ ((~ ((~ radce_lflck[5]) & n0OlOl)) & (~ (radce_lflck[5] & (~ n0OlOl))))) | (~ ((~ ((~ radce_lflck[6]) & n0OO0l)) & (~ (radce_lflck[6] & (~ n0OO0l)))))))), n00iiO = (wire_ni1OOi_dataout[0] & (~ wire_ni1OlO_dataout[0])), n00ili = (wire_ni001l_dataout[0] & (~ wire_ni001i_dataout[0])), n00ill = (radce_adapt & nl10OO), n00ilO = (radce_adapt & (~ nl10OO)), n00iOi = (wire_ni0i0O_dataout[0] & (~ wire_ni0i0l_dataout[0])), n00iOl = (n00ill & ni1O1i), n00iOO = (n00ilO & ni1O1O), n00l0i = (wire_ni0OOl_dataout[0] & (~ wire_ni0OOi_dataout[0])), n00l0l = (n00l1l & ni00iO), n00l0O = (n00l1O & ni00ll), n00l1i = (wire_ni0lli_dataout[0] & (~ wire_ni0liO_dataout[0])), n00l1l = (n00iOl & ni010l), n00l1O = (n00iOO & ni01ii), n00lii = (wire_nii01O_dataout[0] & (~ wire_nii01l_dataout[0])), n00lil = (n00l0l & ni0iOi), n00liO = (n00l0O & ni0iOO), n00lli = (wire_niiiii_dataout[0] & (~ wire_niii0O_dataout[0])), n00lll = (wire_niilll_dataout[0] & (~ wire_niilli_dataout[0])), n00llO = (n0i1Ol & nl10OO), n00lOi = (n0i1Ol & (~ nl10OO)), n00lOl = (wire_niiOOO_dataout[0] & (~ wire_niiOOl_dataout[0])), n00lOO = (n00llO & nii0li), n00O0i = ((~ n0l0ll) & (~ nl10OO)), n00O0l = ((~ n00OiO) & nl10OO), n00O0O = (((~ nii0li) | niiiOl) | niiO1O), n00O1i = (n00lOi & nii0lO), n00O1l = (n0i1OO & (~ ((~ n00O0l) & (~ n00O0i)))), n00O1O = ((n0i1OO & (~ n00O0l)) & (~ n00O0i)), n00Oii = ((nii0li | (~ niiiOl)) | niiO1O), n00Oil = (((~ nii0li) | (~ niiiOl)) | niiO1O), n00OiO = ((nii0li | niiiOl) | (~ niiO1O)), n00Oli = (((~ ((n0l0ii & (~ n0i10i)) & (~ nl10OO))) & (~ ((n0i10i & (~ n0l0li)) & (~ nl10OO)))) & (~ ((~ n0l0ll) & (~ nl10OO)))), n00Oll = ((~ ((n0l0ii & (~ n0i11O)) & (~ nl10OO))) & (~ ((n0i11O & (~ n0l0iO)) & (~ nl10OO)))), n00OlO = ((~ ((~ (((~ rseq_sel[0]) & rseq_sel[1]) & n0l0ii)) & (~ (n0i11l & (~ n0l0il))))) & (~ nl10OO)), n00OOi = ((n0l0ii & n0i11i) & (~ nl10OO)), n00OOl = ((~ (n00Oll & n00Oli)) | (~ (((~ n00OOi) & n00OOO) & (~ n00OlO)))), n00OOO = (((~ (((~ n0i11l) & (~ n0l0il)) & (~ nl10OO))) & (~ (((~ n0i11O) & (~ n0l0iO)) & (~ nl10OO)))) & (~ (((~ n0i10i) & (~ n0l0li)) & (~ nl10OO)))), n0i00i = (radce_adapt | radce_pdb), n0i00l = (rseq_sel[0] & rseq_sel[1]), n0i00O = (radce_adapt | radce_pdb), n0i01i = (radce_adapt | radce_pdb), n0i01l = (rseq_sel[0] | rseq_sel[1]), n0i01O = (radce_adapt | radce_pdb), n0i0ii = (rseq_sel[0] | rseq_sel[1]), n0i0li = (wire_nll0Oi_dataout[0] & (~ wire_nll0lO_dataout[0])), n0i0Oi = (wire_nlll1l_dataout[0] & (~ wire_nlll1i_dataout[0])), n0i0Ol = (radce_adapt & n1l1O), n0i0OO = (radce_adapt & (~ n1l1O)), n0i10i = (rseq_sel[0] | rseq_sel[1]), n0i10l = (radce_rstb & nl10OO), n0i11i = (rseq_sel[0] & rseq_sel[1]), n0i11l = (rseq_sel[0] | (~ rseq_sel[1])), n0i11O = ((~ rseq_sel[0]) | rseq_sel[1]), n0i1ll = (((~ ((~ ((~ rhyst_hf[0]) & nl111i)) & (~ (rhyst_hf[0] & (~ nl111i))))) | (~ ((~ ((~ rhyst_hf[1]) & nl11ii)) & (~ (rhyst_hf[1] & (~ nl11ii)))))) | (~ ((~ ((~ rhyst_hf[2]) & nl11Ol)) & (~ (rhyst_hf[2] & (~ nl11Ol)))))), n0i1lO = ((rhyst_hf[0] | rhyst_hf[1]) | rhyst_hf[2]), n0i1Oi = (radce_adapt & radce_rstb), n0i1Ol = (radce_adapt & n0i1OO), n0i1OO = (((~ ((~ ((~ (ni0iOi & (~ wire_nil1iO_dataout))) & (~ ((~ ni0iOi) & wire_nil1iO_dataout)))) | wire_nl1llO_dataout[0])) & (~ ((~ ((~ (ni0O1l & (~ wire_nil1Oi_dataout))) & (~ ((~ ni0O1l) & wire_nil1Oi_dataout)))) | (~ ((~ (nii10O & (~ wire_nil1OO_dataout))) & (~ ((~ nii10O) & wire_nil1OO_dataout))))))) & ((~ ((~ ((~ (ni00iO & (~ wire_nil1ii_dataout))) & (~ ((~ ni00iO) & wire_nil1ii_dataout)))) | wire_nl1llO_dataout[0])) & (~ ((~ ((~ (ni1O1i & (~ wire_nil01l_dataout))) & (~ ((~ ni1O1i) & wire_nil01l_dataout)))) | (~ ((~ (ni010l & (~ wire_nil10l_dataout))) & (~ ((~ ni010l) & wire_nil10l_dataout)))))))), n0ii0i = (n0i0OO & nll01O), n0ii0O = (wire_nlO1li_dataout[0] & (~ wire_nlO1iO_dataout[0])), n0ii1l = (wire_nllO0O_dataout[0] & (~ wire_nllO0l_dataout[0])), n0ii1O = (n0i0Ol & nll01i), n0iiii = (n0ii1O & nlli0l), n0iiil = (n0ii0i & nlliii), n0iili = (wire_nlO0Ol_dataout[0] & (~ wire_nlO0Oi_dataout[0])), n0iill = (n0iiii & nllliO), n0iilO = (n0iiil & nlllll), n0iiOl = (wire_nlOl1O_dataout[0] & (~ wire_nlOl1l_dataout[0])), n0iiOO = (n0iill & nllOOi), n0il0O = (((~ ((~ ((~ rhyst_lf[0]) & n100i)) & (~ (rhyst_lf[0] & (~ n100i))))) | (~ ((~ ((~ rhyst_lf[1]) & n10li)) & (~ (rhyst_lf[1] & (~ n10li)))))) | (~ ((~ ((~ rhyst_lf[2]) & n1i1l)) & (~ (rhyst_lf[2] & (~ n1i1l)))))), n0il1i = (n0iilO & nllOOO), n0il1l = (((~ (wire_nl1llO_dataout[0] | (~ ((~ (nllOOi & (~ wire_nlOllO_dataout))) & (~ ((~ nllOOi) & wire_nlOllO_dataout)))))) & (~ ((~ ((~ (nlO01l & (~ wire_nlOlOl_dataout))) & (~ ((~ nlO01l) & wire_nlOlOl_dataout)))) | (~ ((~ (nlOi0O & (~ wire_nlOO1i_dataout))) & (~ ((~ nlOi0O) & wire_nlOO1i_dataout))))))) & ((~ (wire_nl1llO_dataout[0] | (~ ((~ (nllliO & (~ wire_nlOlli_dataout))) & (~ ((~ nllliO) & wire_nlOlli_dataout)))))) & (~ ((~ ((~ (nll01i & (~ wire_nlOO1O_dataout))) & (~ ((~ nll01i) & wire_nlOO1O_dataout)))) | (~ ((~ (nlli0l & (~ wire_nlOlil_dataout))) & (~ ((~ nlli0l) & wire_nlOlil_dataout)))))))), n0ilii = ((rhyst_lf[0] | rhyst_lf[1]) | rhyst_lf[2]), n0ilil = (radce_adapt & radce_rstb), n0illl = 1'b1, n0ilOl = (n1O1l & n1O0O), n0ilOO = (n0iO1i & n1OOl), n0iO0i = ((~ (rclkdiv[0] & (~ rclkdiv[1]))) | (~ (rclkdiv[2] & (~ rclkdiv[3])))), n0iO0l = ((~ (rclkdiv[0] & rclkdiv[1])) | (~ ((~ rclkdiv[2]) & (~ rclkdiv[3])))), n0iO1i = (n0ilOl & n1Oli), n0iO1O = ((~ ((~ rclkdiv[2]) & (~ rclkdiv[3]))) | (~ (rclkdiv[0] & (~ rclkdiv[1])))), n0iOil = ((~ (rclkdiv[2] & (~ rclkdiv[3]))) | (~ ((~ rclkdiv[0]) & (~ rclkdiv[1])))), n0iOli = ((~ ((~ rclkdiv[0]) & (~ rclkdiv[1]))) | (~ ((~ rclkdiv[2]) & (~ rclkdiv[3])))), n0iOOl = ((~ ((~ rclkdiv[2]) & (~ rclkdiv[3]))) | (~ ((~ rclkdiv[0]) & rclkdiv[1]))), n0iOOO = ((~ (rclkdiv[2] & (~ rclkdiv[3]))) | (~ ((~ rclkdiv[0]) & rclkdiv[1]))), n0l00l = (((((radce_digital[2] & radce_digital[3]) & rhf_os[0]) & rhf_os[1]) & rhf_os[2]) & rhf_os[3]), n0l00O = (((((radce_digital[4] & radce_digital[5]) & rlf_os[0]) & rlf_os[1]) & rlf_os[2]) & rlf_os[3]), n0l0ii = ((~ ((~ ((rseq_sel[0] & rseq_sel[1]) & (~ n00OiO))) & (~ ((~ n00Oil) & (~ n0i11l))))) | (~ ((~ ((~ n00Oii) & (~ n0i11O))) & (~ ((~ n00O0O) & (~ n0i10i)))))), n0l0il = ((~ ((~ n00Oil) & n0i11i)) & (~ ((~ n00OiO) & (~ n0i11i)))), n0l0iO = ((~ ((~ rseq_sel[1]) & (~ n00Oil))) & (~ (rseq_sel[1] & (~ n00Oii)))), n0l0li = ((~ ((~ n00O0O) & n0i10i)) & (~ ((~ n00Oii) & (~ n0i10i)))), n0l0ll = ((nii0li | niiiOl) | niiO1O), n0l0lO = ((n0l1Oi & wire_ni01l_dataout[0]) & (n0l1iO16 ^ n0l1iO15)), n0l0Oi = (radce_rstb & (~ (n00iil & (~ ni1l0l)))), n0l0Ol = (radce_rstb & ni1lii), n0l0OO = ((~ ((~ ((~ ((~ radce_lflck[11]) & ni11Ol)) & (~ (radce_lflck[11] & (~ ni11Ol))))) | (~ ((~ ((~ radce_lflck[12]) & ni100i)) & (~ (radce_lflck[12] & (~ ni100i))))))) & (~ ((~ ((~ ((~ radce_lflck[13]) & ni10iO)) & (~ (radce_lflck[13] & (~ ni10iO))))) | (~ ((~ ((~ radce_lflck[14]) & ni10OO)) & (~ (radce_lflck[14] & (~ ni10OO)))))))), n0l11i = ((~ (rclkdiv[2] & (~ rclkdiv[3]))) | (~ (rclkdiv[0] & rclkdiv[1]))), n0l1il = (fixed_clk & n1lOl), n0l1Oi = (radce_adapt & wire_nl1lOi_dataout[0]), n0li0i = ((n0l1Oi & wire_ni01O_dataout[0]) & (n0l1ll14 ^ n0l1ll13)), n0li1i = (radce_rstb & (~ (n000OO & (~ n0Oill)))), n0li1l = (radce_rstb & n0OiOi), n0li1O = ((~ ((~ ((~ ((~ radce_hflck[11]) & n0O10l)) & (~ (radce_hflck[11] & (~ n0O10l))))) | (~ ((~ ((~ radce_hflck[12]) & n0O1li)) & (~ (radce_hflck[12] & (~ n0O1li))))))) & (~ ((~ ((~ ((~ radce_hflck[13]) & n0O1OO)) & (~ (radce_hflck[13] & (~ n0O1OO))))) | (~ ((~ ((~ radce_hflck[14]) & n0O00O)) & (~ (radce_hflck[14] & (~ n0O00O)))))))), n0liii = ((lock_lf_ovd | ((~ lock_lf_ovd) & n0l0OO)) & n0li1O), outeqn = wire_ni0OO_dataout[0], outeqp = wire_ni0Ol_dataout[0], r_clk = n0l0lO, rgenctrlout = {nlOi0O, nlO01l, nllOOi, nllliO, nlli0l, nll01i}, tmxselan = n0l0ll, tmxselbn = n0l0li, tmxselcn = n0l0iO, tmxseldn = n0l0il, tmxselvn = (~ n0l0ii), updnn_hf = n0l00O, updnn_lf = (~ n0l00l), vccehxqyx = wire_ni0Oi_dataout[0], vccerxqyx = wire_nl1lOi_dataout[0], vctl_quiet = wire_ni0lO_dataout[0], vssexqyx = wire_nl1llO_dataout[0]; endmodule //stratixiv_hssi_pma_c_adce //synopsys translate_on //VALID FILE // disable it for now as tx_pma model has problem with it `ifdef MODEL_TECH `mti_v2k_int_delays_off `endif