File | Description |
---|
ddr_sdram_0.vhd | A MegaCore® function variation file, which defines a VHDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software. |
ddr_sdram_0.cmp | A VHDL component declaration for the MegaCore function variation. Add the contents of this file to any VHDL architecture that instantiates the MegaCore function. |
ddr_sdram_0_auk_ddr_dqs_group.vhd | Design file containing the datapath byte groups. |
ddr_sdram_0_auk_ddr_clk_gen.vhd | Design file containing the clock output generators. |
ddr_sdram_0_auk_ddr_datapath.vhd | Design file that instantiates the byte groups and the clock output generators. |
ddr_sdram_0_auk_ddr_sdram.vhd | Design file that instantiates the controller logic and the datapath. |
ddr_sdram_0_auk_ddr_dll.vhd | Design file containing the Stratix or Stratix II DLL. |
ddr_sdram_0_debug_design.vhd | Example top-level design file. |
testbench | ddr_sdram_0_debug_design_tb.vhd | Testbench for the example top level design file. |
add_constraints_for_ddr_sdram_0.tcl | DDR constraints script. |
verify_timing_for_ddr_sdram_0.tcl | Post-compilation timing analysis script. |
constraints_out.txt | Log file that IP Toolbench creates while generating the add constraints script. |
ddr_sdram_0_ddr_settings.txt | Critical settings file that stores the custom variation’s parameters. IP Toolbench uses this file to generate the add constraints script. The verify timing script and the DDR Timing Wizard also read this file. |
ddr_sdram_0_pre_compile_ddr_timing_summary.txt | Log file that stores the results of the precompilation system timing analysis. |
ddr_sdram_0.qip | Contains Quartus II project information for your MegaCore function variation. |
ddr_sdram_0.html | The MegaCore function report file. |